CPUM-armv8.cpp@ 107044

Last change on this file since 107044 was 107032, checked in by vboxsync, 8 days ago
VMM/CPUM-armv8: Allow reading/writing the debug control/value registers through CPUMQueryGuestSysReg/CPUMSetGuestSysReg, bugreef:10393 [windows build fix]
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1	/* $Id: CPUM-armv8.cpp 107032 2024-11-18 15:13:53Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager (ARMv8 variant).
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	/** @page pg_cpum CPUM - CPU Monitor / Manager
29	*
30	* The CPU Monitor / Manager keeps track of all the CPU registers.
31	* This is the ARMv8 variant which is doing much less than its x86/AMD6464
32	* counterpart due to the fact that we currently only support the NEM backends
33	* for running ARM guests. It might become complex iff we decide to implement our
34	* own hypervisor.
35	*
36	* @section sec_cpum_logging_armv8 Logging Level Assignments.
37	*
38	* Following log level assignments:
39	* - @todo
40	*
41	*/
42
43
44	/*********************************************************************************************************************************
45	* Header Files *
46	*********************************************************************************************************************************/
47	#define LOG_GROUP LOG_GROUP_CPUM
48	#define CPUM_WITH_NONCONST_HOST_FEATURES
49	#include <VBox/vmm/cpum.h>
50	#include <VBox/vmm/cpumdis.h>
51	#include <VBox/vmm/pgm.h>
52	#include <VBox/vmm/mm.h>
53	#include <VBox/vmm/em.h>
54	#include <VBox/vmm/iem.h>
55	#include <VBox/vmm/dbgf.h>
56	#include <VBox/vmm/ssm.h>
57	#include "CPUMInternal-armv8.h"
58	#include <VBox/vmm/vm.h>
59
60	#include <VBox/param.h>
61	#include <VBox/dis.h>
62	#include <VBox/err.h>
63	#include <VBox/log.h>
64	#include <iprt/assert.h>
65	#include <iprt/cpuset.h>
66	#include <iprt/mem.h>
67	#include <iprt/mp.h>
68	#include <iprt/string.h>
69	#include <iprt/armv8.h>
70
71
72	/*********************************************************************************************************************************
73	* Defined Constants And Macros *
74	*********************************************************************************************************************************/
75
76	/** Internal form used by the macros. */
77	#ifdef VBOX_WITH_STATISTICS
78	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
79	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
80	{ 0 }, { 0 }, { 0 }, { 0 } }
81	#else
82	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
83	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
84	#endif
85
86	/** Function handlers, extended version. */
87	#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
88	RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_##a_enmRdFnSuff, kCpumSysRegWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
89	/** Function handlers, read-only. */
90	#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
91	RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_##a_enmRdFnSuff, kCpumSysRegWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
92	/** Read-only fixed value, ignores all writes. */
93	#define MVI(a_uMsr, a_szName, a_uValue) \
94	RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_FixedValue, kCpumSysRegWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
95	/** Read/Write value from/to CPUMCTX. */
96	#define MVRW(a_uMsr, a_szName, a_offCpum) \
97	RINT(a_uMsr, a_uMsr, kCpumSysRegRdFn_ReadCpumOff, kCpumSysRegWrFn_WriteCpumOff, (uint32_t)a_offCpum, 0, UINT64_MAX, 0, a_szName)
98
99
100	/*********************************************************************************************************************************
101	* Structures and Typedefs *
102	*********************************************************************************************************************************/
103
104	/**
105	* What kind of cpu info dump to perform.
106	*/
107	typedef enum CPUMDUMPTYPE
108	{
109	CPUMDUMPTYPE_TERSE,
110	CPUMDUMPTYPE_DEFAULT,
111	CPUMDUMPTYPE_VERBOSE
112	} CPUMDUMPTYPE;
113	/** Pointer to a cpu info dump type. */
114	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
115
116
117	/*********************************************************************************************************************************
118	* Internal Functions *
119	*********************************************************************************************************************************/
120	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
121	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
122	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
123	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
124	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
125	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
126	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
127	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
128
129
130	/*********************************************************************************************************************************
131	* Global Variables *
132	*********************************************************************************************************************************/
133	#if defined(RT_ARCH_ARM64)
134	/** Host CPU features. */
135	DECL_HIDDEN_DATA(CPUHOSTFEATURES) g_CpumHostFeatures;
136	#endif
137
138	/**
139	* System register ranges.
140	*/
141	static CPUMSYSREGRANGE const g_aSysRegRanges[] =
142	{
143	MFX(ARMV8_AARCH64_SYSREG_OSLAR_EL1, "OSLAR_EL1", WriteOnly, OslarEl1, 0, UINT64_C(0xfffffffffffffffe), UINT64_C(0xfffffffffffffffe)),
144	MFO(ARMV8_AARCH64_SYSREG_OSLSR_EL1, "OSLSR_EL1", OslsrEl1),
145	MVI(ARMV8_AARCH64_SYSREG_OSDLR_EL1, "OSDLR_EL1", 0),
146	MVRW(ARMV8_AARCH64_SYSREG_MDSCR_EL1, "MDSCR_EL1", RT_UOFFSETOF(CPUMCTX, Mdscr)),
147	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(0), "DBGBVR0_EL1", RT_UOFFSETOF(CPUMCTX, aBp[0].Value)),
148	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(1), "DBGBVR1_EL1", RT_UOFFSETOF(CPUMCTX, aBp[1].Value)),
149	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(2), "DBGBVR2_EL1", RT_UOFFSETOF(CPUMCTX, aBp[2].Value)),
150	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(3), "DBGBVR3_EL1", RT_UOFFSETOF(CPUMCTX, aBp[3].Value)),
151	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(4), "DBGBVR4_EL1", RT_UOFFSETOF(CPUMCTX, aBp[4].Value)),
152	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(5), "DBGBVR5_EL1", RT_UOFFSETOF(CPUMCTX, aBp[5].Value)),
153	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(6), "DBGBVR6_EL1", RT_UOFFSETOF(CPUMCTX, aBp[6].Value)),
154	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(7), "DBGBVR7_EL1", RT_UOFFSETOF(CPUMCTX, aBp[7].Value)),
155	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(8), "DBGBVR8_EL1", RT_UOFFSETOF(CPUMCTX, aBp[8].Value)),
156	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(9), "DBGBVR9_EL9", RT_UOFFSETOF(CPUMCTX, aBp[9].Value)),
157	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(10), "DBGBVR10_EL1", RT_UOFFSETOF(CPUMCTX, aBp[10].Value)),
158	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(11), "DBGBVR11_EL1", RT_UOFFSETOF(CPUMCTX, aBp[11].Value)),
159	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(12), "DBGBVR12_EL1", RT_UOFFSETOF(CPUMCTX, aBp[12].Value)),
160	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(13), "DBGBVR13_EL1", RT_UOFFSETOF(CPUMCTX, aBp[13].Value)),
161	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(14), "DBGBVR14_EL1", RT_UOFFSETOF(CPUMCTX, aBp[14].Value)),
162	MVRW(ARMV8_AARCH64_SYSREG_DBGBVRn_EL1(15), "DBGBVR15_EL1", RT_UOFFSETOF(CPUMCTX, aBp[15].Value)),
163	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(0), "DBGBCR0_EL1", RT_UOFFSETOF(CPUMCTX, aBp[0].Ctrl)),
164	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(1), "DBGBCR1_EL1", RT_UOFFSETOF(CPUMCTX, aBp[1].Ctrl)),
165	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(2), "DBGBCR2_EL1", RT_UOFFSETOF(CPUMCTX, aBp[2].Ctrl)),
166	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(3), "DBGBCR3_EL1", RT_UOFFSETOF(CPUMCTX, aBp[3].Ctrl)),
167	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(4), "DBGBCR4_EL1", RT_UOFFSETOF(CPUMCTX, aBp[4].Ctrl)),
168	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(5), "DBGBCR5_EL1", RT_UOFFSETOF(CPUMCTX, aBp[5].Ctrl)),
169	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(6), "DBGBCR6_EL1", RT_UOFFSETOF(CPUMCTX, aBp[6].Ctrl)),
170	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(7), "DBGBCR7_EL1", RT_UOFFSETOF(CPUMCTX, aBp[7].Ctrl)),
171	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(8), "DBGBCR8_EL1", RT_UOFFSETOF(CPUMCTX, aBp[8].Ctrl)),
172	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(9), "DBGBCR9_EL9", RT_UOFFSETOF(CPUMCTX, aBp[9].Ctrl)),
173	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(10), "DBGBCR10_EL1", RT_UOFFSETOF(CPUMCTX, aBp[10].Ctrl)),
174	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(11), "DBGBCR11_EL1", RT_UOFFSETOF(CPUMCTX, aBp[11].Ctrl)),
175	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(12), "DBGBCR12_EL1", RT_UOFFSETOF(CPUMCTX, aBp[12].Ctrl)),
176	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(13), "DBGBCR13_EL1", RT_UOFFSETOF(CPUMCTX, aBp[13].Ctrl)),
177	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(14), "DBGBCR14_EL1", RT_UOFFSETOF(CPUMCTX, aBp[14].Ctrl)),
178	MVRW(ARMV8_AARCH64_SYSREG_DBGBCRn_EL1(15), "DBGBCR15_EL1", RT_UOFFSETOF(CPUMCTX, aBp[15].Ctrl)),
179	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(0), "DBGWVR0_EL1", RT_UOFFSETOF(CPUMCTX, aWp[0].Value)),
180	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(1), "DBGWVR1_EL1", RT_UOFFSETOF(CPUMCTX, aWp[1].Value)),
181	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(2), "DBGWVR2_EL1", RT_UOFFSETOF(CPUMCTX, aWp[2].Value)),
182	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(3), "DBGWVR3_EL1", RT_UOFFSETOF(CPUMCTX, aWp[3].Value)),
183	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(4), "DBGWVR4_EL1", RT_UOFFSETOF(CPUMCTX, aWp[4].Value)),
184	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(5), "DBGWVR5_EL1", RT_UOFFSETOF(CPUMCTX, aWp[5].Value)),
185	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(6), "DBGWVR6_EL1", RT_UOFFSETOF(CPUMCTX, aWp[6].Value)),
186	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(7), "DBGWVR7_EL1", RT_UOFFSETOF(CPUMCTX, aWp[7].Value)),
187	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(8), "DBGWVR8_EL1", RT_UOFFSETOF(CPUMCTX, aWp[8].Value)),
188	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(9), "DBGWVR9_EL9", RT_UOFFSETOF(CPUMCTX, aWp[9].Value)),
189	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(10), "DBGWVR10_EL1", RT_UOFFSETOF(CPUMCTX, aWp[10].Value)),
190	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(11), "DBGWVR11_EL1", RT_UOFFSETOF(CPUMCTX, aWp[11].Value)),
191	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(12), "DBGWVR12_EL1", RT_UOFFSETOF(CPUMCTX, aWp[12].Value)),
192	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(13), "DBGWVR13_EL1", RT_UOFFSETOF(CPUMCTX, aWp[13].Value)),
193	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(14), "DBGWVR14_EL1", RT_UOFFSETOF(CPUMCTX, aWp[14].Value)),
194	MVRW(ARMV8_AARCH64_SYSREG_DBGWVRn_EL1(15), "DBGWVR15_EL1", RT_UOFFSETOF(CPUMCTX, aWp[15].Value)),
195	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(0), "DBGWCR0_EL1", RT_UOFFSETOF(CPUMCTX, aWp[0].Ctrl)),
196	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(1), "DBGWCR1_EL1", RT_UOFFSETOF(CPUMCTX, aWp[1].Ctrl)),
197	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(2), "DBGWCR2_EL1", RT_UOFFSETOF(CPUMCTX, aWp[2].Ctrl)),
198	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(3), "DBGWCR3_EL1", RT_UOFFSETOF(CPUMCTX, aWp[3].Ctrl)),
199	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(4), "DBGWCR4_EL1", RT_UOFFSETOF(CPUMCTX, aWp[4].Ctrl)),
200	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(5), "DBGWCR5_EL1", RT_UOFFSETOF(CPUMCTX, aWp[5].Ctrl)),
201	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(6), "DBGWCR6_EL1", RT_UOFFSETOF(CPUMCTX, aWp[6].Ctrl)),
202	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(7), "DBGWCR7_EL1", RT_UOFFSETOF(CPUMCTX, aWp[7].Ctrl)),
203	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(8), "DBGWCR8_EL1", RT_UOFFSETOF(CPUMCTX, aWp[8].Ctrl)),
204	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(9), "DBGWCR9_EL9", RT_UOFFSETOF(CPUMCTX, aWp[9].Ctrl)),
205	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(10), "DBGWCR10_EL1", RT_UOFFSETOF(CPUMCTX, aWp[10].Ctrl)),
206	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(11), "DBGWCR11_EL1", RT_UOFFSETOF(CPUMCTX, aWp[11].Ctrl)),
207	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(12), "DBGWCR12_EL1", RT_UOFFSETOF(CPUMCTX, aWp[12].Ctrl)),
208	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(13), "DBGWCR13_EL1", RT_UOFFSETOF(CPUMCTX, aWp[13].Ctrl)),
209	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(14), "DBGWCR14_EL1", RT_UOFFSETOF(CPUMCTX, aWp[14].Ctrl)),
210	MVRW(ARMV8_AARCH64_SYSREG_DBGWCRn_EL1(15), "DBGWCR15_EL1", RT_UOFFSETOF(CPUMCTX, aWp[15].Ctrl)),
211	};
212
213
214	/** Saved state field descriptors for CPUMCTX. */
215	static const SSMFIELD g_aCpumCtxFields[] =
216	{
217	SSMFIELD_ENTRY( CPUMCTX, aGRegs[0].x),
218	SSMFIELD_ENTRY( CPUMCTX, aGRegs[1].x),
219	SSMFIELD_ENTRY( CPUMCTX, aGRegs[2].x),
220	SSMFIELD_ENTRY( CPUMCTX, aGRegs[3].x),
221	SSMFIELD_ENTRY( CPUMCTX, aGRegs[4].x),
222	SSMFIELD_ENTRY( CPUMCTX, aGRegs[5].x),
223	SSMFIELD_ENTRY( CPUMCTX, aGRegs[6].x),
224	SSMFIELD_ENTRY( CPUMCTX, aGRegs[7].x),
225	SSMFIELD_ENTRY( CPUMCTX, aGRegs[8].x),
226	SSMFIELD_ENTRY( CPUMCTX, aGRegs[9].x),
227	SSMFIELD_ENTRY( CPUMCTX, aGRegs[10].x),
228	SSMFIELD_ENTRY( CPUMCTX, aGRegs[11].x),
229	SSMFIELD_ENTRY( CPUMCTX, aGRegs[12].x),
230	SSMFIELD_ENTRY( CPUMCTX, aGRegs[13].x),
231	SSMFIELD_ENTRY( CPUMCTX, aGRegs[14].x),
232	SSMFIELD_ENTRY( CPUMCTX, aGRegs[15].x),
233	SSMFIELD_ENTRY( CPUMCTX, aGRegs[16].x),
234	SSMFIELD_ENTRY( CPUMCTX, aGRegs[17].x),
235	SSMFIELD_ENTRY( CPUMCTX, aGRegs[18].x),
236	SSMFIELD_ENTRY( CPUMCTX, aGRegs[19].x),
237	SSMFIELD_ENTRY( CPUMCTX, aGRegs[20].x),
238	SSMFIELD_ENTRY( CPUMCTX, aGRegs[21].x),
239	SSMFIELD_ENTRY( CPUMCTX, aGRegs[22].x),
240	SSMFIELD_ENTRY( CPUMCTX, aGRegs[23].x),
241	SSMFIELD_ENTRY( CPUMCTX, aGRegs[24].x),
242	SSMFIELD_ENTRY( CPUMCTX, aGRegs[25].x),
243	SSMFIELD_ENTRY( CPUMCTX, aGRegs[26].x),
244	SSMFIELD_ENTRY( CPUMCTX, aGRegs[27].x),
245	SSMFIELD_ENTRY( CPUMCTX, aGRegs[28].x),
246	SSMFIELD_ENTRY( CPUMCTX, aGRegs[29].x),
247	SSMFIELD_ENTRY( CPUMCTX, aGRegs[30].x),
248	SSMFIELD_ENTRY( CPUMCTX, aVRegs[0].v),
249	SSMFIELD_ENTRY( CPUMCTX, aVRegs[1].v),
250	SSMFIELD_ENTRY( CPUMCTX, aVRegs[2].v),
251	SSMFIELD_ENTRY( CPUMCTX, aVRegs[3].v),
252	SSMFIELD_ENTRY( CPUMCTX, aVRegs[4].v),
253	SSMFIELD_ENTRY( CPUMCTX, aVRegs[5].v),
254	SSMFIELD_ENTRY( CPUMCTX, aVRegs[6].v),
255	SSMFIELD_ENTRY( CPUMCTX, aVRegs[7].v),
256	SSMFIELD_ENTRY( CPUMCTX, aVRegs[8].v),
257	SSMFIELD_ENTRY( CPUMCTX, aVRegs[9].v),
258	SSMFIELD_ENTRY( CPUMCTX, aVRegs[10].v),
259	SSMFIELD_ENTRY( CPUMCTX, aVRegs[11].v),
260	SSMFIELD_ENTRY( CPUMCTX, aVRegs[12].v),
261	SSMFIELD_ENTRY( CPUMCTX, aVRegs[13].v),
262	SSMFIELD_ENTRY( CPUMCTX, aVRegs[14].v),
263	SSMFIELD_ENTRY( CPUMCTX, aVRegs[15].v),
264	SSMFIELD_ENTRY( CPUMCTX, aVRegs[16].v),
265	SSMFIELD_ENTRY( CPUMCTX, aVRegs[17].v),
266	SSMFIELD_ENTRY( CPUMCTX, aVRegs[18].v),
267	SSMFIELD_ENTRY( CPUMCTX, aVRegs[19].v),
268	SSMFIELD_ENTRY( CPUMCTX, aVRegs[20].v),
269	SSMFIELD_ENTRY( CPUMCTX, aVRegs[21].v),
270	SSMFIELD_ENTRY( CPUMCTX, aVRegs[22].v),
271	SSMFIELD_ENTRY( CPUMCTX, aVRegs[23].v),
272	SSMFIELD_ENTRY( CPUMCTX, aVRegs[24].v),
273	SSMFIELD_ENTRY( CPUMCTX, aVRegs[25].v),
274	SSMFIELD_ENTRY( CPUMCTX, aVRegs[26].v),
275	SSMFIELD_ENTRY( CPUMCTX, aVRegs[27].v),
276	SSMFIELD_ENTRY( CPUMCTX, aVRegs[28].v),
277	SSMFIELD_ENTRY( CPUMCTX, aVRegs[29].v),
278	SSMFIELD_ENTRY( CPUMCTX, aVRegs[30].v),
279	SSMFIELD_ENTRY( CPUMCTX, aVRegs[31].v),
280	SSMFIELD_ENTRY( CPUMCTX, aSpReg[0].u64),
281	SSMFIELD_ENTRY( CPUMCTX, aSpReg[1].u64),
282	SSMFIELD_ENTRY( CPUMCTX, Pc.u64),
283	SSMFIELD_ENTRY( CPUMCTX, Spsr.u64),
284	SSMFIELD_ENTRY( CPUMCTX, Elr.u64),
285	SSMFIELD_ENTRY( CPUMCTX, Sctlr.u64),
286	SSMFIELD_ENTRY( CPUMCTX, Tcr.u64),
287	SSMFIELD_ENTRY( CPUMCTX, Ttbr0.u64),
288	SSMFIELD_ENTRY( CPUMCTX, Ttbr1.u64),
289	SSMFIELD_ENTRY( CPUMCTX, VBar.u64),
290	SSMFIELD_ENTRY( CPUMCTX, aBp[0].Ctrl.u64),
291	SSMFIELD_ENTRY( CPUMCTX, aBp[0].Value.u64),
292	SSMFIELD_ENTRY( CPUMCTX, aBp[1].Ctrl.u64),
293	SSMFIELD_ENTRY( CPUMCTX, aBp[1].Value.u64),
294	SSMFIELD_ENTRY( CPUMCTX, aBp[2].Ctrl.u64),
295	SSMFIELD_ENTRY( CPUMCTX, aBp[2].Value.u64),
296	SSMFIELD_ENTRY( CPUMCTX, aBp[3].Ctrl.u64),
297	SSMFIELD_ENTRY( CPUMCTX, aBp[3].Value.u64),
298	SSMFIELD_ENTRY( CPUMCTX, aBp[4].Ctrl.u64),
299	SSMFIELD_ENTRY( CPUMCTX, aBp[4].Value.u64),
300	SSMFIELD_ENTRY( CPUMCTX, aBp[5].Ctrl.u64),
301	SSMFIELD_ENTRY( CPUMCTX, aBp[5].Value.u64),
302	SSMFIELD_ENTRY( CPUMCTX, aBp[6].Ctrl.u64),
303	SSMFIELD_ENTRY( CPUMCTX, aBp[6].Value.u64),
304	SSMFIELD_ENTRY( CPUMCTX, aBp[7].Ctrl.u64),
305	SSMFIELD_ENTRY( CPUMCTX, aBp[7].Value.u64),
306	SSMFIELD_ENTRY( CPUMCTX, aBp[8].Ctrl.u64),
307	SSMFIELD_ENTRY( CPUMCTX, aBp[8].Value.u64),
308	SSMFIELD_ENTRY( CPUMCTX, aBp[9].Ctrl.u64),
309	SSMFIELD_ENTRY( CPUMCTX, aBp[9].Value.u64),
310	SSMFIELD_ENTRY( CPUMCTX, aBp[10].Ctrl.u64),
311	SSMFIELD_ENTRY( CPUMCTX, aBp[10].Value.u64),
312	SSMFIELD_ENTRY( CPUMCTX, aBp[11].Ctrl.u64),
313	SSMFIELD_ENTRY( CPUMCTX, aBp[11].Value.u64),
314	SSMFIELD_ENTRY( CPUMCTX, aBp[12].Ctrl.u64),
315	SSMFIELD_ENTRY( CPUMCTX, aBp[12].Value.u64),
316	SSMFIELD_ENTRY( CPUMCTX, aBp[13].Ctrl.u64),
317	SSMFIELD_ENTRY( CPUMCTX, aBp[13].Value.u64),
318	SSMFIELD_ENTRY( CPUMCTX, aBp[14].Ctrl.u64),
319	SSMFIELD_ENTRY( CPUMCTX, aBp[14].Value.u64),
320	SSMFIELD_ENTRY( CPUMCTX, aBp[15].Ctrl.u64),
321	SSMFIELD_ENTRY( CPUMCTX, aBp[15].Value.u64),
322	SSMFIELD_ENTRY( CPUMCTX, aWp[0].Ctrl.u64),
323	SSMFIELD_ENTRY( CPUMCTX, aWp[0].Value.u64),
324	SSMFIELD_ENTRY( CPUMCTX, aWp[1].Ctrl.u64),
325	SSMFIELD_ENTRY( CPUMCTX, aWp[1].Value.u64),
326	SSMFIELD_ENTRY( CPUMCTX, aWp[2].Ctrl.u64),
327	SSMFIELD_ENTRY( CPUMCTX, aWp[2].Value.u64),
328	SSMFIELD_ENTRY( CPUMCTX, aWp[3].Ctrl.u64),
329	SSMFIELD_ENTRY( CPUMCTX, aWp[3].Value.u64),
330	SSMFIELD_ENTRY( CPUMCTX, aWp[4].Ctrl.u64),
331	SSMFIELD_ENTRY( CPUMCTX, aWp[4].Value.u64),
332	SSMFIELD_ENTRY( CPUMCTX, aWp[5].Ctrl.u64),
333	SSMFIELD_ENTRY( CPUMCTX, aWp[5].Value.u64),
334	SSMFIELD_ENTRY( CPUMCTX, aWp[6].Ctrl.u64),
335	SSMFIELD_ENTRY( CPUMCTX, aWp[6].Value.u64),
336	SSMFIELD_ENTRY( CPUMCTX, aWp[7].Ctrl.u64),
337	SSMFIELD_ENTRY( CPUMCTX, aWp[7].Value.u64),
338	SSMFIELD_ENTRY( CPUMCTX, aWp[8].Ctrl.u64),
339	SSMFIELD_ENTRY( CPUMCTX, aWp[8].Value.u64),
340	SSMFIELD_ENTRY( CPUMCTX, aWp[9].Ctrl.u64),
341	SSMFIELD_ENTRY( CPUMCTX, aWp[9].Value.u64),
342	SSMFIELD_ENTRY( CPUMCTX, aWp[10].Ctrl.u64),
343	SSMFIELD_ENTRY( CPUMCTX, aWp[10].Value.u64),
344	SSMFIELD_ENTRY( CPUMCTX, aWp[11].Ctrl.u64),
345	SSMFIELD_ENTRY( CPUMCTX, aWp[11].Value.u64),
346	SSMFIELD_ENTRY( CPUMCTX, aWp[12].Ctrl.u64),
347	SSMFIELD_ENTRY( CPUMCTX, aWp[12].Value.u64),
348	SSMFIELD_ENTRY( CPUMCTX, aWp[13].Ctrl.u64),
349	SSMFIELD_ENTRY( CPUMCTX, aWp[13].Value.u64),
350	SSMFIELD_ENTRY( CPUMCTX, aWp[14].Ctrl.u64),
351	SSMFIELD_ENTRY( CPUMCTX, aWp[14].Value.u64),
352	SSMFIELD_ENTRY( CPUMCTX, aWp[15].Ctrl.u64),
353	SSMFIELD_ENTRY( CPUMCTX, aWp[15].Value.u64),
354	SSMFIELD_ENTRY( CPUMCTX, Mdscr.u64),
355	SSMFIELD_ENTRY( CPUMCTX, Apda.Low.u64),
356	SSMFIELD_ENTRY( CPUMCTX, Apda.High.u64),
357	SSMFIELD_ENTRY( CPUMCTX, Apdb.Low.u64),
358	SSMFIELD_ENTRY( CPUMCTX, Apdb.High.u64),
359	SSMFIELD_ENTRY( CPUMCTX, Apga.Low.u64),
360	SSMFIELD_ENTRY( CPUMCTX, Apga.High.u64),
361	SSMFIELD_ENTRY( CPUMCTX, Apia.Low.u64),
362	SSMFIELD_ENTRY( CPUMCTX, Apia.High.u64),
363	SSMFIELD_ENTRY( CPUMCTX, Apib.Low.u64),
364	SSMFIELD_ENTRY( CPUMCTX, Apib.High.u64),
365	SSMFIELD_ENTRY( CPUMCTX, Afsr0.u64),
366	SSMFIELD_ENTRY( CPUMCTX, Afsr1.u64),
367	SSMFIELD_ENTRY( CPUMCTX, Amair.u64),
368	SSMFIELD_ENTRY( CPUMCTX, CntKCtl.u64),
369	SSMFIELD_ENTRY( CPUMCTX, ContextIdr.u64),
370	SSMFIELD_ENTRY( CPUMCTX, Cpacr.u64),
371	SSMFIELD_ENTRY( CPUMCTX, Csselr.u64),
372	SSMFIELD_ENTRY( CPUMCTX, Esr.u64),
373	SSMFIELD_ENTRY( CPUMCTX, Far.u64),
374	SSMFIELD_ENTRY( CPUMCTX, Mair.u64),
375	SSMFIELD_ENTRY( CPUMCTX, Par.u64),
376	SSMFIELD_ENTRY( CPUMCTX, TpIdrRoEl0.u64),
377	SSMFIELD_ENTRY( CPUMCTX, aTpIdr[0].u64),
378	SSMFIELD_ENTRY( CPUMCTX, aTpIdr[1].u64),
379	SSMFIELD_ENTRY( CPUMCTX, MDccInt.u64),
380	SSMFIELD_ENTRY( CPUMCTX, fpcr),
381	SSMFIELD_ENTRY( CPUMCTX, fpsr),
382	SSMFIELD_ENTRY( CPUMCTX, fPState),
383	SSMFIELD_ENTRY( CPUMCTX, fOsLck),
384	SSMFIELD_ENTRY( CPUMCTX, CntvCtlEl0),
385	SSMFIELD_ENTRY( CPUMCTX, CntvCValEl0),
386	/** @name EL2 support:
387	* @{ */
388	SSMFIELD_ENTRY( CPUMCTX, CntHCtlEl2),
389	SSMFIELD_ENTRY( CPUMCTX, CntHpCtlEl2),
390	SSMFIELD_ENTRY( CPUMCTX, CntHpCValEl2),
391	SSMFIELD_ENTRY( CPUMCTX, CntHpTValEl2),
392	SSMFIELD_ENTRY( CPUMCTX, CntVOffEl2),
393	SSMFIELD_ENTRY( CPUMCTX, CptrEl2),
394	SSMFIELD_ENTRY( CPUMCTX, ElrEl2),
395	SSMFIELD_ENTRY( CPUMCTX, EsrEl2),
396	SSMFIELD_ENTRY( CPUMCTX, FarEl2),
397	SSMFIELD_ENTRY( CPUMCTX, HcrEl2),
398	SSMFIELD_ENTRY( CPUMCTX, HpFarEl2),
399	SSMFIELD_ENTRY( CPUMCTX, MairEl2),
400	SSMFIELD_ENTRY( CPUMCTX, MdcrEl2),
401	SSMFIELD_ENTRY( CPUMCTX, SctlrEl2),
402	SSMFIELD_ENTRY( CPUMCTX, SpsrEl2),
403	SSMFIELD_ENTRY( CPUMCTX, SpEl2),
404	SSMFIELD_ENTRY( CPUMCTX, TcrEl2),
405	SSMFIELD_ENTRY( CPUMCTX, TpidrEl2),
406	SSMFIELD_ENTRY( CPUMCTX, Ttbr0El2),
407	SSMFIELD_ENTRY( CPUMCTX, Ttbr1El2),
408	SSMFIELD_ENTRY( CPUMCTX, VBarEl2),
409	SSMFIELD_ENTRY( CPUMCTX, VMpidrEl2),
410	SSMFIELD_ENTRY( CPUMCTX, VPidrEl2),
411	SSMFIELD_ENTRY( CPUMCTX, VTcrEl2),
412	SSMFIELD_ENTRY( CPUMCTX, VTtbrEl2),
413	/** @} */
414
415	SSMFIELD_ENTRY_TERM()
416	};
417
418
419	/**
420	* Initializes the guest system register states.
421	*
422	* @returns VBox status code.
423	* @param pVM The cross context VM structure.
424	*/
425	static int cpumR3InitSysRegs(PVM pVM)
426	{
427	for (uint32_t i = 0; i < RT_ELEMENTS(g_aSysRegRanges); i++)
428	{
429	int rc = CPUMR3SysRegRangesInsert(pVM, &g_aSysRegRanges[i]);
430	AssertLogRelRCReturn(rc, rc);
431	}
432
433	return VINF_SUCCESS;
434	}
435
436
437	/**
438	* Initializes the CPUM.
439	*
440	* @returns VBox status code.
441	* @param pVM The cross context VM structure.
442	*/
443	VMMR3DECL(int) CPUMR3Init(PVM pVM)
444	{
445	LogFlow(("CPUMR3Init\n"));
446
447	/*
448	* Assert alignment, sizes and tables.
449	*/
450	AssertCompileMemberAlignment(VM, cpum.s, 32);
451	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
452	AssertCompileSizeAlignment(CPUMCTX, 64);
453	AssertCompileMemberAlignment(VM, cpum, 64);
454	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
455	#ifdef VBOX_STRICT
456	int rc2 = cpumR3SysRegStrictInitChecks();
457	AssertRCReturn(rc2, rc2);
458	#endif
459
460	pVM->cpum.s.GuestInfo.paSysRegRangesR3 = &pVM->cpum.s.GuestInfo.aSysRegRanges[0];
461	pVM->cpum.s.bResetEl = ARMV8_AARCH64_EL_1;
462
463	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
464
465	/** @cfgm{/CPUM/ResetPcValue, string}
466	* Program counter value after a reset, sets the address of the first instruction to execute. */
467	int rc = CFGMR3QueryU64Def(pCpumCfg, "ResetPcValue", &pVM->cpum.s.u64ResetPc, 0);
468	AssertLogRelRCReturn(rc, rc);
469
470	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
471	* Whether to expose the hardware virtualization (EL2) feature to the guest.
472	* The default is false, and when enabled requires a 64-bit CPU and a NEM backend
473	* supporting it.
474	*/
475	bool fNestedHWVirt = false;
476	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &fNestedHWVirt, false);
477	AssertLogRelRCReturn(rc, rc);
478	if (fNestedHWVirt)
479	pVM->cpum.s.bResetEl = ARMV8_AARCH64_EL_2;
480
481	/*
482	* Register saved state data item.
483	*/
484	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
485	NULL, cpumR3LiveExec, NULL,
486	NULL, cpumR3SaveExec, NULL,
487	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
488	if (RT_FAILURE(rc))
489	return rc;
490
491	/*
492	* Register info handlers and registers with the debugger facility.
493	*/
494	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
495	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
496	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
497	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
498	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
499	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
500	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid information.",
501	&cpumR3CpuIdInfo);
502	DBGFR3InfoRegisterInternal( pVM, "cpufeat", "Displays the guest features.",
503	&cpumR3CpuFeatInfo);
504
505	rc = cpumR3DbgInit(pVM);
506	if (RT_FAILURE(rc))
507	return rc;
508
509	/*
510	* Initialize the Guest system register states.
511	*/
512	rc = cpumR3InitSysRegs(pVM);
513	if (RT_FAILURE(rc))
514	return rc;
515
516	/*
517	* Initialize the general guest CPU state.
518	*/
519	CPUMR3Reset(pVM);
520
521	return VINF_SUCCESS;
522	}
523
524
525	/**
526	* Applies relocations to data and code managed by this
527	* component. This function will be called at init and
528	* whenever the VMM need to relocate it self inside the GC.
529	*
530	* The CPUM will update the addresses used by the switcher.
531	*
532	* @param pVM The cross context VM structure.
533	*/
534	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
535	{
536	RT_NOREF(pVM);
537	}
538
539
540	/**
541	* Terminates the CPUM.
542	*
543	* Termination means cleaning up and freeing all resources,
544	* the VM it self is at this point powered off or suspended.
545	*
546	* @returns VBox status code.
547	* @param pVM The cross context VM structure.
548	*/
549	VMMR3DECL(int) CPUMR3Term(PVM pVM)
550	{
551	RT_NOREF(pVM);
552	return VINF_SUCCESS;
553	}
554
555
556	/**
557	* Resets a virtual CPU.
558	*
559	* Used by CPUMR3Reset and CPU hot plugging.
560	*
561	* @param pVM The cross context VM structure.
562	* @param pVCpu The cross context virtual CPU structure of the CPU that is
563	* being reset. This may differ from the current EMT.
564	*/
565	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
566	{
567	RT_NOREF(pVM);
568
569	/** @todo anything different for VCPU > 0? */
570	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
571
572	/*
573	* Initialize everything to ZERO first.
574	*/
575	RT_BZERO(pCtx, sizeof(*pCtx));
576
577	/* Start in Supervisor mode. */
578	/** @todo Differentiate between Aarch64 and Aarch32 configuation. */
579	pCtx->fPState = ARMV8_SPSR_EL2_AARCH64_SET_EL(pVM->cpum.s.bResetEl)
580	\| ARMV8_SPSR_EL2_AARCH64_SP
581	\| ARMV8_SPSR_EL2_AARCH64_D
582	\| ARMV8_SPSR_EL2_AARCH64_A
583	\| ARMV8_SPSR_EL2_AARCH64_I
584	\| ARMV8_SPSR_EL2_AARCH64_F;
585
586	pCtx->Pc.u64 = pVM->cpum.s.u64ResetPc;
587	/** @todo */
588	}
589
590
591	/**
592	* Resets the CPU.
593	*
594	* @param pVM The cross context VM structure.
595	*/
596	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
597	{
598	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
599	{
600	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
601	CPUMR3ResetCpu(pVM, pVCpu);
602	}
603	}
604
605
606
607
608	/**
609	* Pass 0 live exec callback.
610	*
611	* @returns VINF_SSM_DONT_CALL_AGAIN.
612	* @param pVM The cross context VM structure.
613	* @param pSSM The saved state handle.
614	* @param uPass The pass (0).
615	*/
616	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
617	{
618	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
619	cpumR3SaveCpuId(pVM, pSSM);
620	return VINF_SSM_DONT_CALL_AGAIN;
621	}
622
623
624	/**
625	* Execute state save operation.
626	*
627	* @returns VBox status code.
628	* @param pVM The cross context VM structure.
629	* @param pSSM SSM operation handle.
630	*/
631	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
632	{
633	/*
634	* Save.
635	*/
636	SSMR3PutU32(pSSM, pVM->cCpus);
637	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
638	{
639	PVMCPU const pVCpu = pVM->apCpusR3[idCpu];
640	PCPUMCTX const pGstCtx = &pVCpu->cpum.s.Guest;
641
642	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
643
644	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
645	}
646
647	cpumR3SaveCpuId(pVM, pSSM);
648	return VINF_SUCCESS;
649	}
650
651
652	/**
653	* @callback_method_impl{FNSSMINTLOADPREP}
654	*/
655	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
656	{
657	RT_NOREF(pSSM);
658	pVM->cpum.s.fPendingRestore = true;
659	return VINF_SUCCESS;
660	}
661
662
663	/**
664	* @callback_method_impl{FNSSMINTLOADEXEC}
665	*/
666	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
667	{
668	/*
669	* Validate version.
670	*/
671	if (uVersion != CPUM_SAVED_STATE_VERSION)
672	{
673	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
674	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
675	}
676
677	if (uPass == SSM_PASS_FINAL)
678	{
679	uint32_t cCpus;
680	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
681	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
682	VERR_SSM_UNEXPECTED_DATA);
683
684	/*
685	* Do the per-CPU restoring.
686	*/
687	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
688	{
689	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
690	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
691
692	/*
693	* Restore the CPUMCTX structure.
694	*/
695	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
696	AssertRCReturn(rc, rc);
697
698	/*
699	* Restore a couple of flags.
700	*/
701	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
702	}
703	}
704
705	pVM->cpum.s.fPendingRestore = false;
706
707	/* Load CPUID and explode guest features. */
708	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
709	}
710
711
712	/**
713	* @callback_method_impl{FNSSMINTLOADDONE}
714	*/
715	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
716	{
717	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
718	return VINF_SUCCESS;
719
720	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
721	if (pVM->cpum.s.fPendingRestore)
722	{
723	LogRel(("CPUM: Missing state!\n"));
724	return VERR_INTERNAL_ERROR_2;
725	}
726
727	/** @todo */
728	return VINF_SUCCESS;
729	}
730
731
732	/**
733	* Checks if the CPUM state restore is still pending.
734	*
735	* @returns true / false.
736	* @param pVM The cross context VM structure.
737	*/
738	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
739	{
740	return pVM->cpum.s.fPendingRestore;
741	}
742
743
744	/**
745	* Formats the PSTATE value into mnemonics.
746	*
747	* @param pszPState Where to write the mnemonics. (Assumes sufficient buffer space.)
748	* @param fPState The PSTATE value with both guest hardware and VBox
749	* internal bits included.
750	*/
751	static void cpumR3InfoFormatPState(char *pszPState, uint32_t fPState)
752	{
753	/*
754	* Format the flags.
755	*/
756	static const struct
757	{
758	const char pszSet; const char pszClear; uint32_t fFlag;
759	} s_aFlags[] =
760	{
761	{ "SP", "nSP", ARMV8_SPSR_EL2_AARCH64_SP },
762	{ "M4", "nM4", ARMV8_SPSR_EL2_AARCH64_M4 },
763	{ "T", "nT", ARMV8_SPSR_EL2_AARCH64_T },
764	{ "nF", "F", ARMV8_SPSR_EL2_AARCH64_F },
765	{ "nI", "I", ARMV8_SPSR_EL2_AARCH64_I },
766	{ "nA", "A", ARMV8_SPSR_EL2_AARCH64_A },
767	{ "nD", "D", ARMV8_SPSR_EL2_AARCH64_D },
768	{ "V", "nV", ARMV8_SPSR_EL2_AARCH64_V },
769	{ "C", "nC", ARMV8_SPSR_EL2_AARCH64_C },
770	{ "Z", "nZ", ARMV8_SPSR_EL2_AARCH64_Z },
771	{ "N", "nN", ARMV8_SPSR_EL2_AARCH64_N },
772	};
773	char *psz = pszPState;
774	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
775	{
776	const char *pszAdd = s_aFlags[i].fFlag & fPState ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
777	if (pszAdd)
778	{
779	strcpy(psz, pszAdd);
780	psz += strlen(pszAdd);
781	*psz++ = ' ';
782	}
783	}
784	psz[-1] = '\0';
785	}
786
787
788	/**
789	* Formats a full register dump.
790	*
791	* @param pVM The cross context VM structure.
792	* @param pCtx The context to format.
793	* @param pHlp Output functions.
794	* @param enmType The dump type.
795	*/
796	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType)
797	{
798	RT_NOREF(pVM);
799
800	/*
801	* Format the PSTATE.
802	*/
803	char szPState[80];
804	cpumR3InfoFormatPState(&szPState[0], pCtx->fPState);
805
806	/*
807	* Format the registers.
808	*/
809	switch (enmType)
810	{
811	case CPUMDUMPTYPE_TERSE:
812	if (CPUMIsGuestIn64BitCodeEx(pCtx))
813	pHlp->pfnPrintf(pHlp,
814	"x0=%016RX64 x1=%016RX64 x2=%016RX64 x3=%016RX64\n"
815	"x4=%016RX64 x5=%016RX64 x6=%016RX64 x7=%016RX64\n"
816	"x8=%016RX64 x9=%016RX64 x10=%016RX64 x11=%016RX64\n"
817	"x12=%016RX64 x13=%016RX64 x14=%016RX64 x15=%016RX64\n"
818	"x16=%016RX64 x17=%016RX64 x18=%016RX64 x19=%016RX64\n"
819	"x20=%016RX64 x21=%016RX64 x22=%016RX64 x23=%016RX64\n"
820	"x24=%016RX64 x25=%016RX64 x26=%016RX64 x27=%016RX64\n"
821	"x28=%016RX64 x29=%016RX64 x30=%016RX64\n"
822	"pc=%016RX64 pstate=%016RX64 %s\n"
823	"sp_el0=%016RX64 sp_el1=%016RX64\n",
824	pCtx->aGRegs[0], pCtx->aGRegs[1], pCtx->aGRegs[2], pCtx->aGRegs[3],
825	pCtx->aGRegs[4], pCtx->aGRegs[5], pCtx->aGRegs[6], pCtx->aGRegs[7],
826	pCtx->aGRegs[8], pCtx->aGRegs[9], pCtx->aGRegs[10], pCtx->aGRegs[11],
827	pCtx->aGRegs[12], pCtx->aGRegs[13], pCtx->aGRegs[14], pCtx->aGRegs[15],
828	pCtx->aGRegs[16], pCtx->aGRegs[17], pCtx->aGRegs[18], pCtx->aGRegs[19],
829	pCtx->aGRegs[20], pCtx->aGRegs[21], pCtx->aGRegs[22], pCtx->aGRegs[23],
830	pCtx->aGRegs[24], pCtx->aGRegs[25], pCtx->aGRegs[26], pCtx->aGRegs[27],
831	pCtx->aGRegs[28], pCtx->aGRegs[29], pCtx->aGRegs[30],
832	pCtx->Pc.u64, pCtx->fPState, szPState,
833	pCtx->aSpReg[0].u64, pCtx->aSpReg[1].u64);
834	else
835	AssertFailed();
836	break;
837
838	case CPUMDUMPTYPE_DEFAULT:
839	if (CPUMIsGuestIn64BitCodeEx(pCtx))
840	pHlp->pfnPrintf(pHlp,
841	"x0=%016RX64 x1=%016RX64 x2=%016RX64 x3=%016RX64\n"
842	"x4=%016RX64 x5=%016RX64 x6=%016RX64 x7=%016RX64\n"
843	"x8=%016RX64 x9=%016RX64 x10=%016RX64 x11=%016RX64\n"
844	"x12=%016RX64 x13=%016RX64 x14=%016RX64 x15=%016RX64\n"
845	"x16=%016RX64 x17=%016RX64 x18=%016RX64 x19=%016RX64\n"
846	"x20=%016RX64 x21=%016RX64 x22=%016RX64 x23=%016RX64\n"
847	"x24=%016RX64 x25=%016RX64 x26=%016RX64 x27=%016RX64\n"
848	"x28=%016RX64 x29=%016RX64 x30=%016RX64\n"
849	"pc=%016RX64 pstate=%016RX64 %s\n"
850	"sp_el0=%016RX64 sp_el1=%016RX64 sctlr_el1=%016RX64\n"
851	"tcr_el1=%016RX64 ttbr0_el1=%016RX64 ttbr1_el1=%016RX64\n"
852	"vbar_el1=%016RX64 elr_el1=%016RX64 esr_el1=%016RX64\n",
853	pCtx->aGRegs[0], pCtx->aGRegs[1], pCtx->aGRegs[2], pCtx->aGRegs[3],
854	pCtx->aGRegs[4], pCtx->aGRegs[5], pCtx->aGRegs[6], pCtx->aGRegs[7],
855	pCtx->aGRegs[8], pCtx->aGRegs[9], pCtx->aGRegs[10], pCtx->aGRegs[11],
856	pCtx->aGRegs[12], pCtx->aGRegs[13], pCtx->aGRegs[14], pCtx->aGRegs[15],
857	pCtx->aGRegs[16], pCtx->aGRegs[17], pCtx->aGRegs[18], pCtx->aGRegs[19],
858	pCtx->aGRegs[20], pCtx->aGRegs[21], pCtx->aGRegs[22], pCtx->aGRegs[23],
859	pCtx->aGRegs[24], pCtx->aGRegs[25], pCtx->aGRegs[26], pCtx->aGRegs[27],
860	pCtx->aGRegs[28], pCtx->aGRegs[29], pCtx->aGRegs[30],
861	pCtx->Pc.u64, pCtx->fPState, szPState,
862	pCtx->aSpReg[0].u64, pCtx->aSpReg[1].u64, pCtx->Sctlr.u64,
863	pCtx->Tcr.u64, pCtx->Ttbr0.u64, pCtx->Ttbr1.u64,
864	pCtx->VBar.u64, pCtx->Elr.u64, pCtx->Esr.u64);
865	else
866	AssertFailed();
867	break;
868
869	case CPUMDUMPTYPE_VERBOSE:
870	if (CPUMIsGuestIn64BitCodeEx(pCtx))
871	pHlp->pfnPrintf(pHlp,
872	"x0=%016RX64 x1=%016RX64 x2=%016RX64 x3=%016RX64\n"
873	"x4=%016RX64 x5=%016RX64 x6=%016RX64 x7=%016RX64\n"
874	"x8=%016RX64 x9=%016RX64 x10=%016RX64 x11=%016RX64\n"
875	"x12=%016RX64 x13=%016RX64 x14=%016RX64 x15=%016RX64\n"
876	"x16=%016RX64 x17=%016RX64 x18=%016RX64 x19=%016RX64\n"
877	"x20=%016RX64 x21=%016RX64 x22=%016RX64 x23=%016RX64\n"
878	"x24=%016RX64 x25=%016RX64 x26=%016RX64 x27=%016RX64\n"
879	"x28=%016RX64 x29=%016RX64 x30=%016RX64\n"
880	"pc=%016RX64 pstate=%016RX64 %s\n"
881	"sp_el0=%016RX64 sp_el1=%016RX64 sctlr_el1=%016RX64\n"
882	"tcr_el1=%016RX64 ttbr0_el1=%016RX64 ttbr1_el1=%016RX64\n"
883	"vbar_el1=%016RX64 elr_el1=%016RX64 esr_el1=%016RX64\n"
884	"contextidr_el1=%016RX64 tpidrr0_el0=%016RX64\n"
885	"tpidr_el0=%016RX64 tpidr_el1=%016RX64\n"
886	"far_el1=%016RX64 mair_el1=%016RX64 par_el1=%016RX64\n"
887	"cntv_ctl_el0=%016RX64 cntv_val_el0=%016RX64\n"
888	"afsr0_el1=%016RX64 afsr0_el1=%016RX64 amair_el1=%016RX64\n"
889	"cntkctl_el1=%016RX64 cpacr_el1=%016RX64 csselr_el1=%016RX64\n"
890	"mdccint_el1=%016RX64\n",
891	pCtx->aGRegs[0], pCtx->aGRegs[1], pCtx->aGRegs[2], pCtx->aGRegs[3],
892	pCtx->aGRegs[4], pCtx->aGRegs[5], pCtx->aGRegs[6], pCtx->aGRegs[7],
893	pCtx->aGRegs[8], pCtx->aGRegs[9], pCtx->aGRegs[10], pCtx->aGRegs[11],
894	pCtx->aGRegs[12], pCtx->aGRegs[13], pCtx->aGRegs[14], pCtx->aGRegs[15],
895	pCtx->aGRegs[16], pCtx->aGRegs[17], pCtx->aGRegs[18], pCtx->aGRegs[19],
896	pCtx->aGRegs[20], pCtx->aGRegs[21], pCtx->aGRegs[22], pCtx->aGRegs[23],
897	pCtx->aGRegs[24], pCtx->aGRegs[25], pCtx->aGRegs[26], pCtx->aGRegs[27],
898	pCtx->aGRegs[28], pCtx->aGRegs[29], pCtx->aGRegs[30],
899	pCtx->Pc.u64, pCtx->fPState, szPState,
900	pCtx->aSpReg[0].u64, pCtx->aSpReg[1].u64, pCtx->Sctlr.u64,
901	pCtx->Tcr.u64, pCtx->Ttbr0.u64, pCtx->Ttbr1.u64,
902	pCtx->VBar.u64, pCtx->Elr.u64, pCtx->Esr.u64,
903	pCtx->ContextIdr.u64, pCtx->TpIdrRoEl0.u64,
904	pCtx->aTpIdr[0].u64, pCtx->aTpIdr[1].u64,
905	pCtx->Far.u64, pCtx->Mair.u64, pCtx->Par.u64,
906	pCtx->CntvCtlEl0, pCtx->CntvCValEl0,
907	pCtx->Afsr0.u64, pCtx->Afsr1.u64, pCtx->Amair.u64,
908	pCtx->CntKCtl.u64, pCtx->Cpacr.u64, pCtx->Csselr.u64,
909	pCtx->MDccInt.u64);
910	else
911	AssertFailed();
912
913	pHlp->pfnPrintf(pHlp, "fpcr=%016RX64 fpsr=%016RX64\n", pCtx->fpcr, pCtx->fpsr);
914	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aVRegs); i++)
915	pHlp->pfnPrintf(pHlp,
916	i & 1
917	? "q%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
918	: "q%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
919	i, i < 10 ? " " : "",
920	pCtx->aVRegs[i].au32[3],
921	pCtx->aVRegs[i].au32[2],
922	pCtx->aVRegs[i].au32[1],
923	pCtx->aVRegs[i].au32[0]);
924
925	pHlp->pfnPrintf(pHlp, "mdscr_el1=%016RX64\n", pCtx->Mdscr.u64);
926	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aBp); i++)
927	pHlp->pfnPrintf(pHlp, "DbgBp%u%s: Control=%016RX64 Value=%016RX64\n",
928	i, i < 10 ? " " : "",
929	pCtx->aBp[i].Ctrl, pCtx->aBp[i].Value);
930
931	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aWp); i++)
932	pHlp->pfnPrintf(pHlp, "DbgWp%u%s: Control=%016RX64 Value=%016RX64\n",
933	i, i < 10 ? " " : "",
934	pCtx->aWp[i].Ctrl, pCtx->aWp[i].Value);
935
936	pHlp->pfnPrintf(pHlp, "APDAKey=%016RX64'%016RX64\n", pCtx->Apda.High.u64, pCtx->Apda.Low.u64);
937	pHlp->pfnPrintf(pHlp, "APDBKey=%016RX64'%016RX64\n", pCtx->Apdb.High.u64, pCtx->Apdb.Low.u64);
938	pHlp->pfnPrintf(pHlp, "APGAKey=%016RX64'%016RX64\n", pCtx->Apga.High.u64, pCtx->Apga.Low.u64);
939	pHlp->pfnPrintf(pHlp, "APIAKey=%016RX64'%016RX64\n", pCtx->Apia.High.u64, pCtx->Apia.Low.u64);
940	pHlp->pfnPrintf(pHlp, "APIBKey=%016RX64'%016RX64\n", pCtx->Apib.High.u64, pCtx->Apib.Low.u64);
941
942	break;
943	}
944	}
945
946
947	/**
948	* Display all cpu states and any other cpum info.
949	*
950	* @param pVM The cross context VM structure.
951	* @param pHlp The info helper functions.
952	* @param pszArgs Arguments, ignored.
953	*/
954	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
955	{
956	cpumR3InfoGuest(pVM, pHlp, pszArgs);
957	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
958	}
959
960
961	/**
962	* Parses the info argument.
963	*
964	* The argument starts with 'verbose', 'terse' or 'default' and then
965	* continues with the comment string.
966	*
967	* @param pszArgs The pointer to the argument string.
968	* @param penmType Where to store the dump type request.
969	* @param ppszComment Where to store the pointer to the comment string.
970	*/
971	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
972	{
973	if (!pszArgs)
974	{
975	*penmType = CPUMDUMPTYPE_DEFAULT;
976	*ppszComment = "";
977	}
978	else
979	{
980	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
981	{
982	pszArgs += 7;
983	*penmType = CPUMDUMPTYPE_VERBOSE;
984	}
985	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
986	{
987	pszArgs += 5;
988	*penmType = CPUMDUMPTYPE_TERSE;
989	}
990	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
991	{
992	pszArgs += 7;
993	*penmType = CPUMDUMPTYPE_DEFAULT;
994	}
995	else
996	*penmType = CPUMDUMPTYPE_DEFAULT;
997	*ppszComment = RTStrStripL(pszArgs);
998	}
999	}
1000
1001
1002	/**
1003	* Display the guest cpu state.
1004	*
1005	* @param pVM The cross context VM structure.
1006	* @param pHlp The info helper functions.
1007	* @param pszArgs Arguments.
1008	*/
1009	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1010	{
1011	CPUMDUMPTYPE enmType;
1012	const char *pszComment;
1013	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1014
1015	PVMCPU pVCpu = VMMGetCpu(pVM);
1016	if (!pVCpu)
1017	pVCpu = pVM->apCpusR3[0];
1018
1019	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
1020
1021	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1022	cpumR3InfoOne(pVM, pCtx, pHlp, enmType);
1023	}
1024
1025
1026	/**
1027	* Display the current guest instruction
1028	*
1029	* @param pVM The cross context VM structure.
1030	* @param pHlp The info helper functions.
1031	* @param pszArgs Arguments, ignored.
1032	*/
1033	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1034	{
1035	NOREF(pszArgs);
1036
1037	PVMCPU pVCpu = VMMGetCpu(pVM);
1038	if (!pVCpu)
1039	pVCpu = pVM->apCpusR3[0];
1040
1041	char szInstruction[256];
1042	szInstruction[0] = '\0';
1043	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
1044	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
1045	}
1046
1047
1048	/**
1049	* Called when the ring-3 init phase completes.
1050	*
1051	* @returns VBox status code.
1052	* @param pVM The cross context VM structure.
1053	* @param enmWhat Which init phase.
1054	*/
1055	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1056	{
1057	RT_NOREF(pVM, enmWhat);
1058	return VINF_SUCCESS;
1059	}
1060
1061
1062	/**
1063	* Called when the ring-0 init phases completed.
1064	*
1065	* @param pVM The cross context VM structure.
1066	*/
1067	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
1068	{
1069	/*
1070	* Enable log buffering as we're going to log a lot of lines.
1071	*/
1072	bool const fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1073
1074	/*
1075	* Log the cpuid.
1076	*/
1077	RTCPUSET OnlineSet;
1078	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
1079	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
1080	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
1081	RTCPUID cCores = RTMpGetCoreCount();
1082	if (cCores)
1083	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
1084	LogRel(("*********************** CPUID dump **********************\n"));
1085	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
1086	LogRel(("\n"));
1087	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
1088	LogRel(("****************** End of CPUID dump ********************\n"));
1089
1090	LogRel(("****************** CPU feature dump *********************\n"));
1091	DBGFR3Info(pVM->pUVM, "cpufeat", "verbose", DBGFR3InfoLogRelHlp());
1092	LogRel(("\n"));
1093	DBGFR3_INFO_LOG_SAFE(pVM, "cpufeat", "verbose"); /* macro */
1094	LogRel(("*************** End of CPU feature dump *****************\n"));
1095
1096	/*
1097	* Restore the log buffering state to what it was previously.
1098	*/
1099	RTLogRelSetBuffering(fOldBuffered);
1100	}
1101
1102
1103	/**
1104	* Marks the guest debug state as active.
1105	*
1106	* @param pVCpu The cross context virtual CPU structure.
1107	*
1108	* @note This is used solely by NEM (hence the name) to set the correct flags here
1109	* without loading the host's DRx registers, which is not possible from ring-3 anyway.
1110	* The specific NEM backends have to make sure to load the correct values.
1111	*/
1112	VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu)
1113	{
1114	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HYPER);
1115	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
1116	}
1117
1118
1119	/**
1120	* Marks the hyper debug state as active.
1121	*
1122	* @param pVCpu The cross context virtual CPU structure.
1123	*
1124	* @note This is used solely by NEM (hence the name) to set the correct flags here
1125	* without loading the host's debug registers, which is not possible from ring-3 anyway.
1126	* The specific NEM backends have to make sure to load the correct values.
1127	*/
1128	VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu)
1129	{
1130	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_GUEST);
1131	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
1132	}

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM-armv8.cpp@ 107044

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