VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/APIC.cpp@ 72358

Last change on this file since 72358 was 71280, checked in by vboxsync, 7 years ago

VMM/APIC: Log when Hyper-V x2APIC compatibility mode is enabled.
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1/* $Id: APIC.cpp 71280 2018-03-09 04:36:28Z vboxsync $ */
2/** @file
3 * APIC - Advanced Programmable Interrupt Controller.
4 */
5
6/*
7 * Copyright (C) 2016-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_APIC
23#include <VBox/log.h>
24#include "APICInternal.h"
25#include <VBox/vmm/cpum.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/ssm.h>
30#include <VBox/vmm/vm.h>
31
32
33#ifndef VBOX_DEVICE_STRUCT_TESTCASE
34
35
36/*********************************************************************************************************************************
37* Defined Constants And Macros *
38*********************************************************************************************************************************/
39/** The current APIC saved state version. */
40#define APIC_SAVED_STATE_VERSION 5
41/** VirtualBox 5.1 beta2 - pre fActiveLintX. */
42#define APIC_SAVED_STATE_VERSION_VBOX_51_BETA2 4
43/** The saved state version used by VirtualBox 5.0 and
44 * earlier. */
45#define APIC_SAVED_STATE_VERSION_VBOX_50 3
46/** The saved state version used by VirtualBox v3 and earlier.
47 * This does not include the config. */
48#define APIC_SAVED_STATE_VERSION_VBOX_30 2
49/** Some ancient version... */
50#define APIC_SAVED_STATE_VERSION_ANCIENT 1
51
52#ifdef VBOX_WITH_STATISTICS
53# define X2APIC_MSRRANGE(a_uFirst, a_uLast, a_szName) \
54 { (a_uFirst), (a_uLast), kCpumMsrRdFn_Ia32X2ApicN, kCpumMsrWrFn_Ia32X2ApicN, 0, 0, 0, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
55# define X2APIC_MSRRANGE_INVALID(a_uFirst, a_uLast, a_szName) \
56 { (a_uFirst), (a_uLast), kCpumMsrRdFn_WriteOnly, kCpumMsrWrFn_ReadOnly, 0, 0, 0, 0, UINT64_MAX /*fWrGpMask*/, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
57#else
58# define X2APIC_MSRRANGE(a_uFirst, a_uLast, a_szName) \
59 { (a_uFirst), (a_uLast), kCpumMsrRdFn_Ia32X2ApicN, kCpumMsrWrFn_Ia32X2ApicN, 0, 0, 0, 0, 0, a_szName }
60# define X2APIC_MSRRANGE_INVALID(a_uFirst, a_uLast, a_szName) \
61 { (a_uFirst), (a_uLast), kCpumMsrRdFn_WriteOnly, kCpumMsrWrFn_ReadOnly, 0, 0, 0, 0, UINT64_MAX /*fWrGpMask*/, a_szName }
62#endif
63
64
65/*********************************************************************************************************************************
66* Global Variables *
67*********************************************************************************************************************************/
68/**
69 * MSR range supported by the x2APIC.
70 * See Intel spec. 10.12.2 "x2APIC Register Availability".
71 */
72static CPUMMSRRANGE const g_MsrRange_x2Apic = X2APIC_MSRRANGE(MSR_IA32_X2APIC_START, MSR_IA32_X2APIC_END, "x2APIC range");
73static CPUMMSRRANGE const g_MsrRange_x2Apic_Invalid = X2APIC_MSRRANGE_INVALID(MSR_IA32_X2APIC_START, MSR_IA32_X2APIC_END, "x2APIC range invalid");
74#undef X2APIC_MSRRANGE
75#undef X2APIC_MSRRANGE_GP
76
77/** Saved state field descriptors for XAPICPAGE. */
78static const SSMFIELD g_aXApicPageFields[] =
79{
80 SSMFIELD_ENTRY( XAPICPAGE, id.u8ApicId),
81 SSMFIELD_ENTRY( XAPICPAGE, version.all.u32Version),
82 SSMFIELD_ENTRY( XAPICPAGE, tpr.u8Tpr),
83 SSMFIELD_ENTRY( XAPICPAGE, apr.u8Apr),
84 SSMFIELD_ENTRY( XAPICPAGE, ppr.u8Ppr),
85 SSMFIELD_ENTRY( XAPICPAGE, ldr.all.u32Ldr),
86 SSMFIELD_ENTRY( XAPICPAGE, dfr.all.u32Dfr),
87 SSMFIELD_ENTRY( XAPICPAGE, svr.all.u32Svr),
88 SSMFIELD_ENTRY( XAPICPAGE, isr.u[0].u32Reg),
89 SSMFIELD_ENTRY( XAPICPAGE, isr.u[1].u32Reg),
90 SSMFIELD_ENTRY( XAPICPAGE, isr.u[2].u32Reg),
91 SSMFIELD_ENTRY( XAPICPAGE, isr.u[3].u32Reg),
92 SSMFIELD_ENTRY( XAPICPAGE, isr.u[4].u32Reg),
93 SSMFIELD_ENTRY( XAPICPAGE, isr.u[5].u32Reg),
94 SSMFIELD_ENTRY( XAPICPAGE, isr.u[6].u32Reg),
95 SSMFIELD_ENTRY( XAPICPAGE, isr.u[7].u32Reg),
96 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[0].u32Reg),
97 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[1].u32Reg),
98 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[2].u32Reg),
99 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[3].u32Reg),
100 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[4].u32Reg),
101 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[5].u32Reg),
102 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[6].u32Reg),
103 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[7].u32Reg),
104 SSMFIELD_ENTRY( XAPICPAGE, irr.u[0].u32Reg),
105 SSMFIELD_ENTRY( XAPICPAGE, irr.u[1].u32Reg),
106 SSMFIELD_ENTRY( XAPICPAGE, irr.u[2].u32Reg),
107 SSMFIELD_ENTRY( XAPICPAGE, irr.u[3].u32Reg),
108 SSMFIELD_ENTRY( XAPICPAGE, irr.u[4].u32Reg),
109 SSMFIELD_ENTRY( XAPICPAGE, irr.u[5].u32Reg),
110 SSMFIELD_ENTRY( XAPICPAGE, irr.u[6].u32Reg),
111 SSMFIELD_ENTRY( XAPICPAGE, irr.u[7].u32Reg),
112 SSMFIELD_ENTRY( XAPICPAGE, esr.all.u32Errors),
113 SSMFIELD_ENTRY( XAPICPAGE, icr_lo.all.u32IcrLo),
114 SSMFIELD_ENTRY( XAPICPAGE, icr_hi.all.u32IcrHi),
115 SSMFIELD_ENTRY( XAPICPAGE, lvt_timer.all.u32LvtTimer),
116 SSMFIELD_ENTRY( XAPICPAGE, lvt_thermal.all.u32LvtThermal),
117 SSMFIELD_ENTRY( XAPICPAGE, lvt_perf.all.u32LvtPerf),
118 SSMFIELD_ENTRY( XAPICPAGE, lvt_lint0.all.u32LvtLint0),
119 SSMFIELD_ENTRY( XAPICPAGE, lvt_lint1.all.u32LvtLint1),
120 SSMFIELD_ENTRY( XAPICPAGE, lvt_error.all.u32LvtError),
121 SSMFIELD_ENTRY( XAPICPAGE, timer_icr.u32InitialCount),
122 SSMFIELD_ENTRY( XAPICPAGE, timer_ccr.u32CurrentCount),
123 SSMFIELD_ENTRY( XAPICPAGE, timer_dcr.all.u32DivideValue),
124 SSMFIELD_ENTRY_TERM()
125};
126
127/** Saved state field descriptors for X2APICPAGE. */
128static const SSMFIELD g_aX2ApicPageFields[] =
129{
130 SSMFIELD_ENTRY(X2APICPAGE, id.u32ApicId),
131 SSMFIELD_ENTRY(X2APICPAGE, version.all.u32Version),
132 SSMFIELD_ENTRY(X2APICPAGE, tpr.u8Tpr),
133 SSMFIELD_ENTRY(X2APICPAGE, ppr.u8Ppr),
134 SSMFIELD_ENTRY(X2APICPAGE, ldr.u32LogicalApicId),
135 SSMFIELD_ENTRY(X2APICPAGE, svr.all.u32Svr),
136 SSMFIELD_ENTRY(X2APICPAGE, isr.u[0].u32Reg),
137 SSMFIELD_ENTRY(X2APICPAGE, isr.u[1].u32Reg),
138 SSMFIELD_ENTRY(X2APICPAGE, isr.u[2].u32Reg),
139 SSMFIELD_ENTRY(X2APICPAGE, isr.u[3].u32Reg),
140 SSMFIELD_ENTRY(X2APICPAGE, isr.u[4].u32Reg),
141 SSMFIELD_ENTRY(X2APICPAGE, isr.u[5].u32Reg),
142 SSMFIELD_ENTRY(X2APICPAGE, isr.u[6].u32Reg),
143 SSMFIELD_ENTRY(X2APICPAGE, isr.u[7].u32Reg),
144 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[0].u32Reg),
145 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[1].u32Reg),
146 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[2].u32Reg),
147 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[3].u32Reg),
148 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[4].u32Reg),
149 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[5].u32Reg),
150 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[6].u32Reg),
151 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[7].u32Reg),
152 SSMFIELD_ENTRY(X2APICPAGE, irr.u[0].u32Reg),
153 SSMFIELD_ENTRY(X2APICPAGE, irr.u[1].u32Reg),
154 SSMFIELD_ENTRY(X2APICPAGE, irr.u[2].u32Reg),
155 SSMFIELD_ENTRY(X2APICPAGE, irr.u[3].u32Reg),
156 SSMFIELD_ENTRY(X2APICPAGE, irr.u[4].u32Reg),
157 SSMFIELD_ENTRY(X2APICPAGE, irr.u[5].u32Reg),
158 SSMFIELD_ENTRY(X2APICPAGE, irr.u[6].u32Reg),
159 SSMFIELD_ENTRY(X2APICPAGE, irr.u[7].u32Reg),
160 SSMFIELD_ENTRY(X2APICPAGE, esr.all.u32Errors),
161 SSMFIELD_ENTRY(X2APICPAGE, icr_lo.all.u32IcrLo),
162 SSMFIELD_ENTRY(X2APICPAGE, icr_hi.u32IcrHi),
163 SSMFIELD_ENTRY(X2APICPAGE, lvt_timer.all.u32LvtTimer),
164 SSMFIELD_ENTRY(X2APICPAGE, lvt_thermal.all.u32LvtThermal),
165 SSMFIELD_ENTRY(X2APICPAGE, lvt_perf.all.u32LvtPerf),
166 SSMFIELD_ENTRY(X2APICPAGE, lvt_lint0.all.u32LvtLint0),
167 SSMFIELD_ENTRY(X2APICPAGE, lvt_lint1.all.u32LvtLint1),
168 SSMFIELD_ENTRY(X2APICPAGE, lvt_error.all.u32LvtError),
169 SSMFIELD_ENTRY(X2APICPAGE, timer_icr.u32InitialCount),
170 SSMFIELD_ENTRY(X2APICPAGE, timer_ccr.u32CurrentCount),
171 SSMFIELD_ENTRY(X2APICPAGE, timer_dcr.all.u32DivideValue),
172 SSMFIELD_ENTRY_TERM()
173};
174
175
176/**
177 * Initializes per-VCPU APIC to the state following an INIT reset
178 * ("Wait-for-SIPI" state).
179 *
180 * @param pVCpu The cross context virtual CPU structure.
181 */
182static void apicR3InitIpi(PVMCPU pVCpu)
183{
184 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
185 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
186
187 /*
188 * See Intel spec. 10.4.7.3 "Local APIC State After an INIT Reset (Wait-for-SIPI State)"
189 * and AMD spec 16.3.2 "APIC Registers".
190 *
191 * The reason we don't simply zero out the entire APIC page and only set the non-zero members
192 * is because there are some registers that are not touched by the INIT IPI (e.g. version)
193 * operation and this function is only a subset of the reset operation.
194 */
195 RT_ZERO(pXApicPage->irr);
196 RT_ZERO(pXApicPage->irr);
197 RT_ZERO(pXApicPage->isr);
198 RT_ZERO(pXApicPage->tmr);
199 RT_ZERO(pXApicPage->icr_hi);
200 RT_ZERO(pXApicPage->icr_lo);
201 RT_ZERO(pXApicPage->ldr);
202 RT_ZERO(pXApicPage->tpr);
203 RT_ZERO(pXApicPage->ppr);
204 RT_ZERO(pXApicPage->timer_icr);
205 RT_ZERO(pXApicPage->timer_ccr);
206 RT_ZERO(pXApicPage->timer_dcr);
207
208 pXApicPage->dfr.u.u4Model = XAPICDESTFORMAT_FLAT;
209 pXApicPage->dfr.u.u28ReservedMb1 = UINT32_C(0xfffffff);
210
211 /** @todo CMCI. */
212
213 RT_ZERO(pXApicPage->lvt_timer);
214 pXApicPage->lvt_timer.u.u1Mask = 1;
215
216#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
217 RT_ZERO(pXApicPage->lvt_thermal);
218 pXApicPage->lvt_thermal.u.u1Mask = 1;
219#endif
220
221 RT_ZERO(pXApicPage->lvt_perf);
222 pXApicPage->lvt_perf.u.u1Mask = 1;
223
224 RT_ZERO(pXApicPage->lvt_lint0);
225 pXApicPage->lvt_lint0.u.u1Mask = 1;
226
227 RT_ZERO(pXApicPage->lvt_lint1);
228 pXApicPage->lvt_lint1.u.u1Mask = 1;
229
230 RT_ZERO(pXApicPage->lvt_error);
231 pXApicPage->lvt_error.u.u1Mask = 1;
232
233 RT_ZERO(pXApicPage->svr);
234 pXApicPage->svr.u.u8SpuriousVector = 0xff;
235
236 /* The self-IPI register is reset to 0. See Intel spec. 10.12.5.1 "x2APIC States" */
237 PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
238 RT_ZERO(pX2ApicPage->self_ipi);
239
240 /* Clear the pending-interrupt bitmaps. */
241 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
242 RT_BZERO(&pApicCpu->ApicPibLevel, sizeof(APICPIB));
243 RT_BZERO(pApicCpu->pvApicPibR3, sizeof(APICPIB));
244
245 /* Clear the interrupt line states for LINT0 and LINT1 pins. */
246 pApicCpu->fActiveLint0 = false;
247 pApicCpu->fActiveLint1 = false;
248}
249
250
251/**
252 * Sets the CPUID feature bits for the APIC mode.
253 *
254 * @param pVM The cross context VM structure.
255 * @param enmMode The APIC mode.
256 */
257static void apicR3SetCpuIdFeatureLevel(PVM pVM, PDMAPICMODE enmMode)
258{
259 switch (enmMode)
260 {
261 case PDMAPICMODE_NONE:
262 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
263 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
264 break;
265
266 case PDMAPICMODE_APIC:
267 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
268 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
269 break;
270
271 case PDMAPICMODE_X2APIC:
272 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
273 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
274 break;
275
276 default:
277 AssertMsgFailed(("Unknown/invalid APIC mode: %d\n", (int)enmMode));
278 }
279}
280
281
282/**
283 * Resets the APIC base MSR.
284 *
285 * @param pVCpu The cross context virtual CPU structure.
286 */
287static void apicR3ResetBaseMsr(PVMCPU pVCpu)
288{
289 /*
290 * Initialize the APIC base MSR. The APIC enable-bit is set upon power-up or reset[1].
291 *
292 * A Reset (in xAPIC and x2APIC mode) brings up the local APIC in xAPIC mode.
293 * An INIT IPI does -not- cause a transition between xAPIC and x2APIC mode[2].
294 *
295 * [1] See AMD spec. 14.1.3 "Processor Initialization State"
296 * [2] See Intel spec. 10.12.5.1 "x2APIC States".
297 */
298 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
299
300 /* Construct. */
301 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
302 PAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
303 uint64_t uApicBaseMsr = MSR_IA32_APICBASE_ADDR;
304 if (pVCpu->idCpu == 0)
305 uApicBaseMsr |= MSR_IA32_APICBASE_BSP;
306
307 /* If the VM was configured with no APIC, don't enable xAPIC mode, obviously. */
308 if (pApic->enmMaxMode != PDMAPICMODE_NONE)
309 {
310 uApicBaseMsr |= MSR_IA32_APICBASE_EN;
311
312 /*
313 * While coming out of a reset the APIC is enabled and in xAPIC mode. If software had previously
314 * disabled the APIC (which results in the CPUID bit being cleared as well) we re-enable it here.
315 * See Intel spec. 10.12.5.1 "x2APIC States".
316 */
317 if (CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, true /*fVisible*/) == false)
318 LogRel(("APIC%u: Resetting mode to xAPIC\n", pVCpu->idCpu));
319 }
320
321 /* Commit. */
322 ASMAtomicWriteU64(&pApicCpu->uApicBaseMsr, uApicBaseMsr);
323}
324
325
326/**
327 * Initializes per-VCPU APIC to the state following a power-up or hardware
328 * reset.
329 *
330 * @param pVCpu The cross context virtual CPU structure.
331 * @param fResetApicBaseMsr Whether to reset the APIC base MSR.
332 */
333VMMR3_INT_DECL(void) apicR3ResetCpu(PVMCPU pVCpu, bool fResetApicBaseMsr)
334{
335 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
336
337 LogFlow(("APIC%u: apicR3ResetCpu: fResetApicBaseMsr=%RTbool\n", pVCpu->idCpu, fResetApicBaseMsr));
338
339#ifdef VBOX_STRICT
340 /* Verify that the initial APIC ID reported via CPUID matches our VMCPU ID assumption. */
341 uint32_t uEax, uEbx, uEcx, uEdx;
342 uEax = uEbx = uEcx = uEdx = UINT32_MAX;
343 CPUMGetGuestCpuId(pVCpu, 1, 0, &uEax, &uEbx, &uEcx, &uEdx);
344 Assert(((uEbx >> 24) & 0xff) == pVCpu->idCpu);
345#endif
346
347 /*
348 * The state following a power-up or reset is a superset of the INIT state.
349 * See Intel spec. 10.4.7.3 "Local APIC State After an INIT Reset ('Wait-for-SIPI' State)"
350 */
351 apicR3InitIpi(pVCpu);
352
353 /*
354 * The APIC version register is read-only, so just initialize it here.
355 * It is not clear from the specs, where exactly it is initialized.
356 * The version determines the number of LVT entries and size of the APIC ID (8 bits for P4).
357 */
358 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
359#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
360 pXApicPage->version.u.u8MaxLvtEntry = XAPIC_MAX_LVT_ENTRIES_P4 - 1;
361 pXApicPage->version.u.u8Version = XAPIC_HARDWARE_VERSION_P4;
362 AssertCompile(sizeof(pXApicPage->id.u8ApicId) >= XAPIC_APIC_ID_BIT_COUNT_P4 / 8);
363#else
364# error "Implement Pentium and P6 family APIC architectures"
365#endif
366
367 /** @todo It isn't clear in the spec. where exactly the default base address
368 * is (re)initialized, atm we do it here in Reset. */
369 if (fResetApicBaseMsr)
370 apicR3ResetBaseMsr(pVCpu);
371
372 /*
373 * Initialize the APIC ID register to xAPIC format.
374 */
375 ASMMemZero32(&pXApicPage->id, sizeof(pXApicPage->id));
376 pXApicPage->id.u8ApicId = pVCpu->idCpu;
377}
378
379
380/**
381 * Receives an INIT IPI.
382 *
383 * @param pVCpu The cross context virtual CPU structure.
384 */
385VMMR3_INT_DECL(void) APICR3InitIpi(PVMCPU pVCpu)
386{
387 VMCPU_ASSERT_EMT(pVCpu);
388 LogFlow(("APIC%u: APICR3InitIpi\n", pVCpu->idCpu));
389 apicR3InitIpi(pVCpu);
390}
391
392
393/**
394 * Sets whether Hyper-V compatibility mode (MSR interface) is enabled or not.
395 *
396 * This mode is a hybrid of xAPIC and x2APIC modes, some caveats:
397 * 1. MSRs are used even ones that are missing (illegal) in x2APIC like DFR.
398 * 2. A single ICR is used by the guest to send IPIs rather than 2 ICR writes.
399 * 3. It is unclear what the behaviour will be when invalid bits are set,
400 * currently we follow x2APIC behaviour of causing a \#GP.
401 *
402 * @param pVM The cross context VM structure.
403 * @param fHyperVCompatMode Whether the compatibility mode is enabled.
404 */
405VMMR3_INT_DECL(void) APICR3HvSetCompatMode(PVM pVM, bool fHyperVCompatMode)
406{
407 Assert(pVM);
408 PAPIC pApic = VM_TO_APIC(pVM);
409 pApic->fHyperVCompatMode = fHyperVCompatMode;
410
411 if (fHyperVCompatMode)
412 LogRel(("APIC: Enabling Hyper-V x2APIC compatibility mode\n"));
413
414 int rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic);
415 AssertLogRelRC(rc);
416}
417
418
419/**
420 * Helper for dumping an APIC 256-bit sparse register.
421 *
422 * @param pApicReg The APIC 256-bit spare register.
423 * @param pHlp The debug output helper.
424 */
425static void apicR3DbgInfo256BitReg(volatile const XAPIC256BITREG *pApicReg, PCDBGFINFOHLP pHlp)
426{
427 ssize_t const cFragments = RT_ELEMENTS(pApicReg->u);
428 unsigned const cBitsPerFragment = sizeof(pApicReg->u[0].u32Reg) * 8;
429 XAPIC256BITREG ApicReg;
430 RT_ZERO(ApicReg);
431
432 pHlp->pfnPrintf(pHlp, " ");
433 for (ssize_t i = cFragments - 1; i >= 0; i--)
434 {
435 uint32_t const uFragment = pApicReg->u[i].u32Reg;
436 ApicReg.u[i].u32Reg = uFragment;
437 pHlp->pfnPrintf(pHlp, "%08x", uFragment);
438 }
439 pHlp->pfnPrintf(pHlp, "\n");
440
441 uint32_t cPending = 0;
442 pHlp->pfnPrintf(pHlp, " Pending:");
443 for (ssize_t i = cFragments - 1; i >= 0; i--)
444 {
445 uint32_t uFragment = ApicReg.u[i].u32Reg;
446 if (uFragment)
447 {
448 do
449 {
450 unsigned idxSetBit = ASMBitLastSetU32(uFragment);
451 --idxSetBit;
452 ASMBitClear(&uFragment, idxSetBit);
453
454 idxSetBit += (i * cBitsPerFragment);
455 pHlp->pfnPrintf(pHlp, " %#02x", idxSetBit);
456 ++cPending;
457 } while (uFragment);
458 }
459 }
460 if (!cPending)
461 pHlp->pfnPrintf(pHlp, " None");
462 pHlp->pfnPrintf(pHlp, "\n");
463}
464
465
466/**
467 * Helper for dumping an APIC pending-interrupt bitmap.
468 *
469 * @param pApicPib The pending-interrupt bitmap.
470 * @param pHlp The debug output helper.
471 */
472static void apicR3DbgInfoPib(PCAPICPIB pApicPib, PCDBGFINFOHLP pHlp)
473{
474 /* Copy the pending-interrupt bitmap as an APIC 256-bit sparse register. */
475 XAPIC256BITREG ApicReg;
476 RT_ZERO(ApicReg);
477 ssize_t const cFragmentsDst = RT_ELEMENTS(ApicReg.u);
478 ssize_t const cFragmentsSrc = RT_ELEMENTS(pApicPib->au64VectorBitmap);
479 AssertCompile(RT_ELEMENTS(ApicReg.u) == 2 * RT_ELEMENTS(pApicPib->au64VectorBitmap));
480 for (ssize_t idxPib = cFragmentsSrc - 1, idxReg = cFragmentsDst - 1; idxPib >= 0; idxPib--, idxReg -= 2)
481 {
482 uint64_t const uFragment = pApicPib->au64VectorBitmap[idxPib];
483 uint32_t const uFragmentLo = RT_LO_U32(uFragment);
484 uint32_t const uFragmentHi = RT_HI_U32(uFragment);
485 ApicReg.u[idxReg].u32Reg = uFragmentHi;
486 ApicReg.u[idxReg - 1].u32Reg = uFragmentLo;
487 }
488
489 /* Dump it. */
490 apicR3DbgInfo256BitReg(&ApicReg, pHlp);
491}
492
493
494/**
495 * Dumps basic APIC state.
496 *
497 * @param pVM The cross context VM structure.
498 * @param pHlp The info helpers.
499 * @param pszArgs Arguments, ignored.
500 */
501static DECLCALLBACK(void) apicR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
502{
503 NOREF(pszArgs);
504 PVMCPU pVCpu = VMMGetCpu(pVM);
505 if (!pVCpu)
506 pVCpu = &pVM->aCpus[0];
507
508 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
509 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
510 PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
511
512 uint64_t const uBaseMsr = pApicCpu->uApicBaseMsr;
513 APICMODE const enmMode = apicGetMode(uBaseMsr);
514 bool const fX2ApicMode = XAPIC_IN_X2APIC_MODE(pVCpu);
515
516 pHlp->pfnPrintf(pHlp, "APIC%u:\n", pVCpu->idCpu);
517 pHlp->pfnPrintf(pHlp, " APIC Base MSR = %#RX64 (Addr=%#RX64)\n", uBaseMsr,
518 MSR_IA32_APICBASE_GET_ADDR(uBaseMsr));
519 pHlp->pfnPrintf(pHlp, " Mode = %u (%s)\n", enmMode, apicGetModeName(enmMode));
520 if (fX2ApicMode)
521 {
522 pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pX2ApicPage->id.u32ApicId,
523 pX2ApicPage->id.u32ApicId);
524 }
525 else
526 pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pXApicPage->id.u8ApicId, pXApicPage->id.u8ApicId);
527 pHlp->pfnPrintf(pHlp, " Version = %#x\n", pXApicPage->version.all.u32Version);
528 pHlp->pfnPrintf(pHlp, " APIC Version = %#x\n", pXApicPage->version.u.u8Version);
529 pHlp->pfnPrintf(pHlp, " Max LVT entry index (0..N) = %u\n", pXApicPage->version.u.u8MaxLvtEntry);
530 pHlp->pfnPrintf(pHlp, " EOI Broadcast supression = %RTbool\n", pXApicPage->version.u.fEoiBroadcastSupression);
531 if (!fX2ApicMode)
532 pHlp->pfnPrintf(pHlp, " APR = %u (%#x)\n", pXApicPage->apr.u8Apr, pXApicPage->apr.u8Apr);
533 pHlp->pfnPrintf(pHlp, " TPR = %u (%#x)\n", pXApicPage->tpr.u8Tpr, pXApicPage->tpr.u8Tpr);
534 pHlp->pfnPrintf(pHlp, " Task-priority class = %#x\n", XAPIC_TPR_GET_TP(pXApicPage->tpr.u8Tpr) >> 4);
535 pHlp->pfnPrintf(pHlp, " Task-priority subclass = %#x\n", XAPIC_TPR_GET_TP_SUBCLASS(pXApicPage->tpr.u8Tpr));
536 pHlp->pfnPrintf(pHlp, " PPR = %u (%#x)\n", pXApicPage->ppr.u8Ppr, pXApicPage->ppr.u8Ppr);
537 pHlp->pfnPrintf(pHlp, " Processor-priority class = %#x\n", XAPIC_PPR_GET_PP(pXApicPage->ppr.u8Ppr) >> 4);
538 pHlp->pfnPrintf(pHlp, " Processor-priority subclass = %#x\n", XAPIC_PPR_GET_PP_SUBCLASS(pXApicPage->ppr.u8Ppr));
539 if (!fX2ApicMode)
540 pHlp->pfnPrintf(pHlp, " RRD = %u (%#x)\n", pXApicPage->rrd.u32Rrd, pXApicPage->rrd.u32Rrd);
541 pHlp->pfnPrintf(pHlp, " LDR = %#x\n", pXApicPage->ldr.all.u32Ldr);
542 pHlp->pfnPrintf(pHlp, " Logical APIC ID = %#x\n", fX2ApicMode ? pX2ApicPage->ldr.u32LogicalApicId
543 : pXApicPage->ldr.u.u8LogicalApicId);
544 if (!fX2ApicMode)
545 {
546 pHlp->pfnPrintf(pHlp, " DFR = %#x\n", pXApicPage->dfr.all.u32Dfr);
547 pHlp->pfnPrintf(pHlp, " Model = %#x (%s)\n", pXApicPage->dfr.u.u4Model,
548 apicGetDestFormatName((XAPICDESTFORMAT)pXApicPage->dfr.u.u4Model));
549 }
550 pHlp->pfnPrintf(pHlp, " SVR = %#x\n", pXApicPage->svr.all.u32Svr);
551 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->svr.u.u8SpuriousVector,
552 pXApicPage->svr.u.u8SpuriousVector);
553 pHlp->pfnPrintf(pHlp, " Software Enabled = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fApicSoftwareEnable));
554 pHlp->pfnPrintf(pHlp, " Supress EOI broadcast = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fSupressEoiBroadcast));
555 pHlp->pfnPrintf(pHlp, " ISR\n");
556 apicR3DbgInfo256BitReg(&pXApicPage->isr, pHlp);
557 pHlp->pfnPrintf(pHlp, " TMR\n");
558 apicR3DbgInfo256BitReg(&pXApicPage->tmr, pHlp);
559 pHlp->pfnPrintf(pHlp, " IRR\n");
560 apicR3DbgInfo256BitReg(&pXApicPage->irr, pHlp);
561 pHlp->pfnPrintf(pHlp, " PIB\n");
562 apicR3DbgInfoPib((PCAPICPIB)pApicCpu->pvApicPibR3, pHlp);
563 pHlp->pfnPrintf(pHlp, " Level PIB\n");
564 apicR3DbgInfoPib(&pApicCpu->ApicPibLevel, pHlp);
565 pHlp->pfnPrintf(pHlp, " ESR Internal = %#x\n", pApicCpu->uEsrInternal);
566 pHlp->pfnPrintf(pHlp, " ESR = %#x\n", pXApicPage->esr.all.u32Errors);
567 pHlp->pfnPrintf(pHlp, " Redirectable IPI = %RTbool\n", pXApicPage->esr.u.fRedirectableIpi);
568 pHlp->pfnPrintf(pHlp, " Send Illegal Vector = %RTbool\n", pXApicPage->esr.u.fSendIllegalVector);
569 pHlp->pfnPrintf(pHlp, " Recv Illegal Vector = %RTbool\n", pXApicPage->esr.u.fRcvdIllegalVector);
570 pHlp->pfnPrintf(pHlp, " Illegal Register Address = %RTbool\n", pXApicPage->esr.u.fIllegalRegAddr);
571 pHlp->pfnPrintf(pHlp, " ICR Low = %#x\n", pXApicPage->icr_lo.all.u32IcrLo);
572 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->icr_lo.u.u8Vector,
573 pXApicPage->icr_lo.u.u8Vector);
574 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u3DeliveryMode,
575 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->icr_lo.u.u3DeliveryMode));
576 pHlp->pfnPrintf(pHlp, " Destination Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u1DestMode,
577 apicGetDestModeName((XAPICDESTMODE)pXApicPage->icr_lo.u.u1DestMode));
578 if (!fX2ApicMode)
579 pHlp->pfnPrintf(pHlp, " Delivery Status = %u\n", pXApicPage->icr_lo.u.u1DeliveryStatus);
580 pHlp->pfnPrintf(pHlp, " Level = %u\n", pXApicPage->icr_lo.u.u1Level);
581 pHlp->pfnPrintf(pHlp, " Trigger Mode = %u (%s)\n", pXApicPage->icr_lo.u.u1TriggerMode,
582 apicGetTriggerModeName((XAPICTRIGGERMODE)pXApicPage->icr_lo.u.u1TriggerMode));
583 pHlp->pfnPrintf(pHlp, " Destination shorthand = %#x (%s)\n", pXApicPage->icr_lo.u.u2DestShorthand,
584 apicGetDestShorthandName((XAPICDESTSHORTHAND)pXApicPage->icr_lo.u.u2DestShorthand));
585 pHlp->pfnPrintf(pHlp, " ICR High = %#x\n", pXApicPage->icr_hi.all.u32IcrHi);
586 pHlp->pfnPrintf(pHlp, " Destination field/mask = %#x\n", fX2ApicMode ? pX2ApicPage->icr_hi.u32IcrHi
587 : pXApicPage->icr_hi.u.u8Dest);
588}
589
590
591/**
592 * Helper for dumping the LVT timer.
593 *
594 * @param pVCpu The cross context virtual CPU structure.
595 * @param pHlp The debug output helper.
596 */
597static void apicR3InfoLvtTimer(PVMCPU pVCpu, PCDBGFINFOHLP pHlp)
598{
599 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
600 uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
601 pHlp->pfnPrintf(pHlp, "LVT Timer = %#RX32\n", uLvtTimer);
602 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_timer.u.u8Vector, pXApicPage->lvt_timer.u.u8Vector);
603 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_timer.u.u1DeliveryStatus);
604 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtTimer));
605 pHlp->pfnPrintf(pHlp, " Timer Mode = %#x (%s)\n", pXApicPage->lvt_timer.u.u2TimerMode,
606 apicGetTimerModeName((XAPICTIMERMODE)pXApicPage->lvt_timer.u.u2TimerMode));
607}
608
609
610/**
611 * Dumps APIC Local Vector Table (LVT) information.
612 *
613 * @param pVM The cross context VM structure.
614 * @param pHlp The info helpers.
615 * @param pszArgs Arguments, ignored.
616 */
617static DECLCALLBACK(void) apicR3InfoLvt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
618{
619 NOREF(pszArgs);
620 PVMCPU pVCpu = VMMGetCpu(pVM);
621 if (!pVCpu)
622 pVCpu = &pVM->aCpus[0];
623
624 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
625
626 /*
627 * Delivery modes available in the LVT entries. They're different (more reserved stuff) from the
628 * ICR delivery modes and hence we don't use apicGetDeliveryMode but mostly because we want small,
629 * fixed-length strings to fit our formatting needs here.
630 */
631 static const char * const s_apszLvtDeliveryModes[] =
632 {
633 "Fixed ",
634 "Rsvd ",
635 "SMI ",
636 "Rsvd ",
637 "NMI ",
638 "INIT ",
639 "Rsvd ",
640 "ExtINT"
641 };
642 /* Delivery Status. */
643 static const char * const s_apszLvtDeliveryStatus[] =
644 {
645 "Idle",
646 "Pend"
647 };
648 const char *pszNotApplicable = "";
649
650 pHlp->pfnPrintf(pHlp, "VCPU[%u] APIC Local Vector Table (LVT):\n", pVCpu->idCpu);
651 pHlp->pfnPrintf(pHlp, "lvt timermode mask trigger rirr polarity dlvr_st dlvr_mode vector\n");
652 /* Timer. */
653 {
654 /* Timer modes. */
655 static const char * const s_apszLvtTimerModes[] =
656 {
657 "One-shot ",
658 "Periodic ",
659 "TSC-dline"
660 };
661 const uint32_t uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
662 const XAPICTIMERMODE enmTimerMode = XAPIC_LVT_GET_TIMER_MODE(uLvtTimer);
663 const char *pszTimerMode = s_apszLvtTimerModes[enmTimerMode];
664 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtTimer);
665 const uint8_t uDeliveryStatus = uLvtTimer & XAPIC_LVT_DELIVERY_STATUS;
666 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
667 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
668
669 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
670 "Timer",
671 pszTimerMode,
672 uMask,
673 pszNotApplicable, /* TriggerMode */
674 pszNotApplicable, /* Remote IRR */
675 pszNotApplicable, /* Polarity */
676 pszDeliveryStatus,
677 pszNotApplicable, /* Delivery Mode */
678 uVector,
679 uVector);
680 }
681
682#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
683 /* Thermal sensor. */
684 {
685 uint32_t const uLvtThermal = pXApicPage->lvt_thermal.all.u32LvtThermal;
686 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtThermal);
687 const uint8_t uDeliveryStatus = uLvtThermal & XAPIC_LVT_DELIVERY_STATUS;
688 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
689 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtThermal);
690 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
691 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtThermal);
692
693 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
694 "Thermal",
695 pszNotApplicable, /* Timer mode */
696 uMask,
697 pszNotApplicable, /* TriggerMode */
698 pszNotApplicable, /* Remote IRR */
699 pszNotApplicable, /* Polarity */
700 pszDeliveryStatus,
701 pszDeliveryMode,
702 uVector,
703 uVector);
704 }
705#endif
706
707 /* Performance Monitor Counters. */
708 {
709 uint32_t const uLvtPerf = pXApicPage->lvt_thermal.all.u32LvtThermal;
710 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtPerf);
711 const uint8_t uDeliveryStatus = uLvtPerf & XAPIC_LVT_DELIVERY_STATUS;
712 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
713 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtPerf);
714 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
715 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtPerf);
716
717 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
718 "Perf",
719 pszNotApplicable, /* Timer mode */
720 uMask,
721 pszNotApplicable, /* TriggerMode */
722 pszNotApplicable, /* Remote IRR */
723 pszNotApplicable, /* Polarity */
724 pszDeliveryStatus,
725 pszDeliveryMode,
726 uVector,
727 uVector);
728 }
729
730 /* LINT0, LINT1. */
731 {
732 /* LINTx name. */
733 static const char * const s_apszLvtLint[] =
734 {
735 "LINT0",
736 "LINT1"
737 };
738 /* Trigger mode. */
739 static const char * const s_apszLvtTriggerModes[] =
740 {
741 "Edge ",
742 "Level"
743 };
744 /* Polarity. */
745 static const char * const s_apszLvtPolarity[] =
746 {
747 "ActiveHi",
748 "ActiveLo"
749 };
750
751 uint32_t aLvtLint[2];
752 aLvtLint[0] = pXApicPage->lvt_lint0.all.u32LvtLint0;
753 aLvtLint[1] = pXApicPage->lvt_lint1.all.u32LvtLint1;
754 for (size_t i = 0; i < RT_ELEMENTS(aLvtLint); i++)
755 {
756 uint32_t const uLvtLint = aLvtLint[i];
757 const char *pszLint = s_apszLvtLint[i];
758 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtLint);
759 const XAPICTRIGGERMODE enmTriggerMode = XAPIC_LVT_GET_TRIGGER_MODE(uLvtLint);
760 const char *pszTriggerMode = s_apszLvtTriggerModes[enmTriggerMode];
761 const uint8_t uRemoteIrr = XAPIC_LVT_GET_REMOTE_IRR(uLvtLint);
762 const uint8_t uPolarity = XAPIC_LVT_GET_POLARITY(uLvtLint);
763 const char *pszPolarity = s_apszLvtPolarity[uPolarity];
764 const uint8_t uDeliveryStatus = uLvtLint & XAPIC_LVT_DELIVERY_STATUS;
765 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
766 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtLint);
767 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
768 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtLint);
769
770 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %u %8s %4s %6s %3u (%#x)\n",
771 pszLint,
772 pszNotApplicable, /* Timer mode */
773 uMask,
774 pszTriggerMode,
775 uRemoteIrr,
776 pszPolarity,
777 pszDeliveryStatus,
778 pszDeliveryMode,
779 uVector,
780 uVector);
781 }
782 }
783
784 /* Error. */
785 {
786 uint32_t const uLvtError = pXApicPage->lvt_thermal.all.u32LvtThermal;
787 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtError);
788 const uint8_t uDeliveryStatus = uLvtError & XAPIC_LVT_DELIVERY_STATUS;
789 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
790 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtError);
791 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
792 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtError);
793
794 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
795 "Error",
796 pszNotApplicable, /* Timer mode */
797 uMask,
798 pszNotApplicable, /* TriggerMode */
799 pszNotApplicable, /* Remote IRR */
800 pszNotApplicable, /* Polarity */
801 pszDeliveryStatus,
802 pszDeliveryMode,
803 uVector,
804 uVector);
805 }
806}
807
808
809/**
810 * Dumps the APIC timer information.
811 *
812 * @param pVM The cross context VM structure.
813 * @param pHlp The info helpers.
814 * @param pszArgs Arguments, ignored.
815 */
816static DECLCALLBACK(void) apicR3InfoTimer(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
817{
818 NOREF(pszArgs);
819 PVMCPU pVCpu = VMMGetCpu(pVM);
820 if (!pVCpu)
821 pVCpu = &pVM->aCpus[0];
822
823 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
824 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
825
826 pHlp->pfnPrintf(pHlp, "VCPU[%u] Local APIC timer:\n", pVCpu->idCpu);
827 pHlp->pfnPrintf(pHlp, " ICR = %#RX32\n", pXApicPage->timer_icr.u32InitialCount);
828 pHlp->pfnPrintf(pHlp, " CCR = %#RX32\n", pXApicPage->timer_ccr.u32CurrentCount);
829 pHlp->pfnPrintf(pHlp, " DCR = %#RX32\n", pXApicPage->timer_dcr.all.u32DivideValue);
830 pHlp->pfnPrintf(pHlp, " Timer shift = %#x\n", apicGetTimerShift(pXApicPage));
831 pHlp->pfnPrintf(pHlp, " Timer initial TS = %#RU64\n", pApicCpu->u64TimerInitial);
832 apicR3InfoLvtTimer(pVCpu, pHlp);
833}
834
835
836#ifdef APIC_FUZZY_SSM_COMPAT_TEST
837
838/**
839 * Reads a 32-bit register at a specified offset.
840 *
841 * @returns The value at the specified offset.
842 * @param pXApicPage The xAPIC page.
843 * @param offReg The offset of the register being read.
844 *
845 * @remarks Duplicate of apicReadRaw32()!
846 */
847static uint32_t apicR3ReadRawR32(PCXAPICPAGE pXApicPage, uint16_t offReg)
848{
849 Assert(offReg < sizeof(*pXApicPage) - sizeof(uint32_t));
850 uint8_t const *pbXApic = (const uint8_t *)pXApicPage;
851 uint32_t const uValue = *(const uint32_t *)(pbXApic + offReg);
852 return uValue;
853}
854
855
856/**
857 * Helper for dumping per-VCPU APIC state to the release logger.
858 *
859 * This is primarily concerned about the APIC state relevant for saved-states.
860 *
861 * @param pVCpu The cross context virtual CPU structure.
862 * @param pszPrefix A caller supplied prefix before dumping the state.
863 * @param uVersion Data layout version.
864 */
865static void apicR3DumpState(PVMCPU pVCpu, const char *pszPrefix, uint32_t uVersion)
866{
867 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
868
869 LogRel(("APIC%u: %s (version %u):\n", pVCpu->idCpu, pszPrefix, uVersion));
870
871 switch (uVersion)
872 {
873 case APIC_SAVED_STATE_VERSION:
874 case APIC_SAVED_STATE_VERSION_VBOX_51_BETA2:
875 {
876 /* The auxiliary state. */
877 LogRel(("APIC%u: uApicBaseMsr = %#RX64\n", pVCpu->idCpu, pApicCpu->uApicBaseMsr));
878 LogRel(("APIC%u: uEsrInternal = %#RX64\n", pVCpu->idCpu, pApicCpu->uEsrInternal));
879
880 /* The timer. */
881 LogRel(("APIC%u: u64TimerInitial = %#RU64\n", pVCpu->idCpu, pApicCpu->u64TimerInitial));
882 LogRel(("APIC%u: uHintedTimerInitialCount = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerInitialCount));
883 LogRel(("APIC%u: uHintedTimerShift = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerShift));
884
885 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
886 LogRel(("APIC%u: uTimerICR = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_icr.u32InitialCount));
887 LogRel(("APIC%u: uTimerCCR = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_ccr.u32CurrentCount));
888
889 /* The PIBs. */
890 LogRel(("APIC%u: Edge PIB : %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), pApicCpu->pvApicPibR3));
891 LogRel(("APIC%u: Level PIB: %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), &pApicCpu->ApicPibLevel));
892
893 /* The LINT0, LINT1 interrupt line active states. */
894 LogRel(("APIC%u: fActiveLint0 = %RTbool\n", pVCpu->idCpu, pApicCpu->fActiveLint0));
895 LogRel(("APIC%u: fActiveLint1 = %RTbool\n", pVCpu->idCpu, pApicCpu->fActiveLint1));
896
897 /* The APIC page. */
898 LogRel(("APIC%u: APIC page: %.*Rhxs\n", pVCpu->idCpu, sizeof(XAPICPAGE), pApicCpu->pvApicPageR3));
899 break;
900 }
901
902 case APIC_SAVED_STATE_VERSION_VBOX_50:
903 case APIC_SAVED_STATE_VERSION_VBOX_30:
904 case APIC_SAVED_STATE_VERSION_ANCIENT:
905 {
906 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
907 LogRel(("APIC%u: uApicBaseMsr = %#RX32\n", pVCpu->idCpu, RT_LO_U32(pApicCpu->uApicBaseMsr)));
908 LogRel(("APIC%u: uId = %#RX32\n", pVCpu->idCpu, pXApicPage->id.u8ApicId));
909 LogRel(("APIC%u: uPhysId = N/A\n", pVCpu->idCpu));
910 LogRel(("APIC%u: uArbId = N/A\n", pVCpu->idCpu));
911 LogRel(("APIC%u: uTpr = %#RX32\n", pVCpu->idCpu, pXApicPage->tpr.u8Tpr));
912 LogRel(("APIC%u: uSvr = %#RX32\n", pVCpu->idCpu, pXApicPage->svr.all.u32Svr));
913 LogRel(("APIC%u: uLdr = %#x\n", pVCpu->idCpu, pXApicPage->ldr.all.u32Ldr));
914 LogRel(("APIC%u: uDfr = %#x\n", pVCpu->idCpu, pXApicPage->dfr.all.u32Dfr));
915
916 for (size_t i = 0; i < 8; i++)
917 {
918 LogRel(("APIC%u: Isr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->isr.u[i].u32Reg));
919 LogRel(("APIC%u: Tmr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->tmr.u[i].u32Reg));
920 LogRel(("APIC%u: Irr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->irr.u[i].u32Reg));
921 }
922
923 for (size_t i = 0; i < XAPIC_MAX_LVT_ENTRIES_P4; i++)
924 {
925 uint16_t const offReg = XAPIC_OFF_LVT_START + (i << 4);
926 LogRel(("APIC%u: Lvt[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, apicR3ReadRawR32(pXApicPage, offReg)));
927 }
928
929 LogRel(("APIC%u: uEsr = %#RX32\n", pVCpu->idCpu, pXApicPage->esr.all.u32Errors));
930 LogRel(("APIC%u: uIcr_Lo = %#RX32\n", pVCpu->idCpu, pXApicPage->icr_lo.all.u32IcrLo));
931 LogRel(("APIC%u: uIcr_Hi = %#RX32\n", pVCpu->idCpu, pXApicPage->icr_hi.all.u32IcrHi));
932 LogRel(("APIC%u: uTimerDcr = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_dcr.all.u32DivideValue));
933 LogRel(("APIC%u: uCountShift = %#RX32\n", pVCpu->idCpu, apicGetTimerShift(pXApicPage)));
934 LogRel(("APIC%u: uInitialCount = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_icr.u32InitialCount));
935 LogRel(("APIC%u: u64InitialCountLoadTime = %#RX64\n", pVCpu->idCpu, pApicCpu->u64TimerInitial));
936 LogRel(("APIC%u: u64NextTime / TimerCCR = %#RX64\n", pVCpu->idCpu, pXApicPage->timer_ccr.u32CurrentCount));
937 break;
938 }
939
940 default:
941 {
942 LogRel(("APIC: apicR3DumpState: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
943 break;
944 }
945 }
946}
947
948#endif /* APIC_FUZZY_SSM_COMPAT_TEST */
949
950/**
951 * Worker for saving per-VM APIC data.
952 *
953 * @returns VBox status code.
954 * @param pVM The cross context VM structure.
955 * @param pSSM The SSM handle.
956 */
957static int apicR3SaveVMData(PVM pVM, PSSMHANDLE pSSM)
958{
959 PAPIC pApic = VM_TO_APIC(pVM);
960 SSMR3PutU32(pSSM, pVM->cCpus);
961 SSMR3PutBool(pSSM, pApic->fIoApicPresent);
962 return SSMR3PutU32(pSSM, pApic->enmMaxMode);
963}
964
965
966/**
967 * Worker for loading per-VM APIC data.
968 *
969 * @returns VBox status code.
970 * @param pVM The cross context VM structure.
971 * @param pSSM The SSM handle.
972 */
973static int apicR3LoadVMData(PVM pVM, PSSMHANDLE pSSM)
974{
975 PAPIC pApic = VM_TO_APIC(pVM);
976
977 /* Load and verify number of CPUs. */
978 uint32_t cCpus;
979 int rc = SSMR3GetU32(pSSM, &cCpus);
980 AssertRCReturn(rc, rc);
981 if (cCpus != pVM->cCpus)
982 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%u config=%u"), cCpus, pVM->cCpus);
983
984 /* Load and verify I/O APIC presence. */
985 bool fIoApicPresent;
986 rc = SSMR3GetBool(pSSM, &fIoApicPresent);
987 AssertRCReturn(rc, rc);
988 if (fIoApicPresent != pApic->fIoApicPresent)
989 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApicPresent: saved=%RTbool config=%RTbool"),
990 fIoApicPresent, pApic->fIoApicPresent);
991
992 /* Load and verify configured max APIC mode. */
993 uint32_t uSavedMaxApicMode;
994 rc = SSMR3GetU32(pSSM, &uSavedMaxApicMode);
995 AssertRCReturn(rc, rc);
996 if (uSavedMaxApicMode != (uint32_t)pApic->enmMaxMode)
997 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicMode: saved=%u config=%u"),
998 uSavedMaxApicMode, pApic->enmMaxMode);
999 return VINF_SUCCESS;
1000}
1001
1002
1003/**
1004 * Worker for loading per-VCPU APIC data for legacy (old) saved-states.
1005 *
1006 * @returns VBox status code.
1007 * @param pVCpu The cross context virtual CPU structure.
1008 * @param pSSM The SSM handle.
1009 * @param uVersion Data layout version.
1010 */
1011static int apicR3LoadLegacyVCpuData(PVMCPU pVCpu, PSSMHANDLE pSSM, uint32_t uVersion)
1012{
1013 AssertReturn(uVersion <= APIC_SAVED_STATE_VERSION_VBOX_50, VERR_NOT_SUPPORTED);
1014
1015 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1016 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1017
1018 uint32_t uApicBaseLo;
1019 int rc = SSMR3GetU32(pSSM, &uApicBaseLo);
1020 AssertRCReturn(rc, rc);
1021 pApicCpu->uApicBaseMsr = uApicBaseLo;
1022 Log2(("APIC%u: apicR3LoadLegacyVCpuData: uApicBaseMsr=%#RX64\n", pVCpu->idCpu, pApicCpu->uApicBaseMsr));
1023
1024 switch (uVersion)
1025 {
1026 case APIC_SAVED_STATE_VERSION_VBOX_50:
1027 case APIC_SAVED_STATE_VERSION_VBOX_30:
1028 {
1029 uint32_t uApicId, uPhysApicId, uArbId;
1030 SSMR3GetU32(pSSM, &uApicId); pXApicPage->id.u8ApicId = uApicId;
1031 SSMR3GetU32(pSSM, &uPhysApicId); NOREF(uPhysApicId); /* PhysId == pVCpu->idCpu */
1032 SSMR3GetU32(pSSM, &uArbId); NOREF(uArbId); /* ArbID is & was unused. */
1033 break;
1034 }
1035
1036 case APIC_SAVED_STATE_VERSION_ANCIENT:
1037 {
1038 uint8_t uPhysApicId;
1039 SSMR3GetU8(pSSM, &pXApicPage->id.u8ApicId);
1040 SSMR3GetU8(pSSM, &uPhysApicId); NOREF(uPhysApicId); /* PhysId == pVCpu->idCpu */
1041 break;
1042 }
1043
1044 default:
1045 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1046 }
1047
1048 uint32_t u32Tpr;
1049 SSMR3GetU32(pSSM, &u32Tpr);
1050 pXApicPage->tpr.u8Tpr = u32Tpr & XAPIC_TPR_VALID;
1051
1052 SSMR3GetU32(pSSM, &pXApicPage->svr.all.u32Svr);
1053 SSMR3GetU8(pSSM, &pXApicPage->ldr.u.u8LogicalApicId);
1054
1055 uint8_t uDfr;
1056 SSMR3GetU8(pSSM, &uDfr);
1057 pXApicPage->dfr.u.u4Model = uDfr >> 4;
1058
1059 AssertCompile(RT_ELEMENTS(pXApicPage->isr.u) == 8);
1060 AssertCompile(RT_ELEMENTS(pXApicPage->tmr.u) == 8);
1061 AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 8);
1062 for (size_t i = 0; i < 8; i++)
1063 {
1064 SSMR3GetU32(pSSM, &pXApicPage->isr.u[i].u32Reg);
1065 SSMR3GetU32(pSSM, &pXApicPage->tmr.u[i].u32Reg);
1066 SSMR3GetU32(pSSM, &pXApicPage->irr.u[i].u32Reg);
1067 }
1068
1069 SSMR3GetU32(pSSM, &pXApicPage->lvt_timer.all.u32LvtTimer);
1070 SSMR3GetU32(pSSM, &pXApicPage->lvt_thermal.all.u32LvtThermal);
1071 SSMR3GetU32(pSSM, &pXApicPage->lvt_perf.all.u32LvtPerf);
1072 SSMR3GetU32(pSSM, &pXApicPage->lvt_lint0.all.u32LvtLint0);
1073 SSMR3GetU32(pSSM, &pXApicPage->lvt_lint1.all.u32LvtLint1);
1074 SSMR3GetU32(pSSM, &pXApicPage->lvt_error.all.u32LvtError);
1075
1076 SSMR3GetU32(pSSM, &pXApicPage->esr.all.u32Errors);
1077 SSMR3GetU32(pSSM, &pXApicPage->icr_lo.all.u32IcrLo);
1078 SSMR3GetU32(pSSM, &pXApicPage->icr_hi.all.u32IcrHi);
1079
1080 uint32_t u32TimerShift;
1081 SSMR3GetU32(pSSM, &pXApicPage->timer_dcr.all.u32DivideValue);
1082 SSMR3GetU32(pSSM, &u32TimerShift);
1083 /*
1084 * Old implementation may have left the timer shift uninitialized until
1085 * the timer configuration register was written. Unfortunately zero is
1086 * also a valid timer shift value, so we're just going to ignore it
1087 * completely. The shift count can always be derived from the DCR.
1088 * See @bugref{8245#c98}.
1089 */
1090 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
1091
1092 SSMR3GetU32(pSSM, &pXApicPage->timer_icr.u32InitialCount);
1093 SSMR3GetU64(pSSM, &pApicCpu->u64TimerInitial);
1094 uint64_t uNextTS;
1095 rc = SSMR3GetU64(pSSM, &uNextTS); AssertRCReturn(rc, rc);
1096 if (uNextTS >= pApicCpu->u64TimerInitial + ((pXApicPage->timer_icr.u32InitialCount + 1) << uTimerShift))
1097 pXApicPage->timer_ccr.u32CurrentCount = pXApicPage->timer_icr.u32InitialCount;
1098
1099 rc = TMR3TimerLoad(pApicCpu->pTimerR3, pSSM);
1100 AssertRCReturn(rc, rc);
1101 Assert(pApicCpu->uHintedTimerInitialCount == 0);
1102 Assert(pApicCpu->uHintedTimerShift == 0);
1103 if (TMTimerIsActive(pApicCpu->pTimerR3))
1104 {
1105 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1106 apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
1107 }
1108
1109 return rc;
1110}
1111
1112
1113/**
1114 * @copydoc FNSSMDEVSAVEEXEC
1115 */
1116static DECLCALLBACK(int) apicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1117{
1118 PVM pVM = PDMDevHlpGetVM(pDevIns);
1119 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
1120
1121 LogFlow(("APIC: apicR3SaveExec\n"));
1122
1123 /* Save per-VM data. */
1124 int rc = apicR3SaveVMData(pVM, pSSM);
1125 AssertRCReturn(rc, rc);
1126
1127 /* Save per-VCPU data.*/
1128 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1129 {
1130 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1131 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1132
1133 /* Update interrupts from the pending-interrupts bitmaps to the IRR. */
1134 APICUpdatePendingInterrupts(pVCpu);
1135
1136 /* Save the auxiliary data. */
1137 SSMR3PutU64(pSSM, pApicCpu->uApicBaseMsr);
1138 SSMR3PutU32(pSSM, pApicCpu->uEsrInternal);
1139
1140 /* Save the APIC page. */
1141 if (XAPIC_IN_X2APIC_MODE(pVCpu))
1142 SSMR3PutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
1143 else
1144 SSMR3PutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
1145
1146 /* Save the timer. */
1147 SSMR3PutU64(pSSM, pApicCpu->u64TimerInitial);
1148 TMR3TimerSave(pApicCpu->pTimerR3, pSSM);
1149
1150 /* Save the LINT0, LINT1 interrupt line states. */
1151 SSMR3PutBool(pSSM, pApicCpu->fActiveLint0);
1152 SSMR3PutBool(pSSM, pApicCpu->fActiveLint1);
1153
1154#if defined(APIC_FUZZY_SSM_COMPAT_TEST) || defined(DEBUG_ramshankar)
1155 apicR3DumpState(pVCpu, "Saved state", APIC_SAVED_STATE_VERSION);
1156#endif
1157 }
1158
1159#ifdef APIC_FUZZY_SSM_COMPAT_TEST
1160 /* The state is fuzzy, don't even bother trying to load the guest. */
1161 return VERR_INVALID_STATE;
1162#else
1163 return rc;
1164#endif
1165}
1166
1167
1168/**
1169 * @copydoc FNSSMDEVLOADEXEC
1170 */
1171static DECLCALLBACK(int) apicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1172{
1173 PVM pVM = PDMDevHlpGetVM(pDevIns);
1174
1175 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
1176 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
1177
1178 LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1179
1180 /* Weed out invalid versions. */
1181 if ( uVersion != APIC_SAVED_STATE_VERSION
1182 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_51_BETA2
1183 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_50
1184 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_30
1185 && uVersion != APIC_SAVED_STATE_VERSION_ANCIENT)
1186 {
1187 LogRel(("APIC: apicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1188 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1189 }
1190
1191 int rc = VINF_SUCCESS;
1192 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_30)
1193 {
1194 rc = apicR3LoadVMData(pVM, pSSM);
1195 AssertRCReturn(rc, rc);
1196
1197 if (uVersion == APIC_SAVED_STATE_VERSION)
1198 { /* Load any new additional per-VM data. */ }
1199 }
1200
1201 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1202 {
1203 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1204 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1205
1206 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_50)
1207 {
1208 /* Load the auxiliary data. */
1209 SSMR3GetU64(pSSM, (uint64_t *)&pApicCpu->uApicBaseMsr);
1210 SSMR3GetU32(pSSM, &pApicCpu->uEsrInternal);
1211
1212 /* Load the APIC page. */
1213 if (XAPIC_IN_X2APIC_MODE(pVCpu))
1214 SSMR3GetStruct(pSSM, pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
1215 else
1216 SSMR3GetStruct(pSSM, pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
1217
1218 /* Load the timer. */
1219 rc = SSMR3GetU64(pSSM, &pApicCpu->u64TimerInitial); AssertRCReturn(rc, rc);
1220 rc = TMR3TimerLoad(pApicCpu->pTimerR3, pSSM); AssertRCReturn(rc, rc);
1221 Assert(pApicCpu->uHintedTimerShift == 0);
1222 Assert(pApicCpu->uHintedTimerInitialCount == 0);
1223 if (TMTimerIsActive(pApicCpu->pTimerR3))
1224 {
1225 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
1226 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1227 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
1228 apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
1229 }
1230
1231 /* Load the LINT0, LINT1 interrupt line states. */
1232 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_51_BETA2)
1233 {
1234 SSMR3GetBool(pSSM, (bool *)&pApicCpu->fActiveLint0);
1235 SSMR3GetBool(pSSM, (bool *)&pApicCpu->fActiveLint1);
1236 }
1237 }
1238 else
1239 {
1240 rc = apicR3LoadLegacyVCpuData(pVCpu, pSSM, uVersion);
1241 AssertRCReturn(rc, rc);
1242 }
1243
1244 /*
1245 * Check that we're still good wrt restored data, then tell CPUM about the current CPUID[1].EDX[9] visibility.
1246 */
1247 rc = SSMR3HandleGetStatus(pSSM);
1248 AssertRCReturn(rc, rc);
1249 CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, RT_BOOL(pApicCpu->uApicBaseMsr & MSR_IA32_APICBASE_EN));
1250
1251#if defined(APIC_FUZZY_SSM_COMPAT_TEST) || defined(DEBUG_ramshankar)
1252 apicR3DumpState(pVCpu, "Loaded state", uVersion);
1253#endif
1254 }
1255
1256 return rc;
1257}
1258
1259
1260/**
1261 * The timer callback.
1262 *
1263 * @param pDevIns The device instance.
1264 * @param pTimer The timer handle.
1265 * @param pvUser Opaque pointer to the VMCPU.
1266 *
1267 * @thread Any.
1268 * @remarks Currently this function is invoked on the last EMT, see @c
1269 * idTimerCpu in tmR3TimerCallback(). However, the code does -not-
1270 * rely on this and is designed to work with being invoked on any
1271 * thread.
1272 */
1273static DECLCALLBACK(void) apicR3TimerCallback(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1274{
1275 PVMCPU pVCpu = (PVMCPU)pvUser;
1276 Assert(TMTimerIsLockOwner(pTimer));
1277 Assert(pVCpu);
1278 LogFlow(("APIC%u: apicR3TimerCallback\n", pVCpu->idCpu));
1279 RT_NOREF2(pDevIns, pTimer);
1280
1281 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1282 uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
1283#ifdef VBOX_WITH_STATISTICS
1284 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1285 STAM_COUNTER_INC(&pApicCpu->StatTimerCallback);
1286#endif
1287 if (!XAPIC_LVT_IS_MASKED(uLvtTimer))
1288 {
1289 uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
1290 Log2(("APIC%u: apicR3TimerCallback: Raising timer interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
1291 apicPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE, 0 /* uSrcTag */);
1292 }
1293
1294 XAPICTIMERMODE enmTimerMode = XAPIC_LVT_GET_TIMER_MODE(uLvtTimer);
1295 switch (enmTimerMode)
1296 {
1297 case XAPICTIMERMODE_PERIODIC:
1298 {
1299 /* The initial-count register determines if the periodic timer is re-armed. */
1300 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1301 pXApicPage->timer_ccr.u32CurrentCount = uInitialCount;
1302 if (uInitialCount)
1303 {
1304 Log2(("APIC%u: apicR3TimerCallback: Re-arming timer. uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
1305 apicStartTimer(pVCpu, uInitialCount);
1306 }
1307 break;
1308 }
1309
1310 case XAPICTIMERMODE_ONESHOT:
1311 {
1312 pXApicPage->timer_ccr.u32CurrentCount = 0;
1313 break;
1314 }
1315
1316 case XAPICTIMERMODE_TSC_DEADLINE:
1317 {
1318 /** @todo implement TSC deadline. */
1319 AssertMsgFailed(("APIC: TSC deadline mode unimplemented\n"));
1320 break;
1321 }
1322 }
1323}
1324
1325
1326/**
1327 * @interface_method_impl{PDMDEVREG,pfnReset}
1328 */
1329static DECLCALLBACK(void) apicR3Reset(PPDMDEVINS pDevIns)
1330{
1331 PVM pVM = PDMDevHlpGetVM(pDevIns);
1332 VM_ASSERT_EMT0(pVM);
1333 VM_ASSERT_IS_NOT_RUNNING(pVM);
1334
1335 LogFlow(("APIC: apicR3Reset\n"));
1336
1337 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1338 {
1339 PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
1340 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpuDest);
1341
1342 if (TMTimerIsActive(pApicCpu->pTimerR3))
1343 TMTimerStop(pApicCpu->pTimerR3);
1344
1345 apicR3ResetCpu(pVCpuDest, true /* fResetApicBaseMsr */);
1346
1347 /* Clear the interrupt pending force flag. */
1348 apicClearInterruptFF(pVCpuDest, PDMAPICIRQ_HARDWARE);
1349 }
1350}
1351
1352
1353/**
1354 * @interface_method_impl{PDMDEVREG,pfnRelocate}
1355 */
1356static DECLCALLBACK(void) apicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1357{
1358 PVM pVM = PDMDevHlpGetVM(pDevIns);
1359 PAPIC pApic = VM_TO_APIC(pVM);
1360 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1361
1362 LogFlow(("APIC: apicR3Relocate: pVM=%p pDevIns=%p offDelta=%RGi\n", pVM, pDevIns, offDelta));
1363
1364 pApicDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1365
1366 pApic->pApicDevRC = PDMINS_2_DATA_RCPTR(pDevIns);
1367 pApic->pvApicPibRC += offDelta;
1368
1369 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1370 {
1371 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1372 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1373 pApicCpu->pTimerRC = TMTimerRCPtr(pApicCpu->pTimerR3);
1374
1375 pApicCpu->pvApicPageRC += offDelta;
1376 pApicCpu->pvApicPibRC += offDelta;
1377 Log2(("APIC%u: apicR3Relocate: APIC PIB at %RGv\n", pVCpu->idCpu, pApicCpu->pvApicPibRC));
1378 }
1379}
1380
1381
1382/**
1383 * Terminates the APIC state.
1384 *
1385 * @param pVM The cross context VM structure.
1386 */
1387static void apicR3TermState(PVM pVM)
1388{
1389 PAPIC pApic = VM_TO_APIC(pVM);
1390 LogFlow(("APIC: apicR3TermState: pVM=%p\n", pVM));
1391
1392 /* Unmap and free the PIB. */
1393 if (pApic->pvApicPibR3 != NIL_RTR3PTR)
1394 {
1395 size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
1396 if (cPages == 1)
1397 SUPR3PageFreeEx(pApic->pvApicPibR3, cPages);
1398 else
1399 SUPR3ContFree(pApic->pvApicPibR3, cPages);
1400 pApic->pvApicPibR3 = NIL_RTR3PTR;
1401 pApic->pvApicPibR0 = NIL_RTR0PTR;
1402 pApic->pvApicPibRC = NIL_RTRCPTR;
1403 }
1404
1405 /* Unmap and free the virtual-APIC pages. */
1406 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1407 {
1408 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1409 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1410
1411 pApicCpu->pvApicPibR3 = NIL_RTR3PTR;
1412 pApicCpu->pvApicPibR0 = NIL_RTR0PTR;
1413 pApicCpu->pvApicPibRC = NIL_RTRCPTR;
1414
1415 if (pApicCpu->pvApicPageR3 != NIL_RTR3PTR)
1416 {
1417 SUPR3PageFreeEx(pApicCpu->pvApicPageR3, 1 /* cPages */);
1418 pApicCpu->pvApicPageR3 = NIL_RTR3PTR;
1419 pApicCpu->pvApicPageR0 = NIL_RTR0PTR;
1420 pApicCpu->pvApicPageRC = NIL_RTRCPTR;
1421 }
1422 }
1423}
1424
1425
1426/**
1427 * Initializes the APIC state.
1428 *
1429 * @returns VBox status code.
1430 * @param pVM The cross context VM structure.
1431 */
1432static int apicR3InitState(PVM pVM)
1433{
1434 PAPIC pApic = VM_TO_APIC(pVM);
1435 LogFlow(("APIC: apicR3InitState: pVM=%p\n", pVM));
1436
1437 /* With hardware virtualization, we don't need to map the APIC in GC. */
1438 bool const fNeedsGCMapping = VM_IS_RAW_MODE_ENABLED(pVM);
1439
1440 /*
1441 * Allocate and map the pending-interrupt bitmap (PIB).
1442 *
1443 * We allocate all the VCPUs' PIBs contiguously in order to save space as
1444 * physically contiguous allocations are rounded to a multiple of page size.
1445 */
1446 Assert(pApic->pvApicPibR3 == NIL_RTR3PTR);
1447 Assert(pApic->pvApicPibR0 == NIL_RTR0PTR);
1448 Assert(pApic->pvApicPibRC == NIL_RTRCPTR);
1449 pApic->cbApicPib = RT_ALIGN_Z(pVM->cCpus * sizeof(APICPIB), PAGE_SIZE);
1450 size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
1451 if (cPages == 1)
1452 {
1453 SUPPAGE SupApicPib;
1454 RT_ZERO(SupApicPib);
1455 SupApicPib.Phys = NIL_RTHCPHYS;
1456 int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, &pApic->pvApicPibR3, &pApic->pvApicPibR0, &SupApicPib);
1457 if (RT_SUCCESS(rc))
1458 {
1459 pApic->HCPhysApicPib = SupApicPib.Phys;
1460 AssertLogRelReturn(pApic->pvApicPibR3, VERR_INTERNAL_ERROR);
1461 }
1462 else
1463 {
1464 LogRel(("APIC: Failed to allocate %u bytes for the pending-interrupt bitmap, rc=%Rrc\n", pApic->cbApicPib, rc));
1465 return rc;
1466 }
1467 }
1468 else
1469 pApic->pvApicPibR3 = SUPR3ContAlloc(cPages, &pApic->pvApicPibR0, &pApic->HCPhysApicPib);
1470
1471 if (pApic->pvApicPibR3)
1472 {
1473 AssertLogRelReturn(pApic->pvApicPibR0 != NIL_RTR0PTR, VERR_INTERNAL_ERROR);
1474 AssertLogRelReturn(pApic->HCPhysApicPib != NIL_RTHCPHYS, VERR_INTERNAL_ERROR);
1475
1476 /* Initialize the PIB. */
1477 RT_BZERO(pApic->pvApicPibR3, pApic->cbApicPib);
1478
1479 /* Map the PIB into GC. */
1480 if (fNeedsGCMapping)
1481 {
1482 pApic->pvApicPibRC = NIL_RTRCPTR;
1483 int rc = MMR3HyperMapHCPhys(pVM, pApic->pvApicPibR3, NIL_RTR0PTR, pApic->HCPhysApicPib, pApic->cbApicPib,
1484 "APIC PIB", (PRTGCPTR)&pApic->pvApicPibRC);
1485 if (RT_FAILURE(rc))
1486 {
1487 LogRel(("APIC: Failed to map %u bytes for the pending-interrupt bitmap into GC, rc=%Rrc\n", pApic->cbApicPib,
1488 rc));
1489 apicR3TermState(pVM);
1490 return rc;
1491 }
1492
1493 AssertLogRelReturn(pApic->pvApicPibRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
1494 }
1495
1496 /*
1497 * Allocate the map the virtual-APIC pages.
1498 */
1499 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1500 {
1501 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1502 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1503
1504 SUPPAGE SupApicPage;
1505 RT_ZERO(SupApicPage);
1506 SupApicPage.Phys = NIL_RTHCPHYS;
1507
1508 Assert(pVCpu->idCpu == idCpu);
1509 Assert(pApicCpu->pvApicPageR3 == NIL_RTR0PTR);
1510 Assert(pApicCpu->pvApicPageR0 == NIL_RTR0PTR);
1511 Assert(pApicCpu->pvApicPageRC == NIL_RTRCPTR);
1512 AssertCompile(sizeof(XAPICPAGE) == PAGE_SIZE);
1513 pApicCpu->cbApicPage = sizeof(XAPICPAGE);
1514 int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, &pApicCpu->pvApicPageR3, &pApicCpu->pvApicPageR0,
1515 &SupApicPage);
1516 if (RT_SUCCESS(rc))
1517 {
1518 AssertLogRelReturn(pApicCpu->pvApicPageR3 != NIL_RTR3PTR, VERR_INTERNAL_ERROR);
1519 AssertLogRelReturn(pApicCpu->HCPhysApicPage != NIL_RTHCPHYS, VERR_INTERNAL_ERROR);
1520 pApicCpu->HCPhysApicPage = SupApicPage.Phys;
1521
1522 /* Map the virtual-APIC page into GC. */
1523 if (fNeedsGCMapping)
1524 {
1525 rc = MMR3HyperMapHCPhys(pVM, pApicCpu->pvApicPageR3, NIL_RTR0PTR, pApicCpu->HCPhysApicPage,
1526 pApicCpu->cbApicPage, "APIC", (PRTGCPTR)&pApicCpu->pvApicPageRC);
1527 if (RT_FAILURE(rc))
1528 {
1529 LogRel(("APIC%u: Failed to map %u bytes for the virtual-APIC page into GC, rc=%Rrc", idCpu,
1530 pApicCpu->cbApicPage, rc));
1531 apicR3TermState(pVM);
1532 return rc;
1533 }
1534
1535 AssertLogRelReturn(pApicCpu->pvApicPageRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
1536 }
1537
1538 /* Associate the per-VCPU PIB pointers to the per-VM PIB mapping. */
1539 uint32_t const offApicPib = idCpu * sizeof(APICPIB);
1540 pApicCpu->pvApicPibR0 = (RTR0PTR)((RTR0UINTPTR)pApic->pvApicPibR0 + offApicPib);
1541 pApicCpu->pvApicPibR3 = (RTR3PTR)((RTR3UINTPTR)pApic->pvApicPibR3 + offApicPib);
1542 if (fNeedsGCMapping)
1543 pApicCpu->pvApicPibRC = (RTRCPTR)((RTRCUINTPTR)pApic->pvApicPibRC + offApicPib);
1544
1545 /* Initialize the virtual-APIC state. */
1546 RT_BZERO(pApicCpu->pvApicPageR3, pApicCpu->cbApicPage);
1547 apicR3ResetCpu(pVCpu, true /* fResetApicBaseMsr */);
1548
1549#ifdef DEBUG_ramshankar
1550 Assert(pApicCpu->pvApicPibR3 != NIL_RTR3PTR);
1551 Assert(pApicCpu->pvApicPibR0 != NIL_RTR0PTR);
1552 Assert(!fNeedsGCMapping || pApicCpu->pvApicPibRC != NIL_RTRCPTR);
1553 Assert(pApicCpu->pvApicPageR3 != NIL_RTR3PTR);
1554 Assert(pApicCpu->pvApicPageR0 != NIL_RTR0PTR);
1555 Assert(!fNeedsGCMapping || pApicCpu->pvApicPageRC != NIL_RTRCPTR);
1556 Assert(!fNeedsGCMapping || pApic->pvApicPibRC == pVM->aCpus[0].apic.s.pvApicPibRC);
1557#endif
1558 }
1559 else
1560 {
1561 LogRel(("APIC%u: Failed to allocate %u bytes for the virtual-APIC page, rc=%Rrc\n", idCpu, pApicCpu->cbApicPage, rc));
1562 apicR3TermState(pVM);
1563 return rc;
1564 }
1565 }
1566
1567#ifdef DEBUG_ramshankar
1568 Assert(pApic->pvApicPibR3 != NIL_RTR3PTR);
1569 Assert(pApic->pvApicPibR0 != NIL_RTR0PTR);
1570 Assert(!fNeedsGCMapping || pApic->pvApicPibRC != NIL_RTRCPTR);
1571#endif
1572 return VINF_SUCCESS;
1573 }
1574
1575 LogRel(("APIC: Failed to allocate %u bytes of physically contiguous memory for the pending-interrupt bitmap\n",
1576 pApic->cbApicPib));
1577 return VERR_NO_MEMORY;
1578}
1579
1580
1581/**
1582 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1583 */
1584static DECLCALLBACK(int) apicR3Destruct(PPDMDEVINS pDevIns)
1585{
1586 PVM pVM = PDMDevHlpGetVM(pDevIns);
1587 LogFlow(("APIC: apicR3Destruct: pVM=%p\n", pVM));
1588
1589 apicR3TermState(pVM);
1590 return VINF_SUCCESS;
1591}
1592
1593
1594/**
1595 * @interface_method_impl{PDMDEVREG,pfnInitComplete}
1596 */
1597static DECLCALLBACK(int) apicR3InitComplete(PPDMDEVINS pDevIns)
1598{
1599 PVM pVM = PDMDevHlpGetVM(pDevIns);
1600 PAPIC pApic = VM_TO_APIC(pVM);
1601
1602 /*
1603 * Init APIC settings that rely on HM and CPUM configurations.
1604 */
1605 CPUMCPUIDLEAF CpuLeaf;
1606 int rc = CPUMR3CpuIdGetLeaf(pVM, &CpuLeaf, 1, 0);
1607 AssertRCReturn(rc, rc);
1608
1609 pApic->fSupportsTscDeadline = RT_BOOL(CpuLeaf.uEcx & X86_CPUID_FEATURE_ECX_TSCDEADL);
1610 pApic->fPostedIntrsEnabled = HMR3IsPostedIntrsEnabled(pVM->pUVM);
1611 pApic->fVirtApicRegsEnabled = HMR3IsVirtApicRegsEnabled(pVM->pUVM);
1612
1613 LogRel(("APIC: fPostedIntrsEnabled=%RTbool fVirtApicRegsEnabled=%RTbool fSupportsTscDeadline=%RTbool\n",
1614 pApic->fPostedIntrsEnabled, pApic->fVirtApicRegsEnabled, pApic->fSupportsTscDeadline));
1615
1616 return VINF_SUCCESS;
1617}
1618
1619
1620/**
1621 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1622 */
1623static DECLCALLBACK(int) apicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1624{
1625 /*
1626 * Validate inputs.
1627 */
1628 Assert(iInstance == 0); NOREF(iInstance);
1629 Assert(pDevIns);
1630
1631 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1632 PVM pVM = PDMDevHlpGetVM(pDevIns);
1633 PAPIC pApic = VM_TO_APIC(pVM);
1634
1635 /*
1636 * Init the data.
1637 */
1638 pApicDev->pDevInsR3 = pDevIns;
1639 pApicDev->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1640 pApicDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1641
1642 pApic->pApicDevR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1643 pApic->pApicDevR3 = (PAPICDEV)PDMINS_2_DATA_R3PTR(pDevIns);
1644 pApic->pApicDevRC = PDMINS_2_DATA_RCPTR(pDevIns);
1645
1646 /*
1647 * Validate APIC settings.
1648 */
1649 if (!CFGMR3AreValuesValid(pCfg, "RZEnabled\0"
1650 "Mode\0"
1651 "IOAPIC\0"
1652 "NumCPUs\0"))
1653 {
1654 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1655 N_("APIC configuration error: unknown option specified"));
1656 }
1657
1658 int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pApic->fRZEnabled, true);
1659 AssertLogRelRCReturn(rc, rc);
1660
1661 rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &pApic->fIoApicPresent, true);
1662 AssertLogRelRCReturn(rc, rc);
1663
1664 /* Max APIC feature level. */
1665 uint8_t uMaxMode;
1666 rc = CFGMR3QueryU8Def(pCfg, "Mode", &uMaxMode, PDMAPICMODE_APIC);
1667 AssertLogRelRCReturn(rc, rc);
1668 switch ((PDMAPICMODE)uMaxMode)
1669 {
1670 case PDMAPICMODE_NONE:
1671 LogRel(("APIC: APIC maximum mode configured as 'None', effectively disabled/not-present!\n"));
1672 case PDMAPICMODE_APIC:
1673 case PDMAPICMODE_X2APIC:
1674 break;
1675 default:
1676 return VMR3SetError(pVM->pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, "APIC mode %d unknown.", uMaxMode);
1677 }
1678 pApic->enmMaxMode = (PDMAPICMODE)uMaxMode;
1679
1680 /*
1681 * Disable automatic PDM locking for this device.
1682 */
1683 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1684 AssertRCReturn(rc, rc);
1685
1686 /*
1687 * Register the APIC with PDM.
1688 */
1689 rc = PDMDevHlpAPICRegister(pDevIns);
1690 AssertLogRelRCReturn(rc, rc);
1691
1692 /*
1693 * Initialize the APIC state.
1694 */
1695 if (pApic->enmMaxMode == PDMAPICMODE_X2APIC)
1696 {
1697 rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic);
1698 AssertLogRelRCReturn(rc, rc);
1699 }
1700 else
1701 {
1702 /* We currently don't have a function to remove the range, so we register an range which will cause a #GP. */
1703 rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic_Invalid);
1704 AssertLogRelRCReturn(rc, rc);
1705 }
1706
1707 /* Tell CPUM about the APIC feature level so it can adjust APICBASE MSR GP mask and CPUID bits. */
1708 apicR3SetCpuIdFeatureLevel(pVM, pApic->enmMaxMode);
1709 /* Finally, initialize the state. */
1710 rc = apicR3InitState(pVM);
1711 AssertRCReturn(rc, rc);
1712
1713 /*
1714 * Register the MMIO range.
1715 */
1716 PAPICCPU pApicCpu0 = VMCPU_TO_APICCPU(&pVM->aCpus[0]);
1717 RTGCPHYS GCPhysApicBase = MSR_IA32_APICBASE_GET_ADDR(pApicCpu0->uApicBaseMsr);
1718
1719 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NULL /* pvUser */,
1720 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED,
1721 apicWriteMmio, apicReadMmio, "APIC");
1722 if (RT_FAILURE(rc))
1723 return rc;
1724
1725 if (pApic->fRZEnabled)
1726 {
1727 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NIL_RTRCPTR /*pvUser*/,
1728 "apicWriteMmio", "apicReadMmio");
1729 if (RT_FAILURE(rc))
1730 return rc;
1731
1732 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NIL_RTR0PTR /*pvUser*/,
1733 "apicWriteMmio", "apicReadMmio");
1734 if (RT_FAILURE(rc))
1735 return rc;
1736 }
1737
1738 /*
1739 * Create the APIC timers.
1740 */
1741 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1742 {
1743 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1744 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1745 RTStrPrintf(&pApicCpu->szTimerDesc[0], sizeof(pApicCpu->szTimerDesc), "APIC Timer %u", pVCpu->idCpu);
1746 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicR3TimerCallback, pVCpu, TMTIMER_FLAGS_NO_CRIT_SECT,
1747 pApicCpu->szTimerDesc, &pApicCpu->pTimerR3);
1748 if (RT_SUCCESS(rc))
1749 {
1750 pApicCpu->pTimerR0 = TMTimerR0Ptr(pApicCpu->pTimerR3);
1751 pApicCpu->pTimerRC = TMTimerRCPtr(pApicCpu->pTimerR3);
1752 }
1753 else
1754 return rc;
1755 }
1756
1757 /*
1758 * Register saved state callbacks.
1759 */
1760 rc = PDMDevHlpSSMRegister3(pDevIns, APIC_SAVED_STATE_VERSION, sizeof(*pApicDev), NULL /*pfnLiveExec*/, apicR3SaveExec,
1761 apicR3LoadExec);
1762 if (RT_FAILURE(rc))
1763 return rc;
1764
1765 /*
1766 * Register debugger info callbacks.
1767 *
1768 * We use separate callbacks rather than arguments so they can also be
1769 * dumped in an automated fashion while collecting crash diagnostics and
1770 * not just used during live debugging via the VM debugger.
1771 */
1772 rc = DBGFR3InfoRegisterInternalEx(pVM, "apic", "Dumps APIC basic information.", apicR3Info, DBGFINFO_FLAGS_ALL_EMTS);
1773 rc |= DBGFR3InfoRegisterInternalEx(pVM, "apiclvt", "Dumps APIC LVT information.", apicR3InfoLvt, DBGFINFO_FLAGS_ALL_EMTS);
1774 rc |= DBGFR3InfoRegisterInternalEx(pVM, "apictimer", "Dumps APIC timer information.", apicR3InfoTimer, DBGFINFO_FLAGS_ALL_EMTS);
1775 AssertRCReturn(rc, rc);
1776
1777#ifdef VBOX_WITH_STATISTICS
1778 /*
1779 * Statistics.
1780 */
1781#define APIC_REG_COUNTER(a_Reg, a_Desc, a_Key) \
1782 do { \
1783 rc = STAMR3RegisterF(pVM, a_Reg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, a_Desc, a_Key, idCpu); \
1784 AssertRCReturn(rc, rc); \
1785 } while(0)
1786
1787#define APIC_PROF_COUNTER(a_Reg, a_Desc, a_Key) \
1788 do { \
1789 rc = STAMR3RegisterF(pVM, a_Reg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, a_Desc, a_Key, \
1790 idCpu); \
1791 AssertRCReturn(rc, rc); \
1792 } while(0)
1793
1794 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1795 {
1796 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1797 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1798
1799 APIC_REG_COUNTER(&pApicCpu->StatMmioReadRZ, "Number of APIC MMIO reads in RZ.", "/Devices/APIC/%u/RZ/MmioRead");
1800 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteRZ, "Number of APIC MMIO writes in RZ.", "/Devices/APIC/%u/RZ/MmioWrite");
1801 APIC_REG_COUNTER(&pApicCpu->StatMsrReadRZ, "Number of APIC MSR reads in RZ.", "/Devices/APIC/%u/RZ/MsrRead");
1802 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteRZ, "Number of APIC MSR writes in RZ.", "/Devices/APIC/%u/RZ/MsrWrite");
1803
1804 APIC_REG_COUNTER(&pApicCpu->StatMmioReadR3, "Number of APIC MMIO reads in R3.", "/Devices/APIC/%u/R3/MmioReadR3");
1805 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteR3, "Number of APIC MMIO writes in R3.", "/Devices/APIC/%u/R3/MmioWriteR3");
1806 APIC_REG_COUNTER(&pApicCpu->StatMsrReadR3, "Number of APIC MSR reads in R3.", "/Devices/APIC/%u/R3/MsrReadR3");
1807 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteR3, "Number of APIC MSR writes in R3.", "/Devices/APIC/%u/R3/MsrWriteR3");
1808
1809 APIC_PROF_COUNTER(&pApicCpu->StatUpdatePendingIntrs, "Profiling of APICUpdatePendingInterrupts",
1810 "/PROF/CPU%d/APIC/UpdatePendingInterrupts");
1811 APIC_PROF_COUNTER(&pApicCpu->StatPostIntr, "Profiling of APICPostInterrupt", "/PROF/CPU%d/APIC/PostInterrupt");
1812
1813 APIC_REG_COUNTER(&pApicCpu->StatPostIntrAlreadyPending, "Number of times an interrupt is already pending.",
1814 "/Devices/APIC/%u/PostInterruptAlreadyPending");
1815 APIC_REG_COUNTER(&pApicCpu->StatTimerCallback, "Number of times the timer callback is invoked.",
1816 "/Devices/APIC/%u/TimerCallback");
1817
1818 APIC_REG_COUNTER(&pApicCpu->StatTprWrite, "Number of TPR writes.", "/Devices/APIC/%u/TprWrite");
1819 APIC_REG_COUNTER(&pApicCpu->StatTprRead, "Number of TPR reads.", "/Devices/APIC/%u/TprRead");
1820 APIC_REG_COUNTER(&pApicCpu->StatEoiWrite, "Number of EOI writes.", "/Devices/APIC/%u/EoiWrite");
1821 APIC_REG_COUNTER(&pApicCpu->StatMaskedByTpr, "Number of times TPR masks an interrupt in apicGetInterrupt.",
1822 "/Devices/APIC/%u/MaskedByTpr");
1823 APIC_REG_COUNTER(&pApicCpu->StatMaskedByPpr, "Number of times PPR masks an interrupt in apicGetInterrupt.",
1824 "/Devices/APIC/%u/MaskedByPpr");
1825 APIC_REG_COUNTER(&pApicCpu->StatTimerIcrWrite, "Number of times the timer ICR is written.",
1826 "/Devices/APIC/%u/TimerIcrWrite");
1827 APIC_REG_COUNTER(&pApicCpu->StatIcrLoWrite, "Number of times the ICR Lo (send IPI) is written.",
1828 "/Devices/APIC/%u/IcrLoWrite");
1829 APIC_REG_COUNTER(&pApicCpu->StatIcrHiWrite, "Number of times the ICR Hi is written.",
1830 "/Devices/APIC/%u/IcrHiWrite");
1831 APIC_REG_COUNTER(&pApicCpu->StatIcrFullWrite, "Number of times the ICR full (send IPI, x2APIC) is written.",
1832 "/Devices/APIC/%u/IcrFullWrite");
1833 }
1834# undef APIC_PROF_COUNTER
1835# undef APIC_REG_ACCESS_COUNTER
1836#endif
1837
1838 return VINF_SUCCESS;
1839}
1840
1841
1842/**
1843 * APIC device registration structure.
1844 */
1845const PDMDEVREG g_DeviceAPIC =
1846{
1847 /* u32Version */
1848 PDM_DEVREG_VERSION,
1849 /* szName */
1850 "apic",
1851 /* szRCMod */
1852 "VMMRC.rc",
1853 /* szR0Mod */
1854 "VMMR0.r0",
1855 /* pszDescription */
1856 "Advanced Programmable Interrupt Controller",
1857 /* fFlags */
1858 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36
1859 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
1860 /* fClass */
1861 PDM_DEVREG_CLASS_PIC,
1862 /* cMaxInstances */
1863 1,
1864 /* cbInstance */
1865 sizeof(APICDEV),
1866 /* pfnConstruct */
1867 apicR3Construct,
1868 /* pfnDestruct */
1869 apicR3Destruct,
1870 /* pfnRelocate */
1871 apicR3Relocate,
1872 /* pfnMemSetup */
1873 NULL,
1874 /* pfnPowerOn */
1875 NULL,
1876 /* pfnReset */
1877 apicR3Reset,
1878 /* pfnSuspend */
1879 NULL,
1880 /* pfnResume */
1881 NULL,
1882 /* pfnAttach */
1883 NULL,
1884 /* pfnDetach */
1885 NULL,
1886 /* pfnQueryInterface. */
1887 NULL,
1888 /* pfnInitComplete */
1889 apicR3InitComplete,
1890 /* pfnPowerOff */
1891 NULL,
1892 /* pfnSoftReset */
1893 NULL,
1894 /* u32VersionEnd */
1895 PDM_DEVREG_VERSION
1896};
1897
1898#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1899
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