VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/APIC.cpp@ 69222

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1/* $Id: APIC.cpp 69111 2017-10-17 14:26:02Z vboxsync $ */
2/** @file
3 * APIC - Advanced Programmable Interrupt Controller.
4 */
5
6/*
7 * Copyright (C) 2016-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_APIC
23#include <VBox/log.h>
24#include "APICInternal.h"
25#include <VBox/vmm/cpum.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/ssm.h>
30#include <VBox/vmm/vm.h>
31
32
33#ifndef VBOX_DEVICE_STRUCT_TESTCASE
34
35
36/*********************************************************************************************************************************
37* Defined Constants And Macros *
38*********************************************************************************************************************************/
39/** The current APIC saved state version. */
40#define APIC_SAVED_STATE_VERSION 5
41/** VirtualBox 5.1 beta2 - pre fActiveLintX. */
42#define APIC_SAVED_STATE_VERSION_VBOX_51_BETA2 4
43/** The saved state version used by VirtualBox 5.0 and
44 * earlier. */
45#define APIC_SAVED_STATE_VERSION_VBOX_50 3
46/** The saved state version used by VirtualBox v3 and earlier.
47 * This does not include the config. */
48#define APIC_SAVED_STATE_VERSION_VBOX_30 2
49/** Some ancient version... */
50#define APIC_SAVED_STATE_VERSION_ANCIENT 1
51
52#ifdef VBOX_WITH_STATISTICS
53# define X2APIC_MSRRANGE(a_uFirst, a_uLast, a_szName) \
54 { (a_uFirst), (a_uLast), kCpumMsrRdFn_Ia32X2ApicN, kCpumMsrWrFn_Ia32X2ApicN, 0, 0, 0, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
55# define X2APIC_MSRRANGE_INVALID(a_uFirst, a_uLast, a_szName) \
56 { (a_uFirst), (a_uLast), kCpumMsrRdFn_WriteOnly, kCpumMsrWrFn_ReadOnly, 0, 0, 0, 0, UINT64_MAX /*fWrGpMask*/, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
57#else
58# define X2APIC_MSRRANGE(a_uFirst, a_uLast, a_szName) \
59 { (a_uFirst), (a_uLast), kCpumMsrRdFn_Ia32X2ApicN, kCpumMsrWrFn_Ia32X2ApicN, 0, 0, 0, 0, 0, a_szName }
60# define X2APIC_MSRRANGE_INVALID(a_uFirst, a_uLast, a_szName) \
61 { (a_uFirst), (a_uLast), kCpumMsrRdFn_WriteOnly, kCpumMsrWrFn_ReadOnly, 0, 0, 0, 0, UINT64_MAX /*fWrGpMask*/, a_szName }
62#endif
63
64
65/*********************************************************************************************************************************
66* Global Variables *
67*********************************************************************************************************************************/
68/**
69 * MSR range supported by the x2APIC.
70 * See Intel spec. 10.12.2 "x2APIC Register Availability".
71 */
72static CPUMMSRRANGE const g_MsrRange_x2Apic = X2APIC_MSRRANGE(MSR_IA32_X2APIC_START, MSR_IA32_X2APIC_END, "x2APIC range");
73static CPUMMSRRANGE const g_MsrRange_x2Apic_Invalid = X2APIC_MSRRANGE_INVALID(MSR_IA32_X2APIC_START, MSR_IA32_X2APIC_END, "x2APIC range invalid");
74#undef X2APIC_MSRRANGE
75#undef X2APIC_MSRRANGE_GP
76
77/** Saved state field descriptors for XAPICPAGE. */
78static const SSMFIELD g_aXApicPageFields[] =
79{
80 SSMFIELD_ENTRY( XAPICPAGE, id.u8ApicId),
81 SSMFIELD_ENTRY( XAPICPAGE, version.all.u32Version),
82 SSMFIELD_ENTRY( XAPICPAGE, tpr.u8Tpr),
83 SSMFIELD_ENTRY( XAPICPAGE, apr.u8Apr),
84 SSMFIELD_ENTRY( XAPICPAGE, ppr.u8Ppr),
85 SSMFIELD_ENTRY( XAPICPAGE, ldr.all.u32Ldr),
86 SSMFIELD_ENTRY( XAPICPAGE, dfr.all.u32Dfr),
87 SSMFIELD_ENTRY( XAPICPAGE, svr.all.u32Svr),
88 SSMFIELD_ENTRY( XAPICPAGE, isr.u[0].u32Reg),
89 SSMFIELD_ENTRY( XAPICPAGE, isr.u[1].u32Reg),
90 SSMFIELD_ENTRY( XAPICPAGE, isr.u[2].u32Reg),
91 SSMFIELD_ENTRY( XAPICPAGE, isr.u[3].u32Reg),
92 SSMFIELD_ENTRY( XAPICPAGE, isr.u[4].u32Reg),
93 SSMFIELD_ENTRY( XAPICPAGE, isr.u[5].u32Reg),
94 SSMFIELD_ENTRY( XAPICPAGE, isr.u[6].u32Reg),
95 SSMFIELD_ENTRY( XAPICPAGE, isr.u[7].u32Reg),
96 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[0].u32Reg),
97 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[1].u32Reg),
98 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[2].u32Reg),
99 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[3].u32Reg),
100 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[4].u32Reg),
101 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[5].u32Reg),
102 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[6].u32Reg),
103 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[7].u32Reg),
104 SSMFIELD_ENTRY( XAPICPAGE, irr.u[0].u32Reg),
105 SSMFIELD_ENTRY( XAPICPAGE, irr.u[1].u32Reg),
106 SSMFIELD_ENTRY( XAPICPAGE, irr.u[2].u32Reg),
107 SSMFIELD_ENTRY( XAPICPAGE, irr.u[3].u32Reg),
108 SSMFIELD_ENTRY( XAPICPAGE, irr.u[4].u32Reg),
109 SSMFIELD_ENTRY( XAPICPAGE, irr.u[5].u32Reg),
110 SSMFIELD_ENTRY( XAPICPAGE, irr.u[6].u32Reg),
111 SSMFIELD_ENTRY( XAPICPAGE, irr.u[7].u32Reg),
112 SSMFIELD_ENTRY( XAPICPAGE, esr.all.u32Errors),
113 SSMFIELD_ENTRY( XAPICPAGE, icr_lo.all.u32IcrLo),
114 SSMFIELD_ENTRY( XAPICPAGE, icr_hi.all.u32IcrHi),
115 SSMFIELD_ENTRY( XAPICPAGE, lvt_timer.all.u32LvtTimer),
116 SSMFIELD_ENTRY( XAPICPAGE, lvt_thermal.all.u32LvtThermal),
117 SSMFIELD_ENTRY( XAPICPAGE, lvt_perf.all.u32LvtPerf),
118 SSMFIELD_ENTRY( XAPICPAGE, lvt_lint0.all.u32LvtLint0),
119 SSMFIELD_ENTRY( XAPICPAGE, lvt_lint1.all.u32LvtLint1),
120 SSMFIELD_ENTRY( XAPICPAGE, lvt_error.all.u32LvtError),
121 SSMFIELD_ENTRY( XAPICPAGE, timer_icr.u32InitialCount),
122 SSMFIELD_ENTRY( XAPICPAGE, timer_ccr.u32CurrentCount),
123 SSMFIELD_ENTRY( XAPICPAGE, timer_dcr.all.u32DivideValue),
124 SSMFIELD_ENTRY_TERM()
125};
126
127/** Saved state field descriptors for X2APICPAGE. */
128static const SSMFIELD g_aX2ApicPageFields[] =
129{
130 SSMFIELD_ENTRY(X2APICPAGE, id.u32ApicId),
131 SSMFIELD_ENTRY(X2APICPAGE, version.all.u32Version),
132 SSMFIELD_ENTRY(X2APICPAGE, tpr.u8Tpr),
133 SSMFIELD_ENTRY(X2APICPAGE, ppr.u8Ppr),
134 SSMFIELD_ENTRY(X2APICPAGE, ldr.u32LogicalApicId),
135 SSMFIELD_ENTRY(X2APICPAGE, svr.all.u32Svr),
136 SSMFIELD_ENTRY(X2APICPAGE, isr.u[0].u32Reg),
137 SSMFIELD_ENTRY(X2APICPAGE, isr.u[1].u32Reg),
138 SSMFIELD_ENTRY(X2APICPAGE, isr.u[2].u32Reg),
139 SSMFIELD_ENTRY(X2APICPAGE, isr.u[3].u32Reg),
140 SSMFIELD_ENTRY(X2APICPAGE, isr.u[4].u32Reg),
141 SSMFIELD_ENTRY(X2APICPAGE, isr.u[5].u32Reg),
142 SSMFIELD_ENTRY(X2APICPAGE, isr.u[6].u32Reg),
143 SSMFIELD_ENTRY(X2APICPAGE, isr.u[7].u32Reg),
144 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[0].u32Reg),
145 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[1].u32Reg),
146 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[2].u32Reg),
147 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[3].u32Reg),
148 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[4].u32Reg),
149 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[5].u32Reg),
150 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[6].u32Reg),
151 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[7].u32Reg),
152 SSMFIELD_ENTRY(X2APICPAGE, irr.u[0].u32Reg),
153 SSMFIELD_ENTRY(X2APICPAGE, irr.u[1].u32Reg),
154 SSMFIELD_ENTRY(X2APICPAGE, irr.u[2].u32Reg),
155 SSMFIELD_ENTRY(X2APICPAGE, irr.u[3].u32Reg),
156 SSMFIELD_ENTRY(X2APICPAGE, irr.u[4].u32Reg),
157 SSMFIELD_ENTRY(X2APICPAGE, irr.u[5].u32Reg),
158 SSMFIELD_ENTRY(X2APICPAGE, irr.u[6].u32Reg),
159 SSMFIELD_ENTRY(X2APICPAGE, irr.u[7].u32Reg),
160 SSMFIELD_ENTRY(X2APICPAGE, esr.all.u32Errors),
161 SSMFIELD_ENTRY(X2APICPAGE, icr_lo.all.u32IcrLo),
162 SSMFIELD_ENTRY(X2APICPAGE, icr_hi.u32IcrHi),
163 SSMFIELD_ENTRY(X2APICPAGE, lvt_timer.all.u32LvtTimer),
164 SSMFIELD_ENTRY(X2APICPAGE, lvt_thermal.all.u32LvtThermal),
165 SSMFIELD_ENTRY(X2APICPAGE, lvt_perf.all.u32LvtPerf),
166 SSMFIELD_ENTRY(X2APICPAGE, lvt_lint0.all.u32LvtLint0),
167 SSMFIELD_ENTRY(X2APICPAGE, lvt_lint1.all.u32LvtLint1),
168 SSMFIELD_ENTRY(X2APICPAGE, lvt_error.all.u32LvtError),
169 SSMFIELD_ENTRY(X2APICPAGE, timer_icr.u32InitialCount),
170 SSMFIELD_ENTRY(X2APICPAGE, timer_ccr.u32CurrentCount),
171 SSMFIELD_ENTRY(X2APICPAGE, timer_dcr.all.u32DivideValue),
172 SSMFIELD_ENTRY_TERM()
173};
174
175
176/**
177 * Initializes per-VCPU APIC to the state following an INIT reset
178 * ("Wait-for-SIPI" state).
179 *
180 * @param pVCpu The cross context virtual CPU structure.
181 */
182static void apicR3InitIpi(PVMCPU pVCpu)
183{
184 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
185 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
186
187 /*
188 * See Intel spec. 10.4.7.3 "Local APIC State After an INIT Reset (Wait-for-SIPI State)"
189 * and AMD spec 16.3.2 "APIC Registers".
190 *
191 * The reason we don't simply zero out the entire APIC page and only set the non-zero members
192 * is because there are some registers that are not touched by the INIT IPI (e.g. version)
193 * operation and this function is only a subset of the reset operation.
194 */
195 RT_ZERO(pXApicPage->irr);
196 RT_ZERO(pXApicPage->irr);
197 RT_ZERO(pXApicPage->isr);
198 RT_ZERO(pXApicPage->tmr);
199 RT_ZERO(pXApicPage->icr_hi);
200 RT_ZERO(pXApicPage->icr_lo);
201 RT_ZERO(pXApicPage->ldr);
202 RT_ZERO(pXApicPage->tpr);
203 RT_ZERO(pXApicPage->ppr);
204 RT_ZERO(pXApicPage->timer_icr);
205 RT_ZERO(pXApicPage->timer_ccr);
206 RT_ZERO(pXApicPage->timer_dcr);
207
208 pXApicPage->dfr.u.u4Model = XAPICDESTFORMAT_FLAT;
209 pXApicPage->dfr.u.u28ReservedMb1 = UINT32_C(0xfffffff);
210
211 /** @todo CMCI. */
212
213 RT_ZERO(pXApicPage->lvt_timer);
214 pXApicPage->lvt_timer.u.u1Mask = 1;
215
216#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
217 RT_ZERO(pXApicPage->lvt_thermal);
218 pXApicPage->lvt_thermal.u.u1Mask = 1;
219#endif
220
221 RT_ZERO(pXApicPage->lvt_perf);
222 pXApicPage->lvt_perf.u.u1Mask = 1;
223
224 RT_ZERO(pXApicPage->lvt_lint0);
225 pXApicPage->lvt_lint0.u.u1Mask = 1;
226
227 RT_ZERO(pXApicPage->lvt_lint1);
228 pXApicPage->lvt_lint1.u.u1Mask = 1;
229
230 RT_ZERO(pXApicPage->lvt_error);
231 pXApicPage->lvt_error.u.u1Mask = 1;
232
233 RT_ZERO(pXApicPage->svr);
234 pXApicPage->svr.u.u8SpuriousVector = 0xff;
235
236 /* The self-IPI register is reset to 0. See Intel spec. 10.12.5.1 "x2APIC States" */
237 PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
238 RT_ZERO(pX2ApicPage->self_ipi);
239
240 /* Clear the pending-interrupt bitmaps. */
241 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
242 RT_BZERO(&pApicCpu->ApicPibLevel, sizeof(APICPIB));
243 RT_BZERO(pApicCpu->pvApicPibR3, sizeof(APICPIB));
244
245 /* Clear the interrupt line states for LINT0 and LINT1 pins. */
246 pApicCpu->fActiveLint0 = false;
247 pApicCpu->fActiveLint1 = false;
248}
249
250
251/**
252 * Sets the CPUID feature bits for the APIC mode.
253 *
254 * @param pVM The cross context VM structure.
255 * @param enmMode The APIC mode.
256 */
257static void apicR3SetCpuIdFeatureLevel(PVM pVM, PDMAPICMODE enmMode)
258{
259 switch (enmMode)
260 {
261 case PDMAPICMODE_NONE:
262 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
263 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
264 break;
265
266 case PDMAPICMODE_APIC:
267 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
268 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
269 break;
270
271 case PDMAPICMODE_X2APIC:
272 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
273 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
274 break;
275
276 default:
277 AssertMsgFailed(("Unknown/invalid APIC mode: %d\n", (int)enmMode));
278 }
279}
280
281
282/**
283 * Resets the APIC base MSR.
284 *
285 * @param pVCpu The cross context virtual CPU structure.
286 */
287static void apicR3ResetBaseMsr(PVMCPU pVCpu)
288{
289 /*
290 * Initialize the APIC base MSR. The APIC enable-bit is set upon power-up or reset[1].
291 *
292 * A Reset (in xAPIC and x2APIC mode) brings up the local APIC in xAPIC mode.
293 * An INIT IPI does -not- cause a transition between xAPIC and x2APIC mode[2].
294 *
295 * [1] See AMD spec. 14.1.3 "Processor Initialization State"
296 * [2] See Intel spec. 10.12.5.1 "x2APIC States".
297 */
298 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
299
300 /* Construct. */
301 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
302 PAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
303 uint64_t uApicBaseMsr = MSR_IA32_APICBASE_ADDR;
304 if (pVCpu->idCpu == 0)
305 uApicBaseMsr |= MSR_IA32_APICBASE_BSP;
306
307 /* If the VM was configured with no APIC, don't enable xAPIC mode, obviously. */
308 if (pApic->enmMaxMode != PDMAPICMODE_NONE)
309 {
310 uApicBaseMsr |= MSR_IA32_APICBASE_EN;
311
312 /*
313 * While coming out of a reset the APIC is enabled and in xAPIC mode. If software had previously
314 * disabled the APIC (which results in the CPUID bit being cleared as well) we re-enable it here.
315 * See Intel spec. 10.12.5.1 "x2APIC States".
316 */
317 if (CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, true /*fVisible*/) == false)
318 LogRel(("APIC%u: Resetting mode to xAPIC\n", pVCpu->idCpu));
319 }
320
321 /* Commit. */
322 ASMAtomicWriteU64(&pApicCpu->uApicBaseMsr, uApicBaseMsr);
323}
324
325
326/**
327 * Initializes per-VCPU APIC to the state following a power-up or hardware
328 * reset.
329 *
330 * @param pVCpu The cross context virtual CPU structure.
331 * @param fResetApicBaseMsr Whether to reset the APIC base MSR.
332 */
333VMMR3_INT_DECL(void) apicR3ResetCpu(PVMCPU pVCpu, bool fResetApicBaseMsr)
334{
335 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
336
337 LogFlow(("APIC%u: apicR3ResetCpu: fResetApicBaseMsr=%RTbool\n", pVCpu->idCpu, fResetApicBaseMsr));
338
339#ifdef VBOX_STRICT
340 /* Verify that the initial APIC ID reported via CPUID matches our VMCPU ID assumption. */
341 uint32_t uEax, uEbx, uEcx, uEdx;
342 uEax = uEbx = uEcx = uEdx = UINT32_MAX;
343 CPUMGetGuestCpuId(pVCpu, 1, 0, &uEax, &uEbx, &uEcx, &uEdx);
344 Assert(((uEbx >> 24) & 0xff) == pVCpu->idCpu);
345#endif
346
347 /*
348 * The state following a power-up or reset is a superset of the INIT state.
349 * See Intel spec. 10.4.7.3 "Local APIC State After an INIT Reset ('Wait-for-SIPI' State)"
350 */
351 apicR3InitIpi(pVCpu);
352
353 /*
354 * The APIC version register is read-only, so just initialize it here.
355 * It is not clear from the specs, where exactly it is initialized.
356 * The version determines the number of LVT entries and size of the APIC ID (8 bits for P4).
357 */
358 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
359#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
360 pXApicPage->version.u.u8MaxLvtEntry = XAPIC_MAX_LVT_ENTRIES_P4 - 1;
361 pXApicPage->version.u.u8Version = XAPIC_HARDWARE_VERSION_P4;
362 AssertCompile(sizeof(pXApicPage->id.u8ApicId) >= XAPIC_APIC_ID_BIT_COUNT_P4 / 8);
363#else
364# error "Implement Pentium and P6 family APIC architectures"
365#endif
366
367 /** @todo It isn't clear in the spec. where exactly the default base address
368 * is (re)initialized, atm we do it here in Reset. */
369 if (fResetApicBaseMsr)
370 apicR3ResetBaseMsr(pVCpu);
371
372 /*
373 * Initialize the APIC ID register to xAPIC format.
374 */
375 ASMMemZero32(&pXApicPage->id, sizeof(pXApicPage->id));
376 pXApicPage->id.u8ApicId = pVCpu->idCpu;
377}
378
379
380/**
381 * Receives an INIT IPI.
382 *
383 * @param pVCpu The cross context virtual CPU structure.
384 */
385VMMR3_INT_DECL(void) APICR3InitIpi(PVMCPU pVCpu)
386{
387 VMCPU_ASSERT_EMT(pVCpu);
388 LogFlow(("APIC%u: APICR3InitIpi\n", pVCpu->idCpu));
389 apicR3InitIpi(pVCpu);
390}
391
392
393/**
394 * Sets whether Hyper-V compatibility mode (MSR interface) is enabled or not.
395 *
396 * This mode is a hybrid of xAPIC and x2APIC modes, some caveats:
397 * 1. MSRs are used even ones that are missing (illegal) in x2APIC like DFR.
398 * 2. A single ICR is used by the guest to send IPIs rather than 2 ICR writes.
399 * 3. It is unclear what the behaviour will be when invalid bits are set,
400 * currently we follow x2APIC behaviour of causing a \#GP.
401 *
402 * @param pVM The cross context VM structure.
403 * @param fHyperVCompatMode Whether the compatibility mode is enabled.
404 */
405VMMR3_INT_DECL(void) APICR3HvSetCompatMode(PVM pVM, bool fHyperVCompatMode)
406{
407 Assert(pVM);
408 PAPIC pApic = VM_TO_APIC(pVM);
409 pApic->fHyperVCompatMode = fHyperVCompatMode;
410
411 int rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic);
412 AssertLogRelRC(rc);
413}
414
415
416/**
417 * Helper for dumping an APIC 256-bit sparse register.
418 *
419 * @param pApicReg The APIC 256-bit spare register.
420 * @param pHlp The debug output helper.
421 */
422static void apicR3DbgInfo256BitReg(volatile const XAPIC256BITREG *pApicReg, PCDBGFINFOHLP pHlp)
423{
424 ssize_t const cFragments = RT_ELEMENTS(pApicReg->u);
425 unsigned const cBitsPerFragment = sizeof(pApicReg->u[0].u32Reg) * 8;
426 XAPIC256BITREG ApicReg;
427 RT_ZERO(ApicReg);
428
429 pHlp->pfnPrintf(pHlp, " ");
430 for (ssize_t i = cFragments - 1; i >= 0; i--)
431 {
432 uint32_t const uFragment = pApicReg->u[i].u32Reg;
433 ApicReg.u[i].u32Reg = uFragment;
434 pHlp->pfnPrintf(pHlp, "%08x", uFragment);
435 }
436 pHlp->pfnPrintf(pHlp, "\n");
437
438 uint32_t cPending = 0;
439 pHlp->pfnPrintf(pHlp, " Pending:");
440 for (ssize_t i = cFragments - 1; i >= 0; i--)
441 {
442 uint32_t uFragment = ApicReg.u[i].u32Reg;
443 if (uFragment)
444 {
445 do
446 {
447 unsigned idxSetBit = ASMBitLastSetU32(uFragment);
448 --idxSetBit;
449 ASMBitClear(&uFragment, idxSetBit);
450
451 idxSetBit += (i * cBitsPerFragment);
452 pHlp->pfnPrintf(pHlp, " %#02x", idxSetBit);
453 ++cPending;
454 } while (uFragment);
455 }
456 }
457 if (!cPending)
458 pHlp->pfnPrintf(pHlp, " None");
459 pHlp->pfnPrintf(pHlp, "\n");
460}
461
462
463/**
464 * Helper for dumping an APIC pending-interrupt bitmap.
465 *
466 * @param pApicPib The pending-interrupt bitmap.
467 * @param pHlp The debug output helper.
468 */
469static void apicR3DbgInfoPib(PCAPICPIB pApicPib, PCDBGFINFOHLP pHlp)
470{
471 /* Copy the pending-interrupt bitmap as an APIC 256-bit sparse register. */
472 XAPIC256BITREG ApicReg;
473 RT_ZERO(ApicReg);
474 ssize_t const cFragmentsDst = RT_ELEMENTS(ApicReg.u);
475 ssize_t const cFragmentsSrc = RT_ELEMENTS(pApicPib->au64VectorBitmap);
476 AssertCompile(RT_ELEMENTS(ApicReg.u) == 2 * RT_ELEMENTS(pApicPib->au64VectorBitmap));
477 for (ssize_t idxPib = cFragmentsSrc - 1, idxReg = cFragmentsDst - 1; idxPib >= 0; idxPib--, idxReg -= 2)
478 {
479 uint64_t const uFragment = pApicPib->au64VectorBitmap[idxPib];
480 uint32_t const uFragmentLo = RT_LO_U32(uFragment);
481 uint32_t const uFragmentHi = RT_HI_U32(uFragment);
482 ApicReg.u[idxReg].u32Reg = uFragmentHi;
483 ApicReg.u[idxReg - 1].u32Reg = uFragmentLo;
484 }
485
486 /* Dump it. */
487 apicR3DbgInfo256BitReg(&ApicReg, pHlp);
488}
489
490
491/**
492 * Dumps basic APIC state.
493 *
494 * @param pVM The cross context VM structure.
495 * @param pHlp The info helpers.
496 * @param pszArgs Arguments, ignored.
497 */
498static DECLCALLBACK(void) apicR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
499{
500 NOREF(pszArgs);
501 PVMCPU pVCpu = VMMGetCpu(pVM);
502 if (!pVCpu)
503 pVCpu = &pVM->aCpus[0];
504
505 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
506 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
507 PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
508
509 uint64_t const uBaseMsr = pApicCpu->uApicBaseMsr;
510 APICMODE const enmMode = apicGetMode(uBaseMsr);
511 bool const fX2ApicMode = XAPIC_IN_X2APIC_MODE(pVCpu);
512
513 pHlp->pfnPrintf(pHlp, "APIC%u:\n", pVCpu->idCpu);
514 pHlp->pfnPrintf(pHlp, " APIC Base MSR = %#RX64 (Addr=%#RX64)\n", uBaseMsr,
515 MSR_IA32_APICBASE_GET_ADDR(uBaseMsr));
516 pHlp->pfnPrintf(pHlp, " Mode = %u (%s)\n", enmMode, apicGetModeName(enmMode));
517 if (fX2ApicMode)
518 {
519 pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pX2ApicPage->id.u32ApicId,
520 pX2ApicPage->id.u32ApicId);
521 }
522 else
523 pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pXApicPage->id.u8ApicId, pXApicPage->id.u8ApicId);
524 pHlp->pfnPrintf(pHlp, " Version = %#x\n", pXApicPage->version.all.u32Version);
525 pHlp->pfnPrintf(pHlp, " APIC Version = %#x\n", pXApicPage->version.u.u8Version);
526 pHlp->pfnPrintf(pHlp, " Max LVT entry index (0..N) = %u\n", pXApicPage->version.u.u8MaxLvtEntry);
527 pHlp->pfnPrintf(pHlp, " EOI Broadcast supression = %RTbool\n", pXApicPage->version.u.fEoiBroadcastSupression);
528 if (!fX2ApicMode)
529 pHlp->pfnPrintf(pHlp, " APR = %u (%#x)\n", pXApicPage->apr.u8Apr, pXApicPage->apr.u8Apr);
530 pHlp->pfnPrintf(pHlp, " TPR = %u (%#x)\n", pXApicPage->tpr.u8Tpr, pXApicPage->tpr.u8Tpr);
531 pHlp->pfnPrintf(pHlp, " Task-priority class = %#x\n", XAPIC_TPR_GET_TP(pXApicPage->tpr.u8Tpr) >> 4);
532 pHlp->pfnPrintf(pHlp, " Task-priority subclass = %#x\n", XAPIC_TPR_GET_TP_SUBCLASS(pXApicPage->tpr.u8Tpr));
533 pHlp->pfnPrintf(pHlp, " PPR = %u (%#x)\n", pXApicPage->ppr.u8Ppr, pXApicPage->ppr.u8Ppr);
534 pHlp->pfnPrintf(pHlp, " Processor-priority class = %#x\n", XAPIC_PPR_GET_PP(pXApicPage->ppr.u8Ppr) >> 4);
535 pHlp->pfnPrintf(pHlp, " Processor-priority subclass = %#x\n", XAPIC_PPR_GET_PP_SUBCLASS(pXApicPage->ppr.u8Ppr));
536 if (!fX2ApicMode)
537 pHlp->pfnPrintf(pHlp, " RRD = %u (%#x)\n", pXApicPage->rrd.u32Rrd, pXApicPage->rrd.u32Rrd);
538 pHlp->pfnPrintf(pHlp, " LDR = %#x\n", pXApicPage->ldr.all.u32Ldr);
539 pHlp->pfnPrintf(pHlp, " Logical APIC ID = %#x\n", fX2ApicMode ? pX2ApicPage->ldr.u32LogicalApicId
540 : pXApicPage->ldr.u.u8LogicalApicId);
541 if (!fX2ApicMode)
542 {
543 pHlp->pfnPrintf(pHlp, " DFR = %#x\n", pXApicPage->dfr.all.u32Dfr);
544 pHlp->pfnPrintf(pHlp, " Model = %#x (%s)\n", pXApicPage->dfr.u.u4Model,
545 apicGetDestFormatName((XAPICDESTFORMAT)pXApicPage->dfr.u.u4Model));
546 }
547 pHlp->pfnPrintf(pHlp, " SVR = %#x\n", pXApicPage->svr.all.u32Svr);
548 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->svr.u.u8SpuriousVector,
549 pXApicPage->svr.u.u8SpuriousVector);
550 pHlp->pfnPrintf(pHlp, " Software Enabled = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fApicSoftwareEnable));
551 pHlp->pfnPrintf(pHlp, " Supress EOI broadcast = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fSupressEoiBroadcast));
552 pHlp->pfnPrintf(pHlp, " ISR\n");
553 apicR3DbgInfo256BitReg(&pXApicPage->isr, pHlp);
554 pHlp->pfnPrintf(pHlp, " TMR\n");
555 apicR3DbgInfo256BitReg(&pXApicPage->tmr, pHlp);
556 pHlp->pfnPrintf(pHlp, " IRR\n");
557 apicR3DbgInfo256BitReg(&pXApicPage->irr, pHlp);
558 pHlp->pfnPrintf(pHlp, " PIB\n");
559 apicR3DbgInfoPib((PCAPICPIB)pApicCpu->pvApicPibR3, pHlp);
560 pHlp->pfnPrintf(pHlp, " Level PIB\n");
561 apicR3DbgInfoPib(&pApicCpu->ApicPibLevel, pHlp);
562 pHlp->pfnPrintf(pHlp, " ESR Internal = %#x\n", pApicCpu->uEsrInternal);
563 pHlp->pfnPrintf(pHlp, " ESR = %#x\n", pXApicPage->esr.all.u32Errors);
564 pHlp->pfnPrintf(pHlp, " Redirectable IPI = %RTbool\n", pXApicPage->esr.u.fRedirectableIpi);
565 pHlp->pfnPrintf(pHlp, " Send Illegal Vector = %RTbool\n", pXApicPage->esr.u.fSendIllegalVector);
566 pHlp->pfnPrintf(pHlp, " Recv Illegal Vector = %RTbool\n", pXApicPage->esr.u.fRcvdIllegalVector);
567 pHlp->pfnPrintf(pHlp, " Illegal Register Address = %RTbool\n", pXApicPage->esr.u.fIllegalRegAddr);
568 pHlp->pfnPrintf(pHlp, " ICR Low = %#x\n", pXApicPage->icr_lo.all.u32IcrLo);
569 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->icr_lo.u.u8Vector,
570 pXApicPage->icr_lo.u.u8Vector);
571 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u3DeliveryMode,
572 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->icr_lo.u.u3DeliveryMode));
573 pHlp->pfnPrintf(pHlp, " Destination Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u1DestMode,
574 apicGetDestModeName((XAPICDESTMODE)pXApicPage->icr_lo.u.u1DestMode));
575 if (!fX2ApicMode)
576 pHlp->pfnPrintf(pHlp, " Delivery Status = %u\n", pXApicPage->icr_lo.u.u1DeliveryStatus);
577 pHlp->pfnPrintf(pHlp, " Level = %u\n", pXApicPage->icr_lo.u.u1Level);
578 pHlp->pfnPrintf(pHlp, " Trigger Mode = %u (%s)\n", pXApicPage->icr_lo.u.u1TriggerMode,
579 apicGetTriggerModeName((XAPICTRIGGERMODE)pXApicPage->icr_lo.u.u1TriggerMode));
580 pHlp->pfnPrintf(pHlp, " Destination shorthand = %#x (%s)\n", pXApicPage->icr_lo.u.u2DestShorthand,
581 apicGetDestShorthandName((XAPICDESTSHORTHAND)pXApicPage->icr_lo.u.u2DestShorthand));
582 pHlp->pfnPrintf(pHlp, " ICR High = %#x\n", pXApicPage->icr_hi.all.u32IcrHi);
583 pHlp->pfnPrintf(pHlp, " Destination field/mask = %#x\n", fX2ApicMode ? pX2ApicPage->icr_hi.u32IcrHi
584 : pXApicPage->icr_hi.u.u8Dest);
585}
586
587
588/**
589 * Helper for dumping the LVT timer.
590 *
591 * @param pVCpu The cross context virtual CPU structure.
592 * @param pHlp The debug output helper.
593 */
594static void apicR3InfoLvtTimer(PVMCPU pVCpu, PCDBGFINFOHLP pHlp)
595{
596 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
597 uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
598 pHlp->pfnPrintf(pHlp, "LVT Timer = %#RX32\n", uLvtTimer);
599 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_timer.u.u8Vector, pXApicPage->lvt_timer.u.u8Vector);
600 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_timer.u.u1DeliveryStatus);
601 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtTimer));
602 pHlp->pfnPrintf(pHlp, " Timer Mode = %#x (%s)\n", pXApicPage->lvt_timer.u.u2TimerMode,
603 apicGetTimerModeName((XAPICTIMERMODE)pXApicPage->lvt_timer.u.u2TimerMode));
604}
605
606
607/**
608 * Dumps APIC Local Vector Table (LVT) information.
609 *
610 * @param pVM The cross context VM structure.
611 * @param pHlp The info helpers.
612 * @param pszArgs Arguments, ignored.
613 */
614static DECLCALLBACK(void) apicR3InfoLvt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
615{
616 NOREF(pszArgs);
617 PVMCPU pVCpu = VMMGetCpu(pVM);
618 if (!pVCpu)
619 pVCpu = &pVM->aCpus[0];
620
621 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
622
623 /*
624 * Delivery modes available in the LVT entries. They're different (more reserved stuff) from the
625 * ICR delivery modes and hence we don't use apicGetDeliveryMode but mostly because we want small,
626 * fixed-length strings to fit our formatting needs here.
627 */
628 static const char * const s_apszLvtDeliveryModes[] =
629 {
630 "Fixed ",
631 "Rsvd ",
632 "SMI ",
633 "Rsvd ",
634 "NMI ",
635 "INIT ",
636 "Rsvd ",
637 "ExtINT"
638 };
639 /* Delivery Status. */
640 static const char * const s_apszLvtDeliveryStatus[] =
641 {
642 "Idle",
643 "Pend"
644 };
645 const char *pszNotApplicable = "";
646
647 pHlp->pfnPrintf(pHlp, "VCPU[%u] APIC Local Vector Table (LVT):\n", pVCpu->idCpu);
648 pHlp->pfnPrintf(pHlp, "lvt timermode mask trigger rirr polarity dlvr_st dlvr_mode vector\n");
649 /* Timer. */
650 {
651 /* Timer modes. */
652 static const char * const s_apszLvtTimerModes[] =
653 {
654 "One-shot ",
655 "Periodic ",
656 "TSC-dline"
657 };
658 const uint32_t uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
659 const XAPICTIMERMODE enmTimerMode = XAPIC_LVT_GET_TIMER_MODE(uLvtTimer);
660 const char *pszTimerMode = s_apszLvtTimerModes[enmTimerMode];
661 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtTimer);
662 const uint8_t uDeliveryStatus = uLvtTimer & XAPIC_LVT_DELIVERY_STATUS;
663 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
664 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
665
666 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
667 "Timer",
668 pszTimerMode,
669 uMask,
670 pszNotApplicable, /* TriggerMode */
671 pszNotApplicable, /* Remote IRR */
672 pszNotApplicable, /* Polarity */
673 pszDeliveryStatus,
674 pszNotApplicable, /* Delivery Mode */
675 uVector,
676 uVector);
677 }
678
679#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
680 /* Thermal sensor. */
681 {
682 uint32_t const uLvtThermal = pXApicPage->lvt_thermal.all.u32LvtThermal;
683 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtThermal);
684 const uint8_t uDeliveryStatus = uLvtThermal & XAPIC_LVT_DELIVERY_STATUS;
685 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
686 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtThermal);
687 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
688 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtThermal);
689
690 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
691 "Thermal",
692 pszNotApplicable, /* Timer mode */
693 uMask,
694 pszNotApplicable, /* TriggerMode */
695 pszNotApplicable, /* Remote IRR */
696 pszNotApplicable, /* Polarity */
697 pszDeliveryStatus,
698 pszDeliveryMode,
699 uVector,
700 uVector);
701 }
702#endif
703
704 /* Performance Monitor Counters. */
705 {
706 uint32_t const uLvtPerf = pXApicPage->lvt_thermal.all.u32LvtThermal;
707 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtPerf);
708 const uint8_t uDeliveryStatus = uLvtPerf & XAPIC_LVT_DELIVERY_STATUS;
709 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
710 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtPerf);
711 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
712 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtPerf);
713
714 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
715 "Perf",
716 pszNotApplicable, /* Timer mode */
717 uMask,
718 pszNotApplicable, /* TriggerMode */
719 pszNotApplicable, /* Remote IRR */
720 pszNotApplicable, /* Polarity */
721 pszDeliveryStatus,
722 pszDeliveryMode,
723 uVector,
724 uVector);
725 }
726
727 /* LINT0, LINT1. */
728 {
729 /* LINTx name. */
730 static const char * const s_apszLvtLint[] =
731 {
732 "LINT0",
733 "LINT1"
734 };
735 /* Trigger mode. */
736 static const char * const s_apszLvtTriggerModes[] =
737 {
738 "Edge ",
739 "Level"
740 };
741 /* Polarity. */
742 static const char * const s_apszLvtPolarity[] =
743 {
744 "ActiveHi",
745 "ActiveLo"
746 };
747
748 uint32_t aLvtLint[2];
749 aLvtLint[0] = pXApicPage->lvt_lint0.all.u32LvtLint0;
750 aLvtLint[1] = pXApicPage->lvt_lint1.all.u32LvtLint1;
751 for (size_t i = 0; i < RT_ELEMENTS(aLvtLint); i++)
752 {
753 uint32_t const uLvtLint = aLvtLint[i];
754 const char *pszLint = s_apszLvtLint[i];
755 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtLint);
756 const XAPICTRIGGERMODE enmTriggerMode = XAPIC_LVT_GET_TRIGGER_MODE(uLvtLint);
757 const char *pszTriggerMode = s_apszLvtTriggerModes[enmTriggerMode];
758 const uint8_t uRemoteIrr = XAPIC_LVT_GET_REMOTE_IRR(uLvtLint);
759 const uint8_t uPolarity = XAPIC_LVT_GET_POLARITY(uLvtLint);
760 const char *pszPolarity = s_apszLvtPolarity[uPolarity];
761 const uint8_t uDeliveryStatus = uLvtLint & XAPIC_LVT_DELIVERY_STATUS;
762 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
763 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtLint);
764 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
765 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtLint);
766
767 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %u %8s %4s %6s %3u (%#x)\n",
768 pszLint,
769 pszNotApplicable, /* Timer mode */
770 uMask,
771 pszTriggerMode,
772 uRemoteIrr,
773 pszPolarity,
774 pszDeliveryStatus,
775 pszDeliveryMode,
776 uVector,
777 uVector);
778 }
779 }
780
781 /* Error. */
782 {
783 uint32_t const uLvtError = pXApicPage->lvt_thermal.all.u32LvtThermal;
784 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtError);
785 const uint8_t uDeliveryStatus = uLvtError & XAPIC_LVT_DELIVERY_STATUS;
786 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
787 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtError);
788 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
789 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtError);
790
791 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
792 "Error",
793 pszNotApplicable, /* Timer mode */
794 uMask,
795 pszNotApplicable, /* TriggerMode */
796 pszNotApplicable, /* Remote IRR */
797 pszNotApplicable, /* Polarity */
798 pszDeliveryStatus,
799 pszDeliveryMode,
800 uVector,
801 uVector);
802 }
803}
804
805
806/**
807 * Dumps the APIC timer information.
808 *
809 * @param pVM The cross context VM structure.
810 * @param pHlp The info helpers.
811 * @param pszArgs Arguments, ignored.
812 */
813static DECLCALLBACK(void) apicR3InfoTimer(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
814{
815 NOREF(pszArgs);
816 PVMCPU pVCpu = VMMGetCpu(pVM);
817 if (!pVCpu)
818 pVCpu = &pVM->aCpus[0];
819
820 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
821 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
822
823 pHlp->pfnPrintf(pHlp, "VCPU[%u] Local APIC timer:\n", pVCpu->idCpu);
824 pHlp->pfnPrintf(pHlp, " ICR = %#RX32\n", pXApicPage->timer_icr.u32InitialCount);
825 pHlp->pfnPrintf(pHlp, " CCR = %#RX32\n", pXApicPage->timer_ccr.u32CurrentCount);
826 pHlp->pfnPrintf(pHlp, " DCR = %#RX32\n", pXApicPage->timer_dcr.all.u32DivideValue);
827 pHlp->pfnPrintf(pHlp, " Timer shift = %#x\n", apicGetTimerShift(pXApicPage));
828 pHlp->pfnPrintf(pHlp, " Timer initial TS = %#RU64\n", pApicCpu->u64TimerInitial);
829 apicR3InfoLvtTimer(pVCpu, pHlp);
830}
831
832
833#ifdef APIC_FUZZY_SSM_COMPAT_TEST
834
835/**
836 * Reads a 32-bit register at a specified offset.
837 *
838 * @returns The value at the specified offset.
839 * @param pXApicPage The xAPIC page.
840 * @param offReg The offset of the register being read.
841 *
842 * @remarks Duplicate of apicReadRaw32()!
843 */
844static uint32_t apicR3ReadRawR32(PCXAPICPAGE pXApicPage, uint16_t offReg)
845{
846 Assert(offReg < sizeof(*pXApicPage) - sizeof(uint32_t));
847 uint8_t const *pbXApic = (const uint8_t *)pXApicPage;
848 uint32_t const uValue = *(const uint32_t *)(pbXApic + offReg);
849 return uValue;
850}
851
852
853/**
854 * Helper for dumping per-VCPU APIC state to the release logger.
855 *
856 * This is primarily concerned about the APIC state relevant for saved-states.
857 *
858 * @param pVCpu The cross context virtual CPU structure.
859 * @param pszPrefix A caller supplied prefix before dumping the state.
860 * @param uVersion Data layout version.
861 */
862static void apicR3DumpState(PVMCPU pVCpu, const char *pszPrefix, uint32_t uVersion)
863{
864 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
865
866 LogRel(("APIC%u: %s (version %u):\n", pVCpu->idCpu, pszPrefix, uVersion));
867
868 switch (uVersion)
869 {
870 case APIC_SAVED_STATE_VERSION:
871 case APIC_SAVED_STATE_VERSION_VBOX_51_BETA2:
872 {
873 /* The auxiliary state. */
874 LogRel(("APIC%u: uApicBaseMsr = %#RX64\n", pVCpu->idCpu, pApicCpu->uApicBaseMsr));
875 LogRel(("APIC%u: uEsrInternal = %#RX64\n", pVCpu->idCpu, pApicCpu->uEsrInternal));
876
877 /* The timer. */
878 LogRel(("APIC%u: u64TimerInitial = %#RU64\n", pVCpu->idCpu, pApicCpu->u64TimerInitial));
879 LogRel(("APIC%u: uHintedTimerInitialCount = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerInitialCount));
880 LogRel(("APIC%u: uHintedTimerShift = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerShift));
881
882 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
883 LogRel(("APIC%u: uTimerICR = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_icr.u32InitialCount));
884 LogRel(("APIC%u: uTimerCCR = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_ccr.u32CurrentCount));
885
886 /* The PIBs. */
887 LogRel(("APIC%u: Edge PIB : %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), pApicCpu->pvApicPibR3));
888 LogRel(("APIC%u: Level PIB: %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), &pApicCpu->ApicPibLevel));
889
890 /* The LINT0, LINT1 interrupt line active states. */
891 LogRel(("APIC%u: fActiveLint0 = %RTbool\n", pVCpu->idCpu, pApicCpu->fActiveLint0));
892 LogRel(("APIC%u: fActiveLint1 = %RTbool\n", pVCpu->idCpu, pApicCpu->fActiveLint1));
893
894 /* The APIC page. */
895 LogRel(("APIC%u: APIC page: %.*Rhxs\n", pVCpu->idCpu, sizeof(XAPICPAGE), pApicCpu->pvApicPageR3));
896 break;
897 }
898
899 case APIC_SAVED_STATE_VERSION_VBOX_50:
900 case APIC_SAVED_STATE_VERSION_VBOX_30:
901 case APIC_SAVED_STATE_VERSION_ANCIENT:
902 {
903 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
904 LogRel(("APIC%u: uApicBaseMsr = %#RX32\n", pVCpu->idCpu, RT_LO_U32(pApicCpu->uApicBaseMsr)));
905 LogRel(("APIC%u: uId = %#RX32\n", pVCpu->idCpu, pXApicPage->id.u8ApicId));
906 LogRel(("APIC%u: uPhysId = N/A\n", pVCpu->idCpu));
907 LogRel(("APIC%u: uArbId = N/A\n", pVCpu->idCpu));
908 LogRel(("APIC%u: uTpr = %#RX32\n", pVCpu->idCpu, pXApicPage->tpr.u8Tpr));
909 LogRel(("APIC%u: uSvr = %#RX32\n", pVCpu->idCpu, pXApicPage->svr.all.u32Svr));
910 LogRel(("APIC%u: uLdr = %#x\n", pVCpu->idCpu, pXApicPage->ldr.all.u32Ldr));
911 LogRel(("APIC%u: uDfr = %#x\n", pVCpu->idCpu, pXApicPage->dfr.all.u32Dfr));
912
913 for (size_t i = 0; i < 8; i++)
914 {
915 LogRel(("APIC%u: Isr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->isr.u[i].u32Reg));
916 LogRel(("APIC%u: Tmr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->tmr.u[i].u32Reg));
917 LogRel(("APIC%u: Irr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->irr.u[i].u32Reg));
918 }
919
920 for (size_t i = 0; i < XAPIC_MAX_LVT_ENTRIES_P4; i++)
921 {
922 uint16_t const offReg = XAPIC_OFF_LVT_START + (i << 4);
923 LogRel(("APIC%u: Lvt[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, apicR3ReadRawR32(pXApicPage, offReg)));
924 }
925
926 LogRel(("APIC%u: uEsr = %#RX32\n", pVCpu->idCpu, pXApicPage->esr.all.u32Errors));
927 LogRel(("APIC%u: uIcr_Lo = %#RX32\n", pVCpu->idCpu, pXApicPage->icr_lo.all.u32IcrLo));
928 LogRel(("APIC%u: uIcr_Hi = %#RX32\n", pVCpu->idCpu, pXApicPage->icr_hi.all.u32IcrHi));
929 LogRel(("APIC%u: uTimerDcr = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_dcr.all.u32DivideValue));
930 LogRel(("APIC%u: uCountShift = %#RX32\n", pVCpu->idCpu, apicGetTimerShift(pXApicPage)));
931 LogRel(("APIC%u: uInitialCount = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_icr.u32InitialCount));
932 LogRel(("APIC%u: u64InitialCountLoadTime = %#RX64\n", pVCpu->idCpu, pApicCpu->u64TimerInitial));
933 LogRel(("APIC%u: u64NextTime / TimerCCR = %#RX64\n", pVCpu->idCpu, pXApicPage->timer_ccr.u32CurrentCount));
934 break;
935 }
936
937 default:
938 {
939 LogRel(("APIC: apicR3DumpState: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
940 break;
941 }
942 }
943}
944
945#endif /* APIC_FUZZY_SSM_COMPAT_TEST */
946
947/**
948 * Worker for saving per-VM APIC data.
949 *
950 * @returns VBox status code.
951 * @param pVM The cross context VM structure.
952 * @param pSSM The SSM handle.
953 */
954static int apicR3SaveVMData(PVM pVM, PSSMHANDLE pSSM)
955{
956 PAPIC pApic = VM_TO_APIC(pVM);
957 SSMR3PutU32(pSSM, pVM->cCpus);
958 SSMR3PutBool(pSSM, pApic->fIoApicPresent);
959 return SSMR3PutU32(pSSM, pApic->enmMaxMode);
960}
961
962
963/**
964 * Worker for loading per-VM APIC data.
965 *
966 * @returns VBox status code.
967 * @param pVM The cross context VM structure.
968 * @param pSSM The SSM handle.
969 */
970static int apicR3LoadVMData(PVM pVM, PSSMHANDLE pSSM)
971{
972 PAPIC pApic = VM_TO_APIC(pVM);
973
974 /* Load and verify number of CPUs. */
975 uint32_t cCpus;
976 int rc = SSMR3GetU32(pSSM, &cCpus);
977 AssertRCReturn(rc, rc);
978 if (cCpus != pVM->cCpus)
979 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%u config=%u"), cCpus, pVM->cCpus);
980
981 /* Load and verify I/O APIC presence. */
982 bool fIoApicPresent;
983 rc = SSMR3GetBool(pSSM, &fIoApicPresent);
984 AssertRCReturn(rc, rc);
985 if (fIoApicPresent != pApic->fIoApicPresent)
986 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApicPresent: saved=%RTbool config=%RTbool"),
987 fIoApicPresent, pApic->fIoApicPresent);
988
989 /* Load and verify configured max APIC mode. */
990 uint32_t uSavedMaxApicMode;
991 rc = SSMR3GetU32(pSSM, &uSavedMaxApicMode);
992 AssertRCReturn(rc, rc);
993 if (uSavedMaxApicMode != (uint32_t)pApic->enmMaxMode)
994 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicMode: saved=%u config=%u"),
995 uSavedMaxApicMode, pApic->enmMaxMode);
996 return VINF_SUCCESS;
997}
998
999
1000/**
1001 * Worker for loading per-VCPU APIC data for legacy (old) saved-states.
1002 *
1003 * @returns VBox status code.
1004 * @param pVCpu The cross context virtual CPU structure.
1005 * @param pSSM The SSM handle.
1006 * @param uVersion Data layout version.
1007 */
1008static int apicR3LoadLegacyVCpuData(PVMCPU pVCpu, PSSMHANDLE pSSM, uint32_t uVersion)
1009{
1010 AssertReturn(uVersion <= APIC_SAVED_STATE_VERSION_VBOX_50, VERR_NOT_SUPPORTED);
1011
1012 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1013 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1014
1015 uint32_t uApicBaseLo;
1016 int rc = SSMR3GetU32(pSSM, &uApicBaseLo);
1017 AssertRCReturn(rc, rc);
1018 pApicCpu->uApicBaseMsr = uApicBaseLo;
1019 Log2(("APIC%u: apicR3LoadLegacyVCpuData: uApicBaseMsr=%#RX64\n", pVCpu->idCpu, pApicCpu->uApicBaseMsr));
1020
1021 switch (uVersion)
1022 {
1023 case APIC_SAVED_STATE_VERSION_VBOX_50:
1024 case APIC_SAVED_STATE_VERSION_VBOX_30:
1025 {
1026 uint32_t uApicId, uPhysApicId, uArbId;
1027 SSMR3GetU32(pSSM, &uApicId); pXApicPage->id.u8ApicId = uApicId;
1028 SSMR3GetU32(pSSM, &uPhysApicId); NOREF(uPhysApicId); /* PhysId == pVCpu->idCpu */
1029 SSMR3GetU32(pSSM, &uArbId); NOREF(uArbId); /* ArbID is & was unused. */
1030 break;
1031 }
1032
1033 case APIC_SAVED_STATE_VERSION_ANCIENT:
1034 {
1035 uint8_t uPhysApicId;
1036 SSMR3GetU8(pSSM, &pXApicPage->id.u8ApicId);
1037 SSMR3GetU8(pSSM, &uPhysApicId); NOREF(uPhysApicId); /* PhysId == pVCpu->idCpu */
1038 break;
1039 }
1040
1041 default:
1042 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1043 }
1044
1045 uint32_t u32Tpr;
1046 SSMR3GetU32(pSSM, &u32Tpr);
1047 pXApicPage->tpr.u8Tpr = u32Tpr & XAPIC_TPR_VALID;
1048
1049 SSMR3GetU32(pSSM, &pXApicPage->svr.all.u32Svr);
1050 SSMR3GetU8(pSSM, &pXApicPage->ldr.u.u8LogicalApicId);
1051
1052 uint8_t uDfr;
1053 SSMR3GetU8(pSSM, &uDfr);
1054 pXApicPage->dfr.u.u4Model = uDfr >> 4;
1055
1056 AssertCompile(RT_ELEMENTS(pXApicPage->isr.u) == 8);
1057 AssertCompile(RT_ELEMENTS(pXApicPage->tmr.u) == 8);
1058 AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 8);
1059 for (size_t i = 0; i < 8; i++)
1060 {
1061 SSMR3GetU32(pSSM, &pXApicPage->isr.u[i].u32Reg);
1062 SSMR3GetU32(pSSM, &pXApicPage->tmr.u[i].u32Reg);
1063 SSMR3GetU32(pSSM, &pXApicPage->irr.u[i].u32Reg);
1064 }
1065
1066 SSMR3GetU32(pSSM, &pXApicPage->lvt_timer.all.u32LvtTimer);
1067 SSMR3GetU32(pSSM, &pXApicPage->lvt_thermal.all.u32LvtThermal);
1068 SSMR3GetU32(pSSM, &pXApicPage->lvt_perf.all.u32LvtPerf);
1069 SSMR3GetU32(pSSM, &pXApicPage->lvt_lint0.all.u32LvtLint0);
1070 SSMR3GetU32(pSSM, &pXApicPage->lvt_lint1.all.u32LvtLint1);
1071 SSMR3GetU32(pSSM, &pXApicPage->lvt_error.all.u32LvtError);
1072
1073 SSMR3GetU32(pSSM, &pXApicPage->esr.all.u32Errors);
1074 SSMR3GetU32(pSSM, &pXApicPage->icr_lo.all.u32IcrLo);
1075 SSMR3GetU32(pSSM, &pXApicPage->icr_hi.all.u32IcrHi);
1076
1077 uint32_t u32TimerShift;
1078 SSMR3GetU32(pSSM, &pXApicPage->timer_dcr.all.u32DivideValue);
1079 SSMR3GetU32(pSSM, &u32TimerShift);
1080 /*
1081 * Old implementation may have left the timer shift uninitialized until
1082 * the timer configuration register was written. Unfortunately zero is
1083 * also a valid timer shift value, so we're just going to ignore it
1084 * completely. The shift count can always be derived from the DCR.
1085 * See @bugref{8245#c98}.
1086 */
1087 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
1088
1089 SSMR3GetU32(pSSM, &pXApicPage->timer_icr.u32InitialCount);
1090 SSMR3GetU64(pSSM, &pApicCpu->u64TimerInitial);
1091 uint64_t uNextTS;
1092 rc = SSMR3GetU64(pSSM, &uNextTS); AssertRCReturn(rc, rc);
1093 if (uNextTS >= pApicCpu->u64TimerInitial + ((pXApicPage->timer_icr.u32InitialCount + 1) << uTimerShift))
1094 pXApicPage->timer_ccr.u32CurrentCount = pXApicPage->timer_icr.u32InitialCount;
1095
1096 rc = TMR3TimerLoad(pApicCpu->pTimerR3, pSSM);
1097 AssertRCReturn(rc, rc);
1098 Assert(pApicCpu->uHintedTimerInitialCount == 0);
1099 Assert(pApicCpu->uHintedTimerShift == 0);
1100 if (TMTimerIsActive(pApicCpu->pTimerR3))
1101 {
1102 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1103 apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
1104 }
1105
1106 return rc;
1107}
1108
1109
1110/**
1111 * @copydoc FNSSMDEVSAVEEXEC
1112 */
1113static DECLCALLBACK(int) apicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1114{
1115 PVM pVM = PDMDevHlpGetVM(pDevIns);
1116 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
1117
1118 LogFlow(("APIC: apicR3SaveExec\n"));
1119
1120 /* Save per-VM data. */
1121 int rc = apicR3SaveVMData(pVM, pSSM);
1122 AssertRCReturn(rc, rc);
1123
1124 /* Save per-VCPU data.*/
1125 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1126 {
1127 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1128 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1129
1130 /* Update interrupts from the pending-interrupts bitmaps to the IRR. */
1131 APICUpdatePendingInterrupts(pVCpu);
1132
1133 /* Save the auxiliary data. */
1134 SSMR3PutU64(pSSM, pApicCpu->uApicBaseMsr);
1135 SSMR3PutU32(pSSM, pApicCpu->uEsrInternal);
1136
1137 /* Save the APIC page. */
1138 if (XAPIC_IN_X2APIC_MODE(pVCpu))
1139 SSMR3PutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
1140 else
1141 SSMR3PutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
1142
1143 /* Save the timer. */
1144 SSMR3PutU64(pSSM, pApicCpu->u64TimerInitial);
1145 TMR3TimerSave(pApicCpu->pTimerR3, pSSM);
1146
1147 /* Save the LINT0, LINT1 interrupt line states. */
1148 SSMR3PutBool(pSSM, pApicCpu->fActiveLint0);
1149 SSMR3PutBool(pSSM, pApicCpu->fActiveLint1);
1150
1151#if defined(APIC_FUZZY_SSM_COMPAT_TEST) || defined(DEBUG_ramshankar)
1152 apicR3DumpState(pVCpu, "Saved state", APIC_SAVED_STATE_VERSION);
1153#endif
1154 }
1155
1156#ifdef APIC_FUZZY_SSM_COMPAT_TEST
1157 /* The state is fuzzy, don't even bother trying to load the guest. */
1158 return VERR_INVALID_STATE;
1159#else
1160 return rc;
1161#endif
1162}
1163
1164
1165/**
1166 * @copydoc FNSSMDEVLOADEXEC
1167 */
1168static DECLCALLBACK(int) apicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1169{
1170 PVM pVM = PDMDevHlpGetVM(pDevIns);
1171
1172 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
1173 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
1174
1175 LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1176
1177 /* Weed out invalid versions. */
1178 if ( uVersion != APIC_SAVED_STATE_VERSION
1179 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_51_BETA2
1180 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_50
1181 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_30
1182 && uVersion != APIC_SAVED_STATE_VERSION_ANCIENT)
1183 {
1184 LogRel(("APIC: apicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1185 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1186 }
1187
1188 int rc = VINF_SUCCESS;
1189 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_30)
1190 {
1191 rc = apicR3LoadVMData(pVM, pSSM);
1192 AssertRCReturn(rc, rc);
1193
1194 if (uVersion == APIC_SAVED_STATE_VERSION)
1195 { /* Load any new additional per-VM data. */ }
1196 }
1197
1198 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1199 {
1200 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1201 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1202
1203 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_50)
1204 {
1205 /* Load the auxiliary data. */
1206 SSMR3GetU64(pSSM, (uint64_t *)&pApicCpu->uApicBaseMsr);
1207 SSMR3GetU32(pSSM, &pApicCpu->uEsrInternal);
1208
1209 /* Load the APIC page. */
1210 if (XAPIC_IN_X2APIC_MODE(pVCpu))
1211 SSMR3GetStruct(pSSM, pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
1212 else
1213 SSMR3GetStruct(pSSM, pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
1214
1215 /* Load the timer. */
1216 rc = SSMR3GetU64(pSSM, &pApicCpu->u64TimerInitial); AssertRCReturn(rc, rc);
1217 rc = TMR3TimerLoad(pApicCpu->pTimerR3, pSSM); AssertRCReturn(rc, rc);
1218 Assert(pApicCpu->uHintedTimerShift == 0);
1219 Assert(pApicCpu->uHintedTimerInitialCount == 0);
1220 if (TMTimerIsActive(pApicCpu->pTimerR3))
1221 {
1222 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
1223 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1224 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
1225 apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
1226 }
1227
1228 /* Load the LINT0, LINT1 interrupt line states. */
1229 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_51_BETA2)
1230 {
1231 SSMR3GetBool(pSSM, (bool *)&pApicCpu->fActiveLint0);
1232 SSMR3GetBool(pSSM, (bool *)&pApicCpu->fActiveLint1);
1233 }
1234 }
1235 else
1236 {
1237 rc = apicR3LoadLegacyVCpuData(pVCpu, pSSM, uVersion);
1238 AssertRCReturn(rc, rc);
1239 }
1240
1241 /*
1242 * Check that we're still good wrt restored data, then tell CPUM about the current CPUID[1].EDX[9] visibility.
1243 */
1244 rc = SSMR3HandleGetStatus(pSSM);
1245 AssertRCReturn(rc, rc);
1246 CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, RT_BOOL(pApicCpu->uApicBaseMsr & MSR_IA32_APICBASE_EN));
1247
1248#if defined(APIC_FUZZY_SSM_COMPAT_TEST) || defined(DEBUG_ramshankar)
1249 apicR3DumpState(pVCpu, "Loaded state", uVersion);
1250#endif
1251 }
1252
1253 return rc;
1254}
1255
1256
1257/**
1258 * The timer callback.
1259 *
1260 * @param pDevIns The device instance.
1261 * @param pTimer The timer handle.
1262 * @param pvUser Opaque pointer to the VMCPU.
1263 *
1264 * @thread Any.
1265 * @remarks Currently this function is invoked on the last EMT, see @c
1266 * idTimerCpu in tmR3TimerCallback(). However, the code does -not-
1267 * rely on this and is designed to work with being invoked on any
1268 * thread.
1269 */
1270static DECLCALLBACK(void) apicR3TimerCallback(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1271{
1272 PVMCPU pVCpu = (PVMCPU)pvUser;
1273 Assert(TMTimerIsLockOwner(pTimer));
1274 Assert(pVCpu);
1275 LogFlow(("APIC%u: apicR3TimerCallback\n", pVCpu->idCpu));
1276 RT_NOREF2(pDevIns, pTimer);
1277
1278 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1279 uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
1280#ifdef VBOX_WITH_STATISTICS
1281 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1282 STAM_COUNTER_INC(&pApicCpu->StatTimerCallback);
1283#endif
1284 if (!XAPIC_LVT_IS_MASKED(uLvtTimer))
1285 {
1286 uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
1287 Log2(("APIC%u: apicR3TimerCallback: Raising timer interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
1288 apicPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE, 0 /* uSrcTag */);
1289 }
1290
1291 XAPICTIMERMODE enmTimerMode = XAPIC_LVT_GET_TIMER_MODE(uLvtTimer);
1292 switch (enmTimerMode)
1293 {
1294 case XAPICTIMERMODE_PERIODIC:
1295 {
1296 /* The initial-count register determines if the periodic timer is re-armed. */
1297 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1298 pXApicPage->timer_ccr.u32CurrentCount = uInitialCount;
1299 if (uInitialCount)
1300 {
1301 Log2(("APIC%u: apicR3TimerCallback: Re-arming timer. uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
1302 apicStartTimer(pVCpu, uInitialCount);
1303 }
1304 break;
1305 }
1306
1307 case XAPICTIMERMODE_ONESHOT:
1308 {
1309 pXApicPage->timer_ccr.u32CurrentCount = 0;
1310 break;
1311 }
1312
1313 case XAPICTIMERMODE_TSC_DEADLINE:
1314 {
1315 /** @todo implement TSC deadline. */
1316 AssertMsgFailed(("APIC: TSC deadline mode unimplemented\n"));
1317 break;
1318 }
1319 }
1320}
1321
1322
1323/**
1324 * @interface_method_impl{PDMDEVREG,pfnReset}
1325 */
1326static DECLCALLBACK(void) apicR3Reset(PPDMDEVINS pDevIns)
1327{
1328 PVM pVM = PDMDevHlpGetVM(pDevIns);
1329 VM_ASSERT_EMT0(pVM);
1330 VM_ASSERT_IS_NOT_RUNNING(pVM);
1331
1332 LogFlow(("APIC: apicR3Reset\n"));
1333
1334 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1335 {
1336 PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
1337 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpuDest);
1338
1339 if (TMTimerIsActive(pApicCpu->pTimerR3))
1340 TMTimerStop(pApicCpu->pTimerR3);
1341
1342 apicR3ResetCpu(pVCpuDest, true /* fResetApicBaseMsr */);
1343
1344 /* Clear the interrupt pending force flag. */
1345 apicClearInterruptFF(pVCpuDest, PDMAPICIRQ_HARDWARE);
1346 }
1347}
1348
1349
1350/**
1351 * @interface_method_impl{PDMDEVREG,pfnRelocate}
1352 */
1353static DECLCALLBACK(void) apicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1354{
1355 PVM pVM = PDMDevHlpGetVM(pDevIns);
1356 PAPIC pApic = VM_TO_APIC(pVM);
1357 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1358
1359 LogFlow(("APIC: apicR3Relocate: pVM=%p pDevIns=%p offDelta=%RGi\n", pVM, pDevIns, offDelta));
1360
1361 pApicDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1362
1363 pApic->pApicDevRC = PDMINS_2_DATA_RCPTR(pDevIns);
1364 pApic->pvApicPibRC += offDelta;
1365
1366 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1367 {
1368 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1369 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1370 pApicCpu->pTimerRC = TMTimerRCPtr(pApicCpu->pTimerR3);
1371
1372 pApicCpu->pvApicPageRC += offDelta;
1373 pApicCpu->pvApicPibRC += offDelta;
1374 Log2(("APIC%u: apicR3Relocate: APIC PIB at %RGv\n", pVCpu->idCpu, pApicCpu->pvApicPibRC));
1375 }
1376}
1377
1378
1379/**
1380 * Terminates the APIC state.
1381 *
1382 * @param pVM The cross context VM structure.
1383 */
1384static void apicR3TermState(PVM pVM)
1385{
1386 PAPIC pApic = VM_TO_APIC(pVM);
1387 LogFlow(("APIC: apicR3TermState: pVM=%p\n", pVM));
1388
1389 /* Unmap and free the PIB. */
1390 if (pApic->pvApicPibR3 != NIL_RTR3PTR)
1391 {
1392 size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
1393 if (cPages == 1)
1394 SUPR3PageFreeEx(pApic->pvApicPibR3, cPages);
1395 else
1396 SUPR3ContFree(pApic->pvApicPibR3, cPages);
1397 pApic->pvApicPibR3 = NIL_RTR3PTR;
1398 pApic->pvApicPibR0 = NIL_RTR0PTR;
1399 pApic->pvApicPibRC = NIL_RTRCPTR;
1400 }
1401
1402 /* Unmap and free the virtual-APIC pages. */
1403 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1404 {
1405 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1406 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1407
1408 pApicCpu->pvApicPibR3 = NIL_RTR3PTR;
1409 pApicCpu->pvApicPibR0 = NIL_RTR0PTR;
1410 pApicCpu->pvApicPibRC = NIL_RTRCPTR;
1411
1412 if (pApicCpu->pvApicPageR3 != NIL_RTR3PTR)
1413 {
1414 SUPR3PageFreeEx(pApicCpu->pvApicPageR3, 1 /* cPages */);
1415 pApicCpu->pvApicPageR3 = NIL_RTR3PTR;
1416 pApicCpu->pvApicPageR0 = NIL_RTR0PTR;
1417 pApicCpu->pvApicPageRC = NIL_RTRCPTR;
1418 }
1419 }
1420}
1421
1422
1423/**
1424 * Initializes the APIC state.
1425 *
1426 * @returns VBox status code.
1427 * @param pVM The cross context VM structure.
1428 */
1429static int apicR3InitState(PVM pVM)
1430{
1431 PAPIC pApic = VM_TO_APIC(pVM);
1432 LogFlow(("APIC: apicR3InitState: pVM=%p\n", pVM));
1433
1434 /* With hardware virtualization, we don't need to map the APIC in GC. */
1435 bool const fNeedsGCMapping = !HMIsEnabled(pVM);
1436
1437 /*
1438 * Allocate and map the pending-interrupt bitmap (PIB).
1439 *
1440 * We allocate all the VCPUs' PIBs contiguously in order to save space as
1441 * physically contiguous allocations are rounded to a multiple of page size.
1442 */
1443 Assert(pApic->pvApicPibR3 == NIL_RTR3PTR);
1444 Assert(pApic->pvApicPibR0 == NIL_RTR0PTR);
1445 Assert(pApic->pvApicPibRC == NIL_RTRCPTR);
1446 pApic->cbApicPib = RT_ALIGN_Z(pVM->cCpus * sizeof(APICPIB), PAGE_SIZE);
1447 size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
1448 if (cPages == 1)
1449 {
1450 SUPPAGE SupApicPib;
1451 RT_ZERO(SupApicPib);
1452 SupApicPib.Phys = NIL_RTHCPHYS;
1453 int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, &pApic->pvApicPibR3, &pApic->pvApicPibR0, &SupApicPib);
1454 if (RT_SUCCESS(rc))
1455 {
1456 pApic->HCPhysApicPib = SupApicPib.Phys;
1457 AssertLogRelReturn(pApic->pvApicPibR3, VERR_INTERNAL_ERROR);
1458 }
1459 else
1460 {
1461 LogRel(("APIC: Failed to allocate %u bytes for the pending-interrupt bitmap, rc=%Rrc\n", pApic->cbApicPib, rc));
1462 return rc;
1463 }
1464 }
1465 else
1466 pApic->pvApicPibR3 = SUPR3ContAlloc(cPages, &pApic->pvApicPibR0, &pApic->HCPhysApicPib);
1467
1468 if (pApic->pvApicPibR3)
1469 {
1470 AssertLogRelReturn(pApic->pvApicPibR0 != NIL_RTR0PTR, VERR_INTERNAL_ERROR);
1471 AssertLogRelReturn(pApic->HCPhysApicPib != NIL_RTHCPHYS, VERR_INTERNAL_ERROR);
1472
1473 /* Initialize the PIB. */
1474 RT_BZERO(pApic->pvApicPibR3, pApic->cbApicPib);
1475
1476 /* Map the PIB into GC. */
1477 if (fNeedsGCMapping)
1478 {
1479 pApic->pvApicPibRC = NIL_RTRCPTR;
1480 int rc = MMR3HyperMapHCPhys(pVM, pApic->pvApicPibR3, NIL_RTR0PTR, pApic->HCPhysApicPib, pApic->cbApicPib,
1481 "APIC PIB", (PRTGCPTR)&pApic->pvApicPibRC);
1482 if (RT_FAILURE(rc))
1483 {
1484 LogRel(("APIC: Failed to map %u bytes for the pending-interrupt bitmap into GC, rc=%Rrc\n", pApic->cbApicPib,
1485 rc));
1486 apicR3TermState(pVM);
1487 return rc;
1488 }
1489
1490 AssertLogRelReturn(pApic->pvApicPibRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
1491 }
1492
1493 /*
1494 * Allocate the map the virtual-APIC pages.
1495 */
1496 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1497 {
1498 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1499 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1500
1501 SUPPAGE SupApicPage;
1502 RT_ZERO(SupApicPage);
1503 SupApicPage.Phys = NIL_RTHCPHYS;
1504
1505 Assert(pVCpu->idCpu == idCpu);
1506 Assert(pApicCpu->pvApicPageR3 == NIL_RTR0PTR);
1507 Assert(pApicCpu->pvApicPageR0 == NIL_RTR0PTR);
1508 Assert(pApicCpu->pvApicPageRC == NIL_RTRCPTR);
1509 AssertCompile(sizeof(XAPICPAGE) == PAGE_SIZE);
1510 pApicCpu->cbApicPage = sizeof(XAPICPAGE);
1511 int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, &pApicCpu->pvApicPageR3, &pApicCpu->pvApicPageR0,
1512 &SupApicPage);
1513 if (RT_SUCCESS(rc))
1514 {
1515 AssertLogRelReturn(pApicCpu->pvApicPageR3 != NIL_RTR3PTR, VERR_INTERNAL_ERROR);
1516 AssertLogRelReturn(pApicCpu->HCPhysApicPage != NIL_RTHCPHYS, VERR_INTERNAL_ERROR);
1517 pApicCpu->HCPhysApicPage = SupApicPage.Phys;
1518
1519 /* Map the virtual-APIC page into GC. */
1520 if (fNeedsGCMapping)
1521 {
1522 rc = MMR3HyperMapHCPhys(pVM, pApicCpu->pvApicPageR3, NIL_RTR0PTR, pApicCpu->HCPhysApicPage,
1523 pApicCpu->cbApicPage, "APIC", (PRTGCPTR)&pApicCpu->pvApicPageRC);
1524 if (RT_FAILURE(rc))
1525 {
1526 LogRel(("APIC%u: Failed to map %u bytes for the virtual-APIC page into GC, rc=%Rrc", idCpu,
1527 pApicCpu->cbApicPage, rc));
1528 apicR3TermState(pVM);
1529 return rc;
1530 }
1531
1532 AssertLogRelReturn(pApicCpu->pvApicPageRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
1533 }
1534
1535 /* Associate the per-VCPU PIB pointers to the per-VM PIB mapping. */
1536 uint32_t const offApicPib = idCpu * sizeof(APICPIB);
1537 pApicCpu->pvApicPibR0 = (RTR0PTR)((RTR0UINTPTR)pApic->pvApicPibR0 + offApicPib);
1538 pApicCpu->pvApicPibR3 = (RTR3PTR)((RTR3UINTPTR)pApic->pvApicPibR3 + offApicPib);
1539 if (fNeedsGCMapping)
1540 pApicCpu->pvApicPibRC = (RTRCPTR)((RTRCUINTPTR)pApic->pvApicPibRC + offApicPib);
1541
1542 /* Initialize the virtual-APIC state. */
1543 RT_BZERO(pApicCpu->pvApicPageR3, pApicCpu->cbApicPage);
1544 apicR3ResetCpu(pVCpu, true /* fResetApicBaseMsr */);
1545
1546#ifdef DEBUG_ramshankar
1547 Assert(pApicCpu->pvApicPibR3 != NIL_RTR3PTR);
1548 Assert(pApicCpu->pvApicPibR0 != NIL_RTR0PTR);
1549 Assert(!fNeedsGCMapping || pApicCpu->pvApicPibRC != NIL_RTRCPTR);
1550 Assert(pApicCpu->pvApicPageR3 != NIL_RTR3PTR);
1551 Assert(pApicCpu->pvApicPageR0 != NIL_RTR0PTR);
1552 Assert(!fNeedsGCMapping || pApicCpu->pvApicPageRC != NIL_RTRCPTR);
1553 Assert(!fNeedsGCMapping || pApic->pvApicPibRC == pVM->aCpus[0].apic.s.pvApicPibRC);
1554#endif
1555 }
1556 else
1557 {
1558 LogRel(("APIC%u: Failed to allocate %u bytes for the virtual-APIC page, rc=%Rrc\n", idCpu, pApicCpu->cbApicPage, rc));
1559 apicR3TermState(pVM);
1560 return rc;
1561 }
1562 }
1563
1564#ifdef DEBUG_ramshankar
1565 Assert(pApic->pvApicPibR3 != NIL_RTR3PTR);
1566 Assert(pApic->pvApicPibR0 != NIL_RTR0PTR);
1567 Assert(!fNeedsGCMapping || pApic->pvApicPibRC != NIL_RTRCPTR);
1568#endif
1569 return VINF_SUCCESS;
1570 }
1571
1572 LogRel(("APIC: Failed to allocate %u bytes of physically contiguous memory for the pending-interrupt bitmap\n",
1573 pApic->cbApicPib));
1574 return VERR_NO_MEMORY;
1575}
1576
1577
1578/**
1579 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1580 */
1581static DECLCALLBACK(int) apicR3Destruct(PPDMDEVINS pDevIns)
1582{
1583 PVM pVM = PDMDevHlpGetVM(pDevIns);
1584 LogFlow(("APIC: apicR3Destruct: pVM=%p\n", pVM));
1585
1586 apicR3TermState(pVM);
1587 return VINF_SUCCESS;
1588}
1589
1590
1591/**
1592 * @interface_method_impl{PDMDEVREG,pfnInitComplete}
1593 */
1594static DECLCALLBACK(int) apicR3InitComplete(PPDMDEVINS pDevIns)
1595{
1596 PVM pVM = PDMDevHlpGetVM(pDevIns);
1597 PAPIC pApic = VM_TO_APIC(pVM);
1598
1599 /*
1600 * Init APIC settings that rely on HM and CPUM configurations.
1601 */
1602 CPUMCPUIDLEAF CpuLeaf;
1603 int rc = CPUMR3CpuIdGetLeaf(pVM, &CpuLeaf, 1, 0);
1604 AssertRCReturn(rc, rc);
1605
1606 pApic->fSupportsTscDeadline = RT_BOOL(CpuLeaf.uEcx & X86_CPUID_FEATURE_ECX_TSCDEADL);
1607 pApic->fPostedIntrsEnabled = HMR3IsPostedIntrsEnabled(pVM->pUVM);
1608 pApic->fVirtApicRegsEnabled = HMR3IsVirtApicRegsEnabled(pVM->pUVM);
1609
1610 LogRel(("APIC: fPostedIntrsEnabled=%RTbool fVirtApicRegsEnabled=%RTbool fSupportsTscDeadline=%RTbool\n",
1611 pApic->fPostedIntrsEnabled, pApic->fVirtApicRegsEnabled, pApic->fSupportsTscDeadline));
1612
1613 return VINF_SUCCESS;
1614}
1615
1616
1617/**
1618 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1619 */
1620static DECLCALLBACK(int) apicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1621{
1622 /*
1623 * Validate inputs.
1624 */
1625 Assert(iInstance == 0); NOREF(iInstance);
1626 Assert(pDevIns);
1627
1628 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1629 PVM pVM = PDMDevHlpGetVM(pDevIns);
1630 PAPIC pApic = VM_TO_APIC(pVM);
1631
1632 /*
1633 * Init the data.
1634 */
1635 pApicDev->pDevInsR3 = pDevIns;
1636 pApicDev->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1637 pApicDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1638
1639 pApic->pApicDevR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1640 pApic->pApicDevR3 = (PAPICDEV)PDMINS_2_DATA_R3PTR(pDevIns);
1641 pApic->pApicDevRC = PDMINS_2_DATA_RCPTR(pDevIns);
1642
1643 /*
1644 * Validate APIC settings.
1645 */
1646 if (!CFGMR3AreValuesValid(pCfg, "RZEnabled\0"
1647 "Mode\0"
1648 "IOAPIC\0"
1649 "NumCPUs\0"))
1650 {
1651 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1652 N_("APIC configuration error: unknown option specified"));
1653 }
1654
1655 int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pApic->fRZEnabled, true);
1656 AssertLogRelRCReturn(rc, rc);
1657
1658 rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &pApic->fIoApicPresent, true);
1659 AssertLogRelRCReturn(rc, rc);
1660
1661 /* Max APIC feature level. */
1662 uint8_t uMaxMode;
1663 rc = CFGMR3QueryU8Def(pCfg, "Mode", &uMaxMode, PDMAPICMODE_APIC);
1664 AssertLogRelRCReturn(rc, rc);
1665 switch ((PDMAPICMODE)uMaxMode)
1666 {
1667 case PDMAPICMODE_NONE:
1668 LogRel(("APIC: APIC maximum mode configured as 'None', effectively disabled/not-present!\n"));
1669 case PDMAPICMODE_APIC:
1670 case PDMAPICMODE_X2APIC:
1671 break;
1672 default:
1673 return VMR3SetError(pVM->pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, "APIC mode %d unknown.", uMaxMode);
1674 }
1675 pApic->enmMaxMode = (PDMAPICMODE)uMaxMode;
1676
1677 /*
1678 * Disable automatic PDM locking for this device.
1679 */
1680 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1681 AssertRCReturn(rc, rc);
1682
1683 /*
1684 * Register the APIC with PDM.
1685 */
1686 rc = PDMDevHlpAPICRegister(pDevIns);
1687 AssertLogRelRCReturn(rc, rc);
1688
1689 /*
1690 * Initialize the APIC state.
1691 */
1692 if (pApic->enmMaxMode == PDMAPICMODE_X2APIC)
1693 {
1694 rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic);
1695 AssertLogRelRCReturn(rc, rc);
1696 }
1697 else
1698 {
1699 /* We currently don't have a function to remove the range, so we register an range which will cause a #GP. */
1700 rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic_Invalid);
1701 AssertLogRelRCReturn(rc, rc);
1702 }
1703
1704 /* Tell CPUM about the APIC feature level so it can adjust APICBASE MSR GP mask and CPUID bits. */
1705 apicR3SetCpuIdFeatureLevel(pVM, pApic->enmMaxMode);
1706 /* Finally, initialize the state. */
1707 rc = apicR3InitState(pVM);
1708 AssertRCReturn(rc, rc);
1709
1710 /*
1711 * Register the MMIO range.
1712 */
1713 PAPICCPU pApicCpu0 = VMCPU_TO_APICCPU(&pVM->aCpus[0]);
1714 RTGCPHYS GCPhysApicBase = MSR_IA32_APICBASE_GET_ADDR(pApicCpu0->uApicBaseMsr);
1715
1716 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NULL /* pvUser */,
1717 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED,
1718 apicWriteMmio, apicReadMmio, "APIC");
1719 if (RT_FAILURE(rc))
1720 return rc;
1721
1722 if (pApic->fRZEnabled)
1723 {
1724 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NIL_RTRCPTR /*pvUser*/,
1725 "apicWriteMmio", "apicReadMmio");
1726 if (RT_FAILURE(rc))
1727 return rc;
1728
1729 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NIL_RTR0PTR /*pvUser*/,
1730 "apicWriteMmio", "apicReadMmio");
1731 if (RT_FAILURE(rc))
1732 return rc;
1733 }
1734
1735 /*
1736 * Create the APIC timers.
1737 */
1738 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1739 {
1740 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1741 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1742 RTStrPrintf(&pApicCpu->szTimerDesc[0], sizeof(pApicCpu->szTimerDesc), "APIC Timer %u", pVCpu->idCpu);
1743 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicR3TimerCallback, pVCpu, TMTIMER_FLAGS_NO_CRIT_SECT,
1744 pApicCpu->szTimerDesc, &pApicCpu->pTimerR3);
1745 if (RT_SUCCESS(rc))
1746 {
1747 pApicCpu->pTimerR0 = TMTimerR0Ptr(pApicCpu->pTimerR3);
1748 pApicCpu->pTimerRC = TMTimerRCPtr(pApicCpu->pTimerR3);
1749 }
1750 else
1751 return rc;
1752 }
1753
1754 /*
1755 * Register saved state callbacks.
1756 */
1757 rc = PDMDevHlpSSMRegister3(pDevIns, APIC_SAVED_STATE_VERSION, sizeof(*pApicDev), NULL /*pfnLiveExec*/, apicR3SaveExec,
1758 apicR3LoadExec);
1759 if (RT_FAILURE(rc))
1760 return rc;
1761
1762 /*
1763 * Register debugger info callbacks.
1764 *
1765 * We use separate callbacks rather than arguments so they can also be
1766 * dumped in an automated fashion while collecting crash diagnostics and
1767 * not just used during live debugging via the VM debugger.
1768 */
1769 rc = DBGFR3InfoRegisterInternalEx(pVM, "apic", "Dumps APIC basic information.", apicR3Info, DBGFINFO_FLAGS_ALL_EMTS);
1770 rc |= DBGFR3InfoRegisterInternalEx(pVM, "apiclvt", "Dumps APIC LVT information.", apicR3InfoLvt, DBGFINFO_FLAGS_ALL_EMTS);
1771 rc |= DBGFR3InfoRegisterInternalEx(pVM, "apictimer", "Dumps APIC timer information.", apicR3InfoTimer, DBGFINFO_FLAGS_ALL_EMTS);
1772 AssertRCReturn(rc, rc);
1773
1774#ifdef VBOX_WITH_STATISTICS
1775 /*
1776 * Statistics.
1777 */
1778#define APIC_REG_COUNTER(a_Reg, a_Desc, a_Key) \
1779 do { \
1780 rc = STAMR3RegisterF(pVM, a_Reg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, a_Desc, a_Key, idCpu); \
1781 AssertRCReturn(rc, rc); \
1782 } while(0)
1783
1784#define APIC_PROF_COUNTER(a_Reg, a_Desc, a_Key) \
1785 do { \
1786 rc = STAMR3RegisterF(pVM, a_Reg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, a_Desc, a_Key, \
1787 idCpu); \
1788 AssertRCReturn(rc, rc); \
1789 } while(0)
1790
1791 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1792 {
1793 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1794 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1795
1796 APIC_REG_COUNTER(&pApicCpu->StatMmioReadRZ, "Number of APIC MMIO reads in RZ.", "/Devices/APIC/%u/RZ/MmioRead");
1797 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteRZ, "Number of APIC MMIO writes in RZ.", "/Devices/APIC/%u/RZ/MmioWrite");
1798 APIC_REG_COUNTER(&pApicCpu->StatMsrReadRZ, "Number of APIC MSR reads in RZ.", "/Devices/APIC/%u/RZ/MsrRead");
1799 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteRZ, "Number of APIC MSR writes in RZ.", "/Devices/APIC/%u/RZ/MsrWrite");
1800
1801 APIC_REG_COUNTER(&pApicCpu->StatMmioReadR3, "Number of APIC MMIO reads in R3.", "/Devices/APIC/%u/R3/MmioReadR3");
1802 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteR3, "Number of APIC MMIO writes in R3.", "/Devices/APIC/%u/R3/MmioWriteR3");
1803 APIC_REG_COUNTER(&pApicCpu->StatMsrReadR3, "Number of APIC MSR reads in R3.", "/Devices/APIC/%u/R3/MsrReadR3");
1804 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteR3, "Number of APIC MSR writes in R3.", "/Devices/APIC/%u/R3/MsrWriteR3");
1805
1806 APIC_PROF_COUNTER(&pApicCpu->StatUpdatePendingIntrs, "Profiling of APICUpdatePendingInterrupts",
1807 "/PROF/CPU%d/APIC/UpdatePendingInterrupts");
1808 APIC_PROF_COUNTER(&pApicCpu->StatPostIntr, "Profiling of APICPostInterrupt", "/PROF/CPU%d/APIC/PostInterrupt");
1809
1810 APIC_REG_COUNTER(&pApicCpu->StatPostIntrAlreadyPending, "Number of times an interrupt is already pending.",
1811 "/Devices/APIC/%u/PostInterruptAlreadyPending");
1812 APIC_REG_COUNTER(&pApicCpu->StatTimerCallback, "Number of times the timer callback is invoked.",
1813 "/Devices/APIC/%u/TimerCallback");
1814
1815 APIC_REG_COUNTER(&pApicCpu->StatTprWrite, "Number of TPR writes.", "/Devices/APIC/%u/TprWrite");
1816 APIC_REG_COUNTER(&pApicCpu->StatTprRead, "Number of TPR reads.", "/Devices/APIC/%u/TprRead");
1817 APIC_REG_COUNTER(&pApicCpu->StatEoiWrite, "Number of EOI writes.", "/Devices/APIC/%u/EoiWrite");
1818 APIC_REG_COUNTER(&pApicCpu->StatMaskedByTpr, "Number of times TPR masks an interrupt in apicGetInterrupt.",
1819 "/Devices/APIC/%u/MaskedByTpr");
1820 APIC_REG_COUNTER(&pApicCpu->StatMaskedByPpr, "Number of times PPR masks an interrupt in apicGetInterrupt.",
1821 "/Devices/APIC/%u/MaskedByPpr");
1822 APIC_REG_COUNTER(&pApicCpu->StatTimerIcrWrite, "Number of times the timer ICR is written.",
1823 "/Devices/APIC/%u/TimerIcrWrite");
1824 APIC_REG_COUNTER(&pApicCpu->StatIcrLoWrite, "Number of times the ICR Lo (send IPI) is written.",
1825 "/Devices/APIC/%u/IcrLoWrite");
1826 APIC_REG_COUNTER(&pApicCpu->StatIcrHiWrite, "Number of times the ICR Hi is written.",
1827 "/Devices/APIC/%u/IcrHiWrite");
1828 APIC_REG_COUNTER(&pApicCpu->StatIcrFullWrite, "Number of times the ICR full (send IPI, x2APIC) is written.",
1829 "/Devices/APIC/%u/IcrFullWrite");
1830 }
1831# undef APIC_PROF_COUNTER
1832# undef APIC_REG_ACCESS_COUNTER
1833#endif
1834
1835 return VINF_SUCCESS;
1836}
1837
1838
1839/**
1840 * APIC device registration structure.
1841 */
1842const PDMDEVREG g_DeviceAPIC =
1843{
1844 /* u32Version */
1845 PDM_DEVREG_VERSION,
1846 /* szName */
1847 "apic",
1848 /* szRCMod */
1849 "VMMRC.rc",
1850 /* szR0Mod */
1851 "VMMR0.r0",
1852 /* pszDescription */
1853 "Advanced Programmable Interrupt Controller",
1854 /* fFlags */
1855 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36
1856 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
1857 /* fClass */
1858 PDM_DEVREG_CLASS_PIC,
1859 /* cMaxInstances */
1860 1,
1861 /* cbInstance */
1862 sizeof(APICDEV),
1863 /* pfnConstruct */
1864 apicR3Construct,
1865 /* pfnDestruct */
1866 apicR3Destruct,
1867 /* pfnRelocate */
1868 apicR3Relocate,
1869 /* pfnMemSetup */
1870 NULL,
1871 /* pfnPowerOn */
1872 NULL,
1873 /* pfnReset */
1874 apicR3Reset,
1875 /* pfnSuspend */
1876 NULL,
1877 /* pfnResume */
1878 NULL,
1879 /* pfnAttach */
1880 NULL,
1881 /* pfnDetach */
1882 NULL,
1883 /* pfnQueryInterface. */
1884 NULL,
1885 /* pfnInitComplete */
1886 apicR3InitComplete,
1887 /* pfnPowerOff */
1888 NULL,
1889 /* pfnSoftReset */
1890 NULL,
1891 /* u32VersionEnd */
1892 PDM_DEVREG_VERSION
1893};
1894
1895#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1896
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