VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/APIC.cpp@ 62596

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1/* $Id: APIC.cpp 62460 2016-07-22 16:20:18Z vboxsync $ */
2/** @file
3 * APIC - Advanced Programmable Interrupt Controller.
4 */
5
6/*
7 * Copyright (C) 2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_APIC
23#include <VBox/log.h>
24#include "APICInternal.h"
25#include <VBox/vmm/cpum.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/ssm.h>
30#include <VBox/vmm/vm.h>
31
32
33#ifndef VBOX_DEVICE_STRUCT_TESTCASE
34
35
36/*********************************************************************************************************************************
37* Defined Constants And Macros *
38*********************************************************************************************************************************/
39/** The current APIC saved state version. */
40#define APIC_SAVED_STATE_VERSION 5
41/** VirtualBox 5.1 beta2 - pre fActiveLintX. */
42#define APIC_SAVED_STATE_VERSION_VBOX_51_BETA2 4
43/** The saved state version used by VirtualBox 5.0 and
44 * earlier. */
45#define APIC_SAVED_STATE_VERSION_VBOX_50 3
46/** The saved state version used by VirtualBox v3 and earlier.
47 * This does not include the config. */
48#define APIC_SAVED_STATE_VERSION_VBOX_30 2
49/** Some ancient version... */
50#define APIC_SAVED_STATE_VERSION_ANCIENT 1
51
52#ifdef VBOX_WITH_STATISTICS
53# define X2APIC_MSRRANGE(a_uFirst, a_uLast, a_szName) \
54 { (a_uFirst), (a_uLast), kCpumMsrRdFn_Ia32X2ApicN, kCpumMsrWrFn_Ia32X2ApicN, 0, 0, 0, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
55#else
56# define X2APIC_MSRRANGE(a_uFirst, a_uLast, a_szName) \
57 { (a_uFirst), (a_uLast), kCpumMsrRdFn_Ia32X2ApicN, kCpumMsrWrFn_Ia32X2ApicN, 0, 0, 0, 0, 0, a_szName }
58#endif
59
60
61/*********************************************************************************************************************************
62* Global Variables *
63*********************************************************************************************************************************/
64/**
65 * MSR range supported by the x2APIC.
66 * See Intel spec. 10.12.2 "x2APIC Register Availability".
67 */
68static CPUMMSRRANGE const g_MsrRange_x2Apic = X2APIC_MSRRANGE(MSR_IA32_X2APIC_START, MSR_IA32_X2APIC_END, "x2APIC range");
69#undef X2APIC_MSRRANGE
70
71/** Saved state field descriptors for XAPICPAGE. */
72static const SSMFIELD g_aXApicPageFields[] =
73{
74 SSMFIELD_ENTRY( XAPICPAGE, id.u8ApicId),
75 SSMFIELD_ENTRY( XAPICPAGE, version.all.u32Version),
76 SSMFIELD_ENTRY( XAPICPAGE, tpr.u8Tpr),
77 SSMFIELD_ENTRY( XAPICPAGE, apr.u8Apr),
78 SSMFIELD_ENTRY( XAPICPAGE, ppr.u8Ppr),
79 SSMFIELD_ENTRY( XAPICPAGE, ldr.all.u32Ldr),
80 SSMFIELD_ENTRY( XAPICPAGE, dfr.all.u32Dfr),
81 SSMFIELD_ENTRY( XAPICPAGE, svr.all.u32Svr),
82 SSMFIELD_ENTRY( XAPICPAGE, isr.u[0].u32Reg),
83 SSMFIELD_ENTRY( XAPICPAGE, isr.u[1].u32Reg),
84 SSMFIELD_ENTRY( XAPICPAGE, isr.u[2].u32Reg),
85 SSMFIELD_ENTRY( XAPICPAGE, isr.u[3].u32Reg),
86 SSMFIELD_ENTRY( XAPICPAGE, isr.u[4].u32Reg),
87 SSMFIELD_ENTRY( XAPICPAGE, isr.u[5].u32Reg),
88 SSMFIELD_ENTRY( XAPICPAGE, isr.u[6].u32Reg),
89 SSMFIELD_ENTRY( XAPICPAGE, isr.u[7].u32Reg),
90 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[0].u32Reg),
91 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[1].u32Reg),
92 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[2].u32Reg),
93 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[3].u32Reg),
94 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[4].u32Reg),
95 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[5].u32Reg),
96 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[6].u32Reg),
97 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[7].u32Reg),
98 SSMFIELD_ENTRY( XAPICPAGE, irr.u[0].u32Reg),
99 SSMFIELD_ENTRY( XAPICPAGE, irr.u[1].u32Reg),
100 SSMFIELD_ENTRY( XAPICPAGE, irr.u[2].u32Reg),
101 SSMFIELD_ENTRY( XAPICPAGE, irr.u[3].u32Reg),
102 SSMFIELD_ENTRY( XAPICPAGE, irr.u[4].u32Reg),
103 SSMFIELD_ENTRY( XAPICPAGE, irr.u[5].u32Reg),
104 SSMFIELD_ENTRY( XAPICPAGE, irr.u[6].u32Reg),
105 SSMFIELD_ENTRY( XAPICPAGE, irr.u[7].u32Reg),
106 SSMFIELD_ENTRY( XAPICPAGE, esr.all.u32Errors),
107 SSMFIELD_ENTRY( XAPICPAGE, icr_lo.all.u32IcrLo),
108 SSMFIELD_ENTRY( XAPICPAGE, icr_hi.all.u32IcrHi),
109 SSMFIELD_ENTRY( XAPICPAGE, lvt_timer.all.u32LvtTimer),
110 SSMFIELD_ENTRY( XAPICPAGE, lvt_thermal.all.u32LvtThermal),
111 SSMFIELD_ENTRY( XAPICPAGE, lvt_perf.all.u32LvtPerf),
112 SSMFIELD_ENTRY( XAPICPAGE, lvt_lint0.all.u32LvtLint0),
113 SSMFIELD_ENTRY( XAPICPAGE, lvt_lint1.all.u32LvtLint1),
114 SSMFIELD_ENTRY( XAPICPAGE, lvt_error.all.u32LvtError),
115 SSMFIELD_ENTRY( XAPICPAGE, timer_icr.u32InitialCount),
116 SSMFIELD_ENTRY( XAPICPAGE, timer_ccr.u32CurrentCount),
117 SSMFIELD_ENTRY( XAPICPAGE, timer_dcr.all.u32DivideValue),
118 SSMFIELD_ENTRY_TERM()
119};
120
121/** Saved state field descriptors for X2APICPAGE. */
122static const SSMFIELD g_aX2ApicPageFields[] =
123{
124 SSMFIELD_ENTRY(X2APICPAGE, id.u32ApicId),
125 SSMFIELD_ENTRY(X2APICPAGE, version.all.u32Version),
126 SSMFIELD_ENTRY(X2APICPAGE, tpr.u8Tpr),
127 SSMFIELD_ENTRY(X2APICPAGE, ppr.u8Ppr),
128 SSMFIELD_ENTRY(X2APICPAGE, ldr.u32LogicalApicId),
129 SSMFIELD_ENTRY(X2APICPAGE, svr.all.u32Svr),
130 SSMFIELD_ENTRY(X2APICPAGE, isr.u[0].u32Reg),
131 SSMFIELD_ENTRY(X2APICPAGE, isr.u[1].u32Reg),
132 SSMFIELD_ENTRY(X2APICPAGE, isr.u[2].u32Reg),
133 SSMFIELD_ENTRY(X2APICPAGE, isr.u[3].u32Reg),
134 SSMFIELD_ENTRY(X2APICPAGE, isr.u[4].u32Reg),
135 SSMFIELD_ENTRY(X2APICPAGE, isr.u[5].u32Reg),
136 SSMFIELD_ENTRY(X2APICPAGE, isr.u[6].u32Reg),
137 SSMFIELD_ENTRY(X2APICPAGE, isr.u[7].u32Reg),
138 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[0].u32Reg),
139 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[1].u32Reg),
140 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[2].u32Reg),
141 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[3].u32Reg),
142 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[4].u32Reg),
143 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[5].u32Reg),
144 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[6].u32Reg),
145 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[7].u32Reg),
146 SSMFIELD_ENTRY(X2APICPAGE, irr.u[0].u32Reg),
147 SSMFIELD_ENTRY(X2APICPAGE, irr.u[1].u32Reg),
148 SSMFIELD_ENTRY(X2APICPAGE, irr.u[2].u32Reg),
149 SSMFIELD_ENTRY(X2APICPAGE, irr.u[3].u32Reg),
150 SSMFIELD_ENTRY(X2APICPAGE, irr.u[4].u32Reg),
151 SSMFIELD_ENTRY(X2APICPAGE, irr.u[5].u32Reg),
152 SSMFIELD_ENTRY(X2APICPAGE, irr.u[6].u32Reg),
153 SSMFIELD_ENTRY(X2APICPAGE, irr.u[7].u32Reg),
154 SSMFIELD_ENTRY(X2APICPAGE, esr.all.u32Errors),
155 SSMFIELD_ENTRY(X2APICPAGE, icr_lo.all.u32IcrLo),
156 SSMFIELD_ENTRY(X2APICPAGE, icr_hi.u32IcrHi),
157 SSMFIELD_ENTRY(X2APICPAGE, lvt_timer.all.u32LvtTimer),
158 SSMFIELD_ENTRY(X2APICPAGE, lvt_thermal.all.u32LvtThermal),
159 SSMFIELD_ENTRY(X2APICPAGE, lvt_perf.all.u32LvtPerf),
160 SSMFIELD_ENTRY(X2APICPAGE, lvt_lint0.all.u32LvtLint0),
161 SSMFIELD_ENTRY(X2APICPAGE, lvt_lint1.all.u32LvtLint1),
162 SSMFIELD_ENTRY(X2APICPAGE, lvt_error.all.u32LvtError),
163 SSMFIELD_ENTRY(X2APICPAGE, timer_icr.u32InitialCount),
164 SSMFIELD_ENTRY(X2APICPAGE, timer_ccr.u32CurrentCount),
165 SSMFIELD_ENTRY(X2APICPAGE, timer_dcr.all.u32DivideValue),
166 SSMFIELD_ENTRY_TERM()
167};
168
169
170/**
171 * Initializes per-VCPU APIC to the state following an INIT reset
172 * ("Wait-for-SIPI" state).
173 *
174 * @param pVCpu The cross context virtual CPU structure.
175 */
176static void apicR3InitIpi(PVMCPU pVCpu)
177{
178 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
179 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
180
181 /*
182 * See Intel spec. 10.4.7.3 "Local APIC State After an INIT Reset (Wait-for-SIPI State)"
183 * and AMD spec 16.3.2 "APIC Registers".
184 *
185 * The reason we don't simply zero out the entire APIC page and only set the non-zero members
186 * is because there are some registers that are not touched by the INIT IPI (e.g. version)
187 * operation and this function is only a subset of the reset operation.
188 */
189 RT_ZERO(pXApicPage->irr);
190 RT_ZERO(pXApicPage->irr);
191 RT_ZERO(pXApicPage->isr);
192 RT_ZERO(pXApicPage->tmr);
193 RT_ZERO(pXApicPage->icr_hi);
194 RT_ZERO(pXApicPage->icr_lo);
195 RT_ZERO(pXApicPage->ldr);
196 RT_ZERO(pXApicPage->tpr);
197 RT_ZERO(pXApicPage->ppr);
198 RT_ZERO(pXApicPage->timer_icr);
199 RT_ZERO(pXApicPage->timer_ccr);
200 RT_ZERO(pXApicPage->timer_dcr);
201
202 pXApicPage->dfr.u.u4Model = XAPICDESTFORMAT_FLAT;
203 pXApicPage->dfr.u.u28ReservedMb1 = UINT32_C(0xfffffff);
204
205 /** @todo CMCI. */
206
207 RT_ZERO(pXApicPage->lvt_timer);
208 pXApicPage->lvt_timer.u.u1Mask = 1;
209
210#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
211 RT_ZERO(pXApicPage->lvt_thermal);
212 pXApicPage->lvt_thermal.u.u1Mask = 1;
213#endif
214
215 RT_ZERO(pXApicPage->lvt_perf);
216 pXApicPage->lvt_perf.u.u1Mask = 1;
217
218 RT_ZERO(pXApicPage->lvt_lint0);
219 pXApicPage->lvt_lint0.u.u1Mask = 1;
220
221 RT_ZERO(pXApicPage->lvt_lint1);
222 pXApicPage->lvt_lint1.u.u1Mask = 1;
223
224 RT_ZERO(pXApicPage->lvt_error);
225 pXApicPage->lvt_error.u.u1Mask = 1;
226
227 RT_ZERO(pXApicPage->svr);
228 pXApicPage->svr.u.u8SpuriousVector = 0xff;
229
230 /* The self-IPI register is reset to 0. See Intel spec. 10.12.5.1 "x2APIC States" */
231 PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
232 RT_ZERO(pX2ApicPage->self_ipi);
233
234 /* Clear the pending-interrupt bitmaps. */
235 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
236 RT_BZERO(&pApicCpu->ApicPibLevel, sizeof(APICPIB));
237 RT_BZERO(pApicCpu->pvApicPibR3, sizeof(APICPIB));
238
239 /* Clear the interrupt line states for LINT0 and LINT1 pins. */
240 pApicCpu->fActiveLint0 = false;
241 pApicCpu->fActiveLint1 = false;
242}
243
244
245/**
246 * Resets the APIC base MSR.
247 *
248 * @param pVCpu The cross context virtual CPU structure.
249 */
250static void apicR3ResetBaseMsr(PVMCPU pVCpu)
251{
252 /*
253 * Initialize the APIC base MSR. The APIC enable-bit is set upon power-up or reset[1].
254 *
255 * A Reset (in xAPIC and x2APIC mode) brings up the local APIC in xAPIC mode.
256 * An INIT IPI does -not- cause a transition between xAPIC and x2APIC mode[2].
257 *
258 * [1] See AMD spec. 14.1.3 "Processor Initialization State"
259 * [2] See Intel spec. 10.12.5.1 "x2APIC States".
260 */
261 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
262
263 /* Construct. */
264 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
265 PAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
266 uint64_t uApicBaseMsr = MSR_IA32_APICBASE_ADDR;
267 if (pVCpu->idCpu == 0)
268 uApicBaseMsr |= MSR_IA32_APICBASE_BSP;
269
270 /* If the VM was configured with no APIC, don't enable xAPIC mode, obviously. */
271 if (pApic->enmMaxMode != PDMAPICMODE_NONE)
272 {
273 uApicBaseMsr |= MSR_IA32_APICBASE_EN;
274
275 /*
276 * While coming out of a reset the APIC is enabled and in xAPIC mode. If software had previously
277 * disabled the APIC (which results in the CPUID bit being cleared as well) we re-enable it here.
278 * See Intel spec. 10.12.5.1 "x2APIC States".
279 */
280 if (CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, true /*fVisible*/) == false)
281 LogRel(("APIC%u: Resetting mode to xAPIC\n", pVCpu->idCpu));
282 }
283
284 /* Commit. */
285 ASMAtomicWriteU64(&pApicCpu->uApicBaseMsr, uApicBaseMsr);
286}
287
288
289/**
290 * Initializes per-VCPU APIC to the state following a power-up or hardware
291 * reset.
292 *
293 * @param pVCpu The cross context virtual CPU structure.
294 * @param fResetApicBaseMsr Whether to reset the APIC base MSR.
295 */
296VMMR3_INT_DECL(void) apicR3ResetCpu(PVMCPU pVCpu, bool fResetApicBaseMsr)
297{
298 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
299
300 LogFlow(("APIC%u: apicR3ResetCpu: fResetApicBaseMsr=%RTbool\n", pVCpu->idCpu, fResetApicBaseMsr));
301
302#ifdef VBOX_STRICT
303 /* Verify that the initial APIC ID reported via CPUID matches our VMCPU ID assumption. */
304 uint32_t uEax, uEbx, uEcx, uEdx;
305 uEax = uEbx = uEcx = uEdx = UINT32_MAX;
306 CPUMGetGuestCpuId(pVCpu, 1, 0, &uEax, &uEbx, &uEcx, &uEdx);
307 Assert(((uEbx >> 24) & 0xff) == pVCpu->idCpu);
308#endif
309
310 /*
311 * The state following a power-up or reset is a superset of the INIT state.
312 * See Intel spec. 10.4.7.3 "Local APIC State After an INIT Reset ('Wait-for-SIPI' State)"
313 */
314 apicR3InitIpi(pVCpu);
315
316 /*
317 * The APIC version register is read-only, so just initialize it here.
318 * It is not clear from the specs, where exactly it is initialized.
319 * The version determines the number of LVT entries and size of the APIC ID (8 bits for P4).
320 */
321 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
322#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
323 pXApicPage->version.u.u8MaxLvtEntry = XAPIC_MAX_LVT_ENTRIES_P4 - 1;
324 pXApicPage->version.u.u8Version = XAPIC_HARDWARE_VERSION_P4;
325 AssertCompile(sizeof(pXApicPage->id.u8ApicId) >= XAPIC_APIC_ID_BIT_COUNT_P4 / 8);
326#else
327# error "Implement Pentium and P6 family APIC architectures"
328#endif
329
330 /** @todo It isn't clear in the spec. where exactly the default base address
331 * is (re)initialized, atm we do it here in Reset. */
332 if (fResetApicBaseMsr)
333 apicR3ResetBaseMsr(pVCpu);
334
335 /*
336 * Initialize the APIC ID register to xAPIC format.
337 */
338 ASMMemZero32(&pXApicPage->id, sizeof(pXApicPage->id));
339 pXApicPage->id.u8ApicId = pVCpu->idCpu;
340}
341
342
343/**
344 * Receives an INIT IPI.
345 *
346 * @param pVCpu The cross context virtual CPU structure.
347 */
348VMMR3_INT_DECL(void) APICR3InitIpi(PVMCPU pVCpu)
349{
350 VMCPU_ASSERT_EMT(pVCpu);
351 LogFlow(("APIC%u: APICR3InitIpi\n", pVCpu->idCpu));
352 apicR3InitIpi(pVCpu);
353}
354
355
356/**
357 * Helper for dumping an APIC 256-bit sparse register.
358 *
359 * @param pApicReg The APIC 256-bit spare register.
360 * @param pHlp The debug output helper.
361 */
362static void apicR3DbgInfo256BitReg(volatile const XAPIC256BITREG *pApicReg, PCDBGFINFOHLP pHlp)
363{
364 ssize_t const cFragments = RT_ELEMENTS(pApicReg->u);
365 unsigned const cBitsPerFragment = sizeof(pApicReg->u[0].u32Reg) * 8;
366 XAPIC256BITREG ApicReg;
367 RT_ZERO(ApicReg);
368
369 pHlp->pfnPrintf(pHlp, " ");
370 for (ssize_t i = cFragments - 1; i >= 0; i--)
371 {
372 uint32_t const uFragment = pApicReg->u[i].u32Reg;
373 ApicReg.u[i].u32Reg = uFragment;
374 pHlp->pfnPrintf(pHlp, "%08x", uFragment);
375 }
376 pHlp->pfnPrintf(pHlp, "\n");
377
378 uint32_t cPending = 0;
379 pHlp->pfnPrintf(pHlp, " Pending:");
380 for (ssize_t i = cFragments - 1; i >= 0; i--)
381 {
382 uint32_t uFragment = ApicReg.u[i].u32Reg;
383 if (uFragment)
384 {
385 do
386 {
387 unsigned idxSetBit = ASMBitLastSetU32(uFragment);
388 --idxSetBit;
389 ASMBitClear(&uFragment, idxSetBit);
390
391 idxSetBit += (i * cBitsPerFragment);
392 pHlp->pfnPrintf(pHlp, " %#02x", idxSetBit);
393 ++cPending;
394 } while (uFragment);
395 }
396 }
397 if (!cPending)
398 pHlp->pfnPrintf(pHlp, " None");
399 pHlp->pfnPrintf(pHlp, "\n");
400}
401
402
403/**
404 * Helper for dumping an APIC pending-interrupt bitmap.
405 *
406 * @param pApicPib The pending-interrupt bitmap.
407 * @param pHlp The debug output helper.
408 */
409static void apicR3DbgInfoPib(PCAPICPIB pApicPib, PCDBGFINFOHLP pHlp)
410{
411 /* Copy the pending-interrupt bitmap as an APIC 256-bit sparse register. */
412 XAPIC256BITREG ApicReg;
413 RT_ZERO(ApicReg);
414 ssize_t const cFragmentsDst = RT_ELEMENTS(ApicReg.u);
415 ssize_t const cFragmentsSrc = RT_ELEMENTS(pApicPib->aVectorBitmap);
416 AssertCompile(RT_ELEMENTS(ApicReg.u) == 2 * RT_ELEMENTS(pApicPib->aVectorBitmap));
417 for (ssize_t idxPib = cFragmentsSrc - 1, idxReg = cFragmentsDst - 1; idxPib >= 0; idxPib--, idxReg -= 2)
418 {
419 uint64_t const uFragment = pApicPib->aVectorBitmap[idxPib];
420 uint32_t const uFragmentLo = RT_LO_U32(uFragment);
421 uint32_t const uFragmentHi = RT_HI_U32(uFragment);
422 ApicReg.u[idxReg].u32Reg = uFragmentHi;
423 ApicReg.u[idxReg - 1].u32Reg = uFragmentLo;
424 }
425
426 /* Dump it. */
427 apicR3DbgInfo256BitReg(&ApicReg, pHlp);
428}
429
430
431/**
432 * Dumps basic APIC state.
433 *
434 * @param pVM The cross context VM structure.
435 * @param pHlp The info helpers.
436 * @param pszArgs Arguments, ignored.
437 */
438static DECLCALLBACK(void) apicR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
439{
440 NOREF(pszArgs);
441 PVMCPU pVCpu = VMMGetCpu(pVM);
442 if (!pVCpu)
443 pVCpu = &pVM->aCpus[0];
444
445 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
446 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
447 PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
448
449 uint64_t const uBaseMsr = pApicCpu->uApicBaseMsr;
450 APICMODE const enmMode = apicGetMode(uBaseMsr);
451 bool const fX2ApicMode = XAPIC_IN_X2APIC_MODE(pVCpu);
452
453 pHlp->pfnPrintf(pHlp, "APIC%u:\n", pVCpu->idCpu);
454 pHlp->pfnPrintf(pHlp, " APIC Base MSR = %#RX64 (Addr=%#RX64)\n", uBaseMsr,
455 MSR_IA32_APICBASE_GET_ADDR(uBaseMsr));
456 pHlp->pfnPrintf(pHlp, " Mode = %u (%s)\n", enmMode, apicGetModeName(enmMode));
457 if (fX2ApicMode)
458 {
459 pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pX2ApicPage->id.u32ApicId,
460 pX2ApicPage->id.u32ApicId);
461 }
462 else
463 pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pXApicPage->id.u8ApicId, pXApicPage->id.u8ApicId);
464 pHlp->pfnPrintf(pHlp, " Version = %#x\n", pXApicPage->version.all.u32Version);
465 pHlp->pfnPrintf(pHlp, " APIC Version = %#x\n", pXApicPage->version.u.u8Version);
466 pHlp->pfnPrintf(pHlp, " Max LVT entry index (0..N) = %u\n", pXApicPage->version.u.u8MaxLvtEntry);
467 pHlp->pfnPrintf(pHlp, " EOI Broadcast supression = %RTbool\n", pXApicPage->version.u.fEoiBroadcastSupression);
468 if (!fX2ApicMode)
469 pHlp->pfnPrintf(pHlp, " APR = %u (%#x)\n", pXApicPage->apr.u8Apr, pXApicPage->apr.u8Apr);
470 pHlp->pfnPrintf(pHlp, " TPR = %u (%#x)\n", pXApicPage->tpr.u8Tpr, pXApicPage->tpr.u8Tpr);
471 pHlp->pfnPrintf(pHlp, " Task-priority class = %#x\n", XAPIC_TPR_GET_TP(pXApicPage->tpr.u8Tpr) >> 4);
472 pHlp->pfnPrintf(pHlp, " Task-priority subclass = %#x\n", XAPIC_TPR_GET_TP_SUBCLASS(pXApicPage->tpr.u8Tpr));
473 pHlp->pfnPrintf(pHlp, " PPR = %u (%#x)\n", pXApicPage->ppr.u8Ppr, pXApicPage->ppr.u8Ppr);
474 pHlp->pfnPrintf(pHlp, " Processor-priority class = %#x\n", XAPIC_PPR_GET_PP(pXApicPage->ppr.u8Ppr) >> 4);
475 pHlp->pfnPrintf(pHlp, " Processor-priority subclass = %#x\n", XAPIC_PPR_GET_PP_SUBCLASS(pXApicPage->ppr.u8Ppr));
476 if (!fX2ApicMode)
477 pHlp->pfnPrintf(pHlp, " RRD = %u (%#x)\n", pXApicPage->rrd.u32Rrd, pXApicPage->rrd.u32Rrd);
478 pHlp->pfnPrintf(pHlp, " LDR = %#x\n", pXApicPage->ldr.all.u32Ldr);
479 pHlp->pfnPrintf(pHlp, " Logical APIC ID = %#x\n", fX2ApicMode ? pX2ApicPage->ldr.u32LogicalApicId
480 : pXApicPage->ldr.u.u8LogicalApicId);
481 if (!fX2ApicMode)
482 {
483 pHlp->pfnPrintf(pHlp, " DFR = %#x\n", pXApicPage->dfr.all.u32Dfr);
484 pHlp->pfnPrintf(pHlp, " Model = %#x (%s)\n", pXApicPage->dfr.u.u4Model,
485 apicGetDestFormatName((XAPICDESTFORMAT)pXApicPage->dfr.u.u4Model));
486 }
487 pHlp->pfnPrintf(pHlp, " SVR = %#x\n", pXApicPage->svr.all.u32Svr);
488 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->svr.u.u8SpuriousVector,
489 pXApicPage->svr.u.u8SpuriousVector);
490 pHlp->pfnPrintf(pHlp, " Software Enabled = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fApicSoftwareEnable));
491 pHlp->pfnPrintf(pHlp, " Supress EOI broadcast = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fSupressEoiBroadcast));
492 pHlp->pfnPrintf(pHlp, " ISR\n");
493 apicR3DbgInfo256BitReg(&pXApicPage->isr, pHlp);
494 pHlp->pfnPrintf(pHlp, " TMR\n");
495 apicR3DbgInfo256BitReg(&pXApicPage->tmr, pHlp);
496 pHlp->pfnPrintf(pHlp, " IRR\n");
497 apicR3DbgInfo256BitReg(&pXApicPage->irr, pHlp);
498 pHlp->pfnPrintf(pHlp, " PIB\n");
499 apicR3DbgInfoPib((PCAPICPIB)pApicCpu->pvApicPibR3, pHlp);
500 pHlp->pfnPrintf(pHlp, " Level PIB\n");
501 apicR3DbgInfoPib(&pApicCpu->ApicPibLevel, pHlp);
502 pHlp->pfnPrintf(pHlp, " ESR Internal = %#x\n", pApicCpu->uEsrInternal);
503 pHlp->pfnPrintf(pHlp, " ESR = %#x\n", pXApicPage->esr.all.u32Errors);
504 pHlp->pfnPrintf(pHlp, " Redirectable IPI = %RTbool\n", pXApicPage->esr.u.fRedirectableIpi);
505 pHlp->pfnPrintf(pHlp, " Send Illegal Vector = %RTbool\n", pXApicPage->esr.u.fSendIllegalVector);
506 pHlp->pfnPrintf(pHlp, " Recv Illegal Vector = %RTbool\n", pXApicPage->esr.u.fRcvdIllegalVector);
507 pHlp->pfnPrintf(pHlp, " Illegal Register Address = %RTbool\n", pXApicPage->esr.u.fIllegalRegAddr);
508 pHlp->pfnPrintf(pHlp, " ICR Low = %#x\n", pXApicPage->icr_lo.all.u32IcrLo);
509 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->icr_lo.u.u8Vector,
510 pXApicPage->icr_lo.u.u8Vector);
511 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u3DeliveryMode,
512 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->icr_lo.u.u3DeliveryMode));
513 pHlp->pfnPrintf(pHlp, " Destination Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u1DestMode,
514 apicGetDestModeName((XAPICDESTMODE)pXApicPage->icr_lo.u.u1DestMode));
515 if (!fX2ApicMode)
516 pHlp->pfnPrintf(pHlp, " Delivery Status = %u\n", pXApicPage->icr_lo.u.u1DeliveryStatus);
517 pHlp->pfnPrintf(pHlp, " Level = %u\n", pXApicPage->icr_lo.u.u1Level);
518 pHlp->pfnPrintf(pHlp, " Trigger Mode = %u (%s)\n", pXApicPage->icr_lo.u.u1TriggerMode,
519 apicGetTriggerModeName((XAPICTRIGGERMODE)pXApicPage->icr_lo.u.u1TriggerMode));
520 pHlp->pfnPrintf(pHlp, " Destination shorthand = %#x (%s)\n", pXApicPage->icr_lo.u.u2DestShorthand,
521 apicGetDestShorthandName((XAPICDESTSHORTHAND)pXApicPage->icr_lo.u.u2DestShorthand));
522 pHlp->pfnPrintf(pHlp, " ICR High = %#x\n", pXApicPage->icr_hi.all.u32IcrHi);
523 pHlp->pfnPrintf(pHlp, " Destination field/mask = %#x\n", fX2ApicMode ? pX2ApicPage->icr_hi.u32IcrHi
524 : pXApicPage->icr_hi.u.u8Dest);
525}
526
527
528/**
529 * Helper for dumping the LVT timer.
530 *
531 * @param pVCpu The cross context virtual CPU structure.
532 * @param pHlp The debug output helper.
533 */
534static void apicR3InfoLvtTimer(PVMCPU pVCpu, PCDBGFINFOHLP pHlp)
535{
536 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
537 uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
538 pHlp->pfnPrintf(pHlp, "LVT Timer = %#RX32\n", uLvtTimer);
539 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_timer.u.u8Vector, pXApicPage->lvt_timer.u.u8Vector);
540 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_timer.u.u1DeliveryStatus);
541 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtTimer));
542 pHlp->pfnPrintf(pHlp, " Timer Mode = %#x (%s)\n", pXApicPage->lvt_timer.u.u2TimerMode,
543 apicGetTimerModeName((XAPICTIMERMODE)pXApicPage->lvt_timer.u.u2TimerMode));
544}
545
546
547/**
548 * Dumps APIC Local Vector Table (LVT) information.
549 *
550 * @param pVM The cross context VM structure.
551 * @param pHlp The info helpers.
552 * @param pszArgs Arguments, ignored.
553 */
554static DECLCALLBACK(void) apicR3InfoLvt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
555{
556 NOREF(pszArgs);
557 PVMCPU pVCpu = VMMGetCpu(pVM);
558 if (!pVCpu)
559 pVCpu = &pVM->aCpus[0];
560
561 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
562
563 /*
564 * Delivery modes available in the LVT entries. They're different (more reserved stuff) from the
565 * ICR delivery modes and hence we don't use apicGetDeliveryMode but mostly because we want small,
566 * fixed-length strings to fit our formatting needs here.
567 */
568 static const char * const s_apszLvtDeliveryModes[] =
569 {
570 "Fixed ",
571 "Rsvd ",
572 "SMI ",
573 "Rsvd ",
574 "NMI ",
575 "INIT ",
576 "Rsvd ",
577 "ExtINT"
578 };
579 /* Delivery Status. */
580 static const char * const s_apszLvtDeliveryStatus[] =
581 {
582 "Idle",
583 "Pend"
584 };
585 const char *pszNotApplicable = "";
586
587 pHlp->pfnPrintf(pHlp, "VCPU[%u] APIC Local Vector Table (LVT):\n", pVCpu->idCpu);
588 pHlp->pfnPrintf(pHlp, "lvt timermode mask trigger rirr polarity dlvr_st dlvr_mode vector\n");
589 /* Timer. */
590 {
591 /* Timer modes. */
592 static const char * const s_apszLvtTimerModes[] =
593 {
594 "One-shot ",
595 "Periodic ",
596 "TSC-dline"
597 };
598 const uint32_t uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
599 const XAPICTIMERMODE enmTimerMode = XAPIC_LVT_GET_TIMER_MODE(uLvtTimer);
600 const char *pszTimerMode = s_apszLvtTimerModes[enmTimerMode];
601 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtTimer);
602 const uint8_t uDeliveryStatus = uLvtTimer & XAPIC_LVT_DELIVERY_STATUS;
603 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
604 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
605
606 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
607 "Timer",
608 pszTimerMode,
609 uMask,
610 pszNotApplicable, /* TriggerMode */
611 pszNotApplicable, /* Remote IRR */
612 pszNotApplicable, /* Polarity */
613 pszDeliveryStatus,
614 pszNotApplicable, /* Delivery Mode */
615 uVector,
616 uVector);
617 }
618
619#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
620 /* Thermal sensor. */
621 {
622 uint32_t const uLvtThermal = pXApicPage->lvt_thermal.all.u32LvtThermal;
623 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtThermal);
624 const uint8_t uDeliveryStatus = uLvtThermal & XAPIC_LVT_DELIVERY_STATUS;
625 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
626 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtThermal);
627 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
628 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtThermal);
629
630 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
631 "Thermal",
632 pszNotApplicable, /* Timer mode */
633 uMask,
634 pszNotApplicable, /* TriggerMode */
635 pszNotApplicable, /* Remote IRR */
636 pszNotApplicable, /* Polarity */
637 pszDeliveryStatus,
638 pszDeliveryMode,
639 uVector,
640 uVector);
641 }
642#endif
643
644 /* Performance Monitor Counters. */
645 {
646 uint32_t const uLvtPerf = pXApicPage->lvt_thermal.all.u32LvtThermal;
647 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtPerf);
648 const uint8_t uDeliveryStatus = uLvtPerf & XAPIC_LVT_DELIVERY_STATUS;
649 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
650 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtPerf);
651 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
652 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtPerf);
653
654 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
655 "Perf",
656 pszNotApplicable, /* Timer mode */
657 uMask,
658 pszNotApplicable, /* TriggerMode */
659 pszNotApplicable, /* Remote IRR */
660 pszNotApplicable, /* Polarity */
661 pszDeliveryStatus,
662 pszDeliveryMode,
663 uVector,
664 uVector);
665 }
666
667 /* LINT0, LINT1. */
668 {
669 /* LINTx name. */
670 static const char * const s_apszLvtLint[] =
671 {
672 "LINT0",
673 "LINT1"
674 };
675 /* Trigger mode. */
676 static const char * const s_apszLvtTriggerModes[] =
677 {
678 "Edge ",
679 "Level"
680 };
681 /* Polarity. */
682 static const char * const s_apszLvtPolarity[] =
683 {
684 "ActiveHi",
685 "ActiveLo"
686 };
687
688 uint32_t aLvtLint[2];
689 aLvtLint[0] = pXApicPage->lvt_lint0.all.u32LvtLint0;
690 aLvtLint[1] = pXApicPage->lvt_lint1.all.u32LvtLint1;
691 for (size_t i = 0; i < RT_ELEMENTS(aLvtLint); i++)
692 {
693 uint32_t const uLvtLint = aLvtLint[i];
694 const char *pszLint = s_apszLvtLint[i];
695 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtLint);
696 const XAPICTRIGGERMODE enmTriggerMode = XAPIC_LVT_GET_TRIGGER_MODE(uLvtLint);
697 const char *pszTriggerMode = s_apszLvtTriggerModes[enmTriggerMode];
698 const uint8_t uRemoteIrr = XAPIC_LVT_GET_REMOTE_IRR(uLvtLint);
699 const uint8_t uPolarity = XAPIC_LVT_GET_POLARITY(uLvtLint);
700 const char *pszPolarity = s_apszLvtPolarity[uPolarity];
701 const uint8_t uDeliveryStatus = uLvtLint & XAPIC_LVT_DELIVERY_STATUS;
702 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
703 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtLint);
704 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
705 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtLint);
706
707 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %u %8s %4s %6s %3u (%#x)\n",
708 pszLint,
709 pszNotApplicable, /* Timer mode */
710 uMask,
711 pszTriggerMode,
712 uRemoteIrr,
713 pszPolarity,
714 pszDeliveryStatus,
715 pszDeliveryMode,
716 uVector,
717 uVector);
718 }
719 }
720
721 /* Error. */
722 {
723 uint32_t const uLvtError = pXApicPage->lvt_thermal.all.u32LvtThermal;
724 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtError);
725 const uint8_t uDeliveryStatus = uLvtError & XAPIC_LVT_DELIVERY_STATUS;
726 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
727 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtError);
728 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
729 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtError);
730
731 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
732 "Error",
733 pszNotApplicable, /* Timer mode */
734 uMask,
735 pszNotApplicable, /* TriggerMode */
736 pszNotApplicable, /* Remote IRR */
737 pszNotApplicable, /* Polarity */
738 pszDeliveryStatus,
739 pszDeliveryMode,
740 uVector,
741 uVector);
742 }
743}
744
745
746/**
747 * Dumps the APIC timer information.
748 *
749 * @param pVM The cross context VM structure.
750 * @param pHlp The info helpers.
751 * @param pszArgs Arguments, ignored.
752 */
753static DECLCALLBACK(void) apicR3InfoTimer(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
754{
755 NOREF(pszArgs);
756 PVMCPU pVCpu = VMMGetCpu(pVM);
757 if (!pVCpu)
758 pVCpu = &pVM->aCpus[0];
759
760 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
761 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
762
763 pHlp->pfnPrintf(pHlp, "VCPU[%u] Local APIC timer:\n", pVCpu->idCpu);
764 pHlp->pfnPrintf(pHlp, " ICR = %#RX32\n", pXApicPage->timer_icr.u32InitialCount);
765 pHlp->pfnPrintf(pHlp, " CCR = %#RX32\n", pXApicPage->timer_ccr.u32CurrentCount);
766 pHlp->pfnPrintf(pHlp, " DCR = %#RX32\n", pXApicPage->timer_dcr.all.u32DivideValue);
767 pHlp->pfnPrintf(pHlp, " Timer shift = %#x\n", apicGetTimerShift(pXApicPage));
768 pHlp->pfnPrintf(pHlp, " Timer initial TS = %#RU64\n", pApicCpu->u64TimerInitial);
769 apicR3InfoLvtTimer(pVCpu, pHlp);
770}
771
772
773#ifdef APIC_FUZZY_SSM_COMPAT_TEST
774
775/**
776 * Reads a 32-bit register at a specified offset.
777 *
778 * @returns The value at the specified offset.
779 * @param pXApicPage The xAPIC page.
780 * @param offReg The offset of the register being read.
781 *
782 * @remarks Duplicate of apicReadRaw32()!
783 */
784static uint32_t apicR3ReadRawR32(PCXAPICPAGE pXApicPage, uint16_t offReg)
785{
786 Assert(offReg < sizeof(*pXApicPage) - sizeof(uint32_t));
787 uint8_t const *pbXApic = (const uint8_t *)pXApicPage;
788 uint32_t const uValue = *(const uint32_t *)(pbXApic + offReg);
789 return uValue;
790}
791
792
793/**
794 * Helper for dumping per-VCPU APIC state to the release logger.
795 *
796 * This is primarily concerned about the APIC state relevant for saved-states.
797 *
798 * @param pVCpu The cross context virtual CPU structure.
799 * @param pszPrefix A caller supplied prefix before dumping the state.
800 * @param uVersion Data layout version.
801 */
802static void apicR3DumpState(PVMCPU pVCpu, const char *pszPrefix, uint32_t uVersion)
803{
804 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
805
806 LogRel(("APIC%u: %s (version %u):\n", pVCpu->idCpu, pszPrefix, uVersion));
807
808 switch (uVersion)
809 {
810 case APIC_SAVED_STATE_VERSION:
811 case APIC_SAVED_STATE_VERSION_VBOX_51_BETA2:
812 {
813 /* The auxiliary state. */
814 LogRel(("APIC%u: uApicBaseMsr = %#RX64\n", pVCpu->idCpu, pApicCpu->uApicBaseMsr));
815 LogRel(("APIC%u: uEsrInternal = %#RX64\n", pVCpu->idCpu, pApicCpu->uEsrInternal));
816
817 /* The timer. */
818 LogRel(("APIC%u: u64TimerInitial = %#RU64\n", pVCpu->idCpu, pApicCpu->u64TimerInitial));
819 LogRel(("APIC%u: uHintedTimerInitialCount = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerInitialCount));
820 LogRel(("APIC%u: uHintedTimerShift = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerShift));
821
822 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
823 LogRel(("APIC%u: uTimerICR = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_icr.u32InitialCount));
824 LogRel(("APIC%u: uTimerCCR = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_ccr.u32CurrentCount));
825
826 /* The PIBs. */
827 LogRel(("APIC%u: Edge PIB : %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), pApicCpu->pvApicPibR3));
828 LogRel(("APIC%u: Level PIB: %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), &pApicCpu->ApicPibLevel));
829
830 /* The LINT0, LINT1 interrupt line active states. */
831 LogRel(("APIC%u: fActiveLint0 = %RTbool\n", pVCpu->idCpu, pApicCpu->fActiveLint0));
832 LogRel(("APIC%u: fActiveLint1 = %RTbool\n", pVCpu->idCpu, pApicCpu->fActiveLint1));
833
834 /* The APIC page. */
835 LogRel(("APIC%u: APIC page: %.*Rhxs\n", pVCpu->idCpu, sizeof(XAPICPAGE), pApicCpu->pvApicPageR3));
836 break;
837 }
838
839 case APIC_SAVED_STATE_VERSION_VBOX_50:
840 case APIC_SAVED_STATE_VERSION_VBOX_30:
841 case APIC_SAVED_STATE_VERSION_ANCIENT:
842 {
843 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
844 LogRel(("APIC%u: uApicBaseMsr = %#RX32\n", pVCpu->idCpu, RT_LO_U32(pApicCpu->uApicBaseMsr)));
845 LogRel(("APIC%u: uId = %#RX32\n", pVCpu->idCpu, pXApicPage->id.u8ApicId));
846 LogRel(("APIC%u: uPhysId = N/A\n", pVCpu->idCpu));
847 LogRel(("APIC%u: uArbId = N/A\n", pVCpu->idCpu));
848 LogRel(("APIC%u: uTpr = %#RX32\n", pVCpu->idCpu, pXApicPage->tpr.u8Tpr));
849 LogRel(("APIC%u: uSvr = %#RX32\n", pVCpu->idCpu, pXApicPage->svr.all.u32Svr));
850 LogRel(("APIC%u: uLdr = %#x\n", pVCpu->idCpu, pXApicPage->ldr.all.u32Ldr));
851 LogRel(("APIC%u: uDfr = %#x\n", pVCpu->idCpu, pXApicPage->dfr.all.u32Dfr));
852
853 for (size_t i = 0; i < 8; i++)
854 {
855 LogRel(("APIC%u: Isr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->isr.u[i].u32Reg));
856 LogRel(("APIC%u: Tmr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->tmr.u[i].u32Reg));
857 LogRel(("APIC%u: Irr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->irr.u[i].u32Reg));
858 }
859
860 for (size_t i = 0; i < XAPIC_MAX_LVT_ENTRIES_P4; i++)
861 {
862 uint16_t const offReg = XAPIC_OFF_LVT_START + (i << 4);
863 LogRel(("APIC%u: Lvt[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, apicR3ReadRawR32(pXApicPage, offReg)));
864 }
865
866 LogRel(("APIC%u: uEsr = %#RX32\n", pVCpu->idCpu, pXApicPage->esr.all.u32Errors));
867 LogRel(("APIC%u: uIcr_Lo = %#RX32\n", pVCpu->idCpu, pXApicPage->icr_lo.all.u32IcrLo));
868 LogRel(("APIC%u: uIcr_Hi = %#RX32\n", pVCpu->idCpu, pXApicPage->icr_hi.all.u32IcrHi));
869 LogRel(("APIC%u: uTimerDcr = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_dcr.all.u32DivideValue));
870 LogRel(("APIC%u: uCountShift = %#RX32\n", pVCpu->idCpu, apicGetTimerShift(pXApicPage)));
871 LogRel(("APIC%u: uInitialCount = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_icr.u32InitialCount));
872 LogRel(("APIC%u: u64InitialCountLoadTime = %#RX64\n", pVCpu->idCpu, pApicCpu->u64TimerInitial));
873 LogRel(("APIC%u: u64NextTime / TimerCCR = %#RX64\n", pVCpu->idCpu, pXApicPage->timer_ccr.u32CurrentCount));
874 break;
875 }
876
877 default:
878 {
879 LogRel(("APIC: apicR3DumpState: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
880 break;
881 }
882 }
883}
884
885#endif /* APIC_FUZZY_SSM_COMPAT_TEST */
886
887/**
888 * Worker for saving per-VM APIC data.
889 *
890 * @returns VBox status code.
891 * @param pVM The cross context VM structure.
892 * @param pSSM The SSM handle.
893 */
894static int apicR3SaveVMData(PVM pVM, PSSMHANDLE pSSM)
895{
896 PAPIC pApic = VM_TO_APIC(pVM);
897 SSMR3PutU32(pSSM, pVM->cCpus);
898 SSMR3PutBool(pSSM, pApic->fIoApicPresent);
899 return SSMR3PutU32(pSSM, pApic->enmMaxMode);
900}
901
902
903/**
904 * Worker for loading per-VM APIC data.
905 *
906 * @returns VBox status code.
907 * @param pVM The cross context VM structure.
908 * @param pSSM The SSM handle.
909 */
910static int apicR3LoadVMData(PVM pVM, PSSMHANDLE pSSM)
911{
912 PAPIC pApic = VM_TO_APIC(pVM);
913
914 /* Load and verify number of CPUs. */
915 uint32_t cCpus;
916 int rc = SSMR3GetU32(pSSM, &cCpus);
917 AssertRCReturn(rc, rc);
918 if (cCpus != pVM->cCpus)
919 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%u config=%u"), cCpus, pVM->cCpus);
920
921 /* Load and verify I/O APIC presence. */
922 bool fIoApicPresent;
923 rc = SSMR3GetBool(pSSM, &fIoApicPresent);
924 AssertRCReturn(rc, rc);
925 if (fIoApicPresent != pApic->fIoApicPresent)
926 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApicPresent: saved=%RTbool config=%RTbool"),
927 fIoApicPresent, pApic->fIoApicPresent);
928
929 /* Load and verify configured max APIC mode. */
930 uint32_t uSavedMaxApicMode;
931 rc = SSMR3GetU32(pSSM, &uSavedMaxApicMode);
932 AssertRCReturn(rc, rc);
933 if (uSavedMaxApicMode != (uint32_t)pApic->enmMaxMode)
934 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicMode: saved=%u config=%u"),
935 uSavedMaxApicMode, pApic->enmMaxMode);
936 return VINF_SUCCESS;
937}
938
939
940/**
941 * Worker for loading per-VCPU APIC data for legacy (old) saved-states.
942 *
943 * @returns VBox status code.
944 * @param pVM The cross context VM structure.
945 * @param pVCpu The cross context virtual CPU structure.
946 * @param pSSM The SSM handle.
947 * @param uVersion Data layout version.
948 */
949static int apicR3LoadLegacyVCpuData(PVM pVM, PVMCPU pVCpu, PSSMHANDLE pSSM, uint32_t uVersion)
950{
951 AssertReturn(uVersion <= APIC_SAVED_STATE_VERSION_VBOX_50, VERR_NOT_SUPPORTED);
952
953 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
954 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
955
956 uint32_t uApicBaseLo;
957 int rc = SSMR3GetU32(pSSM, &uApicBaseLo);
958 AssertRCReturn(rc, rc);
959 pApicCpu->uApicBaseMsr = uApicBaseLo;
960 Log2(("APIC%u: apicR3LoadLegacyVCpuData: uApicBaseMsr=%#RX64\n", pVCpu->idCpu, pApicCpu->uApicBaseMsr));
961
962 switch (uVersion)
963 {
964 case APIC_SAVED_STATE_VERSION_VBOX_50:
965 case APIC_SAVED_STATE_VERSION_VBOX_30:
966 {
967 uint32_t uApicId, uPhysApicId, uArbId;
968 SSMR3GetU32(pSSM, &uApicId); pXApicPage->id.u8ApicId = uApicId;
969 SSMR3GetU32(pSSM, &uPhysApicId); NOREF(uPhysApicId); /* PhysId == pVCpu->idCpu */
970 SSMR3GetU32(pSSM, &uArbId); NOREF(uArbId); /* ArbID is & was unused. */
971 break;
972 }
973
974 case APIC_SAVED_STATE_VERSION_ANCIENT:
975 {
976 uint8_t uPhysApicId;
977 SSMR3GetU8(pSSM, &pXApicPage->id.u8ApicId);
978 SSMR3GetU8(pSSM, &uPhysApicId); NOREF(uPhysApicId); /* PhysId == pVCpu->idCpu */
979 break;
980 }
981
982 default:
983 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
984 }
985
986 uint32_t u32Tpr;
987 SSMR3GetU32(pSSM, &u32Tpr);
988 pXApicPage->tpr.u8Tpr = u32Tpr & XAPIC_TPR_VALID;
989
990 SSMR3GetU32(pSSM, &pXApicPage->svr.all.u32Svr);
991 SSMR3GetU8(pSSM, &pXApicPage->ldr.u.u8LogicalApicId);
992
993 uint8_t uDfr;
994 SSMR3GetU8(pSSM, &uDfr);
995 pXApicPage->dfr.u.u4Model = uDfr >> 4;
996
997 AssertCompile(RT_ELEMENTS(pXApicPage->isr.u) == 8);
998 AssertCompile(RT_ELEMENTS(pXApicPage->tmr.u) == 8);
999 AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 8);
1000 for (size_t i = 0; i < 8; i++)
1001 {
1002 SSMR3GetU32(pSSM, &pXApicPage->isr.u[i].u32Reg);
1003 SSMR3GetU32(pSSM, &pXApicPage->tmr.u[i].u32Reg);
1004 SSMR3GetU32(pSSM, &pXApicPage->irr.u[i].u32Reg);
1005 }
1006
1007 SSMR3GetU32(pSSM, &pXApicPage->lvt_timer.all.u32LvtTimer);
1008 SSMR3GetU32(pSSM, &pXApicPage->lvt_thermal.all.u32LvtThermal);
1009 SSMR3GetU32(pSSM, &pXApicPage->lvt_perf.all.u32LvtPerf);
1010 SSMR3GetU32(pSSM, &pXApicPage->lvt_lint0.all.u32LvtLint0);
1011 SSMR3GetU32(pSSM, &pXApicPage->lvt_lint1.all.u32LvtLint1);
1012 SSMR3GetU32(pSSM, &pXApicPage->lvt_error.all.u32LvtError);
1013
1014 SSMR3GetU32(pSSM, &pXApicPage->esr.all.u32Errors);
1015 SSMR3GetU32(pSSM, &pXApicPage->icr_lo.all.u32IcrLo);
1016 SSMR3GetU32(pSSM, &pXApicPage->icr_hi.all.u32IcrHi);
1017
1018 uint32_t u32TimerShift;
1019 SSMR3GetU32(pSSM, &pXApicPage->timer_dcr.all.u32DivideValue);
1020 SSMR3GetU32(pSSM, &u32TimerShift);
1021 /*
1022 * Old implementation may have left the timer shift uninitialized until
1023 * the timer configuration register was written. Unfortunately zero is
1024 * also a valid timer shift value, so we're just going to ignore it
1025 * completely. The shift count can always be derived from the DCR.
1026 * See @bugref{8245#c98}.
1027 */
1028 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
1029
1030 SSMR3GetU32(pSSM, &pXApicPage->timer_icr.u32InitialCount);
1031 SSMR3GetU64(pSSM, &pApicCpu->u64TimerInitial);
1032 uint64_t uNextTS;
1033 rc = SSMR3GetU64(pSSM, &uNextTS); AssertRCReturn(rc, rc);
1034 if (uNextTS >= pApicCpu->u64TimerInitial + ((pXApicPage->timer_icr.u32InitialCount + 1) << uTimerShift))
1035 pXApicPage->timer_ccr.u32CurrentCount = pXApicPage->timer_icr.u32InitialCount;
1036
1037 rc = TMR3TimerLoad(pApicCpu->pTimerR3, pSSM);
1038 AssertRCReturn(rc, rc);
1039 Assert(pApicCpu->uHintedTimerInitialCount == 0);
1040 Assert(pApicCpu->uHintedTimerShift == 0);
1041 if (TMTimerIsActive(pApicCpu->pTimerR3))
1042 {
1043 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1044 apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
1045 }
1046
1047 return rc;
1048}
1049
1050
1051/**
1052 * @copydoc FNSSMDEVLIVEEXEC
1053 */
1054static DECLCALLBACK(int) apicR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
1055{
1056 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1057 PVM pVM = PDMDevHlpGetVM(pApicDev->pDevInsR3);
1058
1059 LogFlow(("APIC: apicR3LiveExec: uPass=%u\n", uPass));
1060
1061 int rc = apicR3SaveVMData(pVM, pSSM);
1062 AssertRCReturn(rc, rc);
1063 return VINF_SSM_DONT_CALL_AGAIN;
1064}
1065
1066
1067/**
1068 * @copydoc FNSSMDEVSAVEEXEC
1069 */
1070static DECLCALLBACK(int) apicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1071{
1072 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1073 PVM pVM = PDMDevHlpGetVM(pDevIns);
1074 PAPIC pApic = VM_TO_APIC(pVM);
1075 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
1076
1077 LogFlow(("APIC: apicR3SaveExec\n"));
1078
1079 /* Save per-VM data. */
1080 int rc = apicR3SaveVMData(pVM, pSSM);
1081 AssertRCReturn(rc, rc);
1082
1083 /* Save per-VCPU data.*/
1084 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1085 {
1086 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1087 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1088
1089 /* Update interrupts from the pending-interrupts bitmaps to the IRR. */
1090 APICUpdatePendingInterrupts(pVCpu);
1091
1092 /* Save the auxiliary data. */
1093 SSMR3PutU64(pSSM, pApicCpu->uApicBaseMsr);
1094 SSMR3PutU32(pSSM, pApicCpu->uEsrInternal);
1095
1096 /* Save the APIC page. */
1097 if (XAPIC_IN_X2APIC_MODE(pVCpu))
1098 SSMR3PutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
1099 else
1100 SSMR3PutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
1101
1102 /* Save the timer. */
1103 SSMR3PutU64(pSSM, pApicCpu->u64TimerInitial);
1104 TMR3TimerSave(pApicCpu->pTimerR3, pSSM);
1105
1106 /* Save the LINT0, LINT1 interrupt line states. */
1107 SSMR3PutBool(pSSM, pApicCpu->fActiveLint0);
1108 SSMR3PutBool(pSSM, pApicCpu->fActiveLint1);
1109
1110#if defined(APIC_FUZZY_SSM_COMPAT_TEST) || defined(DEBUG_ramshankar)
1111 apicR3DumpState(pVCpu, "Saved state", APIC_SAVED_STATE_VERSION);
1112#endif
1113 }
1114
1115#ifdef APIC_FUZZY_SSM_COMPAT_TEST
1116 /* The state is fuzzy, don't even bother trying to load the guest. */
1117 return VERR_INVALID_STATE;
1118#else
1119 return rc;
1120#endif
1121}
1122
1123
1124/**
1125 * @copydoc FNSSMDEVLOADEXEC
1126 */
1127static DECLCALLBACK(int) apicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1128{
1129 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1130 PVM pVM = PDMDevHlpGetVM(pDevIns);
1131 PAPIC pApic = VM_TO_APIC(pVM);
1132
1133 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
1134 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
1135
1136 LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1137
1138 /* Weed out invalid versions. */
1139 if ( uVersion != APIC_SAVED_STATE_VERSION
1140 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_51_BETA2
1141 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_50
1142 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_30
1143 && uVersion != APIC_SAVED_STATE_VERSION_ANCIENT)
1144 {
1145 LogRel(("APIC: apicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1146 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1147 }
1148
1149 int rc = VINF_SUCCESS;
1150 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_30)
1151 {
1152 rc = apicR3LoadVMData(pVM, pSSM);
1153 AssertRCReturn(rc, rc);
1154
1155 if (uVersion == APIC_SAVED_STATE_VERSION)
1156 { /* Load any new additional per-VM data. */ }
1157 }
1158
1159 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1160 {
1161 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1162 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1163
1164 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_50)
1165 {
1166 /* Load the auxiliary data. */
1167 SSMR3GetU64(pSSM, (uint64_t *)&pApicCpu->uApicBaseMsr);
1168 SSMR3GetU32(pSSM, &pApicCpu->uEsrInternal);
1169
1170 /* Load the APIC page. */
1171 if (XAPIC_IN_X2APIC_MODE(pVCpu))
1172 SSMR3GetStruct(pSSM, pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
1173 else
1174 SSMR3GetStruct(pSSM, pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
1175
1176 /* Load the timer. */
1177 rc = SSMR3GetU64(pSSM, &pApicCpu->u64TimerInitial); AssertRCReturn(rc, rc);
1178 rc = TMR3TimerLoad(pApicCpu->pTimerR3, pSSM); AssertRCReturn(rc, rc);
1179 Assert(pApicCpu->uHintedTimerShift == 0);
1180 Assert(pApicCpu->uHintedTimerInitialCount == 0);
1181 if (TMTimerIsActive(pApicCpu->pTimerR3))
1182 {
1183 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
1184 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1185 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
1186 apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
1187 }
1188
1189 /* Load the LINT0, LINT1 interrupt line states. */
1190 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_51_BETA2)
1191 {
1192 SSMR3GetBool(pSSM, (bool *)&pApicCpu->fActiveLint0);
1193 SSMR3GetBool(pSSM, (bool *)&pApicCpu->fActiveLint1);
1194 }
1195 }
1196 else
1197 {
1198 rc = apicR3LoadLegacyVCpuData(pVM, pVCpu, pSSM, uVersion);
1199 AssertRCReturn(rc, rc);
1200 }
1201
1202 /*
1203 * Check that we're still good wrt restored data, then tell CPUM about the current CPUID[1].EDX[9] visibility.
1204 */
1205 rc = SSMR3HandleGetStatus(pSSM);
1206 AssertRCReturn(rc, rc);
1207 CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, RT_BOOL(pApicCpu->uApicBaseMsr & MSR_IA32_APICBASE_EN));
1208
1209#if defined(APIC_FUZZY_SSM_COMPAT_TEST) || defined(DEBUG_ramshankar)
1210 apicR3DumpState(pVCpu, "Loaded state", uVersion);
1211#endif
1212 }
1213
1214 return rc;
1215}
1216
1217
1218/**
1219 * The timer callback.
1220 *
1221 * @param pDevIns The device instance.
1222 * @param pTimer The timer handle.
1223 * @param pvUser Opaque pointer to the VMCPU.
1224 *
1225 * @thread Any.
1226 * @remarks Currently this function is invoked on the last EMT, see @c
1227 * idTimerCpu in tmR3TimerCallback(). However, the code does -not-
1228 * rely on this and is designed to work with being invoked on any
1229 * thread.
1230 */
1231static DECLCALLBACK(void) apicR3TimerCallback(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1232{
1233 PVMCPU pVCpu = (PVMCPU)pvUser;
1234 Assert(TMTimerIsLockOwner(pTimer));
1235 Assert(pVCpu);
1236 LogFlow(("APIC%u: apicR3TimerCallback\n", pVCpu->idCpu));
1237
1238 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1239 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1240 uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
1241 STAM_COUNTER_INC(&pApicCpu->StatTimerCallback);
1242 if (!XAPIC_LVT_IS_MASKED(uLvtTimer))
1243 {
1244 uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
1245 Log2(("APIC%u: apicR3TimerCallback: Raising timer interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
1246 apicPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE);
1247 }
1248
1249 XAPICTIMERMODE enmTimerMode = XAPIC_LVT_GET_TIMER_MODE(uLvtTimer);
1250 switch (enmTimerMode)
1251 {
1252 case XAPICTIMERMODE_PERIODIC:
1253 {
1254 /* The initial-count register determines if the periodic timer is re-armed. */
1255 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1256 pXApicPage->timer_ccr.u32CurrentCount = uInitialCount;
1257 if (uInitialCount)
1258 {
1259 Log2(("APIC%u: apicR3TimerCallback: Re-arming timer. uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
1260 apicStartTimer(pVCpu, uInitialCount);
1261 }
1262 break;
1263 }
1264
1265 case XAPICTIMERMODE_ONESHOT:
1266 {
1267 pXApicPage->timer_ccr.u32CurrentCount = 0;
1268 break;
1269 }
1270
1271 case XAPICTIMERMODE_TSC_DEADLINE:
1272 {
1273 /** @todo implement TSC deadline. */
1274 AssertMsgFailed(("APIC: TSC deadline mode unimplemented\n"));
1275 break;
1276 }
1277 }
1278}
1279
1280
1281/**
1282 * @interface_method_impl{PDMDEVREG,pfnReset}
1283 */
1284static DECLCALLBACK(void) apicR3Reset(PPDMDEVINS pDevIns)
1285{
1286 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1287 PVM pVM = PDMDevHlpGetVM(pDevIns);
1288 VM_ASSERT_EMT0(pVM);
1289 VM_ASSERT_IS_NOT_RUNNING(pVM);
1290
1291 LogFlow(("APIC: apicR3Reset\n"));
1292
1293 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1294 {
1295 PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
1296 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpuDest);
1297
1298 if (TMTimerIsActive(pApicCpu->pTimerR3))
1299 TMTimerStop(pApicCpu->pTimerR3);
1300
1301 apicR3ResetCpu(pVCpuDest, true /* fResetApicBaseMsr */);
1302
1303 /* Clear the interrupt pending force flag. */
1304 apicClearInterruptFF(pVCpuDest, PDMAPICIRQ_HARDWARE);
1305 }
1306}
1307
1308
1309/**
1310 * @interface_method_impl{PDMDEVREG,pfnRelocate}
1311 */
1312static DECLCALLBACK(void) apicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1313{
1314 PVM pVM = PDMDevHlpGetVM(pDevIns);
1315 PAPIC pApic = VM_TO_APIC(pVM);
1316 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1317
1318 LogFlow(("APIC: apicR3Relocate: pVM=%p pDevIns=%p offDelta=%RGi\n", pVM, pDevIns, offDelta));
1319
1320 pApicDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1321 pApicDev->pApicHlpRC = pApicDev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
1322 pApicDev->pCritSectRC = pApicDev->pApicHlpR3->pfnGetRCCritSect(pDevIns);
1323
1324 pApic->pApicDevRC = PDMINS_2_DATA_RCPTR(pDevIns);
1325 pApic->pvApicPibRC += offDelta;
1326
1327 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1328 {
1329 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1330 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1331 pApicCpu->pTimerRC = TMTimerRCPtr(pApicCpu->pTimerR3);
1332
1333 pApicCpu->pvApicPageRC += offDelta;
1334 pApicCpu->pvApicPibRC += offDelta;
1335 Log2(("APIC%u: apicR3Relocate: APIC PIB at %RGv\n", pVCpu->idCpu, pApicCpu->pvApicPibRC));
1336 }
1337}
1338
1339
1340/**
1341 * Terminates the APIC state.
1342 *
1343 * @param pVM The cross context VM structure.
1344 */
1345static void apicR3TermState(PVM pVM)
1346{
1347 PAPIC pApic = VM_TO_APIC(pVM);
1348 LogFlow(("APIC: apicR3TermState: pVM=%p\n", pVM));
1349
1350 /* Unmap and free the PIB. */
1351 if (pApic->pvApicPibR3 != NIL_RTR3PTR)
1352 {
1353 size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
1354 if (cPages == 1)
1355 SUPR3PageFreeEx(pApic->pvApicPibR3, cPages);
1356 else
1357 SUPR3ContFree(pApic->pvApicPibR3, cPages);
1358 pApic->pvApicPibR3 = NIL_RTR3PTR;
1359 pApic->pvApicPibR0 = NIL_RTR0PTR;
1360 pApic->pvApicPibRC = NIL_RTRCPTR;
1361 }
1362
1363 /* Unmap and free the virtual-APIC pages. */
1364 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1365 {
1366 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1367 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1368
1369 pApicCpu->pvApicPibR3 = NIL_RTR3PTR;
1370 pApicCpu->pvApicPibR0 = NIL_RTR0PTR;
1371 pApicCpu->pvApicPibRC = NIL_RTRCPTR;
1372
1373 if (pApicCpu->pvApicPageR3 != NIL_RTR3PTR)
1374 {
1375 SUPR3PageFreeEx(pApicCpu->pvApicPageR3, 1 /* cPages */);
1376 pApicCpu->pvApicPageR3 = NIL_RTR3PTR;
1377 pApicCpu->pvApicPageR0 = NIL_RTR0PTR;
1378 pApicCpu->pvApicPageRC = NIL_RTRCPTR;
1379 }
1380 }
1381}
1382
1383
1384/**
1385 * Initializes the APIC state.
1386 *
1387 * @returns VBox status code.
1388 * @param pVM The cross context VM structure.
1389 */
1390static int apicR3InitState(PVM pVM)
1391{
1392 PAPIC pApic = VM_TO_APIC(pVM);
1393 LogFlow(("APIC: apicR3InitState: pVM=%p\n", pVM));
1394
1395 /* With hardware virtualization, we don't need to map the APIC in GC. */
1396 bool const fNeedsGCMapping = !HMIsEnabled(pVM);
1397
1398 /*
1399 * Allocate and map the pending-interrupt bitmap (PIB).
1400 *
1401 * We allocate all the VCPUs' PIBs contiguously in order to save space as
1402 * physically contiguous allocations are rounded to a multiple of page size.
1403 */
1404 Assert(pApic->pvApicPibR3 == NIL_RTR3PTR);
1405 Assert(pApic->pvApicPibR0 == NIL_RTR0PTR);
1406 Assert(pApic->pvApicPibRC == NIL_RTRCPTR);
1407 pApic->cbApicPib = RT_ALIGN_Z(pVM->cCpus * sizeof(APICPIB), PAGE_SIZE);
1408 size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
1409 if (cPages == 1)
1410 {
1411 SUPPAGE SupApicPib;
1412 RT_ZERO(SupApicPib);
1413 SupApicPib.Phys = NIL_RTHCPHYS;
1414 int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, &pApic->pvApicPibR3, &pApic->pvApicPibR0, &SupApicPib);
1415 if (RT_SUCCESS(rc))
1416 {
1417 pApic->HCPhysApicPib = SupApicPib.Phys;
1418 AssertLogRelReturn(pApic->pvApicPibR3, VERR_INTERNAL_ERROR);
1419 }
1420 else
1421 {
1422 LogRel(("APIC: Failed to allocate %u bytes for the pending-interrupt bitmap, rc=%Rrc\n", pApic->cbApicPib, rc));
1423 return rc;
1424 }
1425 }
1426 else
1427 pApic->pvApicPibR3 = SUPR3ContAlloc(cPages, &pApic->pvApicPibR0, &pApic->HCPhysApicPib);
1428
1429 if (pApic->pvApicPibR3)
1430 {
1431 AssertLogRelReturn(pApic->pvApicPibR0 != NIL_RTR0PTR, VERR_INTERNAL_ERROR);
1432 AssertLogRelReturn(pApic->HCPhysApicPib != NIL_RTHCPHYS, VERR_INTERNAL_ERROR);
1433
1434 /* Initialize the PIB. */
1435 RT_BZERO(pApic->pvApicPibR3, pApic->cbApicPib);
1436
1437 /* Map the PIB into GC. */
1438 if (fNeedsGCMapping)
1439 {
1440 pApic->pvApicPibRC = NIL_RTRCPTR;
1441 int rc = MMR3HyperMapHCPhys(pVM, pApic->pvApicPibR3, NIL_RTR0PTR, pApic->HCPhysApicPib, pApic->cbApicPib,
1442 "APIC PIB", (PRTGCPTR)&pApic->pvApicPibRC);
1443 if (RT_FAILURE(rc))
1444 {
1445 LogRel(("APIC: Failed to map %u bytes for the pending-interrupt bitmap into GC, rc=%Rrc\n", pApic->cbApicPib,
1446 rc));
1447 apicR3TermState(pVM);
1448 return rc;
1449 }
1450
1451 AssertLogRelReturn(pApic->pvApicPibRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
1452 }
1453
1454 /*
1455 * Allocate the map the virtual-APIC pages.
1456 */
1457 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1458 {
1459 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1460 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1461
1462 SUPPAGE SupApicPage;
1463 RT_ZERO(SupApicPage);
1464 SupApicPage.Phys = NIL_RTHCPHYS;
1465
1466 Assert(pVCpu->idCpu == idCpu);
1467 Assert(pApicCpu->pvApicPageR3 == NIL_RTR0PTR);
1468 Assert(pApicCpu->pvApicPageR0 == NIL_RTR0PTR);
1469 Assert(pApicCpu->pvApicPageRC == NIL_RTRCPTR);
1470 AssertCompile(sizeof(XAPICPAGE) == PAGE_SIZE);
1471 pApicCpu->cbApicPage = sizeof(XAPICPAGE);
1472 int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, &pApicCpu->pvApicPageR3, &pApicCpu->pvApicPageR0,
1473 &SupApicPage);
1474 if (RT_SUCCESS(rc))
1475 {
1476 AssertLogRelReturn(pApicCpu->pvApicPageR3 != NIL_RTR3PTR, VERR_INTERNAL_ERROR);
1477 AssertLogRelReturn(pApicCpu->HCPhysApicPage != NIL_RTHCPHYS, VERR_INTERNAL_ERROR);
1478 pApicCpu->HCPhysApicPage = SupApicPage.Phys;
1479
1480 /* Map the virtual-APIC page into GC. */
1481 if (fNeedsGCMapping)
1482 {
1483 rc = MMR3HyperMapHCPhys(pVM, pApicCpu->pvApicPageR3, NIL_RTR0PTR, pApicCpu->HCPhysApicPage,
1484 pApicCpu->cbApicPage, "APIC", (PRTGCPTR)&pApicCpu->pvApicPageRC);
1485 if (RT_FAILURE(rc))
1486 {
1487 LogRel(("APIC%u: Failed to map %u bytes for the virtual-APIC page into GC, rc=%Rrc", idCpu,
1488 pApicCpu->cbApicPage, rc));
1489 apicR3TermState(pVM);
1490 return rc;
1491 }
1492
1493 AssertLogRelReturn(pApicCpu->pvApicPageRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
1494 }
1495
1496 /* Associate the per-VCPU PIB pointers to the per-VM PIB mapping. */
1497 uint32_t const offApicPib = idCpu * sizeof(APICPIB);
1498 pApicCpu->pvApicPibR0 = (RTR0PTR)((RTR0UINTPTR)pApic->pvApicPibR0 + offApicPib);
1499 pApicCpu->pvApicPibR3 = (RTR3PTR)((RTR3UINTPTR)pApic->pvApicPibR3 + offApicPib);
1500 if (fNeedsGCMapping)
1501 pApicCpu->pvApicPibRC = (RTRCPTR)((RTRCUINTPTR)pApic->pvApicPibRC + offApicPib);
1502
1503 /* Initialize the virtual-APIC state. */
1504 RT_BZERO(pApicCpu->pvApicPageR3, pApicCpu->cbApicPage);
1505 apicR3ResetCpu(pVCpu, true /* fResetApicBaseMsr */);
1506
1507#ifdef DEBUG_ramshankar
1508 Assert(pApicCpu->pvApicPibR3 != NIL_RTR3PTR);
1509 Assert(pApicCpu->pvApicPibR0 != NIL_RTR0PTR);
1510 Assert(!fNeedsGCMapping || pApicCpu->pvApicPibRC != NIL_RTRCPTR);
1511 Assert(pApicCpu->pvApicPageR3 != NIL_RTR3PTR);
1512 Assert(pApicCpu->pvApicPageR0 != NIL_RTR0PTR);
1513 Assert(!fNeedsGCMapping || pApicCpu->pvApicPageRC != NIL_RTRCPTR);
1514 Assert(!fNeedsGCMapping || pApic->pvApicPibRC == pVM->aCpus[0].apic.s.pvApicPibRC);
1515#endif
1516 }
1517 else
1518 {
1519 LogRel(("APIC%u: Failed to allocate %u bytes for the virtual-APIC page, rc=%Rrc\n", idCpu, pApicCpu->cbApicPage, rc));
1520 apicR3TermState(pVM);
1521 return rc;
1522 }
1523 }
1524
1525#ifdef DEBUG_ramshankar
1526 Assert(pApic->pvApicPibR3 != NIL_RTR3PTR);
1527 Assert(pApic->pvApicPibR0 != NIL_RTR0PTR);
1528 Assert(!fNeedsGCMapping || pApic->pvApicPibRC != NIL_RTRCPTR);
1529#endif
1530 return VINF_SUCCESS;
1531 }
1532
1533 LogRel(("APIC: Failed to allocate %u bytes of physically contiguous memory for the pending-interrupt bitmap\n",
1534 pApic->cbApicPib));
1535 return VERR_NO_MEMORY;
1536}
1537
1538
1539/**
1540 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1541 */
1542static DECLCALLBACK(int) apicR3Destruct(PPDMDEVINS pDevIns)
1543{
1544 PVM pVM = PDMDevHlpGetVM(pDevIns);
1545 LogFlow(("APIC: apicR3Destruct: pVM=%p\n", pVM));
1546
1547 apicR3TermState(pVM);
1548 return VINF_SUCCESS;
1549}
1550
1551
1552/**
1553 * @interface_method_impl{PDMDEVREG,pfnInitComplete}
1554 */
1555static DECLCALLBACK(int) apicR3InitComplete(PPDMDEVINS pDevIns)
1556{
1557 PVM pVM = PDMDevHlpGetVM(pDevIns);
1558 PAPIC pApic = VM_TO_APIC(pVM);
1559
1560 /*
1561 * Init APIC settings that rely on HM and CPUM configurations.
1562 */
1563 CPUMCPUIDLEAF CpuLeaf;
1564 int rc = CPUMR3CpuIdGetLeaf(pVM, &CpuLeaf, 1, 0);
1565 AssertRCReturn(rc, rc);
1566
1567 pApic->fSupportsTscDeadline = RT_BOOL(CpuLeaf.uEcx & X86_CPUID_FEATURE_ECX_TSCDEADL);
1568 pApic->fPostedIntrsEnabled = HMR3IsPostedIntrsEnabled(pVM->pUVM);
1569 pApic->fVirtApicRegsEnabled = HMR3IsVirtApicRegsEnabled(pVM->pUVM);
1570
1571 LogRel(("APIC: fPostedIntrsEnabled=%RTbool fVirtApicRegsEnabled=%RTbool fSupportsTscDeadline=%RTbool\n",
1572 pApic->fPostedIntrsEnabled, pApic->fVirtApicRegsEnabled, pApic->fSupportsTscDeadline));
1573
1574 return VINF_SUCCESS;
1575}
1576
1577
1578/**
1579 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1580 */
1581static DECLCALLBACK(int) apicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1582{
1583 /*
1584 * Validate inputs.
1585 */
1586 Assert(iInstance == 0);
1587 Assert(pDevIns);
1588
1589 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1590 PVM pVM = PDMDevHlpGetVM(pDevIns);
1591 PAPIC pApic = VM_TO_APIC(pVM);
1592
1593 /*
1594 * Init the data.
1595 */
1596 pApicDev->pDevInsR3 = pDevIns;
1597 pApicDev->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1598 pApicDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1599
1600 pApic->pApicDevR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1601 pApic->pApicDevR3 = (PAPICDEV)PDMINS_2_DATA_R3PTR(pDevIns);
1602 pApic->pApicDevRC = PDMINS_2_DATA_RCPTR(pDevIns);
1603
1604 /*
1605 * Validate APIC settings.
1606 */
1607 if (!CFGMR3AreValuesValid(pCfg, "RZEnabled\0"
1608 "Mode\0"
1609 "IOAPIC\0"
1610 "NumCPUs\0"))
1611 {
1612 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1613 N_("APIC configuration error: unknown option specified"));
1614 }
1615
1616 int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pApic->fRZEnabled, true);
1617 AssertLogRelRCReturn(rc, rc);
1618
1619 rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &pApic->fIoApicPresent, true);
1620 AssertLogRelRCReturn(rc, rc);
1621
1622 /* Max APIC feature level. */
1623 uint8_t uMaxMode;
1624 rc = CFGMR3QueryU8Def(pCfg, "Mode", &uMaxMode, PDMAPICMODE_APIC);
1625 AssertLogRelRCReturn(rc, rc);
1626 switch ((PDMAPICMODE)uMaxMode)
1627 {
1628 case PDMAPICMODE_NONE:
1629#if 1
1630 /** @todo permanently disabling the APIC won't really work (needs
1631 * fixing in HM, CPUM, PDM and possibly other places). See
1632 * @bugref{8353}. */
1633 return VMR3SetError(pVM->pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, "APIC mode 'none' is not supported yet.");
1634#endif
1635 case PDMAPICMODE_APIC:
1636 case PDMAPICMODE_X2APIC:
1637 break;
1638 default:
1639 return VMR3SetError(pVM->pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, "APIC mode %d unknown.", uMaxMode);
1640 }
1641 pApic->enmMaxMode = (PDMAPICMODE)uMaxMode;
1642
1643 /*
1644 * Disable automatic PDM locking for this device.
1645 */
1646 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1647 AssertRCReturn(rc, rc);
1648
1649 /*
1650 * Register the APIC with PDM.
1651 */
1652 PDMAPICREG ApicReg;
1653 RT_ZERO(ApicReg);
1654 ApicReg.u32Version = PDM_APICREG_VERSION;
1655 ApicReg.pfnGetInterruptR3 = apicGetInterrupt;
1656 ApicReg.pfnSetBaseMsrR3 = apicSetBaseMsr;
1657 ApicReg.pfnGetBaseMsrR3 = apicGetBaseMsr;
1658 ApicReg.pfnSetTprR3 = apicSetTpr;
1659 ApicReg.pfnGetTprR3 = apicGetTpr;
1660 ApicReg.pfnWriteMsrR3 = apicWriteMsr;
1661 ApicReg.pfnReadMsrR3 = apicReadMsr;
1662 ApicReg.pfnBusDeliverR3 = apicBusDeliver;
1663 ApicReg.pfnLocalInterruptR3 = apicLocalInterrupt;
1664 ApicReg.pfnGetTimerFreqR3 = apicGetTimerFreq;
1665
1666 /*
1667 * We always require R0 functionality (e.g. apicGetTpr() called by HMR0 VT-x/AMD-V code).
1668 * Hence, 'fRZEnabled' strictly only applies to MMIO and MSR read/write handlers returning
1669 * to ring-3. We still need other handlers like apicGetTpr() in ring-0 for now.
1670 */
1671 {
1672 ApicReg.pszGetInterruptRC = "apicGetInterrupt";
1673 ApicReg.pszSetBaseMsrRC = "apicSetBaseMsr";
1674 ApicReg.pszGetBaseMsrRC = "apicGetBaseMsr";
1675 ApicReg.pszSetTprRC = "apicSetTpr";
1676 ApicReg.pszGetTprRC = "apicGetTpr";
1677 ApicReg.pszWriteMsrRC = "apicWriteMsr";
1678 ApicReg.pszReadMsrRC = "apicReadMsr";
1679 ApicReg.pszBusDeliverRC = "apicBusDeliver";
1680 ApicReg.pszLocalInterruptRC = "apicLocalInterrupt";
1681 ApicReg.pszGetTimerFreqRC = "apicGetTimerFreq";
1682
1683 ApicReg.pszGetInterruptR0 = "apicGetInterrupt";
1684 ApicReg.pszSetBaseMsrR0 = "apicSetBaseMsr";
1685 ApicReg.pszGetBaseMsrR0 = "apicGetBaseMsr";
1686 ApicReg.pszSetTprR0 = "apicSetTpr";
1687 ApicReg.pszGetTprR0 = "apicGetTpr";
1688 ApicReg.pszWriteMsrR0 = "apicWriteMsr";
1689 ApicReg.pszReadMsrR0 = "apicReadMsr";
1690 ApicReg.pszBusDeliverR0 = "apicBusDeliver";
1691 ApicReg.pszLocalInterruptR0 = "apicLocalInterrupt";
1692 ApicReg.pszGetTimerFreqR0 = "apicGetTimerFreq";
1693 }
1694
1695 rc = PDMDevHlpAPICRegister(pDevIns, &ApicReg, &pApicDev->pApicHlpR3);
1696 AssertLogRelRCReturn(rc, rc);
1697 pApicDev->pCritSectR3 = pApicDev->pApicHlpR3->pfnGetR3CritSect(pDevIns);
1698
1699 /*
1700 * Initialize the APIC state.
1701 */
1702 /* First insert the MSR range of the x2APIC if enabled. */
1703 if (pApic->enmMaxMode == PDMAPICMODE_X2APIC)
1704 {
1705 rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic);
1706 AssertLogRelRCReturn(rc, rc);
1707 }
1708
1709 /* Tell CPUM about the APIC feature level so it can adjust APICBASE MSR GP mask and CPUID bits. */
1710 pApicDev->pApicHlpR3->pfnSetFeatureLevel(pDevIns, pApic->enmMaxMode);
1711
1712 /* Initialize the state. */
1713 rc = apicR3InitState(pVM);
1714 AssertRCReturn(rc, rc);
1715
1716 /*
1717 * Register the MMIO range.
1718 */
1719 PAPICCPU pApicCpu0 = VMCPU_TO_APICCPU(&pVM->aCpus[0]);
1720 RTGCPHYS GCPhysApicBase = MSR_IA32_APICBASE_GET_ADDR(pApicCpu0->uApicBaseMsr);
1721
1722 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NULL /* pvUser */,
1723 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED,
1724 apicWriteMmio, apicReadMmio, "APIC");
1725 if (RT_FAILURE(rc))
1726 return rc;
1727
1728 if (pApic->fRZEnabled)
1729 {
1730 pApicDev->pApicHlpRC = pApicDev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
1731 pApicDev->pCritSectRC = pApicDev->pApicHlpR3->pfnGetRCCritSect(pDevIns);
1732 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NIL_RTRCPTR /*pvUser*/,
1733 "apicWriteMmio", "apicReadMmio");
1734 if (RT_FAILURE(rc))
1735 return rc;
1736
1737 pApicDev->pApicHlpR0 = pApicDev->pApicHlpR3->pfnGetR0Helpers(pDevIns);
1738 pApicDev->pCritSectR0 = pApicDev->pApicHlpR3->pfnGetR0CritSect(pDevIns);
1739 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NIL_RTR0PTR /*pvUser*/,
1740 "apicWriteMmio", "apicReadMmio");
1741 if (RT_FAILURE(rc))
1742 return rc;
1743 }
1744
1745 /*
1746 * Create the APIC timers.
1747 */
1748 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1749 {
1750 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1751 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1752 RTStrPrintf(&pApicCpu->szTimerDesc[0], sizeof(pApicCpu->szTimerDesc), "APIC Timer %u", pVCpu->idCpu);
1753 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicR3TimerCallback, pVCpu, TMTIMER_FLAGS_NO_CRIT_SECT,
1754 pApicCpu->szTimerDesc, &pApicCpu->pTimerR3);
1755 if (RT_SUCCESS(rc))
1756 {
1757 pApicCpu->pTimerR0 = TMTimerR0Ptr(pApicCpu->pTimerR3);
1758 pApicCpu->pTimerRC = TMTimerRCPtr(pApicCpu->pTimerR3);
1759 }
1760 else
1761 return rc;
1762 }
1763
1764 /*
1765 * Register saved state callbacks.
1766 */
1767 rc = PDMDevHlpSSMRegister3(pDevIns, APIC_SAVED_STATE_VERSION, sizeof(*pApicDev), NULL /*pfnLiveExec*/, apicR3SaveExec,
1768 apicR3LoadExec);
1769 if (RT_FAILURE(rc))
1770 return rc;
1771
1772 /*
1773 * Register debugger info callbacks.
1774 *
1775 * We use separate callbacks rather than arguments so they can also be
1776 * dumped in an automated fashion while collecting crash diagnostics and
1777 * not just used during live debugging via the VM debugger.
1778 */
1779 rc = DBGFR3InfoRegisterInternalEx(pVM, "apic", "Dumps APIC basic information.", apicR3Info, DBGFINFO_FLAGS_ALL_EMTS);
1780 rc |= DBGFR3InfoRegisterInternalEx(pVM, "apiclvt", "Dumps APIC LVT information.", apicR3InfoLvt, DBGFINFO_FLAGS_ALL_EMTS);
1781 rc |= DBGFR3InfoRegisterInternalEx(pVM, "apictimer", "Dumps APIC timer information.", apicR3InfoTimer, DBGFINFO_FLAGS_ALL_EMTS);
1782 AssertRCReturn(rc, rc);
1783
1784#ifdef VBOX_WITH_STATISTICS
1785 /*
1786 * Statistics.
1787 */
1788#define APIC_REG_COUNTER(a_Reg, a_Desc, a_Key) \
1789 do { \
1790 rc = STAMR3RegisterF(pVM, a_Reg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, a_Desc, a_Key, idCpu); \
1791 AssertRCReturn(rc, rc); \
1792 } while(0)
1793
1794#define APIC_PROF_COUNTER(a_Reg, a_Desc, a_Key) \
1795 do { \
1796 rc = STAMR3RegisterF(pVM, a_Reg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, a_Desc, a_Key, \
1797 idCpu); \
1798 AssertRCReturn(rc, rc); \
1799 } while(0)
1800
1801 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1802 {
1803 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1804 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1805
1806 APIC_REG_COUNTER(&pApicCpu->StatMmioReadRZ, "Number of APIC MMIO reads in RZ.", "/Devices/APIC/%u/RZ/MmioRead");
1807 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteRZ, "Number of APIC MMIO writes in RZ.", "/Devices/APIC/%u/RZ/MmioWrite");
1808 APIC_REG_COUNTER(&pApicCpu->StatMsrReadRZ, "Number of APIC MSR reads in RZ.", "/Devices/APIC/%u/RZ/MsrRead");
1809 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteRZ, "Number of APIC MSR writes in RZ.", "/Devices/APIC/%u/RZ/MsrWrite");
1810
1811 APIC_REG_COUNTER(&pApicCpu->StatMmioReadR3, "Number of APIC MMIO reads in R3.", "/Devices/APIC/%u/R3/MmioReadR3");
1812 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteR3, "Number of APIC MMIO writes in R3.", "/Devices/APIC/%u/R3/MmioWriteR3");
1813 APIC_REG_COUNTER(&pApicCpu->StatMsrReadR3, "Number of APIC MSR reads in R3.", "/Devices/APIC/%u/R3/MsrReadR3");
1814 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteR3, "Number of APIC MSR writes in R3.", "/Devices/APIC/%u/R3/MsrWriteR3");
1815
1816 APIC_PROF_COUNTER(&pApicCpu->StatUpdatePendingIntrs, "Profiling of APICUpdatePendingInterrupts",
1817 "/PROF/CPU%d/APIC/UpdatePendingInterrupts");
1818 APIC_PROF_COUNTER(&pApicCpu->StatPostIntr, "Profiling of APICPostInterrupt", "/PROF/CPU%d/APIC/PostInterrupt");
1819
1820 APIC_REG_COUNTER(&pApicCpu->StatPostIntrAlreadyPending, "Number of times an interrupt is already pending.",
1821 "/Devices/APIC/%u/PostInterruptAlreadyPending");
1822 APIC_REG_COUNTER(&pApicCpu->StatTimerCallback, "Number of times the timer callback is invoked.",
1823 "/Devices/APIC/%u/TimerCallback");
1824
1825 APIC_REG_COUNTER(&pApicCpu->StatTprWrite, "Number of TPR writes.", "/Devices/APIC/%u/TprWrite");
1826 APIC_REG_COUNTER(&pApicCpu->StatTprRead, "Number of TPR reads.", "/Devices/APIC/%u/TprRead");
1827 APIC_REG_COUNTER(&pApicCpu->StatEoiWrite, "Number of EOI writes.", "/Devices/APIC/%u/EoiWrite");
1828 APIC_REG_COUNTER(&pApicCpu->StatMaskedByTpr, "Number of times TPR masks an interrupt in apicGetInterrupt.",
1829 "/Devices/APIC/%u/MaskedByTpr");
1830 APIC_REG_COUNTER(&pApicCpu->StatMaskedByPpr, "Number of times PPR masks an interrupt in apicGetInterrupt.",
1831 "/Devices/APIC/%u/MaskedByPpr");
1832 APIC_REG_COUNTER(&pApicCpu->StatTimerIcrWrite, "Number of times the timer ICR is written.",
1833 "/Devices/APIC/%u/TimerIcrWrite");
1834 APIC_REG_COUNTER(&pApicCpu->StatIcrLoWrite, "Number of times the ICR Lo (send IPI) is written.",
1835 "/Devices/APIC/%u/IcrLoWrite");
1836 }
1837# undef APIC_PROF_COUNTER
1838# undef APIC_REG_ACCESS_COUNTER
1839#endif
1840
1841 return VINF_SUCCESS;
1842}
1843
1844
1845/**
1846 * APIC device registration structure.
1847 */
1848const PDMDEVREG g_DeviceAPIC =
1849{
1850 /* u32Version */
1851 PDM_DEVREG_VERSION,
1852 /* szName */
1853 "apic",
1854 /* szRCMod */
1855 "VMMRC.rc",
1856 /* szR0Mod */
1857 "VMMR0.r0",
1858 /* pszDescription */
1859 "Advanced Programmable Interrupt Controller",
1860 /* fFlags */
1861 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36
1862 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
1863 /* fClass */
1864 PDM_DEVREG_CLASS_PIC,
1865 /* cMaxInstances */
1866 1,
1867 /* cbInstance */
1868 sizeof(APICDEV),
1869 /* pfnConstruct */
1870 apicR3Construct,
1871 /* pfnDestruct */
1872 apicR3Destruct,
1873 /* pfnRelocate */
1874 apicR3Relocate,
1875 /* pfnMemSetup */
1876 NULL,
1877 /* pfnPowerOn */
1878 NULL,
1879 /* pfnReset */
1880 apicR3Reset,
1881 /* pfnSuspend */
1882 NULL,
1883 /* pfnResume */
1884 NULL,
1885 /* pfnAttach */
1886 NULL,
1887 /* pfnDetach */
1888 NULL,
1889 /* pfnQueryInterface. */
1890 NULL,
1891 /* pfnInitComplete */
1892 apicR3InitComplete,
1893 /* pfnPowerOff */
1894 NULL,
1895 /* pfnSoftReset */
1896 NULL,
1897 /* u32VersionEnd */
1898 PDM_DEVREG_VERSION
1899};
1900
1901#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1902
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