VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/APIC.cpp@ 62338

Last change on this file since 62338 was 61848, checked in by vboxsync, 8 years ago

VMM/APIC: Use RZ {R0,RC} for the stat counters rather than separate R0, RC members with only using one of them while running the VM.
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1/* $Id: APIC.cpp 61848 2016-06-23 12:20:44Z vboxsync $ */
2/** @file
3 * APIC - Advanced Programmable Interrupt Controller.
4 */
5
6/*
7 * Copyright (C) 2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_APIC
23#include <VBox/log.h>
24#include "APICInternal.h"
25#include <VBox/vmm/cpum.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/ssm.h>
30#include <VBox/vmm/vm.h>
31
32
33#ifndef VBOX_DEVICE_STRUCT_TESTCASE
34/*********************************************************************************************************************************
35* Defined Constants And Macros *
36*********************************************************************************************************************************/
37/** The current APIC saved state version. */
38#define APIC_SAVED_STATE_VERSION 5
39/** VirtualBox 5.1 beta2 - pre fActiveLintX. */
40#define APIC_SAVED_STATE_VERSION_VBOX_51_BETA2 4
41/** The saved state version used by VirtualBox 5.0 and
42 * earlier. */
43#define APIC_SAVED_STATE_VERSION_VBOX_50 3
44/** The saved state version used by VirtualBox v3 and earlier.
45 * This does not include the config. */
46#define APIC_SAVED_STATE_VERSION_VBOX_30 2
47/** Some ancient version... */
48#define APIC_SAVED_STATE_VERSION_ANCIENT 1
49
50#ifdef VBOX_WITH_STATISTICS
51# define X2APIC_MSRRANGE(a_uFirst, a_uLast, a_szName) \
52 { (a_uFirst), (a_uLast), kCpumMsrRdFn_Ia32X2ApicN, kCpumMsrWrFn_Ia32X2ApicN, 0, 0, 0, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
53#else
54# define X2APIC_MSRRANGE(a_uFirst, a_uLast, a_szName) \
55 { (a_uFirst), (a_uLast), kCpumMsrRdFn_Ia32X2ApicN, kCpumMsrWrFn_Ia32X2ApicN, 0, 0, 0, 0, 0, a_szName }
56#endif
57
58
59/*********************************************************************************************************************************
60* Global Variables *
61*********************************************************************************************************************************/
62/**
63 * MSR range supported by the x2APIC.
64 * See Intel spec. 10.12.2 "x2APIC Register Availability".
65 */
66static CPUMMSRRANGE const g_MsrRange_x2Apic = X2APIC_MSRRANGE(MSR_IA32_X2APIC_START, MSR_IA32_X2APIC_END, "x2APIC range");
67#undef X2APIC_MSRRANGE
68
69/** Saved state field descriptors for XAPICPAGE. */
70static const SSMFIELD g_aXApicPageFields[] =
71{
72 SSMFIELD_ENTRY( XAPICPAGE, id.u8ApicId),
73 SSMFIELD_ENTRY( XAPICPAGE, version.all.u32Version),
74 SSMFIELD_ENTRY( XAPICPAGE, tpr.u8Tpr),
75 SSMFIELD_ENTRY( XAPICPAGE, apr.u8Apr),
76 SSMFIELD_ENTRY( XAPICPAGE, ppr.u8Ppr),
77 SSMFIELD_ENTRY( XAPICPAGE, ldr.all.u32Ldr),
78 SSMFIELD_ENTRY( XAPICPAGE, dfr.all.u32Dfr),
79 SSMFIELD_ENTRY( XAPICPAGE, svr.all.u32Svr),
80 SSMFIELD_ENTRY( XAPICPAGE, isr.u[0].u32Reg),
81 SSMFIELD_ENTRY( XAPICPAGE, isr.u[1].u32Reg),
82 SSMFIELD_ENTRY( XAPICPAGE, isr.u[2].u32Reg),
83 SSMFIELD_ENTRY( XAPICPAGE, isr.u[3].u32Reg),
84 SSMFIELD_ENTRY( XAPICPAGE, isr.u[4].u32Reg),
85 SSMFIELD_ENTRY( XAPICPAGE, isr.u[5].u32Reg),
86 SSMFIELD_ENTRY( XAPICPAGE, isr.u[6].u32Reg),
87 SSMFIELD_ENTRY( XAPICPAGE, isr.u[7].u32Reg),
88 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[0].u32Reg),
89 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[1].u32Reg),
90 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[2].u32Reg),
91 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[3].u32Reg),
92 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[4].u32Reg),
93 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[5].u32Reg),
94 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[6].u32Reg),
95 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[7].u32Reg),
96 SSMFIELD_ENTRY( XAPICPAGE, irr.u[0].u32Reg),
97 SSMFIELD_ENTRY( XAPICPAGE, irr.u[1].u32Reg),
98 SSMFIELD_ENTRY( XAPICPAGE, irr.u[2].u32Reg),
99 SSMFIELD_ENTRY( XAPICPAGE, irr.u[3].u32Reg),
100 SSMFIELD_ENTRY( XAPICPAGE, irr.u[4].u32Reg),
101 SSMFIELD_ENTRY( XAPICPAGE, irr.u[5].u32Reg),
102 SSMFIELD_ENTRY( XAPICPAGE, irr.u[6].u32Reg),
103 SSMFIELD_ENTRY( XAPICPAGE, irr.u[7].u32Reg),
104 SSMFIELD_ENTRY( XAPICPAGE, esr.all.u32Errors),
105 SSMFIELD_ENTRY( XAPICPAGE, icr_lo.all.u32IcrLo),
106 SSMFIELD_ENTRY( XAPICPAGE, icr_hi.all.u32IcrHi),
107 SSMFIELD_ENTRY( XAPICPAGE, lvt_timer.all.u32LvtTimer),
108 SSMFIELD_ENTRY( XAPICPAGE, lvt_thermal.all.u32LvtThermal),
109 SSMFIELD_ENTRY( XAPICPAGE, lvt_perf.all.u32LvtPerf),
110 SSMFIELD_ENTRY( XAPICPAGE, lvt_lint0.all.u32LvtLint0),
111 SSMFIELD_ENTRY( XAPICPAGE, lvt_lint1.all.u32LvtLint1),
112 SSMFIELD_ENTRY( XAPICPAGE, lvt_error.all.u32LvtError),
113 SSMFIELD_ENTRY( XAPICPAGE, timer_icr.u32InitialCount),
114 SSMFIELD_ENTRY( XAPICPAGE, timer_ccr.u32CurrentCount),
115 SSMFIELD_ENTRY( XAPICPAGE, timer_dcr.all.u32DivideValue),
116 SSMFIELD_ENTRY_TERM()
117};
118
119/** Saved state field descriptors for X2APICPAGE. */
120static const SSMFIELD g_aX2ApicPageFields[] =
121{
122 SSMFIELD_ENTRY(X2APICPAGE, id.u32ApicId),
123 SSMFIELD_ENTRY(X2APICPAGE, version.all.u32Version),
124 SSMFIELD_ENTRY(X2APICPAGE, tpr.u8Tpr),
125 SSMFIELD_ENTRY(X2APICPAGE, ppr.u8Ppr),
126 SSMFIELD_ENTRY(X2APICPAGE, ldr.u32LogicalApicId),
127 SSMFIELD_ENTRY(X2APICPAGE, svr.all.u32Svr),
128 SSMFIELD_ENTRY(X2APICPAGE, isr.u[0].u32Reg),
129 SSMFIELD_ENTRY(X2APICPAGE, isr.u[1].u32Reg),
130 SSMFIELD_ENTRY(X2APICPAGE, isr.u[2].u32Reg),
131 SSMFIELD_ENTRY(X2APICPAGE, isr.u[3].u32Reg),
132 SSMFIELD_ENTRY(X2APICPAGE, isr.u[4].u32Reg),
133 SSMFIELD_ENTRY(X2APICPAGE, isr.u[5].u32Reg),
134 SSMFIELD_ENTRY(X2APICPAGE, isr.u[6].u32Reg),
135 SSMFIELD_ENTRY(X2APICPAGE, isr.u[7].u32Reg),
136 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[0].u32Reg),
137 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[1].u32Reg),
138 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[2].u32Reg),
139 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[3].u32Reg),
140 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[4].u32Reg),
141 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[5].u32Reg),
142 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[6].u32Reg),
143 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[7].u32Reg),
144 SSMFIELD_ENTRY(X2APICPAGE, irr.u[0].u32Reg),
145 SSMFIELD_ENTRY(X2APICPAGE, irr.u[1].u32Reg),
146 SSMFIELD_ENTRY(X2APICPAGE, irr.u[2].u32Reg),
147 SSMFIELD_ENTRY(X2APICPAGE, irr.u[3].u32Reg),
148 SSMFIELD_ENTRY(X2APICPAGE, irr.u[4].u32Reg),
149 SSMFIELD_ENTRY(X2APICPAGE, irr.u[5].u32Reg),
150 SSMFIELD_ENTRY(X2APICPAGE, irr.u[6].u32Reg),
151 SSMFIELD_ENTRY(X2APICPAGE, irr.u[7].u32Reg),
152 SSMFIELD_ENTRY(X2APICPAGE, esr.all.u32Errors),
153 SSMFIELD_ENTRY(X2APICPAGE, icr_lo.all.u32IcrLo),
154 SSMFIELD_ENTRY(X2APICPAGE, icr_hi.u32IcrHi),
155 SSMFIELD_ENTRY(X2APICPAGE, lvt_timer.all.u32LvtTimer),
156 SSMFIELD_ENTRY(X2APICPAGE, lvt_thermal.all.u32LvtThermal),
157 SSMFIELD_ENTRY(X2APICPAGE, lvt_perf.all.u32LvtPerf),
158 SSMFIELD_ENTRY(X2APICPAGE, lvt_lint0.all.u32LvtLint0),
159 SSMFIELD_ENTRY(X2APICPAGE, lvt_lint1.all.u32LvtLint1),
160 SSMFIELD_ENTRY(X2APICPAGE, lvt_error.all.u32LvtError),
161 SSMFIELD_ENTRY(X2APICPAGE, timer_icr.u32InitialCount),
162 SSMFIELD_ENTRY(X2APICPAGE, timer_ccr.u32CurrentCount),
163 SSMFIELD_ENTRY(X2APICPAGE, timer_dcr.all.u32DivideValue),
164 SSMFIELD_ENTRY_TERM()
165};
166
167
168/**
169 * Initializes per-VCPU APIC to the state following an INIT reset
170 * ("Wait-for-SIPI" state).
171 *
172 * @param pVCpu The cross context virtual CPU structure.
173 */
174static void apicR3InitIpi(PVMCPU pVCpu)
175{
176 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
177 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
178
179 /*
180 * See Intel spec. 10.4.7.3 "Local APIC State After an INIT Reset (Wait-for-SIPI State)"
181 * and AMD spec 16.3.2 "APIC Registers".
182 *
183 * The reason we don't simply zero out the entire APIC page and only set the non-zero members
184 * is because there are some registers that are not touched by the INIT IPI (e.g. version)
185 * operation and this function is only a subset of the reset operation.
186 */
187 RT_ZERO(pXApicPage->irr);
188 RT_ZERO(pXApicPage->irr);
189 RT_ZERO(pXApicPage->isr);
190 RT_ZERO(pXApicPage->tmr);
191 RT_ZERO(pXApicPage->icr_hi);
192 RT_ZERO(pXApicPage->icr_lo);
193 RT_ZERO(pXApicPage->ldr);
194 RT_ZERO(pXApicPage->tpr);
195 RT_ZERO(pXApicPage->ppr);
196 RT_ZERO(pXApicPage->timer_icr);
197 RT_ZERO(pXApicPage->timer_ccr);
198 RT_ZERO(pXApicPage->timer_dcr);
199
200 pXApicPage->dfr.u.u4Model = XAPICDESTFORMAT_FLAT;
201 pXApicPage->dfr.u.u28ReservedMb1 = UINT32_C(0xfffffff);
202
203 /** @todo CMCI. */
204
205 RT_ZERO(pXApicPage->lvt_timer);
206 pXApicPage->lvt_timer.u.u1Mask = 1;
207
208#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
209 RT_ZERO(pXApicPage->lvt_thermal);
210 pXApicPage->lvt_thermal.u.u1Mask = 1;
211#endif
212
213 RT_ZERO(pXApicPage->lvt_perf);
214 pXApicPage->lvt_perf.u.u1Mask = 1;
215
216 RT_ZERO(pXApicPage->lvt_lint0);
217 pXApicPage->lvt_lint0.u.u1Mask = 1;
218
219 RT_ZERO(pXApicPage->lvt_lint1);
220 pXApicPage->lvt_lint1.u.u1Mask = 1;
221
222 RT_ZERO(pXApicPage->lvt_error);
223 pXApicPage->lvt_error.u.u1Mask = 1;
224
225 RT_ZERO(pXApicPage->svr);
226 pXApicPage->svr.u.u8SpuriousVector = 0xff;
227
228 /* The self-IPI register is reset to 0. See Intel spec. 10.12.5.1 "x2APIC States" */
229 PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
230 RT_ZERO(pX2ApicPage->self_ipi);
231
232 /* Clear the pending-interrupt bitmaps. */
233 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
234 RT_BZERO(&pApicCpu->ApicPibLevel, sizeof(APICPIB));
235 RT_BZERO(pApicCpu->pvApicPibR3, sizeof(APICPIB));
236
237 /* Clear the interrupt line states for LINT0 and LINT1 pins. */
238 pApicCpu->fActiveLint0 = false;
239 pApicCpu->fActiveLint1 = false;
240}
241
242
243/**
244 * Resets the APIC base MSR.
245 *
246 * @param pVCpu The cross context virtual CPU structure.
247 */
248static void apicR3ResetBaseMsr(PVMCPU pVCpu)
249{
250 /*
251 * Initialize the APIC base MSR. The APIC enable-bit is set upon power-up or reset[1].
252 *
253 * A Reset (in xAPIC and x2APIC mode) brings up the local APIC in xAPIC mode.
254 * An INIT IPI does -not- cause a transition between xAPIC and x2APIC mode[2].
255 *
256 * [1] See AMD spec. 14.1.3 "Processor Initialization State"
257 * [2] See Intel spec. 10.12.5.1 "x2APIC States".
258 */
259 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
260
261 /* Construct. */
262 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
263 PAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
264 uint64_t uApicBaseMsr = MSR_IA32_APICBASE_ADDR;
265 if (pVCpu->idCpu == 0)
266 uApicBaseMsr |= MSR_IA32_APICBASE_BSP;
267
268 /* If the VM was configured with no APIC, don't enable xAPIC mode, obviously. */
269 if (pApic->enmMaxMode != PDMAPICMODE_NONE)
270 {
271 uApicBaseMsr |= MSR_IA32_APICBASE_EN;
272
273 /*
274 * While coming out of a reset the APIC is enabled and in xAPIC mode. If software had previously
275 * disabled the APIC (which results in the CPUID bit being cleared as well) we re-enable it here.
276 * See Intel spec. 10.12.5.1 "x2APIC States".
277 */
278 if (CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, true /*fVisible*/) == false)
279 LogRel(("APIC%u: Resetting mode to xAPIC\n", pVCpu->idCpu));
280 }
281
282 /* Commit. */
283 ASMAtomicWriteU64(&pApicCpu->uApicBaseMsr, uApicBaseMsr);
284}
285
286
287/**
288 * Initializes per-VCPU APIC to the state following a power-up or hardware
289 * reset.
290 *
291 * @param pVCpu The cross context virtual CPU structure.
292 * @param fResetApicBaseMsr Whether to reset the APIC base MSR.
293 */
294VMMR3_INT_DECL(void) apicR3ResetCpu(PVMCPU pVCpu, bool fResetApicBaseMsr)
295{
296 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
297
298 LogFlow(("APIC%u: apicR3ResetCpu: fResetApicBaseMsr=%RTbool\n", pVCpu->idCpu, fResetApicBaseMsr));
299
300#ifdef VBOX_STRICT
301 /* Verify that the initial APIC ID reported via CPUID matches our VMCPU ID assumption. */
302 uint32_t uEax, uEbx, uEcx, uEdx;
303 uEax = uEbx = uEcx = uEdx = UINT32_MAX;
304 CPUMGetGuestCpuId(pVCpu, 1, 0, &uEax, &uEbx, &uEcx, &uEdx);
305 Assert(((uEbx >> 24) & 0xff) == pVCpu->idCpu);
306#endif
307
308 /*
309 * The state following a power-up or reset is a superset of the INIT state.
310 * See Intel spec. 10.4.7.3 "Local APIC State After an INIT Reset ('Wait-for-SIPI' State)"
311 */
312 apicR3InitIpi(pVCpu);
313
314 /*
315 * The APIC version register is read-only, so just initialize it here.
316 * It is not clear from the specs, where exactly it is initialized.
317 * The version determines the number of LVT entries and size of the APIC ID (8 bits for P4).
318 */
319 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
320#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
321 pXApicPage->version.u.u8MaxLvtEntry = XAPIC_MAX_LVT_ENTRIES_P4 - 1;
322 pXApicPage->version.u.u8Version = XAPIC_HARDWARE_VERSION_P4;
323 AssertCompile(sizeof(pXApicPage->id.u8ApicId) >= XAPIC_APIC_ID_BIT_COUNT_P4 / 8);
324#else
325# error "Implement Pentium and P6 family APIC architectures"
326#endif
327
328 /** @todo It isn't clear in the spec. where exactly the default base address
329 * is (re)initialized, atm we do it here in Reset. */
330 if (fResetApicBaseMsr)
331 apicR3ResetBaseMsr(pVCpu);
332
333 /*
334 * Initialize the APIC ID register to xAPIC format.
335 */
336 ASMMemZero32(&pXApicPage->id, sizeof(pXApicPage->id));
337 pXApicPage->id.u8ApicId = pVCpu->idCpu;
338}
339
340
341/**
342 * Receives an INIT IPI.
343 *
344 * @param pVCpu The cross context virtual CPU structure.
345 */
346VMMR3_INT_DECL(void) APICR3InitIpi(PVMCPU pVCpu)
347{
348 VMCPU_ASSERT_EMT(pVCpu);
349 LogFlow(("APIC%u: APICR3InitIpi\n", pVCpu->idCpu));
350 apicR3InitIpi(pVCpu);
351}
352
353
354/**
355 * Helper for dumping an APIC 256-bit sparse register.
356 *
357 * @param pApicReg The APIC 256-bit spare register.
358 * @param pHlp The debug output helper.
359 */
360static void apicR3DbgInfo256BitReg(volatile const XAPIC256BITREG *pApicReg, PCDBGFINFOHLP pHlp)
361{
362 ssize_t const cFragments = RT_ELEMENTS(pApicReg->u);
363 unsigned const cBitsPerFragment = sizeof(pApicReg->u[0].u32Reg) * 8;
364 XAPIC256BITREG ApicReg;
365 RT_ZERO(ApicReg);
366
367 pHlp->pfnPrintf(pHlp, " ");
368 for (ssize_t i = cFragments - 1; i >= 0; i--)
369 {
370 uint32_t const uFragment = pApicReg->u[i].u32Reg;
371 ApicReg.u[i].u32Reg = uFragment;
372 pHlp->pfnPrintf(pHlp, "%08x", uFragment);
373 }
374 pHlp->pfnPrintf(pHlp, "\n");
375
376 uint32_t cPending = 0;
377 pHlp->pfnPrintf(pHlp, " Pending:");
378 for (ssize_t i = cFragments - 1; i >= 0; i--)
379 {
380 uint32_t uFragment = ApicReg.u[i].u32Reg;
381 if (uFragment)
382 {
383 do
384 {
385 unsigned idxSetBit = ASMBitLastSetU32(uFragment);
386 --idxSetBit;
387 ASMBitClear(&uFragment, idxSetBit);
388
389 idxSetBit += (i * cBitsPerFragment);
390 pHlp->pfnPrintf(pHlp, " %#02x", idxSetBit);
391 ++cPending;
392 } while (uFragment);
393 }
394 }
395 if (!cPending)
396 pHlp->pfnPrintf(pHlp, " None");
397 pHlp->pfnPrintf(pHlp, "\n");
398}
399
400
401/**
402 * Helper for dumping an APIC pending-interrupt bitmap.
403 *
404 * @param pApicPib The pending-interrupt bitmap.
405 * @param pHlp The debug output helper.
406 */
407static void apicR3DbgInfoPib(PCAPICPIB pApicPib, PCDBGFINFOHLP pHlp)
408{
409 /* Copy the pending-interrupt bitmap as an APIC 256-bit sparse register. */
410 XAPIC256BITREG ApicReg;
411 RT_ZERO(ApicReg);
412 ssize_t const cFragmentsDst = RT_ELEMENTS(ApicReg.u);
413 ssize_t const cFragmentsSrc = RT_ELEMENTS(pApicPib->aVectorBitmap);
414 AssertCompile(RT_ELEMENTS(ApicReg.u) == 2 * RT_ELEMENTS(pApicPib->aVectorBitmap));
415 for (ssize_t idxPib = cFragmentsSrc - 1, idxReg = cFragmentsDst - 1; idxPib >= 0; idxPib--, idxReg -= 2)
416 {
417 uint64_t const uFragment = pApicPib->aVectorBitmap[idxPib];
418 uint32_t const uFragmentLo = RT_LO_U32(uFragment);
419 uint32_t const uFragmentHi = RT_HI_U32(uFragment);
420 ApicReg.u[idxReg].u32Reg = uFragmentHi;
421 ApicReg.u[idxReg - 1].u32Reg = uFragmentLo;
422 }
423
424 /* Dump it. */
425 apicR3DbgInfo256BitReg(&ApicReg, pHlp);
426}
427
428
429/**
430 * Dumps basic APIC state.
431 *
432 * @param pVM The cross context VM structure.
433 * @param pHlp The info helpers.
434 * @param pszArgs Arguments, ignored.
435 */
436static DECLCALLBACK(void) apicR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
437{
438 NOREF(pszArgs);
439 PVMCPU pVCpu = VMMGetCpu(pVM);
440 if (!pVCpu)
441 pVCpu = &pVM->aCpus[0];
442
443 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
444 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
445 PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
446
447 uint64_t const uBaseMsr = pApicCpu->uApicBaseMsr;
448 APICMODE const enmMode = apicGetMode(uBaseMsr);
449 bool const fX2ApicMode = XAPIC_IN_X2APIC_MODE(pVCpu);
450
451 pHlp->pfnPrintf(pHlp, "APIC%u:\n", pVCpu->idCpu);
452 pHlp->pfnPrintf(pHlp, " APIC Base MSR = %#RX64 (Addr=%#RX64)\n", uBaseMsr,
453 MSR_IA32_APICBASE_GET_ADDR(uBaseMsr));
454 pHlp->pfnPrintf(pHlp, " Mode = %u (%s)\n", enmMode, apicGetModeName(enmMode));
455 if (fX2ApicMode)
456 {
457 pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pX2ApicPage->id.u32ApicId,
458 pX2ApicPage->id.u32ApicId);
459 }
460 else
461 pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pXApicPage->id.u8ApicId, pXApicPage->id.u8ApicId);
462 pHlp->pfnPrintf(pHlp, " Version = %#x\n", pXApicPage->version.all.u32Version);
463 pHlp->pfnPrintf(pHlp, " APIC Version = %#x\n", pXApicPage->version.u.u8Version);
464 pHlp->pfnPrintf(pHlp, " Max LVT entry index (0..N) = %u\n", pXApicPage->version.u.u8MaxLvtEntry);
465 pHlp->pfnPrintf(pHlp, " EOI Broadcast supression = %RTbool\n", pXApicPage->version.u.fEoiBroadcastSupression);
466 if (!fX2ApicMode)
467 pHlp->pfnPrintf(pHlp, " APR = %u (%#x)\n", pXApicPage->apr.u8Apr, pXApicPage->apr.u8Apr);
468 pHlp->pfnPrintf(pHlp, " TPR = %u (%#x)\n", pXApicPage->tpr.u8Tpr, pXApicPage->tpr.u8Tpr);
469 pHlp->pfnPrintf(pHlp, " Task-priority class = %#x\n", XAPIC_TPR_GET_TP(pXApicPage->tpr.u8Tpr) >> 4);
470 pHlp->pfnPrintf(pHlp, " Task-priority subclass = %#x\n", XAPIC_TPR_GET_TP_SUBCLASS(pXApicPage->tpr.u8Tpr));
471 pHlp->pfnPrintf(pHlp, " PPR = %u (%#x)\n", pXApicPage->ppr.u8Ppr, pXApicPage->ppr.u8Ppr);
472 pHlp->pfnPrintf(pHlp, " Processor-priority class = %#x\n", XAPIC_PPR_GET_PP(pXApicPage->ppr.u8Ppr) >> 4);
473 pHlp->pfnPrintf(pHlp, " Processor-priority subclass = %#x\n", XAPIC_PPR_GET_PP_SUBCLASS(pXApicPage->ppr.u8Ppr));
474 if (!fX2ApicMode)
475 pHlp->pfnPrintf(pHlp, " RRD = %u (%#x)\n", pXApicPage->rrd.u32Rrd, pXApicPage->rrd.u32Rrd);
476 pHlp->pfnPrintf(pHlp, " LDR = %#x\n", pXApicPage->ldr.all.u32Ldr);
477 pHlp->pfnPrintf(pHlp, " Logical APIC ID = %#x\n", fX2ApicMode ? pX2ApicPage->ldr.u32LogicalApicId
478 : pXApicPage->ldr.u.u8LogicalApicId);
479 if (!fX2ApicMode)
480 {
481 pHlp->pfnPrintf(pHlp, " DFR = %#x\n", pXApicPage->dfr.all.u32Dfr);
482 pHlp->pfnPrintf(pHlp, " Model = %#x (%s)\n", pXApicPage->dfr.u.u4Model,
483 apicGetDestFormatName((XAPICDESTFORMAT)pXApicPage->dfr.u.u4Model));
484 }
485 pHlp->pfnPrintf(pHlp, " SVR = %#x\n", pXApicPage->svr.all.u32Svr);
486 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->svr.u.u8SpuriousVector,
487 pXApicPage->svr.u.u8SpuriousVector);
488 pHlp->pfnPrintf(pHlp, " Software Enabled = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fApicSoftwareEnable));
489 pHlp->pfnPrintf(pHlp, " Supress EOI broadcast = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fSupressEoiBroadcast));
490 pHlp->pfnPrintf(pHlp, " ISR\n");
491 apicR3DbgInfo256BitReg(&pXApicPage->isr, pHlp);
492 pHlp->pfnPrintf(pHlp, " TMR\n");
493 apicR3DbgInfo256BitReg(&pXApicPage->tmr, pHlp);
494 pHlp->pfnPrintf(pHlp, " IRR\n");
495 apicR3DbgInfo256BitReg(&pXApicPage->irr, pHlp);
496 pHlp->pfnPrintf(pHlp, " PIB\n");
497 apicR3DbgInfoPib((PCAPICPIB)pApicCpu->pvApicPibR3, pHlp);
498 pHlp->pfnPrintf(pHlp, " Level PIB\n");
499 apicR3DbgInfoPib(&pApicCpu->ApicPibLevel, pHlp);
500 pHlp->pfnPrintf(pHlp, " ESR Internal = %#x\n", pApicCpu->uEsrInternal);
501 pHlp->pfnPrintf(pHlp, " ESR = %#x\n", pXApicPage->esr.all.u32Errors);
502 pHlp->pfnPrintf(pHlp, " Redirectable IPI = %RTbool\n", pXApicPage->esr.u.fRedirectableIpi);
503 pHlp->pfnPrintf(pHlp, " Send Illegal Vector = %RTbool\n", pXApicPage->esr.u.fSendIllegalVector);
504 pHlp->pfnPrintf(pHlp, " Recv Illegal Vector = %RTbool\n", pXApicPage->esr.u.fRcvdIllegalVector);
505 pHlp->pfnPrintf(pHlp, " Illegal Register Address = %RTbool\n", pXApicPage->esr.u.fIllegalRegAddr);
506 pHlp->pfnPrintf(pHlp, " ICR Low = %#x\n", pXApicPage->icr_lo.all.u32IcrLo);
507 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->icr_lo.u.u8Vector,
508 pXApicPage->icr_lo.u.u8Vector);
509 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u3DeliveryMode,
510 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->icr_lo.u.u3DeliveryMode));
511 pHlp->pfnPrintf(pHlp, " Destination Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u1DestMode,
512 apicGetDestModeName((XAPICDESTMODE)pXApicPage->icr_lo.u.u1DestMode));
513 if (!fX2ApicMode)
514 pHlp->pfnPrintf(pHlp, " Delivery Status = %u\n", pXApicPage->icr_lo.u.u1DeliveryStatus);
515 pHlp->pfnPrintf(pHlp, " Level = %u\n", pXApicPage->icr_lo.u.u1Level);
516 pHlp->pfnPrintf(pHlp, " Trigger Mode = %u (%s)\n", pXApicPage->icr_lo.u.u1TriggerMode,
517 apicGetTriggerModeName((XAPICTRIGGERMODE)pXApicPage->icr_lo.u.u1TriggerMode));
518 pHlp->pfnPrintf(pHlp, " Destination shorthand = %#x (%s)\n", pXApicPage->icr_lo.u.u2DestShorthand,
519 apicGetDestShorthandName((XAPICDESTSHORTHAND)pXApicPage->icr_lo.u.u2DestShorthand));
520 pHlp->pfnPrintf(pHlp, " ICR High = %#x\n", pXApicPage->icr_hi.all.u32IcrHi);
521 pHlp->pfnPrintf(pHlp, " Destination field/mask = %#x\n", fX2ApicMode ? pX2ApicPage->icr_hi.u32IcrHi
522 : pXApicPage->icr_hi.u.u8Dest);
523}
524
525
526/**
527 * Helper for dumping the LVT timer.
528 *
529 * @param pVCpu The cross context virtual CPU structure.
530 * @param pHlp The debug output helper.
531 */
532static void apicR3InfoLvtTimer(PVMCPU pVCpu, PCDBGFINFOHLP pHlp)
533{
534 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
535 uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
536 pHlp->pfnPrintf(pHlp, "LVT Timer = %#RX32\n", uLvtTimer);
537 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_timer.u.u8Vector, pXApicPage->lvt_timer.u.u8Vector);
538 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_timer.u.u1DeliveryStatus);
539 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtTimer));
540 pHlp->pfnPrintf(pHlp, " Timer Mode = %#x (%s)\n", pXApicPage->lvt_timer.u.u2TimerMode,
541 apicGetTimerModeName((XAPICTIMERMODE)pXApicPage->lvt_timer.u.u2TimerMode));
542}
543
544
545/**
546 * Dumps APIC Local Vector Table (LVT) information.
547 *
548 * @param pVM The cross context VM structure.
549 * @param pHlp The info helpers.
550 * @param pszArgs Arguments, ignored.
551 */
552static DECLCALLBACK(void) apicR3InfoLvt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
553{
554 NOREF(pszArgs);
555 PVMCPU pVCpu = VMMGetCpu(pVM);
556 if (!pVCpu)
557 pVCpu = &pVM->aCpus[0];
558
559 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
560
561 /*
562 * Delivery modes available in the LVT entries. They're different (more reserved stuff) from the
563 * ICR delivery modes and hence we don't use apicGetDeliveryMode but mostly because we want small,
564 * fixed-length strings to fit our formatting needs here.
565 */
566 static const char * const s_apszLvtDeliveryModes[] =
567 {
568 "Fixed ",
569 "Rsvd ",
570 "SMI ",
571 "Rsvd ",
572 "NMI ",
573 "INIT ",
574 "Rsvd ",
575 "ExtINT"
576 };
577 /* Delivery Status. */
578 static const char * const s_apszLvtDeliveryStatus[] =
579 {
580 "Idle",
581 "Pend"
582 };
583 const char *pszNotApplicable = "";
584
585 pHlp->pfnPrintf(pHlp, "VCPU[%u] APIC Local Vector Table (LVT):\n", pVCpu->idCpu);
586 pHlp->pfnPrintf(pHlp, "lvt timermode mask trigger rirr polarity dlvr_st dlvr_mode vector\n");
587 /* Timer. */
588 {
589 /* Timer modes. */
590 static const char * const s_apszLvtTimerModes[] =
591 {
592 "One-shot ",
593 "Periodic ",
594 "TSC-dline"
595 };
596 const uint32_t uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
597 const XAPICTIMERMODE enmTimerMode = XAPIC_LVT_GET_TIMER_MODE(uLvtTimer);
598 const char *pszTimerMode = s_apszLvtTimerModes[enmTimerMode];
599 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtTimer);
600 const uint8_t uDeliveryStatus = uLvtTimer & XAPIC_LVT_DELIVERY_STATUS;
601 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
602 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
603
604 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
605 "Timer",
606 pszTimerMode,
607 uMask,
608 pszNotApplicable, /* TriggerMode */
609 pszNotApplicable, /* Remote IRR */
610 pszNotApplicable, /* Polarity */
611 pszDeliveryStatus,
612 pszNotApplicable, /* Delivery Mode */
613 uVector,
614 uVector);
615 }
616
617#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
618 /* Thermal sensor. */
619 {
620 uint32_t const uLvtThermal = pXApicPage->lvt_thermal.all.u32LvtThermal;
621 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtThermal);
622 const uint8_t uDeliveryStatus = uLvtThermal & XAPIC_LVT_DELIVERY_STATUS;
623 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
624 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtThermal);
625 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
626 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtThermal);
627
628 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
629 "Thermal",
630 pszNotApplicable, /* Timer mode */
631 uMask,
632 pszNotApplicable, /* TriggerMode */
633 pszNotApplicable, /* Remote IRR */
634 pszNotApplicable, /* Polarity */
635 pszDeliveryStatus,
636 pszDeliveryMode,
637 uVector,
638 uVector);
639 }
640#endif
641
642 /* Performance Monitor Counters. */
643 {
644 uint32_t const uLvtPerf = pXApicPage->lvt_thermal.all.u32LvtThermal;
645 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtPerf);
646 const uint8_t uDeliveryStatus = uLvtPerf & XAPIC_LVT_DELIVERY_STATUS;
647 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
648 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtPerf);
649 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
650 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtPerf);
651
652 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
653 "Perf",
654 pszNotApplicable, /* Timer mode */
655 uMask,
656 pszNotApplicable, /* TriggerMode */
657 pszNotApplicable, /* Remote IRR */
658 pszNotApplicable, /* Polarity */
659 pszDeliveryStatus,
660 pszDeliveryMode,
661 uVector,
662 uVector);
663 }
664
665 /* LINT0, LINT1. */
666 {
667 /* LINTx name. */
668 static const char * const s_apszLvtLint[] =
669 {
670 "LINT0",
671 "LINT1"
672 };
673 /* Trigger mode. */
674 static const char * const s_apszLvtTriggerModes[] =
675 {
676 "Edge ",
677 "Level"
678 };
679 /* Polarity. */
680 static const char * const s_apszLvtPolarity[] =
681 {
682 "ActiveHi",
683 "ActiveLo"
684 };
685
686 uint32_t aLvtLint[2];
687 aLvtLint[0] = pXApicPage->lvt_lint0.all.u32LvtLint0;
688 aLvtLint[1] = pXApicPage->lvt_lint1.all.u32LvtLint1;
689 for (size_t i = 0; i < RT_ELEMENTS(aLvtLint); i++)
690 {
691 uint32_t const uLvtLint = aLvtLint[i];
692 const char *pszLint = s_apszLvtLint[i];
693 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtLint);
694 const XAPICTRIGGERMODE enmTriggerMode = XAPIC_LVT_GET_TRIGGER_MODE(uLvtLint);
695 const char *pszTriggerMode = s_apszLvtTriggerModes[enmTriggerMode];
696 const uint8_t uRemoteIrr = XAPIC_LVT_GET_REMOTE_IRR(uLvtLint);
697 const uint8_t uPolarity = XAPIC_LVT_GET_POLARITY(uLvtLint);
698 const char *pszPolarity = s_apszLvtPolarity[uPolarity];
699 const uint8_t uDeliveryStatus = uLvtLint & XAPIC_LVT_DELIVERY_STATUS;
700 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
701 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtLint);
702 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
703 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtLint);
704
705 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %u %8s %4s %6s %3u (%#x)\n",
706 pszLint,
707 pszNotApplicable, /* Timer mode */
708 uMask,
709 pszTriggerMode,
710 uRemoteIrr,
711 pszPolarity,
712 pszDeliveryStatus,
713 pszDeliveryMode,
714 uVector,
715 uVector);
716 }
717 }
718
719 /* Error. */
720 {
721 uint32_t const uLvtError = pXApicPage->lvt_thermal.all.u32LvtThermal;
722 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtError);
723 const uint8_t uDeliveryStatus = uLvtError & XAPIC_LVT_DELIVERY_STATUS;
724 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
725 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtError);
726 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
727 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtError);
728
729 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
730 "Error",
731 pszNotApplicable, /* Timer mode */
732 uMask,
733 pszNotApplicable, /* TriggerMode */
734 pszNotApplicable, /* Remote IRR */
735 pszNotApplicable, /* Polarity */
736 pszDeliveryStatus,
737 pszDeliveryMode,
738 uVector,
739 uVector);
740 }
741}
742
743
744/**
745 * Dumps the APIC timer information.
746 *
747 * @param pVM The cross context VM structure.
748 * @param pHlp The info helpers.
749 * @param pszArgs Arguments, ignored.
750 */
751static DECLCALLBACK(void) apicR3InfoTimer(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
752{
753 NOREF(pszArgs);
754 PVMCPU pVCpu = VMMGetCpu(pVM);
755 if (!pVCpu)
756 pVCpu = &pVM->aCpus[0];
757
758 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
759 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
760
761 pHlp->pfnPrintf(pHlp, "VCPU[%u] Local APIC timer:\n", pVCpu->idCpu);
762 pHlp->pfnPrintf(pHlp, " ICR = %#RX32\n", pXApicPage->timer_icr.u32InitialCount);
763 pHlp->pfnPrintf(pHlp, " CCR = %#RX32\n", pXApicPage->timer_ccr.u32CurrentCount);
764 pHlp->pfnPrintf(pHlp, " DCR = %#RX32\n", pXApicPage->timer_dcr.all.u32DivideValue);
765 pHlp->pfnPrintf(pHlp, " Timer shift = %#x\n", apicGetTimerShift(pXApicPage));
766 pHlp->pfnPrintf(pHlp, " Timer initial TS = %#RU64\n", pApicCpu->u64TimerInitial);
767 apicR3InfoLvtTimer(pVCpu, pHlp);
768}
769
770
771#ifdef APIC_FUZZY_SSM_COMPAT_TEST
772
773/**
774 * Reads a 32-bit register at a specified offset.
775 *
776 * @returns The value at the specified offset.
777 * @param pXApicPage The xAPIC page.
778 * @param offReg The offset of the register being read.
779 *
780 * @remarks Duplicate of apicReadRaw32()!
781 */
782static uint32_t apicR3ReadRawR32(PCXAPICPAGE pXApicPage, uint16_t offReg)
783{
784 Assert(offReg < sizeof(*pXApicPage) - sizeof(uint32_t));
785 uint8_t const *pbXApic = (const uint8_t *)pXApicPage;
786 uint32_t const uValue = *(const uint32_t *)(pbXApic + offReg);
787 return uValue;
788}
789
790
791/**
792 * Helper for dumping per-VCPU APIC state to the release logger.
793 *
794 * This is primarily concerned about the APIC state relevant for saved-states.
795 *
796 * @param pVCpu The cross context virtual CPU structure.
797 * @param pszPrefix A caller supplied prefix before dumping the state.
798 * @param uVersion Data layout version.
799 */
800static void apicR3DumpState(PVMCPU pVCpu, const char *pszPrefix, uint32_t uVersion)
801{
802 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
803
804 LogRel(("APIC%u: %s (version %u):\n", pVCpu->idCpu, pszPrefix, uVersion));
805
806 switch (uVersion)
807 {
808 case APIC_SAVED_STATE_VERSION:
809 case APIC_SAVED_STATE_VERSION_VBOX_51_BETA2:
810 {
811 /* The auxiliary state. */
812 LogRel(("APIC%u: uApicBaseMsr = %#RX64\n", pVCpu->idCpu, pApicCpu->uApicBaseMsr));
813 LogRel(("APIC%u: uEsrInternal = %#RX64\n", pVCpu->idCpu, pApicCpu->uEsrInternal));
814
815 /* The timer. */
816 LogRel(("APIC%u: u64TimerInitial = %#RU64\n", pVCpu->idCpu, pApicCpu->u64TimerInitial));
817 LogRel(("APIC%u: uHintedTimerInitialCount = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerInitialCount));
818 LogRel(("APIC%u: uHintedTimerShift = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerShift));
819
820 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
821 LogRel(("APIC%u: uTimerICR = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_icr.u32InitialCount));
822 LogRel(("APIC%u: uTimerCCR = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_ccr.u32CurrentCount));
823
824 /* The PIBs. */
825 LogRel(("APIC%u: Edge PIB : %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), pApicCpu->pvApicPibR3));
826 LogRel(("APIC%u: Level PIB: %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), &pApicCpu->ApicPibLevel));
827
828 /* The LINT0, LINT1 interrupt line active states. */
829 LogRel(("APIC%u: fActiveLint0 = %RTbool\n", pVCpu->idCpu, pApicCpu->fActiveLint0));
830 LogRel(("APIC%u: fActiveLint1 = %RTbool\n", pVCpu->idCpu, pApicCpu->fActiveLint1));
831
832 /* The APIC page. */
833 LogRel(("APIC%u: APIC page: %.*Rhxs\n", pVCpu->idCpu, sizeof(XAPICPAGE), pApicCpu->pvApicPageR3));
834 break;
835 }
836
837 case APIC_SAVED_STATE_VERSION_VBOX_50:
838 case APIC_SAVED_STATE_VERSION_VBOX_30:
839 case APIC_SAVED_STATE_VERSION_ANCIENT:
840 {
841 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
842 LogRel(("APIC%u: uApicBaseMsr = %#RX32\n", pVCpu->idCpu, RT_LO_U32(pApicCpu->uApicBaseMsr)));
843 LogRel(("APIC%u: uId = %#RX32\n", pVCpu->idCpu, pXApicPage->id.u8ApicId));
844 LogRel(("APIC%u: uPhysId = N/A\n", pVCpu->idCpu));
845 LogRel(("APIC%u: uArbId = N/A\n", pVCpu->idCpu));
846 LogRel(("APIC%u: uTpr = %#RX32\n", pVCpu->idCpu, pXApicPage->tpr.u8Tpr));
847 LogRel(("APIC%u: uSvr = %#RX32\n", pVCpu->idCpu, pXApicPage->svr.all.u32Svr));
848 LogRel(("APIC%u: uLdr = %#x\n", pVCpu->idCpu, pXApicPage->ldr.all.u32Ldr));
849 LogRel(("APIC%u: uDfr = %#x\n", pVCpu->idCpu, pXApicPage->dfr.all.u32Dfr));
850
851 for (size_t i = 0; i < 8; i++)
852 {
853 LogRel(("APIC%u: Isr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->isr.u[i].u32Reg));
854 LogRel(("APIC%u: Tmr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->tmr.u[i].u32Reg));
855 LogRel(("APIC%u: Irr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->irr.u[i].u32Reg));
856 }
857
858 for (size_t i = 0; i < XAPIC_MAX_LVT_ENTRIES_P4; i++)
859 {
860 uint16_t const offReg = XAPIC_OFF_LVT_START + (i << 4);
861 LogRel(("APIC%u: Lvt[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, apicR3ReadRawR32(pXApicPage, offReg)));
862 }
863
864 LogRel(("APIC%u: uEsr = %#RX32\n", pVCpu->idCpu, pXApicPage->esr.all.u32Errors));
865 LogRel(("APIC%u: uIcr_Lo = %#RX32\n", pVCpu->idCpu, pXApicPage->icr_lo.all.u32IcrLo));
866 LogRel(("APIC%u: uIcr_Hi = %#RX32\n", pVCpu->idCpu, pXApicPage->icr_hi.all.u32IcrHi));
867 LogRel(("APIC%u: uTimerDcr = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_dcr.all.u32DivideValue));
868 LogRel(("APIC%u: uCountShift = %#RX32\n", pVCpu->idCpu, apicGetTimerShift(pXApicPage)));
869 LogRel(("APIC%u: uInitialCount = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_icr.u32InitialCount));
870 LogRel(("APIC%u: u64InitialCountLoadTime = %#RX64\n", pVCpu->idCpu, pApicCpu->u64TimerInitial));
871 LogRel(("APIC%u: u64NextTime / TimerCCR = %#RX64\n", pVCpu->idCpu, pXApicPage->timer_ccr.u32CurrentCount));
872 break;
873 }
874
875 default:
876 {
877 LogRel(("APIC: apicR3DumpState: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
878 break;
879 }
880 }
881}
882
883#endif /* APIC_FUZZY_SSM_COMPAT_TEST */
884
885/**
886 * Worker for saving per-VM APIC data.
887 *
888 * @returns VBox status code.
889 * @param pVM The cross context VM structure.
890 * @param pSSM The SSM handle.
891 */
892static int apicR3SaveVMData(PVM pVM, PSSMHANDLE pSSM)
893{
894 PAPIC pApic = VM_TO_APIC(pVM);
895 SSMR3PutU32(pSSM, pVM->cCpus);
896 SSMR3PutBool(pSSM, pApic->fIoApicPresent);
897 return SSMR3PutU32(pSSM, pApic->enmMaxMode);
898}
899
900
901/**
902 * Worker for loading per-VM APIC data.
903 *
904 * @returns VBox status code.
905 * @param pVM The cross context VM structure.
906 * @param pSSM The SSM handle.
907 */
908static int apicR3LoadVMData(PVM pVM, PSSMHANDLE pSSM)
909{
910 PAPIC pApic = VM_TO_APIC(pVM);
911
912 /* Load and verify number of CPUs. */
913 uint32_t cCpus;
914 int rc = SSMR3GetU32(pSSM, &cCpus);
915 AssertRCReturn(rc, rc);
916 if (cCpus != pVM->cCpus)
917 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%u config=%u"), cCpus, pVM->cCpus);
918
919 /* Load and verify I/O APIC presence. */
920 bool fIoApicPresent;
921 rc = SSMR3GetBool(pSSM, &fIoApicPresent);
922 AssertRCReturn(rc, rc);
923 if (fIoApicPresent != pApic->fIoApicPresent)
924 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApicPresent: saved=%RTbool config=%RTbool"),
925 fIoApicPresent, pApic->fIoApicPresent);
926
927 /* Load and verify configured max APIC mode. */
928 uint32_t uSavedMaxApicMode;
929 rc = SSMR3GetU32(pSSM, &uSavedMaxApicMode);
930 AssertRCReturn(rc, rc);
931 if (uSavedMaxApicMode != (uint32_t)pApic->enmMaxMode)
932 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicMode: saved=%u config=%u"),
933 uSavedMaxApicMode, pApic->enmMaxMode);
934 return VINF_SUCCESS;
935}
936
937
938/**
939 * Worker for loading per-VCPU APIC data for legacy (old) saved-states.
940 *
941 * @returns VBox status code.
942 * @param pVM The cross context VM structure.
943 * @param pVCpu The cross context virtual CPU structure.
944 * @param pSSM The SSM handle.
945 * @param uVersion Data layout version.
946 */
947static int apicR3LoadLegacyVCpuData(PVM pVM, PVMCPU pVCpu, PSSMHANDLE pSSM, uint32_t uVersion)
948{
949 AssertReturn(uVersion <= APIC_SAVED_STATE_VERSION_VBOX_50, VERR_NOT_SUPPORTED);
950
951 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
952 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
953
954 uint32_t uApicBaseLo;
955 int rc = SSMR3GetU32(pSSM, &uApicBaseLo);
956 AssertRCReturn(rc, rc);
957 pApicCpu->uApicBaseMsr = uApicBaseLo;
958 Log2(("APIC%u: apicR3LoadLegacyVCpuData: uApicBaseMsr=%#RX64\n", pVCpu->idCpu, pApicCpu->uApicBaseMsr));
959
960 switch (uVersion)
961 {
962 case APIC_SAVED_STATE_VERSION_VBOX_50:
963 case APIC_SAVED_STATE_VERSION_VBOX_30:
964 {
965 uint32_t uApicId, uPhysApicId, uArbId;
966 SSMR3GetU32(pSSM, &uApicId); pXApicPage->id.u8ApicId = uApicId;
967 SSMR3GetU32(pSSM, &uPhysApicId); NOREF(uPhysApicId); /* PhysId == pVCpu->idCpu */
968 SSMR3GetU32(pSSM, &uArbId); NOREF(uArbId); /* ArbID is & was unused. */
969 break;
970 }
971
972 case APIC_SAVED_STATE_VERSION_ANCIENT:
973 {
974 uint8_t uPhysApicId;
975 SSMR3GetU8(pSSM, &pXApicPage->id.u8ApicId);
976 SSMR3GetU8(pSSM, &uPhysApicId); NOREF(uPhysApicId); /* PhysId == pVCpu->idCpu */
977 break;
978 }
979
980 default:
981 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
982 }
983
984 uint32_t u32Tpr;
985 SSMR3GetU32(pSSM, &u32Tpr);
986 pXApicPage->tpr.u8Tpr = u32Tpr & XAPIC_TPR_VALID;
987
988 SSMR3GetU32(pSSM, &pXApicPage->svr.all.u32Svr);
989 SSMR3GetU8(pSSM, &pXApicPage->ldr.u.u8LogicalApicId);
990
991 uint8_t uDfr;
992 SSMR3GetU8(pSSM, &uDfr);
993 pXApicPage->dfr.u.u4Model = uDfr >> 4;
994
995 AssertCompile(RT_ELEMENTS(pXApicPage->isr.u) == 8);
996 AssertCompile(RT_ELEMENTS(pXApicPage->tmr.u) == 8);
997 AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 8);
998 for (size_t i = 0; i < 8; i++)
999 {
1000 SSMR3GetU32(pSSM, &pXApicPage->isr.u[i].u32Reg);
1001 SSMR3GetU32(pSSM, &pXApicPage->tmr.u[i].u32Reg);
1002 SSMR3GetU32(pSSM, &pXApicPage->irr.u[i].u32Reg);
1003 }
1004
1005 SSMR3GetU32(pSSM, &pXApicPage->lvt_timer.all.u32LvtTimer);
1006 SSMR3GetU32(pSSM, &pXApicPage->lvt_thermal.all.u32LvtThermal);
1007 SSMR3GetU32(pSSM, &pXApicPage->lvt_perf.all.u32LvtPerf);
1008 SSMR3GetU32(pSSM, &pXApicPage->lvt_lint0.all.u32LvtLint0);
1009 SSMR3GetU32(pSSM, &pXApicPage->lvt_lint1.all.u32LvtLint1);
1010 SSMR3GetU32(pSSM, &pXApicPage->lvt_error.all.u32LvtError);
1011
1012 SSMR3GetU32(pSSM, &pXApicPage->esr.all.u32Errors);
1013 SSMR3GetU32(pSSM, &pXApicPage->icr_lo.all.u32IcrLo);
1014 SSMR3GetU32(pSSM, &pXApicPage->icr_hi.all.u32IcrHi);
1015
1016 uint32_t u32TimerShift;
1017 SSMR3GetU32(pSSM, &pXApicPage->timer_dcr.all.u32DivideValue);
1018 SSMR3GetU32(pSSM, &u32TimerShift);
1019 /*
1020 * Old implementation may have left the timer shift uninitialized until
1021 * the timer configuration register was written. Unfortunately zero is
1022 * also a valid timer shift value, so we're just going to ignore it
1023 * completely. The shift count can always be derived from the DCR.
1024 * See @bugref{8245#c98}.
1025 */
1026 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
1027
1028 SSMR3GetU32(pSSM, &pXApicPage->timer_icr.u32InitialCount);
1029 SSMR3GetU64(pSSM, &pApicCpu->u64TimerInitial);
1030 uint64_t uNextTS;
1031 rc = SSMR3GetU64(pSSM, &uNextTS); AssertRCReturn(rc, rc);
1032 if (uNextTS >= pApicCpu->u64TimerInitial + ((pXApicPage->timer_icr.u32InitialCount + 1) << uTimerShift))
1033 pXApicPage->timer_ccr.u32CurrentCount = pXApicPage->timer_icr.u32InitialCount;
1034
1035 rc = TMR3TimerLoad(pApicCpu->pTimerR3, pSSM);
1036 AssertRCReturn(rc, rc);
1037 Assert(pApicCpu->uHintedTimerInitialCount == 0);
1038 Assert(pApicCpu->uHintedTimerShift == 0);
1039 if (TMTimerIsActive(pApicCpu->pTimerR3))
1040 {
1041 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1042 apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
1043 }
1044
1045 return rc;
1046}
1047
1048
1049/**
1050 * @copydoc FNSSMDEVLIVEEXEC
1051 */
1052static DECLCALLBACK(int) apicR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
1053{
1054 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1055 PVM pVM = PDMDevHlpGetVM(pApicDev->pDevInsR3);
1056
1057 LogFlow(("APIC: apicR3LiveExec: uPass=%u\n", uPass));
1058
1059 int rc = apicR3SaveVMData(pVM, pSSM);
1060 AssertRCReturn(rc, rc);
1061 return VINF_SSM_DONT_CALL_AGAIN;
1062}
1063
1064
1065/**
1066 * @copydoc FNSSMDEVSAVEEXEC
1067 */
1068static DECLCALLBACK(int) apicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1069{
1070 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1071 PVM pVM = PDMDevHlpGetVM(pDevIns);
1072 PAPIC pApic = VM_TO_APIC(pVM);
1073 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
1074
1075 LogFlow(("APIC: apicR3SaveExec\n"));
1076
1077 /* Save per-VM data. */
1078 int rc = apicR3SaveVMData(pVM, pSSM);
1079 AssertRCReturn(rc, rc);
1080
1081 /* Save per-VCPU data.*/
1082 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1083 {
1084 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1085 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1086
1087 /* Update interrupts from the pending-interrupts bitmaps to the IRR. */
1088 APICUpdatePendingInterrupts(pVCpu);
1089
1090 /* Save the auxiliary data. */
1091 SSMR3PutU64(pSSM, pApicCpu->uApicBaseMsr);
1092 SSMR3PutU32(pSSM, pApicCpu->uEsrInternal);
1093
1094 /* Save the APIC page. */
1095 if (XAPIC_IN_X2APIC_MODE(pVCpu))
1096 SSMR3PutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
1097 else
1098 SSMR3PutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
1099
1100 /* Save the timer. */
1101 SSMR3PutU64(pSSM, pApicCpu->u64TimerInitial);
1102 TMR3TimerSave(pApicCpu->pTimerR3, pSSM);
1103
1104 /* Save the LINT0, LINT1 interrupt line states. */
1105 SSMR3PutBool(pSSM, pApicCpu->fActiveLint0);
1106 SSMR3PutBool(pSSM, pApicCpu->fActiveLint1);
1107
1108#if defined(APIC_FUZZY_SSM_COMPAT_TEST) || defined(DEBUG_ramshankar)
1109 apicR3DumpState(pVCpu, "Saved state", APIC_SAVED_STATE_VERSION);
1110#endif
1111 }
1112
1113#ifdef APIC_FUZZY_SSM_COMPAT_TEST
1114 /* The state is fuzzy, don't even bother trying to load the guest. */
1115 return VERR_INVALID_STATE;
1116#else
1117 return rc;
1118#endif
1119}
1120
1121
1122/**
1123 * @copydoc FNSSMDEVLOADEXEC
1124 */
1125static DECLCALLBACK(int) apicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1126{
1127 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1128 PVM pVM = PDMDevHlpGetVM(pDevIns);
1129 PAPIC pApic = VM_TO_APIC(pVM);
1130
1131 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
1132 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
1133
1134 LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1135
1136 /* Weed out invalid versions. */
1137 if ( uVersion != APIC_SAVED_STATE_VERSION
1138 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_51_BETA2
1139 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_50
1140 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_30
1141 && uVersion != APIC_SAVED_STATE_VERSION_ANCIENT)
1142 {
1143 LogRel(("APIC: apicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1144 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1145 }
1146
1147 int rc = VINF_SUCCESS;
1148 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_30)
1149 {
1150 rc = apicR3LoadVMData(pVM, pSSM);
1151 AssertRCReturn(rc, rc);
1152
1153 if (uVersion == APIC_SAVED_STATE_VERSION)
1154 { /* Load any new additional per-VM data. */ }
1155 }
1156
1157 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1158 {
1159 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1160 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1161
1162 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_50)
1163 {
1164 /* Load the auxiliary data. */
1165 SSMR3GetU64(pSSM, (uint64_t *)&pApicCpu->uApicBaseMsr);
1166 SSMR3GetU32(pSSM, &pApicCpu->uEsrInternal);
1167
1168 /* Load the APIC page. */
1169 if (XAPIC_IN_X2APIC_MODE(pVCpu))
1170 SSMR3GetStruct(pSSM, pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
1171 else
1172 SSMR3GetStruct(pSSM, pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
1173
1174 /* Load the timer. */
1175 rc = SSMR3GetU64(pSSM, &pApicCpu->u64TimerInitial); AssertRCReturn(rc, rc);
1176 rc = TMR3TimerLoad(pApicCpu->pTimerR3, pSSM); AssertRCReturn(rc, rc);
1177 Assert(pApicCpu->uHintedTimerShift == 0);
1178 Assert(pApicCpu->uHintedTimerInitialCount == 0);
1179 if (TMTimerIsActive(pApicCpu->pTimerR3))
1180 {
1181 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
1182 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1183 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
1184 apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
1185 }
1186
1187 /* Load the LINT0, LINT1 interrupt line states. */
1188 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_51_BETA2)
1189 {
1190 SSMR3GetBool(pSSM, (bool *)&pApicCpu->fActiveLint0);
1191 SSMR3GetBool(pSSM, (bool *)&pApicCpu->fActiveLint1);
1192 }
1193 }
1194 else
1195 {
1196 rc = apicR3LoadLegacyVCpuData(pVM, pVCpu, pSSM, uVersion);
1197 AssertRCReturn(rc, rc);
1198 }
1199
1200 /*
1201 * Check that we're still good wrt restored data, then tell CPUM about the current CPUID[1].EDX[9] visibility.
1202 */
1203 rc = SSMR3HandleGetStatus(pSSM);
1204 AssertRCReturn(rc, rc);
1205 CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, RT_BOOL(pApicCpu->uApicBaseMsr & MSR_IA32_APICBASE_EN));
1206
1207#if defined(APIC_FUZZY_SSM_COMPAT_TEST) || defined(DEBUG_ramshankar)
1208 apicR3DumpState(pVCpu, "Loaded state", uVersion);
1209#endif
1210 }
1211
1212 return rc;
1213}
1214
1215
1216/**
1217 * The timer callback.
1218 *
1219 * @param pDevIns The device instance.
1220 * @param pTimer The timer handle.
1221 * @param pvUser Opaque pointer to the VMCPU.
1222 *
1223 * @thread Any.
1224 * @remarks Currently this function is invoked on the last EMT, see @c
1225 * idTimerCpu in tmR3TimerCallback(). However, the code does -not-
1226 * rely on this and is designed to work with being invoked on any
1227 * thread.
1228 */
1229static DECLCALLBACK(void) apicR3TimerCallback(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1230{
1231 PVMCPU pVCpu = (PVMCPU)pvUser;
1232 Assert(TMTimerIsLockOwner(pTimer));
1233 Assert(pVCpu);
1234 LogFlow(("APIC%u: apicR3TimerCallback\n", pVCpu->idCpu));
1235
1236 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1237 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1238 uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
1239 STAM_COUNTER_INC(&pApicCpu->StatTimerCallback);
1240 if (!XAPIC_LVT_IS_MASKED(uLvtTimer))
1241 {
1242 uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
1243 Log2(("APIC%u: apicR3TimerCallback: Raising timer interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
1244 apicPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE);
1245 }
1246
1247 XAPICTIMERMODE enmTimerMode = XAPIC_LVT_GET_TIMER_MODE(uLvtTimer);
1248 switch (enmTimerMode)
1249 {
1250 case XAPICTIMERMODE_PERIODIC:
1251 {
1252 /* The initial-count register determines if the periodic timer is re-armed. */
1253 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1254 pXApicPage->timer_ccr.u32CurrentCount = uInitialCount;
1255 if (uInitialCount)
1256 {
1257 Log2(("APIC%u: apicR3TimerCallback: Re-arming timer. uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
1258 apicStartTimer(pVCpu, uInitialCount);
1259 }
1260 break;
1261 }
1262
1263 case XAPICTIMERMODE_ONESHOT:
1264 {
1265 pXApicPage->timer_ccr.u32CurrentCount = 0;
1266 break;
1267 }
1268
1269 case XAPICTIMERMODE_TSC_DEADLINE:
1270 {
1271 /** @todo implement TSC deadline. */
1272 AssertMsgFailed(("APIC: TSC deadline mode unimplemented\n"));
1273 break;
1274 }
1275 }
1276}
1277
1278
1279/**
1280 * @interface_method_impl{PDMDEVREG,pfnReset}
1281 */
1282static DECLCALLBACK(void) apicR3Reset(PPDMDEVINS pDevIns)
1283{
1284 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1285 PVM pVM = PDMDevHlpGetVM(pDevIns);
1286 VM_ASSERT_EMT0(pVM);
1287 VM_ASSERT_IS_NOT_RUNNING(pVM);
1288
1289 LogFlow(("APIC: apicR3Reset\n"));
1290
1291 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1292 {
1293 PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
1294 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpuDest);
1295
1296 if (TMTimerIsActive(pApicCpu->pTimerR3))
1297 TMTimerStop(pApicCpu->pTimerR3);
1298
1299 apicR3ResetCpu(pVCpuDest, true /* fResetApicBaseMsr */);
1300
1301 /* Clear the interrupt pending force flag. */
1302 apicClearInterruptFF(pVCpuDest, PDMAPICIRQ_HARDWARE);
1303 }
1304}
1305
1306
1307/**
1308 * @interface_method_impl{PDMDEVREG,pfnRelocate}
1309 */
1310static DECLCALLBACK(void) apicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1311{
1312 PVM pVM = PDMDevHlpGetVM(pDevIns);
1313 PAPIC pApic = VM_TO_APIC(pVM);
1314 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1315
1316 LogFlow(("APIC: apicR3Relocate: pVM=%p pDevIns=%p offDelta=%RGi\n", pVM, pDevIns, offDelta));
1317
1318 pApicDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1319 pApicDev->pApicHlpRC = pApicDev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
1320 pApicDev->pCritSectRC = pApicDev->pApicHlpR3->pfnGetRCCritSect(pDevIns);
1321
1322 pApic->pApicDevRC = PDMINS_2_DATA_RCPTR(pDevIns);
1323 pApic->pvApicPibRC += offDelta;
1324
1325 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1326 {
1327 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1328 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1329 pApicCpu->pTimerRC = TMTimerRCPtr(pApicCpu->pTimerR3);
1330
1331 pApicCpu->pvApicPageRC += offDelta;
1332 pApicCpu->pvApicPibRC += offDelta;
1333 Log2(("APIC%u: apicR3Relocate: APIC PIB at %RGv\n", pVCpu->idCpu, pApicCpu->pvApicPibRC));
1334 }
1335}
1336
1337
1338/**
1339 * Terminates the APIC state.
1340 *
1341 * @param pVM The cross context VM structure.
1342 */
1343static void apicR3TermState(PVM pVM)
1344{
1345 PAPIC pApic = VM_TO_APIC(pVM);
1346 LogFlow(("APIC: apicR3TermState: pVM=%p\n", pVM));
1347
1348 /* Unmap and free the PIB. */
1349 if (pApic->pvApicPibR3 != NIL_RTR3PTR)
1350 {
1351 size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
1352 if (cPages == 1)
1353 SUPR3PageFreeEx(pApic->pvApicPibR3, cPages);
1354 else
1355 SUPR3ContFree(pApic->pvApicPibR3, cPages);
1356 pApic->pvApicPibR3 = NIL_RTR3PTR;
1357 pApic->pvApicPibR0 = NIL_RTR0PTR;
1358 pApic->pvApicPibRC = NIL_RTRCPTR;
1359 }
1360
1361 /* Unmap and free the virtual-APIC pages. */
1362 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1363 {
1364 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1365 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1366
1367 pApicCpu->pvApicPibR3 = NIL_RTR3PTR;
1368 pApicCpu->pvApicPibR0 = NIL_RTR0PTR;
1369 pApicCpu->pvApicPibRC = NIL_RTRCPTR;
1370
1371 if (pApicCpu->pvApicPageR3 != NIL_RTR3PTR)
1372 {
1373 SUPR3PageFreeEx(pApicCpu->pvApicPageR3, 1 /* cPages */);
1374 pApicCpu->pvApicPageR3 = NIL_RTR3PTR;
1375 pApicCpu->pvApicPageR0 = NIL_RTR0PTR;
1376 pApicCpu->pvApicPageRC = NIL_RTRCPTR;
1377 }
1378 }
1379}
1380
1381
1382/**
1383 * Initializes the APIC state.
1384 *
1385 * @returns VBox status code.
1386 * @param pVM The cross context VM structure.
1387 */
1388static int apicR3InitState(PVM pVM)
1389{
1390 PAPIC pApic = VM_TO_APIC(pVM);
1391 LogFlow(("APIC: apicR3InitState: pVM=%p\n", pVM));
1392
1393 /* With hardware virtualization, we don't need to map the APIC in GC. */
1394 bool const fNeedsGCMapping = !HMIsEnabled(pVM);
1395
1396 /*
1397 * Allocate and map the pending-interrupt bitmap (PIB).
1398 *
1399 * We allocate all the VCPUs' PIBs contiguously in order to save space as
1400 * physically contiguous allocations are rounded to a multiple of page size.
1401 */
1402 Assert(pApic->pvApicPibR3 == NIL_RTR3PTR);
1403 Assert(pApic->pvApicPibR0 == NIL_RTR0PTR);
1404 Assert(pApic->pvApicPibRC == NIL_RTRCPTR);
1405 pApic->cbApicPib = RT_ALIGN_Z(pVM->cCpus * sizeof(APICPIB), PAGE_SIZE);
1406 size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
1407 if (cPages == 1)
1408 {
1409 SUPPAGE SupApicPib;
1410 RT_ZERO(SupApicPib);
1411 SupApicPib.Phys = NIL_RTHCPHYS;
1412 int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, &pApic->pvApicPibR3, &pApic->pvApicPibR0, &SupApicPib);
1413 if (RT_SUCCESS(rc))
1414 {
1415 pApic->HCPhysApicPib = SupApicPib.Phys;
1416 AssertLogRelReturn(pApic->pvApicPibR3, VERR_INTERNAL_ERROR);
1417 }
1418 else
1419 {
1420 LogRel(("APIC: Failed to allocate %u bytes for the pending-interrupt bitmap, rc=%Rrc\n", pApic->cbApicPib, rc));
1421 return rc;
1422 }
1423 }
1424 else
1425 pApic->pvApicPibR3 = SUPR3ContAlloc(cPages, &pApic->pvApicPibR0, &pApic->HCPhysApicPib);
1426
1427 if (pApic->pvApicPibR3)
1428 {
1429 AssertLogRelReturn(pApic->pvApicPibR0 != NIL_RTR0PTR, VERR_INTERNAL_ERROR);
1430 AssertLogRelReturn(pApic->HCPhysApicPib != NIL_RTHCPHYS, VERR_INTERNAL_ERROR);
1431
1432 /* Initialize the PIB. */
1433 RT_BZERO(pApic->pvApicPibR3, pApic->cbApicPib);
1434
1435 /* Map the PIB into GC. */
1436 if (fNeedsGCMapping)
1437 {
1438 pApic->pvApicPibRC = NIL_RTRCPTR;
1439 int rc = MMR3HyperMapHCPhys(pVM, pApic->pvApicPibR3, NIL_RTR0PTR, pApic->HCPhysApicPib, pApic->cbApicPib,
1440 "APIC PIB", (PRTGCPTR)&pApic->pvApicPibRC);
1441 if (RT_FAILURE(rc))
1442 {
1443 LogRel(("APIC: Failed to map %u bytes for the pending-interrupt bitmap into GC, rc=%Rrc\n", pApic->cbApicPib,
1444 rc));
1445 apicR3TermState(pVM);
1446 return rc;
1447 }
1448
1449 AssertLogRelReturn(pApic->pvApicPibRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
1450 }
1451
1452 /*
1453 * Allocate the map the virtual-APIC pages.
1454 */
1455 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1456 {
1457 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1458 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1459
1460 SUPPAGE SupApicPage;
1461 RT_ZERO(SupApicPage);
1462 SupApicPage.Phys = NIL_RTHCPHYS;
1463
1464 Assert(pVCpu->idCpu == idCpu);
1465 Assert(pApicCpu->pvApicPageR3 == NIL_RTR0PTR);
1466 Assert(pApicCpu->pvApicPageR0 == NIL_RTR0PTR);
1467 Assert(pApicCpu->pvApicPageRC == NIL_RTRCPTR);
1468 AssertCompile(sizeof(XAPICPAGE) == PAGE_SIZE);
1469 pApicCpu->cbApicPage = sizeof(XAPICPAGE);
1470 int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, &pApicCpu->pvApicPageR3, &pApicCpu->pvApicPageR0,
1471 &SupApicPage);
1472 if (RT_SUCCESS(rc))
1473 {
1474 AssertLogRelReturn(pApicCpu->pvApicPageR3 != NIL_RTR3PTR, VERR_INTERNAL_ERROR);
1475 AssertLogRelReturn(pApicCpu->HCPhysApicPage != NIL_RTHCPHYS, VERR_INTERNAL_ERROR);
1476 pApicCpu->HCPhysApicPage = SupApicPage.Phys;
1477
1478 /* Map the virtual-APIC page into GC. */
1479 if (fNeedsGCMapping)
1480 {
1481 rc = MMR3HyperMapHCPhys(pVM, pApicCpu->pvApicPageR3, NIL_RTR0PTR, pApicCpu->HCPhysApicPage,
1482 pApicCpu->cbApicPage, "APIC", (PRTGCPTR)&pApicCpu->pvApicPageRC);
1483 if (RT_FAILURE(rc))
1484 {
1485 LogRel(("APIC%u: Failed to map %u bytes for the virtual-APIC page into GC, rc=%Rrc", idCpu,
1486 pApicCpu->cbApicPage, rc));
1487 apicR3TermState(pVM);
1488 return rc;
1489 }
1490
1491 AssertLogRelReturn(pApicCpu->pvApicPageRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
1492 }
1493
1494 /* Associate the per-VCPU PIB pointers to the per-VM PIB mapping. */
1495 uint32_t const offApicPib = idCpu * sizeof(APICPIB);
1496 pApicCpu->pvApicPibR0 = (RTR0PTR)((RTR0UINTPTR)pApic->pvApicPibR0 + offApicPib);
1497 pApicCpu->pvApicPibR3 = (RTR3PTR)((RTR3UINTPTR)pApic->pvApicPibR3 + offApicPib);
1498 if (fNeedsGCMapping)
1499 pApicCpu->pvApicPibRC = (RTRCPTR)((RTRCUINTPTR)pApic->pvApicPibRC + offApicPib);
1500
1501 /* Initialize the virtual-APIC state. */
1502 RT_BZERO(pApicCpu->pvApicPageR3, pApicCpu->cbApicPage);
1503 apicR3ResetCpu(pVCpu, true /* fResetApicBaseMsr */);
1504
1505#ifdef DEBUG_ramshankar
1506 Assert(pApicCpu->pvApicPibR3 != NIL_RTR3PTR);
1507 Assert(pApicCpu->pvApicPibR0 != NIL_RTR0PTR);
1508 Assert(!fNeedsGCMapping || pApicCpu->pvApicPibRC != NIL_RTRCPTR);
1509 Assert(pApicCpu->pvApicPageR3 != NIL_RTR3PTR);
1510 Assert(pApicCpu->pvApicPageR0 != NIL_RTR0PTR);
1511 Assert(!fNeedsGCMapping || pApicCpu->pvApicPageRC != NIL_RTRCPTR);
1512 Assert(!fNeedsGCMapping || pApic->pvApicPibRC == pVM->aCpus[0].apic.s.pvApicPibRC);
1513#endif
1514 }
1515 else
1516 {
1517 LogRel(("APIC%u: Failed to allocate %u bytes for the virtual-APIC page, rc=%Rrc\n", idCpu, pApicCpu->cbApicPage, rc));
1518 apicR3TermState(pVM);
1519 return rc;
1520 }
1521 }
1522
1523#ifdef DEBUG_ramshankar
1524 Assert(pApic->pvApicPibR3 != NIL_RTR3PTR);
1525 Assert(pApic->pvApicPibR0 != NIL_RTR0PTR);
1526 Assert(!fNeedsGCMapping || pApic->pvApicPibRC != NIL_RTRCPTR);
1527#endif
1528 return VINF_SUCCESS;
1529 }
1530
1531 LogRel(("APIC: Failed to allocate %u bytes of physically contiguous memory for the pending-interrupt bitmap\n",
1532 pApic->cbApicPib));
1533 return VERR_NO_MEMORY;
1534}
1535
1536
1537/**
1538 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1539 */
1540static DECLCALLBACK(int) apicR3Destruct(PPDMDEVINS pDevIns)
1541{
1542 PVM pVM = PDMDevHlpGetVM(pDevIns);
1543 LogFlow(("APIC: apicR3Destruct: pVM=%p\n", pVM));
1544
1545 apicR3TermState(pVM);
1546 return VINF_SUCCESS;
1547}
1548
1549
1550/**
1551 * @interface_method_impl{PDMDEVREG,pfnInitComplete}
1552 */
1553static DECLCALLBACK(int) apicR3InitComplete(PPDMDEVINS pDevIns)
1554{
1555 PVM pVM = PDMDevHlpGetVM(pDevIns);
1556 PAPIC pApic = VM_TO_APIC(pVM);
1557
1558 /*
1559 * Init APIC settings that rely on HM and CPUM configurations.
1560 */
1561 CPUMCPUIDLEAF CpuLeaf;
1562 int rc = CPUMR3CpuIdGetLeaf(pVM, &CpuLeaf, 1, 0);
1563 AssertRCReturn(rc, rc);
1564
1565 pApic->fSupportsTscDeadline = RT_BOOL(CpuLeaf.uEcx & X86_CPUID_FEATURE_ECX_TSCDEADL);
1566 pApic->fPostedIntrsEnabled = HMR3IsPostedIntrsEnabled(pVM->pUVM);
1567 pApic->fVirtApicRegsEnabled = HMR3IsVirtApicRegsEnabled(pVM->pUVM);
1568
1569 LogRel(("APIC: fPostedIntrsEnabled=%RTbool fVirtApicRegsEnabled=%RTbool fSupportsTscDeadline=%RTbool\n",
1570 pApic->fPostedIntrsEnabled, pApic->fVirtApicRegsEnabled, pApic->fSupportsTscDeadline));
1571
1572 return VINF_SUCCESS;
1573}
1574
1575
1576/**
1577 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1578 */
1579static DECLCALLBACK(int) apicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1580{
1581 /*
1582 * Validate inputs.
1583 */
1584 Assert(iInstance == 0);
1585 Assert(pDevIns);
1586
1587 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1588 PVM pVM = PDMDevHlpGetVM(pDevIns);
1589 PAPIC pApic = VM_TO_APIC(pVM);
1590
1591 /*
1592 * Init the data.
1593 */
1594 pApicDev->pDevInsR3 = pDevIns;
1595 pApicDev->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1596 pApicDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1597
1598 pApic->pApicDevR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1599 pApic->pApicDevR3 = (PAPICDEV)PDMINS_2_DATA_R3PTR(pDevIns);
1600 pApic->pApicDevRC = PDMINS_2_DATA_RCPTR(pDevIns);
1601
1602 /*
1603 * Validate APIC settings.
1604 */
1605 if (!CFGMR3AreValuesValid(pCfg, "RZEnabled\0"
1606 "Mode\0"
1607 "IOAPIC\0"
1608 "NumCPUs\0"))
1609 {
1610 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1611 N_("APIC configuration error: unknown option specified"));
1612 }
1613
1614 int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pApic->fRZEnabled, true);
1615 AssertLogRelRCReturn(rc, rc);
1616
1617 rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &pApic->fIoApicPresent, true);
1618 AssertLogRelRCReturn(rc, rc);
1619
1620 /* Max APIC feature level. */
1621 uint8_t uMaxMode;
1622 rc = CFGMR3QueryU8Def(pCfg, "Mode", &uMaxMode, PDMAPICMODE_APIC);
1623 AssertLogRelRCReturn(rc, rc);
1624 switch ((PDMAPICMODE)uMaxMode)
1625 {
1626 case PDMAPICMODE_NONE:
1627#if 1
1628 /** @todo permanently disabling the APIC won't really work (needs
1629 * fixing in HM, CPUM, PDM and possibly other places). See
1630 * @bugref{8353}. */
1631 return VMR3SetError(pVM->pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, "APIC mode 'none' is not supported yet.");
1632#endif
1633 case PDMAPICMODE_APIC:
1634 case PDMAPICMODE_X2APIC:
1635 break;
1636 default:
1637 return VMR3SetError(pVM->pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, "APIC mode %d unknown.", uMaxMode);
1638 }
1639 pApic->enmMaxMode = (PDMAPICMODE)uMaxMode;
1640
1641 /*
1642 * Disable automatic PDM locking for this device.
1643 */
1644 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1645 AssertRCReturn(rc, rc);
1646
1647 /*
1648 * Register the APIC with PDM.
1649 */
1650 PDMAPICREG ApicReg;
1651 RT_ZERO(ApicReg);
1652 ApicReg.u32Version = PDM_APICREG_VERSION;
1653 ApicReg.pfnGetInterruptR3 = apicGetInterrupt;
1654 ApicReg.pfnSetBaseMsrR3 = apicSetBaseMsr;
1655 ApicReg.pfnGetBaseMsrR3 = apicGetBaseMsr;
1656 ApicReg.pfnSetTprR3 = apicSetTpr;
1657 ApicReg.pfnGetTprR3 = apicGetTpr;
1658 ApicReg.pfnWriteMsrR3 = apicWriteMsr;
1659 ApicReg.pfnReadMsrR3 = apicReadMsr;
1660 ApicReg.pfnBusDeliverR3 = apicBusDeliver;
1661 ApicReg.pfnLocalInterruptR3 = apicLocalInterrupt;
1662 ApicReg.pfnGetTimerFreqR3 = apicGetTimerFreq;
1663
1664 /*
1665 * We always require R0 functionality (e.g. apicGetTpr() called by HMR0 VT-x/AMD-V code).
1666 * Hence, 'fRZEnabled' strictly only applies to MMIO and MSR read/write handlers returning
1667 * to ring-3. We still need other handlers like apicGetTpr() in ring-0 for now.
1668 */
1669 {
1670 ApicReg.pszGetInterruptRC = "apicGetInterrupt";
1671 ApicReg.pszSetBaseMsrRC = "apicSetBaseMsr";
1672 ApicReg.pszGetBaseMsrRC = "apicGetBaseMsr";
1673 ApicReg.pszSetTprRC = "apicSetTpr";
1674 ApicReg.pszGetTprRC = "apicGetTpr";
1675 ApicReg.pszWriteMsrRC = "apicWriteMsr";
1676 ApicReg.pszReadMsrRC = "apicReadMsr";
1677 ApicReg.pszBusDeliverRC = "apicBusDeliver";
1678 ApicReg.pszLocalInterruptRC = "apicLocalInterrupt";
1679 ApicReg.pszGetTimerFreqRC = "apicGetTimerFreq";
1680
1681 ApicReg.pszGetInterruptR0 = "apicGetInterrupt";
1682 ApicReg.pszSetBaseMsrR0 = "apicSetBaseMsr";
1683 ApicReg.pszGetBaseMsrR0 = "apicGetBaseMsr";
1684 ApicReg.pszSetTprR0 = "apicSetTpr";
1685 ApicReg.pszGetTprR0 = "apicGetTpr";
1686 ApicReg.pszWriteMsrR0 = "apicWriteMsr";
1687 ApicReg.pszReadMsrR0 = "apicReadMsr";
1688 ApicReg.pszBusDeliverR0 = "apicBusDeliver";
1689 ApicReg.pszLocalInterruptR0 = "apicLocalInterrupt";
1690 ApicReg.pszGetTimerFreqR0 = "apicGetTimerFreq";
1691 }
1692
1693 rc = PDMDevHlpAPICRegister(pDevIns, &ApicReg, &pApicDev->pApicHlpR3);
1694 AssertLogRelRCReturn(rc, rc);
1695 pApicDev->pCritSectR3 = pApicDev->pApicHlpR3->pfnGetR3CritSect(pDevIns);
1696
1697 /*
1698 * Initialize the APIC state.
1699 */
1700 /* First insert the MSR range of the x2APIC if enabled. */
1701 if (pApic->enmMaxMode == PDMAPICMODE_X2APIC)
1702 {
1703 rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic);
1704 AssertLogRelRCReturn(rc, rc);
1705 }
1706
1707 /* Tell CPUM about the APIC feature level so it can adjust APICBASE MSR GP mask and CPUID bits. */
1708 pApicDev->pApicHlpR3->pfnSetFeatureLevel(pDevIns, pApic->enmMaxMode);
1709
1710 /* Initialize the state. */
1711 rc = apicR3InitState(pVM);
1712 AssertRCReturn(rc, rc);
1713
1714 /*
1715 * Register the MMIO range.
1716 */
1717 PAPICCPU pApicCpu0 = VMCPU_TO_APICCPU(&pVM->aCpus[0]);
1718 RTGCPHYS GCPhysApicBase = MSR_IA32_APICBASE_GET_ADDR(pApicCpu0->uApicBaseMsr);
1719
1720 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NULL /* pvUser */,
1721 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED,
1722 apicWriteMmio, apicReadMmio, "APIC");
1723 if (RT_FAILURE(rc))
1724 return rc;
1725
1726 if (pApic->fRZEnabled)
1727 {
1728 pApicDev->pApicHlpRC = pApicDev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
1729 pApicDev->pCritSectRC = pApicDev->pApicHlpR3->pfnGetRCCritSect(pDevIns);
1730 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NIL_RTRCPTR /*pvUser*/,
1731 "apicWriteMmio", "apicReadMmio");
1732 if (RT_FAILURE(rc))
1733 return rc;
1734
1735 pApicDev->pApicHlpR0 = pApicDev->pApicHlpR3->pfnGetR0Helpers(pDevIns);
1736 pApicDev->pCritSectR0 = pApicDev->pApicHlpR3->pfnGetR0CritSect(pDevIns);
1737 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NIL_RTR0PTR /*pvUser*/,
1738 "apicWriteMmio", "apicReadMmio");
1739 if (RT_FAILURE(rc))
1740 return rc;
1741 }
1742
1743 /*
1744 * Create the APIC timers.
1745 */
1746 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1747 {
1748 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1749 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1750 RTStrPrintf(&pApicCpu->szTimerDesc[0], sizeof(pApicCpu->szTimerDesc), "APIC Timer %u", pVCpu->idCpu);
1751 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicR3TimerCallback, pVCpu, TMTIMER_FLAGS_NO_CRIT_SECT,
1752 pApicCpu->szTimerDesc, &pApicCpu->pTimerR3);
1753 if (RT_SUCCESS(rc))
1754 {
1755 pApicCpu->pTimerR0 = TMTimerR0Ptr(pApicCpu->pTimerR3);
1756 pApicCpu->pTimerRC = TMTimerRCPtr(pApicCpu->pTimerR3);
1757 }
1758 else
1759 return rc;
1760 }
1761
1762 /*
1763 * Register saved state callbacks.
1764 */
1765 rc = PDMDevHlpSSMRegister3(pDevIns, APIC_SAVED_STATE_VERSION, sizeof(*pApicDev), NULL /*pfnLiveExec*/, apicR3SaveExec,
1766 apicR3LoadExec);
1767 if (RT_FAILURE(rc))
1768 return rc;
1769
1770 /*
1771 * Register debugger info callbacks.
1772 *
1773 * We use separate callbacks rather than arguments so they can also be
1774 * dumped in an automated fashion while collecting crash diagnostics and
1775 * not just used during live debugging via the VM debugger.
1776 */
1777 rc = DBGFR3InfoRegisterInternalEx(pVM, "apic", "Dumps APIC basic information.", apicR3Info, DBGFINFO_FLAGS_ALL_EMTS);
1778 rc |= DBGFR3InfoRegisterInternalEx(pVM, "apiclvt", "Dumps APIC LVT information.", apicR3InfoLvt, DBGFINFO_FLAGS_ALL_EMTS);
1779 rc |= DBGFR3InfoRegisterInternalEx(pVM, "apictimer", "Dumps APIC timer information.", apicR3InfoTimer, DBGFINFO_FLAGS_ALL_EMTS);
1780 AssertRCReturn(rc, rc);
1781
1782#ifdef VBOX_WITH_STATISTICS
1783 /*
1784 * Statistics.
1785 */
1786#define APIC_REG_COUNTER(a_Reg, a_Desc, a_Key) \
1787 do { \
1788 rc = STAMR3RegisterF(pVM, a_Reg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, a_Desc, a_Key, idCpu); \
1789 AssertRCReturn(rc, rc); \
1790 } while(0)
1791
1792#define APIC_PROF_COUNTER(a_Reg, a_Desc, a_Key) \
1793 do { \
1794 rc = STAMR3RegisterF(pVM, a_Reg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, a_Desc, a_Key, \
1795 idCpu); \
1796 AssertRCReturn(rc, rc); \
1797 } while(0)
1798
1799 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1800 {
1801 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1802 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1803
1804 APIC_REG_COUNTER(&pApicCpu->StatMmioReadRZ, "Number of APIC MMIO reads in RZ.", "/Devices/APIC/%u/RZ/MmioRead");
1805 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteRZ, "Number of APIC MMIO writes in RZ.", "/Devices/APIC/%u/RZ/MmioWrite");
1806 APIC_REG_COUNTER(&pApicCpu->StatMsrReadRZ, "Number of APIC MSR reads in RZ.", "/Devices/APIC/%u/RZ/MsrRead");
1807 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteRZ, "Number of APIC MSR writes in RZ.", "/Devices/APIC/%u/RZ/MsrWrite");
1808
1809 APIC_REG_COUNTER(&pApicCpu->StatMmioReadR3, "Number of APIC MMIO reads in R3.", "/Devices/APIC/%u/R3/MmioReadR3");
1810 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteR3, "Number of APIC MMIO writes in R3.", "/Devices/APIC/%u/R3/MmioWriteR3");
1811 APIC_REG_COUNTER(&pApicCpu->StatMsrReadR3, "Number of APIC MSR reads in R3.", "/Devices/APIC/%u/R3/MsrReadR3");
1812 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteR3, "Number of APIC MSR writes in R3.", "/Devices/APIC/%u/R3/MsrWriteR3");
1813
1814 APIC_PROF_COUNTER(&pApicCpu->StatUpdatePendingIntrs, "Profiling of APICUpdatePendingInterrupts",
1815 "/PROF/CPU%d/APIC/UpdatePendingInterrupts");
1816 APIC_PROF_COUNTER(&pApicCpu->StatPostIntr, "Profiling of APICPostInterrupt", "/PROF/CPU%d/APIC/PostInterrupt");
1817
1818 APIC_REG_COUNTER(&pApicCpu->StatPostIntrAlreadyPending, "Number of times an interrupt is already pending.",
1819 "/Devices/APIC/%u/PostInterruptAlreadyPending");
1820 APIC_REG_COUNTER(&pApicCpu->StatTimerCallback, "Number of times the timer callback is invoked.",
1821 "/Devices/APIC/%u/TimerCallback");
1822
1823 APIC_REG_COUNTER(&pApicCpu->StatTprWrite, "Number of TPR writes.", "/Devices/APIC/%u/TprWrite");
1824 APIC_REG_COUNTER(&pApicCpu->StatTprRead, "Number of TPR reads.", "/Devices/APIC/%u/TprRead");
1825 APIC_REG_COUNTER(&pApicCpu->StatEoiWrite, "Number of EOI writes.", "/Devices/APIC/%u/EoiWrite");
1826 APIC_REG_COUNTER(&pApicCpu->StatMaskedByTpr, "Number of times TPR masks an interrupt in apicGetInterrupt.",
1827 "/Devices/APIC/%u/MaskedByTpr");
1828 APIC_REG_COUNTER(&pApicCpu->StatMaskedByPpr, "Number of times PPR masks an interrupt in apicGetInterrupt.",
1829 "/Devices/APIC/%u/MaskedByPpr");
1830 APIC_REG_COUNTER(&pApicCpu->StatTimerIcrWrite, "Number of times the timer ICR is written.",
1831 "/Devices/APIC/%u/TimerIcrWrite");
1832 APIC_REG_COUNTER(&pApicCpu->StatIcrLoWrite, "Number of times the ICR Lo (send IPI) is written.",
1833 "/Devices/APIC/%u/IcrLoWrite");
1834 }
1835# undef APIC_PROF_COUNTER
1836# undef APIC_REG_ACCESS_COUNTER
1837#endif
1838
1839 return VINF_SUCCESS;
1840}
1841
1842
1843/**
1844 * APIC device registration structure.
1845 */
1846const PDMDEVREG g_DeviceAPIC =
1847{
1848 /* u32Version */
1849 PDM_DEVREG_VERSION,
1850 /* szName */
1851 "apic",
1852 /* szRCMod */
1853 "VMMRC.rc",
1854 /* szR0Mod */
1855 "VMMR0.r0",
1856 /* pszDescription */
1857 "Advanced Programmable Interrupt Controller",
1858 /* fFlags */
1859 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36
1860 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
1861 /* fClass */
1862 PDM_DEVREG_CLASS_PIC,
1863 /* cMaxInstances */
1864 1,
1865 /* cbInstance */
1866 sizeof(APICDEV),
1867 /* pfnConstruct */
1868 apicR3Construct,
1869 /* pfnDestruct */
1870 apicR3Destruct,
1871 /* pfnRelocate */
1872 apicR3Relocate,
1873 /* pfnMemSetup */
1874 NULL,
1875 /* pfnPowerOn */
1876 NULL,
1877 /* pfnReset */
1878 apicR3Reset,
1879 /* pfnSuspend */
1880 NULL,
1881 /* pfnResume */
1882 NULL,
1883 /* pfnAttach */
1884 NULL,
1885 /* pfnDetach */
1886 NULL,
1887 /* pfnQueryInterface. */
1888 NULL,
1889 /* pfnInitComplete */
1890 apicR3InitComplete,
1891 /* pfnPowerOff */
1892 NULL,
1893 /* pfnSoftReset */
1894 NULL,
1895 /* u32VersionEnd */
1896 PDM_DEVREG_VERSION
1897};
1898
1899#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1900
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