VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/APIC.cpp@ 61116

Last change on this file since 61116 was 61116, checked in by vboxsync, 8 years ago

Main/Console: Use the APICMODE enum, tabs.
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1/* $Id: APIC.cpp 61116 2016-05-23 08:56:09Z vboxsync $ */
2/** @file
3 * APIC - Advanced Programmable Interrupt Controller.
4 */
5
6/*
7 * Copyright (C) 2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_APIC
23#include <VBox/log.h>
24#include "APICInternal.h"
25#include <VBox/vmm/cpum.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/ssm.h>
30#include <VBox/vmm/vm.h>
31
32
33#ifndef VBOX_DEVICE_STRUCT_TESTCASE
34/*********************************************************************************************************************************
35* Defined Constants And Macros *
36*********************************************************************************************************************************/
37/** The current APIC saved state version. */
38#define APIC_SAVED_STATE_VERSION 4
39/** The saved state version used by VirtualBox 5.0 and
40 * earlier. */
41#define APIC_SAVED_STATE_VERSION_VBOX_50 3
42/** The saved state version used by VirtualBox v3 and earlier.
43 * This does not include the config. */
44#define APIC_SAVED_STATE_VERSION_VBOX_30 2
45/** Some ancient version... */
46#define APIC_SAVED_STATE_VERSION_ANCIENT 1
47
48
49/*********************************************************************************************************************************
50* Global Variables *
51*********************************************************************************************************************************/
52/** Saved state field descriptors for XAPICPAGE. */
53static const SSMFIELD g_aXApicPageFields[] =
54{
55 SSMFIELD_ENTRY( XAPICPAGE, id.u8ApicId),
56 SSMFIELD_ENTRY( XAPICPAGE, version.all.u32Version),
57 SSMFIELD_ENTRY( XAPICPAGE, tpr.u8Tpr),
58 SSMFIELD_ENTRY( XAPICPAGE, apr.u8Apr),
59 SSMFIELD_ENTRY( XAPICPAGE, ppr.u8Ppr),
60 SSMFIELD_ENTRY( XAPICPAGE, ldr.all.u32Ldr),
61 SSMFIELD_ENTRY( XAPICPAGE, dfr.all.u32Dfr),
62 SSMFIELD_ENTRY( XAPICPAGE, svr.all.u32Svr),
63 SSMFIELD_ENTRY( XAPICPAGE, isr.u[0].u32Reg),
64 SSMFIELD_ENTRY( XAPICPAGE, isr.u[1].u32Reg),
65 SSMFIELD_ENTRY( XAPICPAGE, isr.u[2].u32Reg),
66 SSMFIELD_ENTRY( XAPICPAGE, isr.u[3].u32Reg),
67 SSMFIELD_ENTRY( XAPICPAGE, isr.u[4].u32Reg),
68 SSMFIELD_ENTRY( XAPICPAGE, isr.u[5].u32Reg),
69 SSMFIELD_ENTRY( XAPICPAGE, isr.u[6].u32Reg),
70 SSMFIELD_ENTRY( XAPICPAGE, isr.u[7].u32Reg),
71 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[0].u32Reg),
72 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[1].u32Reg),
73 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[2].u32Reg),
74 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[3].u32Reg),
75 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[4].u32Reg),
76 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[5].u32Reg),
77 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[6].u32Reg),
78 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[7].u32Reg),
79 SSMFIELD_ENTRY( XAPICPAGE, irr.u[0].u32Reg),
80 SSMFIELD_ENTRY( XAPICPAGE, irr.u[1].u32Reg),
81 SSMFIELD_ENTRY( XAPICPAGE, irr.u[2].u32Reg),
82 SSMFIELD_ENTRY( XAPICPAGE, irr.u[3].u32Reg),
83 SSMFIELD_ENTRY( XAPICPAGE, irr.u[4].u32Reg),
84 SSMFIELD_ENTRY( XAPICPAGE, irr.u[5].u32Reg),
85 SSMFIELD_ENTRY( XAPICPAGE, irr.u[6].u32Reg),
86 SSMFIELD_ENTRY( XAPICPAGE, irr.u[7].u32Reg),
87 SSMFIELD_ENTRY( XAPICPAGE, esr.all.u32Errors),
88 SSMFIELD_ENTRY( XAPICPAGE, icr_lo.all.u32IcrLo),
89 SSMFIELD_ENTRY( XAPICPAGE, icr_hi.all.u32IcrHi),
90 SSMFIELD_ENTRY( XAPICPAGE, lvt_timer.all.u32LvtTimer),
91 SSMFIELD_ENTRY( XAPICPAGE, lvt_thermal.all.u32LvtThermal),
92 SSMFIELD_ENTRY( XAPICPAGE, lvt_perf.all.u32LvtPerf),
93 SSMFIELD_ENTRY( XAPICPAGE, lvt_lint0.all.u32LvtLint0),
94 SSMFIELD_ENTRY( XAPICPAGE, lvt_lint1.all.u32LvtLint1),
95 SSMFIELD_ENTRY( XAPICPAGE, lvt_error.all.u32LvtError),
96 SSMFIELD_ENTRY( XAPICPAGE, timer_icr.u32InitialCount),
97 SSMFIELD_ENTRY( XAPICPAGE, timer_ccr.u32CurrentCount),
98 SSMFIELD_ENTRY( XAPICPAGE, timer_dcr.all.u32DivideValue),
99 SSMFIELD_ENTRY_TERM()
100};
101
102/** Saved state field descriptors for X2APICPAGE. */
103static const SSMFIELD g_aX2ApicPageFields[] =
104{
105 SSMFIELD_ENTRY(X2APICPAGE, id.u32ApicId),
106 SSMFIELD_ENTRY(X2APICPAGE, version.all.u32Version),
107 SSMFIELD_ENTRY(X2APICPAGE, tpr.u8Tpr),
108 SSMFIELD_ENTRY(X2APICPAGE, ppr.u8Ppr),
109 SSMFIELD_ENTRY(X2APICPAGE, ldr.u32LogicalApicId),
110 SSMFIELD_ENTRY(X2APICPAGE, svr.all.u32Svr),
111 SSMFIELD_ENTRY(X2APICPAGE, isr.u[0].u32Reg),
112 SSMFIELD_ENTRY(X2APICPAGE, isr.u[1].u32Reg),
113 SSMFIELD_ENTRY(X2APICPAGE, isr.u[2].u32Reg),
114 SSMFIELD_ENTRY(X2APICPAGE, isr.u[3].u32Reg),
115 SSMFIELD_ENTRY(X2APICPAGE, isr.u[4].u32Reg),
116 SSMFIELD_ENTRY(X2APICPAGE, isr.u[5].u32Reg),
117 SSMFIELD_ENTRY(X2APICPAGE, isr.u[6].u32Reg),
118 SSMFIELD_ENTRY(X2APICPAGE, isr.u[7].u32Reg),
119 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[0].u32Reg),
120 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[1].u32Reg),
121 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[2].u32Reg),
122 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[3].u32Reg),
123 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[4].u32Reg),
124 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[5].u32Reg),
125 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[6].u32Reg),
126 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[7].u32Reg),
127 SSMFIELD_ENTRY(X2APICPAGE, irr.u[0].u32Reg),
128 SSMFIELD_ENTRY(X2APICPAGE, irr.u[1].u32Reg),
129 SSMFIELD_ENTRY(X2APICPAGE, irr.u[2].u32Reg),
130 SSMFIELD_ENTRY(X2APICPAGE, irr.u[3].u32Reg),
131 SSMFIELD_ENTRY(X2APICPAGE, irr.u[4].u32Reg),
132 SSMFIELD_ENTRY(X2APICPAGE, irr.u[5].u32Reg),
133 SSMFIELD_ENTRY(X2APICPAGE, irr.u[6].u32Reg),
134 SSMFIELD_ENTRY(X2APICPAGE, irr.u[7].u32Reg),
135 SSMFIELD_ENTRY(X2APICPAGE, esr.all.u32Errors),
136 SSMFIELD_ENTRY(X2APICPAGE, icr_lo.all.u32IcrLo),
137 SSMFIELD_ENTRY(X2APICPAGE, icr_hi.u32IcrHi),
138 SSMFIELD_ENTRY(X2APICPAGE, lvt_timer.all.u32LvtTimer),
139 SSMFIELD_ENTRY(X2APICPAGE, lvt_thermal.all.u32LvtThermal),
140 SSMFIELD_ENTRY(X2APICPAGE, lvt_perf.all.u32LvtPerf),
141 SSMFIELD_ENTRY(X2APICPAGE, lvt_lint0.all.u32LvtLint0),
142 SSMFIELD_ENTRY(X2APICPAGE, lvt_lint1.all.u32LvtLint1),
143 SSMFIELD_ENTRY(X2APICPAGE, lvt_error.all.u32LvtError),
144 SSMFIELD_ENTRY(X2APICPAGE, timer_icr.u32InitialCount),
145 SSMFIELD_ENTRY(X2APICPAGE, timer_ccr.u32CurrentCount),
146 SSMFIELD_ENTRY(X2APICPAGE, timer_dcr.all.u32DivideValue),
147 SSMFIELD_ENTRY_TERM()
148};
149
150
151/**
152 * Initializes per-VCPU APIC to the state following an INIT reset
153 * ("Wait-for-SIPI" state).
154 *
155 * @param pVCpu The cross context virtual CPU structure.
156 */
157static void apicR3InitIpi(PVMCPU pVCpu)
158{
159 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
160 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
161
162 /*
163 * See Intel spec. 10.4.7.3 "Local APIC State After an INIT Reset (Wait-for-SIPI State)"
164 * and AMD spec 16.3.2 "APIC Registers".
165 */
166 RT_ZERO(pXApicPage->irr);
167 RT_ZERO(pXApicPage->irr);
168 RT_ZERO(pXApicPage->isr);
169 RT_ZERO(pXApicPage->tmr);
170 RT_ZERO(pXApicPage->icr_hi);
171 RT_ZERO(pXApicPage->icr_lo);
172 RT_ZERO(pXApicPage->ldr);
173 RT_ZERO(pXApicPage->tpr);
174 RT_ZERO(pXApicPage->timer_icr);
175 RT_ZERO(pXApicPage->timer_ccr);
176 RT_ZERO(pXApicPage->timer_dcr);
177
178 pXApicPage->dfr.u.u4Model = XAPICDESTFORMAT_FLAT;
179 pXApicPage->dfr.u.u28ReservedMb1 = UINT32_C(0xfffffff);
180
181 /** @todo CMCI. */
182
183 RT_ZERO(pXApicPage->lvt_timer);
184 pXApicPage->lvt_timer.u.u1Mask = 1;
185
186#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
187 RT_ZERO(pXApicPage->lvt_thermal);
188 pXApicPage->lvt_thermal.u.u1Mask = 1;
189#endif
190
191 RT_ZERO(pXApicPage->lvt_perf);
192 pXApicPage->lvt_perf.u.u1Mask = 1;
193
194 RT_ZERO(pXApicPage->lvt_lint0);
195 pXApicPage->lvt_lint0.u.u1Mask = 1;
196
197 RT_ZERO(pXApicPage->lvt_lint1);
198 pXApicPage->lvt_lint1.u.u1Mask = 1;
199
200 RT_ZERO(pXApicPage->lvt_error);
201 pXApicPage->lvt_error.u.u1Mask = 1;
202
203 RT_ZERO(pXApicPage->svr);
204 pXApicPage->svr.u.u8SpuriousVector = 0xff;
205
206 /* The self-IPI register is reset to 0. See Intel spec. 10.12.5.1 "x2APIC States" */
207 PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
208 RT_ZERO(pX2ApicPage->self_ipi);
209
210 /* Clear the pending-interrupt bitmaps. */
211 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
212 RT_BZERO(&pApicCpu->ApicPibLevel, sizeof(APICPIB));
213 RT_BZERO(pApicCpu->pvApicPibR3, sizeof(APICPIB));
214}
215
216
217/**
218 * Resets the APIC base MSR.
219 *
220 * @param pVCpu The cross context virtual CPU structure.
221 */
222static void apicR3ResetBaseMsr(PVMCPU pVCpu)
223{
224 /*
225 * Initialize the APIC base MSR. The APIC enable-bit is set upon power-up or reset[1].
226 *
227 * A Reset (in xAPIC and x2APIC mode) brings up the local APIC in xAPIC mode.
228 * An INIT IPI does -not- cause a transition between xAPIC and x2APIC mode[2].
229 *
230 * [1] See AMD spec. 14.1.3 "Processor Initialization State"
231 * [2] See Intel spec. 10.12.5.1 "x2APIC States".
232 */
233 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
234
235 /* Construct. */
236 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
237 PAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
238 uint64_t uApicBaseMsr = MSR_IA32_APICBASE_ADDR;;
239 if (pVCpu->idCpu == 0)
240 uApicBaseMsr |= MSR_IA32_APICBASE_BSP;
241
242 /* If the VM was configured with disabled mode, don't enable xAPIC mode. */
243 if (pApic->enmOriginalMode != APICMODE_DISABLED)
244 {
245 uApicBaseMsr |= MSR_IA32_APICBASE_EN;
246
247 /** @todo CPUID bits needs to be done on a per-VCPU basis! */
248 CPUMSetGuestCpuIdFeature(pVCpu->CTX_SUFF(pVM), CPUMCPUIDFEATURE_APIC);
249 LogRel(("APIC%u: Switched mode to xAPIC\n", pVCpu->idCpu));
250 }
251
252 /* Commit. */
253 ASMAtomicWriteU64(&pApicCpu->uApicBaseMsr, uApicBaseMsr);
254}
255
256
257/**
258 * Initializes per-VCPU APIC to the state following a power-up or hardware
259 * reset.
260 *
261 * @param pVCpu The cross context virtual CPU structure.
262 * @param fResetApicBaseMsr Whether to reset the APIC base MSR.
263 */
264VMMR3_INT_DECL(void) APICR3Reset(PVMCPU pVCpu, bool fResetApicBaseMsr)
265{
266 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
267
268 LogFlow(("APIC%u: APICR3Reset: fResetApicBaseMsr=%RTbool\n", pVCpu->idCpu, fResetApicBaseMsr));
269
270#ifdef VBOX_STRICT
271 /* Verify that the initial APIC ID reported via CPUID matches our VMCPU ID assumption. */
272 uint32_t uEax, uEbx, uEcx, uEdx;
273 uEax = uEbx = uEcx = uEdx = UINT32_MAX;
274 CPUMGetGuestCpuId(pVCpu, 1, 0, &uEax, &uEbx, &uEcx, &uEdx);
275 Assert(((uEbx >> 24) & 0xff) == pVCpu->idCpu);
276#endif
277
278 /*
279 * The state following a power-up or reset is a superset of the INIT state.
280 * See Intel spec. 10.4.7.3 "Local APIC State After an INIT Reset ('Wait-for-SIPI' State)"
281 */
282 apicR3InitIpi(pVCpu);
283
284 /*
285 * The APIC version register is read-only, so just initialize it here.
286 * It is not clear from the specs, where exactly it is initialized.
287 * The version determines the number of LVT entries and size of the APIC ID (8 bits for P4).
288 */
289 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
290#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
291 pXApicPage->version.u.u8MaxLvtEntry = XAPIC_MAX_LVT_ENTRIES_P4 - 1;
292 pXApicPage->version.u.u8Version = XAPIC_HARDWARE_VERSION_P4;
293 AssertCompile(sizeof(pXApicPage->id.u8ApicId) >= XAPIC_APIC_ID_BIT_COUNT_P4 / 8);
294#else
295# error "Implement Pentium and P6 family APIC architectures"
296#endif
297
298 /** @todo It isn't clear in the spec. where exactly the default base address
299 * is (re)initialized, atm we do it here in Reset. */
300 if (fResetApicBaseMsr)
301 apicR3ResetBaseMsr(pVCpu);
302
303 /*
304 * Initialize the APIC ID register to xAPIC format.
305 */
306 ASMMemZero32(&pXApicPage->id, sizeof(pXApicPage->id));
307 pXApicPage->id.u8ApicId = pVCpu->idCpu;
308}
309
310
311/**
312 * Receives an INIT IPI.
313 *
314 * @param pVCpu The cross context virtual CPU structure.
315 */
316VMMR3_INT_DECL(void) APICR3InitIpi(PVMCPU pVCpu)
317{
318 VMCPU_ASSERT_EMT(pVCpu);
319 LogFlow(("APIC%u: APICR3InitIpi\n", pVCpu->idCpu));
320 apicR3InitIpi(pVCpu);
321}
322
323
324/**
325 * Helper for dumping an APIC 256-bit sparse register.
326 *
327 * @param pApicReg The APIC 256-bit spare register.
328 * @param pHlp The debug output helper.
329 */
330static void apicR3DbgInfo256BitReg(volatile const XAPIC256BITREG *pApicReg, PCDBGFINFOHLP pHlp)
331{
332 ssize_t const cFragments = RT_ELEMENTS(pApicReg->u);
333 unsigned const cBitsPerFragment = sizeof(pApicReg->u[0].u32Reg) * 8;
334 XAPIC256BITREG ApicReg;
335 RT_ZERO(ApicReg);
336
337 pHlp->pfnPrintf(pHlp, " ");
338 for (ssize_t i = cFragments - 1; i >= 0; i--)
339 {
340 uint32_t const uFragment = pApicReg->u[i].u32Reg;
341 ApicReg.u[i].u32Reg = uFragment;
342 pHlp->pfnPrintf(pHlp, "%08x", uFragment);
343 }
344 pHlp->pfnPrintf(pHlp, "\n");
345
346 uint32_t cPending = 0;
347 pHlp->pfnPrintf(pHlp, " Pending:");
348 for (ssize_t i = cFragments - 1; i >= 0; i--)
349 {
350 uint32_t uFragment = ApicReg.u[i].u32Reg;
351 if (uFragment)
352 {
353 do
354 {
355 unsigned idxSetBit = ASMBitLastSetU32(uFragment);
356 --idxSetBit;
357 ASMBitClear(&uFragment, idxSetBit);
358
359 idxSetBit += (i * cBitsPerFragment);
360 pHlp->pfnPrintf(pHlp, " %#02x", idxSetBit);
361 ++cPending;
362 } while (uFragment);
363 }
364 }
365 if (!cPending)
366 pHlp->pfnPrintf(pHlp, " None");
367 pHlp->pfnPrintf(pHlp, "\n");
368}
369
370
371/**
372 * Helper for dumping an APIC pending-interrupt bitmap.
373 *
374 * @param pApicPib The pending-interrupt bitmap.
375 * @param pHlp The debug output helper.
376 */
377static void apicR3DbgInfoPib(PCAPICPIB pApicPib, PCDBGFINFOHLP pHlp)
378{
379 /* Copy the pending-interrupt bitmap as an APIC 256-bit sparse register. */
380 XAPIC256BITREG ApicReg;
381 RT_ZERO(ApicReg);
382 ssize_t const cFragmentsDst = RT_ELEMENTS(ApicReg.u);
383 ssize_t const cFragmentsSrc = RT_ELEMENTS(pApicPib->aVectorBitmap);
384 AssertCompile(RT_ELEMENTS(ApicReg.u) == 2 * RT_ELEMENTS(pApicPib->aVectorBitmap));
385 for (ssize_t idxPib = cFragmentsSrc - 1, idxReg = cFragmentsDst - 1; idxPib >= 0; idxPib--, idxReg -= 2)
386 {
387 uint64_t const uFragment = pApicPib->aVectorBitmap[idxPib];
388 uint32_t const uFragmentLo = RT_LO_U32(uFragment);
389 uint32_t const uFragmentHi = RT_HI_U32(uFragment);
390 ApicReg.u[idxReg].u32Reg = uFragmentHi;
391 ApicReg.u[idxReg - 1].u32Reg = uFragmentLo;
392 }
393
394 /* Dump it. */
395 apicR3DbgInfo256BitReg(&ApicReg, pHlp);
396}
397
398
399/**
400 * Dumps basic APIC state.
401 *
402 * @param pVCpu The cross context virtual CPU structure.
403 * @param pHlp The debug output helper.
404 */
405static void apicR3DbgInfoBasic(PVMCPU pVCpu, PCDBGFINFOHLP pHlp)
406{
407 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
408 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
409 PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
410
411 uint64_t const uBaseMsr = pApicCpu->uApicBaseMsr;
412 APICMODE const enmMode = apicGetMode(uBaseMsr);
413 bool const fX2ApicMode = XAPIC_IN_X2APIC_MODE(pVCpu);
414
415 pHlp->pfnPrintf(pHlp, "VCPU[%u] APIC:\n", pVCpu->idCpu);
416 pHlp->pfnPrintf(pHlp, " APIC Base MSR = %#RX64 (Addr=%#RX64)\n", uBaseMsr,
417 MSR_IA32_APICBASE_GET_ADDR(uBaseMsr));
418 pHlp->pfnPrintf(pHlp, " Mode = %#x (%s)\n", enmMode, apicGetModeName(enmMode));
419 if (fX2ApicMode)
420 {
421 pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pX2ApicPage->id.u32ApicId,
422 pX2ApicPage->id.u32ApicId);
423 }
424 else
425 pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pXApicPage->id.u8ApicId, pXApicPage->id.u8ApicId);
426 pHlp->pfnPrintf(pHlp, " Version = %#x\n", pXApicPage->version.all.u32Version);
427 pHlp->pfnPrintf(pHlp, " APIC Version = %#x\n", pXApicPage->version.u.u8Version);
428 pHlp->pfnPrintf(pHlp, " Max LVT entry index (0..N) = %u\n", pXApicPage->version.u.u8MaxLvtEntry);
429 pHlp->pfnPrintf(pHlp, " EOI Broadcast supression = %RTbool\n", pXApicPage->version.u.fEoiBroadcastSupression);
430 if (!fX2ApicMode)
431 pHlp->pfnPrintf(pHlp, " APR = %u (%#x)\n", pXApicPage->apr.u8Apr, pXApicPage->apr.u8Apr);
432 pHlp->pfnPrintf(pHlp, " TPR = %u (%#x)\n", pXApicPage->tpr.u8Tpr, pXApicPage->tpr.u8Tpr);
433 pHlp->pfnPrintf(pHlp, " Task-priority class = %#x\n", XAPIC_TPR_GET_TP(pXApicPage->tpr.u8Tpr));
434 pHlp->pfnPrintf(pHlp, " Task-priority subclass = %#x\n", XAPIC_TPR_GET_TP_SUBCLASS(pXApicPage->tpr.u8Tpr));
435 pHlp->pfnPrintf(pHlp, " PPR = %u (%#x)\n", pXApicPage->ppr.u8Ppr, pXApicPage->ppr.u8Ppr);
436 pHlp->pfnPrintf(pHlp, " Processor-priority class = %#x\n", XAPIC_PPR_GET_PP(pXApicPage->ppr.u8Ppr));
437 pHlp->pfnPrintf(pHlp, " Processor-priority subclass = %#x\n", XAPIC_PPR_GET_PP_SUBCLASS(pXApicPage->ppr.u8Ppr));
438 if (!fX2ApicMode)
439 pHlp->pfnPrintf(pHlp, " RRD = %u (%#x)\n", pXApicPage->rrd.u32Rrd, pXApicPage->rrd.u32Rrd);
440 pHlp->pfnPrintf(pHlp, " LDR = %#x\n", pXApicPage->ldr.all.u32Ldr);
441 pHlp->pfnPrintf(pHlp, " Logical APIC ID = %#x\n", fX2ApicMode ? pX2ApicPage->ldr.u32LogicalApicId
442 : pXApicPage->ldr.u.u8LogicalApicId);
443 if (!fX2ApicMode)
444 {
445 pHlp->pfnPrintf(pHlp, " DFR = %#x\n", pXApicPage->dfr.all.u32Dfr);
446 pHlp->pfnPrintf(pHlp, " Model = %#x (%s)\n", pXApicPage->dfr.u.u4Model,
447 apicGetDestFormatName((XAPICDESTFORMAT)pXApicPage->dfr.u.u4Model));
448 }
449 pHlp->pfnPrintf(pHlp, " SVR\n");
450 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->svr.u.u8SpuriousVector,
451 pXApicPage->svr.u.u8SpuriousVector);
452 pHlp->pfnPrintf(pHlp, " Software Enabled = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fApicSoftwareEnable));
453 pHlp->pfnPrintf(pHlp, " Supress EOI broadcast = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fSupressEoiBroadcast));
454 pHlp->pfnPrintf(pHlp, " ISR\n");
455 apicR3DbgInfo256BitReg(&pXApicPage->isr, pHlp);
456 pHlp->pfnPrintf(pHlp, " TMR\n");
457 apicR3DbgInfo256BitReg(&pXApicPage->tmr, pHlp);
458 pHlp->pfnPrintf(pHlp, " IRR\n");
459 apicR3DbgInfo256BitReg(&pXApicPage->irr, pHlp);
460 pHlp->pfnPrintf(pHlp, " PIB\n");
461 apicR3DbgInfoPib((PCAPICPIB)pApicCpu->pvApicPibR3, pHlp);
462 pHlp->pfnPrintf(pHlp, " Level PIB\n");
463 apicR3DbgInfoPib(&pApicCpu->ApicPibLevel, pHlp);
464 pHlp->pfnPrintf(pHlp, " ESR Internal = %#x\n", pApicCpu->uEsrInternal);
465 pHlp->pfnPrintf(pHlp, " ESR = %#x\n", pXApicPage->esr.all.u32Errors);
466 pHlp->pfnPrintf(pHlp, " Redirectable IPI = %RTbool\n", pXApicPage->esr.u.fRedirectableIpi);
467 pHlp->pfnPrintf(pHlp, " Send Illegal Vector = %RTbool\n", pXApicPage->esr.u.fSendIllegalVector);
468 pHlp->pfnPrintf(pHlp, " Recv Illegal Vector = %RTbool\n", pXApicPage->esr.u.fRcvdIllegalVector);
469 pHlp->pfnPrintf(pHlp, " Illegal Register Address = %RTbool\n", pXApicPage->esr.u.fIllegalRegAddr);
470 pHlp->pfnPrintf(pHlp, " ICR Low = %#x\n", pXApicPage->icr_lo.all.u32IcrLo);
471 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->icr_lo.u.u8Vector,
472 pXApicPage->icr_lo.u.u8Vector);
473 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u3DeliveryMode,
474 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->icr_lo.u.u3DeliveryMode));
475 pHlp->pfnPrintf(pHlp, " Destination Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u1DestMode,
476 apicGetDestModeName((XAPICDESTMODE)pXApicPage->icr_lo.u.u1DestMode));
477 if (!fX2ApicMode)
478 pHlp->pfnPrintf(pHlp, " Delivery Status = %u\n", pXApicPage->icr_lo.u.u1DeliveryStatus);
479 pHlp->pfnPrintf(pHlp, " Level = %u\n", pXApicPage->icr_lo.u.u1Level);
480 pHlp->pfnPrintf(pHlp, " Trigger Mode = %u (%s)\n", pXApicPage->icr_lo.u.u1TriggerMode,
481 apicGetTriggerModeName((XAPICTRIGGERMODE)pXApicPage->icr_lo.u.u1TriggerMode));
482 pHlp->pfnPrintf(pHlp, " Destination shorthand = %#x (%s)\n", pXApicPage->icr_lo.u.u2DestShorthand,
483 apicGetDestShorthandName((XAPICDESTSHORTHAND)pXApicPage->icr_lo.u.u2DestShorthand));
484 pHlp->pfnPrintf(pHlp, " ICR High = %#x\n", pXApicPage->icr_hi.all.u32IcrHi);
485 pHlp->pfnPrintf(pHlp, " Destination field/mask = %#x\n", fX2ApicMode ? pX2ApicPage->icr_hi.u32IcrHi
486 : pXApicPage->icr_hi.u.u8Dest);
487}
488
489
490/**
491 * Helper for dumping the LVT timer.
492 *
493 * @param pVCpu The cross context virtual CPU structure.
494 * @param pHlp The debug output helper.
495 */
496static void apicR3DbgInfoLvtTimer(PVMCPU pVCpu, PCDBGFINFOHLP pHlp)
497{
498 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
499 uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
500 pHlp->pfnPrintf(pHlp, "LVT Timer = %#RX32\n", uLvtTimer);
501 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_timer.u.u8Vector, pXApicPage->lvt_timer.u.u8Vector);
502 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_timer.u.u1DeliveryStatus);
503 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtTimer));
504 pHlp->pfnPrintf(pHlp, " Timer Mode = %#x (%s)\n", pXApicPage->lvt_timer.u.u2TimerMode,
505 apicGetTimerModeName((XAPICTIMERMODE)pXApicPage->lvt_timer.u.u2TimerMode));
506 pHlp->pfnPrintf(pHlp, "\n");
507}
508
509
510/**
511 * Dumps APIC Local Vector Table (LVT) state.
512 *
513 * @param pVCpu The cross context virtual CPU structure.
514 * @param pHlp The debug output helper.
515 */
516static void apicR3DbgInfoLvt(PVMCPU pVCpu, PCDBGFINFOHLP pHlp)
517{
518 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
519
520 apicR3DbgInfoLvtTimer(pVCpu, pHlp);
521
522#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
523 uint32_t const uLvtThermal = pXApicPage->lvt_thermal.all.u32LvtThermal;
524 pHlp->pfnPrintf(pHlp, "LVT Thermal = %#RX32)\n", uLvtThermal);
525 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_thermal.u.u8Vector,
526 pXApicPage->lvt_thermal.u.u8Vector);
527 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->lvt_thermal.u.u3DeliveryMode,
528 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->lvt_thermal.u.u3DeliveryMode));
529 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_thermal.u.u1DeliveryStatus);
530 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtThermal));
531 pHlp->pfnPrintf(pHlp, "\n");
532#endif
533
534 uint32_t const uLvtPerf = pXApicPage->lvt_perf.all.u32LvtPerf;
535 pHlp->pfnPrintf(pHlp, "LVT Perf = %#RX32\n", uLvtPerf);
536 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_perf.u.u8Vector, pXApicPage->lvt_perf.u.u8Vector);
537 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->lvt_perf.u.u3DeliveryMode,
538 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->lvt_perf.u.u3DeliveryMode));
539 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_perf.u.u1DeliveryStatus);
540 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtPerf));
541 pHlp->pfnPrintf(pHlp, "\n");
542
543 uint32_t const uLvtLint0 = pXApicPage->lvt_lint0.all.u32LvtLint0;
544 pHlp->pfnPrintf(pHlp, "LVT LINT0 = %#RX32\n", uLvtLint0);
545 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_lint0.u.u8Vector, pXApicPage->lvt_lint0.u.u8Vector);
546 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->lvt_lint0.u.u3DeliveryMode,
547 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->lvt_lint0.u.u3DeliveryMode));
548 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_lint0.u.u1DeliveryStatus);
549 pHlp->pfnPrintf(pHlp, " Pin polarity = %u\n", pXApicPage->lvt_lint0.u.u1IntrPolarity);
550 pHlp->pfnPrintf(pHlp, " Remote IRR = %u\n", pXApicPage->lvt_lint0.u.u1RemoteIrr);
551 pHlp->pfnPrintf(pHlp, " Trigger Mode = %u (%s)\n", pXApicPage->lvt_lint0.u.u1TriggerMode,
552 apicGetTriggerModeName((XAPICTRIGGERMODE)pXApicPage->lvt_lint0.u.u1TriggerMode));
553 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtLint0));
554 pHlp->pfnPrintf(pHlp, "\n");
555
556 uint32_t const uLvtLint1 = pXApicPage->lvt_lint1.all.u32LvtLint1;
557 pHlp->pfnPrintf(pHlp, "LVT LINT1 = %#RX32\n", uLvtLint1);
558 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_lint1.u.u8Vector, pXApicPage->lvt_lint1.u.u8Vector);
559 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->lvt_lint1.u.u3DeliveryMode,
560 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->lvt_lint1.u.u3DeliveryMode));
561 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_lint1.u.u1DeliveryStatus);
562 pHlp->pfnPrintf(pHlp, " Pin polarity = %u\n", pXApicPage->lvt_lint1.u.u1IntrPolarity);
563 pHlp->pfnPrintf(pHlp, " Remote IRR = %u\n", pXApicPage->lvt_lint1.u.u1RemoteIrr);
564 pHlp->pfnPrintf(pHlp, " Trigger Mode = %u (%s)\n", pXApicPage->lvt_lint1.u.u1TriggerMode,
565 apicGetTriggerModeName((XAPICTRIGGERMODE)pXApicPage->lvt_lint1.u.u1TriggerMode));
566 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtLint1));
567 pHlp->pfnPrintf(pHlp, "\n");
568
569 uint32_t const uLvtError = pXApicPage->lvt_error.all.u32LvtError;
570 pHlp->pfnPrintf(pHlp, "LVT Error = %#RX32\n", uLvtError);
571 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_error.u.u8Vector, pXApicPage->lvt_error.u.u8Vector);
572 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_error.u.u1DeliveryStatus);
573 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtError));
574 pHlp->pfnPrintf(pHlp, "\n");
575}
576
577
578/**
579 * Dumps APIC Timer state.
580 *
581 * @param pVCpu The cross context virtual CPU structure.
582 * @param pHlp The debug output helper.
583 */
584static void apicR3DbgInfoTimer(PVMCPU pVCpu, PCDBGFINFOHLP pHlp)
585{
586 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
587 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
588
589 pHlp->pfnPrintf(pHlp, "Local APIC timer:\n");
590 pHlp->pfnPrintf(pHlp, " ICR = %#RX32\n", pXApicPage->timer_icr.u32InitialCount);
591 pHlp->pfnPrintf(pHlp, " CCR = %#RX32\n", pXApicPage->timer_ccr.u32CurrentCount);
592 pHlp->pfnPrintf(pHlp, " DCR = %#RX32\n", pXApicPage->timer_dcr.all.u32DivideValue);
593 pHlp->pfnPrintf(pHlp, " Timer shift = %#x\n", apicGetTimerShift(pXApicPage));
594 pHlp->pfnPrintf(pHlp, " Timer initial TS = %#RU64\n", pApicCpu->u64TimerInitial);
595 pHlp->pfnPrintf(pHlp, "\n");
596
597 apicR3DbgInfoLvtTimer(pVCpu, pHlp);
598}
599
600
601/**
602 * @callback_method_impl{FNDBGFHANDLERDEV,
603 * Dumps the APIC state according to given argument for debugging purposes.}
604 */
605static DECLCALLBACK(void) apicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
606{
607 PVM pVM = PDMDevHlpGetVM(pDevIns);
608 PVMCPU pVCpu = VMMGetCpu(pVM);
609 Assert(pVCpu);
610
611 if (pszArgs == NULL || !*pszArgs || !strcmp(pszArgs, "basic"))
612 apicR3DbgInfoBasic(pVCpu, pHlp);
613 else if (!strcmp(pszArgs, "lvt"))
614 apicR3DbgInfoLvt(pVCpu, pHlp);
615 else if (!strcmp(pszArgs, "timer"))
616 apicR3DbgInfoTimer(pVCpu, pHlp);
617 else
618 pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'lvt', 'timer'\n");
619}
620
621
622/**
623 * Converts legacy PDMAPICMODE to the new APICMODE enum.
624 *
625 * @returns The new APIC mode.
626 * @param enmLegacyMode The legacy mode to convert.
627 */
628static APICMODE apicR3ConvertFromLegacyApicMode(PDMAPICMODE enmLegacyMode)
629{
630 switch (enmLegacyMode)
631 {
632 case PDMAPICMODE_NONE: return APICMODE_DISABLED;
633 case PDMAPICMODE_APIC: return APICMODE_XAPIC;
634 case PDMAPICMODE_X2APIC: return APICMODE_X2APIC;
635 case PDMAPICMODE_INVALID: return APICMODE_INVALID;
636 default: break;
637 }
638 return (APICMODE)enmLegacyMode;
639}
640
641
642/**
643 * Converts the new APICMODE enum to the legacy PDMAPICMODE enum.
644 *
645 * @returns The legacy APIC mode.
646 * @param enmMode The APIC mode to convert.
647 */
648static PDMAPICMODE apicR3ConvertToLegacyApicMode(APICMODE enmMode)
649{
650 switch (enmMode)
651 {
652 case APICMODE_DISABLED: return PDMAPICMODE_NONE;
653 case APICMODE_XAPIC: return PDMAPICMODE_APIC;
654 case APICMODE_X2APIC: return PDMAPICMODE_X2APIC;
655 case APICMODE_INVALID: return PDMAPICMODE_INVALID;
656 default: break;
657 }
658 return (PDMAPICMODE)enmMode;
659}
660
661
662#ifdef APIC_FUZZY_SSM_COMPAT_TEST
663/**
664 * Reads a 32-bit register at a specified offset.
665 *
666 * @returns The value at the specified offset.
667 * @param pXApicPage The xAPIC page.
668 * @param offReg The offset of the register being read.
669 *
670 * @remarks Duplicate of apicReadRaw32()!
671 */
672static uint32_t apicR3ReadRawR32(PCXAPICPAGE pXApicPage, uint16_t offReg)
673{
674 Assert(offReg < sizeof(*pXApicPage) - sizeof(uint32_t));
675 uint8_t const *pbXApic = (const uint8_t *)pXApicPage;
676 uint32_t const uValue = *(const uint32_t *)(pbXApic + offReg);
677 return uValue;
678}
679
680
681/**
682 * Helper for dumping per-VCPU APIC state to the release logger.
683 *
684 * This is primarily concerned about the APIC state relevant for saved-states.
685 *
686 * @param pVCpu The cross context virtual CPU structure.
687 * @param pszPrefix A caller supplied prefix before dumping the state.
688 * @param uVersion Data layout version.
689 */
690static void apicR3DumpState(PVMCPU pVCpu, const char *pszPrefix, uint32_t uVersion)
691{
692 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
693
694 LogRel(("APIC%u: %s (version %u):\n", pVCpu->idCpu, pszPrefix, uVersion));
695
696 switch (uVersion)
697 {
698 case APIC_SAVED_STATE_VERSION:
699 {
700 /* The auxiliary state. */
701 LogRel(("APIC%u: uApicBaseMsr = %#RX64\n", pVCpu->idCpu, pApicCpu->uApicBaseMsr));
702 LogRel(("APIC%u: uEsrInternal = %#RX64\n", pVCpu->idCpu, pApicCpu->uEsrInternal));
703
704 /* The timer. */
705 LogRel(("APIC%u: u64TimerInitial = %#RU64\n", pVCpu->idCpu, pApicCpu->u64TimerInitial));
706 LogRel(("APIC%u: uHintedTimerInitialCount = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerInitialCount));
707 LogRel(("APIC%u: uHintedTimerShift = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerShift));
708
709 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
710 LogRel(("APIC%u: uTimerICR = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_icr.u32InitialCount));
711 LogRel(("APIC%u: uTimerCCR = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_ccr.u32CurrentCount));
712
713 /* The PIBs. */
714 LogRel(("APIC%u: Edge PIB : %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), pApicCpu->pvApicPibR3));
715 LogRel(("APIC%u: Level PIB: %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), &pApicCpu->ApicPibLevel));
716
717 /* The APIC page. */
718 LogRel(("APIC%u: APIC page: %.*Rhxs\n", pVCpu->idCpu, sizeof(XAPICPAGE), pApicCpu->pvApicPageR3));
719 break;
720 }
721
722 case APIC_SAVED_STATE_VERSION_VBOX_50:
723 case APIC_SAVED_STATE_VERSION_VBOX_30:
724 case APIC_SAVED_STATE_VERSION_ANCIENT:
725 {
726 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
727 LogRel(("APIC%u: uApicBaseMsr = %#RX32\n", pVCpu->idCpu, RT_LO_U32(pApicCpu->uApicBaseMsr)));
728 LogRel(("APIC%u: uId = %#RX32\n", pVCpu->idCpu, pXApicPage->id.u8ApicId));
729 LogRel(("APIC%u: uPhysId = N/A\n", pVCpu->idCpu));
730 LogRel(("APIC%u: uArbId = N/A\n", pVCpu->idCpu));
731 LogRel(("APIC%u: uTpr = %#RX32\n", pVCpu->idCpu, pXApicPage->tpr.u8Tpr));
732 LogRel(("APIC%u: uSvr = %#RX32\n", pVCpu->idCpu, pXApicPage->svr.all.u32Svr));
733 LogRel(("APIC%u: uLdr = %#x\n", pVCpu->idCpu, pXApicPage->ldr.all.u32Ldr));
734 LogRel(("APIC%u: uDfr = %#x\n", pVCpu->idCpu, pXApicPage->dfr.all.u32Dfr));
735
736 for (size_t i = 0; i < 8; i++)
737 {
738 LogRel(("APIC%u: Isr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->isr.u[i].u32Reg));
739 LogRel(("APIC%u: Tmr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->tmr.u[i].u32Reg));
740 LogRel(("APIC%u: Irr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->irr.u[i].u32Reg));
741 }
742
743 for (size_t i = 0; i < XAPIC_MAX_LVT_ENTRIES_P4; i++)
744 {
745 uint16_t const offReg = XAPIC_OFF_LVT_START + (i << 4);
746 LogRel(("APIC%u: Lvt[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, apicR3ReadRawR32(pXApicPage, offReg)));
747 }
748
749 LogRel(("APIC%u: uEsr = %#RX32\n", pVCpu->idCpu, pXApicPage->esr.all.u32Errors));
750 LogRel(("APIC%u: uIcr_Lo = %#RX32\n", pVCpu->idCpu, pXApicPage->icr_lo.all.u32IcrLo));
751 LogRel(("APIC%u: uIcr_Hi = %#RX32\n", pVCpu->idCpu, pXApicPage->icr_hi.all.u32IcrHi));
752 LogRel(("APIC%u: uTimerDcr = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_dcr.all.u32DivideValue));
753 LogRel(("APIC%u: uCountShift = %#RX32\n", pVCpu->idCpu, apicGetTimerShift(pXApicPage)));
754 LogRel(("APIC%u: uInitialCount = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_icr.u32InitialCount));
755 LogRel(("APIC%u: u64InitialCountLoadTime = %#RX64\n", pVCpu->idCpu, pApicCpu->u64TimerInitial));
756 LogRel(("APIC%u: u64NextTime / TimerCCR = %#RX64\n", pVCpu->idCpu, pXApicPage->timer_ccr.u32CurrentCount));
757 break;
758 }
759
760 default:
761 {
762 LogRel(("APIC: apicR3DumpState: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
763 break;
764 }
765 }
766}
767#endif /* APIC_FUZZY_SSM_COMPAT_TEST */
768
769
770/**
771 * Worker for saving per-VM APIC data.
772 *
773 * @returns VBox status code.
774 * @param pVM The cross context VM structure.
775 * @param pSSM The SSM handle.
776 */
777static int apicR3SaveVMData(PVM pVM, PSSMHANDLE pSSM)
778{
779 PAPIC pApic = VM_TO_APIC(pVM);
780 SSMR3PutU32(pSSM, pVM->cCpus);
781 SSMR3PutBool(pSSM, pApic->fIoApicPresent);
782 return SSMR3PutU32(pSSM, apicR3ConvertToLegacyApicMode(pApic->enmOriginalMode));
783}
784
785
786/**
787 * Worker for loading per-VM APIC data.
788 *
789 * @returns VBox status code.
790 * @param pVM The cross context VM structure.
791 * @param pSSM The SSM handle.
792 */
793static int apicR3LoadVMData(PVM pVM, PSSMHANDLE pSSM)
794{
795 PAPIC pApic = VM_TO_APIC(pVM);
796
797 /* Load and verify number of CPUs. */
798 uint32_t cCpus;
799 int rc = SSMR3GetU32(pSSM, &cCpus);
800 AssertRCReturn(rc, rc);
801 if (cCpus != pVM->cCpus)
802 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%u config=%u"), cCpus, pVM->cCpus);
803
804 /* Load and verify I/O APIC presence. */
805 bool fIoApicPresent;
806 rc = SSMR3GetBool(pSSM, &fIoApicPresent);
807 AssertRCReturn(rc, rc);
808 if (fIoApicPresent != pApic->fIoApicPresent)
809 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApicPresent: saved=%RTbool config=%RTbool"),
810 fIoApicPresent, pApic->fIoApicPresent);
811
812 /* Load and verify configured APIC mode. */
813 uint32_t uLegacyApicMode;
814 rc = SSMR3GetU32(pSSM, &uLegacyApicMode);
815 AssertRCReturn(rc, rc);
816 APICMODE const enmApicMode = apicR3ConvertFromLegacyApicMode((PDMAPICMODE)uLegacyApicMode);
817 if (enmApicMode != pApic->enmOriginalMode)
818 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicMode: saved=%u (%u) config=%u (%u)"),
819 uLegacyApicMode, enmApicMode, apicR3ConvertToLegacyApicMode(pApic->enmOriginalMode),
820 pApic->enmOriginalMode);
821 return VINF_SUCCESS;
822}
823
824
825/**
826 * Worker for loading per-VCPU APIC data for legacy (old) saved-states.
827 *
828 * @returns VBox status code.
829 * @param pVM The cross context VM structure.
830 * @param pVCpu The cross context virtual CPU structure.
831 * @param pSSM The SSM handle.
832 * @param uVersion Data layout version.
833 */
834static int apicR3LoadLegacyVCpuData(PVM pVM, PVMCPU pVCpu, PSSMHANDLE pSSM, uint32_t uVersion)
835{
836 AssertReturn(uVersion <= APIC_SAVED_STATE_VERSION_VBOX_50, VERR_NOT_SUPPORTED);
837
838 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
839 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
840
841 uint32_t uApicBaseLo;
842 int rc = SSMR3GetU32(pSSM, &uApicBaseLo);
843 AssertRCReturn(rc, rc);
844 pApicCpu->uApicBaseMsr = uApicBaseLo;
845 Log2(("APIC%u: apicR3LoadLegacyVCpuData: uApicBaseMsr=%#RX64\n", pVCpu->idCpu, pApicCpu->uApicBaseMsr));
846
847 switch (uVersion)
848 {
849 case APIC_SAVED_STATE_VERSION_VBOX_50:
850 case APIC_SAVED_STATE_VERSION_VBOX_30:
851 {
852 uint32_t uApicId, uPhysApicId, uArbId;
853 SSMR3GetU32(pSSM, &uApicId); pXApicPage->id.u8ApicId = uApicId;
854 SSMR3GetU32(pSSM, &uPhysApicId); NOREF(uPhysApicId); /* PhysId == pVCpu->idCpu */
855 SSMR3GetU32(pSSM, &uArbId); NOREF(uArbId); /* ArbID is & was unused. */
856 break;
857 }
858
859 case APIC_SAVED_STATE_VERSION_ANCIENT:
860 {
861 uint8_t uPhysApicId;
862 SSMR3GetU8(pSSM, &pXApicPage->id.u8ApicId);
863 SSMR3GetU8(pSSM, &uPhysApicId); NOREF(uPhysApicId); /* PhysId == pVCpu->idCpu */
864 break;
865 }
866
867 default:
868 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
869 }
870
871 uint32_t u32Tpr;
872 SSMR3GetU32(pSSM, &u32Tpr);
873 pXApicPage->tpr.u8Tpr = u32Tpr & XAPIC_TPR_VALID;
874
875 SSMR3GetU32(pSSM, &pXApicPage->svr.all.u32Svr);
876 SSMR3GetU8(pSSM, &pXApicPage->ldr.u.u8LogicalApicId);
877
878 uint8_t uDfr;
879 SSMR3GetU8(pSSM, &uDfr);
880 pXApicPage->dfr.u.u4Model = uDfr >> 4;
881
882 AssertCompile(RT_ELEMENTS(pXApicPage->isr.u) == 8);
883 AssertCompile(RT_ELEMENTS(pXApicPage->tmr.u) == 8);
884 AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 8);
885 for (size_t i = 0; i < 8; i++)
886 {
887 SSMR3GetU32(pSSM, &pXApicPage->isr.u[i].u32Reg);
888 SSMR3GetU32(pSSM, &pXApicPage->tmr.u[i].u32Reg);
889 SSMR3GetU32(pSSM, &pXApicPage->irr.u[i].u32Reg);
890 }
891
892 SSMR3GetU32(pSSM, &pXApicPage->lvt_timer.all.u32LvtTimer);
893 SSMR3GetU32(pSSM, &pXApicPage->lvt_thermal.all.u32LvtThermal);
894 SSMR3GetU32(pSSM, &pXApicPage->lvt_perf.all.u32LvtPerf);
895 SSMR3GetU32(pSSM, &pXApicPage->lvt_lint0.all.u32LvtLint0);
896 SSMR3GetU32(pSSM, &pXApicPage->lvt_lint1.all.u32LvtLint1);
897 SSMR3GetU32(pSSM, &pXApicPage->lvt_error.all.u32LvtError);
898
899 SSMR3GetU32(pSSM, &pXApicPage->esr.all.u32Errors);
900 SSMR3GetU32(pSSM, &pXApicPage->icr_lo.all.u32IcrLo);
901 SSMR3GetU32(pSSM, &pXApicPage->icr_hi.all.u32IcrHi);
902
903 uint32_t u32TimerShift;
904 SSMR3GetU32(pSSM, &pXApicPage->timer_dcr.all.u32DivideValue);
905 SSMR3GetU32(pSSM, &u32TimerShift);
906 /*
907 * Old implementation may have left the timer shift uninitialized until
908 * the timer configuration register was written. Unfortunately zero is
909 * also a valid timer shift value, so we're just going to ignore it
910 * completely. The shift count can always be derived from the DCR.
911 * See @bugref{8245#c98}.
912 */
913 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
914
915 SSMR3GetU32(pSSM, &pXApicPage->timer_icr.u32InitialCount);
916 SSMR3GetU64(pSSM, &pApicCpu->u64TimerInitial);
917 uint64_t uNextTS;
918 rc = SSMR3GetU64(pSSM, &uNextTS); AssertRCReturn(rc, rc);
919 if (uNextTS >= pApicCpu->u64TimerInitial + ((pXApicPage->timer_icr.u32InitialCount + 1) << uTimerShift))
920 pXApicPage->timer_ccr.u32CurrentCount = pXApicPage->timer_icr.u32InitialCount;
921
922 rc = TMR3TimerLoad(pApicCpu->pTimerR3, pSSM);
923 AssertRCReturn(rc, rc);
924 Assert(pApicCpu->uHintedTimerInitialCount == 0);
925 Assert(pApicCpu->uHintedTimerShift == 0);
926 if (TMTimerIsActive(pApicCpu->pTimerR3))
927 {
928 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
929 apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
930 }
931
932 return rc;
933}
934
935
936/**
937 * @copydoc FNSSMDEVLIVEEXEC
938 */
939static DECLCALLBACK(int) apicR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
940{
941 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
942 PVM pVM = PDMDevHlpGetVM(pApicDev->pDevInsR3);
943
944 LogFlow(("APIC: apicR3LiveExec: uPass=%u\n", uPass));
945
946 int rc = apicR3SaveVMData(pVM, pSSM);
947 AssertRCReturn(rc, rc);
948 return VINF_SSM_DONT_CALL_AGAIN;
949}
950
951
952/**
953 * @copydoc FNSSMDEVSAVEEXEC
954 */
955static DECLCALLBACK(int) apicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
956{
957 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
958 PVM pVM = PDMDevHlpGetVM(pDevIns);
959 PAPIC pApic = VM_TO_APIC(pVM);
960 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
961
962 LogFlow(("APIC: apicR3SaveExec\n"));
963
964 /* Save per-VM data. */
965 int rc = apicR3SaveVMData(pVM, pSSM);
966 AssertRCReturn(rc, rc);
967
968 /* Save per-VCPU data.*/
969 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
970 {
971 PVMCPU pVCpu = &pVM->aCpus[idCpu];
972 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
973
974 /* Update interrupts from the pending-interrupts bitmaps to the IRR. */
975 APICUpdatePendingInterrupts(pVCpu);
976
977 /* Save the auxiliary data. */
978 SSMR3PutU64(pSSM, pApicCpu->uApicBaseMsr);
979 SSMR3PutU32(pSSM, pApicCpu->uEsrInternal);
980
981 /* Save the APIC page. */
982 if (XAPIC_IN_X2APIC_MODE(pVCpu))
983 SSMR3PutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
984 else
985 SSMR3PutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
986
987 /* Save the timer. */
988 SSMR3PutU64(pSSM, pApicCpu->u64TimerInitial);
989 TMR3TimerSave(pApicCpu->pTimerR3, pSSM);
990
991#if defined(APIC_FUZZY_SSM_COMPAT_TEST) || defined(DEBUG_ramshankar)
992 apicR3DumpState(pVCpu, "Saved state", APIC_SAVED_STATE_VERSION);
993#endif
994 }
995
996#ifdef APIC_FUZZY_SSM_COMPAT_TEST
997 /* The state is fuzzy, don't even bother trying to load the guest. */
998 return VERR_INVALID_STATE;
999#else
1000 return rc;
1001#endif
1002}
1003
1004
1005/**
1006 * @copydoc FNSSMDEVLOADEXEC
1007 */
1008static DECLCALLBACK(int) apicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1009{
1010 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1011 PVM pVM = PDMDevHlpGetVM(pDevIns);
1012 PAPIC pApic = VM_TO_APIC(pVM);
1013
1014 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
1015 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
1016
1017 LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1018
1019 /* Weed out invalid versions. */
1020 if ( uVersion != APIC_SAVED_STATE_VERSION
1021 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_50
1022 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_30
1023 && uVersion != APIC_SAVED_STATE_VERSION_ANCIENT)
1024 {
1025 LogRel(("APIC: apicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1026 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1027 }
1028
1029 int rc = VINF_SUCCESS;
1030 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_30)
1031 {
1032 rc = apicR3LoadVMData(pVM, pSSM);
1033 AssertRCReturn(rc, rc);
1034
1035 if (uVersion == APIC_SAVED_STATE_VERSION)
1036 { /* Load any new additional per-VM data. */ }
1037 }
1038
1039 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1040 {
1041 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1042 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1043
1044 if (uVersion == APIC_SAVED_STATE_VERSION)
1045 {
1046 /* Load the auxiliary data. */
1047 SSMR3GetU64(pSSM, (uint64_t *)&pApicCpu->uApicBaseMsr);
1048 SSMR3GetU32(pSSM, &pApicCpu->uEsrInternal);
1049
1050 /* Load the APIC page. */
1051 if (XAPIC_IN_X2APIC_MODE(pVCpu))
1052 SSMR3GetStruct(pSSM, pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
1053 else
1054 SSMR3GetStruct(pSSM, pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
1055
1056 /* Load the timer. */
1057 rc = SSMR3GetU64(pSSM, &pApicCpu->u64TimerInitial); AssertRCReturn(rc, rc);
1058 rc = TMR3TimerLoad(pApicCpu->pTimerR3, pSSM); AssertRCReturn(rc, rc);
1059 Assert(pApicCpu->uHintedTimerShift == 0);
1060 Assert(pApicCpu->uHintedTimerInitialCount == 0);
1061 if (TMTimerIsActive(pApicCpu->pTimerR3))
1062 {
1063 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
1064 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1065 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
1066 apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
1067 }
1068 }
1069 else
1070 {
1071 rc = apicR3LoadLegacyVCpuData(pVM, pVCpu, pSSM, uVersion);
1072 AssertRCReturn(rc, rc);
1073 }
1074
1075#if defined(APIC_FUZZY_SSM_COMPAT_TEST) || defined(DEBUG_ramshankar)
1076 apicR3DumpState(pVCpu, "Loaded state", uVersion);
1077#endif
1078 }
1079
1080 return rc;
1081}
1082
1083
1084/**
1085 * The timer callback.
1086 *
1087 * @param pDevIns The device instance.
1088 * @param pTimer The timer handle.
1089 * @param pvUser Opaque pointer to the VMCPU.
1090 *
1091 * @thread Any.
1092 * @remarks Currently this function is invoked on the last EMT, see @c
1093 * idTimerCpu in tmR3TimerCallback(). However, the code does -not-
1094 * rely on this and is designed to work with being invoked on any
1095 * thread.
1096 */
1097static DECLCALLBACK(void) apicR3TimerCallback(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1098{
1099 PVMCPU pVCpu = (PVMCPU)pvUser;
1100 Assert(TMTimerIsLockOwner(pTimer));
1101 Assert(pVCpu);
1102 LogFlow(("APIC%u: apicR3TimerCallback\n", pVCpu->idCpu));
1103
1104 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1105 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1106 uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
1107 STAM_COUNTER_INC(&pApicCpu->StatTimerCallback);
1108 if (!XAPIC_LVT_IS_MASKED(uLvtTimer))
1109 {
1110 uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
1111 Log2(("APIC%u: apicR3TimerCallback: Raising timer interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
1112 APICPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE);
1113 }
1114
1115 XAPICTIMERMODE enmTimerMode = XAPIC_LVT_GET_TIMER_MODE(uLvtTimer);
1116 switch (enmTimerMode)
1117 {
1118 case XAPICTIMERMODE_PERIODIC:
1119 {
1120 /* The initial-count register determines if the periodic timer is re-armed. */
1121 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1122 pXApicPage->timer_ccr.u32CurrentCount = uInitialCount;
1123 if (uInitialCount)
1124 {
1125 Log2(("APIC%u: apicR3TimerCallback: Re-arming timer. uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
1126 APICStartTimer(pVCpu, uInitialCount);
1127 }
1128 break;
1129 }
1130
1131 case XAPICTIMERMODE_ONESHOT:
1132 {
1133 pXApicPage->timer_ccr.u32CurrentCount = 0;
1134 break;
1135 }
1136
1137 case XAPICTIMERMODE_TSC_DEADLINE:
1138 {
1139 /** @todo implement TSC deadline. */
1140 AssertMsgFailed(("APIC: TSC deadline mode unimplemented\n"));
1141 break;
1142 }
1143 }
1144}
1145
1146
1147/**
1148 * @interface_method_impl{PDMDEVREG,pfnReset}
1149 */
1150static DECLCALLBACK(void) apicR3Reset(PPDMDEVINS pDevIns)
1151{
1152 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1153 PVM pVM = PDMDevHlpGetVM(pDevIns);
1154 VM_ASSERT_EMT0(pVM);
1155 VM_ASSERT_IS_NOT_RUNNING(pVM);
1156
1157 LogFlow(("APIC: apicR3Reset\n"));
1158
1159 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1160 {
1161 PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
1162 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpuDest);
1163
1164 if (TMTimerIsActive(pApicCpu->pTimerR3))
1165 TMTimerStop(pApicCpu->pTimerR3);
1166
1167 APICR3Reset(pVCpuDest, true /* fResetApicBaseMsr */);
1168
1169 /* Clear the interrupt pending force flag. */
1170 APICClearInterruptFF(pVCpuDest, PDMAPICIRQ_HARDWARE);
1171 }
1172}
1173
1174
1175/**
1176 * @interface_method_impl{PDMDEVREG,pfnRelocate}
1177 */
1178static DECLCALLBACK(void) apicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1179{
1180 PVM pVM = PDMDevHlpGetVM(pDevIns);
1181 PAPIC pApic = VM_TO_APIC(pVM);
1182 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1183
1184 LogFlow(("APIC: apicR3Relocate: pVM=%p pDevIns=%p offDelta=%RGi\n", pVM, pDevIns, offDelta));
1185
1186 pApicDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1187 pApicDev->pApicHlpRC = pApicDev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
1188 pApicDev->pCritSectRC = pApicDev->pApicHlpR3->pfnGetRCCritSect(pDevIns);
1189
1190 pApic->pApicDevRC = PDMINS_2_DATA_RCPTR(pDevIns);
1191 pApic->pvApicPibRC += offDelta;
1192
1193 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1194 {
1195 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1196 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1197 pApicCpu->pTimerRC = TMTimerRCPtr(pApicCpu->pTimerR3);
1198
1199 pApicCpu->pvApicPageRC += offDelta;
1200 pApicCpu->pvApicPibRC += offDelta;
1201 Log2(("APIC%u: apicR3Relocate: APIC PIB at %RGv\n", pVCpu->idCpu, pApicCpu->pvApicPibRC));
1202 }
1203}
1204
1205
1206/**
1207 * Terminates the APIC state.
1208 *
1209 * @param pVM The cross context VM structure.
1210 */
1211static void apicR3TermState(PVM pVM)
1212{
1213 PAPIC pApic = VM_TO_APIC(pVM);
1214 LogFlow(("APIC: apicR3TermState: pVM=%p\n", pVM));
1215
1216 /* Unmap and free the PIB. */
1217 if (pApic->pvApicPibR3 != NIL_RTR3PTR)
1218 {
1219 size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
1220 if (cPages == 1)
1221 SUPR3PageFreeEx(pApic->pvApicPibR3, cPages);
1222 else
1223 SUPR3ContFree(pApic->pvApicPibR3, cPages);
1224 pApic->pvApicPibR3 = NIL_RTR3PTR;
1225 pApic->pvApicPibR0 = NIL_RTR0PTR;
1226 pApic->pvApicPibRC = NIL_RTRCPTR;
1227 }
1228
1229 /* Unmap and free the virtual-APIC pages. */
1230 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1231 {
1232 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1233 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1234
1235 pApicCpu->pvApicPibR3 = NIL_RTR3PTR;
1236 pApicCpu->pvApicPibR0 = NIL_RTR0PTR;
1237 pApicCpu->pvApicPibRC = NIL_RTRCPTR;
1238
1239 if (pApicCpu->pvApicPageR3 != NIL_RTR3PTR)
1240 {
1241 SUPR3PageFreeEx(pApicCpu->pvApicPageR3, 1 /* cPages */);
1242 pApicCpu->pvApicPageR3 = NIL_RTR3PTR;
1243 pApicCpu->pvApicPageR0 = NIL_RTR0PTR;
1244 pApicCpu->pvApicPageRC = NIL_RTRCPTR;
1245 }
1246 }
1247}
1248
1249
1250/**
1251 * Initializes the APIC state.
1252 *
1253 * @returns VBox status code.
1254 * @param pVM The cross context VM structure.
1255 */
1256static int apicR3InitState(PVM pVM)
1257{
1258 PAPIC pApic = VM_TO_APIC(pVM);
1259 LogFlow(("APIC: apicR3InitState: pVM=%p\n", pVM));
1260
1261 /* With hardware virtualization, we don't need to map the APIC in GC. */
1262 bool const fNeedsGCMapping = !HMIsEnabled(pVM);
1263
1264 /*
1265 * Allocate and map the pending-interrupt bitmap (PIB).
1266 *
1267 * We allocate all the VCPUs' PIBs contiguously in order to save space as
1268 * physically contiguous allocations are rounded to a multiple of page size.
1269 */
1270 Assert(pApic->pvApicPibR3 == NIL_RTR3PTR);
1271 Assert(pApic->pvApicPibR0 == NIL_RTR0PTR);
1272 Assert(pApic->pvApicPibRC == NIL_RTRCPTR);
1273 pApic->cbApicPib = RT_ALIGN_Z(pVM->cCpus * sizeof(APICPIB), PAGE_SIZE);
1274 size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
1275 if (cPages == 1)
1276 {
1277 SUPPAGE SupApicPib;
1278 RT_ZERO(SupApicPib);
1279 SupApicPib.Phys = NIL_RTHCPHYS;
1280 int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, &pApic->pvApicPibR3, &pApic->pvApicPibR0, &SupApicPib);
1281 if (RT_SUCCESS(rc))
1282 {
1283 pApic->HCPhysApicPib = SupApicPib.Phys;
1284 AssertLogRelReturn(pApic->pvApicPibR3, VERR_INTERNAL_ERROR);
1285 }
1286 else
1287 {
1288 LogRel(("APIC: Failed to allocate %u bytes for the pending-interrupt bitmap, rc=%Rrc\n", pApic->cbApicPib, rc));
1289 return rc;
1290 }
1291 }
1292 else
1293 pApic->pvApicPibR3 = SUPR3ContAlloc(cPages, &pApic->pvApicPibR0, &pApic->HCPhysApicPib);
1294
1295 if (pApic->pvApicPibR3)
1296 {
1297 AssertLogRelReturn(pApic->pvApicPibR0 != NIL_RTR0PTR, VERR_INTERNAL_ERROR);
1298 AssertLogRelReturn(pApic->HCPhysApicPib != NIL_RTHCPHYS, VERR_INTERNAL_ERROR);
1299
1300 /* Initialize the PIB. */
1301 RT_BZERO(pApic->pvApicPibR3, pApic->cbApicPib);
1302
1303 /* Map the PIB into GC. */
1304 if (fNeedsGCMapping)
1305 {
1306 pApic->pvApicPibRC = NIL_RTRCPTR;
1307 int rc = MMR3HyperMapHCPhys(pVM, pApic->pvApicPibR3, NIL_RTR0PTR, pApic->HCPhysApicPib, pApic->cbApicPib,
1308 "APIC PIB", (PRTGCPTR)&pApic->pvApicPibRC);
1309 if (RT_FAILURE(rc))
1310 {
1311 LogRel(("APIC: Failed to map %u bytes for the pending-interrupt bitmap into GC, rc=%Rrc\n", pApic->cbApicPib,
1312 rc));
1313 apicR3TermState(pVM);
1314 return rc;
1315 }
1316
1317 AssertLogRelReturn(pApic->pvApicPibRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
1318 }
1319
1320 /*
1321 * Allocate the map the virtual-APIC pages.
1322 */
1323 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1324 {
1325 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1326 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1327
1328 SUPPAGE SupApicPage;
1329 RT_ZERO(SupApicPage);
1330 SupApicPage.Phys = NIL_RTHCPHYS;
1331
1332 Assert(pVCpu->idCpu == idCpu);
1333 Assert(pApicCpu->pvApicPageR3 == NIL_RTR0PTR);
1334 Assert(pApicCpu->pvApicPageR0 == NIL_RTR0PTR);
1335 Assert(pApicCpu->pvApicPageRC == NIL_RTRCPTR);
1336 AssertCompile(sizeof(XAPICPAGE) == PAGE_SIZE);
1337 pApicCpu->cbApicPage = sizeof(XAPICPAGE);
1338 int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, &pApicCpu->pvApicPageR3, &pApicCpu->pvApicPageR0,
1339 &SupApicPage);
1340 if (RT_SUCCESS(rc))
1341 {
1342 AssertLogRelReturn(pApicCpu->pvApicPageR3 != NIL_RTR3PTR, VERR_INTERNAL_ERROR);
1343 AssertLogRelReturn(pApicCpu->HCPhysApicPage != NIL_RTHCPHYS, VERR_INTERNAL_ERROR);
1344 pApicCpu->HCPhysApicPage = SupApicPage.Phys;
1345
1346 /* Map the virtual-APIC page into GC. */
1347 if (fNeedsGCMapping)
1348 {
1349 rc = MMR3HyperMapHCPhys(pVM, pApicCpu->pvApicPageR3, NIL_RTR0PTR, pApicCpu->HCPhysApicPage,
1350 pApicCpu->cbApicPage, "APIC", (PRTGCPTR)&pApicCpu->pvApicPageRC);
1351 if (RT_FAILURE(rc))
1352 {
1353 LogRel(("APIC%u: Failed to map %u bytes for the virtual-APIC page into GC, rc=%Rrc", idCpu,
1354 pApicCpu->cbApicPage, rc));
1355 apicR3TermState(pVM);
1356 return rc;
1357 }
1358
1359 AssertLogRelReturn(pApicCpu->pvApicPageRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
1360 }
1361
1362 /* Associate the per-VCPU PIB pointers to the per-VM PIB mapping. */
1363 uint32_t const offApicPib = idCpu * sizeof(APICPIB);
1364 pApicCpu->pvApicPibR0 = (RTR0PTR)((RTR0UINTPTR)pApic->pvApicPibR0 + offApicPib);
1365 pApicCpu->pvApicPibR3 = (RTR3PTR)((RTR3UINTPTR)pApic->pvApicPibR3 + offApicPib);
1366 if (fNeedsGCMapping)
1367 pApicCpu->pvApicPibRC = (RTRCPTR)((RTRCUINTPTR)pApic->pvApicPibRC + offApicPib);
1368
1369 /* Initialize the virtual-APIC state. */
1370 RT_BZERO(pApicCpu->pvApicPageR3, pApicCpu->cbApicPage);
1371 APICR3Reset(pVCpu, true /* fResetApicBaseMsr */);
1372
1373#ifdef DEBUG_ramshankar
1374 Assert(pApicCpu->pvApicPibR3 != NIL_RTR3PTR);
1375 Assert(pApicCpu->pvApicPibR0 != NIL_RTR0PTR);
1376 Assert(!fNeedsGCMapping || pApicCpu->pvApicPibRC != NIL_RTRCPTR);
1377 Assert(pApicCpu->pvApicPageR3 != NIL_RTR3PTR);
1378 Assert(pApicCpu->pvApicPageR0 != NIL_RTR0PTR);
1379 Assert(!fNeedsGCMapping || pApicCpu->pvApicPageRC != NIL_RTRCPTR);
1380 Assert(!fNeedsGCMapping || pApic->pvApicPibRC == pVM->aCpus[0].apic.s.pvApicPibRC);
1381#endif
1382 }
1383 else
1384 {
1385 LogRel(("APIC%u: Failed to allocate %u bytes for the virtual-APIC page, rc=%Rrc\n", pApicCpu->cbApicPage, rc));
1386 apicR3TermState(pVM);
1387 return rc;
1388 }
1389 }
1390
1391#ifdef DEBUG_ramshankar
1392 Assert(pApic->pvApicPibR3 != NIL_RTR3PTR);
1393 Assert(pApic->pvApicPibR0 != NIL_RTR0PTR);
1394 Assert(!fNeedsGCMapping || pApic->pvApicPibRC != NIL_RTRCPTR);
1395#endif
1396 return VINF_SUCCESS;
1397 }
1398
1399 LogRel(("APIC: Failed to allocate %u bytes of physically contiguous memory for the pending-interrupt bitmap\n",
1400 pApic->cbApicPib));
1401 return VERR_NO_MEMORY;
1402}
1403
1404
1405/**
1406 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1407 */
1408static DECLCALLBACK(int) apicR3Destruct(PPDMDEVINS pDevIns)
1409{
1410 PVM pVM = PDMDevHlpGetVM(pDevIns);
1411 LogFlow(("APIC: apicR3Destruct: pVM=%p\n", pVM));
1412
1413 apicR3TermState(pVM);
1414 return VINF_SUCCESS;
1415}
1416
1417
1418/**
1419 * @interface_method_impl{PDMDEVREG,pfnInitComplete}
1420 */
1421static DECLCALLBACK(int) apicR3InitComplete(PPDMDEVINS pDevIns)
1422{
1423 PVM pVM = PDMDevHlpGetVM(pDevIns);
1424 PAPIC pApic = VM_TO_APIC(pVM);
1425
1426 /*
1427 * Init APIC settings that rely on HM and CPUM configurations.
1428 */
1429 CPUMCPUIDLEAF CpuLeaf;
1430 int rc = CPUMR3CpuIdGetLeaf(pVM, &CpuLeaf, 1, 0);
1431 AssertRCReturn(rc, rc);
1432
1433 pApic->fSupportsTscDeadline = RT_BOOL(CpuLeaf.uEcx & X86_CPUID_FEATURE_ECX_TSCDEADL);
1434 pApic->fPostedIntrsEnabled = HMR3IsPostedIntrsEnabled(pVM->pUVM);
1435 pApic->fVirtApicRegsEnabled = HMR3IsVirtApicRegsEnabled(pVM->pUVM);
1436
1437 LogRel(("APIC: fPostedIntrsEnabled=%RTbool fVirtApicRegsEnabled=%RTbool fSupportsTscDeadline=%RTbool\n",
1438 pApic->fPostedIntrsEnabled, pApic->fVirtApicRegsEnabled, pApic->fSupportsTscDeadline));
1439
1440 return VINF_SUCCESS;
1441}
1442
1443
1444/**
1445 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1446 */
1447static DECLCALLBACK(int) apicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1448{
1449 /*
1450 * Validate inputs.
1451 */
1452 Assert(iInstance == 0);
1453 Assert(pDevIns);
1454
1455 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1456 PVM pVM = PDMDevHlpGetVM(pDevIns);
1457 PAPIC pApic = VM_TO_APIC(pVM);
1458
1459 /*
1460 * Validate APIC settings.
1461 */
1462 if (!CFGMR3AreValuesValid(pCfg, "RZEnabled\0"
1463 "Mode\0"
1464 "IOAPIC\0"
1465 "NumCPUs\0"))
1466 {
1467 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1468 N_("APIC configuration error: unknown option specified"));
1469 }
1470
1471 int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pApic->fRZEnabled, true);
1472 AssertLogRelRCReturn(rc, rc);
1473
1474 rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &pApic->fIoApicPresent, true);
1475 AssertLogRelRCReturn(rc, rc);
1476
1477 uint8_t uOriginalMode;
1478 rc = CFGMR3QueryU8Def(pCfg, "Mode", &uOriginalMode, APICMODE_XAPIC);
1479 AssertLogRelRCReturn(rc, rc);
1480
1481 /* Validate APIC modes. */
1482 APICMODE const enmOriginalMode = (APICMODE)uOriginalMode;
1483 switch (enmOriginalMode)
1484 {
1485 case APICMODE_DISABLED:
1486 {
1487 /** @todo permanently disabling the APIC won't really work (needs
1488 * fixing in HM, CPUM, PDM and possibly other places). See
1489 * @bugref{8353}. */
1490#if 0
1491 pApic->enmOriginalMode = enmOriginalMode;
1492 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
1493 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
1494 break;
1495#else
1496 return VMR3SetError(pVM->pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, "APIC mode 'disabled' is not supported yet.");
1497#endif
1498 }
1499
1500 case APICMODE_X2APIC:
1501 pApic->enmOriginalMode = enmOriginalMode;
1502 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
1503 break;
1504
1505 case APICMODE_XAPIC:
1506 pApic->enmOriginalMode = enmOriginalMode;
1507 /* The CPUID bit will be updated in apicR3ResetBaseMsr(). */
1508 break;
1509
1510 default:
1511 return VMR3SetError(pVM->pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, "APIC mode %#x unknown.", uOriginalMode);
1512 }
1513
1514 /*
1515 * Initialize the APIC state.
1516 */
1517 pApicDev->pDevInsR3 = pDevIns;
1518 pApicDev->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1519 pApicDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1520
1521 pApic->pApicDevR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1522 pApic->pApicDevR3 = (PAPICDEV)PDMINS_2_DATA_R3PTR(pDevIns);
1523 pApic->pApicDevRC = PDMINS_2_DATA_RCPTR(pDevIns);
1524
1525 rc = apicR3InitState(pVM);
1526 AssertRCReturn(rc, rc);
1527
1528 /*
1529 * Disable automatic PDM locking for this device.
1530 */
1531 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1532 AssertRCReturn(rc, rc);
1533
1534 /*
1535 * Register the APIC.
1536 */
1537 PDMAPICREG ApicReg;
1538 RT_ZERO(ApicReg);
1539 ApicReg.u32Version = PDM_APICREG_VERSION;
1540 ApicReg.pfnGetInterruptR3 = APICGetInterrupt;
1541 ApicReg.pfnSetBaseMsrR3 = APICSetBaseMsr;
1542 ApicReg.pfnGetBaseMsrR3 = APICGetBaseMsr;
1543 ApicReg.pfnSetTprR3 = APICSetTpr;
1544 ApicReg.pfnGetTprR3 = APICGetTpr;
1545 ApicReg.pfnWriteMsrR3 = APICWriteMsr;
1546 ApicReg.pfnReadMsrR3 = APICReadMsr;
1547 ApicReg.pfnBusDeliverR3 = APICBusDeliver;
1548 ApicReg.pfnLocalInterruptR3 = APICLocalInterrupt;
1549 ApicReg.pfnGetTimerFreqR3 = APICGetTimerFreq;
1550
1551 /*
1552 * We always require R0 functionality (e.g. APICGetTpr() called by HMR0 VT-x/AMD-V code).
1553 * Hence, 'fRZEnabled' strictly only applies to MMIO and MSR read/write handlers returning
1554 * to ring-3. We still need other handlers like APICGetTpr() in ring-0 for now.
1555 */
1556 {
1557 ApicReg.pszGetInterruptRC = "APICGetInterrupt";
1558 ApicReg.pszSetBaseMsrRC = "APICSetBaseMsr";
1559 ApicReg.pszGetBaseMsrRC = "APICGetBaseMsr";
1560 ApicReg.pszSetTprRC = "APICSetTpr";
1561 ApicReg.pszGetTprRC = "APICGetTpr";
1562 ApicReg.pszWriteMsrRC = "APICWriteMsr";
1563 ApicReg.pszReadMsrRC = "APICReadMsr";
1564 ApicReg.pszBusDeliverRC = "APICBusDeliver";
1565 ApicReg.pszLocalInterruptRC = "APICLocalInterrupt";
1566 ApicReg.pszGetTimerFreqRC = "APICGetTimerFreq";
1567
1568 ApicReg.pszGetInterruptR0 = "APICGetInterrupt";
1569 ApicReg.pszSetBaseMsrR0 = "APICSetBaseMsr";
1570 ApicReg.pszGetBaseMsrR0 = "APICGetBaseMsr";
1571 ApicReg.pszSetTprR0 = "APICSetTpr";
1572 ApicReg.pszGetTprR0 = "APICGetTpr";
1573 ApicReg.pszWriteMsrR0 = "APICWriteMsr";
1574 ApicReg.pszReadMsrR0 = "APICReadMsr";
1575 ApicReg.pszBusDeliverR0 = "APICBusDeliver";
1576 ApicReg.pszLocalInterruptR0 = "APICLocalInterrupt";
1577 ApicReg.pszGetTimerFreqR0 = "APICGetTimerFreq";
1578 }
1579
1580 rc = PDMDevHlpAPICRegister(pDevIns, &ApicReg, &pApicDev->pApicHlpR3);
1581 AssertLogRelRCReturn(rc, rc);
1582 pApicDev->pCritSectR3 = pApicDev->pApicHlpR3->pfnGetR3CritSect(pDevIns);
1583
1584 /*
1585 * Register the MMIO range.
1586 */
1587 PAPICCPU pApicCpu0 = VMCPU_TO_APICCPU(&pVM->aCpus[0]);
1588 RTGCPHYS GCPhysApicBase = MSR_IA32_APICBASE_GET_ADDR(pApicCpu0->uApicBaseMsr);
1589
1590 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NULL /* pvUser */,
1591 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED,
1592 APICWriteMmio, APICReadMmio, "APIC");
1593 if (RT_FAILURE(rc))
1594 return rc;
1595
1596 if (pApic->fRZEnabled)
1597 {
1598 pApicDev->pApicHlpRC = pApicDev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
1599 pApicDev->pCritSectRC = pApicDev->pApicHlpR3->pfnGetRCCritSect(pDevIns);
1600 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NIL_RTRCPTR /*pvUser*/,
1601 "APICWriteMmio", "APICReadMmio");
1602 if (RT_FAILURE(rc))
1603 return rc;
1604
1605 pApicDev->pApicHlpR0 = pApicDev->pApicHlpR3->pfnGetR0Helpers(pDevIns);
1606 pApicDev->pCritSectR0 = pApicDev->pApicHlpR3->pfnGetR0CritSect(pDevIns);
1607 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NIL_RTR0PTR /*pvUser*/,
1608 "APICWriteMmio", "APICReadMmio");
1609 if (RT_FAILURE(rc))
1610 return rc;
1611 }
1612
1613 /*
1614 * Create the APIC timers.
1615 */
1616 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1617 {
1618 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1619 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1620 RTStrPrintf(&pApicCpu->szTimerDesc[0], sizeof(pApicCpu->szTimerDesc), "APIC Timer %u", pVCpu->idCpu);
1621 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicR3TimerCallback, pVCpu, TMTIMER_FLAGS_NO_CRIT_SECT,
1622 pApicCpu->szTimerDesc, &pApicCpu->pTimerR3);
1623 if (RT_SUCCESS(rc))
1624 {
1625 pApicCpu->pTimerR0 = TMTimerR0Ptr(pApicCpu->pTimerR3);
1626 pApicCpu->pTimerRC = TMTimerRCPtr(pApicCpu->pTimerR3);
1627 }
1628 else
1629 return rc;
1630 }
1631
1632 /*
1633 * Register saved state callbacks.
1634 */
1635 rc = PDMDevHlpSSMRegister3(pDevIns, APIC_SAVED_STATE_VERSION, sizeof(*pApicDev), NULL /*pfnLiveExec*/, apicR3SaveExec,
1636 apicR3LoadExec);
1637 if (RT_FAILURE(rc))
1638 return rc;
1639
1640 /*
1641 * Register debugger info callback.
1642 */
1643 rc = PDMDevHlpDBGFInfoRegister(pDevIns, "apic", "Display local APIC state for current CPU. Recognizes "
1644 "'basic', 'lvt', 'timer' as arguments, defaults to 'basic'.", apicR3DbgInfo);
1645 AssertRCReturn(rc, rc);
1646
1647#ifdef VBOX_WITH_STATISTICS
1648 /*
1649 * Statistics.
1650 */
1651#define APIC_REG_COUNTER(a_Reg, a_Desc, a_Key) \
1652 do { \
1653 rc = STAMR3RegisterF(pVM, a_Reg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, a_Desc, a_Key, idCpu); \
1654 AssertRCReturn(rc, rc); \
1655 } while(0)
1656
1657#define APIC_PROF_COUNTER(a_Reg, a_Desc, a_Key) \
1658 do { \
1659 rc = STAMR3RegisterF(pVM, a_Reg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, a_Desc, a_Key, \
1660 idCpu); \
1661 AssertRCReturn(rc, rc); \
1662 } while(0)
1663
1664 bool const fHasRC = !HMIsEnabled(pVM);
1665 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1666 {
1667 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1668 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1669
1670 APIC_REG_COUNTER(&pApicCpu->StatMmioReadR0, "Number of APIC MMIO reads in R0.", "/Devices/APIC/%u/R0/MmioRead");
1671 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteR0, "Number of APIC MMIO writes in R0.", "/Devices/APIC/%u/R0/MmioWrite");
1672 APIC_REG_COUNTER(&pApicCpu->StatMsrReadR0, "Number of APIC MSR reads in R0.", "/Devices/APIC/%u/R0/MsrRead");
1673 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteR0, "Number of APIC MSR writes in R0.", "/Devices/APIC/%u/R0/MsrWrite");
1674
1675 APIC_REG_COUNTER(&pApicCpu->StatMmioReadR3, "Number of APIC MMIO reads in R3.", "/Devices/APIC/%u/R3/MmioReadR3");
1676 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteR3, "Number of APIC MMIO writes in R3.", "/Devices/APIC/%u/R3/MmioWriteR3");
1677 APIC_REG_COUNTER(&pApicCpu->StatMsrReadR3, "Number of APIC MSR reads in R3.", "/Devices/APIC/%u/R3/MsrReadR3");
1678 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteR3, "Number of APIC MSR writes in R3.", "/Devices/APIC/%u/R3/MsrWriteR3");
1679
1680 if (fHasRC)
1681 {
1682 APIC_REG_COUNTER(&pApicCpu->StatMmioReadRC, "Number of APIC MMIO reads in RC.", "/Devices/APIC/%u/RC/MmioRead");
1683 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteRC, "Number of APIC MMIO writes in RC.", "/Devices/APIC/%u/RC/MmioWrite");
1684 APIC_REG_COUNTER(&pApicCpu->StatMsrReadRC, "Number of APIC MSR reads in RC.", "/Devices/APIC/%u/RC/MsrRead");
1685 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteRC, "Number of APIC MSR writes in RC.", "/Devices/APIC/%u/RC/MsrWrite");
1686 }
1687
1688 APIC_PROF_COUNTER(&pApicCpu->StatUpdatePendingIntrs, "Profiling of APICUpdatePendingInterrupts",
1689 "/PROF/CPU%d/APIC/UpdatePendingInterrupts");
1690 APIC_PROF_COUNTER(&pApicCpu->StatPostIntr, "Profiling of APICPostInterrupt", "/PROF/CPU%d/APIC/PostInterrupt");
1691
1692 APIC_REG_COUNTER(&pApicCpu->StatPostIntrAlreadyPending, "Number of times an interrupt is already pending.",
1693 "/Devices/APIC/%u/PostInterruptAlreadyPending");
1694 APIC_REG_COUNTER(&pApicCpu->StatTimerCallback, "Number of times the timer callback is invoked.",
1695 "/Devices/APIC/%u/TimerCallback");
1696
1697 APIC_REG_COUNTER(&pApicCpu->StatTprWrite, "Number of TPR writes.", "/Devices/APIC/%u/TprWrite");
1698 APIC_REG_COUNTER(&pApicCpu->StatTprRead, "Number of TPR reads.", "/Devices/APIC/%u/TprRead");
1699 APIC_REG_COUNTER(&pApicCpu->StatEoiWrite, "Number of EOI writes.", "/Devices/APIC/%u/EoiWrite");
1700 APIC_REG_COUNTER(&pApicCpu->StatMaskedByTpr, "Number of times TPR masks an interrupt in APICGetInterrupt.",
1701 "/Devices/APIC/%u/MaskedByTpr");
1702 APIC_REG_COUNTER(&pApicCpu->StatMaskedByPpr, "Number of time PPR masks an interrupt in APICGetInterrupt.",
1703 "/Devices/APIC/%u/MaskedByPpr");
1704 }
1705# undef APIC_PROF_COUNTER
1706# undef APIC_REG_ACCESS_COUNTER
1707#endif
1708
1709 return VINF_SUCCESS;
1710}
1711
1712
1713/**
1714 * APIC device registration structure.
1715 */
1716const PDMDEVREG g_DeviceAPIC =
1717{
1718 /* u32Version */
1719 PDM_DEVREG_VERSION,
1720 /* szName */
1721 "apic",
1722 /* szRCMod */
1723 "VMMRC.rc",
1724 /* szR0Mod */
1725 "VMMR0.r0",
1726 /* pszDescription */
1727 "Advanced Programmable Interrupt Controller",
1728 /* fFlags */
1729 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36
1730 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
1731 /* fClass */
1732 PDM_DEVREG_CLASS_PIC,
1733 /* cMaxInstances */
1734 1,
1735 /* cbInstance */
1736 sizeof(APICDEV),
1737 /* pfnConstruct */
1738 apicR3Construct,
1739 /* pfnDestruct */
1740 apicR3Destruct,
1741 /* pfnRelocate */
1742 apicR3Relocate,
1743 /* pfnMemSetup */
1744 NULL,
1745 /* pfnPowerOn */
1746 NULL,
1747 /* pfnReset */
1748 apicR3Reset,
1749 /* pfnSuspend */
1750 NULL,
1751 /* pfnResume */
1752 NULL,
1753 /* pfnAttach */
1754 NULL,
1755 /* pfnDetach */
1756 NULL,
1757 /* pfnQueryInterface. */
1758 NULL,
1759 /* pfnInitComplete */
1760 apicR3InitComplete,
1761 /* pfnPowerOff */
1762 NULL,
1763 /* pfnSoftReset */
1764 NULL,
1765 /* u32VersionEnd */
1766 PDM_DEVREG_VERSION
1767};
1768
1769#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1770
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