VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp@ 65932

Last change on this file since 65932 was 65338, checked in by vboxsync, 8 years ago

Remove the old, unused I/O APIC code and related define.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 27.9 KB
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1/* $Id: PDMR0Device.cpp 65338 2017-01-16 14:11:15Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, R0 Device parts.
4 */
5
6/*
7 * Copyright (C) 2006-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
24#include "PDMInternal.h"
25#include <VBox/vmm/pdm.h>
26#include <VBox/vmm/pgm.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/vm.h>
29#include <VBox/vmm/vmm.h>
30#include <VBox/vmm/patm.h>
31#include <VBox/vmm/hm.h>
32#include <VBox/vmm/apic.h>
33
34#include <VBox/log.h>
35#include <VBox/err.h>
36#include <VBox/vmm/gvmm.h>
37#include <iprt/asm.h>
38#include <iprt/assert.h>
39#include <iprt/string.h>
40
41#include "dtrace/VBoxVMM.h"
42#include "PDMInline.h"
43
44
45/*********************************************************************************************************************************
46* Global Variables *
47*********************************************************************************************************************************/
48RT_C_DECLS_BEGIN
49extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp;
50extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp;
51extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp;
52extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp;
53extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp;
54extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp;
55extern DECLEXPORT(const PDMDRVHLPR0) g_pdmR0DrvHlp;
56RT_C_DECLS_END
57
58
59/*********************************************************************************************************************************
60* Internal Functions *
61*********************************************************************************************************************************/
62static bool pdmR0IsaSetIrq(PVM pVM, int iIrq, int iLevel, uint32_t uTagSrc);
63
64
65
66/** @name Ring-0 Device Helpers
67 * @{
68 */
69
70/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysRead} */
71static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
72 void *pvBuf, size_t cbRead)
73{
74 PDMDEV_ASSERT_DEVINS(pDevIns);
75 if (!pPciDev) /* NULL is an alias for the default PCI device. */
76 pPciDev = pDevIns->Internal.s.pHeadPciDevR0;
77 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
78
79#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
80 /*
81 * Just check the busmaster setting here and forward the request to the generic read helper.
82 */
83 if (PCIDevIsBusmaster(pPciDev))
84 { /* likely */ }
85 else
86 {
87 Log(("pdmRCDevHlp_PCIPhysRead: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#zx\n",
88 pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
89 return VERR_PDM_NOT_PCI_BUS_MASTER;
90 }
91#endif
92
93 return pDevIns->pHlpR0->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead);
94}
95
96
97/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysWrite} */
98static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
99 const void *pvBuf, size_t cbWrite)
100{
101 PDMDEV_ASSERT_DEVINS(pDevIns);
102 if (!pPciDev) /* NULL is an alias for the default PCI device. */
103 pPciDev = pDevIns->Internal.s.pHeadPciDevR0;
104 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
105
106#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
107 /*
108 * Just check the busmaster setting here and forward the request to the generic read helper.
109 */
110 if (PCIDevIsBusmaster(pPciDev))
111 { /* likely */ }
112 else
113 {
114 Log(("pdmRCDevHlp_PCIPhysWrite: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#zx\n",
115 pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
116 return VERR_PDM_NOT_PCI_BUS_MASTER;
117 }
118#endif
119
120 return pDevIns->pHlpR0->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
121}
122
123
124/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
125static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
126{
127 PDMDEV_ASSERT_DEVINS(pDevIns);
128 if (!pPciDev) /* NULL is an alias for the default PCI device. */
129 pPciDev = pDevIns->Internal.s.pHeadPciDevR0;
130 AssertReturnVoid(pPciDev);
131 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: pPciDev=%p:{%#x} iIrq=%d iLevel=%d\n",
132 pDevIns, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iIrq, iLevel));
133 PVM pVM = pDevIns->Internal.s.pVMR0;
134 PPDMPCIBUS pPciBus = pPciDev->Int.s.pPdmBusR0;
135
136 pdmLock(pVM);
137 uint32_t uTagSrc;
138 if (iLevel & PDM_IRQ_LEVEL_HIGH)
139 {
140 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
141 if (iLevel == PDM_IRQ_LEVEL_HIGH)
142 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
143 else
144 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
145 }
146 else
147 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
148
149 if ( pPciBus
150 && pPciBus->pDevInsR0)
151 {
152 pPciBus->pfnSetIrqR0(pPciBus->pDevInsR0, pPciDev, iIrq, iLevel, uTagSrc);
153
154 pdmUnlock(pVM);
155
156 if (iLevel == PDM_IRQ_LEVEL_LOW)
157 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
158 }
159 else
160 {
161 pdmUnlock(pVM);
162
163 /* queue for ring-3 execution. */
164 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
165 AssertReturnVoid(pTask);
166
167 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
168 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
169 pTask->u.PciSetIRQ.iIrq = iIrq;
170 pTask->u.PciSetIRQ.iLevel = iLevel;
171 pTask->u.PciSetIRQ.uTagSrc = uTagSrc;
172 pTask->u.PciSetIRQ.pPciDevR3 = MMHyperR0ToR3(pVM, pPciDev);
173
174 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
175 }
176
177 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
178}
179
180
181/** @interface_method_impl{PDMDEVHLPR0,pfnISASetIrq} */
182static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
183{
184 PDMDEV_ASSERT_DEVINS(pDevIns);
185 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
186 PVM pVM = pDevIns->Internal.s.pVMR0;
187
188 pdmLock(pVM);
189 uint32_t uTagSrc;
190 if (iLevel & PDM_IRQ_LEVEL_HIGH)
191 {
192 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
193 if (iLevel == PDM_IRQ_LEVEL_HIGH)
194 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
195 else
196 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
197 }
198 else
199 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
200
201 bool fRc = pdmR0IsaSetIrq(pVM, iIrq, iLevel, uTagSrc);
202
203 if (iLevel == PDM_IRQ_LEVEL_LOW && fRc)
204 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
205 pdmUnlock(pVM);
206 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
207}
208
209
210/** @interface_method_impl{PDMDEVHLPR0,pfnPhysRead} */
211static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
212{
213 PDMDEV_ASSERT_DEVINS(pDevIns);
214 LogFlow(("pdmR0DevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
215 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
216
217 VBOXSTRICTRC rcStrict = PGMPhysRead(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
218 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
219
220 Log(("pdmR0DevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
221 return VBOXSTRICTRC_VAL(rcStrict);
222}
223
224
225/** @interface_method_impl{PDMDEVHLPR0,pfnPhysWrite} */
226static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
227{
228 PDMDEV_ASSERT_DEVINS(pDevIns);
229 LogFlow(("pdmR0DevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
230 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
231
232 VBOXSTRICTRC rcStrict = PGMPhysWrite(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
233 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
234
235 Log(("pdmR0DevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
236 return VBOXSTRICTRC_VAL(rcStrict);
237}
238
239
240/** @interface_method_impl{PDMDEVHLPR0,pfnA20IsEnabled} */
241static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
242{
243 PDMDEV_ASSERT_DEVINS(pDevIns);
244 LogFlow(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
245
246 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pVMR0));
247
248 Log(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
249 return fEnabled;
250}
251
252
253/** @interface_method_impl{PDMDEVHLPR0,pfnVMState} */
254static DECLCALLBACK(VMSTATE) pdmR0DevHlp_VMState(PPDMDEVINS pDevIns)
255{
256 PDMDEV_ASSERT_DEVINS(pDevIns);
257
258 VMSTATE enmVMState = pDevIns->Internal.s.pVMR0->enmVMState;
259
260 LogFlow(("pdmR0DevHlp_VMState: caller=%p/%d: returns %d\n", pDevIns, pDevIns->iInstance, enmVMState));
261 return enmVMState;
262}
263
264
265/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetError} */
266static DECLCALLBACK(int) pdmR0DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
267{
268 PDMDEV_ASSERT_DEVINS(pDevIns);
269 va_list args;
270 va_start(args, pszFormat);
271 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
272 va_end(args);
273 return rc;
274}
275
276
277/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetErrorV} */
278static DECLCALLBACK(int) pdmR0DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
279{
280 PDMDEV_ASSERT_DEVINS(pDevIns);
281 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
282 return rc;
283}
284
285
286/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeError} */
287static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
288{
289 PDMDEV_ASSERT_DEVINS(pDevIns);
290 va_list va;
291 va_start(va, pszFormat);
292 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
293 va_end(va);
294 return rc;
295}
296
297
298/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeErrorV} */
299static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
300{
301 PDMDEV_ASSERT_DEVINS(pDevIns);
302 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
303 return rc;
304}
305
306
307/** @interface_method_impl{PDMDEVHLPR0,pfnPATMSetMMIOPatchInfo} */
308static DECLCALLBACK(int) pdmR0DevHlp_PATMSetMMIOPatchInfo(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPTR pCachedData)
309{
310 PDMDEV_ASSERT_DEVINS(pDevIns);
311 LogFlow(("pdmR0DevHlp_PATMSetMMIOPatchInfo: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
312
313 AssertFailed();
314 NOREF(GCPhys); NOREF(pCachedData); NOREF(pDevIns);
315
316/* return PATMSetMMIOPatchInfo(pDevIns->Internal.s.pVMR0, GCPhys, pCachedData); */
317 return VINF_SUCCESS;
318}
319
320
321/** @interface_method_impl{PDMDEVHLPR0,pfnGetVM} */
322static DECLCALLBACK(PVM) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns)
323{
324 PDMDEV_ASSERT_DEVINS(pDevIns);
325 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
326 return pDevIns->Internal.s.pVMR0;
327}
328
329
330/** @interface_method_impl{PDMDEVHLPR0,pfnGetVMCPU} */
331static DECLCALLBACK(PVMCPU) pdmR0DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
332{
333 PDMDEV_ASSERT_DEVINS(pDevIns);
334 LogFlow(("pdmR0DevHlp_GetVMCPU: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
335 return VMMGetCpu(pDevIns->Internal.s.pVMR0);
336}
337
338
339/** @interface_method_impl{PDMDEVHLPRC,pfnGetCurrentCpuId} */
340static DECLCALLBACK(VMCPUID) pdmR0DevHlp_GetCurrentCpuId(PPDMDEVINS pDevIns)
341{
342 PDMDEV_ASSERT_DEVINS(pDevIns);
343 VMCPUID idCpu = VMMGetCpuId(pDevIns->Internal.s.pVMR0);
344 LogFlow(("pdmR0DevHlp_GetCurrentCpuId: caller='%p'/%d for CPU %u\n", pDevIns, pDevIns->iInstance, idCpu));
345 return idCpu;
346}
347
348
349/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGet} */
350static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
351{
352 PDMDEV_ASSERT_DEVINS(pDevIns);
353 LogFlow(("pdmR0DevHlp_TMTimeVirtGet: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
354 return TMVirtualGet(pDevIns->Internal.s.pVMR0);
355}
356
357
358/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetFreq} */
359static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
360{
361 PDMDEV_ASSERT_DEVINS(pDevIns);
362 LogFlow(("pdmR0DevHlp_TMTimeVirtGetFreq: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
363 return TMVirtualGetFreq(pDevIns->Internal.s.pVMR0);
364}
365
366
367/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetNano} */
368static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
369{
370 PDMDEV_ASSERT_DEVINS(pDevIns);
371 LogFlow(("pdmR0DevHlp_TMTimeVirtGetNano: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
372 return TMVirtualToNano(pDevIns->Internal.s.pVMR0, TMVirtualGet(pDevIns->Internal.s.pVMR0));
373}
374
375
376/** @interface_method_impl{PDMDEVHLPR0,pfnDBGFTraceBuf} */
377static DECLCALLBACK(RTTRACEBUF) pdmR0DevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
378{
379 PDMDEV_ASSERT_DEVINS(pDevIns);
380 RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pVMR0->hTraceBufR0;
381 LogFlow(("pdmR3DevHlp_DBGFTraceBuf: caller='%p'/%d: returns %p\n", pDevIns, pDevIns->iInstance, hTraceBuf));
382 return hTraceBuf;
383}
384
385
386/** @interface_method_impl{PDMDEVHLPR0,pfnCanEmulateIoBlock} */
387static DECLCALLBACK(bool) pdmR0DevHlp_CanEmulateIoBlock(PPDMDEVINS pDevIns)
388{
389 PDMDEV_ASSERT_DEVINS(pDevIns);
390 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
391 return HMCanEmulateIoBlock(VMMGetCpu(pDevIns->Internal.s.pVMR0));
392}
393
394
395/**
396 * The Ring-0 Device Helper Callbacks.
397 */
398extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp =
399{
400 PDM_DEVHLPR0_VERSION,
401 pdmR0DevHlp_PCIPhysRead,
402 pdmR0DevHlp_PCIPhysWrite,
403 pdmR0DevHlp_PCISetIrq,
404 pdmR0DevHlp_ISASetIrq,
405 pdmR0DevHlp_PhysRead,
406 pdmR0DevHlp_PhysWrite,
407 pdmR0DevHlp_A20IsEnabled,
408 pdmR0DevHlp_VMState,
409 pdmR0DevHlp_VMSetError,
410 pdmR0DevHlp_VMSetErrorV,
411 pdmR0DevHlp_VMSetRuntimeError,
412 pdmR0DevHlp_VMSetRuntimeErrorV,
413 pdmR0DevHlp_PATMSetMMIOPatchInfo,
414 pdmR0DevHlp_GetVM,
415 pdmR0DevHlp_CanEmulateIoBlock,
416 pdmR0DevHlp_GetVMCPU,
417 pdmR0DevHlp_GetCurrentCpuId,
418 pdmR0DevHlp_TMTimeVirtGet,
419 pdmR0DevHlp_TMTimeVirtGetFreq,
420 pdmR0DevHlp_TMTimeVirtGetNano,
421 pdmR0DevHlp_DBGFTraceBuf,
422 NULL,
423 NULL,
424 NULL,
425 NULL,
426 NULL,
427 NULL,
428 NULL,
429 NULL,
430 NULL,
431 NULL,
432 PDM_DEVHLPR0_VERSION
433};
434
435/** @} */
436
437
438
439
440/** @name PIC Ring-0 Helpers
441 * @{
442 */
443
444/** @interface_method_impl{PDMPICHLPR0,pfnSetInterruptFF} */
445static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
446{
447 PDMDEV_ASSERT_DEVINS(pDevIns);
448 PVM pVM = pDevIns->Internal.s.pVMR0;
449 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
450 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
451 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
452}
453
454
455/** @interface_method_impl{PDMPICHLPR0,pfnClearInterruptFF} */
456static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
457{
458 PDMDEV_ASSERT_DEVINS(pDevIns);
459 PVM pVM = pDevIns->Internal.s.pVMR0;
460 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
461 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
462 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
463}
464
465
466/** @interface_method_impl{PDMPICHLPR0,pfnLock} */
467static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
468{
469 PDMDEV_ASSERT_DEVINS(pDevIns);
470 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
471}
472
473
474/** @interface_method_impl{PDMPICHLPR0,pfnUnlock} */
475static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns)
476{
477 PDMDEV_ASSERT_DEVINS(pDevIns);
478 pdmUnlock(pDevIns->Internal.s.pVMR0);
479}
480
481
482/**
483 * The Ring-0 PIC Helper Callbacks.
484 */
485extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp =
486{
487 PDM_PICHLPR0_VERSION,
488 pdmR0PicHlp_SetInterruptFF,
489 pdmR0PicHlp_ClearInterruptFF,
490 pdmR0PicHlp_Lock,
491 pdmR0PicHlp_Unlock,
492 PDM_PICHLPR0_VERSION
493};
494
495/** @} */
496
497
498/** @name I/O APIC Ring-0 Helpers
499 * @{
500 */
501
502/** @interface_method_impl{PDMIOAPICHLPR0,pfnApicBusDeliver} */
503static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
504 uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
505 uint8_t u8TriggerMode, uint32_t uTagSrc)
506{
507 PDMDEV_ASSERT_DEVINS(pDevIns);
508 PVM pVM = pDevIns->Internal.s.pVMR0;
509 LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
510 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
511 return APICBusDeliver(pVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
512}
513
514
515/** @interface_method_impl{PDMIOAPICHLPR0,pfnLock} */
516static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
517{
518 PDMDEV_ASSERT_DEVINS(pDevIns);
519 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
520}
521
522
523/** @interface_method_impl{PDMIOAPICHLPR0,pfnUnlock} */
524static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns)
525{
526 PDMDEV_ASSERT_DEVINS(pDevIns);
527 pdmUnlock(pDevIns->Internal.s.pVMR0);
528}
529
530
531/**
532 * The Ring-0 I/O APIC Helper Callbacks.
533 */
534extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp =
535{
536 PDM_IOAPICHLPR0_VERSION,
537 pdmR0IoApicHlp_ApicBusDeliver,
538 pdmR0IoApicHlp_Lock,
539 pdmR0IoApicHlp_Unlock,
540 PDM_IOAPICHLPR0_VERSION
541};
542
543/** @} */
544
545
546
547
548/** @name PCI Bus Ring-0 Helpers
549 * @{
550 */
551
552/** @interface_method_impl{PDMPCIHLPR0,pfnIsaSetIrq} */
553static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
554{
555 PDMDEV_ASSERT_DEVINS(pDevIns);
556 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
557 PVM pVM = pDevIns->Internal.s.pVMR0;
558
559 pdmLock(pVM);
560 pdmR0IsaSetIrq(pVM, iIrq, iLevel, uTagSrc);
561 pdmUnlock(pVM);
562}
563
564
565/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSetIrq} */
566static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
567{
568 PDMDEV_ASSERT_DEVINS(pDevIns);
569 Log4(("pdmR0PciHlp_IoApicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
570 PVM pVM = pDevIns->Internal.s.pVMR0;
571
572 if (pVM->pdm.s.IoApic.pDevInsR0)
573 pVM->pdm.s.IoApic.pfnSetIrqR0(pVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel, uTagSrc);
574 else if (pVM->pdm.s.IoApic.pDevInsR3)
575 {
576 /* queue for ring-3 execution. */
577 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
578 if (pTask)
579 {
580 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
581 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
582 pTask->u.IoApicSetIRQ.iIrq = iIrq;
583 pTask->u.IoApicSetIRQ.iLevel = iLevel;
584 pTask->u.IoApicSetIRQ.uTagSrc = uTagSrc;
585
586 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
587 }
588 else
589 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
590 }
591}
592
593
594/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSendMsi} */
595static DECLCALLBACK(void) pdmR0PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)
596{
597 PDMDEV_ASSERT_DEVINS(pDevIns);
598 Log4(("pdmR0PciHlp_IoApicSendMsi: GCPhys=%p uValue=%d uTagSrc=%#x\n", GCPhys, uValue, uTagSrc));
599 PVM pVM = pDevIns->Internal.s.pVMR0;
600 if (pVM->pdm.s.IoApic.pDevInsR0)
601 pVM->pdm.s.IoApic.pfnSendMsiR0(pVM->pdm.s.IoApic.pDevInsR0, GCPhys, uValue, uTagSrc);
602 else
603 AssertFatalMsgFailed(("Lazy bastards!"));
604}
605
606
607/** @interface_method_impl{PDMPCIHLPR0,pfnLock} */
608static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
609{
610 PDMDEV_ASSERT_DEVINS(pDevIns);
611 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
612}
613
614
615/** @interface_method_impl{PDMPCIHLPR0,pfnUnlock} */
616static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns)
617{
618 PDMDEV_ASSERT_DEVINS(pDevIns);
619 pdmUnlock(pDevIns->Internal.s.pVMR0);
620}
621
622
623/**
624 * The Ring-0 PCI Bus Helper Callbacks.
625 */
626extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp =
627{
628 PDM_PCIHLPR0_VERSION,
629 pdmR0PciHlp_IsaSetIrq,
630 pdmR0PciHlp_IoApicSetIrq,
631 pdmR0PciHlp_IoApicSendMsi,
632 pdmR0PciHlp_Lock,
633 pdmR0PciHlp_Unlock,
634 PDM_PCIHLPR0_VERSION, /* the end */
635};
636
637/** @} */
638
639
640
641
642/** @name HPET Ring-0 Helpers
643 * @{
644 */
645/* none */
646
647/**
648 * The Ring-0 HPET Helper Callbacks.
649 */
650extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp =
651{
652 PDM_HPETHLPR0_VERSION,
653 PDM_HPETHLPR0_VERSION, /* the end */
654};
655
656/** @} */
657
658
659/** @name Raw PCI Ring-0 Helpers
660 * @{
661 */
662/* none */
663
664/**
665 * The Ring-0 PCI raw Helper Callbacks.
666 */
667extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp =
668{
669 PDM_PCIRAWHLPR0_VERSION,
670 PDM_PCIRAWHLPR0_VERSION, /* the end */
671};
672
673/** @} */
674
675
676/** @name Ring-0 Context Driver Helpers
677 * @{
678 */
679
680/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetError} */
681static DECLCALLBACK(int) pdmR0DrvHlp_VMSetError(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
682{
683 PDMDRV_ASSERT_DRVINS(pDrvIns);
684 va_list args;
685 va_start(args, pszFormat);
686 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
687 va_end(args);
688 return rc;
689}
690
691
692/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetErrorV} */
693static DECLCALLBACK(int) pdmR0DrvHlp_VMSetErrorV(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
694{
695 PDMDRV_ASSERT_DRVINS(pDrvIns);
696 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
697 return rc;
698}
699
700
701/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetRuntimeError} */
702static DECLCALLBACK(int) pdmR0DrvHlp_VMSetRuntimeError(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId,
703 const char *pszFormat, ...)
704{
705 PDMDRV_ASSERT_DRVINS(pDrvIns);
706 va_list va;
707 va_start(va, pszFormat);
708 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
709 va_end(va);
710 return rc;
711}
712
713
714/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetRuntimeErrorV} */
715static DECLCALLBACK(int) pdmR0DrvHlp_VMSetRuntimeErrorV(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId,
716 const char *pszFormat, va_list va)
717{
718 PDMDRV_ASSERT_DRVINS(pDrvIns);
719 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
720 return rc;
721}
722
723
724/** @interface_method_impl{PDMDRVHLPR0,pfnAssertEMT} */
725static DECLCALLBACK(bool) pdmR0DrvHlp_AssertEMT(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
726{
727 PDMDRV_ASSERT_DRVINS(pDrvIns);
728 if (VM_IS_EMT(pDrvIns->Internal.s.pVMR0))
729 return true;
730
731 RTAssertMsg1Weak("AssertEMT", iLine, pszFile, pszFunction);
732 RTAssertPanic();
733 return false;
734}
735
736
737/** @interface_method_impl{PDMDRVHLPR0,pfnAssertOther} */
738static DECLCALLBACK(bool) pdmR0DrvHlp_AssertOther(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
739{
740 PDMDRV_ASSERT_DRVINS(pDrvIns);
741 if (!VM_IS_EMT(pDrvIns->Internal.s.pVMR0))
742 return true;
743
744 RTAssertMsg1Weak("AssertOther", iLine, pszFile, pszFunction);
745 RTAssertPanic();
746 return false;
747}
748
749
750/** @interface_method_impl{PDMDRVHLPR0,pfnFTSetCheckpoint} */
751static DECLCALLBACK(int) pdmR0DrvHlp_FTSetCheckpoint(PPDMDRVINS pDrvIns, FTMCHECKPOINTTYPE enmType)
752{
753 PDMDRV_ASSERT_DRVINS(pDrvIns);
754 return FTMSetCheckpoint(pDrvIns->Internal.s.pVMR0, enmType);
755}
756
757
758/**
759 * The Ring-0 Context Driver Helper Callbacks.
760 */
761extern DECLEXPORT(const PDMDRVHLPR0) g_pdmR0DrvHlp =
762{
763 PDM_DRVHLPRC_VERSION,
764 pdmR0DrvHlp_VMSetError,
765 pdmR0DrvHlp_VMSetErrorV,
766 pdmR0DrvHlp_VMSetRuntimeError,
767 pdmR0DrvHlp_VMSetRuntimeErrorV,
768 pdmR0DrvHlp_AssertEMT,
769 pdmR0DrvHlp_AssertOther,
770 pdmR0DrvHlp_FTSetCheckpoint,
771 PDM_DRVHLPRC_VERSION
772};
773
774/** @} */
775
776
777
778
779/**
780 * Sets an irq on the PIC and I/O APIC.
781 *
782 * @returns true if delivered, false if postponed.
783 * @param pVM The cross context VM structure.
784 * @param iIrq The irq.
785 * @param iLevel The new level.
786 * @param uTagSrc The IRQ tag and source.
787 *
788 * @remarks The caller holds the PDM lock.
789 */
790static bool pdmR0IsaSetIrq(PVM pVM, int iIrq, int iLevel, uint32_t uTagSrc)
791{
792 if (RT_LIKELY( ( pVM->pdm.s.IoApic.pDevInsR0
793 || !pVM->pdm.s.IoApic.pDevInsR3)
794 && ( pVM->pdm.s.Pic.pDevInsR0
795 || !pVM->pdm.s.Pic.pDevInsR3)))
796 {
797 if (pVM->pdm.s.Pic.pDevInsR0)
798 pVM->pdm.s.Pic.pfnSetIrqR0(pVM->pdm.s.Pic.pDevInsR0, iIrq, iLevel, uTagSrc);
799 if (pVM->pdm.s.IoApic.pDevInsR0)
800 pVM->pdm.s.IoApic.pfnSetIrqR0(pVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel, uTagSrc);
801 return true;
802 }
803
804 /* queue for ring-3 execution. */
805 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
806 AssertReturn(pTask, false);
807
808 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
809 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
810 pTask->u.IsaSetIRQ.iIrq = iIrq;
811 pTask->u.IsaSetIRQ.iLevel = iLevel;
812 pTask->u.IsaSetIRQ.uTagSrc = uTagSrc;
813
814 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
815 return false;
816}
817
818
819/**
820 * PDMDevHlpCallR0 helper.
821 *
822 * @returns See PFNPDMDEVREQHANDLERR0.
823 * @param pVM The cross context VM structure. (For validation.)
824 * @param pReq Pointer to the request buffer.
825 */
826VMMR0_INT_DECL(int) PDMR0DeviceCallReqHandler(PVM pVM, PPDMDEVICECALLREQHANDLERREQ pReq)
827{
828 /*
829 * Validate input and make the call.
830 */
831 AssertPtrReturn(pVM, VERR_INVALID_POINTER);
832 AssertPtrReturn(pReq, VERR_INVALID_POINTER);
833 AssertMsgReturn(pReq->Hdr.cbReq == sizeof(*pReq), ("%#x != %#x\n", pReq->Hdr.cbReq, sizeof(*pReq)), VERR_INVALID_PARAMETER);
834
835 PPDMDEVINS pDevIns = pReq->pDevInsR0;
836 AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
837 AssertReturn(pDevIns->Internal.s.pVMR0 == pVM, VERR_INVALID_PARAMETER);
838
839 PFNPDMDEVREQHANDLERR0 pfnReqHandlerR0 = pReq->pfnReqHandlerR0;
840 AssertPtrReturn(pfnReqHandlerR0, VERR_INVALID_POINTER);
841
842 return pfnReqHandlerR0(pDevIns, pReq->uOperation, pReq->u64Arg);
843}
844
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