VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp@ 37529

Last change on this file since 37529 was 37410, checked in by vboxsync, 14 years ago

VMM,SUPDrv: Created DBGFTrace.
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1/* $Id: PDMR0Device.cpp 37410 2011-06-10 15:11:40Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, R0 Device parts.
4 */
5
6/*
7 * Copyright (C) 2006-2011 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#include "PDMInternal.h"
24#include <VBox/vmm/pdm.h>
25#include <VBox/vmm/pgm.h>
26#include <VBox/vmm/mm.h>
27#include <VBox/vmm/vm.h>
28#include <VBox/vmm/vmm.h>
29#include <VBox/vmm/patm.h>
30#include <VBox/vmm/hwaccm.h>
31
32#include <VBox/log.h>
33#include <VBox/err.h>
34#include <VBox/vmm/gvmm.h>
35#include <iprt/asm.h>
36#include <iprt/assert.h>
37#include <iprt/string.h>
38
39
40/*******************************************************************************
41* Global Variables *
42*******************************************************************************/
43RT_C_DECLS_BEGIN
44extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp;
45extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp;
46extern DECLEXPORT(const PDMAPICHLPR0) g_pdmR0ApicHlp;
47extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp;
48extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp;
49extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp;
50extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp;
51extern DECLEXPORT(const PDMDRVHLPR0) g_pdmR0DrvHlp;
52RT_C_DECLS_END
53
54
55/*******************************************************************************
56* Internal Functions *
57*******************************************************************************/
58static void pdmR0IsaSetIrq(PVM pVM, int iIrq, int iLevel);
59static void pdmR0IoApicSetIrq(PVM pVM, int iIrq, int iLevel);
60static void pdmR0IoApicSendMsi(PVM pVM, RTGCPHYS GCAddr, uint32_t uValue);
61
62
63
64/** @name Ring-0 Device Helpers
65 * @{
66 */
67
68/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
69static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
70{
71 PDMDEV_ASSERT_DEVINS(pDevIns);
72 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
73
74 PVM pVM = pDevIns->Internal.s.pVMR0;
75 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR0;
76 PPDMPCIBUS pPciBus = pDevIns->Internal.s.pPciBusR0;
77 if ( pPciDev
78 && pPciBus
79 && pPciBus->pDevInsR0)
80 {
81 pdmLock(pVM);
82 pPciBus->pfnSetIrqR0(pPciBus->pDevInsR0, pPciDev, iIrq, iLevel);
83 pdmUnlock(pVM);
84 }
85 else
86 {
87 /* queue for ring-3 execution. */
88 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
89 if (pTask)
90 {
91 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
92 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
93 pTask->u.SetIRQ.iIrq = iIrq;
94 pTask->u.SetIRQ.iLevel = iLevel;
95
96 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
97 }
98 else
99 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
100 }
101
102 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: returns void\n", pDevIns, pDevIns->iInstance));
103}
104
105
106/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
107static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
108{
109 PDMDEV_ASSERT_DEVINS(pDevIns);
110 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
111
112 pdmR0IsaSetIrq(pDevIns->Internal.s.pVMR0, iIrq, iLevel);
113
114 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: returns void\n", pDevIns, pDevIns->iInstance));
115}
116
117
118/** @interface_method_impl{PDMDEVHLPR0,pfnPhysRead} */
119static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
120{
121 PDMDEV_ASSERT_DEVINS(pDevIns);
122 LogFlow(("pdmR0DevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
123 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
124
125 int rc = PGMPhysRead(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbRead);
126 AssertRC(rc); /** @todo track down the users for this bugger. */
127
128 Log(("pdmR0DevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, rc));
129 return rc;
130}
131
132
133/** @interface_method_impl{PDMDEVHLPR0,pfnPhysWrite} */
134static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
135{
136 PDMDEV_ASSERT_DEVINS(pDevIns);
137 LogFlow(("pdmR0DevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
138 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
139
140 int rc = PGMPhysWrite(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbWrite);
141 AssertRC(rc); /** @todo track down the users for this bugger. */
142
143 Log(("pdmR0DevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, rc));
144 return rc;
145}
146
147
148/** @interface_method_impl{PDMDEVHLPR0,pfnA20IsEnabled} */
149static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
150{
151 PDMDEV_ASSERT_DEVINS(pDevIns);
152 LogFlow(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
153
154 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pVMR0));
155
156 Log(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
157 return fEnabled;
158}
159
160
161/** @interface_method_impl{PDMDEVHLPR0,pfnVMState} */
162static DECLCALLBACK(VMSTATE) pdmR0DevHlp_VMState(PPDMDEVINS pDevIns)
163{
164 PDMDEV_ASSERT_DEVINS(pDevIns);
165
166 VMSTATE enmVMState = pDevIns->Internal.s.pVMR0->enmVMState;
167
168 LogFlow(("pdmR0DevHlp_VMState: caller=%p/%d: returns %d\n", pDevIns, pDevIns->iInstance, enmVMState));
169 return enmVMState;
170}
171
172
173/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetError} */
174static DECLCALLBACK(int) pdmR0DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
175{
176 PDMDEV_ASSERT_DEVINS(pDevIns);
177 va_list args;
178 va_start(args, pszFormat);
179 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
180 va_end(args);
181 return rc;
182}
183
184
185/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetErrorV} */
186static DECLCALLBACK(int) pdmR0DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
187{
188 PDMDEV_ASSERT_DEVINS(pDevIns);
189 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
190 return rc;
191}
192
193
194/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeError} */
195static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
196{
197 PDMDEV_ASSERT_DEVINS(pDevIns);
198 va_list va;
199 va_start(va, pszFormat);
200 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
201 va_end(va);
202 return rc;
203}
204
205
206/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeErrorV} */
207static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
208{
209 PDMDEV_ASSERT_DEVINS(pDevIns);
210 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
211 return rc;
212}
213
214
215/** @copydoc PDMDEVHLPR0::pdmR0DevHlp_PATMSetMMIOPatchInfo*/
216static DECLCALLBACK(int) pdmR0DevHlp_PATMSetMMIOPatchInfo(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPTR pCachedData)
217{
218 PDMDEV_ASSERT_DEVINS(pDevIns);
219 LogFlow(("pdmR0DevHlp_PATMSetMMIOPatchInfo: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
220
221 AssertFailed();
222
223/* return PATMSetMMIOPatchInfo(pDevIns->Internal.s.pVMR0, GCPhys, pCachedData); */
224 return VINF_SUCCESS;
225}
226
227
228/** @interface_method_impl{PDMDEVHLPR0,pfnGetVM} */
229static DECLCALLBACK(PVM) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns)
230{
231 PDMDEV_ASSERT_DEVINS(pDevIns);
232 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
233 return pDevIns->Internal.s.pVMR0;
234}
235
236
237/** @interface_method_impl{PDMDEVHLPR0,pfnCanEmulateIoBlock} */
238static DECLCALLBACK(bool) pdmR0DevHlp_CanEmulateIoBlock(PPDMDEVINS pDevIns)
239{
240 PDMDEV_ASSERT_DEVINS(pDevIns);
241 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
242 return HWACCMCanEmulateIoBlock(VMMGetCpu(pDevIns->Internal.s.pVMR0));
243}
244
245
246/** @interface_method_impl{PDMDEVHLPR0,pfnGetVMCPU} */
247static DECLCALLBACK(PVMCPU) pdmR0DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
248{
249 PDMDEV_ASSERT_DEVINS(pDevIns);
250 LogFlow(("pdmR0DevHlp_GetVMCPU: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
251 return VMMGetCpu(pDevIns->Internal.s.pVMR0);
252}
253
254
255/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGet} */
256static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
257{
258 PDMDEV_ASSERT_DEVINS(pDevIns);
259 LogFlow(("pdmR0DevHlp_TMTimeVirtGet: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
260 return TMVirtualGet(pDevIns->Internal.s.pVMR0);
261}
262
263
264/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetFreq} */
265static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
266{
267 PDMDEV_ASSERT_DEVINS(pDevIns);
268 LogFlow(("pdmR0DevHlp_TMTimeVirtGetFreq: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
269 return TMVirtualGetFreq(pDevIns->Internal.s.pVMR0);
270}
271
272
273/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetNano} */
274static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
275{
276 PDMDEV_ASSERT_DEVINS(pDevIns);
277 LogFlow(("pdmR0DevHlp_TMTimeVirtGetNano: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
278 return TMVirtualToNano(pDevIns->Internal.s.pVMR0, TMVirtualGet(pDevIns->Internal.s.pVMR0));
279}
280
281
282/** @interface_method_impl{PDMDEVHLPR0,pfnDBGFTraceBuf} */
283static DECLCALLBACK(RTTRACEBUF) pdmR0DevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
284{
285 PDMDEV_ASSERT_DEVINS(pDevIns);
286 RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pVMR0->hTraceBufR0;
287 LogFlow(("pdmR3DevHlp_DBGFTraceBuf: caller='%p'/%d: returns %p\n", pDevIns, pDevIns->iInstance, hTraceBuf));
288 return hTraceBuf;
289}
290
291
292/**
293 * The Ring-0 Device Helper Callbacks.
294 */
295extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp =
296{
297 PDM_DEVHLPR0_VERSION,
298 pdmR0DevHlp_PCISetIrq,
299 pdmR0DevHlp_ISASetIrq,
300 pdmR0DevHlp_PhysRead,
301 pdmR0DevHlp_PhysWrite,
302 pdmR0DevHlp_A20IsEnabled,
303 pdmR0DevHlp_VMState,
304 pdmR0DevHlp_VMSetError,
305 pdmR0DevHlp_VMSetErrorV,
306 pdmR0DevHlp_VMSetRuntimeError,
307 pdmR0DevHlp_VMSetRuntimeErrorV,
308 pdmR0DevHlp_PATMSetMMIOPatchInfo,
309 pdmR0DevHlp_GetVM,
310 pdmR0DevHlp_CanEmulateIoBlock,
311 pdmR0DevHlp_GetVMCPU,
312 pdmR0DevHlp_TMTimeVirtGet,
313 pdmR0DevHlp_TMTimeVirtGetFreq,
314 pdmR0DevHlp_TMTimeVirtGetNano,
315 pdmR0DevHlp_DBGFTraceBuf,
316 PDM_DEVHLPR0_VERSION
317};
318
319/** @} */
320
321
322
323
324/** @name PIC Ring-0 Helpers
325 * @{
326 */
327
328/** @interface_method_impl{PDMPICHLPR0,pfnSetInterruptFF} */
329static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
330{
331 PDMDEV_ASSERT_DEVINS(pDevIns);
332 PVM pVM = pDevIns->Internal.s.pVMR0;
333
334 if (pVM->pdm.s.Apic.pfnLocalInterruptR0)
335 {
336 LogFlow(("pdmR0PicHlp_SetInterruptFF: caller='%p'/%d: Setting local interrupt on LAPIC\n",
337 pDevIns, pDevIns->iInstance));
338 /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
339 pVM->pdm.s.Apic.pfnLocalInterruptR0(pVM->pdm.s.Apic.pDevInsR0, 0, 1);
340 return;
341 }
342
343 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
344
345 LogFlow(("pdmR0PicHlp_SetInterruptFF: caller=%p/%d: VMCPU_FF_INTERRUPT_PIC %d -> 1\n",
346 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
347
348 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
349}
350
351
352/** @interface_method_impl{PDMPICHLPR0,pfnClearInterruptFF} */
353static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
354{
355 PDMDEV_ASSERT_DEVINS(pDevIns);
356 PVM pVM = pDevIns->Internal.s.pVMR0;
357
358 if (pVM->pdm.s.Apic.pfnLocalInterruptR0)
359 {
360 /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
361 LogFlow(("pdmR0PicHlp_ClearInterruptFF: caller='%s'/%d: Clearing local interrupt on LAPIC\n",
362 pDevIns, pDevIns->iInstance));
363 /* Lower the LAPIC's LINT0 line instead of signaling the CPU directly. */
364 pVM->pdm.s.Apic.pfnLocalInterruptR0(pVM->pdm.s.Apic.pDevInsR0, 0, 0);
365 return;
366 }
367
368 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
369
370 LogFlow(("pdmR0PicHlp_ClearInterruptFF: caller=%p/%d: VMCPU_FF_INTERRUPT_PIC %d -> 0\n",
371 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
372
373 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
374}
375
376
377/** @interface_method_impl{PDMPICHLPR0,pfnLock} */
378static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
379{
380 PDMDEV_ASSERT_DEVINS(pDevIns);
381 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
382}
383
384
385/** @interface_method_impl{PDMPICHLPR0,pfnUnlock} */
386static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns)
387{
388 PDMDEV_ASSERT_DEVINS(pDevIns);
389 pdmUnlock(pDevIns->Internal.s.pVMR0);
390}
391
392
393/**
394 * The Ring-0 PIC Helper Callbacks.
395 */
396extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp =
397{
398 PDM_PICHLPR0_VERSION,
399 pdmR0PicHlp_SetInterruptFF,
400 pdmR0PicHlp_ClearInterruptFF,
401 pdmR0PicHlp_Lock,
402 pdmR0PicHlp_Unlock,
403 PDM_PICHLPR0_VERSION
404};
405
406/** @} */
407
408
409
410
411/** @name APIC Ring-0 Helpers
412 * @{
413 */
414
415/** @interface_method_impl{PDMAPICHLPR0,pfnSetInterruptFF} */
416static DECLCALLBACK(void) pdmR0ApicHlp_SetInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
417{
418 PDMDEV_ASSERT_DEVINS(pDevIns);
419 PVM pVM = pDevIns->Internal.s.pVMR0;
420 PVMCPU pVCpu = &pVM->aCpus[idCpu];
421
422 AssertReturnVoid(idCpu < pVM->cCpus);
423
424 LogFlow(("pdmR0ApicHlp_SetInterruptFF: CPU%d=caller=%p/%d: VM_FF_INTERRUPT %d -> 1 (CPU%d)\n",
425 VMMGetCpuId(pVM), pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_APIC), idCpu));
426
427 switch (enmType)
428 {
429 case PDMAPICIRQ_HARDWARE:
430 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC);
431 break;
432 case PDMAPICIRQ_NMI:
433 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI);
434 break;
435 case PDMAPICIRQ_SMI:
436 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_SMI);
437 break;
438 case PDMAPICIRQ_EXTINT:
439 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
440 break;
441 default:
442 AssertMsgFailed(("enmType=%d\n", enmType));
443 break;
444 }
445
446 /* We need to wait up the target CPU. */
447 if (VMMGetCpuId(pVM) != idCpu)
448 {
449 switch (VMCPU_GET_STATE(pVCpu))
450 {
451 case VMCPUSTATE_STARTED_EXEC:
452 GVMMR0SchedPokeEx(pVM, pVCpu->idCpu, false /* don't take the used lock */);
453 break;
454
455 case VMCPUSTATE_STARTED_HALTED:
456 GVMMR0SchedWakeUpEx(pVM, pVCpu->idCpu, false /* don't take the used lock */);
457 break;
458
459 default:
460 break; /* nothing to do in other states. */
461 }
462 }
463}
464
465
466/** @interface_method_impl{PDMAPICHLPR0,pfnClearInterruptFF} */
467static DECLCALLBACK(void) pdmR0ApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
468{
469 PDMDEV_ASSERT_DEVINS(pDevIns);
470 PVM pVM = pDevIns->Internal.s.pVMR0;
471 PVMCPU pVCpu = &pVM->aCpus[idCpu];
472
473 AssertReturnVoid(idCpu < pVM->cCpus);
474
475 LogFlow(("pdmR0ApicHlp_ClearInterruptFF: caller=%p/%d: VM_FF_INTERRUPT %d -> 0\n",
476 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_APIC)));
477
478 /* Note: NMI/SMI can't be cleared. */
479 switch (enmType)
480 {
481 case PDMAPICIRQ_HARDWARE:
482 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
483 break;
484 case PDMAPICIRQ_EXTINT:
485 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
486 break;
487 default:
488 AssertMsgFailed(("enmType=%d\n", enmType));
489 break;
490 }
491}
492
493
494/** @interface_method_impl{PDMAPICHLPR0,pfnChangeFeature} */
495static DECLCALLBACK(void) pdmR0ApicHlp_ChangeFeature(PPDMDEVINS pDevIns, PDMAPICVERSION enmVersion)
496{
497 PDMDEV_ASSERT_DEVINS(pDevIns);
498 LogFlow(("pdmR0ApicHlp_ChangeFeature: caller=%p/%d: version=%d\n", pDevIns, pDevIns->iInstance, (int)enmVersion));
499 switch (enmVersion)
500 {
501 case PDMAPICVERSION_NONE:
502 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
503 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
504 break;
505 case PDMAPICVERSION_APIC:
506 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
507 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
508 break;
509 case PDMAPICVERSION_X2APIC:
510 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
511 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
512 break;
513 default:
514 AssertMsgFailed(("Unknown APIC version: %d\n", (int)enmVersion));
515 }
516}
517
518
519/** @interface_method_impl{PDMAPICHLPR0,pfnLock} */
520static DECLCALLBACK(int) pdmR0ApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
521{
522 PDMDEV_ASSERT_DEVINS(pDevIns);
523 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
524}
525
526
527/** @interface_method_impl{PDMAPICHLPR0,pfnUnlock} */
528static DECLCALLBACK(void) pdmR0ApicHlp_Unlock(PPDMDEVINS pDevIns)
529{
530 PDMDEV_ASSERT_DEVINS(pDevIns);
531 pdmUnlock(pDevIns->Internal.s.pVMR0);
532}
533
534
535/** @interface_method_impl{PDMAPICHLPR0,pfnGetCpuId} */
536static DECLCALLBACK(VMCPUID) pdmR0ApicHlp_GetCpuId(PPDMDEVINS pDevIns)
537{
538 PDMDEV_ASSERT_DEVINS(pDevIns);
539 return VMMGetCpuId(pDevIns->Internal.s.pVMR0);
540}
541
542
543/**
544 * The Ring-0 APIC Helper Callbacks.
545 */
546extern DECLEXPORT(const PDMAPICHLPR0) g_pdmR0ApicHlp =
547{
548 PDM_APICHLPR0_VERSION,
549 pdmR0ApicHlp_SetInterruptFF,
550 pdmR0ApicHlp_ClearInterruptFF,
551 pdmR0ApicHlp_ChangeFeature,
552 pdmR0ApicHlp_Lock,
553 pdmR0ApicHlp_Unlock,
554 pdmR0ApicHlp_GetCpuId,
555 PDM_APICHLPR0_VERSION
556};
557
558/** @} */
559
560
561
562
563/** @name I/O APIC Ring-0 Helpers
564 * @{
565 */
566
567/** @interface_method_impl{PDMIOAPICHLPR0,pfnApicBusDeliver} */
568static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
569 uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode)
570{
571 PDMDEV_ASSERT_DEVINS(pDevIns);
572 PVM pVM = pDevIns->Internal.s.pVMR0;
573 LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 iVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8\n",
574 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
575 Assert(pVM->pdm.s.Apic.pDevInsR0);
576 if (pVM->pdm.s.Apic.pfnBusDeliverR0)
577 return pVM->pdm.s.Apic.pfnBusDeliverR0(pVM->pdm.s.Apic.pDevInsR0, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
578 return VINF_SUCCESS;
579}
580
581
582/** @interface_method_impl{PDMIOAPICHLPR0,pfnLock} */
583static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
584{
585 PDMDEV_ASSERT_DEVINS(pDevIns);
586 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
587}
588
589
590/** @interface_method_impl{PDMIOAPICHLPR0,pfnUnlock} */
591static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns)
592{
593 PDMDEV_ASSERT_DEVINS(pDevIns);
594 pdmUnlock(pDevIns->Internal.s.pVMR0);
595}
596
597
598/**
599 * The Ring-0 I/O APIC Helper Callbacks.
600 */
601extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp =
602{
603 PDM_IOAPICHLPR0_VERSION,
604 pdmR0IoApicHlp_ApicBusDeliver,
605 pdmR0IoApicHlp_Lock,
606 pdmR0IoApicHlp_Unlock,
607 PDM_IOAPICHLPR0_VERSION
608};
609
610/** @} */
611
612
613
614
615/** @name PCI Bus Ring-0 Helpers
616 * @{
617 */
618
619/** @interface_method_impl{PDMPCIHLPR0,pfnIsaSetIrq} */
620static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
621{
622 PDMDEV_ASSERT_DEVINS(pDevIns);
623 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
624 pdmR0IsaSetIrq(pDevIns->Internal.s.pVMR0, iIrq, iLevel);
625}
626
627
628/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSetIrq} */
629static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
630{
631 PDMDEV_ASSERT_DEVINS(pDevIns);
632 Log4(("pdmR0PciHlp_IoApicSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
633 pdmR0IoApicSetIrq(pDevIns->Internal.s.pVMR0, iIrq, iLevel);
634}
635
636/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSendMsi} */
637static DECLCALLBACK(void) pdmR0PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue)
638{
639 PDMDEV_ASSERT_DEVINS(pDevIns);
640 Log4(("pdmR0PciHlp_IoApicSendMsi: Address=%p Value=%d\n", GCAddr, uValue));
641 pdmR0IoApicSendMsi(pDevIns->Internal.s.pVMR0, GCAddr, uValue);
642}
643
644/** @interface_method_impl{PDMPCIHLPR0,pfnLock} */
645static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
646{
647 PDMDEV_ASSERT_DEVINS(pDevIns);
648 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
649}
650
651
652/** @interface_method_impl{PDMPCIHLPR0,pfnUnlock} */
653static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns)
654{
655 PDMDEV_ASSERT_DEVINS(pDevIns);
656 pdmUnlock(pDevIns->Internal.s.pVMR0);
657}
658
659
660/**
661 * The Ring-0 PCI Bus Helper Callbacks.
662 */
663extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp =
664{
665 PDM_PCIHLPR0_VERSION,
666 pdmR0PciHlp_IsaSetIrq,
667 pdmR0PciHlp_IoApicSetIrq,
668 pdmR0PciHlp_IoApicSendMsi,
669 pdmR0PciHlp_Lock,
670 pdmR0PciHlp_Unlock,
671 PDM_PCIHLPR0_VERSION, /* the end */
672};
673
674/** @} */
675
676
677
678
679/** @name HPET Ring-0 Helpers
680 * @{
681 */
682/* none */
683
684/**
685 * The Ring-0 HPET Helper Callbacks.
686 */
687extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp =
688{
689 PDM_HPETHLPR0_VERSION,
690 PDM_HPETHLPR0_VERSION, /* the end */
691};
692
693/** @} */
694
695
696/** @name Raw PCI Ring-0 Helpers
697 * @{
698 */
699/* none */
700
701/**
702 * The Ring-0 PCI raw Helper Callbacks.
703 */
704extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp =
705{
706 PDM_PCIRAWHLPR0_VERSION,
707 PDM_PCIRAWHLPR0_VERSION, /* the end */
708};
709
710/** @} */
711
712
713/** @name Ring-0 Context Driver Helpers
714 * @{
715 */
716
717/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetError} */
718static DECLCALLBACK(int) pdmR0DrvHlp_VMSetError(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
719{
720 PDMDRV_ASSERT_DRVINS(pDrvIns);
721 va_list args;
722 va_start(args, pszFormat);
723 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
724 va_end(args);
725 return rc;
726}
727
728
729/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetErrorV} */
730static DECLCALLBACK(int) pdmR0DrvHlp_VMSetErrorV(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
731{
732 PDMDRV_ASSERT_DRVINS(pDrvIns);
733 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
734 return rc;
735}
736
737
738/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetRuntimeError} */
739static DECLCALLBACK(int) pdmR0DrvHlp_VMSetRuntimeError(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
740{
741 PDMDRV_ASSERT_DRVINS(pDrvIns);
742 va_list va;
743 va_start(va, pszFormat);
744 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
745 va_end(va);
746 return rc;
747}
748
749
750/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetErrorV} */
751static DECLCALLBACK(int) pdmR0DrvHlp_VMSetRuntimeErrorV(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
752{
753 PDMDRV_ASSERT_DRVINS(pDrvIns);
754 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
755 return rc;
756}
757
758
759/** @interface_method_impl{PDMDRVHLPR0,pfnAssertEMT} */
760static DECLCALLBACK(bool) pdmR0DrvHlp_AssertEMT(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
761{
762 PDMDRV_ASSERT_DRVINS(pDrvIns);
763 if (VM_IS_EMT(pDrvIns->Internal.s.pVMR0))
764 return true;
765
766 RTAssertMsg1Weak("AssertEMT", iLine, pszFile, pszFunction);
767 RTAssertPanic();
768 return false;
769}
770
771
772/** @interface_method_impl{PDMDRVHLPR0,pfnAssertOther} */
773static DECLCALLBACK(bool) pdmR0DrvHlp_AssertOther(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
774{
775 PDMDRV_ASSERT_DRVINS(pDrvIns);
776 if (!VM_IS_EMT(pDrvIns->Internal.s.pVMR0))
777 return true;
778
779 RTAssertMsg1Weak("AssertOther", iLine, pszFile, pszFunction);
780 RTAssertPanic();
781 return false;
782}
783
784
785/** @interface_method_impl{PDMDRVHLPR0,pfnFTSetCheckpoint} */
786static DECLCALLBACK(int) pdmR0DrvHlp_FTSetCheckpoint(PPDMDRVINS pDrvIns, FTMCHECKPOINTTYPE enmType)
787{
788 PDMDRV_ASSERT_DRVINS(pDrvIns);
789 return FTMSetCheckpoint(pDrvIns->Internal.s.pVMR0, enmType);
790}
791
792
793/**
794 * The Ring-0 Context Driver Helper Callbacks.
795 */
796extern DECLEXPORT(const PDMDRVHLPR0) g_pdmR0DrvHlp =
797{
798 PDM_DRVHLPRC_VERSION,
799 pdmR0DrvHlp_VMSetError,
800 pdmR0DrvHlp_VMSetErrorV,
801 pdmR0DrvHlp_VMSetRuntimeError,
802 pdmR0DrvHlp_VMSetRuntimeErrorV,
803 pdmR0DrvHlp_AssertEMT,
804 pdmR0DrvHlp_AssertOther,
805 pdmR0DrvHlp_FTSetCheckpoint,
806 PDM_DRVHLPRC_VERSION
807};
808
809/** @} */
810
811
812
813
814/**
815 * Sets an irq on the I/O APIC.
816 *
817 * @param pVM The VM handle.
818 * @param iIrq The irq.
819 * @param iLevel The new level.
820 */
821static void pdmR0IsaSetIrq(PVM pVM, int iIrq, int iLevel)
822{
823 if ( ( pVM->pdm.s.IoApic.pDevInsR0
824 || !pVM->pdm.s.IoApic.pDevInsR3)
825 && ( pVM->pdm.s.Pic.pDevInsR0
826 || !pVM->pdm.s.Pic.pDevInsR3))
827 {
828 pdmLock(pVM);
829 if (pVM->pdm.s.Pic.pDevInsR0)
830 pVM->pdm.s.Pic.pfnSetIrqR0(pVM->pdm.s.Pic.pDevInsR0, iIrq, iLevel);
831 if (pVM->pdm.s.IoApic.pDevInsR0)
832 pVM->pdm.s.IoApic.pfnSetIrqR0(pVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel);
833 pdmUnlock(pVM);
834 }
835 else
836 {
837 /* queue for ring-3 execution. */
838 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
839 if (pTask)
840 {
841 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
842 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
843 pTask->u.SetIRQ.iIrq = iIrq;
844 pTask->u.SetIRQ.iLevel = iLevel;
845
846 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
847 }
848 else
849 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
850 }
851}
852
853
854/**
855 * Sets an irq on the I/O APIC.
856 *
857 * @param pVM The VM handle.
858 * @param iIrq The irq.
859 * @param iLevel The new level.
860 */
861static void pdmR0IoApicSetIrq(PVM pVM, int iIrq, int iLevel)
862{
863 if (pVM->pdm.s.IoApic.pDevInsR0)
864 {
865 pdmLock(pVM);
866 pVM->pdm.s.IoApic.pfnSetIrqR0(pVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel);
867 pdmUnlock(pVM);
868 }
869 else if (pVM->pdm.s.IoApic.pDevInsR3)
870 {
871 /* queue for ring-3 execution. */
872 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
873 if (pTask)
874 {
875 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
876 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
877 pTask->u.SetIRQ.iIrq = iIrq;
878 pTask->u.SetIRQ.iLevel = iLevel;
879
880 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
881 }
882 else
883 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
884 }
885}
886
887
888/**
889 * PDMDevHlpCallR0 helper.
890 *
891 * @returns See PFNPDMDEVREQHANDLERR0.
892 * @param pVM The VM handle (for validation).
893 * @param pReq The request buffer.
894 */
895VMMR0_INT_DECL(int) PDMR0DeviceCallReqHandler(PVM pVM, PPDMDEVICECALLREQHANDLERREQ pReq)
896{
897 /*
898 * Validate input and make the call.
899 */
900 AssertPtrReturn(pVM, VERR_INVALID_POINTER);
901 AssertPtrReturn(pReq, VERR_INVALID_POINTER);
902 AssertMsgReturn(pReq->Hdr.cbReq == sizeof(*pReq), ("%#x != %#x\n", pReq->Hdr.cbReq, sizeof(*pReq)), VERR_INVALID_PARAMETER);
903
904 PPDMDEVINS pDevIns = pReq->pDevInsR0;
905 AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
906 AssertReturn(pDevIns->Internal.s.pVMR0 == pVM, VERR_INVALID_PARAMETER);
907
908 PFNPDMDEVREQHANDLERR0 pfnReqHandlerR0 = pReq->pfnReqHandlerR0;
909 AssertPtrReturn(pfnReqHandlerR0, VERR_INVALID_POINTER);
910
911 return pfnReqHandlerR0(pDevIns, pReq->uOperation, pReq->u64Arg);
912}
913
914/**
915 * Sends an MSI to I/O APIC.
916 *
917 * @param pVM The VM handle.
918 * @param GCAddr Address of the message.
919 * @param uValue Value of the message.
920 */
921static void pdmR0IoApicSendMsi(PVM pVM, RTGCPHYS GCAddr, uint32_t uValue)
922{
923 if (pVM->pdm.s.IoApic.pDevInsR0)
924 {
925 pdmLock(pVM);
926 pVM->pdm.s.IoApic.pfnSendMsiR0(pVM->pdm.s.IoApic.pDevInsR0, GCAddr, uValue);
927 pdmUnlock(pVM);
928 }
929}
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