VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp@ 35676

Last change on this file since 35676 was 35676, checked in by vboxsync, 14 years ago

Main, VMM: PCI passthrough work
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1/* $Id: PDMR0Device.cpp 35676 2011-01-24 14:24:34Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, R0 Device parts.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#include "PDMInternal.h"
24#include <VBox/vmm/pdm.h>
25#include <VBox/vmm/pgm.h>
26#include <VBox/vmm/mm.h>
27#include <VBox/vmm/vm.h>
28#include <VBox/vmm/vmm.h>
29#include <VBox/vmm/patm.h>
30#include <VBox/vmm/hwaccm.h>
31
32#include <VBox/log.h>
33#include <VBox/err.h>
34#include <VBox/vmm/gvmm.h>
35#include <iprt/asm.h>
36#include <iprt/assert.h>
37#include <iprt/string.h>
38
39
40/*******************************************************************************
41* Global Variables *
42*******************************************************************************/
43RT_C_DECLS_BEGIN
44extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp;
45extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp;
46extern DECLEXPORT(const PDMAPICHLPR0) g_pdmR0ApicHlp;
47extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp;
48extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp;
49extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp;
50extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp;
51extern DECLEXPORT(const PDMDRVHLPR0) g_pdmR0DrvHlp;
52RT_C_DECLS_END
53
54
55/*******************************************************************************
56* Internal Functions *
57*******************************************************************************/
58static void pdmR0IsaSetIrq(PVM pVM, int iIrq, int iLevel);
59static void pdmR0IoApicSetIrq(PVM pVM, int iIrq, int iLevel);
60static void pdmR0IoApicSendMsi(PVM pVM, RTGCPHYS GCAddr, uint32_t uValue);
61
62
63
64/** @name Ring-0 Device Helpers
65 * @{
66 */
67
68/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
69static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
70{
71 PDMDEV_ASSERT_DEVINS(pDevIns);
72 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
73
74 PVM pVM = pDevIns->Internal.s.pVMR0;
75 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR0;
76 PPDMPCIBUS pPciBus = pDevIns->Internal.s.pPciBusR0;
77 if ( pPciDev
78 && pPciBus
79 && pPciBus->pDevInsR0)
80 {
81 pdmLock(pVM);
82 pPciBus->pfnSetIrqR0(pPciBus->pDevInsR0, pPciDev, iIrq, iLevel);
83 pdmUnlock(pVM);
84 }
85 else
86 {
87 /* queue for ring-3 execution. */
88 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
89 if (pTask)
90 {
91 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
92 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
93 pTask->u.SetIRQ.iIrq = iIrq;
94 pTask->u.SetIRQ.iLevel = iLevel;
95
96 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
97 }
98 else
99 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
100 }
101
102 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: returns void\n", pDevIns, pDevIns->iInstance));
103}
104
105
106/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
107static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
108{
109 PDMDEV_ASSERT_DEVINS(pDevIns);
110 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
111
112 pdmR0IsaSetIrq(pDevIns->Internal.s.pVMR0, iIrq, iLevel);
113
114 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: returns void\n", pDevIns, pDevIns->iInstance));
115}
116
117
118/** @interface_method_impl{PDMDEVHLPR0,pfnPhysRead} */
119static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
120{
121 PDMDEV_ASSERT_DEVINS(pDevIns);
122 LogFlow(("pdmR0DevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
123 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
124
125 int rc = PGMPhysRead(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbRead);
126 AssertRC(rc); /** @todo track down the users for this bugger. */
127
128 Log(("pdmR0DevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, rc));
129 return rc;
130}
131
132
133/** @interface_method_impl{PDMDEVHLPR0,pfnPhysWrite} */
134static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
135{
136 PDMDEV_ASSERT_DEVINS(pDevIns);
137 LogFlow(("pdmR0DevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
138 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
139
140 int rc = PGMPhysWrite(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbWrite);
141 AssertRC(rc); /** @todo track down the users for this bugger. */
142
143 Log(("pdmR0DevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, rc));
144 return rc;
145}
146
147
148/** @interface_method_impl{PDMDEVHLPR0,pfnA20IsEnabled} */
149static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
150{
151 PDMDEV_ASSERT_DEVINS(pDevIns);
152 LogFlow(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
153
154 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pVMR0));
155
156 Log(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
157 return fEnabled;
158}
159
160
161/** @interface_method_impl{PDMDEVHLPR0,pfnVMState} */
162static DECLCALLBACK(VMSTATE) pdmR0DevHlp_VMState(PPDMDEVINS pDevIns)
163{
164 PDMDEV_ASSERT_DEVINS(pDevIns);
165
166 VMSTATE enmVMState = pDevIns->Internal.s.pVMR0->enmVMState;
167
168 LogFlow(("pdmR0DevHlp_VMState: caller=%p/%d: returns %d\n", pDevIns, pDevIns->iInstance, enmVMState));
169 return enmVMState;
170}
171
172
173/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetError} */
174static DECLCALLBACK(int) pdmR0DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
175{
176 PDMDEV_ASSERT_DEVINS(pDevIns);
177 va_list args;
178 va_start(args, pszFormat);
179 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
180 va_end(args);
181 return rc;
182}
183
184
185/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetErrorV} */
186static DECLCALLBACK(int) pdmR0DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
187{
188 PDMDEV_ASSERT_DEVINS(pDevIns);
189 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
190 return rc;
191}
192
193
194/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeError} */
195static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
196{
197 PDMDEV_ASSERT_DEVINS(pDevIns);
198 va_list va;
199 va_start(va, pszFormat);
200 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
201 va_end(va);
202 return rc;
203}
204
205
206/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeErrorV} */
207static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
208{
209 PDMDEV_ASSERT_DEVINS(pDevIns);
210 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
211 return rc;
212}
213
214
215/** @copydoc PDMDEVHLPR0::pdmR0DevHlp_PATMSetMMIOPatchInfo*/
216static DECLCALLBACK(int) pdmR0DevHlp_PATMSetMMIOPatchInfo(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPTR pCachedData)
217{
218 PDMDEV_ASSERT_DEVINS(pDevIns);
219 LogFlow(("pdmR0DevHlp_PATMSetMMIOPatchInfo: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
220
221 AssertFailed();
222
223/* return PATMSetMMIOPatchInfo(pDevIns->Internal.s.pVMR0, GCPhys, pCachedData); */
224 return VINF_SUCCESS;
225}
226
227
228/** @interface_method_impl{PDMDEVHLPR0,pfnGetVM} */
229static DECLCALLBACK(PVM) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns)
230{
231 PDMDEV_ASSERT_DEVINS(pDevIns);
232 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
233 return pDevIns->Internal.s.pVMR0;
234}
235
236
237/** @interface_method_impl{PDMDEVHLPR0,pfnCanEmulateIoBlock} */
238static DECLCALLBACK(bool) pdmR0DevHlp_CanEmulateIoBlock(PPDMDEVINS pDevIns)
239{
240 PDMDEV_ASSERT_DEVINS(pDevIns);
241 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
242 return HWACCMCanEmulateIoBlock(VMMGetCpu(pDevIns->Internal.s.pVMR0));
243}
244
245
246/** @interface_method_impl{PDMDEVHLPR0,pfnGetVMCPU} */
247static DECLCALLBACK(PVMCPU) pdmR0DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
248{
249 PDMDEV_ASSERT_DEVINS(pDevIns);
250 LogFlow(("pdmR0DevHlp_GetVMCPU: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
251 return VMMGetCpu(pDevIns->Internal.s.pVMR0);
252}
253
254
255/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGet} */
256static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
257{
258 PDMDEV_ASSERT_DEVINS(pDevIns);
259 LogFlow(("pdmR0DevHlp_TMTimeVirtGet: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
260 return TMVirtualGet(pDevIns->Internal.s.pVMR0);
261}
262
263
264/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetFreq} */
265static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
266{
267 PDMDEV_ASSERT_DEVINS(pDevIns);
268 LogFlow(("pdmR0DevHlp_TMTimeVirtGetFreq: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
269 return TMVirtualGetFreq(pDevIns->Internal.s.pVMR0);
270}
271
272
273/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetNano} */
274static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
275{
276 PDMDEV_ASSERT_DEVINS(pDevIns);
277 LogFlow(("pdmR0DevHlp_TMTimeVirtGetNano: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
278 return TMVirtualToNano(pDevIns->Internal.s.pVMR0, TMVirtualGet(pDevIns->Internal.s.pVMR0));
279}
280
281
282/**
283 * The Ring-0 Device Helper Callbacks.
284 */
285extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp =
286{
287 PDM_DEVHLPR0_VERSION,
288 pdmR0DevHlp_PCISetIrq,
289 pdmR0DevHlp_ISASetIrq,
290 pdmR0DevHlp_PhysRead,
291 pdmR0DevHlp_PhysWrite,
292 pdmR0DevHlp_A20IsEnabled,
293 pdmR0DevHlp_VMState,
294 pdmR0DevHlp_VMSetError,
295 pdmR0DevHlp_VMSetErrorV,
296 pdmR0DevHlp_VMSetRuntimeError,
297 pdmR0DevHlp_VMSetRuntimeErrorV,
298 pdmR0DevHlp_PATMSetMMIOPatchInfo,
299 pdmR0DevHlp_GetVM,
300 pdmR0DevHlp_CanEmulateIoBlock,
301 pdmR0DevHlp_GetVMCPU,
302 pdmR0DevHlp_TMTimeVirtGet,
303 pdmR0DevHlp_TMTimeVirtGetFreq,
304 pdmR0DevHlp_TMTimeVirtGetNano,
305 PDM_DEVHLPR0_VERSION
306};
307
308/** @} */
309
310
311
312
313/** @name PIC Ring-0 Helpers
314 * @{
315 */
316
317/** @interface_method_impl{PDMPICHLPR0,pfnSetInterruptFF} */
318static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
319{
320 PDMDEV_ASSERT_DEVINS(pDevIns);
321 PVM pVM = pDevIns->Internal.s.pVMR0;
322
323 if (pVM->pdm.s.Apic.pfnLocalInterruptR0)
324 {
325 LogFlow(("pdmR0PicHlp_SetInterruptFF: caller='%p'/%d: Setting local interrupt on LAPIC\n",
326 pDevIns, pDevIns->iInstance));
327 /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
328 pVM->pdm.s.Apic.pfnLocalInterruptR0(pVM->pdm.s.Apic.pDevInsR0, 0, 1);
329 return;
330 }
331
332 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
333
334 LogFlow(("pdmR0PicHlp_SetInterruptFF: caller=%p/%d: VMCPU_FF_INTERRUPT_PIC %d -> 1\n",
335 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
336
337 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
338}
339
340
341/** @interface_method_impl{PDMPICHLPR0,pfnClearInterruptFF} */
342static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
343{
344 PDMDEV_ASSERT_DEVINS(pDevIns);
345 PVM pVM = pDevIns->Internal.s.pVMR0;
346
347 if (pVM->pdm.s.Apic.pfnLocalInterruptR0)
348 {
349 /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
350 LogFlow(("pdmR0PicHlp_ClearInterruptFF: caller='%s'/%d: Clearing local interrupt on LAPIC\n",
351 pDevIns, pDevIns->iInstance));
352 /* Lower the LAPIC's LINT0 line instead of signaling the CPU directly. */
353 pVM->pdm.s.Apic.pfnLocalInterruptR0(pVM->pdm.s.Apic.pDevInsR0, 0, 0);
354 return;
355 }
356
357 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
358
359 LogFlow(("pdmR0PicHlp_ClearInterruptFF: caller=%p/%d: VMCPU_FF_INTERRUPT_PIC %d -> 0\n",
360 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
361
362 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
363}
364
365
366/** @interface_method_impl{PDMPICHLPR0,pfnLock} */
367static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
368{
369 PDMDEV_ASSERT_DEVINS(pDevIns);
370 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
371}
372
373
374/** @interface_method_impl{PDMPICHLPR0,pfnUnlock} */
375static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns)
376{
377 PDMDEV_ASSERT_DEVINS(pDevIns);
378 pdmUnlock(pDevIns->Internal.s.pVMR0);
379}
380
381
382/**
383 * The Ring-0 PIC Helper Callbacks.
384 */
385extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp =
386{
387 PDM_PICHLPR0_VERSION,
388 pdmR0PicHlp_SetInterruptFF,
389 pdmR0PicHlp_ClearInterruptFF,
390 pdmR0PicHlp_Lock,
391 pdmR0PicHlp_Unlock,
392 PDM_PICHLPR0_VERSION
393};
394
395/** @} */
396
397
398
399
400/** @name APIC Ring-0 Helpers
401 * @{
402 */
403
404/** @interface_method_impl{PDMAPICHLPR0,pfnSetInterruptFF} */
405static DECLCALLBACK(void) pdmR0ApicHlp_SetInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
406{
407 PDMDEV_ASSERT_DEVINS(pDevIns);
408 PVM pVM = pDevIns->Internal.s.pVMR0;
409 PVMCPU pVCpu = &pVM->aCpus[idCpu];
410
411 AssertReturnVoid(idCpu < pVM->cCpus);
412
413 LogFlow(("pdmR0ApicHlp_SetInterruptFF: CPU%d=caller=%p/%d: VM_FF_INTERRUPT %d -> 1 (CPU%d)\n",
414 VMMGetCpuId(pVM), pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_APIC), idCpu));
415
416 switch (enmType)
417 {
418 case PDMAPICIRQ_HARDWARE:
419 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC);
420 break;
421 case PDMAPICIRQ_NMI:
422 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI);
423 break;
424 case PDMAPICIRQ_SMI:
425 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_SMI);
426 break;
427 case PDMAPICIRQ_EXTINT:
428 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
429 break;
430 default:
431 AssertMsgFailed(("enmType=%d\n", enmType));
432 break;
433 }
434
435 /* We need to wait up the target CPU. */
436 if (VMMGetCpuId(pVM) != idCpu)
437 {
438 switch (VMCPU_GET_STATE(pVCpu))
439 {
440 case VMCPUSTATE_STARTED_EXEC:
441 GVMMR0SchedPokeEx(pVM, pVCpu->idCpu, false /* don't take the used lock */);
442 break;
443
444 case VMCPUSTATE_STARTED_HALTED:
445 GVMMR0SchedWakeUpEx(pVM, pVCpu->idCpu, false /* don't take the used lock */);
446 break;
447
448 default:
449 break; /* nothing to do in other states. */
450 }
451 }
452}
453
454
455/** @interface_method_impl{PDMAPICHLPR0,pfnClearInterruptFF} */
456static DECLCALLBACK(void) pdmR0ApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
457{
458 PDMDEV_ASSERT_DEVINS(pDevIns);
459 PVM pVM = pDevIns->Internal.s.pVMR0;
460 PVMCPU pVCpu = &pVM->aCpus[idCpu];
461
462 AssertReturnVoid(idCpu < pVM->cCpus);
463
464 LogFlow(("pdmR0ApicHlp_ClearInterruptFF: caller=%p/%d: VM_FF_INTERRUPT %d -> 0\n",
465 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_APIC)));
466
467 /* Note: NMI/SMI can't be cleared. */
468 switch (enmType)
469 {
470 case PDMAPICIRQ_HARDWARE:
471 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
472 break;
473 case PDMAPICIRQ_EXTINT:
474 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
475 break;
476 default:
477 AssertMsgFailed(("enmType=%d\n", enmType));
478 break;
479 }
480}
481
482
483/** @interface_method_impl{PDMAPICHLPR0,pfnChangeFeature} */
484static DECLCALLBACK(void) pdmR0ApicHlp_ChangeFeature(PPDMDEVINS pDevIns, PDMAPICVERSION enmVersion)
485{
486 PDMDEV_ASSERT_DEVINS(pDevIns);
487 LogFlow(("pdmR0ApicHlp_ChangeFeature: caller=%p/%d: version=%d\n", pDevIns, pDevIns->iInstance, (int)enmVersion));
488 switch (enmVersion)
489 {
490 case PDMAPICVERSION_NONE:
491 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
492 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
493 break;
494 case PDMAPICVERSION_APIC:
495 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
496 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
497 break;
498 case PDMAPICVERSION_X2APIC:
499 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
500 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
501 break;
502 default:
503 AssertMsgFailed(("Unknown APIC version: %d\n", (int)enmVersion));
504 }
505}
506
507
508/** @interface_method_impl{PDMAPICHLPR0,pfnLock} */
509static DECLCALLBACK(int) pdmR0ApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
510{
511 PDMDEV_ASSERT_DEVINS(pDevIns);
512 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
513}
514
515
516/** @interface_method_impl{PDMAPICHLPR0,pfnUnlock} */
517static DECLCALLBACK(void) pdmR0ApicHlp_Unlock(PPDMDEVINS pDevIns)
518{
519 PDMDEV_ASSERT_DEVINS(pDevIns);
520 pdmUnlock(pDevIns->Internal.s.pVMR0);
521}
522
523
524/** @interface_method_impl{PDMAPICHLPR0,pfnGetCpuId} */
525static DECLCALLBACK(VMCPUID) pdmR0ApicHlp_GetCpuId(PPDMDEVINS pDevIns)
526{
527 PDMDEV_ASSERT_DEVINS(pDevIns);
528 return VMMGetCpuId(pDevIns->Internal.s.pVMR0);
529}
530
531
532/**
533 * The Ring-0 APIC Helper Callbacks.
534 */
535extern DECLEXPORT(const PDMAPICHLPR0) g_pdmR0ApicHlp =
536{
537 PDM_APICHLPR0_VERSION,
538 pdmR0ApicHlp_SetInterruptFF,
539 pdmR0ApicHlp_ClearInterruptFF,
540 pdmR0ApicHlp_ChangeFeature,
541 pdmR0ApicHlp_Lock,
542 pdmR0ApicHlp_Unlock,
543 pdmR0ApicHlp_GetCpuId,
544 PDM_APICHLPR0_VERSION
545};
546
547/** @} */
548
549
550
551
552/** @name I/O APIC Ring-0 Helpers
553 * @{
554 */
555
556/** @interface_method_impl{PDMIOAPICHLPR0,pfnApicBusDeliver} */
557static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
558 uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode)
559{
560 PDMDEV_ASSERT_DEVINS(pDevIns);
561 PVM pVM = pDevIns->Internal.s.pVMR0;
562 LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 iVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8\n",
563 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
564 Assert(pVM->pdm.s.Apic.pDevInsR0);
565 if (pVM->pdm.s.Apic.pfnBusDeliverR0)
566 return pVM->pdm.s.Apic.pfnBusDeliverR0(pVM->pdm.s.Apic.pDevInsR0, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
567 return VINF_SUCCESS;
568}
569
570
571/** @interface_method_impl{PDMIOAPICHLPR0,pfnLock} */
572static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
573{
574 PDMDEV_ASSERT_DEVINS(pDevIns);
575 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
576}
577
578
579/** @interface_method_impl{PDMIOAPICHLPR0,pfnUnlock} */
580static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns)
581{
582 PDMDEV_ASSERT_DEVINS(pDevIns);
583 pdmUnlock(pDevIns->Internal.s.pVMR0);
584}
585
586
587/**
588 * The Ring-0 I/O APIC Helper Callbacks.
589 */
590extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp =
591{
592 PDM_IOAPICHLPR0_VERSION,
593 pdmR0IoApicHlp_ApicBusDeliver,
594 pdmR0IoApicHlp_Lock,
595 pdmR0IoApicHlp_Unlock,
596 PDM_IOAPICHLPR0_VERSION
597};
598
599/** @} */
600
601
602
603
604/** @name PCI Bus Ring-0 Helpers
605 * @{
606 */
607
608/** @interface_method_impl{PDMPCIHLPR0,pfnIsaSetIrq} */
609static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
610{
611 PDMDEV_ASSERT_DEVINS(pDevIns);
612 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
613 pdmR0IsaSetIrq(pDevIns->Internal.s.pVMR0, iIrq, iLevel);
614}
615
616
617/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSetIrq} */
618static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
619{
620 PDMDEV_ASSERT_DEVINS(pDevIns);
621 Log4(("pdmR0PciHlp_IoApicSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
622 pdmR0IoApicSetIrq(pDevIns->Internal.s.pVMR0, iIrq, iLevel);
623}
624
625/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSendMsi} */
626static DECLCALLBACK(void) pdmR0PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue)
627{
628 PDMDEV_ASSERT_DEVINS(pDevIns);
629 Log4(("pdmR0PciHlp_IoApicSendMsi: Address=%p Value=%d\n", GCAddr, uValue));
630 pdmR0IoApicSendMsi(pDevIns->Internal.s.pVMR0, GCAddr, uValue);
631}
632
633/** @interface_method_impl{PDMPCIHLPR0,pfnLock} */
634static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
635{
636 PDMDEV_ASSERT_DEVINS(pDevIns);
637 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
638}
639
640
641/** @interface_method_impl{PDMPCIHLPR0,pfnUnlock} */
642static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns)
643{
644 PDMDEV_ASSERT_DEVINS(pDevIns);
645 pdmUnlock(pDevIns->Internal.s.pVMR0);
646}
647
648
649/**
650 * The Ring-0 PCI Bus Helper Callbacks.
651 */
652extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp =
653{
654 PDM_PCIHLPR0_VERSION,
655 pdmR0PciHlp_IsaSetIrq,
656 pdmR0PciHlp_IoApicSetIrq,
657 pdmR0PciHlp_IoApicSendMsi,
658 pdmR0PciHlp_Lock,
659 pdmR0PciHlp_Unlock,
660 PDM_PCIHLPR0_VERSION, /* the end */
661};
662
663/** @} */
664
665
666
667
668/** @name HPET Ring-0 Helpers
669 * @{
670 */
671
672/**
673 * The Ring-0 HPET Helper Callbacks.
674 */
675extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp =
676{
677 PDM_HPETHLPR0_VERSION,
678 PDM_HPETHLPR0_VERSION, /* the end */
679};
680
681/** @} */
682
683/** @name Raw PCI Ring-0 Helpers
684 * @{
685 */
686/**
687 * The Ring-0 PCI raw Helper Callbacks.
688 */
689extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp =
690{
691 PDM_PCIRAWHLPR0_VERSION,
692 PDM_PCIRAWHLPR0_VERSION, /* the end */
693};
694
695/** @} */
696
697/** @name Ring-0 Context Driver Helpers
698 * @{
699 */
700
701/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetError} */
702static DECLCALLBACK(int) pdmR0DrvHlp_VMSetError(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
703{
704 PDMDRV_ASSERT_DRVINS(pDrvIns);
705 va_list args;
706 va_start(args, pszFormat);
707 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
708 va_end(args);
709 return rc;
710}
711
712
713/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetErrorV} */
714static DECLCALLBACK(int) pdmR0DrvHlp_VMSetErrorV(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
715{
716 PDMDRV_ASSERT_DRVINS(pDrvIns);
717 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
718 return rc;
719}
720
721
722/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetRuntimeError} */
723static DECLCALLBACK(int) pdmR0DrvHlp_VMSetRuntimeError(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
724{
725 PDMDRV_ASSERT_DRVINS(pDrvIns);
726 va_list va;
727 va_start(va, pszFormat);
728 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
729 va_end(va);
730 return rc;
731}
732
733
734/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetErrorV} */
735static DECLCALLBACK(int) pdmR0DrvHlp_VMSetRuntimeErrorV(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
736{
737 PDMDRV_ASSERT_DRVINS(pDrvIns);
738 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
739 return rc;
740}
741
742
743/** @interface_method_impl{PDMDRVHLPR0,pfnAssertEMT} */
744static DECLCALLBACK(bool) pdmR0DrvHlp_AssertEMT(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
745{
746 PDMDRV_ASSERT_DRVINS(pDrvIns);
747 if (VM_IS_EMT(pDrvIns->Internal.s.pVMR0))
748 return true;
749
750 RTAssertMsg1Weak("AssertEMT", iLine, pszFile, pszFunction);
751 RTAssertPanic();
752 return false;
753}
754
755
756/** @interface_method_impl{PDMDRVHLPR0,pfnAssertOther} */
757static DECLCALLBACK(bool) pdmR0DrvHlp_AssertOther(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
758{
759 PDMDRV_ASSERT_DRVINS(pDrvIns);
760 if (!VM_IS_EMT(pDrvIns->Internal.s.pVMR0))
761 return true;
762
763 RTAssertMsg1Weak("AssertOther", iLine, pszFile, pszFunction);
764 RTAssertPanic();
765 return false;
766}
767
768
769/** @interface_method_impl{PDMDRVHLPR0,pfnFTSetCheckpoint} */
770static DECLCALLBACK(int) pdmR0DrvHlp_FTSetCheckpoint(PPDMDRVINS pDrvIns, FTMCHECKPOINTTYPE enmType)
771{
772 PDMDRV_ASSERT_DRVINS(pDrvIns);
773 return FTMSetCheckpoint(pDrvIns->Internal.s.pVMR0, enmType);
774}
775
776
777/**
778 * The Ring-0 Context Driver Helper Callbacks.
779 */
780extern DECLEXPORT(const PDMDRVHLPR0) g_pdmR0DrvHlp =
781{
782 PDM_DRVHLPRC_VERSION,
783 pdmR0DrvHlp_VMSetError,
784 pdmR0DrvHlp_VMSetErrorV,
785 pdmR0DrvHlp_VMSetRuntimeError,
786 pdmR0DrvHlp_VMSetRuntimeErrorV,
787 pdmR0DrvHlp_AssertEMT,
788 pdmR0DrvHlp_AssertOther,
789 pdmR0DrvHlp_FTSetCheckpoint,
790 PDM_DRVHLPRC_VERSION
791};
792
793/** @} */
794
795
796
797
798/**
799 * Sets an irq on the I/O APIC.
800 *
801 * @param pVM The VM handle.
802 * @param iIrq The irq.
803 * @param iLevel The new level.
804 */
805static void pdmR0IsaSetIrq(PVM pVM, int iIrq, int iLevel)
806{
807 if ( ( pVM->pdm.s.IoApic.pDevInsR0
808 || !pVM->pdm.s.IoApic.pDevInsR3)
809 && ( pVM->pdm.s.Pic.pDevInsR0
810 || !pVM->pdm.s.Pic.pDevInsR3))
811 {
812 pdmLock(pVM);
813 if (pVM->pdm.s.Pic.pDevInsR0)
814 pVM->pdm.s.Pic.pfnSetIrqR0(pVM->pdm.s.Pic.pDevInsR0, iIrq, iLevel);
815 if (pVM->pdm.s.IoApic.pDevInsR0)
816 pVM->pdm.s.IoApic.pfnSetIrqR0(pVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel);
817 pdmUnlock(pVM);
818 }
819 else
820 {
821 /* queue for ring-3 execution. */
822 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
823 if (pTask)
824 {
825 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
826 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
827 pTask->u.SetIRQ.iIrq = iIrq;
828 pTask->u.SetIRQ.iLevel = iLevel;
829
830 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
831 }
832 else
833 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
834 }
835}
836
837
838/**
839 * Sets an irq on the I/O APIC.
840 *
841 * @param pVM The VM handle.
842 * @param iIrq The irq.
843 * @param iLevel The new level.
844 */
845static void pdmR0IoApicSetIrq(PVM pVM, int iIrq, int iLevel)
846{
847 if (pVM->pdm.s.IoApic.pDevInsR0)
848 {
849 pdmLock(pVM);
850 pVM->pdm.s.IoApic.pfnSetIrqR0(pVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel);
851 pdmUnlock(pVM);
852 }
853 else if (pVM->pdm.s.IoApic.pDevInsR3)
854 {
855 /* queue for ring-3 execution. */
856 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
857 if (pTask)
858 {
859 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
860 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
861 pTask->u.SetIRQ.iIrq = iIrq;
862 pTask->u.SetIRQ.iLevel = iLevel;
863
864 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
865 }
866 else
867 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
868 }
869}
870
871
872/**
873 * PDMDevHlpCallR0 helper.
874 *
875 * @returns See PFNPDMDEVREQHANDLERR0.
876 * @param pVM The VM handle (for validation).
877 * @param pReq The request buffer.
878 */
879VMMR0_INT_DECL(int) PDMR0DeviceCallReqHandler(PVM pVM, PPDMDEVICECALLREQHANDLERREQ pReq)
880{
881 /*
882 * Validate input and make the call.
883 */
884 AssertPtrReturn(pVM, VERR_INVALID_POINTER);
885 AssertPtrReturn(pReq, VERR_INVALID_POINTER);
886 AssertMsgReturn(pReq->Hdr.cbReq == sizeof(*pReq), ("%#x != %#x\n", pReq->Hdr.cbReq, sizeof(*pReq)), VERR_INVALID_PARAMETER);
887
888 PPDMDEVINS pDevIns = pReq->pDevInsR0;
889 AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
890 AssertReturn(pDevIns->Internal.s.pVMR0 == pVM, VERR_INVALID_PARAMETER);
891
892 PFNPDMDEVREQHANDLERR0 pfnReqHandlerR0 = pReq->pfnReqHandlerR0;
893 AssertPtrReturn(pfnReqHandlerR0, VERR_INVALID_POINTER);
894
895 return pfnReqHandlerR0(pDevIns, pReq->uOperation, pReq->u64Arg);
896}
897
898/**
899 * Sends an MSI to I/O APIC.
900 *
901 * @param pVM The VM handle.
902 * @param GCAddr Address of the message.
903 * @param uValue Value of the message.
904 */
905static void pdmR0IoApicSendMsi(PVM pVM, RTGCPHYS GCAddr, uint32_t uValue)
906{
907 if (pVM->pdm.s.IoApic.pDevInsR0)
908 {
909 pdmLock(pVM);
910 pVM->pdm.s.IoApic.pfnSendMsiR0(pVM->pdm.s.IoApic.pDevInsR0, GCAddr, uValue);
911 pdmUnlock(pVM);
912 }
913}
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