VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp@ 24125

Last change on this file since 24125 was 24125, checked in by vboxsync, 15 years ago

DevAPIC/PDM: Properly route PIC interrupts through local APIC (fixes double time interrupt delivery in some Linux kernels).
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1/* $Id: PDMR0Device.cpp 24125 2009-10-28 09:58:41Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, R0 Device parts.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PDM_DEVICE
27#include "PDMInternal.h"
28#include <VBox/pdm.h>
29#include <VBox/pgm.h>
30#include <VBox/mm.h>
31#include <VBox/vm.h>
32#include <VBox/vmm.h>
33#include <VBox/patm.h>
34#include <VBox/hwaccm.h>
35
36#include <VBox/log.h>
37#include <VBox/err.h>
38#include <VBox/gvmm.h>
39#include <iprt/asm.h>
40#include <iprt/assert.h>
41#include <iprt/string.h>
42
43
44/*******************************************************************************
45* Global Variables *
46*******************************************************************************/
47RT_C_DECLS_BEGIN
48extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp;
49extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp;
50extern DECLEXPORT(const PDMAPICHLPR0) g_pdmR0ApicHlp;
51extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp;
52extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp;
53RT_C_DECLS_END
54
55
56/*******************************************************************************
57* Internal Functions *
58*******************************************************************************/
59/** @name GC Device Helpers
60 * @{
61 */
62static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
63static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
64static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead);
65static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite);
66static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns);
67static DECLCALLBACK(int) pdmR0DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...);
68static DECLCALLBACK(int) pdmR0DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va);
69static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...);
70static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va);
71static DECLCALLBACK(int) pdmR0DevHlp_PATMSetMMIOPatchInfo(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPTR pCachedData);
72static DECLCALLBACK(PVM) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns);
73static DECLCALLBACK(bool) pdmR0DevHlp_CanEmulateIoBlock(PPDMDEVINS pDevIns);
74static DECLCALLBACK(PVMCPU) pdmR0DevHlp_GetVMCPU(PPDMDEVINS pDevIns);
75/** @} */
76
77
78/** @name PIC GC Helpers
79 * @{
80 */
81static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns);
82static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns);
83static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc);
84static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns);
85/** @} */
86
87
88/** @name APIC GC Helpers
89 * @{
90 */
91static DECLCALLBACK(void) pdmR0ApicHlp_SetInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu);
92static DECLCALLBACK(void) pdmR0ApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu);
93static DECLCALLBACK(void) pdmR0ApicHlp_ChangeFeature(PPDMDEVINS pDevIns, PDMAPICVERSION enmVersion);
94static DECLCALLBACK(int) pdmR0ApicHlp_Lock(PPDMDEVINS pDevIns, int rc);
95static DECLCALLBACK(void) pdmR0ApicHlp_Unlock(PPDMDEVINS pDevIns);
96static DECLCALLBACK(VMCPUID) pdmR0ApicHlp_GetCpuId(PPDMDEVINS pDevIns);
97/** @} */
98
99
100/** @name I/O APIC GC Helpers
101 * @{
102 */
103static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
104 uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode);
105static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc);
106static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns);
107/** @} */
108
109
110/** @name PCI Bus GC Helpers
111 * @{
112 */
113static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
114static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
115static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc);
116static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns);
117/** @} */
118
119
120static void pdmR0IsaSetIrq(PVM pVM, int iIrq, int iLevel);
121static void pdmR0IoApicSetIrq(PVM pVM, int iIrq, int iLevel);
122
123
124
125/**
126 * The Guest Context Device Helper Callbacks.
127 */
128extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp =
129{
130 PDM_DEVHLPR0_VERSION,
131 pdmR0DevHlp_PCISetIrq,
132 pdmR0DevHlp_ISASetIrq,
133 pdmR0DevHlp_PhysRead,
134 pdmR0DevHlp_PhysWrite,
135 pdmR0DevHlp_A20IsEnabled,
136 pdmR0DevHlp_VMSetError,
137 pdmR0DevHlp_VMSetErrorV,
138 pdmR0DevHlp_VMSetRuntimeError,
139 pdmR0DevHlp_VMSetRuntimeErrorV,
140 pdmR0DevHlp_PATMSetMMIOPatchInfo,
141 pdmR0DevHlp_GetVM,
142 pdmR0DevHlp_CanEmulateIoBlock,
143 pdmR0DevHlp_GetVMCPU,
144 PDM_DEVHLPR0_VERSION
145};
146
147/**
148 * The Guest Context PIC Helper Callbacks.
149 */
150extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp =
151{
152 PDM_PICHLPR0_VERSION,
153 pdmR0PicHlp_SetInterruptFF,
154 pdmR0PicHlp_ClearInterruptFF,
155 pdmR0PicHlp_Lock,
156 pdmR0PicHlp_Unlock,
157 PDM_PICHLPR0_VERSION
158};
159
160
161/**
162 * The Guest Context APIC Helper Callbacks.
163 */
164extern DECLEXPORT(const PDMAPICHLPR0) g_pdmR0ApicHlp =
165{
166 PDM_APICHLPR0_VERSION,
167 pdmR0ApicHlp_SetInterruptFF,
168 pdmR0ApicHlp_ClearInterruptFF,
169 pdmR0ApicHlp_ChangeFeature,
170 pdmR0ApicHlp_Lock,
171 pdmR0ApicHlp_Unlock,
172 pdmR0ApicHlp_GetCpuId,
173 PDM_APICHLPR0_VERSION
174};
175
176
177/**
178 * The Guest Context I/O APIC Helper Callbacks.
179 */
180extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp =
181{
182 PDM_IOAPICHLPR0_VERSION,
183 pdmR0IoApicHlp_ApicBusDeliver,
184 pdmR0IoApicHlp_Lock,
185 pdmR0IoApicHlp_Unlock,
186 PDM_IOAPICHLPR0_VERSION
187};
188
189
190/**
191 * The Guest Context PCI Bus Helper Callbacks.
192 */
193extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp =
194{
195 PDM_PCIHLPR0_VERSION,
196 pdmR0PciHlp_IsaSetIrq,
197 pdmR0PciHlp_IoApicSetIrq,
198 pdmR0PciHlp_Lock,
199 pdmR0PciHlp_Unlock,
200 PDM_PCIHLPR0_VERSION, /* the end */
201};
202
203
204
205
206/** @copydoc PDMDEVHLPR0::pfnPCISetIrq */
207static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
208{
209 PDMDEV_ASSERT_DEVINS(pDevIns);
210 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
211
212 PVM pVM = pDevIns->Internal.s.pVMR0;
213 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR0;
214 PPDMPCIBUS pPciBus = pDevIns->Internal.s.pPciBusR0;
215 if ( pPciDev
216 && pPciBus
217 && pPciBus->pDevInsR0)
218 {
219 pdmLock(pVM);
220 pPciBus->pfnSetIrqR0(pPciBus->pDevInsR0, pPciDev, iIrq, iLevel);
221 pdmUnlock(pVM);
222 }
223 else
224 {
225 /* queue for ring-3 execution. */
226 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
227 if (pTask)
228 {
229 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
230 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
231 pTask->u.SetIRQ.iIrq = iIrq;
232 pTask->u.SetIRQ.iLevel = iLevel;
233
234 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
235 }
236 else
237 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
238 }
239
240 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: returns void\n", pDevIns, pDevIns->iInstance));
241}
242
243
244/** @copydoc PDMDEVHLPR0::pfnPCISetIrq */
245static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
246{
247 PDMDEV_ASSERT_DEVINS(pDevIns);
248 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
249
250 pdmR0IsaSetIrq(pDevIns->Internal.s.pVMR0, iIrq, iLevel);
251
252 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: returns void\n", pDevIns, pDevIns->iInstance));
253}
254
255
256/** @copydoc PDMDEVHLPR0::pfnPhysRead */
257static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
258{
259 PDMDEV_ASSERT_DEVINS(pDevIns);
260 LogFlow(("pdmR0DevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
261 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
262
263 int rc = PGMPhysRead(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbRead);
264 AssertRC(rc); /** @todo track down the users for this bugger. */
265
266 Log(("pdmR0DevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, rc));
267 return rc;
268}
269
270
271/** @copydoc PDMDEVHLPR0::pfnPhysWrite */
272static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
273{
274 PDMDEV_ASSERT_DEVINS(pDevIns);
275 LogFlow(("pdmR0DevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
276 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
277
278 int rc = PGMPhysWrite(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbWrite);
279 AssertRC(rc); /** @todo track down the users for this bugger. */
280
281 Log(("pdmR0DevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, rc));
282 return rc;
283}
284
285
286/** @copydoc PDMDEVHLPR0::pfnA20IsEnabled */
287static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
288{
289 PDMDEV_ASSERT_DEVINS(pDevIns);
290 LogFlow(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
291
292 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pVMR0));
293
294 Log(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
295 return fEnabled;
296}
297
298
299/** @copydoc PDMDEVHLPR0::pfnVMSetError */
300static DECLCALLBACK(int) pdmR0DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
301{
302 PDMDEV_ASSERT_DEVINS(pDevIns);
303 va_list args;
304 va_start(args, pszFormat);
305 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
306 va_end(args);
307 return rc;
308}
309
310
311/** @copydoc PDMDEVHLPR0::pfnVMSetErrorV */
312static DECLCALLBACK(int) pdmR0DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
313{
314 PDMDEV_ASSERT_DEVINS(pDevIns);
315 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
316 return rc;
317}
318
319
320/** @copydoc PDMDEVHLPR0::pfnVMSetRuntimeError */
321static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
322{
323 PDMDEV_ASSERT_DEVINS(pDevIns);
324 va_list va;
325 va_start(va, pszFormat);
326 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
327 va_end(va);
328 return rc;
329}
330
331
332/** @copydoc PDMDEVHLPR0::pfnVMSetRuntimeErrorV */
333static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
334{
335 PDMDEV_ASSERT_DEVINS(pDevIns);
336 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
337 return rc;
338}
339
340
341/** @copydoc PDMDEVHLPR0::pdmR0DevHlp_PATMSetMMIOPatchInfo*/
342static DECLCALLBACK(int) pdmR0DevHlp_PATMSetMMIOPatchInfo(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPTR pCachedData)
343{
344 PDMDEV_ASSERT_DEVINS(pDevIns);
345 LogFlow(("pdmR0DevHlp_PATMSetMMIOPatchInfo: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
346
347 AssertFailed();
348
349/* return PATMSetMMIOPatchInfo(pDevIns->Internal.s.pVMR0, GCPhys, pCachedData); */
350 return VINF_SUCCESS;
351}
352
353
354/** @copydoc PDMDEVHLPR0::pfnGetVM */
355static DECLCALLBACK(PVM) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns)
356{
357 PDMDEV_ASSERT_DEVINS(pDevIns);
358 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
359 return pDevIns->Internal.s.pVMR0;
360}
361
362
363/** @copydoc PDMDEVHLPR0::pfnCanEmulateIoBlock */
364static DECLCALLBACK(bool) pdmR0DevHlp_CanEmulateIoBlock(PPDMDEVINS pDevIns)
365{
366 PDMDEV_ASSERT_DEVINS(pDevIns);
367 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
368 return HWACCMCanEmulateIoBlock(VMMGetCpu(pDevIns->Internal.s.pVMR0));
369}
370
371
372/** @copydoc PDMDEVHLPR0::pfnGetVMCPU */
373static DECLCALLBACK(PVMCPU) pdmR0DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
374{
375 PDMDEV_ASSERT_DEVINS(pDevIns);
376 LogFlow(("pdmR0DevHlp_GetVMCPU: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
377 return VMMGetCpu(pDevIns->Internal.s.pVMR0);
378}
379
380
381
382
383/** @copydoc PDMPICHLPR0::pfnSetInterruptFF */
384static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
385{
386 PDMDEV_ASSERT_DEVINS(pDevIns);
387 PVM pVM = pDevIns->Internal.s.pVMR0;
388 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
389
390 LogFlow(("pdmR0PicHlp_SetInterruptFF: caller=%p/%d: VMCPU_FF_INTERRUPT_PIC %d -> 1\n",
391 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
392
393 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
394}
395
396
397/** @copydoc PDMPICHLPR0::pfnClearInterruptFF */
398static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
399{
400 PDMDEV_ASSERT_DEVINS(pDevIns);
401 PVM pVM = pDevIns->Internal.s.pVMR0;
402 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
403
404 LogFlow(("pdmR0PicHlp_ClearInterruptFF: caller=%p/%d: VMCPU_FF_INTERRUPT_PIC %d -> 0\n",
405 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
406
407 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
408}
409
410
411/** @copydoc PDMPICHLPR0::pfnLock */
412static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
413{
414 PDMDEV_ASSERT_DEVINS(pDevIns);
415 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
416}
417
418
419/** @copydoc PDMPICHLPR0::pfnUnlock */
420static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns)
421{
422 PDMDEV_ASSERT_DEVINS(pDevIns);
423 pdmUnlock(pDevIns->Internal.s.pVMR0);
424}
425
426
427
428/** @copydoc PDMAPICHLPR0::pfnSetInterruptFF */
429static DECLCALLBACK(void) pdmR0ApicHlp_SetInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
430{
431 PDMDEV_ASSERT_DEVINS(pDevIns);
432 PVM pVM = pDevIns->Internal.s.pVMR0;
433 PVMCPU pVCpu = &pVM->aCpus[idCpu];
434
435 AssertReturnVoid(idCpu < pVM->cCpus);
436
437 LogFlow(("pdmR0ApicHlp_SetInterruptFF: CPU%d=caller=%p/%d: VM_FF_INTERRUPT %d -> 1 (CPU%d)\n",
438 VMMGetCpuId(pVM), pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_APIC), idCpu));
439
440 switch (enmType)
441 {
442 case PDMAPICIRQ_HARDWARE:
443 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC);
444 break;
445 case PDMAPICIRQ_NMI:
446 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI);
447 break;
448 case PDMAPICIRQ_SMI:
449 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_SMI);
450 break;
451 default:
452 AssertMsgFailed(("enmType=%d\n", enmType));
453 break;
454 }
455
456 /* We need to wait up the target CPU. */
457 if (VMMGetCpuId(pVM) != idCpu)
458 {
459 switch (VMCPU_GET_STATE(pVCpu))
460 {
461 case VMCPUSTATE_STARTED_EXEC:
462 GVMMR0SchedPokeEx(pVM, pVCpu->idCpu, false /* don't take the used lock */);
463 break;
464
465 case VMCPUSTATE_STARTED_HALTED:
466 GVMMR0SchedWakeUpEx(pVM, pVCpu->idCpu, false /* don't take the used lock */);
467 break;
468
469 default:
470 break; /* nothing to do in other states. */
471 }
472 }
473}
474
475
476/** @copydoc PDMAPICHLPR0::pfnClearInterruptFF */
477static DECLCALLBACK(void) pdmR0ApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
478{
479 PDMDEV_ASSERT_DEVINS(pDevIns);
480 PVM pVM = pDevIns->Internal.s.pVMR0;
481 PVMCPU pVCpu = &pVM->aCpus[idCpu];
482
483 AssertReturnVoid(idCpu < pVM->cCpus);
484
485 LogFlow(("pdmR0ApicHlp_ClearInterruptFF: caller=%p/%d: VM_FF_INTERRUPT %d -> 0\n",
486 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_APIC)));
487
488 /* Note: NMI/SMI can't be cleared. */
489 switch (enmType)
490 {
491 case PDMAPICIRQ_HARDWARE:
492 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
493 break;
494 case PDMAPICIRQ_EXTINT:
495 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
496 break;
497 default:
498 AssertMsgFailed(("enmType=%d\n", enmType));
499 break;
500 }
501}
502
503
504/** @copydoc PDMAPICHLPR0::pfnChangeFeature */
505static DECLCALLBACK(void) pdmR0ApicHlp_ChangeFeature(PPDMDEVINS pDevIns, PDMAPICVERSION enmVersion)
506{
507 PDMDEV_ASSERT_DEVINS(pDevIns);
508 LogFlow(("pdmR0ApicHlp_ChangeFeature: caller=%p/%d: version=%d\n", pDevIns, pDevIns->iInstance, (int)enmVersion));
509 switch (enmVersion)
510 {
511 case PDMAPICVERSION_NONE:
512 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
513 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
514 break;
515 case PDMAPICVERSION_APIC:
516 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
517 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
518 break;
519 case PDMAPICVERSION_X2APIC:
520 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
521 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
522 break;
523 default:
524 AssertMsgFailed(("Unknown APIC version: %d\n", (int)enmVersion));
525 }
526}
527
528
529/** @copydoc PDMAPICHLPR0::pfnLock */
530static DECLCALLBACK(int) pdmR0ApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
531{
532 PDMDEV_ASSERT_DEVINS(pDevIns);
533 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
534}
535
536
537/** @copydoc PDMAPICHLPR0::pfnUnlock */
538static DECLCALLBACK(void) pdmR0ApicHlp_Unlock(PPDMDEVINS pDevIns)
539{
540 PDMDEV_ASSERT_DEVINS(pDevIns);
541 pdmUnlock(pDevIns->Internal.s.pVMR0);
542}
543
544
545/** @copydoc PDMAPICHLPR0::pfnGetCpuId */
546static DECLCALLBACK(VMCPUID) pdmR0ApicHlp_GetCpuId(PPDMDEVINS pDevIns)
547{
548 PDMDEV_ASSERT_DEVINS(pDevIns);
549 return VMMGetCpuId(pDevIns->Internal.s.pVMR0);
550}
551
552
553
554
555
556/** @copydoc PDMIOAPICHLPR0::pfnApicBusDeliver */
557static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
558 uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode)
559{
560 PDMDEV_ASSERT_DEVINS(pDevIns);
561 PVM pVM = pDevIns->Internal.s.pVMR0;
562 LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 iVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8\n",
563 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
564 Assert(pVM->pdm.s.Apic.pDevInsR0);
565 if (pVM->pdm.s.Apic.pfnBusDeliverR0)
566 return pVM->pdm.s.Apic.pfnBusDeliverR0(pVM->pdm.s.Apic.pDevInsR0, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
567 return VINF_SUCCESS;
568}
569
570
571/** @copydoc PDMIOAPICHLPR0::pfnLock */
572static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
573{
574 PDMDEV_ASSERT_DEVINS(pDevIns);
575 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
576}
577
578
579/** @copydoc PDMIOAPICHLPR0::pfnUnlock */
580static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns)
581{
582 PDMDEV_ASSERT_DEVINS(pDevIns);
583 pdmUnlock(pDevIns->Internal.s.pVMR0);
584}
585
586
587
588
589
590/** @copydoc PDMPCIHLPR0::pfnIsaSetIrq */
591static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
592{
593 PDMDEV_ASSERT_DEVINS(pDevIns);
594 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
595 pdmR0IsaSetIrq(pDevIns->Internal.s.pVMR0, iIrq, iLevel);
596}
597
598
599/** @copydoc PDMPCIHLPR0::pfnIoApicSetIrq */
600static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
601{
602 PDMDEV_ASSERT_DEVINS(pDevIns);
603 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
604 pdmR0IoApicSetIrq(pDevIns->Internal.s.pVMR0, iIrq, iLevel);
605}
606
607
608/** @copydoc PDMPCIHLPR0::pfnLock */
609static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
610{
611 PDMDEV_ASSERT_DEVINS(pDevIns);
612 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
613}
614
615
616/** @copydoc PDMPCIHLPR0::pfnUnlock */
617static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns)
618{
619 PDMDEV_ASSERT_DEVINS(pDevIns);
620 pdmUnlock(pDevIns->Internal.s.pVMR0);
621}
622
623
624
625
626/**
627 * Sets an irq on the I/O APIC.
628 *
629 * @param pVM The VM handle.
630 * @param iIrq The irq.
631 * @param iLevel The new level.
632 */
633static void pdmR0IsaSetIrq(PVM pVM, int iIrq, int iLevel)
634{
635 if ( ( pVM->pdm.s.IoApic.pDevInsR0
636 || !pVM->pdm.s.IoApic.pDevInsR3)
637 && ( pVM->pdm.s.Pic.pDevInsR0
638 || !pVM->pdm.s.Pic.pDevInsR3))
639 {
640 pdmLock(pVM);
641 if (pVM->pdm.s.Pic.pDevInsR0)
642 pVM->pdm.s.Pic.pfnSetIrqR0(pVM->pdm.s.Pic.pDevInsR0, iIrq, iLevel);
643 if (pVM->pdm.s.IoApic.pDevInsR0)
644 pVM->pdm.s.IoApic.pfnSetIrqR0(pVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel);
645 pdmUnlock(pVM);
646 }
647 else
648 {
649 /* queue for ring-3 execution. */
650 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
651 if (pTask)
652 {
653 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
654 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
655 pTask->u.SetIRQ.iIrq = iIrq;
656 pTask->u.SetIRQ.iLevel = iLevel;
657
658 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
659 }
660 else
661 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
662 }
663}
664
665
666/**
667 * Sets an irq on the I/O APIC.
668 *
669 * @param pVM The VM handle.
670 * @param iIrq The irq.
671 * @param iLevel The new level.
672 */
673static void pdmR0IoApicSetIrq(PVM pVM, int iIrq, int iLevel)
674{
675 if (pVM->pdm.s.IoApic.pDevInsR0)
676 {
677 pdmLock(pVM);
678 pVM->pdm.s.IoApic.pfnSetIrqR0(pVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel);
679 pdmUnlock(pVM);
680 }
681 else if (pVM->pdm.s.IoApic.pDevInsR3)
682 {
683 /* queue for ring-3 execution. */
684 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
685 if (pTask)
686 {
687 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
688 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
689 pTask->u.SetIRQ.iIrq = iIrq;
690 pTask->u.SetIRQ.iLevel = iLevel;
691
692 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
693 }
694 else
695 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
696 }
697}
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