VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp@ 18768

Last change on this file since 18768 was 18666, checked in by vboxsync, 15 years ago

VMM: Clean out the VBOX_WITH_NEW_PHYS_CODE #ifdefs. (part 2)
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  • Property svn:keywords set to Id
File size: 21.1 KB
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1/* $Id: PDMR0Device.cpp 18666 2009-04-02 23:10:12Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, R0 Device parts.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_PDM_DEVICE
27#include "PDMInternal.h"
28#include <VBox/pdm.h>
29#include <VBox/pgm.h>
30#include <VBox/mm.h>
31#include <VBox/vm.h>
32#include <VBox/patm.h>
33#include <VBox/hwaccm.h>
34
35#include <VBox/log.h>
36#include <VBox/err.h>
37#include <iprt/asm.h>
38#include <iprt/assert.h>
39#include <iprt/string.h>
40
41
42/*******************************************************************************
43* Global Variables *
44*******************************************************************************/
45__BEGIN_DECLS
46extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp;
47extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp;
48extern DECLEXPORT(const PDMAPICHLPR0) g_pdmR0ApicHlp;
49extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp;
50extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp;
51__END_DECLS
52
53
54/*******************************************************************************
55* Internal Functions *
56*******************************************************************************/
57/** @name GC Device Helpers
58 * @{
59 */
60static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
61static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
62static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead);
63static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite);
64static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns);
65static DECLCALLBACK(int) pdmR0DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...);
66static DECLCALLBACK(int) pdmR0DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va);
67static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...);
68static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va);
69static DECLCALLBACK(int) pdmR0DevHlp_PATMSetMMIOPatchInfo(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPTR pCachedData);
70static DECLCALLBACK(PVM) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns);
71static DECLCALLBACK(bool) pdmR0DevHlp_CanEmulateIoBlock(PPDMDEVINS pDevIns);
72/** @} */
73
74
75/** @name PIC GC Helpers
76 * @{
77 */
78static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns);
79static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns);
80static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc);
81static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns);
82/** @} */
83
84
85/** @name APIC GC Helpers
86 * @{
87 */
88static DECLCALLBACK(void) pdmR0ApicHlp_SetInterruptFF(PPDMDEVINS pDevIns, VMCPUID idCpu);
89static DECLCALLBACK(void) pdmR0ApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, VMCPUID idCpu);
90static DECLCALLBACK(void) pdmR0ApicHlp_ChangeFeature(PPDMDEVINS pDevIns, PDMAPICVERSION enmVersion);
91static DECLCALLBACK(int) pdmR0ApicHlp_Lock(PPDMDEVINS pDevIns, int rc);
92static DECLCALLBACK(void) pdmR0ApicHlp_Unlock(PPDMDEVINS pDevIns);
93static DECLCALLBACK(VMCPUID) pdmR0ApicHlp_GetCpuId(PPDMDEVINS pDevIns);
94/** @} */
95
96
97/** @name I/O APIC GC Helpers
98 * @{
99 */
100static DECLCALLBACK(void) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
101 uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode);
102static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc);
103static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns);
104/** @} */
105
106
107/** @name PCI Bus GC Helpers
108 * @{
109 */
110static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
111static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
112static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc);
113static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns);
114/** @} */
115
116
117static void pdmR0IsaSetIrq(PVM pVM, int iIrq, int iLevel);
118static void pdmR0IoApicSetIrq(PVM pVM, int iIrq, int iLevel);
119
120
121
122/**
123 * The Guest Context Device Helper Callbacks.
124 */
125extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp =
126{
127 PDM_DEVHLPR0_VERSION,
128 pdmR0DevHlp_PCISetIrq,
129 pdmR0DevHlp_ISASetIrq,
130 pdmR0DevHlp_PhysRead,
131 pdmR0DevHlp_PhysWrite,
132 pdmR0DevHlp_A20IsEnabled,
133 pdmR0DevHlp_VMSetError,
134 pdmR0DevHlp_VMSetErrorV,
135 pdmR0DevHlp_VMSetRuntimeError,
136 pdmR0DevHlp_VMSetRuntimeErrorV,
137 pdmR0DevHlp_PATMSetMMIOPatchInfo,
138 pdmR0DevHlp_GetVM,
139 pdmR0DevHlp_CanEmulateIoBlock,
140 PDM_DEVHLPR0_VERSION
141};
142
143/**
144 * The Guest Context PIC Helper Callbacks.
145 */
146extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp =
147{
148 PDM_PICHLPR0_VERSION,
149 pdmR0PicHlp_SetInterruptFF,
150 pdmR0PicHlp_ClearInterruptFF,
151 pdmR0PicHlp_Lock,
152 pdmR0PicHlp_Unlock,
153 PDM_PICHLPR0_VERSION
154};
155
156
157/**
158 * The Guest Context APIC Helper Callbacks.
159 */
160extern DECLEXPORT(const PDMAPICHLPR0) g_pdmR0ApicHlp =
161{
162 PDM_APICHLPR0_VERSION,
163 pdmR0ApicHlp_SetInterruptFF,
164 pdmR0ApicHlp_ClearInterruptFF,
165 pdmR0ApicHlp_ChangeFeature,
166 pdmR0ApicHlp_Lock,
167 pdmR0ApicHlp_Unlock,
168 pdmR0ApicHlp_GetCpuId,
169 PDM_APICHLPR0_VERSION
170};
171
172
173/**
174 * The Guest Context I/O APIC Helper Callbacks.
175 */
176extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp =
177{
178 PDM_IOAPICHLPR0_VERSION,
179 pdmR0IoApicHlp_ApicBusDeliver,
180 pdmR0IoApicHlp_Lock,
181 pdmR0IoApicHlp_Unlock,
182 PDM_IOAPICHLPR0_VERSION
183};
184
185
186/**
187 * The Guest Context PCI Bus Helper Callbacks.
188 */
189extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp =
190{
191 PDM_PCIHLPR0_VERSION,
192 pdmR0PciHlp_IsaSetIrq,
193 pdmR0PciHlp_IoApicSetIrq,
194 pdmR0PciHlp_Lock,
195 pdmR0PciHlp_Unlock,
196 PDM_PCIHLPR0_VERSION, /* the end */
197};
198
199
200
201
202/** @copydoc PDMDEVHLPR0::pfnPCISetIrq */
203static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
204{
205 PDMDEV_ASSERT_DEVINS(pDevIns);
206 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
207
208 PVM pVM = pDevIns->Internal.s.pVMR0;
209 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR0;
210 PPDMPCIBUS pPciBus = pDevIns->Internal.s.pPciBusR0;
211 if ( pPciDev
212 && pPciBus
213 && pPciBus->pDevInsR0)
214 {
215 pdmLock(pVM);
216 pPciBus->pfnSetIrqR0(pPciBus->pDevInsR0, pPciDev, iIrq, iLevel);
217 pdmUnlock(pVM);
218 }
219 else
220 {
221 /* queue for ring-3 execution. */
222 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
223 if (pTask)
224 {
225 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
226 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
227 pTask->u.SetIRQ.iIrq = iIrq;
228 pTask->u.SetIRQ.iLevel = iLevel;
229
230 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
231 }
232 else
233 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
234 }
235
236 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: returns void\n", pDevIns, pDevIns->iInstance));
237}
238
239
240/** @copydoc PDMDEVHLPR0::pfnPCISetIrq */
241static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
242{
243 PDMDEV_ASSERT_DEVINS(pDevIns);
244 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
245
246 pdmR0IsaSetIrq(pDevIns->Internal.s.pVMR0, iIrq, iLevel);
247
248 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: returns void\n", pDevIns, pDevIns->iInstance));
249}
250
251
252/** @copydoc PDMDEVHLPR0::pfnPhysRead */
253static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
254{
255 PDMDEV_ASSERT_DEVINS(pDevIns);
256 LogFlow(("pdmR0DevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
257 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
258
259 int rc = PGMPhysRead(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbRead);
260 AssertRC(rc); /** @todo track down the users for this bugger. */
261
262 Log(("pdmR0DevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, rc));
263 return rc;
264}
265
266
267/** @copydoc PDMDEVHLPR0::pfnPhysWrite */
268static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
269{
270 PDMDEV_ASSERT_DEVINS(pDevIns);
271 LogFlow(("pdmR0DevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
272 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
273
274 int rc = PGMPhysWrite(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbWrite);
275 AssertRC(rc); /** @todo track down the users for this bugger. */
276
277 Log(("pdmR0DevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, rc));
278 return rc;
279}
280
281
282/** @copydoc PDMDEVHLPR0::pfnA20IsEnabled */
283static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
284{
285 PDMDEV_ASSERT_DEVINS(pDevIns);
286 LogFlow(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
287
288 bool fEnabled = PGMPhysIsA20Enabled(pDevIns->Internal.s.pVMR0);
289
290 Log(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
291 return fEnabled;
292}
293
294
295/** @copydoc PDMDEVHLPR0::pfnVMSetError */
296static DECLCALLBACK(int) pdmR0DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
297{
298 PDMDEV_ASSERT_DEVINS(pDevIns);
299 va_list args;
300 va_start(args, pszFormat);
301 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
302 va_end(args);
303 return rc;
304}
305
306
307/** @copydoc PDMDEVHLPR0::pfnVMSetErrorV */
308static DECLCALLBACK(int) pdmR0DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
309{
310 PDMDEV_ASSERT_DEVINS(pDevIns);
311 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
312 return rc;
313}
314
315
316/** @copydoc PDMDEVHLPR0::pfnVMSetRuntimeError */
317static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
318{
319 PDMDEV_ASSERT_DEVINS(pDevIns);
320 va_list va;
321 va_start(va, pszFormat);
322 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
323 va_end(va);
324 return rc;
325}
326
327
328/** @copydoc PDMDEVHLPR0::pfnVMSetRuntimeErrorV */
329static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
330{
331 PDMDEV_ASSERT_DEVINS(pDevIns);
332 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
333 return rc;
334}
335
336
337/** @copydoc PDMDEVHLPR0::pdmR0DevHlp_PATMSetMMIOPatchInfo*/
338static DECLCALLBACK(int) pdmR0DevHlp_PATMSetMMIOPatchInfo(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPTR pCachedData)
339{
340 PDMDEV_ASSERT_DEVINS(pDevIns);
341 LogFlow(("pdmR0DevHlp_PATMSetMMIOPatchInfo: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
342
343 AssertFailed();
344
345/* return PATMSetMMIOPatchInfo(pDevIns->Internal.s.pVMR0, GCPhys, pCachedData); */
346 return VINF_SUCCESS;
347}
348
349
350/** @copydoc PDMDEVHLPR0::pfnGetVM */
351static DECLCALLBACK(PVM) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns)
352{
353 PDMDEV_ASSERT_DEVINS(pDevIns);
354 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
355 return pDevIns->Internal.s.pVMR0;
356}
357
358
359/** @copydoc PDMDEVHLPR0::pfnCanEmulateIoBlock */
360static DECLCALLBACK(bool) pdmR0DevHlp_CanEmulateIoBlock(PPDMDEVINS pDevIns)
361{
362 PDMDEV_ASSERT_DEVINS(pDevIns);
363 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
364 return HWACCMCanEmulateIoBlock(pDevIns->Internal.s.pVMR0);
365}
366
367
368
369
370
371/** @copydoc PDMPICHLPR0::pfnSetInterruptFF */
372static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
373{
374 PDMDEV_ASSERT_DEVINS(pDevIns);
375 LogFlow(("pdmR0PicHlp_SetInterruptFF: caller=%p/%d: VM_FF_INTERRUPT_PIC %d -> 1\n",
376 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVMR0, 0, VM_FF_INTERRUPT_PIC)));
377 /* for PIC we always deliver to CPU 0, MP use APIC */
378 VMCPU_FF_SET(pDevIns->Internal.s.pVMR0, 0, VM_FF_INTERRUPT_PIC);
379}
380
381
382/** @copydoc PDMPICHLPR0::pfnClearInterruptFF */
383static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
384{
385 PDMDEV_ASSERT_DEVINS(pDevIns);
386 LogFlow(("pdmR0PicHlp_ClearInterruptFF: caller=%p/%d: VM_FF_INTERRUPT_PIC %d -> 0\n",
387 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVMR0, 0, VM_FF_INTERRUPT_PIC)));
388 /* for PIC we always deliver to CPU 0, MP use APIC */
389 VMCPU_FF_CLEAR(pDevIns->Internal.s.pVMR0, 0, VM_FF_INTERRUPT_PIC);
390}
391
392
393/** @copydoc PDMPICHLPR0::pfnLock */
394static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
395{
396 PDMDEV_ASSERT_DEVINS(pDevIns);
397 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
398}
399
400
401/** @copydoc PDMPICHLPR0::pfnUnlock */
402static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns)
403{
404 PDMDEV_ASSERT_DEVINS(pDevIns);
405 pdmUnlock(pDevIns->Internal.s.pVMR0);
406}
407
408
409
410/** @copydoc PDMAPICHLPR0::pfnSetInterruptFF */
411static DECLCALLBACK(void) pdmR0ApicHlp_SetInterruptFF(PPDMDEVINS pDevIns, VMCPUID idCpu)
412{
413 PDMDEV_ASSERT_DEVINS(pDevIns);
414
415 LogFlow(("pdmR0ApicHlp_SetInterruptFF: caller=%p/%d: VM_FF_INTERRUPT %d -> 1\n",
416 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVMR0, idCpu, VM_FF_INTERRUPT_APIC)));
417 VMCPU_FF_SET(pDevIns->Internal.s.pVMR0, idCpu, VM_FF_INTERRUPT_APIC);
418}
419
420
421/** @copydoc PDMAPICHLPR0::pfnClearInterruptFF */
422static DECLCALLBACK(void) pdmR0ApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, VMCPUID idCpu)
423{
424 PDMDEV_ASSERT_DEVINS(pDevIns);
425
426 LogFlow(("pdmR0ApicHlp_ClearInterruptFF: caller=%p/%d: VM_FF_INTERRUPT %d -> 0\n",
427 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVMR0, idCpu, VM_FF_INTERRUPT_APIC)));
428 VMCPU_FF_CLEAR(pDevIns->Internal.s.pVMR0, idCpu, VM_FF_INTERRUPT_APIC);
429}
430
431
432/** @copydoc PDMAPICHLPR0::pfnChangeFeature */
433static DECLCALLBACK(void) pdmR0ApicHlp_ChangeFeature(PPDMDEVINS pDevIns, PDMAPICVERSION enmVersion)
434{
435 PDMDEV_ASSERT_DEVINS(pDevIns);
436 LogFlow(("pdmR0ApicHlp_ChangeFeature: caller=%p/%d: version=%d\n", pDevIns, pDevIns->iInstance, (int)enmVersion));
437 switch (enmVersion)
438 {
439 case PDMAPICVERSION_NONE:
440 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
441 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
442 break;
443 case PDMAPICVERSION_APIC:
444 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
445 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
446 break;
447 case PDMAPICVERSION_X2APIC:
448 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
449 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
450 break;
451 default:
452 AssertMsgFailed(("Unknown APIC version: %d\n", (int)enmVersion));
453 }
454}
455
456
457/** @copydoc PDMAPICHLPR0::pfnLock */
458static DECLCALLBACK(int) pdmR0ApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
459{
460 PDMDEV_ASSERT_DEVINS(pDevIns);
461 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
462}
463
464
465/** @copydoc PDMAPICHLPR0::pfnUnlock */
466static DECLCALLBACK(void) pdmR0ApicHlp_Unlock(PPDMDEVINS pDevIns)
467{
468 PDMDEV_ASSERT_DEVINS(pDevIns);
469 pdmUnlock(pDevIns->Internal.s.pVMR0);
470}
471
472
473/** @copydoc PDMAPICHLPR0::pfnGetCpuId */
474static DECLCALLBACK(VMCPUID) pdmR0ApicHlp_GetCpuId(PPDMDEVINS pDevIns)
475{
476 PDMDEV_ASSERT_DEVINS(pDevIns);
477 return VMMGetCpuId(pDevIns->Internal.s.pVMR0);
478}
479
480
481/** @copydoc PDMIOAPICHLPR0::pfnApicBusDeliver */
482static DECLCALLBACK(void) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
483 uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode)
484{
485 PDMDEV_ASSERT_DEVINS(pDevIns);
486 PVM pVM = pDevIns->Internal.s.pVMR0;
487 LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 iVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8\n",
488 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
489 Assert(pVM->pdm.s.Apic.pDevInsR0);
490 if (pVM->pdm.s.Apic.pfnBusDeliverR0)
491 pVM->pdm.s.Apic.pfnBusDeliverR0(pVM->pdm.s.Apic.pDevInsR0, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
492}
493
494
495/** @copydoc PDMIOAPICHLPR0::pfnLock */
496static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
497{
498 PDMDEV_ASSERT_DEVINS(pDevIns);
499 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
500}
501
502
503/** @copydoc PDMIOAPICHLPR0::pfnUnlock */
504static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns)
505{
506 PDMDEV_ASSERT_DEVINS(pDevIns);
507 pdmUnlock(pDevIns->Internal.s.pVMR0);
508}
509
510
511
512
513
514/** @copydoc PDMPCIHLPR0::pfnIsaSetIrq */
515static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
516{
517 PDMDEV_ASSERT_DEVINS(pDevIns);
518 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
519 pdmR0IsaSetIrq(pDevIns->Internal.s.pVMR0, iIrq, iLevel);
520}
521
522
523/** @copydoc PDMPCIHLPR0::pfnIoApicSetIrq */
524static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
525{
526 PDMDEV_ASSERT_DEVINS(pDevIns);
527 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
528 pdmR0IoApicSetIrq(pDevIns->Internal.s.pVMR0, iIrq, iLevel);
529}
530
531
532/** @copydoc PDMPCIHLPR0::pfnLock */
533static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
534{
535 PDMDEV_ASSERT_DEVINS(pDevIns);
536 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
537}
538
539
540/** @copydoc PDMPCIHLPR0::pfnUnlock */
541static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns)
542{
543 PDMDEV_ASSERT_DEVINS(pDevIns);
544 pdmUnlock(pDevIns->Internal.s.pVMR0);
545}
546
547
548
549
550/**
551 * Sets an irq on the I/O APIC.
552 *
553 * @param pVM The VM handle.
554 * @param iIrq The irq.
555 * @param iLevel The new level.
556 */
557static void pdmR0IsaSetIrq(PVM pVM, int iIrq, int iLevel)
558{
559 if ( ( pVM->pdm.s.IoApic.pDevInsR0
560 || !pVM->pdm.s.IoApic.pDevInsR3)
561 && ( pVM->pdm.s.Pic.pDevInsR0
562 || !pVM->pdm.s.Pic.pDevInsR3))
563 {
564 pdmLock(pVM);
565 if (pVM->pdm.s.Pic.pDevInsR0)
566 pVM->pdm.s.Pic.pfnSetIrqR0(pVM->pdm.s.Pic.pDevInsR0, iIrq, iLevel);
567 if (pVM->pdm.s.IoApic.pDevInsR0)
568 pVM->pdm.s.IoApic.pfnSetIrqR0(pVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel);
569 pdmUnlock(pVM);
570 }
571 else
572 {
573 /* queue for ring-3 execution. */
574 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
575 if (pTask)
576 {
577 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
578 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
579 pTask->u.SetIRQ.iIrq = iIrq;
580 pTask->u.SetIRQ.iLevel = iLevel;
581
582 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
583 }
584 else
585 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
586 }
587}
588
589
590/**
591 * Sets an irq on the I/O APIC.
592 *
593 * @param pVM The VM handle.
594 * @param iIrq The irq.
595 * @param iLevel The new level.
596 */
597static void pdmR0IoApicSetIrq(PVM pVM, int iIrq, int iLevel)
598{
599 if (pVM->pdm.s.IoApic.pDevInsR0)
600 {
601 pdmLock(pVM);
602 pVM->pdm.s.IoApic.pfnSetIrqR0(pVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel);
603 pdmUnlock(pVM);
604 }
605 else if (pVM->pdm.s.IoApic.pDevInsR3)
606 {
607 /* queue for ring-3 execution. */
608 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
609 if (pTask)
610 {
611 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
612 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
613 pTask->u.SetIRQ.iIrq = iIrq;
614 pTask->u.SetIRQ.iLevel = iLevel;
615
616 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
617 }
618 else
619 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
620 }
621}
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