VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/PDMR0DevHlp.cpp@ 89684

Last change on this file since 89684 was 89620, checked in by vboxsync, 4 years ago

Intel IOMMU: bugref:9967 Allow PDMIoApicSetEoi operation to be queued to ring-3 if I/O APIC isn't available in R0.
This key change is taking the PDM lock such that it doesn't fail (VINF_SUCCESS instead of VINF_IOM_R3_MMIO_WRITE for rcBusy, which wouldn't have worked anyway when called via APICHvSetEoi for instance).
Also cleaned up the prototype of PDMIoApicSendMsi a bit (use PVMCC instead of PPDMDEVINS).
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 69.1 KB
Line 
1/* $Id: PDMR0DevHlp.cpp 89620 2021-06-11 08:51:10Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, R0 Device Helper parts.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
24#include "PDMInternal.h"
25#include <VBox/vmm/pdm.h>
26#include <VBox/vmm/apic.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/gvm.h>
30#include <VBox/vmm/vmm.h>
31#include <VBox/vmm/vmcc.h>
32#include <VBox/vmm/gvmm.h>
33
34#include <VBox/log.h>
35#include <VBox/err.h>
36#include <VBox/sup.h>
37#include <iprt/asm.h>
38#include <iprt/assert.h>
39#include <iprt/ctype.h>
40#include <iprt/string.h>
41
42#include "dtrace/VBoxVMM.h"
43#include "PDMInline.h"
44
45
46/*********************************************************************************************************************************
47* Global Variables *
48*********************************************************************************************************************************/
49RT_C_DECLS_BEGIN
50extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp;
51extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlpTracing;
52extern DECLEXPORT(const PDMPICHLP) g_pdmR0PicHlp;
53extern DECLEXPORT(const PDMIOAPICHLP) g_pdmR0IoApicHlp;
54extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp;
55extern DECLEXPORT(const PDMIOMMUHLPR0) g_pdmR0IommuHlp;
56extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp;
57extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp;
58RT_C_DECLS_END
59
60
61/*********************************************************************************************************************************
62* Internal Functions *
63*********************************************************************************************************************************/
64
65
66/** @name Ring-0 Device Helpers
67 * @{
68 */
69
70/** @interface_method_impl{PDMDEVHLPR0,pfnIoPortSetUpContextEx} */
71static DECLCALLBACK(int) pdmR0DevHlp_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
72 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
73 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
74 void *pvUser)
75{
76 PDMDEV_ASSERT_DEVINS(pDevIns);
77 LogFlow(("pdmR0DevHlp_IoPortSetUpContextEx: caller='%s'/%d: hIoPorts=%#x pfnOut=%p pfnIn=%p pfnOutStr=%p pfnInStr=%p pvUser=%p\n",
78 pDevIns->pReg->szName, pDevIns->iInstance, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser));
79 PGVM pGVM = pDevIns->Internal.s.pGVM;
80 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
81 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
82
83 int rc = IOMR0IoPortSetUpContext(pGVM, pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
84
85 LogFlow(("pdmR0DevHlp_IoPortSetUpContextEx: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
86 return rc;
87}
88
89
90/** @interface_method_impl{PDMDEVHLPR0,pfnMmioSetUpContextEx} */
91static DECLCALLBACK(int) pdmR0DevHlp_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
92 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
93{
94 PDMDEV_ASSERT_DEVINS(pDevIns);
95 LogFlow(("pdmR0DevHlp_MmioSetUpContextEx: caller='%s'/%d: hRegion=%#x pfnWrite=%p pfnRead=%p pfnFill=%p pvUser=%p\n",
96 pDevIns->pReg->szName, pDevIns->iInstance, hRegion, pfnWrite, pfnRead, pfnFill, pvUser));
97 PGVM pGVM = pDevIns->Internal.s.pGVM;
98 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
99 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
100
101 int rc = IOMR0MmioSetUpContext(pGVM, pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
102
103 LogFlow(("pdmR0DevHlp_MmioSetUpContextEx: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
104 return rc;
105}
106
107
108/** @interface_method_impl{PDMDEVHLPR0,pfnMmio2SetUpContext} */
109static DECLCALLBACK(int) pdmR0DevHlp_Mmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
110 size_t offSub, size_t cbSub, void **ppvMapping)
111{
112 PDMDEV_ASSERT_DEVINS(pDevIns);
113 LogFlow(("pdmR0DevHlp_Mmio2SetUpContext: caller='%s'/%d: hRegion=%#x offSub=%#zx cbSub=%#zx ppvMapping=%p\n",
114 pDevIns->pReg->szName, pDevIns->iInstance, hRegion, offSub, cbSub, ppvMapping));
115 *ppvMapping = NULL;
116
117 PGVM pGVM = pDevIns->Internal.s.pGVM;
118 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
119 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
120
121 int rc = PGMR0PhysMMIO2MapKernel(pGVM, pDevIns, hRegion, offSub, cbSub, ppvMapping);
122
123 LogFlow(("pdmR0DevHlp_Mmio2SetUpContext: caller='%s'/%d: returns %Rrc (%p)\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *ppvMapping));
124 return rc;
125}
126
127
128/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysRead} */
129static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
130 void *pvBuf, size_t cbRead, uint32_t fFlags)
131{
132 PDMDEV_ASSERT_DEVINS(pDevIns);
133 if (!pPciDev) /* NULL is an alias for the default PCI device. */
134 pPciDev = pDevIns->apPciDevs[0];
135 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
136 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
137
138#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
139 /*
140 * Just check the busmaster setting here and forward the request to the generic read helper.
141 */
142 if (PCIDevIsBusmaster(pPciDev))
143 { /* likely */ }
144 else
145 {
146 LogFunc(("caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#zx\n", pDevIns, pDevIns->iInstance,
147 VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
148 memset(pvBuf, 0xff, cbRead);
149 return VERR_PDM_NOT_PCI_BUS_MASTER;
150 }
151#endif
152
153#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
154 int rc = pdmIommuMemAccessRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, fFlags);
155 if ( rc == VERR_IOMMU_NOT_PRESENT
156 || rc == VERR_IOMMU_CANNOT_CALL_SELF)
157 { /* likely - ASSUMING most VMs won't be configured with an IOMMU. */ }
158 else
159 return rc;
160#endif
161
162 return pDevIns->pHlpR0->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, fFlags);
163}
164
165
166/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysWrite} */
167static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
168 const void *pvBuf, size_t cbWrite, uint32_t fFlags)
169{
170 PDMDEV_ASSERT_DEVINS(pDevIns);
171 if (!pPciDev) /* NULL is an alias for the default PCI device. */
172 pPciDev = pDevIns->apPciDevs[0];
173 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
174 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
175
176#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
177 /*
178 * Just check the busmaster setting here and forward the request to the generic read helper.
179 */
180 if (PCIDevIsBusmaster(pPciDev))
181 { /* likely */ }
182 else
183 {
184 LogFunc(("caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#zx\n", pDevIns, pDevIns->iInstance,
185 VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
186 return VERR_PDM_NOT_PCI_BUS_MASTER;
187 }
188#endif
189
190#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
191 int rc = pdmIommuMemAccessWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, fFlags);
192 if ( rc == VERR_IOMMU_NOT_PRESENT
193 || rc == VERR_IOMMU_CANNOT_CALL_SELF)
194 { /* likely - ASSUMING most VMs won't be configured with an IOMMU. */ }
195 else
196 return rc;
197#endif
198
199 return pDevIns->pHlpR0->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, fFlags);
200}
201
202
203/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
204static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
205{
206 PDMDEV_ASSERT_DEVINS(pDevIns);
207 if (!pPciDev) /* NULL is an alias for the default PCI device. */
208 pPciDev = pDevIns->apPciDevs[0];
209 AssertReturnVoid(pPciDev);
210 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: pPciDev=%p:{%#x} iIrq=%d iLevel=%d\n",
211 pDevIns, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iIrq, iLevel));
212 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
213
214 PGVM pGVM = pDevIns->Internal.s.pGVM;
215 size_t const idxBus = pPciDev->Int.s.idxPdmBus;
216 AssertReturnVoid(idxBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
217 PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[idxBus];
218
219 pdmLock(pGVM);
220
221 uint32_t uTagSrc;
222 if (iLevel & PDM_IRQ_LEVEL_HIGH)
223 {
224 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
225 if (iLevel == PDM_IRQ_LEVEL_HIGH)
226 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
227 else
228 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
229 }
230 else
231 uTagSrc = pDevIns->Internal.s.pIntR3R0->uLastIrqTag;
232
233 if (pPciBusR0->pDevInsR0)
234 {
235 pPciBusR0->pfnSetIrqR0(pPciBusR0->pDevInsR0, pPciDev, iIrq, iLevel, uTagSrc);
236
237 pdmUnlock(pGVM);
238
239 if (iLevel == PDM_IRQ_LEVEL_LOW)
240 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
241 }
242 else
243 {
244 pdmUnlock(pGVM);
245
246 /* queue for ring-3 execution. */
247 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
248 AssertReturnVoid(pTask);
249
250 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
251 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
252 pTask->u.PciSetIrq.iIrq = iIrq;
253 pTask->u.PciSetIrq.iLevel = iLevel;
254 pTask->u.PciSetIrq.uTagSrc = uTagSrc;
255 pTask->u.PciSetIrq.pPciDevR3 = MMHyperR0ToR3(pGVM, pPciDev);
256
257 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
258 }
259
260 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
261}
262
263
264/** @interface_method_impl{PDMDEVHLPR0,pfnISASetIrq} */
265static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
266{
267 PDMDEV_ASSERT_DEVINS(pDevIns);
268 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
269 PGVM pGVM = pDevIns->Internal.s.pGVM;
270
271 pdmLock(pGVM);
272 uint32_t uTagSrc;
273 if (iLevel & PDM_IRQ_LEVEL_HIGH)
274 {
275 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
276 if (iLevel == PDM_IRQ_LEVEL_HIGH)
277 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
278 else
279 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
280 }
281 else
282 uTagSrc = pDevIns->Internal.s.pIntR3R0->uLastIrqTag;
283
284 bool fRc = pdmR0IsaSetIrq(pGVM, iIrq, iLevel, uTagSrc);
285
286 if (iLevel == PDM_IRQ_LEVEL_LOW && fRc)
287 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
288 pdmUnlock(pGVM);
289 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
290}
291
292
293/** @interface_method_impl{PDMDEVHLPR0,pfnPhysRead} */
294static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags)
295{
296 RT_NOREF(fFlags);
297
298 PDMDEV_ASSERT_DEVINS(pDevIns);
299 LogFlow(("pdmR0DevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
300 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
301
302 VBOXSTRICTRC rcStrict = PGMPhysRead(pDevIns->Internal.s.pGVM, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
303 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
304
305 Log(("pdmR0DevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
306 return VBOXSTRICTRC_VAL(rcStrict);
307}
308
309
310/** @interface_method_impl{PDMDEVHLPR0,pfnPhysWrite} */
311static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags)
312{
313 RT_NOREF(fFlags);
314
315 PDMDEV_ASSERT_DEVINS(pDevIns);
316 LogFlow(("pdmR0DevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
317 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
318
319 VBOXSTRICTRC rcStrict = PGMPhysWrite(pDevIns->Internal.s.pGVM, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
320 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
321
322 Log(("pdmR0DevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
323 return VBOXSTRICTRC_VAL(rcStrict);
324}
325
326
327/** @interface_method_impl{PDMDEVHLPR0,pfnA20IsEnabled} */
328static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
329{
330 PDMDEV_ASSERT_DEVINS(pDevIns);
331 LogFlow(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
332
333 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pGVM));
334
335 Log(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
336 return fEnabled;
337}
338
339
340/** @interface_method_impl{PDMDEVHLPR0,pfnVMState} */
341static DECLCALLBACK(VMSTATE) pdmR0DevHlp_VMState(PPDMDEVINS pDevIns)
342{
343 PDMDEV_ASSERT_DEVINS(pDevIns);
344
345 VMSTATE enmVMState = pDevIns->Internal.s.pGVM->enmVMState;
346
347 LogFlow(("pdmR0DevHlp_VMState: caller=%p/%d: returns %d\n", pDevIns, pDevIns->iInstance, enmVMState));
348 return enmVMState;
349}
350
351
352/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetError} */
353static DECLCALLBACK(int) pdmR0DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
354{
355 PDMDEV_ASSERT_DEVINS(pDevIns);
356 va_list args;
357 va_start(args, pszFormat);
358 int rc2 = VMSetErrorV(pDevIns->Internal.s.pGVM, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
359 va_end(args);
360 return rc;
361}
362
363
364/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetErrorV} */
365static DECLCALLBACK(int) pdmR0DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
366{
367 PDMDEV_ASSERT_DEVINS(pDevIns);
368 int rc2 = VMSetErrorV(pDevIns->Internal.s.pGVM, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
369 return rc;
370}
371
372
373/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeError} */
374static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
375{
376 PDMDEV_ASSERT_DEVINS(pDevIns);
377 va_list va;
378 va_start(va, pszFormat);
379 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pGVM, fFlags, pszErrorId, pszFormat, va);
380 va_end(va);
381 return rc;
382}
383
384
385/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeErrorV} */
386static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
387{
388 PDMDEV_ASSERT_DEVINS(pDevIns);
389 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pGVM, fFlags, pszErrorId, pszFormat, va);
390 return rc;
391}
392
393
394
395/** @interface_method_impl{PDMDEVHLPR0,pfnGetVM} */
396static DECLCALLBACK(PVMCC) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns)
397{
398 PDMDEV_ASSERT_DEVINS(pDevIns);
399 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
400 return pDevIns->Internal.s.pGVM;
401}
402
403
404/** @interface_method_impl{PDMDEVHLPR0,pfnGetVMCPU} */
405static DECLCALLBACK(PVMCPUCC) pdmR0DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
406{
407 PDMDEV_ASSERT_DEVINS(pDevIns);
408 LogFlow(("pdmR0DevHlp_GetVMCPU: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
409 return VMMGetCpu(pDevIns->Internal.s.pGVM);
410}
411
412
413/** @interface_method_impl{PDMDEVHLPRC,pfnGetCurrentCpuId} */
414static DECLCALLBACK(VMCPUID) pdmR0DevHlp_GetCurrentCpuId(PPDMDEVINS pDevIns)
415{
416 PDMDEV_ASSERT_DEVINS(pDevIns);
417 VMCPUID idCpu = VMMGetCpuId(pDevIns->Internal.s.pGVM);
418 LogFlow(("pdmR0DevHlp_GetCurrentCpuId: caller='%p'/%d for CPU %u\n", pDevIns, pDevIns->iInstance, idCpu));
419 return idCpu;
420}
421
422
423/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromMicro} */
424static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
425{
426 PDMDEV_ASSERT_DEVINS(pDevIns);
427 return TMTimerFromMicro(pDevIns->Internal.s.pGVM, hTimer, cMicroSecs);
428}
429
430
431/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromMilli} */
432static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
433{
434 PDMDEV_ASSERT_DEVINS(pDevIns);
435 return TMTimerFromMilli(pDevIns->Internal.s.pGVM, hTimer, cMilliSecs);
436}
437
438
439/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromNano} */
440static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
441{
442 PDMDEV_ASSERT_DEVINS(pDevIns);
443 return TMTimerFromNano(pDevIns->Internal.s.pGVM, hTimer, cNanoSecs);
444}
445
446/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGet} */
447static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
448{
449 PDMDEV_ASSERT_DEVINS(pDevIns);
450 return TMTimerGet(pDevIns->Internal.s.pGVM, hTimer);
451}
452
453
454/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGetFreq} */
455static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
456{
457 PDMDEV_ASSERT_DEVINS(pDevIns);
458 return TMTimerGetFreq(pDevIns->Internal.s.pGVM, hTimer);
459}
460
461
462/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGetNano} */
463static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
464{
465 PDMDEV_ASSERT_DEVINS(pDevIns);
466 return TMTimerGetNano(pDevIns->Internal.s.pGVM, hTimer);
467}
468
469
470/** @interface_method_impl{PDMDEVHLPR0,pfnTimerIsActive} */
471static DECLCALLBACK(bool) pdmR0DevHlp_TimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
472{
473 PDMDEV_ASSERT_DEVINS(pDevIns);
474 return TMTimerIsActive(pDevIns->Internal.s.pGVM, hTimer);
475}
476
477
478/** @interface_method_impl{PDMDEVHLPR0,pfnTimerIsLockOwner} */
479static DECLCALLBACK(bool) pdmR0DevHlp_TimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
480{
481 PDMDEV_ASSERT_DEVINS(pDevIns);
482 return TMTimerIsLockOwner(pDevIns->Internal.s.pGVM, hTimer);
483}
484
485
486/** @interface_method_impl{PDMDEVHLPR0,pfnTimerLockClock} */
487static DECLCALLBACK(VBOXSTRICTRC) pdmR0DevHlp_TimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
488{
489 PDMDEV_ASSERT_DEVINS(pDevIns);
490 return TMTimerLock(pDevIns->Internal.s.pGVM, hTimer, rcBusy);
491}
492
493
494/** @interface_method_impl{PDMDEVHLPR0,pfnTimerLockClock2} */
495static DECLCALLBACK(VBOXSTRICTRC) pdmR0DevHlp_TimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer,
496 PPDMCRITSECT pCritSect, int rcBusy)
497{
498 PDMDEV_ASSERT_DEVINS(pDevIns);
499 VBOXSTRICTRC rc = TMTimerLock(pDevIns->Internal.s.pGVM, hTimer, rcBusy);
500 if (rc == VINF_SUCCESS)
501 {
502 rc = PDMCritSectEnter(pCritSect, rcBusy);
503 if (rc == VINF_SUCCESS)
504 return rc;
505 AssertRC(VBOXSTRICTRC_VAL(rc));
506 TMTimerUnlock(pDevIns->Internal.s.pGVM, hTimer);
507 }
508 else
509 AssertRC(VBOXSTRICTRC_VAL(rc));
510 return rc;
511}
512
513
514/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSet} */
515static DECLCALLBACK(int) pdmR0DevHlp_TimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
516{
517 PDMDEV_ASSERT_DEVINS(pDevIns);
518 return TMTimerSet(pDevIns->Internal.s.pGVM, hTimer, uExpire);
519}
520
521
522/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetFrequencyHint} */
523static DECLCALLBACK(int) pdmR0DevHlp_TimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
524{
525 PDMDEV_ASSERT_DEVINS(pDevIns);
526 return TMTimerSetFrequencyHint(pDevIns->Internal.s.pGVM, hTimer, uHz);
527}
528
529
530/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetMicro} */
531static DECLCALLBACK(int) pdmR0DevHlp_TimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
532{
533 PDMDEV_ASSERT_DEVINS(pDevIns);
534 return TMTimerSetMicro(pDevIns->Internal.s.pGVM, hTimer, cMicrosToNext);
535}
536
537
538/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetMillies} */
539static DECLCALLBACK(int) pdmR0DevHlp_TimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
540{
541 PDMDEV_ASSERT_DEVINS(pDevIns);
542 return TMTimerSetMillies(pDevIns->Internal.s.pGVM, hTimer, cMilliesToNext);
543}
544
545
546/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetNano} */
547static DECLCALLBACK(int) pdmR0DevHlp_TimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
548{
549 PDMDEV_ASSERT_DEVINS(pDevIns);
550 return TMTimerSetNano(pDevIns->Internal.s.pGVM, hTimer, cNanosToNext);
551}
552
553
554/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetRelative} */
555static DECLCALLBACK(int) pdmR0DevHlp_TimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
556{
557 PDMDEV_ASSERT_DEVINS(pDevIns);
558 return TMTimerSetRelative(pDevIns->Internal.s.pGVM, hTimer, cTicksToNext, pu64Now);
559}
560
561
562/** @interface_method_impl{PDMDEVHLPR0,pfnTimerStop} */
563static DECLCALLBACK(int) pdmR0DevHlp_TimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
564{
565 PDMDEV_ASSERT_DEVINS(pDevIns);
566 return TMTimerStop(pDevIns->Internal.s.pGVM, hTimer);
567}
568
569
570/** @interface_method_impl{PDMDEVHLPR0,pfnTimerUnlockClock} */
571static DECLCALLBACK(void) pdmR0DevHlp_TimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
572{
573 PDMDEV_ASSERT_DEVINS(pDevIns);
574 TMTimerUnlock(pDevIns->Internal.s.pGVM, hTimer);
575}
576
577
578/** @interface_method_impl{PDMDEVHLPR0,pfnTimerUnlockClock2} */
579static DECLCALLBACK(void) pdmR0DevHlp_TimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
580{
581 PDMDEV_ASSERT_DEVINS(pDevIns);
582 TMTimerUnlock(pDevIns->Internal.s.pGVM, hTimer);
583 int rc = PDMCritSectLeave(pCritSect);
584 AssertRC(rc);
585}
586
587
588/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGet} */
589static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
590{
591 PDMDEV_ASSERT_DEVINS(pDevIns);
592 LogFlow(("pdmR0DevHlp_TMTimeVirtGet: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
593 return TMVirtualGet(pDevIns->Internal.s.pGVM);
594}
595
596
597/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetFreq} */
598static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
599{
600 PDMDEV_ASSERT_DEVINS(pDevIns);
601 LogFlow(("pdmR0DevHlp_TMTimeVirtGetFreq: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
602 return TMVirtualGetFreq(pDevIns->Internal.s.pGVM);
603}
604
605
606/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetNano} */
607static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
608{
609 PDMDEV_ASSERT_DEVINS(pDevIns);
610 LogFlow(("pdmR0DevHlp_TMTimeVirtGetNano: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
611 return TMVirtualToNano(pDevIns->Internal.s.pGVM, TMVirtualGet(pDevIns->Internal.s.pGVM));
612}
613
614
615/** @interface_method_impl{PDMDEVHLPR0,pfnQueueToPtr} */
616static DECLCALLBACK(PPDMQUEUE) pdmR0DevHlp_QueueToPtr(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
617{
618 PDMDEV_ASSERT_DEVINS(pDevIns);
619 RT_NOREF(pDevIns);
620 return (PPDMQUEUE)MMHyperR3ToCC(pDevIns->Internal.s.pGVM, hQueue);
621}
622
623
624/** @interface_method_impl{PDMDEVHLPR0,pfnQueueAlloc} */
625static DECLCALLBACK(PPDMQUEUEITEMCORE) pdmR0DevHlp_QueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
626{
627 return PDMQueueAlloc(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue));
628}
629
630
631/** @interface_method_impl{PDMDEVHLPR0,pfnQueueInsert} */
632static DECLCALLBACK(void) pdmR0DevHlp_QueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
633{
634 return PDMQueueInsert(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue), pItem);
635}
636
637
638/** @interface_method_impl{PDMDEVHLPR0,pfnQueueInsertEx} */
639static DECLCALLBACK(void) pdmR0DevHlp_QueueInsertEx(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem,
640 uint64_t cNanoMaxDelay)
641{
642 return PDMQueueInsertEx(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue), pItem, cNanoMaxDelay);
643}
644
645
646/** @interface_method_impl{PDMDEVHLPR0,pfnQueueFlushIfNecessary} */
647static DECLCALLBACK(bool) pdmR0DevHlp_QueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
648{
649 return PDMQueueFlushIfNecessary(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue));
650}
651
652
653/** @interface_method_impl{PDMDEVHLPR0,pfnTaskTrigger} */
654static DECLCALLBACK(int) pdmR0DevHlp_TaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
655{
656 PDMDEV_ASSERT_DEVINS(pDevIns);
657 LogFlow(("pdmR0DevHlp_TaskTrigger: caller='%s'/%d: hTask=%RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, hTask));
658
659 int rc = PDMTaskTrigger(pDevIns->Internal.s.pGVM, PDMTASKTYPE_DEV, pDevIns->pDevInsForR3, hTask);
660
661 LogFlow(("pdmR0DevHlp_TaskTrigger: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
662 return rc;
663}
664
665
666/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventSignal} */
667static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
668{
669 PDMDEV_ASSERT_DEVINS(pDevIns);
670 LogFlow(("pdmR0DevHlp_SUPSemEventSignal: caller='%s'/%d: hEvent=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEvent));
671
672 int rc = SUPSemEventSignal(pDevIns->Internal.s.pGVM->pSession, hEvent);
673
674 LogFlow(("pdmR0DevHlp_SUPSemEventSignal: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
675 return rc;
676}
677
678
679/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNoResume} */
680static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
681{
682 PDMDEV_ASSERT_DEVINS(pDevIns);
683 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNoResume: caller='%s'/%d: hEvent=%p cNsTimeout=%RU32\n",
684 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, cMillies));
685
686 int rc = SUPSemEventWaitNoResume(pDevIns->Internal.s.pGVM->pSession, hEvent, cMillies);
687
688 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNoResume: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
689 return rc;
690}
691
692
693/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNsAbsIntr} */
694static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
695{
696 PDMDEV_ASSERT_DEVINS(pDevIns);
697 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsAbsIntr: caller='%s'/%d: hEvent=%p uNsTimeout=%RU64\n",
698 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, uNsTimeout));
699
700 int rc = SUPSemEventWaitNsAbsIntr(pDevIns->Internal.s.pGVM->pSession, hEvent, uNsTimeout);
701
702 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsAbsIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
703 return rc;
704}
705
706
707/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNsRelIntr} */
708static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
709{
710 PDMDEV_ASSERT_DEVINS(pDevIns);
711 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsRelIntr: caller='%s'/%d: hEvent=%p cNsTimeout=%RU64\n",
712 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, cNsTimeout));
713
714 int rc = SUPSemEventWaitNsRelIntr(pDevIns->Internal.s.pGVM->pSession, hEvent, cNsTimeout);
715
716 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsRelIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
717 return rc;
718}
719
720
721/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventGetResolution} */
722static DECLCALLBACK(uint32_t) pdmR0DevHlp_SUPSemEventGetResolution(PPDMDEVINS pDevIns)
723{
724 PDMDEV_ASSERT_DEVINS(pDevIns);
725 LogFlow(("pdmR0DevHlp_SUPSemEventGetResolution: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
726
727 uint32_t cNsResolution = SUPSemEventGetResolution(pDevIns->Internal.s.pGVM->pSession);
728
729 LogFlow(("pdmR0DevHlp_SUPSemEventGetResolution: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, cNsResolution));
730 return cNsResolution;
731}
732
733
734/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiSignal} */
735static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
736{
737 PDMDEV_ASSERT_DEVINS(pDevIns);
738 LogFlow(("pdmR0DevHlp_SUPSemEventMultiSignal: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
739
740 int rc = SUPSemEventMultiSignal(pDevIns->Internal.s.pGVM->pSession, hEventMulti);
741
742 LogFlow(("pdmR0DevHlp_SUPSemEventMultiSignal: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
743 return rc;
744}
745
746
747/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiReset} */
748static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
749{
750 PDMDEV_ASSERT_DEVINS(pDevIns);
751 LogFlow(("pdmR0DevHlp_SUPSemEventMultiReset: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
752
753 int rc = SUPSemEventMultiReset(pDevIns->Internal.s.pGVM->pSession, hEventMulti);
754
755 LogFlow(("pdmR0DevHlp_SUPSemEventMultiReset: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
756 return rc;
757}
758
759
760/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNoResume} */
761static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
762 uint32_t cMillies)
763{
764 PDMDEV_ASSERT_DEVINS(pDevIns);
765 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNoResume: caller='%s'/%d: hEventMulti=%p cMillies=%RU32\n",
766 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, cMillies));
767
768 int rc = SUPSemEventMultiWaitNoResume(pDevIns->Internal.s.pGVM->pSession, hEventMulti, cMillies);
769
770 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNoResume: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
771 return rc;
772}
773
774
775/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNsAbsIntr} */
776static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
777 uint64_t uNsTimeout)
778{
779 PDMDEV_ASSERT_DEVINS(pDevIns);
780 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr: caller='%s'/%d: hEventMulti=%p uNsTimeout=%RU64\n",
781 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, uNsTimeout));
782
783 int rc = SUPSemEventMultiWaitNsAbsIntr(pDevIns->Internal.s.pGVM->pSession, hEventMulti, uNsTimeout);
784
785 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
786 return rc;
787}
788
789
790/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNsRelIntr} */
791static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
792 uint64_t cNsTimeout)
793{
794 PDMDEV_ASSERT_DEVINS(pDevIns);
795 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr: caller='%s'/%d: hEventMulti=%p cNsTimeout=%RU64\n",
796 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, cNsTimeout));
797
798 int rc = SUPSemEventMultiWaitNsRelIntr(pDevIns->Internal.s.pGVM->pSession, hEventMulti, cNsTimeout);
799
800 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
801 return rc;
802}
803
804
805/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiGetResolution} */
806static DECLCALLBACK(uint32_t) pdmR0DevHlp_SUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
807{
808 PDMDEV_ASSERT_DEVINS(pDevIns);
809 LogFlow(("pdmR0DevHlp_SUPSemEventMultiGetResolution: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
810
811 uint32_t cNsResolution = SUPSemEventMultiGetResolution(pDevIns->Internal.s.pGVM->pSession);
812
813 LogFlow(("pdmR0DevHlp_SUPSemEventMultiGetResolution: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, cNsResolution));
814 return cNsResolution;
815}
816
817
818/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectGetNop} */
819static DECLCALLBACK(PPDMCRITSECT) pdmR0DevHlp_CritSectGetNop(PPDMDEVINS pDevIns)
820{
821 PDMDEV_ASSERT_DEVINS(pDevIns);
822 PGVM pGVM = pDevIns->Internal.s.pGVM;
823
824 PPDMCRITSECT pCritSect = &pGVM->pdm.s.NopCritSect;
825 LogFlow(("pdmR0DevHlp_CritSectGetNop: caller='%s'/%d: return %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
826 return pCritSect;
827}
828
829
830/** @interface_method_impl{PDMDEVHLPR0,pfnSetDeviceCritSect} */
831static DECLCALLBACK(int) pdmR0DevHlp_SetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
832{
833 /*
834 * Validate input.
835 *
836 * Note! We only allow the automatically created default critical section
837 * to be replaced by this API.
838 */
839 PDMDEV_ASSERT_DEVINS(pDevIns);
840 AssertPtrReturn(pCritSect, VERR_INVALID_POINTER);
841 LogFlow(("pdmR0DevHlp_SetDeviceCritSect: caller='%s'/%d: pCritSect=%p (%s)\n",
842 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect, pCritSect->s.pszName));
843 AssertReturn(PDMCritSectIsInitialized(pCritSect), VERR_INVALID_PARAMETER);
844 PGVM pGVM = pDevIns->Internal.s.pGVM;
845 AssertReturn(pCritSect->s.pVMR0 == pGVM, VERR_INVALID_PARAMETER);
846
847 VM_ASSERT_EMT(pGVM);
848 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
849
850 /*
851 * Check that ring-3 has already done this, then effect the change.
852 */
853 AssertReturn(pDevIns->pDevInsForR3R0->Internal.s.fIntFlags & PDMDEVINSINT_FLAGS_CHANGED_CRITSECT, VERR_WRONG_ORDER);
854 pDevIns->pCritSectRoR0 = pCritSect;
855
856 LogFlow(("pdmR0DevHlp_SetDeviceCritSect: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
857 return VINF_SUCCESS;
858}
859
860
861/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectEnter} */
862static DECLCALLBACK(int) pdmR0DevHlp_CritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
863{
864 PDMDEV_ASSERT_DEVINS(pDevIns);
865 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
866 return PDMCritSectEnter(pCritSect, rcBusy);
867}
868
869
870/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectEnterDebug} */
871static DECLCALLBACK(int) pdmR0DevHlp_CritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
872{
873 PDMDEV_ASSERT_DEVINS(pDevIns);
874 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
875 return PDMCritSectEnterDebug(pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
876}
877
878
879/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectTryEnter} */
880static DECLCALLBACK(int) pdmR0DevHlp_CritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
881{
882 PDMDEV_ASSERT_DEVINS(pDevIns);
883 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
884 return PDMCritSectTryEnter(pCritSect);
885}
886
887
888/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectTryEnterDebug} */
889static DECLCALLBACK(int) pdmR0DevHlp_CritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
890{
891 PDMDEV_ASSERT_DEVINS(pDevIns);
892 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
893 return PDMCritSectTryEnterDebug(pCritSect, uId, RT_SRC_POS_ARGS);
894}
895
896
897/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectLeave} */
898static DECLCALLBACK(int) pdmR0DevHlp_CritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
899{
900 PDMDEV_ASSERT_DEVINS(pDevIns);
901 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
902 return PDMCritSectLeave(pCritSect);
903}
904
905
906/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectIsOwner} */
907static DECLCALLBACK(bool) pdmR0DevHlp_CritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
908{
909 PDMDEV_ASSERT_DEVINS(pDevIns);
910 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
911 return PDMCritSectIsOwner(pCritSect);
912}
913
914
915/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectIsInitialized} */
916static DECLCALLBACK(bool) pdmR0DevHlp_CritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
917{
918 PDMDEV_ASSERT_DEVINS(pDevIns);
919 RT_NOREF(pDevIns);
920 return PDMCritSectIsInitialized(pCritSect);
921}
922
923
924/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectHasWaiters} */
925static DECLCALLBACK(bool) pdmR0DevHlp_CritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
926{
927 PDMDEV_ASSERT_DEVINS(pDevIns);
928 RT_NOREF(pDevIns);
929 return PDMCritSectHasWaiters(pCritSect);
930}
931
932
933/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectGetRecursion} */
934static DECLCALLBACK(uint32_t) pdmR0DevHlp_CritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
935{
936 PDMDEV_ASSERT_DEVINS(pDevIns);
937 RT_NOREF(pDevIns);
938 return PDMCritSectGetRecursion(pCritSect);
939}
940
941
942/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectScheduleExitEvent} */
943static DECLCALLBACK(int) pdmR0DevHlp_CritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect,
944 SUPSEMEVENT hEventToSignal)
945{
946 PDMDEV_ASSERT_DEVINS(pDevIns);
947 RT_NOREF(pDevIns);
948 return PDMHCCritSectScheduleExitEvent(pCritSect, hEventToSignal);
949}
950
951
952/** @interface_method_impl{PDMDEVHLPR0,pfnDBGFTraceBuf} */
953static DECLCALLBACK(RTTRACEBUF) pdmR0DevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
954{
955 PDMDEV_ASSERT_DEVINS(pDevIns);
956 RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pGVM->hTraceBufR0;
957 LogFlow(("pdmR0DevHlp_DBGFTraceBuf: caller='%p'/%d: returns %p\n", pDevIns, pDevIns->iInstance, hTraceBuf));
958 return hTraceBuf;
959}
960
961
962/** @interface_method_impl{PDMDEVHLPR0,pfnPCIBusSetUpContext} */
963static DECLCALLBACK(int) pdmR0DevHlp_PCIBusSetUpContext(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp)
964{
965 PDMDEV_ASSERT_DEVINS(pDevIns);
966 LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: pPciBusReg=%p{.u32Version=%#x, .iBus=%#u, .pfnSetIrq=%p, u32EnvVersion=%#x} ppPciHlp=%p\n",
967 pDevIns, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->iBus, pPciBusReg->pfnSetIrq,
968 pPciBusReg->u32EndVersion, ppPciHlp));
969 PGVM pGVM = pDevIns->Internal.s.pGVM;
970
971 /*
972 * Validate input.
973 */
974 AssertPtrReturn(pPciBusReg, VERR_INVALID_POINTER);
975 AssertLogRelMsgReturn(pPciBusReg->u32Version == PDM_PCIBUSREGCC_VERSION,
976 ("%#x vs %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
977 AssertPtrReturn(pPciBusReg->pfnSetIrq, VERR_INVALID_POINTER);
978 AssertLogRelMsgReturn(pPciBusReg->u32EndVersion == PDM_PCIBUSREGCC_VERSION,
979 ("%#x vs %#x\n", pPciBusReg->u32EndVersion, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
980
981 AssertPtrReturn(ppPciHlp, VERR_INVALID_POINTER);
982
983 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
984 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
985
986 /* Check the shared bus data (registered earlier from ring-3): */
987 uint32_t iBus = pPciBusReg->iBus;
988 ASMCompilerBarrier();
989 AssertLogRelMsgReturn(iBus < RT_ELEMENTS(pGVM->pdm.s.aPciBuses), ("iBus=%#x\n", iBus), VERR_OUT_OF_RANGE);
990 PPDMPCIBUS pPciBusShared = &pGVM->pdm.s.aPciBuses[iBus];
991 AssertLogRelMsgReturn(pPciBusShared->iBus == iBus, ("%u vs %u\n", pPciBusShared->iBus, iBus), VERR_INVALID_PARAMETER);
992 AssertLogRelMsgReturn(pPciBusShared->pDevInsR3 == pDevIns->pDevInsForR3,
993 ("%p vs %p (iBus=%u)\n", pPciBusShared->pDevInsR3, pDevIns->pDevInsForR3, iBus), VERR_NOT_OWNER);
994
995 /* Check that the bus isn't already registered in ring-0: */
996 AssertCompile(RT_ELEMENTS(pGVM->pdm.s.aPciBuses) == RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
997 PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[iBus];
998 AssertLogRelMsgReturn(pPciBusR0->pDevInsR0 == NULL,
999 ("%p (caller pDevIns=%p, iBus=%u)\n", pPciBusR0->pDevInsR0, pDevIns, iBus),
1000 VERR_ALREADY_EXISTS);
1001
1002 /*
1003 * Do the registering.
1004 */
1005 pPciBusR0->iBus = iBus;
1006 pPciBusR0->uPadding0 = 0xbeefbeef;
1007 pPciBusR0->pfnSetIrqR0 = pPciBusReg->pfnSetIrq;
1008 pPciBusR0->pDevInsR0 = pDevIns;
1009
1010 *ppPciHlp = &g_pdmR0PciHlp;
1011
1012 LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: returns VINF_SUCCESS\n", pDevIns, pDevIns->iInstance));
1013 return VINF_SUCCESS;
1014}
1015
1016
1017/** @interface_method_impl{PDMDEVHLPR0,pfnIommuSetUpContext} */
1018static DECLCALLBACK(int) pdmR0DevHlp_IommuSetUpContext(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp)
1019{
1020 PDMDEV_ASSERT_DEVINS(pDevIns);
1021 LogFlow(("pdmR0DevHlp_IommuSetUpContext: caller='%p'/%d: pIommuReg=%p{.u32Version=%#x, u32TheEnd=%#x} ppIommuHlp=%p\n",
1022 pDevIns, pDevIns->iInstance, pIommuReg, pIommuReg->u32Version, pIommuReg->u32TheEnd, ppIommuHlp));
1023 PGVM pGVM = pDevIns->Internal.s.pGVM;
1024
1025 /*
1026 * Validate input.
1027 */
1028 AssertPtrReturn(pIommuReg, VERR_INVALID_POINTER);
1029 AssertLogRelMsgReturn(pIommuReg->u32Version == PDM_IOMMUREGCC_VERSION,
1030 ("%#x vs %#x\n", pIommuReg->u32Version, PDM_IOMMUREGCC_VERSION), VERR_VERSION_MISMATCH);
1031 AssertPtrReturn(pIommuReg->pfnMemAccess, VERR_INVALID_POINTER);
1032 AssertPtrReturn(pIommuReg->pfnMemBulkAccess, VERR_INVALID_POINTER);
1033 AssertPtrReturn(pIommuReg->pfnMsiRemap, VERR_INVALID_POINTER);
1034 AssertLogRelMsgReturn(pIommuReg->u32TheEnd == PDM_IOMMUREGCC_VERSION,
1035 ("%#x vs %#x\n", pIommuReg->u32TheEnd, PDM_IOMMUREGCC_VERSION), VERR_VERSION_MISMATCH);
1036
1037 AssertPtrReturn(ppIommuHlp, VERR_INVALID_POINTER);
1038
1039 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1040 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1041
1042 /* Check the IOMMU shared data (registered earlier from ring-3). */
1043 uint32_t const idxIommu = pIommuReg->idxIommu;
1044 ASMCompilerBarrier();
1045 AssertLogRelMsgReturn(idxIommu < RT_ELEMENTS(pGVM->pdm.s.aIommus), ("idxIommu=%#x\n", idxIommu), VERR_OUT_OF_RANGE);
1046 PPDMIOMMUR3 pIommuShared = &pGVM->pdm.s.aIommus[idxIommu];
1047 AssertLogRelMsgReturn(pIommuShared->idxIommu == idxIommu, ("%u vs %u\n", pIommuShared->idxIommu, idxIommu), VERR_INVALID_PARAMETER);
1048 AssertLogRelMsgReturn(pIommuShared->pDevInsR3 == pDevIns->pDevInsForR3,
1049 ("%p vs %p (idxIommu=%u)\n", pIommuShared->pDevInsR3, pDevIns->pDevInsForR3, idxIommu), VERR_NOT_OWNER);
1050
1051 /* Check that the IOMMU isn't already registered in ring-0. */
1052 AssertCompile(RT_ELEMENTS(pGVM->pdm.s.aIommus) == RT_ELEMENTS(pGVM->pdmr0.s.aIommus));
1053 PPDMIOMMUR0 pIommuR0 = &pGVM->pdmr0.s.aIommus[idxIommu];
1054 AssertLogRelMsgReturn(pIommuR0->pDevInsR0 == NULL,
1055 ("%p (caller pDevIns=%p, idxIommu=%u)\n", pIommuR0->pDevInsR0, pDevIns, idxIommu),
1056 VERR_ALREADY_EXISTS);
1057
1058 /*
1059 * Register.
1060 */
1061 pIommuR0->idxIommu = idxIommu;
1062 pIommuR0->uPadding0 = 0xdeaddead;
1063 pIommuR0->pDevInsR0 = pDevIns;
1064 pIommuR0->pfnMemAccess = pIommuReg->pfnMemAccess;
1065 pIommuR0->pfnMemBulkAccess = pIommuReg->pfnMemBulkAccess;
1066 pIommuR0->pfnMsiRemap = pIommuReg->pfnMsiRemap;
1067
1068 *ppIommuHlp = &g_pdmR0IommuHlp;
1069
1070 LogFlow(("pdmR0DevHlp_IommuSetUpContext: caller='%p'/%d: returns VINF_SUCCESS\n", pDevIns, pDevIns->iInstance));
1071 return VINF_SUCCESS;
1072}
1073
1074
1075/** @interface_method_impl{PDMDEVHLPR0,pfnPICSetUpContext} */
1076static DECLCALLBACK(int) pdmR0DevHlp_PICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
1077{
1078 PDMDEV_ASSERT_DEVINS(pDevIns);
1079 LogFlow(("pdmR0DevHlp_PICSetUpContext: caller='%s'/%d: pPicReg=%p:{.u32Version=%#x, .pfnSetIrq=%p, .pfnGetInterrupt=%p, .u32TheEnd=%#x } ppPicHlp=%p\n",
1080 pDevIns->pReg->szName, pDevIns->iInstance, pPicReg, pPicReg->u32Version, pPicReg->pfnSetIrq, pPicReg->pfnGetInterrupt, pPicReg->u32TheEnd, ppPicHlp));
1081 PGVM pGVM = pDevIns->Internal.s.pGVM;
1082
1083 /*
1084 * Validate input.
1085 */
1086 AssertMsgReturn(pPicReg->u32Version == PDM_PICREG_VERSION,
1087 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pPicReg->u32Version, PDM_PICREG_VERSION),
1088 VERR_VERSION_MISMATCH);
1089 AssertPtrReturn(pPicReg->pfnSetIrq, VERR_INVALID_POINTER);
1090 AssertPtrReturn(pPicReg->pfnGetInterrupt, VERR_INVALID_POINTER);
1091 AssertMsgReturn(pPicReg->u32TheEnd == PDM_PICREG_VERSION,
1092 ("%s/%d: u32TheEnd=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pPicReg->u32TheEnd, PDM_PICREG_VERSION),
1093 VERR_VERSION_MISMATCH);
1094 AssertPtrReturn(ppPicHlp, VERR_INVALID_POINTER);
1095
1096 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1097 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1098
1099 /* Check that it's the same device as made the ring-3 registrations: */
1100 AssertLogRelMsgReturn(pGVM->pdm.s.Pic.pDevInsR3 == pDevIns->pDevInsForR3,
1101 ("%p vs %p\n", pGVM->pdm.s.Pic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1102
1103 /* Check that it isn't already registered in ring-0: */
1104 AssertLogRelMsgReturn(pGVM->pdm.s.Pic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Pic.pDevInsR0, pDevIns),
1105 VERR_ALREADY_EXISTS);
1106
1107 /*
1108 * Take down the callbacks and instance.
1109 */
1110 pGVM->pdm.s.Pic.pDevInsR0 = pDevIns;
1111 pGVM->pdm.s.Pic.pfnSetIrqR0 = pPicReg->pfnSetIrq;
1112 pGVM->pdm.s.Pic.pfnGetInterruptR0 = pPicReg->pfnGetInterrupt;
1113 Log(("PDM: Registered PIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1114
1115 /* set the helper pointer and return. */
1116 *ppPicHlp = &g_pdmR0PicHlp;
1117 LogFlow(("pdmR0DevHlp_PICSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1118 return VINF_SUCCESS;
1119}
1120
1121
1122/** @interface_method_impl{PDMDEVHLPR0,pfnApicSetUpContext} */
1123static DECLCALLBACK(int) pdmR0DevHlp_ApicSetUpContext(PPDMDEVINS pDevIns)
1124{
1125 PDMDEV_ASSERT_DEVINS(pDevIns);
1126 LogFlow(("pdmR0DevHlp_ApicSetUpContext: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
1127 PGVM pGVM = pDevIns->Internal.s.pGVM;
1128
1129 /*
1130 * Validate input.
1131 */
1132 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1133 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1134
1135 /* Check that it's the same device as made the ring-3 registrations: */
1136 AssertLogRelMsgReturn(pGVM->pdm.s.Apic.pDevInsR3 == pDevIns->pDevInsForR3,
1137 ("%p vs %p\n", pGVM->pdm.s.Apic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1138
1139 /* Check that it isn't already registered in ring-0: */
1140 AssertLogRelMsgReturn(pGVM->pdm.s.Apic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Apic.pDevInsR0, pDevIns),
1141 VERR_ALREADY_EXISTS);
1142
1143 /*
1144 * Take down the instance.
1145 */
1146 pGVM->pdm.s.Apic.pDevInsR0 = pDevIns;
1147 Log(("PDM: Registered APIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1148
1149 /* set the helper pointer and return. */
1150 LogFlow(("pdmR0DevHlp_ApicSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1151 return VINF_SUCCESS;
1152}
1153
1154
1155/** @interface_method_impl{PDMDEVHLPR0,pfnIoApicSetUpContext} */
1156static DECLCALLBACK(int) pdmR0DevHlp_IoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
1157{
1158 PDMDEV_ASSERT_DEVINS(pDevIns);
1159 LogFlow(("pdmR0DevHlp_IoApicSetUpContext: caller='%s'/%d: pIoApicReg=%p:{.u32Version=%#x, .pfnSetIrq=%p, .pfnSendMsi=%p, .pfnSetEoi=%p, .u32TheEnd=%#x } ppIoApicHlp=%p\n",
1160 pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg, pIoApicReg->u32Version, pIoApicReg->pfnSetIrq, pIoApicReg->pfnSendMsi, pIoApicReg->pfnSetEoi, pIoApicReg->u32TheEnd, ppIoApicHlp));
1161 PGVM pGVM = pDevIns->Internal.s.pGVM;
1162
1163 /*
1164 * Validate input.
1165 */
1166 AssertMsgReturn(pIoApicReg->u32Version == PDM_IOAPICREG_VERSION,
1167 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg->u32Version, PDM_IOAPICREG_VERSION),
1168 VERR_VERSION_MISMATCH);
1169 AssertPtrReturn(pIoApicReg->pfnSetIrq, VERR_INVALID_POINTER);
1170 AssertPtrReturn(pIoApicReg->pfnSendMsi, VERR_INVALID_POINTER);
1171 AssertPtrReturn(pIoApicReg->pfnSetEoi, VERR_INVALID_POINTER);
1172 AssertMsgReturn(pIoApicReg->u32TheEnd == PDM_IOAPICREG_VERSION,
1173 ("%s/%d: u32TheEnd=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg->u32TheEnd, PDM_IOAPICREG_VERSION),
1174 VERR_VERSION_MISMATCH);
1175 AssertPtrReturn(ppIoApicHlp, VERR_INVALID_POINTER);
1176
1177 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1178 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1179
1180 /* Check that it's the same device as made the ring-3 registrations: */
1181 AssertLogRelMsgReturn(pGVM->pdm.s.IoApic.pDevInsR3 == pDevIns->pDevInsForR3,
1182 ("%p vs %p\n", pGVM->pdm.s.IoApic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1183
1184 /* Check that it isn't already registered in ring-0: */
1185 AssertLogRelMsgReturn(pGVM->pdm.s.IoApic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.IoApic.pDevInsR0, pDevIns),
1186 VERR_ALREADY_EXISTS);
1187
1188 /*
1189 * Take down the callbacks and instance.
1190 */
1191 pGVM->pdm.s.IoApic.pDevInsR0 = pDevIns;
1192 pGVM->pdm.s.IoApic.pfnSetIrqR0 = pIoApicReg->pfnSetIrq;
1193 pGVM->pdm.s.IoApic.pfnSendMsiR0 = pIoApicReg->pfnSendMsi;
1194 pGVM->pdm.s.IoApic.pfnSetEoiR0 = pIoApicReg->pfnSetEoi;
1195 Log(("PDM: Registered IOAPIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1196
1197 /* set the helper pointer and return. */
1198 *ppIoApicHlp = &g_pdmR0IoApicHlp;
1199 LogFlow(("pdmR0DevHlp_IoApicSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1200 return VINF_SUCCESS;
1201}
1202
1203
1204/** @interface_method_impl{PDMDEVHLPR0,pfnHpetSetUpContext} */
1205static DECLCALLBACK(int) pdmR0DevHlp_HpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp)
1206{
1207 PDMDEV_ASSERT_DEVINS(pDevIns);
1208 LogFlow(("pdmR0DevHlp_HpetSetUpContext: caller='%s'/%d: pHpetReg=%p:{.u32Version=%#x, } ppHpetHlp=%p\n",
1209 pDevIns->pReg->szName, pDevIns->iInstance, pHpetReg, pHpetReg->u32Version, ppHpetHlp));
1210 PGVM pGVM = pDevIns->Internal.s.pGVM;
1211
1212 /*
1213 * Validate input.
1214 */
1215 AssertMsgReturn(pHpetReg->u32Version == PDM_HPETREG_VERSION,
1216 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pHpetReg->u32Version, PDM_HPETREG_VERSION),
1217 VERR_VERSION_MISMATCH);
1218 AssertPtrReturn(ppHpetHlp, VERR_INVALID_POINTER);
1219
1220 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1221 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1222
1223 /* Check that it's the same device as made the ring-3 registrations: */
1224 AssertLogRelMsgReturn(pGVM->pdm.s.pHpet == pDevIns->pDevInsForR3, ("%p vs %p\n", pGVM->pdm.s.pHpet, pDevIns->pDevInsForR3),
1225 VERR_NOT_OWNER);
1226
1227 ///* Check that it isn't already registered in ring-0: */
1228 //AssertLogRelMsgReturn(pGVM->pdm.s.Hpet.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Hpet.pDevInsR0, pDevIns),
1229 // VERR_ALREADY_EXISTS);
1230
1231 /*
1232 * Nothing to take down here at present.
1233 */
1234 Log(("PDM: Registered HPET device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1235
1236 /* set the helper pointer and return. */
1237 *ppHpetHlp = &g_pdmR0HpetHlp;
1238 LogFlow(("pdmR0DevHlp_HpetSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1239 return VINF_SUCCESS;
1240}
1241
1242
1243/**
1244 * The Ring-0 Device Helper Callbacks.
1245 */
1246extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp =
1247{
1248 PDM_DEVHLPR0_VERSION,
1249 pdmR0DevHlp_IoPortSetUpContextEx,
1250 pdmR0DevHlp_MmioSetUpContextEx,
1251 pdmR0DevHlp_Mmio2SetUpContext,
1252 pdmR0DevHlp_PCIPhysRead,
1253 pdmR0DevHlp_PCIPhysWrite,
1254 pdmR0DevHlp_PCISetIrq,
1255 pdmR0DevHlp_ISASetIrq,
1256 pdmR0DevHlp_PhysRead,
1257 pdmR0DevHlp_PhysWrite,
1258 pdmR0DevHlp_A20IsEnabled,
1259 pdmR0DevHlp_VMState,
1260 pdmR0DevHlp_VMSetError,
1261 pdmR0DevHlp_VMSetErrorV,
1262 pdmR0DevHlp_VMSetRuntimeError,
1263 pdmR0DevHlp_VMSetRuntimeErrorV,
1264 pdmR0DevHlp_GetVM,
1265 pdmR0DevHlp_GetVMCPU,
1266 pdmR0DevHlp_GetCurrentCpuId,
1267 pdmR0DevHlp_TimerFromMicro,
1268 pdmR0DevHlp_TimerFromMilli,
1269 pdmR0DevHlp_TimerFromNano,
1270 pdmR0DevHlp_TimerGet,
1271 pdmR0DevHlp_TimerGetFreq,
1272 pdmR0DevHlp_TimerGetNano,
1273 pdmR0DevHlp_TimerIsActive,
1274 pdmR0DevHlp_TimerIsLockOwner,
1275 pdmR0DevHlp_TimerLockClock,
1276 pdmR0DevHlp_TimerLockClock2,
1277 pdmR0DevHlp_TimerSet,
1278 pdmR0DevHlp_TimerSetFrequencyHint,
1279 pdmR0DevHlp_TimerSetMicro,
1280 pdmR0DevHlp_TimerSetMillies,
1281 pdmR0DevHlp_TimerSetNano,
1282 pdmR0DevHlp_TimerSetRelative,
1283 pdmR0DevHlp_TimerStop,
1284 pdmR0DevHlp_TimerUnlockClock,
1285 pdmR0DevHlp_TimerUnlockClock2,
1286 pdmR0DevHlp_TMTimeVirtGet,
1287 pdmR0DevHlp_TMTimeVirtGetFreq,
1288 pdmR0DevHlp_TMTimeVirtGetNano,
1289 pdmR0DevHlp_QueueToPtr,
1290 pdmR0DevHlp_QueueAlloc,
1291 pdmR0DevHlp_QueueInsert,
1292 pdmR0DevHlp_QueueInsertEx,
1293 pdmR0DevHlp_QueueFlushIfNecessary,
1294 pdmR0DevHlp_TaskTrigger,
1295 pdmR0DevHlp_SUPSemEventSignal,
1296 pdmR0DevHlp_SUPSemEventWaitNoResume,
1297 pdmR0DevHlp_SUPSemEventWaitNsAbsIntr,
1298 pdmR0DevHlp_SUPSemEventWaitNsRelIntr,
1299 pdmR0DevHlp_SUPSemEventGetResolution,
1300 pdmR0DevHlp_SUPSemEventMultiSignal,
1301 pdmR0DevHlp_SUPSemEventMultiReset,
1302 pdmR0DevHlp_SUPSemEventMultiWaitNoResume,
1303 pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr,
1304 pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr,
1305 pdmR0DevHlp_SUPSemEventMultiGetResolution,
1306 pdmR0DevHlp_CritSectGetNop,
1307 pdmR0DevHlp_SetDeviceCritSect,
1308 pdmR0DevHlp_CritSectEnter,
1309 pdmR0DevHlp_CritSectEnterDebug,
1310 pdmR0DevHlp_CritSectTryEnter,
1311 pdmR0DevHlp_CritSectTryEnterDebug,
1312 pdmR0DevHlp_CritSectLeave,
1313 pdmR0DevHlp_CritSectIsOwner,
1314 pdmR0DevHlp_CritSectIsInitialized,
1315 pdmR0DevHlp_CritSectHasWaiters,
1316 pdmR0DevHlp_CritSectGetRecursion,
1317 pdmR0DevHlp_CritSectScheduleExitEvent,
1318 pdmR0DevHlp_DBGFTraceBuf,
1319 pdmR0DevHlp_PCIBusSetUpContext,
1320 pdmR0DevHlp_IommuSetUpContext,
1321 pdmR0DevHlp_PICSetUpContext,
1322 pdmR0DevHlp_ApicSetUpContext,
1323 pdmR0DevHlp_IoApicSetUpContext,
1324 pdmR0DevHlp_HpetSetUpContext,
1325 NULL /*pfnReserved1*/,
1326 NULL /*pfnReserved2*/,
1327 NULL /*pfnReserved3*/,
1328 NULL /*pfnReserved4*/,
1329 NULL /*pfnReserved5*/,
1330 NULL /*pfnReserved6*/,
1331 NULL /*pfnReserved7*/,
1332 NULL /*pfnReserved8*/,
1333 NULL /*pfnReserved9*/,
1334 NULL /*pfnReserved10*/,
1335 PDM_DEVHLPR0_VERSION
1336};
1337
1338
1339#ifdef VBOX_WITH_DBGF_TRACING
1340/**
1341 * The Ring-0 Device Helper Callbacks - tracing variant.
1342 */
1343extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlpTracing =
1344{
1345 PDM_DEVHLPR0_VERSION,
1346 pdmR0DevHlpTracing_IoPortSetUpContextEx,
1347 pdmR0DevHlpTracing_MmioSetUpContextEx,
1348 pdmR0DevHlp_Mmio2SetUpContext,
1349 pdmR0DevHlpTracing_PCIPhysRead,
1350 pdmR0DevHlpTracing_PCIPhysWrite,
1351 pdmR0DevHlpTracing_PCISetIrq,
1352 pdmR0DevHlpTracing_ISASetIrq,
1353 pdmR0DevHlp_PhysRead,
1354 pdmR0DevHlp_PhysWrite,
1355 pdmR0DevHlp_A20IsEnabled,
1356 pdmR0DevHlp_VMState,
1357 pdmR0DevHlp_VMSetError,
1358 pdmR0DevHlp_VMSetErrorV,
1359 pdmR0DevHlp_VMSetRuntimeError,
1360 pdmR0DevHlp_VMSetRuntimeErrorV,
1361 pdmR0DevHlp_GetVM,
1362 pdmR0DevHlp_GetVMCPU,
1363 pdmR0DevHlp_GetCurrentCpuId,
1364 pdmR0DevHlp_TimerFromMicro,
1365 pdmR0DevHlp_TimerFromMilli,
1366 pdmR0DevHlp_TimerFromNano,
1367 pdmR0DevHlp_TimerGet,
1368 pdmR0DevHlp_TimerGetFreq,
1369 pdmR0DevHlp_TimerGetNano,
1370 pdmR0DevHlp_TimerIsActive,
1371 pdmR0DevHlp_TimerIsLockOwner,
1372 pdmR0DevHlp_TimerLockClock,
1373 pdmR0DevHlp_TimerLockClock2,
1374 pdmR0DevHlp_TimerSet,
1375 pdmR0DevHlp_TimerSetFrequencyHint,
1376 pdmR0DevHlp_TimerSetMicro,
1377 pdmR0DevHlp_TimerSetMillies,
1378 pdmR0DevHlp_TimerSetNano,
1379 pdmR0DevHlp_TimerSetRelative,
1380 pdmR0DevHlp_TimerStop,
1381 pdmR0DevHlp_TimerUnlockClock,
1382 pdmR0DevHlp_TimerUnlockClock2,
1383 pdmR0DevHlp_TMTimeVirtGet,
1384 pdmR0DevHlp_TMTimeVirtGetFreq,
1385 pdmR0DevHlp_TMTimeVirtGetNano,
1386 pdmR0DevHlp_QueueToPtr,
1387 pdmR0DevHlp_QueueAlloc,
1388 pdmR0DevHlp_QueueInsert,
1389 pdmR0DevHlp_QueueInsertEx,
1390 pdmR0DevHlp_QueueFlushIfNecessary,
1391 pdmR0DevHlp_TaskTrigger,
1392 pdmR0DevHlp_SUPSemEventSignal,
1393 pdmR0DevHlp_SUPSemEventWaitNoResume,
1394 pdmR0DevHlp_SUPSemEventWaitNsAbsIntr,
1395 pdmR0DevHlp_SUPSemEventWaitNsRelIntr,
1396 pdmR0DevHlp_SUPSemEventGetResolution,
1397 pdmR0DevHlp_SUPSemEventMultiSignal,
1398 pdmR0DevHlp_SUPSemEventMultiReset,
1399 pdmR0DevHlp_SUPSemEventMultiWaitNoResume,
1400 pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr,
1401 pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr,
1402 pdmR0DevHlp_SUPSemEventMultiGetResolution,
1403 pdmR0DevHlp_CritSectGetNop,
1404 pdmR0DevHlp_SetDeviceCritSect,
1405 pdmR0DevHlp_CritSectEnter,
1406 pdmR0DevHlp_CritSectEnterDebug,
1407 pdmR0DevHlp_CritSectTryEnter,
1408 pdmR0DevHlp_CritSectTryEnterDebug,
1409 pdmR0DevHlp_CritSectLeave,
1410 pdmR0DevHlp_CritSectIsOwner,
1411 pdmR0DevHlp_CritSectIsInitialized,
1412 pdmR0DevHlp_CritSectHasWaiters,
1413 pdmR0DevHlp_CritSectGetRecursion,
1414 pdmR0DevHlp_CritSectScheduleExitEvent,
1415 pdmR0DevHlp_DBGFTraceBuf,
1416 pdmR0DevHlp_PCIBusSetUpContext,
1417 pdmR0DevHlp_IommuSetUpContext,
1418 pdmR0DevHlp_PICSetUpContext,
1419 pdmR0DevHlp_ApicSetUpContext,
1420 pdmR0DevHlp_IoApicSetUpContext,
1421 pdmR0DevHlp_HpetSetUpContext,
1422 NULL /*pfnReserved1*/,
1423 NULL /*pfnReserved2*/,
1424 NULL /*pfnReserved3*/,
1425 NULL /*pfnReserved4*/,
1426 NULL /*pfnReserved5*/,
1427 NULL /*pfnReserved6*/,
1428 NULL /*pfnReserved7*/,
1429 NULL /*pfnReserved8*/,
1430 NULL /*pfnReserved9*/,
1431 NULL /*pfnReserved10*/,
1432 PDM_DEVHLPR0_VERSION
1433};
1434#endif
1435
1436
1437/** @} */
1438
1439
1440/** @name PIC Ring-0 Helpers
1441 * @{
1442 */
1443
1444/** @interface_method_impl{PDMPICHLP,pfnSetInterruptFF} */
1445static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
1446{
1447 PDMDEV_ASSERT_DEVINS(pDevIns);
1448 PGVM pGVM = (PGVM)pDevIns->Internal.s.pGVM;
1449 PVMCPUCC pVCpu = &pGVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
1450 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
1451 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
1452}
1453
1454
1455/** @interface_method_impl{PDMPICHLP,pfnClearInterruptFF} */
1456static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
1457{
1458 PDMDEV_ASSERT_DEVINS(pDevIns);
1459 PGVM pGVM = (PGVM)pDevIns->Internal.s.pGVM;
1460 PVMCPUCC pVCpu = &pGVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
1461 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
1462 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
1463}
1464
1465
1466/** @interface_method_impl{PDMPICHLP,pfnLock} */
1467static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
1468{
1469 PDMDEV_ASSERT_DEVINS(pDevIns);
1470 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1471}
1472
1473
1474/** @interface_method_impl{PDMPICHLP,pfnUnlock} */
1475static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns)
1476{
1477 PDMDEV_ASSERT_DEVINS(pDevIns);
1478 pdmUnlock(pDevIns->Internal.s.pGVM);
1479}
1480
1481
1482/**
1483 * The Ring-0 PIC Helper Callbacks.
1484 */
1485extern DECLEXPORT(const PDMPICHLP) g_pdmR0PicHlp =
1486{
1487 PDM_PICHLP_VERSION,
1488 pdmR0PicHlp_SetInterruptFF,
1489 pdmR0PicHlp_ClearInterruptFF,
1490 pdmR0PicHlp_Lock,
1491 pdmR0PicHlp_Unlock,
1492 PDM_PICHLP_VERSION
1493};
1494
1495/** @} */
1496
1497
1498/** @name I/O APIC Ring-0 Helpers
1499 * @{
1500 */
1501
1502/** @interface_method_impl{PDMIOAPICHLP,pfnApicBusDeliver} */
1503static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
1504 uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
1505 uint8_t u8TriggerMode, uint32_t uTagSrc)
1506{
1507 PDMDEV_ASSERT_DEVINS(pDevIns);
1508 PGVM pGVM = pDevIns->Internal.s.pGVM;
1509 LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
1510 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
1511 return APICBusDeliver(pGVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
1512}
1513
1514
1515/** @interface_method_impl{PDMIOAPICHLP,pfnLock} */
1516static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
1517{
1518 PDMDEV_ASSERT_DEVINS(pDevIns);
1519 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1520}
1521
1522
1523/** @interface_method_impl{PDMIOAPICHLP,pfnUnlock} */
1524static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns)
1525{
1526 PDMDEV_ASSERT_DEVINS(pDevIns);
1527 pdmUnlock(pDevIns->Internal.s.pGVM);
1528}
1529
1530
1531/** @interface_method_impl{PDMIOAPICHLP,pfnLockIsOwner} */
1532static DECLCALLBACK(bool) pdmR0IoApicHlp_LockIsOwner(PPDMDEVINS pDevIns)
1533{
1534 PDMDEV_ASSERT_DEVINS(pDevIns);
1535 return pdmLockIsOwner(pDevIns->Internal.s.pGVM);
1536}
1537
1538
1539/** @interface_method_impl{PDMIOAPICHLP,pfnIommuMsiRemap} */
1540static DECLCALLBACK(int) pdmR0IoApicHlp_IommuMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1541{
1542 PDMDEV_ASSERT_DEVINS(pDevIns);
1543 LogFlow(("pdmR0IoApicHlp_IommuMsiRemap: caller='%s'/%d: pMsiIn=(%#RX64, %#RU32)\n", pDevIns->pReg->szName,
1544 pDevIns->iInstance, pMsiIn->Addr.u64, pMsiIn->Data.u32));
1545
1546#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
1547 if (pdmIommuIsPresent(pDevIns))
1548 {
1549 PGVM pGVM = pDevIns->Internal.s.pGVM;
1550 PPDMIOMMUR0 pIommu = &pGVM->pdmr0.s.aIommus[0];
1551 if (pIommu->pDevInsR0)
1552 return pdmIommuMsiRemap(pDevIns, idDevice, pMsiIn, pMsiOut);
1553 AssertMsgFailedReturn(("Implement queueing PDM task for remapping MSI via IOMMU in ring-3"), VERR_IOMMU_IPE_0);
1554 }
1555#else
1556 RT_NOREF(pDevIns, idDevice);
1557#endif
1558 return VERR_IOMMU_NOT_PRESENT;
1559}
1560
1561
1562/**
1563 * The Ring-0 I/O APIC Helper Callbacks.
1564 */
1565extern DECLEXPORT(const PDMIOAPICHLP) g_pdmR0IoApicHlp =
1566{
1567 PDM_IOAPICHLP_VERSION,
1568 pdmR0IoApicHlp_ApicBusDeliver,
1569 pdmR0IoApicHlp_Lock,
1570 pdmR0IoApicHlp_Unlock,
1571 pdmR0IoApicHlp_LockIsOwner,
1572 pdmR0IoApicHlp_IommuMsiRemap,
1573 PDM_IOAPICHLP_VERSION
1574};
1575
1576/** @} */
1577
1578
1579
1580
1581/** @name PCI Bus Ring-0 Helpers
1582 * @{
1583 */
1584
1585/** @interface_method_impl{PDMPCIHLPR0,pfnIsaSetIrq} */
1586static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
1587{
1588 PDMDEV_ASSERT_DEVINS(pDevIns);
1589 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
1590 PGVM pGVM = pDevIns->Internal.s.pGVM;
1591
1592 pdmLock(pGVM);
1593 pdmR0IsaSetIrq(pGVM, iIrq, iLevel, uTagSrc);
1594 pdmUnlock(pGVM);
1595}
1596
1597
1598/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSetIrq} */
1599static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
1600{
1601 PDMDEV_ASSERT_DEVINS(pDevIns);
1602 Log4(("pdmR0PciHlp_IoApicSetIrq: uBusDevFn=%#x iIrq=%d iLevel=%d uTagSrc=%#x\n", uBusDevFn, iIrq, iLevel, uTagSrc));
1603 PGVM pGVM = pDevIns->Internal.s.pGVM;
1604
1605 if (pGVM->pdm.s.IoApic.pDevInsR0)
1606 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, uBusDevFn, iIrq, iLevel, uTagSrc);
1607 else if (pGVM->pdm.s.IoApic.pDevInsR3)
1608 {
1609 /* queue for ring-3 execution. */
1610 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
1611 if (pTask)
1612 {
1613 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
1614 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
1615 pTask->u.IoApicSetIrq.uBusDevFn = uBusDevFn;
1616 pTask->u.IoApicSetIrq.iIrq = iIrq;
1617 pTask->u.IoApicSetIrq.iLevel = iLevel;
1618 pTask->u.IoApicSetIrq.uTagSrc = uTagSrc;
1619
1620 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
1621 }
1622 else
1623 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
1624 }
1625}
1626
1627
1628/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSendMsi} */
1629static DECLCALLBACK(void) pdmR0PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
1630{
1631 PDMDEV_ASSERT_DEVINS(pDevIns);
1632 Assert(PCIBDF_IS_VALID(uBusDevFn));
1633 Log4(("pdmR0PciHlp_IoApicSendMsi: uBusDevFn=%#x Msi=(Addr:%#RX64 Data:%#RX32) uTagSrc=%#x\n", uBusDevFn, pMsi->Addr.u64,
1634 pMsi->Data.u32, uTagSrc));
1635 PDMIoApicSendMsi(pDevIns->Internal.s.pGVM, uBusDevFn, pMsi, uTagSrc);
1636}
1637
1638
1639/** @interface_method_impl{PDMPCIHLPR0,pfnLock} */
1640static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
1641{
1642 PDMDEV_ASSERT_DEVINS(pDevIns);
1643 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1644}
1645
1646
1647/** @interface_method_impl{PDMPCIHLPR0,pfnUnlock} */
1648static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns)
1649{
1650 PDMDEV_ASSERT_DEVINS(pDevIns);
1651 pdmUnlock(pDevIns->Internal.s.pGVM);
1652}
1653
1654
1655/** @interface_method_impl{PDMPCIHLPR0,pfnGetBusByNo} */
1656static DECLCALLBACK(PPDMDEVINS) pdmR0PciHlp_GetBusByNo(PPDMDEVINS pDevIns, uint32_t idxPdmBus)
1657{
1658 PDMDEV_ASSERT_DEVINS(pDevIns);
1659 PGVM pGVM = pDevIns->Internal.s.pGVM;
1660 AssertReturn(idxPdmBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses), NULL);
1661 PPDMDEVINS pRetDevIns = pGVM->pdmr0.s.aPciBuses[idxPdmBus].pDevInsR0;
1662 LogFlow(("pdmR3PciHlp_GetBusByNo: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRetDevIns));
1663 return pRetDevIns;
1664}
1665
1666
1667/**
1668 * The Ring-0 PCI Bus Helper Callbacks.
1669 */
1670extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp =
1671{
1672 PDM_PCIHLPR0_VERSION,
1673 pdmR0PciHlp_IsaSetIrq,
1674 pdmR0PciHlp_IoApicSetIrq,
1675 pdmR0PciHlp_IoApicSendMsi,
1676 pdmR0PciHlp_Lock,
1677 pdmR0PciHlp_Unlock,
1678 pdmR0PciHlp_GetBusByNo,
1679 PDM_PCIHLPR0_VERSION, /* the end */
1680};
1681
1682/** @} */
1683
1684
1685/** @name IOMMU Ring-0 Helpers
1686 * @{
1687 */
1688
1689/** @interface_method_impl{PDMIOMMUHLPR0,pfnLock} */
1690static DECLCALLBACK(int) pdmR0IommuHlp_Lock(PPDMDEVINS pDevIns, int rc)
1691{
1692 PDMDEV_ASSERT_DEVINS(pDevIns);
1693 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1694}
1695
1696
1697/** @interface_method_impl{PDMIOMMUHLPR0,pfnUnlock} */
1698static DECLCALLBACK(void) pdmR0IommuHlp_Unlock(PPDMDEVINS pDevIns)
1699{
1700 PDMDEV_ASSERT_DEVINS(pDevIns);
1701 pdmUnlock(pDevIns->Internal.s.pGVM);
1702}
1703
1704
1705/** @interface_method_impl{PDMIOMMUHLPR0,pfnLockIsOwner} */
1706static DECLCALLBACK(bool) pdmR0IommuHlp_LockIsOwner(PPDMDEVINS pDevIns)
1707{
1708 PDMDEV_ASSERT_DEVINS(pDevIns);
1709 return pdmLockIsOwner(pDevIns->Internal.s.pGVM);
1710}
1711
1712
1713/** @interface_method_impl{PDMIOMMUHLPR0,pfnSendMsi} */
1714static DECLCALLBACK(void) pdmR0IommuHlp_SendMsi(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc)
1715{
1716 PDMDEV_ASSERT_DEVINS(pDevIns);
1717 PDMIoApicSendMsi(pDevIns->Internal.s.pGVM, NIL_PCIBDF, pMsi, uTagSrc);
1718}
1719
1720
1721/**
1722 * The Ring-0 IOMMU Helper Callbacks.
1723 */
1724extern DECLEXPORT(const PDMIOMMUHLPR0) g_pdmR0IommuHlp =
1725{
1726 PDM_IOMMUHLPR0_VERSION,
1727 pdmR0IommuHlp_Lock,
1728 pdmR0IommuHlp_Unlock,
1729 pdmR0IommuHlp_LockIsOwner,
1730 pdmR0IommuHlp_SendMsi,
1731 PDM_IOMMUHLPR0_VERSION, /* the end */
1732};
1733
1734/** @} */
1735
1736
1737/** @name HPET Ring-0 Helpers
1738 * @{
1739 */
1740/* none */
1741
1742/**
1743 * The Ring-0 HPET Helper Callbacks.
1744 */
1745extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp =
1746{
1747 PDM_HPETHLPR0_VERSION,
1748 PDM_HPETHLPR0_VERSION, /* the end */
1749};
1750
1751/** @} */
1752
1753
1754/** @name Raw PCI Ring-0 Helpers
1755 * @{
1756 */
1757/* none */
1758
1759/**
1760 * The Ring-0 PCI raw Helper Callbacks.
1761 */
1762extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp =
1763{
1764 PDM_PCIRAWHLPR0_VERSION,
1765 PDM_PCIRAWHLPR0_VERSION, /* the end */
1766};
1767
1768/** @} */
1769
1770
1771
1772
1773/**
1774 * Sets an irq on the PIC and I/O APIC.
1775 *
1776 * @returns true if delivered, false if postponed.
1777 * @param pGVM The global (ring-0) VM structure.
1778 * @param iIrq The irq.
1779 * @param iLevel The new level.
1780 * @param uTagSrc The IRQ tag and source.
1781 *
1782 * @remarks The caller holds the PDM lock.
1783 */
1784DECLHIDDEN(bool) pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc)
1785{
1786 if (RT_LIKELY( ( pGVM->pdm.s.IoApic.pDevInsR0
1787 || !pGVM->pdm.s.IoApic.pDevInsR3)
1788 && ( pGVM->pdm.s.Pic.pDevInsR0
1789 || !pGVM->pdm.s.Pic.pDevInsR3)))
1790 {
1791 if (pGVM->pdm.s.Pic.pDevInsR0)
1792 pGVM->pdm.s.Pic.pfnSetIrqR0(pGVM->pdm.s.Pic.pDevInsR0, iIrq, iLevel, uTagSrc);
1793 if (pGVM->pdm.s.IoApic.pDevInsR0)
1794 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, NIL_PCIBDF, iIrq, iLevel, uTagSrc);
1795 return true;
1796 }
1797
1798 /* queue for ring-3 execution. */
1799 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
1800 AssertReturn(pTask, false);
1801
1802 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
1803 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
1804 pTask->u.IsaSetIrq.uBusDevFn = NIL_PCIBDF;
1805 pTask->u.IsaSetIrq.iIrq = iIrq;
1806 pTask->u.IsaSetIrq.iLevel = iLevel;
1807 pTask->u.IsaSetIrq.uTagSrc = uTagSrc;
1808
1809 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
1810 return false;
1811}
1812
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