VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/PDMR0DevHlp.cpp@ 84826

Last change on this file since 84826 was 84826, checked in by vboxsync, 5 years ago

AMD IOMMU: bugref:9654 PDM interface changes for supplying bus:device:function for devices' initiating PCI interrupts and MSIs.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 69.0 KB
Line 
1/* $Id: PDMR0DevHlp.cpp 84826 2020-06-15 08:20:40Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, R0 Device Helper parts.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
24#include "PDMInternal.h"
25#include <VBox/vmm/pdm.h>
26#include <VBox/vmm/apic.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/gvm.h>
30#include <VBox/vmm/vmm.h>
31#include <VBox/vmm/vmcc.h>
32#include <VBox/vmm/gvmm.h>
33
34#include <VBox/log.h>
35#include <VBox/err.h>
36#include <VBox/sup.h>
37#include <iprt/asm.h>
38#include <iprt/assert.h>
39#include <iprt/ctype.h>
40#include <iprt/string.h>
41
42#include "dtrace/VBoxVMM.h"
43#include "PDMInline.h"
44
45
46/*********************************************************************************************************************************
47* Global Variables *
48*********************************************************************************************************************************/
49RT_C_DECLS_BEGIN
50extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp;
51extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlpTracing;
52extern DECLEXPORT(const PDMPICHLP) g_pdmR0PicHlp;
53extern DECLEXPORT(const PDMIOAPICHLP) g_pdmR0IoApicHlp;
54extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp;
55extern DECLEXPORT(const PDMIOMMUHLPR0) g_pdmR0IommuHlp;
56extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp;
57extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp;
58RT_C_DECLS_END
59
60
61/*********************************************************************************************************************************
62* Internal Functions *
63*********************************************************************************************************************************/
64
65
66/** @name Ring-0 Device Helpers
67 * @{
68 */
69
70/** @interface_method_impl{PDMDEVHLPR0,pfnIoPortSetUpContextEx} */
71static DECLCALLBACK(int) pdmR0DevHlp_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
72 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
73 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
74 void *pvUser)
75{
76 PDMDEV_ASSERT_DEVINS(pDevIns);
77 LogFlow(("pdmR0DevHlp_IoPortSetUpContextEx: caller='%s'/%d: hIoPorts=%#x pfnOut=%p pfnIn=%p pfnOutStr=%p pfnInStr=%p pvUser=%p\n",
78 pDevIns->pReg->szName, pDevIns->iInstance, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser));
79 PGVM pGVM = pDevIns->Internal.s.pGVM;
80 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
81 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
82
83 int rc = IOMR0IoPortSetUpContext(pGVM, pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
84
85 LogFlow(("pdmR0DevHlp_IoPortSetUpContextEx: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
86 return rc;
87}
88
89
90/** @interface_method_impl{PDMDEVHLPR0,pfnMmioSetUpContextEx} */
91static DECLCALLBACK(int) pdmR0DevHlp_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
92 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
93{
94 PDMDEV_ASSERT_DEVINS(pDevIns);
95 LogFlow(("pdmR0DevHlp_MmioSetUpContextEx: caller='%s'/%d: hRegion=%#x pfnWrite=%p pfnRead=%p pfnFill=%p pvUser=%p\n",
96 pDevIns->pReg->szName, pDevIns->iInstance, hRegion, pfnWrite, pfnRead, pfnFill, pvUser));
97 PGVM pGVM = pDevIns->Internal.s.pGVM;
98 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
99 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
100
101 int rc = IOMR0MmioSetUpContext(pGVM, pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
102
103 LogFlow(("pdmR0DevHlp_MmioSetUpContextEx: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
104 return rc;
105}
106
107
108/** @interface_method_impl{PDMDEVHLPR0,pfnMmio2SetUpContext} */
109static DECLCALLBACK(int) pdmR0DevHlp_Mmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
110 size_t offSub, size_t cbSub, void **ppvMapping)
111{
112 PDMDEV_ASSERT_DEVINS(pDevIns);
113 LogFlow(("pdmR0DevHlp_Mmio2SetUpContext: caller='%s'/%d: hRegion=%#x offSub=%#zx cbSub=%#zx ppvMapping=%p\n",
114 pDevIns->pReg->szName, pDevIns->iInstance, hRegion, offSub, cbSub, ppvMapping));
115 *ppvMapping = NULL;
116
117 PGVM pGVM = pDevIns->Internal.s.pGVM;
118 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
119 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
120
121 int rc = PGMR0PhysMMIO2MapKernel(pGVM, pDevIns, hRegion, offSub, cbSub, ppvMapping);
122
123 LogFlow(("pdmR0DevHlp_Mmio2SetUpContext: caller='%s'/%d: returns %Rrc (%p)\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *ppvMapping));
124 return rc;
125}
126
127
128/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysRead} */
129static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
130 void *pvBuf, size_t cbRead, uint32_t fFlags)
131{
132 PDMDEV_ASSERT_DEVINS(pDevIns);
133 if (!pPciDev) /* NULL is an alias for the default PCI device. */
134 pPciDev = pDevIns->apPciDevs[0];
135 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
136 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
137
138#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
139 /*
140 * Just check the busmaster setting here and forward the request to the generic read helper.
141 */
142 if (PCIDevIsBusmaster(pPciDev))
143 { /* likely */ }
144 else
145 {
146 Log(("pdmRCDevHlp_PCIPhysRead: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#zx\n",
147 pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
148 memset(pvBuf, 0xff, cbRead);
149 return VERR_PDM_NOT_PCI_BUS_MASTER;
150 }
151#endif
152
153#ifdef VBOX_WITH_IOMMU_AMD
154 /** @todo IOMMU: Optimize/re-organize things here later. */
155 PGVM pGVM = pDevIns->Internal.s.pGVM;
156 PPDMIOMMUR0 pIommu = &pGVM->pdmr0.s.aIommus[0];
157 PPDMDEVINS pDevInsIommu = pIommu->CTX_SUFF(pDevIns);
158 if ( pDevInsIommu
159 && pDevInsIommu != pDevIns)
160 {
161 size_t const idxBus = pPciDev->Int.s.idxPdmBus;
162 Assert(idxBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
163 PPDMPCIBUSR0 pBus = &pGVM->pdmr0.s.aPciBuses[idxBus];
164
165 RTGCPHYS GCPhysOut;
166 uint16_t const uDeviceId = PCIBDF_MAKE(pBus->iBus, pPciDev->uDevFn);
167 int rc = pIommu->pfnMemRead(pDevInsIommu, uDeviceId, GCPhys, cbRead, &GCPhysOut);
168 if (RT_FAILURE(rc))
169 {
170 Log(("pdmR0DevHlp_PCIPhysRead: IOMMU translation failed. uDeviceId=%#x GCPhys=%#RGp cb=%u rc=%Rrc\n", uDeviceId,
171 GCPhys, cbRead, rc));
172 return rc;
173 }
174 }
175#endif
176
177 return pDevIns->pHlpR0->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, fFlags);
178}
179
180
181/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysWrite} */
182static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
183 const void *pvBuf, size_t cbWrite, uint32_t fFlags)
184{
185 PDMDEV_ASSERT_DEVINS(pDevIns);
186 if (!pPciDev) /* NULL is an alias for the default PCI device. */
187 pPciDev = pDevIns->apPciDevs[0];
188 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
189 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
190
191#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
192 /*
193 * Just check the busmaster setting here and forward the request to the generic read helper.
194 */
195 if (PCIDevIsBusmaster(pPciDev))
196 { /* likely */ }
197 else
198 {
199 Log(("pdmRCDevHlp_PCIPhysWrite: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#zx\n",
200 pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
201 return VERR_PDM_NOT_PCI_BUS_MASTER;
202 }
203#endif
204
205#ifdef VBOX_WITH_IOMMU_AMD
206 /** @todo IOMMU: Optimize/re-organize things here later. */
207 PGVM pGVM = pDevIns->Internal.s.pGVM;
208 PPDMIOMMUR0 pIommu = &pGVM->pdmr0.s.aIommus[0];
209 PPDMDEVINS pDevInsIommu = pIommu->CTX_SUFF(pDevIns);
210 if ( pDevInsIommu
211 && pDevInsIommu != pDevIns)
212 {
213 size_t const idxBus = pPciDev->Int.s.idxPdmBus;
214 Assert(idxBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
215 PPDMPCIBUSR0 pBus = &pGVM->pdmr0.s.aPciBuses[idxBus];
216
217 RTGCPHYS GCPhysOut;
218 uint16_t const uDeviceId = PCIBDF_MAKE(pBus->iBus, pPciDev->uDevFn);
219 int rc = pIommu->pfnMemWrite(pDevInsIommu, uDeviceId, GCPhys, cbWrite, &GCPhysOut);
220 if (RT_FAILURE(rc))
221 {
222 Log(("pdmR0DevHlp_PCIPhysWrite: IOMMU translation failed. uDeviceId=%#x GCPhys=%#RGp cb=%u rc=%Rrc\n", uDeviceId,
223 GCPhys, cbWrite, rc));
224 return rc;
225 }
226 }
227#endif
228
229 return pDevIns->pHlpR0->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, fFlags);
230}
231
232
233/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
234static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
235{
236 PDMDEV_ASSERT_DEVINS(pDevIns);
237 if (!pPciDev) /* NULL is an alias for the default PCI device. */
238 pPciDev = pDevIns->apPciDevs[0];
239 AssertReturnVoid(pPciDev);
240 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: pPciDev=%p:{%#x} iIrq=%d iLevel=%d\n",
241 pDevIns, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iIrq, iLevel));
242 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
243
244 PGVM pGVM = pDevIns->Internal.s.pGVM;
245 size_t const idxBus = pPciDev->Int.s.idxPdmBus;
246 AssertReturnVoid(idxBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
247 PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[idxBus];
248
249 pdmLock(pGVM);
250
251 uint32_t uTagSrc;
252 if (iLevel & PDM_IRQ_LEVEL_HIGH)
253 {
254 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
255 if (iLevel == PDM_IRQ_LEVEL_HIGH)
256 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
257 else
258 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
259 }
260 else
261 uTagSrc = pDevIns->Internal.s.pIntR3R0->uLastIrqTag;
262
263 if (pPciBusR0->pDevInsR0)
264 {
265 pPciBusR0->pfnSetIrqR0(pPciBusR0->pDevInsR0, pPciDev, iIrq, iLevel, uTagSrc);
266
267 pdmUnlock(pGVM);
268
269 if (iLevel == PDM_IRQ_LEVEL_LOW)
270 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
271 }
272 else
273 {
274 pdmUnlock(pGVM);
275
276 /* queue for ring-3 execution. */
277 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
278 AssertReturnVoid(pTask);
279
280 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
281 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
282 pTask->u.PciSetIRQ.iIrq = iIrq;
283 pTask->u.PciSetIRQ.iLevel = iLevel;
284 pTask->u.PciSetIRQ.uTagSrc = uTagSrc;
285 pTask->u.PciSetIRQ.pPciDevR3 = MMHyperR0ToR3(pGVM, pPciDev);
286
287 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
288 }
289
290 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
291}
292
293
294/** @interface_method_impl{PDMDEVHLPR0,pfnISASetIrq} */
295static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
296{
297 PDMDEV_ASSERT_DEVINS(pDevIns);
298 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
299 PGVM pGVM = pDevIns->Internal.s.pGVM;
300
301 pdmLock(pGVM);
302 uint32_t uTagSrc;
303 if (iLevel & PDM_IRQ_LEVEL_HIGH)
304 {
305 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
306 if (iLevel == PDM_IRQ_LEVEL_HIGH)
307 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
308 else
309 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
310 }
311 else
312 uTagSrc = pDevIns->Internal.s.pIntR3R0->uLastIrqTag;
313
314 bool fRc = pdmR0IsaSetIrq(pGVM, iIrq, iLevel, uTagSrc);
315
316 if (iLevel == PDM_IRQ_LEVEL_LOW && fRc)
317 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
318 pdmUnlock(pGVM);
319 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
320}
321
322
323/** @interface_method_impl{PDMDEVHLPR0,pfnPhysRead} */
324static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags)
325{
326 RT_NOREF(fFlags);
327
328 PDMDEV_ASSERT_DEVINS(pDevIns);
329 LogFlow(("pdmR0DevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
330 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
331
332 VBOXSTRICTRC rcStrict = PGMPhysRead(pDevIns->Internal.s.pGVM, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
333 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
334
335 Log(("pdmR0DevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
336 return VBOXSTRICTRC_VAL(rcStrict);
337}
338
339
340/** @interface_method_impl{PDMDEVHLPR0,pfnPhysWrite} */
341static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags)
342{
343 RT_NOREF(fFlags);
344
345 PDMDEV_ASSERT_DEVINS(pDevIns);
346 LogFlow(("pdmR0DevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
347 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
348
349 VBOXSTRICTRC rcStrict = PGMPhysWrite(pDevIns->Internal.s.pGVM, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
350 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
351
352 Log(("pdmR0DevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
353 return VBOXSTRICTRC_VAL(rcStrict);
354}
355
356
357/** @interface_method_impl{PDMDEVHLPR0,pfnA20IsEnabled} */
358static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
359{
360 PDMDEV_ASSERT_DEVINS(pDevIns);
361 LogFlow(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
362
363 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pGVM));
364
365 Log(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
366 return fEnabled;
367}
368
369
370/** @interface_method_impl{PDMDEVHLPR0,pfnVMState} */
371static DECLCALLBACK(VMSTATE) pdmR0DevHlp_VMState(PPDMDEVINS pDevIns)
372{
373 PDMDEV_ASSERT_DEVINS(pDevIns);
374
375 VMSTATE enmVMState = pDevIns->Internal.s.pGVM->enmVMState;
376
377 LogFlow(("pdmR0DevHlp_VMState: caller=%p/%d: returns %d\n", pDevIns, pDevIns->iInstance, enmVMState));
378 return enmVMState;
379}
380
381
382/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetError} */
383static DECLCALLBACK(int) pdmR0DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
384{
385 PDMDEV_ASSERT_DEVINS(pDevIns);
386 va_list args;
387 va_start(args, pszFormat);
388 int rc2 = VMSetErrorV(pDevIns->Internal.s.pGVM, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
389 va_end(args);
390 return rc;
391}
392
393
394/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetErrorV} */
395static DECLCALLBACK(int) pdmR0DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
396{
397 PDMDEV_ASSERT_DEVINS(pDevIns);
398 int rc2 = VMSetErrorV(pDevIns->Internal.s.pGVM, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
399 return rc;
400}
401
402
403/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeError} */
404static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
405{
406 PDMDEV_ASSERT_DEVINS(pDevIns);
407 va_list va;
408 va_start(va, pszFormat);
409 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pGVM, fFlags, pszErrorId, pszFormat, va);
410 va_end(va);
411 return rc;
412}
413
414
415/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeErrorV} */
416static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
417{
418 PDMDEV_ASSERT_DEVINS(pDevIns);
419 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pGVM, fFlags, pszErrorId, pszFormat, va);
420 return rc;
421}
422
423
424
425/** @interface_method_impl{PDMDEVHLPR0,pfnGetVM} */
426static DECLCALLBACK(PVMCC) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns)
427{
428 PDMDEV_ASSERT_DEVINS(pDevIns);
429 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
430 return pDevIns->Internal.s.pGVM;
431}
432
433
434/** @interface_method_impl{PDMDEVHLPR0,pfnGetVMCPU} */
435static DECLCALLBACK(PVMCPUCC) pdmR0DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
436{
437 PDMDEV_ASSERT_DEVINS(pDevIns);
438 LogFlow(("pdmR0DevHlp_GetVMCPU: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
439 return VMMGetCpu(pDevIns->Internal.s.pGVM);
440}
441
442
443/** @interface_method_impl{PDMDEVHLPRC,pfnGetCurrentCpuId} */
444static DECLCALLBACK(VMCPUID) pdmR0DevHlp_GetCurrentCpuId(PPDMDEVINS pDevIns)
445{
446 PDMDEV_ASSERT_DEVINS(pDevIns);
447 VMCPUID idCpu = VMMGetCpuId(pDevIns->Internal.s.pGVM);
448 LogFlow(("pdmR0DevHlp_GetCurrentCpuId: caller='%p'/%d for CPU %u\n", pDevIns, pDevIns->iInstance, idCpu));
449 return idCpu;
450}
451
452
453/** @interface_method_impl{PDMDEVHLPR0,pfnTimerToPtr} */
454static DECLCALLBACK(PTMTIMERR0) pdmR0DevHlp_TimerToPtr(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
455{
456 PDMDEV_ASSERT_DEVINS(pDevIns);
457 RT_NOREF(pDevIns);
458 return (PTMTIMERR0)MMHyperR3ToCC(pDevIns->Internal.s.pGVM, hTimer);
459}
460
461
462/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromMicro} */
463static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
464{
465 return TMTimerFromMicro(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cMicroSecs);
466}
467
468
469/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromMilli} */
470static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
471{
472 return TMTimerFromMilli(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cMilliSecs);
473}
474
475
476/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromNano} */
477static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
478{
479 return TMTimerFromNano(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cNanoSecs);
480}
481
482/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGet} */
483static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
484{
485 return TMTimerGet(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
486}
487
488
489/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGetFreq} */
490static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
491{
492 return TMTimerGetFreq(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
493}
494
495
496/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGetNano} */
497static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
498{
499 return TMTimerGetNano(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
500}
501
502
503/** @interface_method_impl{PDMDEVHLPR0,pfnTimerIsActive} */
504static DECLCALLBACK(bool) pdmR0DevHlp_TimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
505{
506 return TMTimerIsActive(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
507}
508
509
510/** @interface_method_impl{PDMDEVHLPR0,pfnTimerIsLockOwner} */
511static DECLCALLBACK(bool) pdmR0DevHlp_TimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
512{
513 return TMTimerIsLockOwner(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
514}
515
516
517/** @interface_method_impl{PDMDEVHLPR0,pfnTimerLockClock} */
518static DECLCALLBACK(VBOXSTRICTRC) pdmR0DevHlp_TimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
519{
520 return TMTimerLock(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), rcBusy);
521}
522
523
524/** @interface_method_impl{PDMDEVHLPR0,pfnTimerLockClock2} */
525static DECLCALLBACK(VBOXSTRICTRC) pdmR0DevHlp_TimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer,
526 PPDMCRITSECT pCritSect, int rcBusy)
527{
528 VBOXSTRICTRC rc = TMTimerLock(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), rcBusy);
529 if (rc == VINF_SUCCESS)
530 {
531 rc = PDMCritSectEnter(pCritSect, rcBusy);
532 if (rc == VINF_SUCCESS)
533 return rc;
534 AssertRC(VBOXSTRICTRC_VAL(rc));
535 TMTimerUnlock(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
536 }
537 else
538 AssertRC(VBOXSTRICTRC_VAL(rc));
539 return rc;
540}
541
542
543/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSet} */
544static DECLCALLBACK(int) pdmR0DevHlp_TimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
545{
546 return TMTimerSet(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), uExpire);
547}
548
549
550/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetFrequencyHint} */
551static DECLCALLBACK(int) pdmR0DevHlp_TimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
552{
553 return TMTimerSetFrequencyHint(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), uHz);
554}
555
556
557/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetMicro} */
558static DECLCALLBACK(int) pdmR0DevHlp_TimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
559{
560 return TMTimerSetMicro(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cMicrosToNext);
561}
562
563
564/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetMillies} */
565static DECLCALLBACK(int) pdmR0DevHlp_TimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
566{
567 return TMTimerSetMillies(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cMilliesToNext);
568}
569
570
571/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetNano} */
572static DECLCALLBACK(int) pdmR0DevHlp_TimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
573{
574 return TMTimerSetNano(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cNanosToNext);
575}
576
577
578/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetRelative} */
579static DECLCALLBACK(int) pdmR0DevHlp_TimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
580{
581 return TMTimerSetRelative(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cTicksToNext, pu64Now);
582}
583
584
585/** @interface_method_impl{PDMDEVHLPR0,pfnTimerStop} */
586static DECLCALLBACK(int) pdmR0DevHlp_TimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
587{
588 return TMTimerStop(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
589}
590
591
592/** @interface_method_impl{PDMDEVHLPR0,pfnTimerUnlockClock} */
593static DECLCALLBACK(void) pdmR0DevHlp_TimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
594{
595 TMTimerUnlock(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
596}
597
598
599/** @interface_method_impl{PDMDEVHLPR0,pfnTimerUnlockClock2} */
600static DECLCALLBACK(void) pdmR0DevHlp_TimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
601{
602 TMTimerUnlock(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
603 int rc = PDMCritSectLeave(pCritSect);
604 AssertRC(rc);
605}
606
607
608/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGet} */
609static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
610{
611 PDMDEV_ASSERT_DEVINS(pDevIns);
612 LogFlow(("pdmR0DevHlp_TMTimeVirtGet: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
613 return TMVirtualGet(pDevIns->Internal.s.pGVM);
614}
615
616
617/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetFreq} */
618static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
619{
620 PDMDEV_ASSERT_DEVINS(pDevIns);
621 LogFlow(("pdmR0DevHlp_TMTimeVirtGetFreq: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
622 return TMVirtualGetFreq(pDevIns->Internal.s.pGVM);
623}
624
625
626/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetNano} */
627static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
628{
629 PDMDEV_ASSERT_DEVINS(pDevIns);
630 LogFlow(("pdmR0DevHlp_TMTimeVirtGetNano: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
631 return TMVirtualToNano(pDevIns->Internal.s.pGVM, TMVirtualGet(pDevIns->Internal.s.pGVM));
632}
633
634
635/** @interface_method_impl{PDMDEVHLPR0,pfnQueueToPtr} */
636static DECLCALLBACK(PPDMQUEUE) pdmR0DevHlp_QueueToPtr(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
637{
638 PDMDEV_ASSERT_DEVINS(pDevIns);
639 RT_NOREF(pDevIns);
640 return (PPDMQUEUE)MMHyperR3ToCC(pDevIns->Internal.s.pGVM, hQueue);
641}
642
643
644/** @interface_method_impl{PDMDEVHLPR0,pfnQueueAlloc} */
645static DECLCALLBACK(PPDMQUEUEITEMCORE) pdmR0DevHlp_QueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
646{
647 return PDMQueueAlloc(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue));
648}
649
650
651/** @interface_method_impl{PDMDEVHLPR0,pfnQueueInsert} */
652static DECLCALLBACK(void) pdmR0DevHlp_QueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
653{
654 return PDMQueueInsert(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue), pItem);
655}
656
657
658/** @interface_method_impl{PDMDEVHLPR0,pfnQueueInsertEx} */
659static DECLCALLBACK(void) pdmR0DevHlp_QueueInsertEx(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem,
660 uint64_t cNanoMaxDelay)
661{
662 return PDMQueueInsertEx(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue), pItem, cNanoMaxDelay);
663}
664
665
666/** @interface_method_impl{PDMDEVHLPR0,pfnQueueFlushIfNecessary} */
667static DECLCALLBACK(bool) pdmR0DevHlp_QueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
668{
669 return PDMQueueFlushIfNecessary(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue));
670}
671
672
673/** @interface_method_impl{PDMDEVHLPR0,pfnTaskTrigger} */
674static DECLCALLBACK(int) pdmR0DevHlp_TaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
675{
676 PDMDEV_ASSERT_DEVINS(pDevIns);
677 LogFlow(("pdmR0DevHlp_TaskTrigger: caller='%s'/%d: hTask=%RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, hTask));
678
679 int rc = PDMTaskTrigger(pDevIns->Internal.s.pGVM, PDMTASKTYPE_DEV, pDevIns->pDevInsForR3, hTask);
680
681 LogFlow(("pdmR0DevHlp_TaskTrigger: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
682 return rc;
683}
684
685
686/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventSignal} */
687static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
688{
689 PDMDEV_ASSERT_DEVINS(pDevIns);
690 LogFlow(("pdmR0DevHlp_SUPSemEventSignal: caller='%s'/%d: hEvent=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEvent));
691
692 int rc = SUPSemEventSignal(pDevIns->Internal.s.pGVM->pSession, hEvent);
693
694 LogFlow(("pdmR0DevHlp_SUPSemEventSignal: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
695 return rc;
696}
697
698
699/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNoResume} */
700static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
701{
702 PDMDEV_ASSERT_DEVINS(pDevIns);
703 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNoResume: caller='%s'/%d: hEvent=%p cNsTimeout=%RU32\n",
704 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, cMillies));
705
706 int rc = SUPSemEventWaitNoResume(pDevIns->Internal.s.pGVM->pSession, hEvent, cMillies);
707
708 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNoResume: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
709 return rc;
710}
711
712
713/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNsAbsIntr} */
714static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
715{
716 PDMDEV_ASSERT_DEVINS(pDevIns);
717 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsAbsIntr: caller='%s'/%d: hEvent=%p uNsTimeout=%RU64\n",
718 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, uNsTimeout));
719
720 int rc = SUPSemEventWaitNsAbsIntr(pDevIns->Internal.s.pGVM->pSession, hEvent, uNsTimeout);
721
722 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsAbsIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
723 return rc;
724}
725
726
727/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNsRelIntr} */
728static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
729{
730 PDMDEV_ASSERT_DEVINS(pDevIns);
731 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsRelIntr: caller='%s'/%d: hEvent=%p cNsTimeout=%RU64\n",
732 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, cNsTimeout));
733
734 int rc = SUPSemEventWaitNsRelIntr(pDevIns->Internal.s.pGVM->pSession, hEvent, cNsTimeout);
735
736 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsRelIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
737 return rc;
738}
739
740
741/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventGetResolution} */
742static DECLCALLBACK(uint32_t) pdmR0DevHlp_SUPSemEventGetResolution(PPDMDEVINS pDevIns)
743{
744 PDMDEV_ASSERT_DEVINS(pDevIns);
745 LogFlow(("pdmR0DevHlp_SUPSemEventGetResolution: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
746
747 uint32_t cNsResolution = SUPSemEventGetResolution(pDevIns->Internal.s.pGVM->pSession);
748
749 LogFlow(("pdmR0DevHlp_SUPSemEventGetResolution: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, cNsResolution));
750 return cNsResolution;
751}
752
753
754/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiSignal} */
755static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
756{
757 PDMDEV_ASSERT_DEVINS(pDevIns);
758 LogFlow(("pdmR0DevHlp_SUPSemEventMultiSignal: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
759
760 int rc = SUPSemEventMultiSignal(pDevIns->Internal.s.pGVM->pSession, hEventMulti);
761
762 LogFlow(("pdmR0DevHlp_SUPSemEventMultiSignal: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
763 return rc;
764}
765
766
767/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiReset} */
768static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
769{
770 PDMDEV_ASSERT_DEVINS(pDevIns);
771 LogFlow(("pdmR0DevHlp_SUPSemEventMultiReset: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
772
773 int rc = SUPSemEventMultiReset(pDevIns->Internal.s.pGVM->pSession, hEventMulti);
774
775 LogFlow(("pdmR0DevHlp_SUPSemEventMultiReset: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
776 return rc;
777}
778
779
780/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNoResume} */
781static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
782 uint32_t cMillies)
783{
784 PDMDEV_ASSERT_DEVINS(pDevIns);
785 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNoResume: caller='%s'/%d: hEventMulti=%p cMillies=%RU32\n",
786 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, cMillies));
787
788 int rc = SUPSemEventMultiWaitNoResume(pDevIns->Internal.s.pGVM->pSession, hEventMulti, cMillies);
789
790 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNoResume: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
791 return rc;
792}
793
794
795/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNsAbsIntr} */
796static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
797 uint64_t uNsTimeout)
798{
799 PDMDEV_ASSERT_DEVINS(pDevIns);
800 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr: caller='%s'/%d: hEventMulti=%p uNsTimeout=%RU64\n",
801 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, uNsTimeout));
802
803 int rc = SUPSemEventMultiWaitNsAbsIntr(pDevIns->Internal.s.pGVM->pSession, hEventMulti, uNsTimeout);
804
805 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
806 return rc;
807}
808
809
810/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNsRelIntr} */
811static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
812 uint64_t cNsTimeout)
813{
814 PDMDEV_ASSERT_DEVINS(pDevIns);
815 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr: caller='%s'/%d: hEventMulti=%p cNsTimeout=%RU64\n",
816 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, cNsTimeout));
817
818 int rc = SUPSemEventMultiWaitNsRelIntr(pDevIns->Internal.s.pGVM->pSession, hEventMulti, cNsTimeout);
819
820 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
821 return rc;
822}
823
824
825/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiGetResolution} */
826static DECLCALLBACK(uint32_t) pdmR0DevHlp_SUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
827{
828 PDMDEV_ASSERT_DEVINS(pDevIns);
829 LogFlow(("pdmR0DevHlp_SUPSemEventMultiGetResolution: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
830
831 uint32_t cNsResolution = SUPSemEventMultiGetResolution(pDevIns->Internal.s.pGVM->pSession);
832
833 LogFlow(("pdmR0DevHlp_SUPSemEventMultiGetResolution: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, cNsResolution));
834 return cNsResolution;
835}
836
837
838/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectGetNop} */
839static DECLCALLBACK(PPDMCRITSECT) pdmR0DevHlp_CritSectGetNop(PPDMDEVINS pDevIns)
840{
841 PDMDEV_ASSERT_DEVINS(pDevIns);
842 PGVM pGVM = pDevIns->Internal.s.pGVM;
843
844 PPDMCRITSECT pCritSect = &pGVM->pdm.s.NopCritSect;
845 LogFlow(("pdmR0DevHlp_CritSectGetNop: caller='%s'/%d: return %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
846 return pCritSect;
847}
848
849
850/** @interface_method_impl{PDMDEVHLPR0,pfnSetDeviceCritSect} */
851static DECLCALLBACK(int) pdmR0DevHlp_SetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
852{
853 /*
854 * Validate input.
855 *
856 * Note! We only allow the automatically created default critical section
857 * to be replaced by this API.
858 */
859 PDMDEV_ASSERT_DEVINS(pDevIns);
860 AssertPtrReturn(pCritSect, VERR_INVALID_POINTER);
861 LogFlow(("pdmR0DevHlp_SetDeviceCritSect: caller='%s'/%d: pCritSect=%p (%s)\n",
862 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect, pCritSect->s.pszName));
863 AssertReturn(PDMCritSectIsInitialized(pCritSect), VERR_INVALID_PARAMETER);
864 PGVM pGVM = pDevIns->Internal.s.pGVM;
865 AssertReturn(pCritSect->s.pVMR0 == pGVM, VERR_INVALID_PARAMETER);
866
867 VM_ASSERT_EMT(pGVM);
868 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
869
870 /*
871 * Check that ring-3 has already done this, then effect the change.
872 */
873 AssertReturn(pDevIns->pDevInsForR3R0->Internal.s.fIntFlags & PDMDEVINSINT_FLAGS_CHANGED_CRITSECT, VERR_WRONG_ORDER);
874 pDevIns->pCritSectRoR0 = pCritSect;
875
876 LogFlow(("pdmR0DevHlp_SetDeviceCritSect: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
877 return VINF_SUCCESS;
878}
879
880
881/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectEnter} */
882static DECLCALLBACK(int) pdmR0DevHlp_CritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
883{
884 PDMDEV_ASSERT_DEVINS(pDevIns);
885 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
886 return PDMCritSectEnter(pCritSect, rcBusy);
887}
888
889
890/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectEnterDebug} */
891static DECLCALLBACK(int) pdmR0DevHlp_CritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
892{
893 PDMDEV_ASSERT_DEVINS(pDevIns);
894 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
895 return PDMCritSectEnterDebug(pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
896}
897
898
899/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectTryEnter} */
900static DECLCALLBACK(int) pdmR0DevHlp_CritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
901{
902 PDMDEV_ASSERT_DEVINS(pDevIns);
903 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
904 return PDMCritSectTryEnter(pCritSect);
905}
906
907
908/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectTryEnterDebug} */
909static DECLCALLBACK(int) pdmR0DevHlp_CritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
910{
911 PDMDEV_ASSERT_DEVINS(pDevIns);
912 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
913 return PDMCritSectTryEnterDebug(pCritSect, uId, RT_SRC_POS_ARGS);
914}
915
916
917/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectLeave} */
918static DECLCALLBACK(int) pdmR0DevHlp_CritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
919{
920 PDMDEV_ASSERT_DEVINS(pDevIns);
921 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
922 return PDMCritSectLeave(pCritSect);
923}
924
925
926/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectIsOwner} */
927static DECLCALLBACK(bool) pdmR0DevHlp_CritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
928{
929 PDMDEV_ASSERT_DEVINS(pDevIns);
930 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
931 return PDMCritSectIsOwner(pCritSect);
932}
933
934
935/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectIsInitialized} */
936static DECLCALLBACK(bool) pdmR0DevHlp_CritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
937{
938 PDMDEV_ASSERT_DEVINS(pDevIns);
939 RT_NOREF(pDevIns);
940 return PDMCritSectIsInitialized(pCritSect);
941}
942
943
944/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectHasWaiters} */
945static DECLCALLBACK(bool) pdmR0DevHlp_CritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
946{
947 PDMDEV_ASSERT_DEVINS(pDevIns);
948 RT_NOREF(pDevIns);
949 return PDMCritSectHasWaiters(pCritSect);
950}
951
952
953/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectGetRecursion} */
954static DECLCALLBACK(uint32_t) pdmR0DevHlp_CritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
955{
956 PDMDEV_ASSERT_DEVINS(pDevIns);
957 RT_NOREF(pDevIns);
958 return PDMCritSectGetRecursion(pCritSect);
959}
960
961
962/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectScheduleExitEvent} */
963static DECLCALLBACK(int) pdmR0DevHlp_CritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect,
964 SUPSEMEVENT hEventToSignal)
965{
966 PDMDEV_ASSERT_DEVINS(pDevIns);
967 RT_NOREF(pDevIns);
968 return PDMHCCritSectScheduleExitEvent(pCritSect, hEventToSignal);
969}
970
971
972/** @interface_method_impl{PDMDEVHLPR0,pfnDBGFTraceBuf} */
973static DECLCALLBACK(RTTRACEBUF) pdmR0DevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
974{
975 PDMDEV_ASSERT_DEVINS(pDevIns);
976 RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pGVM->hTraceBufR0;
977 LogFlow(("pdmR0DevHlp_DBGFTraceBuf: caller='%p'/%d: returns %p\n", pDevIns, pDevIns->iInstance, hTraceBuf));
978 return hTraceBuf;
979}
980
981
982/** @interface_method_impl{PDMDEVHLPR0,pfnPCIBusSetUpContext} */
983static DECLCALLBACK(int) pdmR0DevHlp_PCIBusSetUpContext(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp)
984{
985 PDMDEV_ASSERT_DEVINS(pDevIns);
986 LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: pPciBusReg=%p{.u32Version=%#x, .iBus=%#u, .pfnSetIrq=%p, u32EnvVersion=%#x} ppPciHlp=%p\n",
987 pDevIns, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->iBus, pPciBusReg->pfnSetIrq,
988 pPciBusReg->u32EndVersion, ppPciHlp));
989 PGVM pGVM = pDevIns->Internal.s.pGVM;
990
991 /*
992 * Validate input.
993 */
994 AssertPtrReturn(pPciBusReg, VERR_INVALID_POINTER);
995 AssertLogRelMsgReturn(pPciBusReg->u32Version == PDM_PCIBUSREGCC_VERSION,
996 ("%#x vs %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
997 AssertPtrReturn(pPciBusReg->pfnSetIrq, VERR_INVALID_POINTER);
998 AssertLogRelMsgReturn(pPciBusReg->u32EndVersion == PDM_PCIBUSREGCC_VERSION,
999 ("%#x vs %#x\n", pPciBusReg->u32EndVersion, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
1000
1001 AssertPtrReturn(ppPciHlp, VERR_INVALID_POINTER);
1002
1003 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1004 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1005
1006 /* Check the shared bus data (registered earlier from ring-3): */
1007 uint32_t iBus = pPciBusReg->iBus;
1008 ASMCompilerBarrier();
1009 AssertLogRelMsgReturn(iBus < RT_ELEMENTS(pGVM->pdm.s.aPciBuses), ("iBus=%#x\n", iBus), VERR_OUT_OF_RANGE);
1010 PPDMPCIBUS pPciBusShared = &pGVM->pdm.s.aPciBuses[iBus];
1011 AssertLogRelMsgReturn(pPciBusShared->iBus == iBus, ("%u vs %u\n", pPciBusShared->iBus, iBus), VERR_INVALID_PARAMETER);
1012 AssertLogRelMsgReturn(pPciBusShared->pDevInsR3 == pDevIns->pDevInsForR3,
1013 ("%p vs %p (iBus=%u)\n", pPciBusShared->pDevInsR3, pDevIns->pDevInsForR3, iBus), VERR_NOT_OWNER);
1014
1015 /* Check that the bus isn't already registered in ring-0: */
1016 AssertCompile(RT_ELEMENTS(pGVM->pdm.s.aPciBuses) == RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
1017 PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[iBus];
1018 AssertLogRelMsgReturn(pPciBusR0->pDevInsR0 == NULL,
1019 ("%p (caller pDevIns=%p, iBus=%u)\n", pPciBusR0->pDevInsR0, pDevIns, iBus),
1020 VERR_ALREADY_EXISTS);
1021
1022 /*
1023 * Do the registering.
1024 */
1025 pPciBusR0->iBus = iBus;
1026 pPciBusR0->uPadding0 = 0xbeefbeef;
1027 pPciBusR0->pfnSetIrqR0 = pPciBusReg->pfnSetIrq;
1028 pPciBusR0->pDevInsR0 = pDevIns;
1029
1030 *ppPciHlp = &g_pdmR0PciHlp;
1031
1032 LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: returns VINF_SUCCESS\n", pDevIns, pDevIns->iInstance));
1033 return VINF_SUCCESS;
1034}
1035
1036
1037/** @interface_method_impl{PDMDEVHLPR0,pfnIommuSetUpContext} */
1038static DECLCALLBACK(int) pdmR0DevHlp_IommuSetUpContext(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp)
1039{
1040 PDMDEV_ASSERT_DEVINS(pDevIns);
1041 LogFlow(("pdmR0DevHlp_IommuSetUpContext: caller='%p'/%d: pIommuReg=%p{.u32Version=%#x, u32TheEnd=%#x} ppIommuHlp=%p\n",
1042 pDevIns, pDevIns->iInstance, pIommuReg, pIommuReg->u32Version, pIommuReg->u32TheEnd, ppIommuHlp));
1043 PGVM pGVM = pDevIns->Internal.s.pGVM;
1044
1045 /*
1046 * Validate input.
1047 */
1048 AssertPtrReturn(pIommuReg, VERR_INVALID_POINTER);
1049 AssertLogRelMsgReturn(pIommuReg->u32Version == PDM_IOMMUREGCC_VERSION,
1050 ("%#x vs %#x\n", pIommuReg->u32Version, PDM_IOMMUREGCC_VERSION), VERR_VERSION_MISMATCH);
1051 AssertLogRelMsgReturn(pIommuReg->u32TheEnd == PDM_IOMMUREGCC_VERSION,
1052 ("%#x vs %#x\n", pIommuReg->u32TheEnd, PDM_IOMMUREGCC_VERSION), VERR_VERSION_MISMATCH);
1053
1054 AssertPtrReturn(ppIommuHlp, VERR_INVALID_POINTER);
1055
1056 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1057 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1058
1059 /* Check the IOMMU shared data (registered earlier from ring-3). */
1060 uint32_t const idxIommu = pIommuReg->idxIommu;
1061 ASMCompilerBarrier();
1062 AssertLogRelMsgReturn(idxIommu < RT_ELEMENTS(pGVM->pdm.s.aIommus), ("idxIommu=%#x\n", idxIommu), VERR_OUT_OF_RANGE);
1063 PPDMIOMMU pIommuShared = &pGVM->pdm.s.aIommus[idxIommu];
1064 AssertLogRelMsgReturn(pIommuShared->idxIommu == idxIommu, ("%u vs %u\n", pIommuShared->idxIommu, idxIommu), VERR_INVALID_PARAMETER);
1065 AssertLogRelMsgReturn(pIommuShared->pDevInsR3 == pDevIns->pDevInsForR3,
1066 ("%p vs %p (idxIommu=%u)\n", pIommuShared->pDevInsR3, pDevIns->pDevInsForR3, idxIommu), VERR_NOT_OWNER);
1067
1068 /* Check that the IOMMU isn't already registered in ring-0. */
1069 AssertCompile(RT_ELEMENTS(pGVM->pdm.s.aIommus) == RT_ELEMENTS(pGVM->pdmr0.s.aIommus));
1070 PPDMIOMMUR0 pIommuR0 = &pGVM->pdmr0.s.aIommus[idxIommu];
1071 AssertLogRelMsgReturn(pIommuR0->pDevInsR0 == NULL,
1072 ("%p (caller pDevIns=%p, idxIommu=%u)\n", pIommuR0->pDevInsR0, pDevIns, idxIommu),
1073 VERR_ALREADY_EXISTS);
1074
1075 /*
1076 * Register.
1077 */
1078 pIommuR0->idxIommu = idxIommu;
1079 pIommuR0->uPadding0 = 0xdeaddead;
1080 pIommuR0->pDevInsR0 = pDevIns;
1081
1082 *ppIommuHlp = &g_pdmR0IommuHlp;
1083
1084 LogFlow(("pdmR0DevHlp_IommuSetUpContext: caller='%p'/%d: returns VINF_SUCCESS\n", pDevIns, pDevIns->iInstance));
1085 return VINF_SUCCESS;
1086}
1087
1088
1089/** @interface_method_impl{PDMDEVHLPR0,pfnPICSetUpContext} */
1090static DECLCALLBACK(int) pdmR0DevHlp_PICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
1091{
1092 PDMDEV_ASSERT_DEVINS(pDevIns);
1093 LogFlow(("pdmR0DevHlp_PICSetUpContext: caller='%s'/%d: pPicReg=%p:{.u32Version=%#x, .pfnSetIrq=%p, .pfnGetInterrupt=%p, .u32TheEnd=%#x } ppPicHlp=%p\n",
1094 pDevIns->pReg->szName, pDevIns->iInstance, pPicReg, pPicReg->u32Version, pPicReg->pfnSetIrq, pPicReg->pfnGetInterrupt, pPicReg->u32TheEnd, ppPicHlp));
1095 PGVM pGVM = pDevIns->Internal.s.pGVM;
1096
1097 /*
1098 * Validate input.
1099 */
1100 AssertMsgReturn(pPicReg->u32Version == PDM_PICREG_VERSION,
1101 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pPicReg->u32Version, PDM_PICREG_VERSION),
1102 VERR_VERSION_MISMATCH);
1103 AssertPtrReturn(pPicReg->pfnSetIrq, VERR_INVALID_POINTER);
1104 AssertPtrReturn(pPicReg->pfnGetInterrupt, VERR_INVALID_POINTER);
1105 AssertMsgReturn(pPicReg->u32TheEnd == PDM_PICREG_VERSION,
1106 ("%s/%d: u32TheEnd=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pPicReg->u32TheEnd, PDM_PICREG_VERSION),
1107 VERR_VERSION_MISMATCH);
1108 AssertPtrReturn(ppPicHlp, VERR_INVALID_POINTER);
1109
1110 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1111 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1112
1113 /* Check that it's the same device as made the ring-3 registrations: */
1114 AssertLogRelMsgReturn(pGVM->pdm.s.Pic.pDevInsR3 == pDevIns->pDevInsForR3,
1115 ("%p vs %p\n", pGVM->pdm.s.Pic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1116
1117 /* Check that it isn't already registered in ring-0: */
1118 AssertLogRelMsgReturn(pGVM->pdm.s.Pic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Pic.pDevInsR0, pDevIns),
1119 VERR_ALREADY_EXISTS);
1120
1121 /*
1122 * Take down the callbacks and instance.
1123 */
1124 pGVM->pdm.s.Pic.pDevInsR0 = pDevIns;
1125 pGVM->pdm.s.Pic.pfnSetIrqR0 = pPicReg->pfnSetIrq;
1126 pGVM->pdm.s.Pic.pfnGetInterruptR0 = pPicReg->pfnGetInterrupt;
1127 Log(("PDM: Registered PIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1128
1129 /* set the helper pointer and return. */
1130 *ppPicHlp = &g_pdmR0PicHlp;
1131 LogFlow(("pdmR0DevHlp_PICSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1132 return VINF_SUCCESS;
1133}
1134
1135
1136/** @interface_method_impl{PDMDEVHLPR0,pfnApicSetUpContext} */
1137static DECLCALLBACK(int) pdmR0DevHlp_ApicSetUpContext(PPDMDEVINS pDevIns)
1138{
1139 PDMDEV_ASSERT_DEVINS(pDevIns);
1140 LogFlow(("pdmR0DevHlp_ApicSetUpContext: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
1141 PGVM pGVM = pDevIns->Internal.s.pGVM;
1142
1143 /*
1144 * Validate input.
1145 */
1146 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1147 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1148
1149 /* Check that it's the same device as made the ring-3 registrations: */
1150 AssertLogRelMsgReturn(pGVM->pdm.s.Apic.pDevInsR3 == pDevIns->pDevInsForR3,
1151 ("%p vs %p\n", pGVM->pdm.s.Apic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1152
1153 /* Check that it isn't already registered in ring-0: */
1154 AssertLogRelMsgReturn(pGVM->pdm.s.Apic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Apic.pDevInsR0, pDevIns),
1155 VERR_ALREADY_EXISTS);
1156
1157 /*
1158 * Take down the instance.
1159 */
1160 pGVM->pdm.s.Apic.pDevInsR0 = pDevIns;
1161 Log(("PDM: Registered APIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1162
1163 /* set the helper pointer and return. */
1164 LogFlow(("pdmR0DevHlp_ApicSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1165 return VINF_SUCCESS;
1166}
1167
1168
1169/** @interface_method_impl{PDMDEVHLPR0,pfnIoApicSetUpContext} */
1170static DECLCALLBACK(int) pdmR0DevHlp_IoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
1171{
1172 PDMDEV_ASSERT_DEVINS(pDevIns);
1173 LogFlow(("pdmR0DevHlp_IoApicSetUpContext: caller='%s'/%d: pIoApicReg=%p:{.u32Version=%#x, .pfnSetIrq=%p, .pfnSendMsi=%p, .pfnSetEoi=%p, .u32TheEnd=%#x } ppIoApicHlp=%p\n",
1174 pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg, pIoApicReg->u32Version, pIoApicReg->pfnSetIrq, pIoApicReg->pfnSendMsi, pIoApicReg->pfnSetEoi, pIoApicReg->u32TheEnd, ppIoApicHlp));
1175 PGVM pGVM = pDevIns->Internal.s.pGVM;
1176
1177 /*
1178 * Validate input.
1179 */
1180 AssertMsgReturn(pIoApicReg->u32Version == PDM_IOAPICREG_VERSION,
1181 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg->u32Version, PDM_IOAPICREG_VERSION),
1182 VERR_VERSION_MISMATCH);
1183 AssertPtrReturn(pIoApicReg->pfnSetIrq, VERR_INVALID_POINTER);
1184 AssertPtrReturn(pIoApicReg->pfnSendMsi, VERR_INVALID_POINTER);
1185 AssertPtrReturn(pIoApicReg->pfnSetEoi, VERR_INVALID_POINTER);
1186 AssertMsgReturn(pIoApicReg->u32TheEnd == PDM_IOAPICREG_VERSION,
1187 ("%s/%d: u32TheEnd=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg->u32TheEnd, PDM_IOAPICREG_VERSION),
1188 VERR_VERSION_MISMATCH);
1189 AssertPtrReturn(ppIoApicHlp, VERR_INVALID_POINTER);
1190
1191 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1192 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1193
1194 /* Check that it's the same device as made the ring-3 registrations: */
1195 AssertLogRelMsgReturn(pGVM->pdm.s.IoApic.pDevInsR3 == pDevIns->pDevInsForR3,
1196 ("%p vs %p\n", pGVM->pdm.s.IoApic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1197
1198 /* Check that it isn't already registered in ring-0: */
1199 AssertLogRelMsgReturn(pGVM->pdm.s.IoApic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.IoApic.pDevInsR0, pDevIns),
1200 VERR_ALREADY_EXISTS);
1201
1202 /*
1203 * Take down the callbacks and instance.
1204 */
1205 pGVM->pdm.s.IoApic.pDevInsR0 = pDevIns;
1206 pGVM->pdm.s.IoApic.pfnSetIrqR0 = pIoApicReg->pfnSetIrq;
1207 pGVM->pdm.s.IoApic.pfnSendMsiR0 = pIoApicReg->pfnSendMsi;
1208 pGVM->pdm.s.IoApic.pfnSetEoiR0 = pIoApicReg->pfnSetEoi;
1209 Log(("PDM: Registered IOAPIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1210
1211 /* set the helper pointer and return. */
1212 *ppIoApicHlp = &g_pdmR0IoApicHlp;
1213 LogFlow(("pdmR0DevHlp_IoApicSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1214 return VINF_SUCCESS;
1215}
1216
1217
1218/** @interface_method_impl{PDMDEVHLPR0,pfnHpetSetUpContext} */
1219static DECLCALLBACK(int) pdmR0DevHlp_HpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp)
1220{
1221 PDMDEV_ASSERT_DEVINS(pDevIns);
1222 LogFlow(("pdmR0DevHlp_HpetSetUpContext: caller='%s'/%d: pHpetReg=%p:{.u32Version=%#x, } ppHpetHlp=%p\n",
1223 pDevIns->pReg->szName, pDevIns->iInstance, pHpetReg, pHpetReg->u32Version, ppHpetHlp));
1224 PGVM pGVM = pDevIns->Internal.s.pGVM;
1225
1226 /*
1227 * Validate input.
1228 */
1229 AssertMsgReturn(pHpetReg->u32Version == PDM_HPETREG_VERSION,
1230 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pHpetReg->u32Version, PDM_HPETREG_VERSION),
1231 VERR_VERSION_MISMATCH);
1232 AssertPtrReturn(ppHpetHlp, VERR_INVALID_POINTER);
1233
1234 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1235 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1236
1237 /* Check that it's the same device as made the ring-3 registrations: */
1238 AssertLogRelMsgReturn(pGVM->pdm.s.pHpet == pDevIns->pDevInsForR3, ("%p vs %p\n", pGVM->pdm.s.pHpet, pDevIns->pDevInsForR3),
1239 VERR_NOT_OWNER);
1240
1241 ///* Check that it isn't already registered in ring-0: */
1242 //AssertLogRelMsgReturn(pGVM->pdm.s.Hpet.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Hpet.pDevInsR0, pDevIns),
1243 // VERR_ALREADY_EXISTS);
1244
1245 /*
1246 * Nothing to take down here at present.
1247 */
1248 Log(("PDM: Registered HPET device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1249
1250 /* set the helper pointer and return. */
1251 *ppHpetHlp = &g_pdmR0HpetHlp;
1252 LogFlow(("pdmR0DevHlp_HpetSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1253 return VINF_SUCCESS;
1254}
1255
1256
1257/**
1258 * The Ring-0 Device Helper Callbacks.
1259 */
1260extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp =
1261{
1262 PDM_DEVHLPR0_VERSION,
1263 pdmR0DevHlp_IoPortSetUpContextEx,
1264 pdmR0DevHlp_MmioSetUpContextEx,
1265 pdmR0DevHlp_Mmio2SetUpContext,
1266 pdmR0DevHlp_PCIPhysRead,
1267 pdmR0DevHlp_PCIPhysWrite,
1268 pdmR0DevHlp_PCISetIrq,
1269 pdmR0DevHlp_ISASetIrq,
1270 pdmR0DevHlp_PhysRead,
1271 pdmR0DevHlp_PhysWrite,
1272 pdmR0DevHlp_A20IsEnabled,
1273 pdmR0DevHlp_VMState,
1274 pdmR0DevHlp_VMSetError,
1275 pdmR0DevHlp_VMSetErrorV,
1276 pdmR0DevHlp_VMSetRuntimeError,
1277 pdmR0DevHlp_VMSetRuntimeErrorV,
1278 pdmR0DevHlp_GetVM,
1279 pdmR0DevHlp_GetVMCPU,
1280 pdmR0DevHlp_GetCurrentCpuId,
1281 pdmR0DevHlp_TimerToPtr,
1282 pdmR0DevHlp_TimerFromMicro,
1283 pdmR0DevHlp_TimerFromMilli,
1284 pdmR0DevHlp_TimerFromNano,
1285 pdmR0DevHlp_TimerGet,
1286 pdmR0DevHlp_TimerGetFreq,
1287 pdmR0DevHlp_TimerGetNano,
1288 pdmR0DevHlp_TimerIsActive,
1289 pdmR0DevHlp_TimerIsLockOwner,
1290 pdmR0DevHlp_TimerLockClock,
1291 pdmR0DevHlp_TimerLockClock2,
1292 pdmR0DevHlp_TimerSet,
1293 pdmR0DevHlp_TimerSetFrequencyHint,
1294 pdmR0DevHlp_TimerSetMicro,
1295 pdmR0DevHlp_TimerSetMillies,
1296 pdmR0DevHlp_TimerSetNano,
1297 pdmR0DevHlp_TimerSetRelative,
1298 pdmR0DevHlp_TimerStop,
1299 pdmR0DevHlp_TimerUnlockClock,
1300 pdmR0DevHlp_TimerUnlockClock2,
1301 pdmR0DevHlp_TMTimeVirtGet,
1302 pdmR0DevHlp_TMTimeVirtGetFreq,
1303 pdmR0DevHlp_TMTimeVirtGetNano,
1304 pdmR0DevHlp_QueueToPtr,
1305 pdmR0DevHlp_QueueAlloc,
1306 pdmR0DevHlp_QueueInsert,
1307 pdmR0DevHlp_QueueInsertEx,
1308 pdmR0DevHlp_QueueFlushIfNecessary,
1309 pdmR0DevHlp_TaskTrigger,
1310 pdmR0DevHlp_SUPSemEventSignal,
1311 pdmR0DevHlp_SUPSemEventWaitNoResume,
1312 pdmR0DevHlp_SUPSemEventWaitNsAbsIntr,
1313 pdmR0DevHlp_SUPSemEventWaitNsRelIntr,
1314 pdmR0DevHlp_SUPSemEventGetResolution,
1315 pdmR0DevHlp_SUPSemEventMultiSignal,
1316 pdmR0DevHlp_SUPSemEventMultiReset,
1317 pdmR0DevHlp_SUPSemEventMultiWaitNoResume,
1318 pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr,
1319 pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr,
1320 pdmR0DevHlp_SUPSemEventMultiGetResolution,
1321 pdmR0DevHlp_CritSectGetNop,
1322 pdmR0DevHlp_SetDeviceCritSect,
1323 pdmR0DevHlp_CritSectEnter,
1324 pdmR0DevHlp_CritSectEnterDebug,
1325 pdmR0DevHlp_CritSectTryEnter,
1326 pdmR0DevHlp_CritSectTryEnterDebug,
1327 pdmR0DevHlp_CritSectLeave,
1328 pdmR0DevHlp_CritSectIsOwner,
1329 pdmR0DevHlp_CritSectIsInitialized,
1330 pdmR0DevHlp_CritSectHasWaiters,
1331 pdmR0DevHlp_CritSectGetRecursion,
1332 pdmR0DevHlp_CritSectScheduleExitEvent,
1333 pdmR0DevHlp_DBGFTraceBuf,
1334 pdmR0DevHlp_PCIBusSetUpContext,
1335 pdmR0DevHlp_IommuSetUpContext,
1336 pdmR0DevHlp_PICSetUpContext,
1337 pdmR0DevHlp_ApicSetUpContext,
1338 pdmR0DevHlp_IoApicSetUpContext,
1339 pdmR0DevHlp_HpetSetUpContext,
1340 NULL /*pfnReserved1*/,
1341 NULL /*pfnReserved2*/,
1342 NULL /*pfnReserved3*/,
1343 NULL /*pfnReserved4*/,
1344 NULL /*pfnReserved5*/,
1345 NULL /*pfnReserved6*/,
1346 NULL /*pfnReserved7*/,
1347 NULL /*pfnReserved8*/,
1348 NULL /*pfnReserved9*/,
1349 NULL /*pfnReserved10*/,
1350 PDM_DEVHLPR0_VERSION
1351};
1352
1353
1354#ifdef VBOX_WITH_DBGF_TRACING
1355/**
1356 * The Ring-0 Device Helper Callbacks - tracing variant.
1357 */
1358extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlpTracing =
1359{
1360 PDM_DEVHLPR0_VERSION,
1361 pdmR0DevHlpTracing_IoPortSetUpContextEx,
1362 pdmR0DevHlpTracing_MmioSetUpContextEx,
1363 pdmR0DevHlp_Mmio2SetUpContext,
1364 pdmR0DevHlpTracing_PCIPhysRead,
1365 pdmR0DevHlpTracing_PCIPhysWrite,
1366 pdmR0DevHlpTracing_PCISetIrq,
1367 pdmR0DevHlpTracing_ISASetIrq,
1368 pdmR0DevHlp_PhysRead,
1369 pdmR0DevHlp_PhysWrite,
1370 pdmR0DevHlp_A20IsEnabled,
1371 pdmR0DevHlp_VMState,
1372 pdmR0DevHlp_VMSetError,
1373 pdmR0DevHlp_VMSetErrorV,
1374 pdmR0DevHlp_VMSetRuntimeError,
1375 pdmR0DevHlp_VMSetRuntimeErrorV,
1376 pdmR0DevHlp_GetVM,
1377 pdmR0DevHlp_GetVMCPU,
1378 pdmR0DevHlp_GetCurrentCpuId,
1379 pdmR0DevHlp_TimerToPtr,
1380 pdmR0DevHlp_TimerFromMicro,
1381 pdmR0DevHlp_TimerFromMilli,
1382 pdmR0DevHlp_TimerFromNano,
1383 pdmR0DevHlp_TimerGet,
1384 pdmR0DevHlp_TimerGetFreq,
1385 pdmR0DevHlp_TimerGetNano,
1386 pdmR0DevHlp_TimerIsActive,
1387 pdmR0DevHlp_TimerIsLockOwner,
1388 pdmR0DevHlp_TimerLockClock,
1389 pdmR0DevHlp_TimerLockClock2,
1390 pdmR0DevHlp_TimerSet,
1391 pdmR0DevHlp_TimerSetFrequencyHint,
1392 pdmR0DevHlp_TimerSetMicro,
1393 pdmR0DevHlp_TimerSetMillies,
1394 pdmR0DevHlp_TimerSetNano,
1395 pdmR0DevHlp_TimerSetRelative,
1396 pdmR0DevHlp_TimerStop,
1397 pdmR0DevHlp_TimerUnlockClock,
1398 pdmR0DevHlp_TimerUnlockClock2,
1399 pdmR0DevHlp_TMTimeVirtGet,
1400 pdmR0DevHlp_TMTimeVirtGetFreq,
1401 pdmR0DevHlp_TMTimeVirtGetNano,
1402 pdmR0DevHlp_QueueToPtr,
1403 pdmR0DevHlp_QueueAlloc,
1404 pdmR0DevHlp_QueueInsert,
1405 pdmR0DevHlp_QueueInsertEx,
1406 pdmR0DevHlp_QueueFlushIfNecessary,
1407 pdmR0DevHlp_TaskTrigger,
1408 pdmR0DevHlp_SUPSemEventSignal,
1409 pdmR0DevHlp_SUPSemEventWaitNoResume,
1410 pdmR0DevHlp_SUPSemEventWaitNsAbsIntr,
1411 pdmR0DevHlp_SUPSemEventWaitNsRelIntr,
1412 pdmR0DevHlp_SUPSemEventGetResolution,
1413 pdmR0DevHlp_SUPSemEventMultiSignal,
1414 pdmR0DevHlp_SUPSemEventMultiReset,
1415 pdmR0DevHlp_SUPSemEventMultiWaitNoResume,
1416 pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr,
1417 pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr,
1418 pdmR0DevHlp_SUPSemEventMultiGetResolution,
1419 pdmR0DevHlp_CritSectGetNop,
1420 pdmR0DevHlp_SetDeviceCritSect,
1421 pdmR0DevHlp_CritSectEnter,
1422 pdmR0DevHlp_CritSectEnterDebug,
1423 pdmR0DevHlp_CritSectTryEnter,
1424 pdmR0DevHlp_CritSectTryEnterDebug,
1425 pdmR0DevHlp_CritSectLeave,
1426 pdmR0DevHlp_CritSectIsOwner,
1427 pdmR0DevHlp_CritSectIsInitialized,
1428 pdmR0DevHlp_CritSectHasWaiters,
1429 pdmR0DevHlp_CritSectGetRecursion,
1430 pdmR0DevHlp_CritSectScheduleExitEvent,
1431 pdmR0DevHlp_DBGFTraceBuf,
1432 pdmR0DevHlp_PCIBusSetUpContext,
1433 pdmR0DevHlp_IommuSetUpContext,
1434 pdmR0DevHlp_PICSetUpContext,
1435 pdmR0DevHlp_ApicSetUpContext,
1436 pdmR0DevHlp_IoApicSetUpContext,
1437 pdmR0DevHlp_HpetSetUpContext,
1438 NULL /*pfnReserved1*/,
1439 NULL /*pfnReserved2*/,
1440 NULL /*pfnReserved3*/,
1441 NULL /*pfnReserved4*/,
1442 NULL /*pfnReserved5*/,
1443 NULL /*pfnReserved6*/,
1444 NULL /*pfnReserved7*/,
1445 NULL /*pfnReserved8*/,
1446 NULL /*pfnReserved9*/,
1447 NULL /*pfnReserved10*/,
1448 PDM_DEVHLPR0_VERSION
1449};
1450#endif
1451
1452
1453/** @} */
1454
1455
1456/** @name PIC Ring-0 Helpers
1457 * @{
1458 */
1459
1460/** @interface_method_impl{PDMPICHLP,pfnSetInterruptFF} */
1461static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
1462{
1463 PDMDEV_ASSERT_DEVINS(pDevIns);
1464 PGVM pGVM = (PGVM)pDevIns->Internal.s.pGVM;
1465 PVMCPUCC pVCpu = &pGVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
1466 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
1467 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
1468}
1469
1470
1471/** @interface_method_impl{PDMPICHLP,pfnClearInterruptFF} */
1472static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
1473{
1474 PDMDEV_ASSERT_DEVINS(pDevIns);
1475 PGVM pGVM = (PGVM)pDevIns->Internal.s.pGVM;
1476 PVMCPUCC pVCpu = &pGVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
1477 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
1478 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
1479}
1480
1481
1482/** @interface_method_impl{PDMPICHLP,pfnLock} */
1483static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
1484{
1485 PDMDEV_ASSERT_DEVINS(pDevIns);
1486 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1487}
1488
1489
1490/** @interface_method_impl{PDMPICHLP,pfnUnlock} */
1491static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns)
1492{
1493 PDMDEV_ASSERT_DEVINS(pDevIns);
1494 pdmUnlock(pDevIns->Internal.s.pGVM);
1495}
1496
1497
1498/**
1499 * The Ring-0 PIC Helper Callbacks.
1500 */
1501extern DECLEXPORT(const PDMPICHLP) g_pdmR0PicHlp =
1502{
1503 PDM_PICHLP_VERSION,
1504 pdmR0PicHlp_SetInterruptFF,
1505 pdmR0PicHlp_ClearInterruptFF,
1506 pdmR0PicHlp_Lock,
1507 pdmR0PicHlp_Unlock,
1508 PDM_PICHLP_VERSION
1509};
1510
1511/** @} */
1512
1513
1514/** @name I/O APIC Ring-0 Helpers
1515 * @{
1516 */
1517
1518/** @interface_method_impl{PDMIOAPICHLP,pfnApicBusDeliver} */
1519static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
1520 uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
1521 uint8_t u8TriggerMode, uint32_t uTagSrc)
1522{
1523 PDMDEV_ASSERT_DEVINS(pDevIns);
1524 PGVM pGVM = pDevIns->Internal.s.pGVM;
1525 LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
1526 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
1527 return APICBusDeliver(pGVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
1528}
1529
1530
1531/** @interface_method_impl{PDMIOAPICHLP,pfnLock} */
1532static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
1533{
1534 PDMDEV_ASSERT_DEVINS(pDevIns);
1535 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1536}
1537
1538
1539/** @interface_method_impl{PDMIOAPICHLP,pfnUnlock} */
1540static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns)
1541{
1542 PDMDEV_ASSERT_DEVINS(pDevIns);
1543 pdmUnlock(pDevIns->Internal.s.pGVM);
1544}
1545
1546
1547/** @interface_method_impl{PDMIOAPICHLP,pfnIommuMsiRemap} */
1548static DECLCALLBACK(int) pdmR0IoApicHlp_IommuMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1549{
1550 PDMDEV_ASSERT_DEVINS(pDevIns);
1551 LogFlow(("pdmR0IoApicHlp_IommuMsiRemap: caller='%s'/%d: pMsiIn=(%#RX64, %#RU32)\n", pDevIns->pReg->szName,
1552 pDevIns->iInstance, pMsiIn->Addr.u64, pMsiIn->Data.u32));
1553
1554#ifdef VBOX_WITH_IOMMU_AMD
1555 /** @todo IOMMU: Optimize/re-organize things here later. */
1556 PGVM pGVM = pDevIns->Internal.s.pGVM;
1557 PPDMIOMMUR0 pIommu = &pGVM->pdmr0.s.aIommus[0];
1558 PPDMDEVINS pDevInsIommu = pIommu->CTX_SUFF(pDevIns);
1559 if ( pDevInsIommu
1560 && pDevInsIommu != pDevIns)
1561 {
1562 int rc = pIommu->pfnMsiRemap(pDevInsIommu, uDevId, pMsiIn, pMsiOut);
1563 if (RT_FAILURE(rc))
1564 {
1565 Log(("pdmR0IoApicHlp_IommuMsiRemap: IOMMU MSI remap failed. uDevId=%#x pMsiIn=(%#RX64, %#RU32) rc=%Rrc\n",
1566 uDevId, pMsiIn->Addr.u64, pMsiIn->Data.u32, rc));
1567 return rc;
1568 }
1569 }
1570#else
1571 RT_NOREF(pDevIns, uDevId);
1572 *pMsiOut = *pMsiIn;
1573#endif
1574 return VINF_SUCCESS;
1575}
1576
1577
1578/**
1579 * The Ring-0 I/O APIC Helper Callbacks.
1580 */
1581extern DECLEXPORT(const PDMIOAPICHLP) g_pdmR0IoApicHlp =
1582{
1583 PDM_IOAPICHLP_VERSION,
1584 pdmR0IoApicHlp_ApicBusDeliver,
1585 pdmR0IoApicHlp_Lock,
1586 pdmR0IoApicHlp_Unlock,
1587 pdmR0IoApicHlp_IommuMsiRemap,
1588 PDM_IOAPICHLP_VERSION
1589};
1590
1591/** @} */
1592
1593
1594
1595
1596/** @name PCI Bus Ring-0 Helpers
1597 * @{
1598 */
1599
1600/** @interface_method_impl{PDMPCIHLPR0,pfnIsaSetIrq} */
1601static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
1602{
1603 PDMDEV_ASSERT_DEVINS(pDevIns);
1604 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
1605 PGVM pGVM = pDevIns->Internal.s.pGVM;
1606
1607 pdmLock(pGVM);
1608 pdmR0IsaSetIrq(pGVM, iIrq, iLevel, uTagSrc);
1609 pdmUnlock(pGVM);
1610}
1611
1612
1613/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSetIrq} */
1614static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
1615{
1616 PDMDEV_ASSERT_DEVINS(pDevIns);
1617 Log4(("pdmR0PciHlp_IoApicSetIrq: uBusDevFn=%#x iIrq=%d iLevel=%d uTagSrc=%#x\n", uBusDevFn, iIrq, iLevel, uTagSrc));
1618 PGVM pGVM = pDevIns->Internal.s.pGVM;
1619
1620 if (pGVM->pdm.s.IoApic.pDevInsR0)
1621 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, uBusDevFn, iIrq, iLevel, uTagSrc);
1622 else if (pGVM->pdm.s.IoApic.pDevInsR3)
1623 {
1624 /* queue for ring-3 execution. */
1625 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
1626 if (pTask)
1627 {
1628 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
1629 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
1630 pTask->u.IoApicSetIRQ.uBusDevFn = uBusDevFn;
1631 pTask->u.IoApicSetIRQ.iIrq = iIrq;
1632 pTask->u.IoApicSetIRQ.iLevel = iLevel;
1633 pTask->u.IoApicSetIRQ.uTagSrc = uTagSrc;
1634
1635 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
1636 }
1637 else
1638 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
1639 }
1640}
1641
1642
1643/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSendMsi} */
1644static DECLCALLBACK(void) pdmR0PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
1645{
1646 PDMDEV_ASSERT_DEVINS(pDevIns);
1647 Assert(PCIBDF_IS_VALID(uBusDevFn));
1648 Log4(("pdmR0PciHlp_IoApicSendMsi: uBusDevFn=%#x Msi=(Addr:%#RX64 Data:%#RX32) uTagSrc=%#x\n", uBusDevFn, pMsi->Addr.u64,
1649 pMsi->Data.u32, uTagSrc));
1650 PGVM pGVM = pDevIns->Internal.s.pGVM;
1651 if (pGVM->pdm.s.IoApic.pDevInsR0)
1652 pGVM->pdm.s.IoApic.pfnSendMsiR0(pGVM->pdm.s.IoApic.pDevInsR0, uBusDevFn, pMsi, uTagSrc);
1653 else
1654 AssertFatalMsgFailed(("Lazy bastards!"));
1655}
1656
1657
1658/** @interface_method_impl{PDMPCIHLPR0,pfnLock} */
1659static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
1660{
1661 PDMDEV_ASSERT_DEVINS(pDevIns);
1662 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1663}
1664
1665
1666/** @interface_method_impl{PDMPCIHLPR0,pfnUnlock} */
1667static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns)
1668{
1669 PDMDEV_ASSERT_DEVINS(pDevIns);
1670 pdmUnlock(pDevIns->Internal.s.pGVM);
1671}
1672
1673
1674/** @interface_method_impl{PDMPCIHLPR0,pfnGetBusByNo} */
1675static DECLCALLBACK(PPDMDEVINS) pdmR0PciHlp_GetBusByNo(PPDMDEVINS pDevIns, uint32_t idxPdmBus)
1676{
1677 PDMDEV_ASSERT_DEVINS(pDevIns);
1678 PGVM pGVM = pDevIns->Internal.s.pGVM;
1679 AssertReturn(idxPdmBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses), NULL);
1680 PPDMDEVINS pRetDevIns = pGVM->pdmr0.s.aPciBuses[idxPdmBus].pDevInsR0;
1681 LogFlow(("pdmR3PciHlp_GetBusByNo: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRetDevIns));
1682 return pRetDevIns;
1683}
1684
1685
1686/**
1687 * The Ring-0 PCI Bus Helper Callbacks.
1688 */
1689extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp =
1690{
1691 PDM_PCIHLPR0_VERSION,
1692 pdmR0PciHlp_IsaSetIrq,
1693 pdmR0PciHlp_IoApicSetIrq,
1694 pdmR0PciHlp_IoApicSendMsi,
1695 pdmR0PciHlp_Lock,
1696 pdmR0PciHlp_Unlock,
1697 pdmR0PciHlp_GetBusByNo,
1698 PDM_PCIHLPR0_VERSION, /* the end */
1699};
1700
1701/** @} */
1702
1703
1704/** @name IOMMU Ring-0 Helpers
1705 * @{
1706 */
1707
1708/**
1709 * The Ring-0 IOMMU Helper Callbacks.
1710 */
1711extern DECLEXPORT(const PDMIOMMUHLPR0) g_pdmR0IommuHlp =
1712{
1713 PDM_IOMMUHLPR0_VERSION,
1714 PDM_IOMMUHLPR0_VERSION, /* the end */
1715};
1716
1717/** @} */
1718
1719
1720/** @name HPET Ring-0 Helpers
1721 * @{
1722 */
1723/* none */
1724
1725/**
1726 * The Ring-0 HPET Helper Callbacks.
1727 */
1728extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp =
1729{
1730 PDM_HPETHLPR0_VERSION,
1731 PDM_HPETHLPR0_VERSION, /* the end */
1732};
1733
1734/** @} */
1735
1736
1737/** @name Raw PCI Ring-0 Helpers
1738 * @{
1739 */
1740/* none */
1741
1742/**
1743 * The Ring-0 PCI raw Helper Callbacks.
1744 */
1745extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp =
1746{
1747 PDM_PCIRAWHLPR0_VERSION,
1748 PDM_PCIRAWHLPR0_VERSION, /* the end */
1749};
1750
1751/** @} */
1752
1753
1754
1755
1756/**
1757 * Sets an irq on the PIC and I/O APIC.
1758 *
1759 * @returns true if delivered, false if postponed.
1760 * @param pGVM The global (ring-0) VM structure.
1761 * @param uBusDevFn The bus:device:function of the device initiating the IRQ.
1762 * Can be NIL_PCIBDF.
1763 * @param iIrq The irq.
1764 * @param iLevel The new level.
1765 * @param uTagSrc The IRQ tag and source.
1766 *
1767 * @remarks The caller holds the PDM lock.
1768 */
1769DECLHIDDEN(bool) pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc)
1770{
1771 if (RT_LIKELY( ( pGVM->pdm.s.IoApic.pDevInsR0
1772 || !pGVM->pdm.s.IoApic.pDevInsR3)
1773 && ( pGVM->pdm.s.Pic.pDevInsR0
1774 || !pGVM->pdm.s.Pic.pDevInsR3)))
1775 {
1776 if (pGVM->pdm.s.Pic.pDevInsR0)
1777 pGVM->pdm.s.Pic.pfnSetIrqR0(pGVM->pdm.s.Pic.pDevInsR0, iIrq, iLevel, uTagSrc);
1778 if (pGVM->pdm.s.IoApic.pDevInsR0)
1779 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, NIL_PCIBDF, iIrq, iLevel, uTagSrc);
1780 return true;
1781 }
1782
1783 /* queue for ring-3 execution. */
1784 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
1785 AssertReturn(pTask, false);
1786
1787 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
1788 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
1789 pTask->u.IsaSetIRQ.uBusDevFn = NIL_PCIBDF;
1790 pTask->u.IsaSetIRQ.iIrq = iIrq;
1791 pTask->u.IsaSetIRQ.iLevel = iLevel;
1792 pTask->u.IsaSetIRQ.uTagSrc = uTagSrc;
1793
1794 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
1795 return false;
1796}
1797
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette