VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/PDMR0DevHlp.cpp@ 87466

Last change on this file since 87466 was 87371, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Handle the case where an access might result in non-contiguous physical addresses after address translation via the IOMMU.
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1/* $Id: PDMR0DevHlp.cpp 87371 2021-01-22 14:42:17Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, R0 Device Helper parts.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
24#include "PDMInternal.h"
25#include <VBox/vmm/pdm.h>
26#include <VBox/vmm/apic.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/gvm.h>
30#include <VBox/vmm/vmm.h>
31#include <VBox/vmm/vmcc.h>
32#include <VBox/vmm/gvmm.h>
33
34#include <VBox/log.h>
35#include <VBox/err.h>
36#include <VBox/sup.h>
37#include <iprt/asm.h>
38#include <iprt/assert.h>
39#include <iprt/ctype.h>
40#include <iprt/string.h>
41
42#include "dtrace/VBoxVMM.h"
43#include "PDMInline.h"
44
45
46/*********************************************************************************************************************************
47* Global Variables *
48*********************************************************************************************************************************/
49RT_C_DECLS_BEGIN
50extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp;
51extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlpTracing;
52extern DECLEXPORT(const PDMPICHLP) g_pdmR0PicHlp;
53extern DECLEXPORT(const PDMIOAPICHLP) g_pdmR0IoApicHlp;
54extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp;
55extern DECLEXPORT(const PDMIOMMUHLPR0) g_pdmR0IommuHlp;
56extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp;
57extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp;
58RT_C_DECLS_END
59
60
61/*********************************************************************************************************************************
62* Internal Functions *
63*********************************************************************************************************************************/
64
65
66/** @name Ring-0 Device Helpers
67 * @{
68 */
69
70/** @interface_method_impl{PDMDEVHLPR0,pfnIoPortSetUpContextEx} */
71static DECLCALLBACK(int) pdmR0DevHlp_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
72 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
73 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
74 void *pvUser)
75{
76 PDMDEV_ASSERT_DEVINS(pDevIns);
77 LogFlow(("pdmR0DevHlp_IoPortSetUpContextEx: caller='%s'/%d: hIoPorts=%#x pfnOut=%p pfnIn=%p pfnOutStr=%p pfnInStr=%p pvUser=%p\n",
78 pDevIns->pReg->szName, pDevIns->iInstance, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser));
79 PGVM pGVM = pDevIns->Internal.s.pGVM;
80 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
81 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
82
83 int rc = IOMR0IoPortSetUpContext(pGVM, pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
84
85 LogFlow(("pdmR0DevHlp_IoPortSetUpContextEx: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
86 return rc;
87}
88
89
90/** @interface_method_impl{PDMDEVHLPR0,pfnMmioSetUpContextEx} */
91static DECLCALLBACK(int) pdmR0DevHlp_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
92 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
93{
94 PDMDEV_ASSERT_DEVINS(pDevIns);
95 LogFlow(("pdmR0DevHlp_MmioSetUpContextEx: caller='%s'/%d: hRegion=%#x pfnWrite=%p pfnRead=%p pfnFill=%p pvUser=%p\n",
96 pDevIns->pReg->szName, pDevIns->iInstance, hRegion, pfnWrite, pfnRead, pfnFill, pvUser));
97 PGVM pGVM = pDevIns->Internal.s.pGVM;
98 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
99 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
100
101 int rc = IOMR0MmioSetUpContext(pGVM, pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
102
103 LogFlow(("pdmR0DevHlp_MmioSetUpContextEx: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
104 return rc;
105}
106
107
108/** @interface_method_impl{PDMDEVHLPR0,pfnMmio2SetUpContext} */
109static DECLCALLBACK(int) pdmR0DevHlp_Mmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
110 size_t offSub, size_t cbSub, void **ppvMapping)
111{
112 PDMDEV_ASSERT_DEVINS(pDevIns);
113 LogFlow(("pdmR0DevHlp_Mmio2SetUpContext: caller='%s'/%d: hRegion=%#x offSub=%#zx cbSub=%#zx ppvMapping=%p\n",
114 pDevIns->pReg->szName, pDevIns->iInstance, hRegion, offSub, cbSub, ppvMapping));
115 *ppvMapping = NULL;
116
117 PGVM pGVM = pDevIns->Internal.s.pGVM;
118 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
119 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
120
121 int rc = PGMR0PhysMMIO2MapKernel(pGVM, pDevIns, hRegion, offSub, cbSub, ppvMapping);
122
123 LogFlow(("pdmR0DevHlp_Mmio2SetUpContext: caller='%s'/%d: returns %Rrc (%p)\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *ppvMapping));
124 return rc;
125}
126
127
128/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysRead} */
129static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
130 void *pvBuf, size_t cbRead, uint32_t fFlags)
131{
132 PDMDEV_ASSERT_DEVINS(pDevIns);
133 if (!pPciDev) /* NULL is an alias for the default PCI device. */
134 pPciDev = pDevIns->apPciDevs[0];
135 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
136 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
137
138#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
139 /*
140 * Just check the busmaster setting here and forward the request to the generic read helper.
141 */
142 if (PCIDevIsBusmaster(pPciDev))
143 { /* likely */ }
144 else
145 {
146 Log(("pdmRCDevHlp_PCIPhysRead: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#zx\n",
147 pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
148 memset(pvBuf, 0xff, cbRead);
149 return VERR_PDM_NOT_PCI_BUS_MASTER;
150 }
151#endif
152
153#ifdef VBOX_WITH_IOMMU_AMD
154 /** @todo IOMMU: Optimize/re-organize things here later. */
155 PGVM pGVM = pDevIns->Internal.s.pGVM;
156 PPDMIOMMUR0 pIommu = &pGVM->pdmr0.s.aIommus[0];
157 PPDMDEVINS pDevInsIommu = pIommu->CTX_SUFF(pDevIns);
158 if ( pDevInsIommu
159 && pDevInsIommu != pDevIns)
160 {
161 size_t const idxBus = pPciDev->Int.s.idxPdmBus;
162 Assert(idxBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
163 PPDMPCIBUSR0 pBus = &pGVM->pdmr0.s.aPciBuses[idxBus];
164 uint16_t const uDeviceId = PCIBDF_MAKE(pBus->iBus, pPciDev->uDevFn);
165 int rc = VINF_SUCCESS;
166 while (cbRead > 0)
167 {
168 RTGCPHYS GCPhysOut;
169 size_t cbContig;
170 rc = pIommu->pfnMemAccess(pDevInsIommu, uDeviceId, GCPhys, cbRead, PDMIOMMU_MEM_F_READ, &GCPhysOut, &cbContig);
171 if (RT_SUCCESS(rc))
172 {
173 /** @todo Handle strict return codes from PGMPhysRead. */
174 rc = pDevIns->pHlpR0->pfnPhysRead(pDevIns, GCPhysOut, pvBuf, cbRead, fFlags);
175 if (RT_SUCCESS(rc))
176 {
177 cbRead -= cbContig;
178 pvBuf = (void *)((uintptr_t)pvBuf + cbContig);
179 GCPhys += cbContig;
180 }
181 else
182 break;
183 }
184 else
185 {
186 Log(("pdmR0DevHlp_PCIPhysRead: IOMMU translation failed. uDeviceId=%#x GCPhys=%#RGp cb=%u rc=%Rrc\n", uDeviceId,
187 GCPhys, cbRead, rc));
188 break;
189 }
190 }
191 return rc;
192 }
193#endif
194
195 return pDevIns->pHlpR0->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, fFlags);
196}
197
198
199/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysWrite} */
200static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
201 const void *pvBuf, size_t cbWrite, uint32_t fFlags)
202{
203 PDMDEV_ASSERT_DEVINS(pDevIns);
204 if (!pPciDev) /* NULL is an alias for the default PCI device. */
205 pPciDev = pDevIns->apPciDevs[0];
206 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
207 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
208
209#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
210 /*
211 * Just check the busmaster setting here and forward the request to the generic read helper.
212 */
213 if (PCIDevIsBusmaster(pPciDev))
214 { /* likely */ }
215 else
216 {
217 Log(("pdmRCDevHlp_PCIPhysWrite: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#zx\n",
218 pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
219 return VERR_PDM_NOT_PCI_BUS_MASTER;
220 }
221#endif
222
223#ifdef VBOX_WITH_IOMMU_AMD
224 /** @todo IOMMU: Optimize/re-organize things here later. */
225 PGVM pGVM = pDevIns->Internal.s.pGVM;
226 PPDMIOMMUR0 pIommu = &pGVM->pdmr0.s.aIommus[0];
227 PPDMDEVINS pDevInsIommu = pIommu->CTX_SUFF(pDevIns);
228 if ( pDevInsIommu
229 && pDevInsIommu != pDevIns)
230 {
231 size_t const idxBus = pPciDev->Int.s.idxPdmBus;
232 Assert(idxBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
233 PPDMPCIBUSR0 pBus = &pGVM->pdmr0.s.aPciBuses[idxBus];
234 uint16_t const uDeviceId = PCIBDF_MAKE(pBus->iBus, pPciDev->uDevFn);
235 int rc = VINF_SUCCESS;
236 while (cbWrite > 0)
237 {
238 RTGCPHYS GCPhysOut;
239 size_t cbContig;
240 rc = pIommu->pfnMemAccess(pDevInsIommu, uDeviceId, GCPhys, cbWrite, PDMIOMMU_MEM_F_WRITE, &GCPhysOut, &cbContig);
241 if (RT_SUCCESS(rc))
242 {
243 /** @todo Handle strict return codes from PGMPhysWrite. */
244 rc = pDevIns->pHlpR0->pfnPhysWrite(pDevIns, GCPhysOut, pvBuf, cbWrite, fFlags);
245 if (RT_SUCCESS(rc))
246 {
247 cbWrite -= cbContig;
248 pvBuf = (const void *)((uintptr_t)pvBuf + cbContig);
249 GCPhys += cbContig;
250 }
251 else
252 break;
253 }
254 else
255 {
256 Log(("pdmR0DevHlp_PCIPhysWrite: IOMMU translation failed. uDeviceId=%#x GCPhys=%#RGp cb=%u rc=%Rrc\n", uDeviceId,
257 GCPhys, cbWrite, rc));
258 break;
259 }
260 }
261 return rc;
262 }
263#endif
264
265 return pDevIns->pHlpR0->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, fFlags);
266}
267
268
269/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
270static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
271{
272 PDMDEV_ASSERT_DEVINS(pDevIns);
273 if (!pPciDev) /* NULL is an alias for the default PCI device. */
274 pPciDev = pDevIns->apPciDevs[0];
275 AssertReturnVoid(pPciDev);
276 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: pPciDev=%p:{%#x} iIrq=%d iLevel=%d\n",
277 pDevIns, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iIrq, iLevel));
278 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
279
280 PGVM pGVM = pDevIns->Internal.s.pGVM;
281 size_t const idxBus = pPciDev->Int.s.idxPdmBus;
282 AssertReturnVoid(idxBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
283 PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[idxBus];
284
285 pdmLock(pGVM);
286
287 uint32_t uTagSrc;
288 if (iLevel & PDM_IRQ_LEVEL_HIGH)
289 {
290 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
291 if (iLevel == PDM_IRQ_LEVEL_HIGH)
292 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
293 else
294 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
295 }
296 else
297 uTagSrc = pDevIns->Internal.s.pIntR3R0->uLastIrqTag;
298
299 if (pPciBusR0->pDevInsR0)
300 {
301 pPciBusR0->pfnSetIrqR0(pPciBusR0->pDevInsR0, pPciDev, iIrq, iLevel, uTagSrc);
302
303 pdmUnlock(pGVM);
304
305 if (iLevel == PDM_IRQ_LEVEL_LOW)
306 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
307 }
308 else
309 {
310 pdmUnlock(pGVM);
311
312 /* queue for ring-3 execution. */
313 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
314 AssertReturnVoid(pTask);
315
316 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
317 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
318 pTask->u.PciSetIRQ.iIrq = iIrq;
319 pTask->u.PciSetIRQ.iLevel = iLevel;
320 pTask->u.PciSetIRQ.uTagSrc = uTagSrc;
321 pTask->u.PciSetIRQ.pPciDevR3 = MMHyperR0ToR3(pGVM, pPciDev);
322
323 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
324 }
325
326 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
327}
328
329
330/** @interface_method_impl{PDMDEVHLPR0,pfnISASetIrq} */
331static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
332{
333 PDMDEV_ASSERT_DEVINS(pDevIns);
334 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
335 PGVM pGVM = pDevIns->Internal.s.pGVM;
336
337 pdmLock(pGVM);
338 uint32_t uTagSrc;
339 if (iLevel & PDM_IRQ_LEVEL_HIGH)
340 {
341 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
342 if (iLevel == PDM_IRQ_LEVEL_HIGH)
343 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
344 else
345 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
346 }
347 else
348 uTagSrc = pDevIns->Internal.s.pIntR3R0->uLastIrqTag;
349
350 bool fRc = pdmR0IsaSetIrq(pGVM, iIrq, iLevel, uTagSrc);
351
352 if (iLevel == PDM_IRQ_LEVEL_LOW && fRc)
353 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
354 pdmUnlock(pGVM);
355 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
356}
357
358
359/** @interface_method_impl{PDMDEVHLPR0,pfnPhysRead} */
360static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags)
361{
362 RT_NOREF(fFlags);
363
364 PDMDEV_ASSERT_DEVINS(pDevIns);
365 LogFlow(("pdmR0DevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
366 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
367
368 VBOXSTRICTRC rcStrict = PGMPhysRead(pDevIns->Internal.s.pGVM, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
369 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
370
371 Log(("pdmR0DevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
372 return VBOXSTRICTRC_VAL(rcStrict);
373}
374
375
376/** @interface_method_impl{PDMDEVHLPR0,pfnPhysWrite} */
377static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags)
378{
379 RT_NOREF(fFlags);
380
381 PDMDEV_ASSERT_DEVINS(pDevIns);
382 LogFlow(("pdmR0DevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
383 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
384
385 VBOXSTRICTRC rcStrict = PGMPhysWrite(pDevIns->Internal.s.pGVM, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
386 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
387
388 Log(("pdmR0DevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
389 return VBOXSTRICTRC_VAL(rcStrict);
390}
391
392
393/** @interface_method_impl{PDMDEVHLPR0,pfnA20IsEnabled} */
394static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
395{
396 PDMDEV_ASSERT_DEVINS(pDevIns);
397 LogFlow(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
398
399 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pGVM));
400
401 Log(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
402 return fEnabled;
403}
404
405
406/** @interface_method_impl{PDMDEVHLPR0,pfnVMState} */
407static DECLCALLBACK(VMSTATE) pdmR0DevHlp_VMState(PPDMDEVINS pDevIns)
408{
409 PDMDEV_ASSERT_DEVINS(pDevIns);
410
411 VMSTATE enmVMState = pDevIns->Internal.s.pGVM->enmVMState;
412
413 LogFlow(("pdmR0DevHlp_VMState: caller=%p/%d: returns %d\n", pDevIns, pDevIns->iInstance, enmVMState));
414 return enmVMState;
415}
416
417
418/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetError} */
419static DECLCALLBACK(int) pdmR0DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
420{
421 PDMDEV_ASSERT_DEVINS(pDevIns);
422 va_list args;
423 va_start(args, pszFormat);
424 int rc2 = VMSetErrorV(pDevIns->Internal.s.pGVM, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
425 va_end(args);
426 return rc;
427}
428
429
430/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetErrorV} */
431static DECLCALLBACK(int) pdmR0DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
432{
433 PDMDEV_ASSERT_DEVINS(pDevIns);
434 int rc2 = VMSetErrorV(pDevIns->Internal.s.pGVM, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
435 return rc;
436}
437
438
439/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeError} */
440static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
441{
442 PDMDEV_ASSERT_DEVINS(pDevIns);
443 va_list va;
444 va_start(va, pszFormat);
445 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pGVM, fFlags, pszErrorId, pszFormat, va);
446 va_end(va);
447 return rc;
448}
449
450
451/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeErrorV} */
452static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
453{
454 PDMDEV_ASSERT_DEVINS(pDevIns);
455 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pGVM, fFlags, pszErrorId, pszFormat, va);
456 return rc;
457}
458
459
460
461/** @interface_method_impl{PDMDEVHLPR0,pfnGetVM} */
462static DECLCALLBACK(PVMCC) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns)
463{
464 PDMDEV_ASSERT_DEVINS(pDevIns);
465 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
466 return pDevIns->Internal.s.pGVM;
467}
468
469
470/** @interface_method_impl{PDMDEVHLPR0,pfnGetVMCPU} */
471static DECLCALLBACK(PVMCPUCC) pdmR0DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
472{
473 PDMDEV_ASSERT_DEVINS(pDevIns);
474 LogFlow(("pdmR0DevHlp_GetVMCPU: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
475 return VMMGetCpu(pDevIns->Internal.s.pGVM);
476}
477
478
479/** @interface_method_impl{PDMDEVHLPRC,pfnGetCurrentCpuId} */
480static DECLCALLBACK(VMCPUID) pdmR0DevHlp_GetCurrentCpuId(PPDMDEVINS pDevIns)
481{
482 PDMDEV_ASSERT_DEVINS(pDevIns);
483 VMCPUID idCpu = VMMGetCpuId(pDevIns->Internal.s.pGVM);
484 LogFlow(("pdmR0DevHlp_GetCurrentCpuId: caller='%p'/%d for CPU %u\n", pDevIns, pDevIns->iInstance, idCpu));
485 return idCpu;
486}
487
488
489/** @interface_method_impl{PDMDEVHLPR0,pfnTimerToPtr} */
490static DECLCALLBACK(PTMTIMERR0) pdmR0DevHlp_TimerToPtr(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
491{
492 PDMDEV_ASSERT_DEVINS(pDevIns);
493 RT_NOREF(pDevIns);
494 return (PTMTIMERR0)MMHyperR3ToCC(pDevIns->Internal.s.pGVM, hTimer);
495}
496
497
498/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromMicro} */
499static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
500{
501 return TMTimerFromMicro(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cMicroSecs);
502}
503
504
505/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromMilli} */
506static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
507{
508 return TMTimerFromMilli(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cMilliSecs);
509}
510
511
512/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromNano} */
513static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
514{
515 return TMTimerFromNano(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cNanoSecs);
516}
517
518/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGet} */
519static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
520{
521 return TMTimerGet(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
522}
523
524
525/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGetFreq} */
526static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
527{
528 return TMTimerGetFreq(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
529}
530
531
532/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGetNano} */
533static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
534{
535 return TMTimerGetNano(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
536}
537
538
539/** @interface_method_impl{PDMDEVHLPR0,pfnTimerIsActive} */
540static DECLCALLBACK(bool) pdmR0DevHlp_TimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
541{
542 return TMTimerIsActive(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
543}
544
545
546/** @interface_method_impl{PDMDEVHLPR0,pfnTimerIsLockOwner} */
547static DECLCALLBACK(bool) pdmR0DevHlp_TimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
548{
549 return TMTimerIsLockOwner(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
550}
551
552
553/** @interface_method_impl{PDMDEVHLPR0,pfnTimerLockClock} */
554static DECLCALLBACK(VBOXSTRICTRC) pdmR0DevHlp_TimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
555{
556 return TMTimerLock(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), rcBusy);
557}
558
559
560/** @interface_method_impl{PDMDEVHLPR0,pfnTimerLockClock2} */
561static DECLCALLBACK(VBOXSTRICTRC) pdmR0DevHlp_TimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer,
562 PPDMCRITSECT pCritSect, int rcBusy)
563{
564 VBOXSTRICTRC rc = TMTimerLock(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), rcBusy);
565 if (rc == VINF_SUCCESS)
566 {
567 rc = PDMCritSectEnter(pCritSect, rcBusy);
568 if (rc == VINF_SUCCESS)
569 return rc;
570 AssertRC(VBOXSTRICTRC_VAL(rc));
571 TMTimerUnlock(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
572 }
573 else
574 AssertRC(VBOXSTRICTRC_VAL(rc));
575 return rc;
576}
577
578
579/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSet} */
580static DECLCALLBACK(int) pdmR0DevHlp_TimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
581{
582 return TMTimerSet(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), uExpire);
583}
584
585
586/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetFrequencyHint} */
587static DECLCALLBACK(int) pdmR0DevHlp_TimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
588{
589 return TMTimerSetFrequencyHint(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), uHz);
590}
591
592
593/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetMicro} */
594static DECLCALLBACK(int) pdmR0DevHlp_TimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
595{
596 return TMTimerSetMicro(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cMicrosToNext);
597}
598
599
600/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetMillies} */
601static DECLCALLBACK(int) pdmR0DevHlp_TimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
602{
603 return TMTimerSetMillies(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cMilliesToNext);
604}
605
606
607/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetNano} */
608static DECLCALLBACK(int) pdmR0DevHlp_TimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
609{
610 return TMTimerSetNano(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cNanosToNext);
611}
612
613
614/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetRelative} */
615static DECLCALLBACK(int) pdmR0DevHlp_TimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
616{
617 return TMTimerSetRelative(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cTicksToNext, pu64Now);
618}
619
620
621/** @interface_method_impl{PDMDEVHLPR0,pfnTimerStop} */
622static DECLCALLBACK(int) pdmR0DevHlp_TimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
623{
624 return TMTimerStop(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
625}
626
627
628/** @interface_method_impl{PDMDEVHLPR0,pfnTimerUnlockClock} */
629static DECLCALLBACK(void) pdmR0DevHlp_TimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
630{
631 TMTimerUnlock(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
632}
633
634
635/** @interface_method_impl{PDMDEVHLPR0,pfnTimerUnlockClock2} */
636static DECLCALLBACK(void) pdmR0DevHlp_TimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
637{
638 TMTimerUnlock(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
639 int rc = PDMCritSectLeave(pCritSect);
640 AssertRC(rc);
641}
642
643
644/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGet} */
645static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
646{
647 PDMDEV_ASSERT_DEVINS(pDevIns);
648 LogFlow(("pdmR0DevHlp_TMTimeVirtGet: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
649 return TMVirtualGet(pDevIns->Internal.s.pGVM);
650}
651
652
653/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetFreq} */
654static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
655{
656 PDMDEV_ASSERT_DEVINS(pDevIns);
657 LogFlow(("pdmR0DevHlp_TMTimeVirtGetFreq: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
658 return TMVirtualGetFreq(pDevIns->Internal.s.pGVM);
659}
660
661
662/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetNano} */
663static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
664{
665 PDMDEV_ASSERT_DEVINS(pDevIns);
666 LogFlow(("pdmR0DevHlp_TMTimeVirtGetNano: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
667 return TMVirtualToNano(pDevIns->Internal.s.pGVM, TMVirtualGet(pDevIns->Internal.s.pGVM));
668}
669
670
671/** @interface_method_impl{PDMDEVHLPR0,pfnQueueToPtr} */
672static DECLCALLBACK(PPDMQUEUE) pdmR0DevHlp_QueueToPtr(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
673{
674 PDMDEV_ASSERT_DEVINS(pDevIns);
675 RT_NOREF(pDevIns);
676 return (PPDMQUEUE)MMHyperR3ToCC(pDevIns->Internal.s.pGVM, hQueue);
677}
678
679
680/** @interface_method_impl{PDMDEVHLPR0,pfnQueueAlloc} */
681static DECLCALLBACK(PPDMQUEUEITEMCORE) pdmR0DevHlp_QueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
682{
683 return PDMQueueAlloc(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue));
684}
685
686
687/** @interface_method_impl{PDMDEVHLPR0,pfnQueueInsert} */
688static DECLCALLBACK(void) pdmR0DevHlp_QueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
689{
690 return PDMQueueInsert(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue), pItem);
691}
692
693
694/** @interface_method_impl{PDMDEVHLPR0,pfnQueueInsertEx} */
695static DECLCALLBACK(void) pdmR0DevHlp_QueueInsertEx(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem,
696 uint64_t cNanoMaxDelay)
697{
698 return PDMQueueInsertEx(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue), pItem, cNanoMaxDelay);
699}
700
701
702/** @interface_method_impl{PDMDEVHLPR0,pfnQueueFlushIfNecessary} */
703static DECLCALLBACK(bool) pdmR0DevHlp_QueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
704{
705 return PDMQueueFlushIfNecessary(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue));
706}
707
708
709/** @interface_method_impl{PDMDEVHLPR0,pfnTaskTrigger} */
710static DECLCALLBACK(int) pdmR0DevHlp_TaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
711{
712 PDMDEV_ASSERT_DEVINS(pDevIns);
713 LogFlow(("pdmR0DevHlp_TaskTrigger: caller='%s'/%d: hTask=%RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, hTask));
714
715 int rc = PDMTaskTrigger(pDevIns->Internal.s.pGVM, PDMTASKTYPE_DEV, pDevIns->pDevInsForR3, hTask);
716
717 LogFlow(("pdmR0DevHlp_TaskTrigger: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
718 return rc;
719}
720
721
722/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventSignal} */
723static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
724{
725 PDMDEV_ASSERT_DEVINS(pDevIns);
726 LogFlow(("pdmR0DevHlp_SUPSemEventSignal: caller='%s'/%d: hEvent=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEvent));
727
728 int rc = SUPSemEventSignal(pDevIns->Internal.s.pGVM->pSession, hEvent);
729
730 LogFlow(("pdmR0DevHlp_SUPSemEventSignal: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
731 return rc;
732}
733
734
735/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNoResume} */
736static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
737{
738 PDMDEV_ASSERT_DEVINS(pDevIns);
739 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNoResume: caller='%s'/%d: hEvent=%p cNsTimeout=%RU32\n",
740 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, cMillies));
741
742 int rc = SUPSemEventWaitNoResume(pDevIns->Internal.s.pGVM->pSession, hEvent, cMillies);
743
744 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNoResume: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
745 return rc;
746}
747
748
749/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNsAbsIntr} */
750static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
751{
752 PDMDEV_ASSERT_DEVINS(pDevIns);
753 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsAbsIntr: caller='%s'/%d: hEvent=%p uNsTimeout=%RU64\n",
754 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, uNsTimeout));
755
756 int rc = SUPSemEventWaitNsAbsIntr(pDevIns->Internal.s.pGVM->pSession, hEvent, uNsTimeout);
757
758 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsAbsIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
759 return rc;
760}
761
762
763/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNsRelIntr} */
764static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
765{
766 PDMDEV_ASSERT_DEVINS(pDevIns);
767 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsRelIntr: caller='%s'/%d: hEvent=%p cNsTimeout=%RU64\n",
768 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, cNsTimeout));
769
770 int rc = SUPSemEventWaitNsRelIntr(pDevIns->Internal.s.pGVM->pSession, hEvent, cNsTimeout);
771
772 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsRelIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
773 return rc;
774}
775
776
777/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventGetResolution} */
778static DECLCALLBACK(uint32_t) pdmR0DevHlp_SUPSemEventGetResolution(PPDMDEVINS pDevIns)
779{
780 PDMDEV_ASSERT_DEVINS(pDevIns);
781 LogFlow(("pdmR0DevHlp_SUPSemEventGetResolution: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
782
783 uint32_t cNsResolution = SUPSemEventGetResolution(pDevIns->Internal.s.pGVM->pSession);
784
785 LogFlow(("pdmR0DevHlp_SUPSemEventGetResolution: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, cNsResolution));
786 return cNsResolution;
787}
788
789
790/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiSignal} */
791static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
792{
793 PDMDEV_ASSERT_DEVINS(pDevIns);
794 LogFlow(("pdmR0DevHlp_SUPSemEventMultiSignal: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
795
796 int rc = SUPSemEventMultiSignal(pDevIns->Internal.s.pGVM->pSession, hEventMulti);
797
798 LogFlow(("pdmR0DevHlp_SUPSemEventMultiSignal: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
799 return rc;
800}
801
802
803/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiReset} */
804static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
805{
806 PDMDEV_ASSERT_DEVINS(pDevIns);
807 LogFlow(("pdmR0DevHlp_SUPSemEventMultiReset: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
808
809 int rc = SUPSemEventMultiReset(pDevIns->Internal.s.pGVM->pSession, hEventMulti);
810
811 LogFlow(("pdmR0DevHlp_SUPSemEventMultiReset: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
812 return rc;
813}
814
815
816/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNoResume} */
817static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
818 uint32_t cMillies)
819{
820 PDMDEV_ASSERT_DEVINS(pDevIns);
821 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNoResume: caller='%s'/%d: hEventMulti=%p cMillies=%RU32\n",
822 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, cMillies));
823
824 int rc = SUPSemEventMultiWaitNoResume(pDevIns->Internal.s.pGVM->pSession, hEventMulti, cMillies);
825
826 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNoResume: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
827 return rc;
828}
829
830
831/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNsAbsIntr} */
832static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
833 uint64_t uNsTimeout)
834{
835 PDMDEV_ASSERT_DEVINS(pDevIns);
836 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr: caller='%s'/%d: hEventMulti=%p uNsTimeout=%RU64\n",
837 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, uNsTimeout));
838
839 int rc = SUPSemEventMultiWaitNsAbsIntr(pDevIns->Internal.s.pGVM->pSession, hEventMulti, uNsTimeout);
840
841 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
842 return rc;
843}
844
845
846/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNsRelIntr} */
847static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
848 uint64_t cNsTimeout)
849{
850 PDMDEV_ASSERT_DEVINS(pDevIns);
851 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr: caller='%s'/%d: hEventMulti=%p cNsTimeout=%RU64\n",
852 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, cNsTimeout));
853
854 int rc = SUPSemEventMultiWaitNsRelIntr(pDevIns->Internal.s.pGVM->pSession, hEventMulti, cNsTimeout);
855
856 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
857 return rc;
858}
859
860
861/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiGetResolution} */
862static DECLCALLBACK(uint32_t) pdmR0DevHlp_SUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
863{
864 PDMDEV_ASSERT_DEVINS(pDevIns);
865 LogFlow(("pdmR0DevHlp_SUPSemEventMultiGetResolution: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
866
867 uint32_t cNsResolution = SUPSemEventMultiGetResolution(pDevIns->Internal.s.pGVM->pSession);
868
869 LogFlow(("pdmR0DevHlp_SUPSemEventMultiGetResolution: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, cNsResolution));
870 return cNsResolution;
871}
872
873
874/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectGetNop} */
875static DECLCALLBACK(PPDMCRITSECT) pdmR0DevHlp_CritSectGetNop(PPDMDEVINS pDevIns)
876{
877 PDMDEV_ASSERT_DEVINS(pDevIns);
878 PGVM pGVM = pDevIns->Internal.s.pGVM;
879
880 PPDMCRITSECT pCritSect = &pGVM->pdm.s.NopCritSect;
881 LogFlow(("pdmR0DevHlp_CritSectGetNop: caller='%s'/%d: return %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
882 return pCritSect;
883}
884
885
886/** @interface_method_impl{PDMDEVHLPR0,pfnSetDeviceCritSect} */
887static DECLCALLBACK(int) pdmR0DevHlp_SetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
888{
889 /*
890 * Validate input.
891 *
892 * Note! We only allow the automatically created default critical section
893 * to be replaced by this API.
894 */
895 PDMDEV_ASSERT_DEVINS(pDevIns);
896 AssertPtrReturn(pCritSect, VERR_INVALID_POINTER);
897 LogFlow(("pdmR0DevHlp_SetDeviceCritSect: caller='%s'/%d: pCritSect=%p (%s)\n",
898 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect, pCritSect->s.pszName));
899 AssertReturn(PDMCritSectIsInitialized(pCritSect), VERR_INVALID_PARAMETER);
900 PGVM pGVM = pDevIns->Internal.s.pGVM;
901 AssertReturn(pCritSect->s.pVMR0 == pGVM, VERR_INVALID_PARAMETER);
902
903 VM_ASSERT_EMT(pGVM);
904 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
905
906 /*
907 * Check that ring-3 has already done this, then effect the change.
908 */
909 AssertReturn(pDevIns->pDevInsForR3R0->Internal.s.fIntFlags & PDMDEVINSINT_FLAGS_CHANGED_CRITSECT, VERR_WRONG_ORDER);
910 pDevIns->pCritSectRoR0 = pCritSect;
911
912 LogFlow(("pdmR0DevHlp_SetDeviceCritSect: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
913 return VINF_SUCCESS;
914}
915
916
917/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectEnter} */
918static DECLCALLBACK(int) pdmR0DevHlp_CritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
919{
920 PDMDEV_ASSERT_DEVINS(pDevIns);
921 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
922 return PDMCritSectEnter(pCritSect, rcBusy);
923}
924
925
926/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectEnterDebug} */
927static DECLCALLBACK(int) pdmR0DevHlp_CritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
928{
929 PDMDEV_ASSERT_DEVINS(pDevIns);
930 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
931 return PDMCritSectEnterDebug(pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
932}
933
934
935/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectTryEnter} */
936static DECLCALLBACK(int) pdmR0DevHlp_CritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
937{
938 PDMDEV_ASSERT_DEVINS(pDevIns);
939 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
940 return PDMCritSectTryEnter(pCritSect);
941}
942
943
944/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectTryEnterDebug} */
945static DECLCALLBACK(int) pdmR0DevHlp_CritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
946{
947 PDMDEV_ASSERT_DEVINS(pDevIns);
948 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
949 return PDMCritSectTryEnterDebug(pCritSect, uId, RT_SRC_POS_ARGS);
950}
951
952
953/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectLeave} */
954static DECLCALLBACK(int) pdmR0DevHlp_CritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
955{
956 PDMDEV_ASSERT_DEVINS(pDevIns);
957 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
958 return PDMCritSectLeave(pCritSect);
959}
960
961
962/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectIsOwner} */
963static DECLCALLBACK(bool) pdmR0DevHlp_CritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
964{
965 PDMDEV_ASSERT_DEVINS(pDevIns);
966 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
967 return PDMCritSectIsOwner(pCritSect);
968}
969
970
971/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectIsInitialized} */
972static DECLCALLBACK(bool) pdmR0DevHlp_CritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
973{
974 PDMDEV_ASSERT_DEVINS(pDevIns);
975 RT_NOREF(pDevIns);
976 return PDMCritSectIsInitialized(pCritSect);
977}
978
979
980/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectHasWaiters} */
981static DECLCALLBACK(bool) pdmR0DevHlp_CritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
982{
983 PDMDEV_ASSERT_DEVINS(pDevIns);
984 RT_NOREF(pDevIns);
985 return PDMCritSectHasWaiters(pCritSect);
986}
987
988
989/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectGetRecursion} */
990static DECLCALLBACK(uint32_t) pdmR0DevHlp_CritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
991{
992 PDMDEV_ASSERT_DEVINS(pDevIns);
993 RT_NOREF(pDevIns);
994 return PDMCritSectGetRecursion(pCritSect);
995}
996
997
998/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectScheduleExitEvent} */
999static DECLCALLBACK(int) pdmR0DevHlp_CritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect,
1000 SUPSEMEVENT hEventToSignal)
1001{
1002 PDMDEV_ASSERT_DEVINS(pDevIns);
1003 RT_NOREF(pDevIns);
1004 return PDMHCCritSectScheduleExitEvent(pCritSect, hEventToSignal);
1005}
1006
1007
1008/** @interface_method_impl{PDMDEVHLPR0,pfnDBGFTraceBuf} */
1009static DECLCALLBACK(RTTRACEBUF) pdmR0DevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
1010{
1011 PDMDEV_ASSERT_DEVINS(pDevIns);
1012 RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pGVM->hTraceBufR0;
1013 LogFlow(("pdmR0DevHlp_DBGFTraceBuf: caller='%p'/%d: returns %p\n", pDevIns, pDevIns->iInstance, hTraceBuf));
1014 return hTraceBuf;
1015}
1016
1017
1018/** @interface_method_impl{PDMDEVHLPR0,pfnPCIBusSetUpContext} */
1019static DECLCALLBACK(int) pdmR0DevHlp_PCIBusSetUpContext(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp)
1020{
1021 PDMDEV_ASSERT_DEVINS(pDevIns);
1022 LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: pPciBusReg=%p{.u32Version=%#x, .iBus=%#u, .pfnSetIrq=%p, u32EnvVersion=%#x} ppPciHlp=%p\n",
1023 pDevIns, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->iBus, pPciBusReg->pfnSetIrq,
1024 pPciBusReg->u32EndVersion, ppPciHlp));
1025 PGVM pGVM = pDevIns->Internal.s.pGVM;
1026
1027 /*
1028 * Validate input.
1029 */
1030 AssertPtrReturn(pPciBusReg, VERR_INVALID_POINTER);
1031 AssertLogRelMsgReturn(pPciBusReg->u32Version == PDM_PCIBUSREGCC_VERSION,
1032 ("%#x vs %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
1033 AssertPtrReturn(pPciBusReg->pfnSetIrq, VERR_INVALID_POINTER);
1034 AssertLogRelMsgReturn(pPciBusReg->u32EndVersion == PDM_PCIBUSREGCC_VERSION,
1035 ("%#x vs %#x\n", pPciBusReg->u32EndVersion, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
1036
1037 AssertPtrReturn(ppPciHlp, VERR_INVALID_POINTER);
1038
1039 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1040 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1041
1042 /* Check the shared bus data (registered earlier from ring-3): */
1043 uint32_t iBus = pPciBusReg->iBus;
1044 ASMCompilerBarrier();
1045 AssertLogRelMsgReturn(iBus < RT_ELEMENTS(pGVM->pdm.s.aPciBuses), ("iBus=%#x\n", iBus), VERR_OUT_OF_RANGE);
1046 PPDMPCIBUS pPciBusShared = &pGVM->pdm.s.aPciBuses[iBus];
1047 AssertLogRelMsgReturn(pPciBusShared->iBus == iBus, ("%u vs %u\n", pPciBusShared->iBus, iBus), VERR_INVALID_PARAMETER);
1048 AssertLogRelMsgReturn(pPciBusShared->pDevInsR3 == pDevIns->pDevInsForR3,
1049 ("%p vs %p (iBus=%u)\n", pPciBusShared->pDevInsR3, pDevIns->pDevInsForR3, iBus), VERR_NOT_OWNER);
1050
1051 /* Check that the bus isn't already registered in ring-0: */
1052 AssertCompile(RT_ELEMENTS(pGVM->pdm.s.aPciBuses) == RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
1053 PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[iBus];
1054 AssertLogRelMsgReturn(pPciBusR0->pDevInsR0 == NULL,
1055 ("%p (caller pDevIns=%p, iBus=%u)\n", pPciBusR0->pDevInsR0, pDevIns, iBus),
1056 VERR_ALREADY_EXISTS);
1057
1058 /*
1059 * Do the registering.
1060 */
1061 pPciBusR0->iBus = iBus;
1062 pPciBusR0->uPadding0 = 0xbeefbeef;
1063 pPciBusR0->pfnSetIrqR0 = pPciBusReg->pfnSetIrq;
1064 pPciBusR0->pDevInsR0 = pDevIns;
1065
1066 *ppPciHlp = &g_pdmR0PciHlp;
1067
1068 LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: returns VINF_SUCCESS\n", pDevIns, pDevIns->iInstance));
1069 return VINF_SUCCESS;
1070}
1071
1072
1073/** @interface_method_impl{PDMDEVHLPR0,pfnIommuSetUpContext} */
1074static DECLCALLBACK(int) pdmR0DevHlp_IommuSetUpContext(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp)
1075{
1076 PDMDEV_ASSERT_DEVINS(pDevIns);
1077 LogFlow(("pdmR0DevHlp_IommuSetUpContext: caller='%p'/%d: pIommuReg=%p{.u32Version=%#x, u32TheEnd=%#x} ppIommuHlp=%p\n",
1078 pDevIns, pDevIns->iInstance, pIommuReg, pIommuReg->u32Version, pIommuReg->u32TheEnd, ppIommuHlp));
1079 PGVM pGVM = pDevIns->Internal.s.pGVM;
1080
1081 /*
1082 * Validate input.
1083 */
1084 AssertPtrReturn(pIommuReg, VERR_INVALID_POINTER);
1085 AssertLogRelMsgReturn(pIommuReg->u32Version == PDM_IOMMUREGCC_VERSION,
1086 ("%#x vs %#x\n", pIommuReg->u32Version, PDM_IOMMUREGCC_VERSION), VERR_VERSION_MISMATCH);
1087 AssertPtrReturn(pIommuReg->pfnMemAccess, VERR_INVALID_POINTER);
1088 AssertPtrReturn(pIommuReg->pfnMemBulkAccess, VERR_INVALID_POINTER);
1089 AssertPtrReturn(pIommuReg->pfnMsiRemap, VERR_INVALID_POINTER);
1090 AssertLogRelMsgReturn(pIommuReg->u32TheEnd == PDM_IOMMUREGCC_VERSION,
1091 ("%#x vs %#x\n", pIommuReg->u32TheEnd, PDM_IOMMUREGCC_VERSION), VERR_VERSION_MISMATCH);
1092
1093 AssertPtrReturn(ppIommuHlp, VERR_INVALID_POINTER);
1094
1095 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1096 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1097
1098 /* Check the IOMMU shared data (registered earlier from ring-3). */
1099 uint32_t const idxIommu = pIommuReg->idxIommu;
1100 ASMCompilerBarrier();
1101 AssertLogRelMsgReturn(idxIommu < RT_ELEMENTS(pGVM->pdm.s.aIommus), ("idxIommu=%#x\n", idxIommu), VERR_OUT_OF_RANGE);
1102 PPDMIOMMU pIommuShared = &pGVM->pdm.s.aIommus[idxIommu];
1103 AssertLogRelMsgReturn(pIommuShared->idxIommu == idxIommu, ("%u vs %u\n", pIommuShared->idxIommu, idxIommu), VERR_INVALID_PARAMETER);
1104 AssertLogRelMsgReturn(pIommuShared->pDevInsR3 == pDevIns->pDevInsForR3,
1105 ("%p vs %p (idxIommu=%u)\n", pIommuShared->pDevInsR3, pDevIns->pDevInsForR3, idxIommu), VERR_NOT_OWNER);
1106
1107 /* Check that the IOMMU isn't already registered in ring-0. */
1108 AssertCompile(RT_ELEMENTS(pGVM->pdm.s.aIommus) == RT_ELEMENTS(pGVM->pdmr0.s.aIommus));
1109 PPDMIOMMUR0 pIommuR0 = &pGVM->pdmr0.s.aIommus[idxIommu];
1110 AssertLogRelMsgReturn(pIommuR0->pDevInsR0 == NULL,
1111 ("%p (caller pDevIns=%p, idxIommu=%u)\n", pIommuR0->pDevInsR0, pDevIns, idxIommu),
1112 VERR_ALREADY_EXISTS);
1113
1114 /*
1115 * Register.
1116 */
1117 pIommuR0->idxIommu = idxIommu;
1118 pIommuR0->uPadding0 = 0xdeaddead;
1119 pIommuR0->pDevInsR0 = pDevIns;
1120 pIommuR0->pfnMemAccess = pIommuReg->pfnMemAccess;
1121 pIommuR0->pfnMemBulkAccess = pIommuReg->pfnMemBulkAccess;
1122 pIommuR0->pfnMsiRemap = pIommuReg->pfnMsiRemap;
1123
1124 *ppIommuHlp = &g_pdmR0IommuHlp;
1125
1126 LogFlow(("pdmR0DevHlp_IommuSetUpContext: caller='%p'/%d: returns VINF_SUCCESS\n", pDevIns, pDevIns->iInstance));
1127 return VINF_SUCCESS;
1128}
1129
1130
1131/** @interface_method_impl{PDMDEVHLPR0,pfnPICSetUpContext} */
1132static DECLCALLBACK(int) pdmR0DevHlp_PICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
1133{
1134 PDMDEV_ASSERT_DEVINS(pDevIns);
1135 LogFlow(("pdmR0DevHlp_PICSetUpContext: caller='%s'/%d: pPicReg=%p:{.u32Version=%#x, .pfnSetIrq=%p, .pfnGetInterrupt=%p, .u32TheEnd=%#x } ppPicHlp=%p\n",
1136 pDevIns->pReg->szName, pDevIns->iInstance, pPicReg, pPicReg->u32Version, pPicReg->pfnSetIrq, pPicReg->pfnGetInterrupt, pPicReg->u32TheEnd, ppPicHlp));
1137 PGVM pGVM = pDevIns->Internal.s.pGVM;
1138
1139 /*
1140 * Validate input.
1141 */
1142 AssertMsgReturn(pPicReg->u32Version == PDM_PICREG_VERSION,
1143 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pPicReg->u32Version, PDM_PICREG_VERSION),
1144 VERR_VERSION_MISMATCH);
1145 AssertPtrReturn(pPicReg->pfnSetIrq, VERR_INVALID_POINTER);
1146 AssertPtrReturn(pPicReg->pfnGetInterrupt, VERR_INVALID_POINTER);
1147 AssertMsgReturn(pPicReg->u32TheEnd == PDM_PICREG_VERSION,
1148 ("%s/%d: u32TheEnd=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pPicReg->u32TheEnd, PDM_PICREG_VERSION),
1149 VERR_VERSION_MISMATCH);
1150 AssertPtrReturn(ppPicHlp, VERR_INVALID_POINTER);
1151
1152 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1153 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1154
1155 /* Check that it's the same device as made the ring-3 registrations: */
1156 AssertLogRelMsgReturn(pGVM->pdm.s.Pic.pDevInsR3 == pDevIns->pDevInsForR3,
1157 ("%p vs %p\n", pGVM->pdm.s.Pic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1158
1159 /* Check that it isn't already registered in ring-0: */
1160 AssertLogRelMsgReturn(pGVM->pdm.s.Pic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Pic.pDevInsR0, pDevIns),
1161 VERR_ALREADY_EXISTS);
1162
1163 /*
1164 * Take down the callbacks and instance.
1165 */
1166 pGVM->pdm.s.Pic.pDevInsR0 = pDevIns;
1167 pGVM->pdm.s.Pic.pfnSetIrqR0 = pPicReg->pfnSetIrq;
1168 pGVM->pdm.s.Pic.pfnGetInterruptR0 = pPicReg->pfnGetInterrupt;
1169 Log(("PDM: Registered PIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1170
1171 /* set the helper pointer and return. */
1172 *ppPicHlp = &g_pdmR0PicHlp;
1173 LogFlow(("pdmR0DevHlp_PICSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1174 return VINF_SUCCESS;
1175}
1176
1177
1178/** @interface_method_impl{PDMDEVHLPR0,pfnApicSetUpContext} */
1179static DECLCALLBACK(int) pdmR0DevHlp_ApicSetUpContext(PPDMDEVINS pDevIns)
1180{
1181 PDMDEV_ASSERT_DEVINS(pDevIns);
1182 LogFlow(("pdmR0DevHlp_ApicSetUpContext: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
1183 PGVM pGVM = pDevIns->Internal.s.pGVM;
1184
1185 /*
1186 * Validate input.
1187 */
1188 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1189 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1190
1191 /* Check that it's the same device as made the ring-3 registrations: */
1192 AssertLogRelMsgReturn(pGVM->pdm.s.Apic.pDevInsR3 == pDevIns->pDevInsForR3,
1193 ("%p vs %p\n", pGVM->pdm.s.Apic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1194
1195 /* Check that it isn't already registered in ring-0: */
1196 AssertLogRelMsgReturn(pGVM->pdm.s.Apic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Apic.pDevInsR0, pDevIns),
1197 VERR_ALREADY_EXISTS);
1198
1199 /*
1200 * Take down the instance.
1201 */
1202 pGVM->pdm.s.Apic.pDevInsR0 = pDevIns;
1203 Log(("PDM: Registered APIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1204
1205 /* set the helper pointer and return. */
1206 LogFlow(("pdmR0DevHlp_ApicSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1207 return VINF_SUCCESS;
1208}
1209
1210
1211/** @interface_method_impl{PDMDEVHLPR0,pfnIoApicSetUpContext} */
1212static DECLCALLBACK(int) pdmR0DevHlp_IoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
1213{
1214 PDMDEV_ASSERT_DEVINS(pDevIns);
1215 LogFlow(("pdmR0DevHlp_IoApicSetUpContext: caller='%s'/%d: pIoApicReg=%p:{.u32Version=%#x, .pfnSetIrq=%p, .pfnSendMsi=%p, .pfnSetEoi=%p, .u32TheEnd=%#x } ppIoApicHlp=%p\n",
1216 pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg, pIoApicReg->u32Version, pIoApicReg->pfnSetIrq, pIoApicReg->pfnSendMsi, pIoApicReg->pfnSetEoi, pIoApicReg->u32TheEnd, ppIoApicHlp));
1217 PGVM pGVM = pDevIns->Internal.s.pGVM;
1218
1219 /*
1220 * Validate input.
1221 */
1222 AssertMsgReturn(pIoApicReg->u32Version == PDM_IOAPICREG_VERSION,
1223 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg->u32Version, PDM_IOAPICREG_VERSION),
1224 VERR_VERSION_MISMATCH);
1225 AssertPtrReturn(pIoApicReg->pfnSetIrq, VERR_INVALID_POINTER);
1226 AssertPtrReturn(pIoApicReg->pfnSendMsi, VERR_INVALID_POINTER);
1227 AssertPtrReturn(pIoApicReg->pfnSetEoi, VERR_INVALID_POINTER);
1228 AssertMsgReturn(pIoApicReg->u32TheEnd == PDM_IOAPICREG_VERSION,
1229 ("%s/%d: u32TheEnd=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg->u32TheEnd, PDM_IOAPICREG_VERSION),
1230 VERR_VERSION_MISMATCH);
1231 AssertPtrReturn(ppIoApicHlp, VERR_INVALID_POINTER);
1232
1233 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1234 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1235
1236 /* Check that it's the same device as made the ring-3 registrations: */
1237 AssertLogRelMsgReturn(pGVM->pdm.s.IoApic.pDevInsR3 == pDevIns->pDevInsForR3,
1238 ("%p vs %p\n", pGVM->pdm.s.IoApic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1239
1240 /* Check that it isn't already registered in ring-0: */
1241 AssertLogRelMsgReturn(pGVM->pdm.s.IoApic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.IoApic.pDevInsR0, pDevIns),
1242 VERR_ALREADY_EXISTS);
1243
1244 /*
1245 * Take down the callbacks and instance.
1246 */
1247 pGVM->pdm.s.IoApic.pDevInsR0 = pDevIns;
1248 pGVM->pdm.s.IoApic.pfnSetIrqR0 = pIoApicReg->pfnSetIrq;
1249 pGVM->pdm.s.IoApic.pfnSendMsiR0 = pIoApicReg->pfnSendMsi;
1250 pGVM->pdm.s.IoApic.pfnSetEoiR0 = pIoApicReg->pfnSetEoi;
1251 Log(("PDM: Registered IOAPIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1252
1253 /* set the helper pointer and return. */
1254 *ppIoApicHlp = &g_pdmR0IoApicHlp;
1255 LogFlow(("pdmR0DevHlp_IoApicSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1256 return VINF_SUCCESS;
1257}
1258
1259
1260/** @interface_method_impl{PDMDEVHLPR0,pfnHpetSetUpContext} */
1261static DECLCALLBACK(int) pdmR0DevHlp_HpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp)
1262{
1263 PDMDEV_ASSERT_DEVINS(pDevIns);
1264 LogFlow(("pdmR0DevHlp_HpetSetUpContext: caller='%s'/%d: pHpetReg=%p:{.u32Version=%#x, } ppHpetHlp=%p\n",
1265 pDevIns->pReg->szName, pDevIns->iInstance, pHpetReg, pHpetReg->u32Version, ppHpetHlp));
1266 PGVM pGVM = pDevIns->Internal.s.pGVM;
1267
1268 /*
1269 * Validate input.
1270 */
1271 AssertMsgReturn(pHpetReg->u32Version == PDM_HPETREG_VERSION,
1272 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pHpetReg->u32Version, PDM_HPETREG_VERSION),
1273 VERR_VERSION_MISMATCH);
1274 AssertPtrReturn(ppHpetHlp, VERR_INVALID_POINTER);
1275
1276 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1277 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1278
1279 /* Check that it's the same device as made the ring-3 registrations: */
1280 AssertLogRelMsgReturn(pGVM->pdm.s.pHpet == pDevIns->pDevInsForR3, ("%p vs %p\n", pGVM->pdm.s.pHpet, pDevIns->pDevInsForR3),
1281 VERR_NOT_OWNER);
1282
1283 ///* Check that it isn't already registered in ring-0: */
1284 //AssertLogRelMsgReturn(pGVM->pdm.s.Hpet.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Hpet.pDevInsR0, pDevIns),
1285 // VERR_ALREADY_EXISTS);
1286
1287 /*
1288 * Nothing to take down here at present.
1289 */
1290 Log(("PDM: Registered HPET device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1291
1292 /* set the helper pointer and return. */
1293 *ppHpetHlp = &g_pdmR0HpetHlp;
1294 LogFlow(("pdmR0DevHlp_HpetSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1295 return VINF_SUCCESS;
1296}
1297
1298
1299/**
1300 * The Ring-0 Device Helper Callbacks.
1301 */
1302extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp =
1303{
1304 PDM_DEVHLPR0_VERSION,
1305 pdmR0DevHlp_IoPortSetUpContextEx,
1306 pdmR0DevHlp_MmioSetUpContextEx,
1307 pdmR0DevHlp_Mmio2SetUpContext,
1308 pdmR0DevHlp_PCIPhysRead,
1309 pdmR0DevHlp_PCIPhysWrite,
1310 pdmR0DevHlp_PCISetIrq,
1311 pdmR0DevHlp_ISASetIrq,
1312 pdmR0DevHlp_PhysRead,
1313 pdmR0DevHlp_PhysWrite,
1314 pdmR0DevHlp_A20IsEnabled,
1315 pdmR0DevHlp_VMState,
1316 pdmR0DevHlp_VMSetError,
1317 pdmR0DevHlp_VMSetErrorV,
1318 pdmR0DevHlp_VMSetRuntimeError,
1319 pdmR0DevHlp_VMSetRuntimeErrorV,
1320 pdmR0DevHlp_GetVM,
1321 pdmR0DevHlp_GetVMCPU,
1322 pdmR0DevHlp_GetCurrentCpuId,
1323 pdmR0DevHlp_TimerToPtr,
1324 pdmR0DevHlp_TimerFromMicro,
1325 pdmR0DevHlp_TimerFromMilli,
1326 pdmR0DevHlp_TimerFromNano,
1327 pdmR0DevHlp_TimerGet,
1328 pdmR0DevHlp_TimerGetFreq,
1329 pdmR0DevHlp_TimerGetNano,
1330 pdmR0DevHlp_TimerIsActive,
1331 pdmR0DevHlp_TimerIsLockOwner,
1332 pdmR0DevHlp_TimerLockClock,
1333 pdmR0DevHlp_TimerLockClock2,
1334 pdmR0DevHlp_TimerSet,
1335 pdmR0DevHlp_TimerSetFrequencyHint,
1336 pdmR0DevHlp_TimerSetMicro,
1337 pdmR0DevHlp_TimerSetMillies,
1338 pdmR0DevHlp_TimerSetNano,
1339 pdmR0DevHlp_TimerSetRelative,
1340 pdmR0DevHlp_TimerStop,
1341 pdmR0DevHlp_TimerUnlockClock,
1342 pdmR0DevHlp_TimerUnlockClock2,
1343 pdmR0DevHlp_TMTimeVirtGet,
1344 pdmR0DevHlp_TMTimeVirtGetFreq,
1345 pdmR0DevHlp_TMTimeVirtGetNano,
1346 pdmR0DevHlp_QueueToPtr,
1347 pdmR0DevHlp_QueueAlloc,
1348 pdmR0DevHlp_QueueInsert,
1349 pdmR0DevHlp_QueueInsertEx,
1350 pdmR0DevHlp_QueueFlushIfNecessary,
1351 pdmR0DevHlp_TaskTrigger,
1352 pdmR0DevHlp_SUPSemEventSignal,
1353 pdmR0DevHlp_SUPSemEventWaitNoResume,
1354 pdmR0DevHlp_SUPSemEventWaitNsAbsIntr,
1355 pdmR0DevHlp_SUPSemEventWaitNsRelIntr,
1356 pdmR0DevHlp_SUPSemEventGetResolution,
1357 pdmR0DevHlp_SUPSemEventMultiSignal,
1358 pdmR0DevHlp_SUPSemEventMultiReset,
1359 pdmR0DevHlp_SUPSemEventMultiWaitNoResume,
1360 pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr,
1361 pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr,
1362 pdmR0DevHlp_SUPSemEventMultiGetResolution,
1363 pdmR0DevHlp_CritSectGetNop,
1364 pdmR0DevHlp_SetDeviceCritSect,
1365 pdmR0DevHlp_CritSectEnter,
1366 pdmR0DevHlp_CritSectEnterDebug,
1367 pdmR0DevHlp_CritSectTryEnter,
1368 pdmR0DevHlp_CritSectTryEnterDebug,
1369 pdmR0DevHlp_CritSectLeave,
1370 pdmR0DevHlp_CritSectIsOwner,
1371 pdmR0DevHlp_CritSectIsInitialized,
1372 pdmR0DevHlp_CritSectHasWaiters,
1373 pdmR0DevHlp_CritSectGetRecursion,
1374 pdmR0DevHlp_CritSectScheduleExitEvent,
1375 pdmR0DevHlp_DBGFTraceBuf,
1376 pdmR0DevHlp_PCIBusSetUpContext,
1377 pdmR0DevHlp_IommuSetUpContext,
1378 pdmR0DevHlp_PICSetUpContext,
1379 pdmR0DevHlp_ApicSetUpContext,
1380 pdmR0DevHlp_IoApicSetUpContext,
1381 pdmR0DevHlp_HpetSetUpContext,
1382 NULL /*pfnReserved1*/,
1383 NULL /*pfnReserved2*/,
1384 NULL /*pfnReserved3*/,
1385 NULL /*pfnReserved4*/,
1386 NULL /*pfnReserved5*/,
1387 NULL /*pfnReserved6*/,
1388 NULL /*pfnReserved7*/,
1389 NULL /*pfnReserved8*/,
1390 NULL /*pfnReserved9*/,
1391 NULL /*pfnReserved10*/,
1392 PDM_DEVHLPR0_VERSION
1393};
1394
1395
1396#ifdef VBOX_WITH_DBGF_TRACING
1397/**
1398 * The Ring-0 Device Helper Callbacks - tracing variant.
1399 */
1400extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlpTracing =
1401{
1402 PDM_DEVHLPR0_VERSION,
1403 pdmR0DevHlpTracing_IoPortSetUpContextEx,
1404 pdmR0DevHlpTracing_MmioSetUpContextEx,
1405 pdmR0DevHlp_Mmio2SetUpContext,
1406 pdmR0DevHlpTracing_PCIPhysRead,
1407 pdmR0DevHlpTracing_PCIPhysWrite,
1408 pdmR0DevHlpTracing_PCISetIrq,
1409 pdmR0DevHlpTracing_ISASetIrq,
1410 pdmR0DevHlp_PhysRead,
1411 pdmR0DevHlp_PhysWrite,
1412 pdmR0DevHlp_A20IsEnabled,
1413 pdmR0DevHlp_VMState,
1414 pdmR0DevHlp_VMSetError,
1415 pdmR0DevHlp_VMSetErrorV,
1416 pdmR0DevHlp_VMSetRuntimeError,
1417 pdmR0DevHlp_VMSetRuntimeErrorV,
1418 pdmR0DevHlp_GetVM,
1419 pdmR0DevHlp_GetVMCPU,
1420 pdmR0DevHlp_GetCurrentCpuId,
1421 pdmR0DevHlp_TimerToPtr,
1422 pdmR0DevHlp_TimerFromMicro,
1423 pdmR0DevHlp_TimerFromMilli,
1424 pdmR0DevHlp_TimerFromNano,
1425 pdmR0DevHlp_TimerGet,
1426 pdmR0DevHlp_TimerGetFreq,
1427 pdmR0DevHlp_TimerGetNano,
1428 pdmR0DevHlp_TimerIsActive,
1429 pdmR0DevHlp_TimerIsLockOwner,
1430 pdmR0DevHlp_TimerLockClock,
1431 pdmR0DevHlp_TimerLockClock2,
1432 pdmR0DevHlp_TimerSet,
1433 pdmR0DevHlp_TimerSetFrequencyHint,
1434 pdmR0DevHlp_TimerSetMicro,
1435 pdmR0DevHlp_TimerSetMillies,
1436 pdmR0DevHlp_TimerSetNano,
1437 pdmR0DevHlp_TimerSetRelative,
1438 pdmR0DevHlp_TimerStop,
1439 pdmR0DevHlp_TimerUnlockClock,
1440 pdmR0DevHlp_TimerUnlockClock2,
1441 pdmR0DevHlp_TMTimeVirtGet,
1442 pdmR0DevHlp_TMTimeVirtGetFreq,
1443 pdmR0DevHlp_TMTimeVirtGetNano,
1444 pdmR0DevHlp_QueueToPtr,
1445 pdmR0DevHlp_QueueAlloc,
1446 pdmR0DevHlp_QueueInsert,
1447 pdmR0DevHlp_QueueInsertEx,
1448 pdmR0DevHlp_QueueFlushIfNecessary,
1449 pdmR0DevHlp_TaskTrigger,
1450 pdmR0DevHlp_SUPSemEventSignal,
1451 pdmR0DevHlp_SUPSemEventWaitNoResume,
1452 pdmR0DevHlp_SUPSemEventWaitNsAbsIntr,
1453 pdmR0DevHlp_SUPSemEventWaitNsRelIntr,
1454 pdmR0DevHlp_SUPSemEventGetResolution,
1455 pdmR0DevHlp_SUPSemEventMultiSignal,
1456 pdmR0DevHlp_SUPSemEventMultiReset,
1457 pdmR0DevHlp_SUPSemEventMultiWaitNoResume,
1458 pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr,
1459 pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr,
1460 pdmR0DevHlp_SUPSemEventMultiGetResolution,
1461 pdmR0DevHlp_CritSectGetNop,
1462 pdmR0DevHlp_SetDeviceCritSect,
1463 pdmR0DevHlp_CritSectEnter,
1464 pdmR0DevHlp_CritSectEnterDebug,
1465 pdmR0DevHlp_CritSectTryEnter,
1466 pdmR0DevHlp_CritSectTryEnterDebug,
1467 pdmR0DevHlp_CritSectLeave,
1468 pdmR0DevHlp_CritSectIsOwner,
1469 pdmR0DevHlp_CritSectIsInitialized,
1470 pdmR0DevHlp_CritSectHasWaiters,
1471 pdmR0DevHlp_CritSectGetRecursion,
1472 pdmR0DevHlp_CritSectScheduleExitEvent,
1473 pdmR0DevHlp_DBGFTraceBuf,
1474 pdmR0DevHlp_PCIBusSetUpContext,
1475 pdmR0DevHlp_IommuSetUpContext,
1476 pdmR0DevHlp_PICSetUpContext,
1477 pdmR0DevHlp_ApicSetUpContext,
1478 pdmR0DevHlp_IoApicSetUpContext,
1479 pdmR0DevHlp_HpetSetUpContext,
1480 NULL /*pfnReserved1*/,
1481 NULL /*pfnReserved2*/,
1482 NULL /*pfnReserved3*/,
1483 NULL /*pfnReserved4*/,
1484 NULL /*pfnReserved5*/,
1485 NULL /*pfnReserved6*/,
1486 NULL /*pfnReserved7*/,
1487 NULL /*pfnReserved8*/,
1488 NULL /*pfnReserved9*/,
1489 NULL /*pfnReserved10*/,
1490 PDM_DEVHLPR0_VERSION
1491};
1492#endif
1493
1494
1495/** @} */
1496
1497
1498/** @name PIC Ring-0 Helpers
1499 * @{
1500 */
1501
1502/** @interface_method_impl{PDMPICHLP,pfnSetInterruptFF} */
1503static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
1504{
1505 PDMDEV_ASSERT_DEVINS(pDevIns);
1506 PGVM pGVM = (PGVM)pDevIns->Internal.s.pGVM;
1507 PVMCPUCC pVCpu = &pGVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
1508 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
1509 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
1510}
1511
1512
1513/** @interface_method_impl{PDMPICHLP,pfnClearInterruptFF} */
1514static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
1515{
1516 PDMDEV_ASSERT_DEVINS(pDevIns);
1517 PGVM pGVM = (PGVM)pDevIns->Internal.s.pGVM;
1518 PVMCPUCC pVCpu = &pGVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
1519 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
1520 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
1521}
1522
1523
1524/** @interface_method_impl{PDMPICHLP,pfnLock} */
1525static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
1526{
1527 PDMDEV_ASSERT_DEVINS(pDevIns);
1528 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1529}
1530
1531
1532/** @interface_method_impl{PDMPICHLP,pfnUnlock} */
1533static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns)
1534{
1535 PDMDEV_ASSERT_DEVINS(pDevIns);
1536 pdmUnlock(pDevIns->Internal.s.pGVM);
1537}
1538
1539
1540/**
1541 * The Ring-0 PIC Helper Callbacks.
1542 */
1543extern DECLEXPORT(const PDMPICHLP) g_pdmR0PicHlp =
1544{
1545 PDM_PICHLP_VERSION,
1546 pdmR0PicHlp_SetInterruptFF,
1547 pdmR0PicHlp_ClearInterruptFF,
1548 pdmR0PicHlp_Lock,
1549 pdmR0PicHlp_Unlock,
1550 PDM_PICHLP_VERSION
1551};
1552
1553/** @} */
1554
1555
1556/** @name I/O APIC Ring-0 Helpers
1557 * @{
1558 */
1559
1560/** @interface_method_impl{PDMIOAPICHLP,pfnApicBusDeliver} */
1561static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
1562 uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
1563 uint8_t u8TriggerMode, uint32_t uTagSrc)
1564{
1565 PDMDEV_ASSERT_DEVINS(pDevIns);
1566 PGVM pGVM = pDevIns->Internal.s.pGVM;
1567 LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
1568 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
1569 return APICBusDeliver(pGVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
1570}
1571
1572
1573/** @interface_method_impl{PDMIOAPICHLP,pfnLock} */
1574static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
1575{
1576 PDMDEV_ASSERT_DEVINS(pDevIns);
1577 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1578}
1579
1580
1581/** @interface_method_impl{PDMIOAPICHLP,pfnUnlock} */
1582static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns)
1583{
1584 PDMDEV_ASSERT_DEVINS(pDevIns);
1585 pdmUnlock(pDevIns->Internal.s.pGVM);
1586}
1587
1588
1589/** @interface_method_impl{PDMIOAPICHLP,pfnIommuMsiRemap} */
1590static DECLCALLBACK(int) pdmR0IoApicHlp_IommuMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1591{
1592 PDMDEV_ASSERT_DEVINS(pDevIns);
1593 LogFlow(("pdmR0IoApicHlp_IommuMsiRemap: caller='%s'/%d: pMsiIn=(%#RX64, %#RU32)\n", pDevIns->pReg->szName,
1594 pDevIns->iInstance, pMsiIn->Addr.u64, pMsiIn->Data.u32));
1595
1596#ifdef VBOX_WITH_IOMMU_AMD
1597 /** @todo IOMMU: Optimize/re-organize things here later. */
1598 PGVM pGVM = pDevIns->Internal.s.pGVM;
1599 PPDMIOMMUR0 pIommu = &pGVM->pdmr0.s.aIommus[0];
1600 PPDMDEVINS pDevInsIommu = pIommu->CTX_SUFF(pDevIns);
1601 if ( pDevInsIommu
1602 && pDevInsIommu != pDevIns)
1603 {
1604 AssertMsgReturn(VALID_PTR(pIommu->pfnMsiRemap),
1605 ("pdmR0IoApicHlp_IommuMsiRemap: pfnMsiRemap invalid!\n"), VERR_INVALID_POINTER);
1606 int rc = pIommu->pfnMsiRemap(pDevInsIommu, uDevId, pMsiIn, pMsiOut);
1607 if (RT_SUCCESS(rc))
1608 return rc;
1609
1610 Log(("pdmR0IoApicHlp_IommuMsiRemap: IOMMU MSI remap failed. uDevId=%#x pMsiIn=(%#RX64, %#RU32) rc=%Rrc\n",
1611 uDevId, pMsiIn->Addr.u64, pMsiIn->Data.u32, rc));
1612 }
1613#else
1614 RT_NOREF(pDevIns, uDevId);
1615#endif
1616
1617 *pMsiOut = *pMsiIn;
1618 return VINF_SUCCESS;
1619}
1620
1621
1622/**
1623 * The Ring-0 I/O APIC Helper Callbacks.
1624 */
1625extern DECLEXPORT(const PDMIOAPICHLP) g_pdmR0IoApicHlp =
1626{
1627 PDM_IOAPICHLP_VERSION,
1628 pdmR0IoApicHlp_ApicBusDeliver,
1629 pdmR0IoApicHlp_Lock,
1630 pdmR0IoApicHlp_Unlock,
1631 pdmR0IoApicHlp_IommuMsiRemap,
1632 PDM_IOAPICHLP_VERSION
1633};
1634
1635/** @} */
1636
1637
1638
1639
1640/** @name PCI Bus Ring-0 Helpers
1641 * @{
1642 */
1643
1644/** @interface_method_impl{PDMPCIHLPR0,pfnIsaSetIrq} */
1645static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
1646{
1647 PDMDEV_ASSERT_DEVINS(pDevIns);
1648 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
1649 PGVM pGVM = pDevIns->Internal.s.pGVM;
1650
1651 pdmLock(pGVM);
1652 pdmR0IsaSetIrq(pGVM, iIrq, iLevel, uTagSrc);
1653 pdmUnlock(pGVM);
1654}
1655
1656
1657/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSetIrq} */
1658static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
1659{
1660 PDMDEV_ASSERT_DEVINS(pDevIns);
1661 Log4(("pdmR0PciHlp_IoApicSetIrq: uBusDevFn=%#x iIrq=%d iLevel=%d uTagSrc=%#x\n", uBusDevFn, iIrq, iLevel, uTagSrc));
1662 PGVM pGVM = pDevIns->Internal.s.pGVM;
1663
1664 if (pGVM->pdm.s.IoApic.pDevInsR0)
1665 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, uBusDevFn, iIrq, iLevel, uTagSrc);
1666 else if (pGVM->pdm.s.IoApic.pDevInsR3)
1667 {
1668 /* queue for ring-3 execution. */
1669 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
1670 if (pTask)
1671 {
1672 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
1673 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
1674 pTask->u.IoApicSetIRQ.uBusDevFn = uBusDevFn;
1675 pTask->u.IoApicSetIRQ.iIrq = iIrq;
1676 pTask->u.IoApicSetIRQ.iLevel = iLevel;
1677 pTask->u.IoApicSetIRQ.uTagSrc = uTagSrc;
1678
1679 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
1680 }
1681 else
1682 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
1683 }
1684}
1685
1686
1687/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSendMsi} */
1688static DECLCALLBACK(void) pdmR0PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
1689{
1690 PDMDEV_ASSERT_DEVINS(pDevIns);
1691 Assert(PCIBDF_IS_VALID(uBusDevFn));
1692 Log4(("pdmR0PciHlp_IoApicSendMsi: uBusDevFn=%#x Msi=(Addr:%#RX64 Data:%#RX32) uTagSrc=%#x\n", uBusDevFn, pMsi->Addr.u64,
1693 pMsi->Data.u32, uTagSrc));
1694 PGVM pGVM = pDevIns->Internal.s.pGVM;
1695 if (pGVM->pdm.s.IoApic.pDevInsR0)
1696 pGVM->pdm.s.IoApic.pfnSendMsiR0(pGVM->pdm.s.IoApic.pDevInsR0, uBusDevFn, pMsi, uTagSrc);
1697 else
1698 AssertFatalMsgFailed(("Lazy bastards!"));
1699}
1700
1701
1702/** @interface_method_impl{PDMPCIHLPR0,pfnLock} */
1703static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
1704{
1705 PDMDEV_ASSERT_DEVINS(pDevIns);
1706 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1707}
1708
1709
1710/** @interface_method_impl{PDMPCIHLPR0,pfnUnlock} */
1711static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns)
1712{
1713 PDMDEV_ASSERT_DEVINS(pDevIns);
1714 pdmUnlock(pDevIns->Internal.s.pGVM);
1715}
1716
1717
1718/** @interface_method_impl{PDMPCIHLPR0,pfnGetBusByNo} */
1719static DECLCALLBACK(PPDMDEVINS) pdmR0PciHlp_GetBusByNo(PPDMDEVINS pDevIns, uint32_t idxPdmBus)
1720{
1721 PDMDEV_ASSERT_DEVINS(pDevIns);
1722 PGVM pGVM = pDevIns->Internal.s.pGVM;
1723 AssertReturn(idxPdmBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses), NULL);
1724 PPDMDEVINS pRetDevIns = pGVM->pdmr0.s.aPciBuses[idxPdmBus].pDevInsR0;
1725 LogFlow(("pdmR3PciHlp_GetBusByNo: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRetDevIns));
1726 return pRetDevIns;
1727}
1728
1729
1730/**
1731 * The Ring-0 PCI Bus Helper Callbacks.
1732 */
1733extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp =
1734{
1735 PDM_PCIHLPR0_VERSION,
1736 pdmR0PciHlp_IsaSetIrq,
1737 pdmR0PciHlp_IoApicSetIrq,
1738 pdmR0PciHlp_IoApicSendMsi,
1739 pdmR0PciHlp_Lock,
1740 pdmR0PciHlp_Unlock,
1741 pdmR0PciHlp_GetBusByNo,
1742 PDM_PCIHLPR0_VERSION, /* the end */
1743};
1744
1745/** @} */
1746
1747
1748/** @name IOMMU Ring-0 Helpers
1749 * @{
1750 */
1751
1752/**
1753 * The Ring-0 IOMMU Helper Callbacks.
1754 */
1755extern DECLEXPORT(const PDMIOMMUHLPR0) g_pdmR0IommuHlp =
1756{
1757 PDM_IOMMUHLPR0_VERSION,
1758 PDM_IOMMUHLPR0_VERSION, /* the end */
1759};
1760
1761/** @} */
1762
1763
1764/** @name HPET Ring-0 Helpers
1765 * @{
1766 */
1767/* none */
1768
1769/**
1770 * The Ring-0 HPET Helper Callbacks.
1771 */
1772extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp =
1773{
1774 PDM_HPETHLPR0_VERSION,
1775 PDM_HPETHLPR0_VERSION, /* the end */
1776};
1777
1778/** @} */
1779
1780
1781/** @name Raw PCI Ring-0 Helpers
1782 * @{
1783 */
1784/* none */
1785
1786/**
1787 * The Ring-0 PCI raw Helper Callbacks.
1788 */
1789extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp =
1790{
1791 PDM_PCIRAWHLPR0_VERSION,
1792 PDM_PCIRAWHLPR0_VERSION, /* the end */
1793};
1794
1795/** @} */
1796
1797
1798
1799
1800/**
1801 * Sets an irq on the PIC and I/O APIC.
1802 *
1803 * @returns true if delivered, false if postponed.
1804 * @param pGVM The global (ring-0) VM structure.
1805 * @param iIrq The irq.
1806 * @param iLevel The new level.
1807 * @param uTagSrc The IRQ tag and source.
1808 *
1809 * @remarks The caller holds the PDM lock.
1810 */
1811DECLHIDDEN(bool) pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc)
1812{
1813 if (RT_LIKELY( ( pGVM->pdm.s.IoApic.pDevInsR0
1814 || !pGVM->pdm.s.IoApic.pDevInsR3)
1815 && ( pGVM->pdm.s.Pic.pDevInsR0
1816 || !pGVM->pdm.s.Pic.pDevInsR3)))
1817 {
1818 if (pGVM->pdm.s.Pic.pDevInsR0)
1819 pGVM->pdm.s.Pic.pfnSetIrqR0(pGVM->pdm.s.Pic.pDevInsR0, iIrq, iLevel, uTagSrc);
1820 if (pGVM->pdm.s.IoApic.pDevInsR0)
1821 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, NIL_PCIBDF, iIrq, iLevel, uTagSrc);
1822 return true;
1823 }
1824
1825 /* queue for ring-3 execution. */
1826 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
1827 AssertReturn(pTask, false);
1828
1829 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
1830 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
1831 pTask->u.IsaSetIRQ.uBusDevFn = NIL_PCIBDF;
1832 pTask->u.IsaSetIRQ.iIrq = iIrq;
1833 pTask->u.IsaSetIRQ.iLevel = iLevel;
1834 pTask->u.IsaSetIRQ.uTagSrc = uTagSrc;
1835
1836 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
1837 return false;
1838}
1839
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