VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.h@ 25046

Last change on this file since 25046 was 20374, checked in by vboxsync, 16 years ago

*: s/RT_\(BEGIN|END\)_DECLS/RT_C_DECLS_\1/g
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 16.3 KB
Line 
1/* $Id: HWVMXR0.h 20374 2009-06-08 00:43:21Z vboxsync $ */
2/** @file
3 * HWACCM VT-x - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___HWVMXR0_h
23#define ___HWVMXR0_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/em.h>
28#include <VBox/stam.h>
29#include <VBox/dis.h>
30#include <VBox/hwaccm.h>
31#include <VBox/pgm.h>
32#include <VBox/hwacc_vmx.h>
33
34RT_C_DECLS_BEGIN
35
36/** @defgroup grp_vmx_int Internal
37 * @ingroup grp_vmx
38 * @internal
39 * @{
40 */
41
42/* Read cache indices. */
43#define VMX_VMCS64_GUEST_RIP_CACHE_IDX 0
44#define VMX_VMCS64_GUEST_RSP_CACHE_IDX 1
45#define VMX_VMCS_GUEST_RFLAGS_CACHE_IDX 2
46#define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE_CACHE_IDX 3
47#define VMX_VMCS_CTRL_CR0_READ_SHADOW_CACHE_IDX 4
48#define VMX_VMCS64_GUEST_CR0_CACHE_IDX 5
49#define VMX_VMCS_CTRL_CR4_READ_SHADOW_CACHE_IDX 6
50#define VMX_VMCS64_GUEST_CR4_CACHE_IDX 7
51#define VMX_VMCS64_GUEST_DR7_CACHE_IDX 8
52#define VMX_VMCS32_GUEST_SYSENTER_CS_CACHE_IDX 9
53#define VMX_VMCS64_GUEST_SYSENTER_EIP_CACHE_IDX 10
54#define VMX_VMCS64_GUEST_SYSENTER_ESP_CACHE_IDX 11
55#define VMX_VMCS32_GUEST_GDTR_LIMIT_CACHE_IDX 12
56#define VMX_VMCS64_GUEST_GDTR_BASE_CACHE_IDX 13
57#define VMX_VMCS32_GUEST_IDTR_LIMIT_CACHE_IDX 14
58#define VMX_VMCS64_GUEST_IDTR_BASE_CACHE_IDX 15
59#define VMX_VMCS16_GUEST_FIELD_CS_CACHE_IDX 16
60#define VMX_VMCS32_GUEST_CS_LIMIT_CACHE_IDX 17
61#define VMX_VMCS64_GUEST_CS_BASE_CACHE_IDX 18
62#define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS_CACHE_IDX 19
63#define VMX_VMCS16_GUEST_FIELD_DS_CACHE_IDX 20
64#define VMX_VMCS32_GUEST_DS_LIMIT_CACHE_IDX 21
65#define VMX_VMCS64_GUEST_DS_BASE_CACHE_IDX 22
66#define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS_CACHE_IDX 23
67#define VMX_VMCS16_GUEST_FIELD_ES_CACHE_IDX 24
68#define VMX_VMCS32_GUEST_ES_LIMIT_CACHE_IDX 25
69#define VMX_VMCS64_GUEST_ES_BASE_CACHE_IDX 26
70#define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS_CACHE_IDX 27
71#define VMX_VMCS16_GUEST_FIELD_FS_CACHE_IDX 28
72#define VMX_VMCS32_GUEST_FS_LIMIT_CACHE_IDX 29
73#define VMX_VMCS64_GUEST_FS_BASE_CACHE_IDX 30
74#define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS_CACHE_IDX 31
75#define VMX_VMCS16_GUEST_FIELD_GS_CACHE_IDX 32
76#define VMX_VMCS32_GUEST_GS_LIMIT_CACHE_IDX 33
77#define VMX_VMCS64_GUEST_GS_BASE_CACHE_IDX 34
78#define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS_CACHE_IDX 35
79#define VMX_VMCS16_GUEST_FIELD_SS_CACHE_IDX 36
80#define VMX_VMCS32_GUEST_SS_LIMIT_CACHE_IDX 37
81#define VMX_VMCS64_GUEST_SS_BASE_CACHE_IDX 38
82#define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS_CACHE_IDX 39
83#define VMX_VMCS16_GUEST_FIELD_TR_CACHE_IDX 40
84#define VMX_VMCS32_GUEST_TR_LIMIT_CACHE_IDX 41
85#define VMX_VMCS64_GUEST_TR_BASE_CACHE_IDX 42
86#define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS_CACHE_IDX 43
87#define VMX_VMCS16_GUEST_FIELD_LDTR_CACHE_IDX 44
88#define VMX_VMCS32_GUEST_LDTR_LIMIT_CACHE_IDX 45
89#define VMX_VMCS64_GUEST_LDTR_BASE_CACHE_IDX 46
90#define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS_CACHE_IDX 47
91#define VMX_VMCS32_RO_EXIT_REASON_CACHE_IDX 48
92#define VMX_VMCS32_RO_VM_INSTR_ERROR_CACHE_IDX 49
93#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH_CACHE_IDX 50
94#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE_CACHE_IDX 51
95#define VMX_VMCS32_RO_EXIT_INSTR_INFO_CACHE_IDX 52
96#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO_CACHE_IDX 53
97#define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX 54
98#define VMX_VMCS32_RO_IDT_INFO_CACHE_IDX 55
99#define VMX_VMCS32_RO_IDT_ERRCODE_CACHE_IDX 56
100#define VMX_VMCS_MAX_CACHE_IDX (VMX_VMCS32_RO_IDT_ERRCODE_CACHE_IDX+1)
101#define VMX_VMCS64_GUEST_CR3_CACHE_IDX 57
102#define VMX_VMCS_EXIT_PHYS_ADDR_FULL_CACHE_IDX 58
103#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX (VMX_VMCS_EXIT_PHYS_ADDR_FULL_CACHE_IDX+1)
104
105
106#ifdef IN_RING0
107
108/**
109 * Enters the VT-x session
110 *
111 * @returns VBox status code.
112 * @param pVM The VM to operate on.
113 * @param pVCpu The VMCPU to operate on.
114 * @param pCpu CPU info struct
115 */
116VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
117
118/**
119 * Leaves the VT-x session
120 *
121 * @returns VBox status code.
122 * @param pVM The VM to operate on.
123 * @param pVCpu The VMCPU to operate on.
124 * @param pCtx CPU context
125 */
126VMMR0DECL(int) VMXR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
127
128
129/**
130 * Sets up and activates VT-x on the current CPU
131 *
132 * @returns VBox status code.
133 * @param pCpu CPU info struct
134 * @param pVM The VM to operate on. (can be NULL after a resume)
135 * @param pvPageCpu Pointer to the global cpu page
136 * @param pPageCpuPhys Physical address of the global cpu page
137 */
138VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
139
140/**
141 * Deactivates VT-x on the current CPU
142 *
143 * @returns VBox status code.
144 * @param pCpu CPU info struct
145 * @param pvPageCpu Pointer to the global cpu page
146 * @param pPageCpuPhys Physical address of the global cpu page
147 */
148VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
149
150/**
151 * Does Ring-0 per VM VT-x init.
152 *
153 * @returns VBox status code.
154 * @param pVM The VM to operate on.
155 */
156VMMR0DECL(int) VMXR0InitVM(PVM pVM);
157
158/**
159 * Does Ring-0 per VM VT-x termination.
160 *
161 * @returns VBox status code.
162 * @param pVM The VM to operate on.
163 */
164VMMR0DECL(int) VMXR0TermVM(PVM pVM);
165
166/**
167 * Sets up VT-x for the specified VM
168 *
169 * @returns VBox status code.
170 * @param pVM The VM to operate on.
171 */
172VMMR0DECL(int) VMXR0SetupVM(PVM pVM);
173
174
175/**
176 * Save the host state
177 *
178 * @returns VBox status code.
179 * @param pVM The VM to operate on.
180 * @param pVCpu The VMCPU to operate on.
181 */
182VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu);
183
184/**
185 * Loads the guest state
186 *
187 * @returns VBox status code.
188 * @param pVM The VM to operate on.
189 * @param pVCpu The VMCPU to operate on.
190 * @param pCtx Guest context
191 */
192VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
193
194
195/**
196 * Runs guest code in a VT-x VM.
197 *
198 * @returns VBox status code.
199 * @param pVM The VM to operate on.
200 * @param pVCpu The VMCPU to operate on.
201 * @param pCtx Guest context
202 */
203VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
204
205
206# if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
207/**
208 * Executes the specified handler in 64 mode
209 *
210 * @returns VBox status code.
211 * @param pVM The VM to operate on.
212 * @param pVCpu The VMCPU to operate on.
213 * @param pCtx Guest context
214 * @param pfnHandler RC handler
215 * @param cbParam Number of parameters
216 * @param paParam Array of 32 bits parameters
217 */
218VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam);
219# endif
220
221# define VMX_WRITE_SELREG(REG, reg) \
222{ \
223 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_##REG, pCtx->reg); \
224 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT, pCtx->reg##Hid.u32Limit); \
225 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_##REG##_BASE, pCtx->reg##Hid.u64Base); \
226 if ((pCtx->eflags.u32 & X86_EFL_VM)) \
227 val = pCtx->reg##Hid.Attr.u; \
228 else \
229 if (CPUMIsGuestInRealModeEx(pCtx)) \
230 { \
231 /* Must override this or else VT-x will fail with invalid guest state errors. */ \
232 /* DPL=3, present, code/data, r/w/accessed. */ \
233 val = 0xf3; \
234 } \
235 else \
236 if ( ((!pCtx->csHid.Attr.n.u1DefBig && !CPUMIsGuestIn64BitCodeEx(pCtx)) || pCtx->reg) \
237 && pCtx->reg##Hid.Attr.n.u1Present == 1) \
238 val = pCtx->reg##Hid.Attr.u | X86_SEL_TYPE_ACCESSED; \
239 else \
240 val = 0x10000; /* Invalid guest state error otherwise. (BIT(16) = Unusable) */ \
241 \
242 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, val); \
243}
244
245# define VMX_READ_SELREG(REG, reg) \
246{ \
247 VMXReadCachedVMCS(VMX_VMCS16_GUEST_FIELD_##REG, &val); \
248 pCtx->reg = val; \
249 VMXReadCachedVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT, &val); \
250 pCtx->reg##Hid.u32Limit = val; \
251 VMXReadCachedVMCS(VMX_VMCS64_GUEST_##REG##_BASE, &val); \
252 pCtx->reg##Hid.u64Base = val; \
253 VMXReadCachedVMCS(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, &val); \
254 pCtx->reg##Hid.Attr.u = val; \
255}
256
257/* Don't read from the cache in this macro; used only in case of failure where the cache is out of sync. */
258# define VMX_LOG_SELREG(REG, szSelReg) \
259{ \
260 VMXReadVMCS(VMX_VMCS16_GUEST_FIELD_##REG, &val); \
261 Log(("%s Selector %x\n", szSelReg, val)); \
262 VMXReadVMCS(VMX_VMCS32_GUEST_##REG##_LIMIT, &val); \
263 Log(("%s Limit %x\n", szSelReg, val)); \
264 VMXReadVMCS(VMX_VMCS64_GUEST_##REG##_BASE, &val); \
265 Log(("%s Base %RX64\n", szSelReg, (uint64_t)val)); \
266 VMXReadVMCS(VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS, &val); \
267 Log(("%s Attributes %x\n", szSelReg, val)); \
268}
269
270/**
271 * Cache VMCS writes for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
272 *
273 * @param pVCpu The VMCPU to operate on.
274 * @param idxField VMCS field
275 * @param u64Val Value
276 */
277VMMR0DECL(int) VMXWriteCachedVMCSEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val);
278
279#ifdef VMX_USE_CACHED_VMCS_ACCESSES
280/**
281 * Return value of cached VMCS read for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
282 *
283 * @param pVCpu The VMCPU to operate on.
284 * @param idxField VMCS cache index (not VMCS field index!)
285 * @param pVal Value
286 */
287DECLINLINE(int) VMXReadCachedVMCSEx(PVMCPU pVCpu, uint32_t idxCache, RTGCUINTREG *pVal)
288{
289 Assert(idxCache <= VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX);
290 *pVal = pVCpu->hwaccm.s.vmx.VMCSCache.Read.aFieldVal[idxCache];
291 return VINF_SUCCESS;
292}
293#endif
294
295/**
296 * Return value of cached VMCS read for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
297 *
298 * @param idxField VMCS field
299 * @param pVal Value pointer (out)
300 */
301#ifdef VMX_USE_CACHED_VMCS_ACCESSES
302# define VMXReadCachedVMCS(idxField, pVal) VMXReadCachedVMCSEx(pVCpu, idxField##_CACHE_IDX, pVal)
303#else
304# define VMXReadCachedVMCS(idxField, pVal) VMXReadVMCS(idxField, pVal)
305#endif
306
307/**
308 * Setup cached VMCS for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
309 *
310 * @param pVCpu The VMCPU to operate on.
311 * @param idxField VMCS field
312 */
313#define VMXSetupCachedReadVMCS(pCache, idxField) \
314{ \
315 Assert(pCache->Read.aField[idxField##_CACHE_IDX] == 0); \
316 pCache->Read.aField[idxField##_CACHE_IDX] = idxField; \
317 pCache->Read.aFieldVal[idxField##_CACHE_IDX] = 0; \
318}
319
320#define VMX_SETUP_SELREG(REG, pCache) \
321{ \
322 VMXSetupCachedReadVMCS(pCache, VMX_VMCS16_GUEST_FIELD_##REG); \
323 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_##REG##_LIMIT); \
324 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_##REG##_BASE); \
325 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_##REG##_ACCESS_RIGHTS); \
326}
327
328/**
329 * Prepares for and executes VMLAUNCH (32 bits guest mode)
330 *
331 * @returns VBox status code
332 * @param fResume vmlauch/vmresume
333 * @param pCtx Guest context
334 * @param pCache VMCS cache
335 * @param pVM The VM to operate on.
336 * @param pVCpu The VMCPU to operate on.
337 */
338DECLASM(int) VMXR0StartVM32(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
339
340/**
341 * Prepares for and executes VMLAUNCH (64 bits guest mode)
342 *
343 * @returns VBox status code
344 * @param fResume vmlauch/vmresume
345 * @param pCtx Guest context
346 * @param pCache VMCS cache
347 * @param pVM The VM to operate on.
348 * @param pVCpu The VMCPU to operate on.
349 */
350DECLASM(int) VMXR0StartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
351
352# if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
353/**
354 * Prepares for and executes VMLAUNCH (64 bits guest mode)
355 *
356 * @returns VBox status code
357 * @param fResume vmlauch/vmresume
358 * @param pCtx Guest context
359 * @param pCache VMCS cache
360 * @param pVM The VM to operate on.
361 * @param pVCpu The VMCPU to operate on.
362 */
363DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
364# endif
365
366#endif /* IN_RING0 */
367
368/** @} */
369
370RT_C_DECLS_END
371
372#endif
373
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette