VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 19015

Last change on this file since 19015 was 19015, checked in by vboxsync, 16 years ago

Split up TRPM. (guest SMP)
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1/* $Id: HWVMXR0.cpp 19015 2009-04-20 07:54:29Z vboxsync $ */
2/** @file
3 * HWACCM VMX - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/pgm.h>
32#include <VBox/pdm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/selm.h>
36#include <VBox/iom.h>
37#include <VBox/rem.h>
38#include <iprt/param.h>
39#include <iprt/assert.h>
40#include <iprt/asm.h>
41#include <iprt/string.h>
42#include "HWVMXR0.h"
43
44/*******************************************************************************
45* Defined Constants And Macros *
46*******************************************************************************/
47#if defined(RT_ARCH_AMD64)
48# define VMX_IS_64BIT_HOST_MODE() (true)
49#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
50# define VMX_IS_64BIT_HOST_MODE() (g_fVMXIs64bitHost != 0)
51#else
52# define VMX_IS_64BIT_HOST_MODE() (false)
53#endif
54
55/*******************************************************************************
56* Global Variables *
57*******************************************************************************/
58/* IO operation lookup arrays. */
59static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
60static uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
61
62#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
63/** See HWACCMR0A.asm. */
64extern "C" uint32_t g_fVMXIs64bitHost;
65#endif
66
67/*******************************************************************************
68* Local Functions *
69*******************************************************************************/
70static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx);
71static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu);
72static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu);
73static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu);
74static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
75static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
76static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
77#ifdef VBOX_STRICT
78static bool vmxR0IsValidReadField(uint32_t idxField);
79static bool vmxR0IsValidWriteField(uint32_t idxField);
80#endif
81
82static void VMXR0CheckError(PVM pVM, PVMCPU pVCpu, int rc)
83{
84 if (rc == VERR_VMX_GENERIC)
85 {
86 RTCCUINTREG instrError;
87
88 VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
89 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
90 }
91 pVM->hwaccm.s.lLastError = rc;
92}
93
94/**
95 * Sets up and activates VT-x on the current CPU
96 *
97 * @returns VBox status code.
98 * @param pCpu CPU info struct
99 * @param pVM The VM to operate on. (can be NULL after a resume!!)
100 * @param pvPageCpu Pointer to the global cpu page
101 * @param pPageCpuPhys Physical address of the global cpu page
102 */
103VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
104{
105 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
106 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
107
108#ifdef LOG_ENABLED
109 SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
110#endif
111 if (pVM)
112 {
113 /* Set revision dword at the beginning of the VMXON structure. */
114 *(uint32_t *)pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
115 }
116
117 /** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
118 * (which can have very bad consequences!!!)
119 */
120
121 /* Make sure the VMX instructions don't cause #UD faults. */
122 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
123
124 /* Enter VMX Root Mode */
125 int rc = VMXEnable(pPageCpuPhys);
126 if (RT_FAILURE(rc))
127 {
128 if (pVM)
129 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
130 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
131 return VERR_VMX_VMXON_FAILED;
132 }
133 return VINF_SUCCESS;
134}
135
136/**
137 * Deactivates VT-x on the current CPU
138 *
139 * @returns VBox status code.
140 * @param pCpu CPU info struct
141 * @param pvPageCpu Pointer to the global cpu page
142 * @param pPageCpuPhys Physical address of the global cpu page
143 */
144VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
145{
146 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
147 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
148
149 /* Leave VMX Root Mode. */
150 VMXDisable();
151
152 /* And clear the X86_CR4_VMXE bit */
153 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
154
155#ifdef LOG_ENABLED
156 SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
157#endif
158 return VINF_SUCCESS;
159}
160
161/**
162 * Does Ring-0 per VM VT-x init.
163 *
164 * @returns VBox status code.
165 * @param pVM The VM to operate on.
166 */
167VMMR0DECL(int) VMXR0InitVM(PVM pVM)
168{
169 int rc;
170
171#ifdef LOG_ENABLED
172 SUPR0Printf("VMXR0InitVM %x\n", pVM);
173#endif
174
175 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
176
177 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
178 {
179 /* Allocate one page for the virtual APIC mmio cache. */
180 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
181 AssertRC(rc);
182 if (RT_FAILURE(rc))
183 return rc;
184
185 pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
186 pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
187 ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
188 }
189 else
190 {
191 pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
192 pVM->hwaccm.s.vmx.pAPIC = 0;
193 pVM->hwaccm.s.vmx.pAPICPhys = 0;
194 }
195
196 /* Allocate the MSR bitmap if this feature is supported. */
197 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
198 {
199 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
200 AssertRC(rc);
201 if (RT_FAILURE(rc))
202 return rc;
203
204 pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
205 pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
206 memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
207 }
208
209#ifdef VBOX_WITH_CRASHDUMP_MAGIC
210 {
211 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjScratch, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
212 AssertRC(rc);
213 if (RT_FAILURE(rc))
214 return rc;
215
216 pVM->hwaccm.s.vmx.pScratch = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjScratch);
217 pVM->hwaccm.s.vmx.pScratchPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjScratch, 0);
218
219 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
220 strcpy((char *)pVM->hwaccm.s.vmx.pScratch, "SCRATCH Magic");
221 *(uint64_t *)(pVM->hwaccm.s.vmx.pScratch + 16) = UINT64_C(0xDEADBEEFDEADBEEF);
222 }
223#endif
224
225 /* Allocate VMCBs for all guest CPUs. */
226 for (unsigned i=0;i<pVM->cCPUs;i++)
227 {
228 PVMCPU pVCpu = &pVM->aCpus[i];
229
230 pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
231
232 /* Allocate one page for the VM control structure (VMCS). */
233 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
234 AssertRC(rc);
235 if (RT_FAILURE(rc))
236 return rc;
237
238 pVCpu->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVMCS);
239 pVCpu->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVMCS, 0);
240 ASMMemZero32(pVCpu->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
241
242 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
243 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
244
245 /* Current guest paging mode. */
246 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
247
248#ifdef LOG_ENABLED
249 SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVCpu->hwaccm.s.vmx.pVMCS, (uint32_t)pVCpu->hwaccm.s.vmx.pVMCSPhys);
250#endif
251 }
252
253 return VINF_SUCCESS;
254}
255
256/**
257 * Does Ring-0 per VM VT-x termination.
258 *
259 * @returns VBox status code.
260 * @param pVM The VM to operate on.
261 */
262VMMR0DECL(int) VMXR0TermVM(PVM pVM)
263{
264 for (unsigned i=0;i<pVM->cCPUs;i++)
265 {
266 if (pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
267 {
268 RTR0MemObjFree(pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS, false);
269 pVM->aCpus[i].hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
270 pVM->aCpus[i].hwaccm.s.vmx.pVMCS = 0;
271 pVM->aCpus[i].hwaccm.s.vmx.pVMCSPhys = 0;
272 }
273 }
274 if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
275 {
276 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
277 pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
278 pVM->hwaccm.s.vmx.pAPIC = 0;
279 pVM->hwaccm.s.vmx.pAPICPhys = 0;
280 }
281 if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
282 {
283 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
284 pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
285 pVM->hwaccm.s.vmx.pMSRBitmap = 0;
286 pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
287 }
288#ifdef VBOX_WITH_CRASHDUMP_MAGIC
289 if (pVM->hwaccm.s.vmx.pMemObjScratch != NIL_RTR0MEMOBJ)
290 {
291 ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
292 RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjScratch, false);
293 pVM->hwaccm.s.vmx.pMemObjScratch = NIL_RTR0MEMOBJ;
294 pVM->hwaccm.s.vmx.pScratch = 0;
295 pVM->hwaccm.s.vmx.pScratchPhys = 0;
296 }
297#endif
298 return VINF_SUCCESS;
299}
300
301/**
302 * Sets up VT-x for the specified VM
303 *
304 * @returns VBox status code.
305 * @param pVM The VM to operate on.
306 */
307VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
308{
309 int rc = VINF_SUCCESS;
310 uint32_t val;
311
312 AssertReturn(pVM, VERR_INVALID_PARAMETER);
313
314 for (unsigned i=0;i<pVM->cCPUs;i++)
315 {
316 PVMCPU pVCpu = &pVM->aCpus[i];
317
318 Assert(pVCpu->hwaccm.s.vmx.pVMCS);
319
320 /* Set revision dword at the beginning of the VMCS structure. */
321 *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
322
323 /* Clear VM Control Structure. */
324 Log(("pVMCSPhys = %RHp\n", pVCpu->hwaccm.s.vmx.pVMCSPhys));
325 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
326 if (RT_FAILURE(rc))
327 goto vmx_end;
328
329 /* Activate the VM Control Structure. */
330 rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
331 if (RT_FAILURE(rc))
332 goto vmx_end;
333
334 /* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
335 * Set required bits to one and zero according to the MSR capabilities.
336 */
337 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
338 /* External and non-maskable interrupts cause VM-exits. */
339 val = val | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT | VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
340 val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
341
342 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
343 AssertRC(rc);
344
345 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
346 * Set required bits to one and zero according to the MSR capabilities.
347 */
348 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
349 /* Program which event cause VM-exits and which features we want to use. */
350 val = val | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
351 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
352 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
353 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
354 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT
355 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
356
357 /* Without nested paging we should intercept invlpg and cr3 mov instructions. */
358 if (!pVM->hwaccm.s.fNestedPaging)
359 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
360 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
361 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
362
363 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
364 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
365 {
366 /* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
367 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
368 Assert(pVM->hwaccm.s.vmx.pAPIC);
369 }
370 else
371 /* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
372 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
373
374#ifdef VBOX_WITH_VTX_MSR_BITMAPS
375 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
376 {
377 Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
378 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
379 }
380#endif
381
382 /* We will use the secondary control if it's present. */
383 val |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
384
385 /* Mask away the bits that the CPU doesn't support */
386 /** @todo make sure they don't conflict with the above requirements. */
387 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
388 pVCpu->hwaccm.s.vmx.proc_ctls = val;
389
390 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
391 AssertRC(rc);
392
393 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
394 {
395 /* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
396 * Set required bits to one and zero according to the MSR capabilities.
397 */
398 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
399 val |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
400
401#ifdef HWACCM_VTX_WITH_EPT
402 if (pVM->hwaccm.s.fNestedPaging)
403 val |= VMX_VMCS_CTRL_PROC_EXEC2_EPT;
404#endif /* HWACCM_VTX_WITH_EPT */
405#ifdef HWACCM_VTX_WITH_VPID
406 else
407 if (pVM->hwaccm.s.vmx.fVPID)
408 val |= VMX_VMCS_CTRL_PROC_EXEC2_VPID;
409#endif /* HWACCM_VTX_WITH_VPID */
410
411 /* Mask away the bits that the CPU doesn't support */
412 /** @todo make sure they don't conflict with the above requirements. */
413 val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
414
415 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
416 AssertRC(rc);
417 }
418
419 /* VMX_VMCS_CTRL_CR3_TARGET_COUNT
420 * Set required bits to one and zero according to the MSR capabilities.
421 */
422 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
423 AssertRC(rc);
424
425 /* Forward all exception except #NM & #PF to the guest.
426 * We always need to check pagefaults since our shadow page table can be out of sync.
427 * And we always lazily sync the FPU & XMM state.
428 */
429
430 /** @todo Possible optimization:
431 * Keep the FPU and XMM state current in the EM thread. That way there's no need to
432 * lazily sync anything, but the downside is that we can't use the FPU stack or XMM
433 * registers ourselves of course.
434 *
435 * Note: only possible if the current state is actually ours (X86_CR0_TS flag)
436 */
437
438 /* Don't filter page faults; all of them should cause a switch. */
439 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
440 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
441 AssertRC(rc);
442
443 /* Init TSC offset to zero. */
444 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
445 AssertRC(rc);
446
447 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
448 AssertRC(rc);
449
450 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
451 AssertRC(rc);
452
453 /* Set the MSR bitmap address. */
454 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
455 {
456 /* Optional */
457 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
458 AssertRC(rc);
459 }
460
461 /* Clear MSR controls. */
462 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
463 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
464 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
465 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
466 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
467 AssertRC(rc);
468
469 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
470 {
471 Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
472 /* Optional */
473 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
474 rc |= VMXWriteVMCS64(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
475 AssertRC(rc);
476 }
477
478 /* Set link pointer to -1. Not currently used. */
479 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL);
480 AssertRC(rc);
481
482 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
483 rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
484 AssertRC(rc);
485
486 /* Configure the VMCS read cache. */
487 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
488
489 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RIP);
490 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RSP);
491 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RFLAGS);
492 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE);
493 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR0_READ_SHADOW);
494 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR0);
495 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR4_READ_SHADOW);
496 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR4);
497 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_DR7);
498 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_SYSENTER_CS);
499 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_EIP);
500 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_ESP);
501 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_GDTR_LIMIT);
502 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_GDTR_BASE);
503 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_IDTR_LIMIT);
504 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_IDTR_BASE);
505
506 VMX_SETUP_SELREG(ES, pCache);
507 VMX_SETUP_SELREG(SS, pCache);
508 VMX_SETUP_SELREG(CS, pCache);
509 VMX_SETUP_SELREG(DS, pCache);
510 VMX_SETUP_SELREG(FS, pCache);
511 VMX_SETUP_SELREG(GS, pCache);
512 VMX_SETUP_SELREG(LDTR, pCache);
513 VMX_SETUP_SELREG(TR, pCache);
514
515 /* Status code VMCS reads. */
516 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_REASON);
517 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_VM_INSTR_ERROR);
518 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_LENGTH);
519 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE);
520 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO);
521 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_INFO);
522 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
523 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_INFO);
524 VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_ERRCODE);
525
526 if (pVM->hwaccm.s.fNestedPaging)
527 {
528 VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR3);
529 VMXSetupCachedReadVMCS(pCache, VMX_VMCS_EXIT_PHYS_ADDR_FULL);
530 pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
531 }
532 else
533 pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
534 } /* for each VMCPU */
535
536 /* Choose the right TLB setup function. */
537 if (pVM->hwaccm.s.fNestedPaging)
538 {
539 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBEPT;
540
541 /* Default values for flushing. */
542 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
543 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
544
545 /* If the capabilities specify we can do more, then make use of it. */
546 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
547 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
548 else
549 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
550 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
551
552 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
553 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
554 }
555#ifdef HWACCM_VTX_WITH_VPID
556 else
557 if (pVM->hwaccm.s.vmx.fVPID)
558 {
559 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBVPID;
560
561 /* Default values for flushing. */
562 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
563 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
564
565 /* If the capabilities specify we can do more, then make use of it. */
566 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
567 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
568 else
569 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
570 pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
571
572 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
573 pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
574 }
575#endif /* HWACCM_VTX_WITH_VPID */
576 else
577 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBDummy;
578
579vmx_end:
580 VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
581 return rc;
582}
583
584
585/**
586 * Injects an event (trap or external interrupt)
587 *
588 * @returns VBox status code.
589 * @param pVM The VM to operate on.
590 * @param pVCpu The VMCPU to operate on.
591 * @param pCtx CPU Context
592 * @param intInfo VMX interrupt info
593 * @param cbInstr Opcode length of faulting instruction
594 * @param errCode Error code (optional)
595 */
596static int VMXR0InjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
597{
598 int rc;
599 uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
600
601#ifdef VBOX_STRICT
602 if (iGate == 0xE)
603 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
604 else
605 if (iGate < 0x20)
606 LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode));
607 else
608 {
609 LogFlow(("INJ-EI: %x at %RGv\n", iGate, (RTGCPTR)pCtx->rip));
610 Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || !VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
611 Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW || pCtx->eflags.u32 & X86_EFL_IF);
612 }
613#endif
614
615#ifdef HWACCM_VMX_EMULATE_REALMODE
616 if (CPUMIsGuestInRealModeEx(pCtx))
617 {
618 RTGCPHYS GCPhysHandler;
619 uint16_t offset, ip;
620 RTSEL sel;
621
622 /* Injecting events doesn't work right with real mode emulation.
623 * (#GP if we try to inject external hardware interrupts)
624 * Inject the interrupt or trap directly instead.
625 *
626 * ASSUMES no access handlers for the bits we read or write below (should be safe).
627 */
628 Log(("Manual interrupt/trap '%x' inject (real mode)\n", iGate));
629
630 /* Check if the interrupt handler is present. */
631 if (iGate * 4 + 3 > pCtx->idtr.cbIdt)
632 {
633 Log(("IDT cbIdt violation\n"));
634 if (iGate != X86_XCPT_DF)
635 {
636 RTGCUINTPTR intInfo;
637
638 intInfo = (iGate == X86_XCPT_GP) ? (uint32_t)X86_XCPT_DF : iGate;
639 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
640 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
641 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
642
643 return VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0 /* no error code according to the Intel docs */);
644 }
645 Log(("Triple fault -> reset the VM!\n"));
646 return VINF_EM_RESET;
647 }
648 if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
649 || iGate == 3 /* Both #BP and #OF point to the instruction after. */
650 || iGate == 4)
651 {
652 ip = pCtx->ip + cbInstr;
653 }
654 else
655 ip = pCtx->ip;
656
657 /* Read the selector:offset pair of the interrupt handler. */
658 GCPhysHandler = (RTGCPHYS)pCtx->idtr.pIdt + iGate * 4;
659 rc = PGMPhysSimpleReadGCPhys(pVM, &offset, GCPhysHandler, sizeof(offset)); AssertRC(rc);
660 rc = PGMPhysSimpleReadGCPhys(pVM, &sel, GCPhysHandler + 2, sizeof(sel)); AssertRC(rc);
661
662 LogFlow(("IDT handler %04X:%04X\n", sel, offset));
663
664 /* Construct the stack frame. */
665 /** @todo should check stack limit. */
666 pCtx->sp -= 2;
667 LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss, pCtx->sp, pCtx->eflags.u));
668 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t)); AssertRC(rc);
669 pCtx->sp -= 2;
670 LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss, pCtx->sp, pCtx->cs));
671 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t)); AssertRC(rc);
672 pCtx->sp -= 2;
673 LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss, pCtx->sp, ip));
674 rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &ip, sizeof(ip)); AssertRC(rc);
675
676 /* Update the CPU state for executing the handler. */
677 pCtx->rip = offset;
678 pCtx->cs = sel;
679 pCtx->csHid.u64Base = sel << 4;
680 pCtx->eflags.u &= ~(X86_EFL_IF|X86_EFL_TF|X86_EFL_RF|X86_EFL_AC);
681
682 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_SEGMENT_REGS;
683 return VINF_SUCCESS;
684 }
685#endif /* HWACCM_VMX_EMULATE_REALMODE */
686
687 /* Set event injection state. */
688 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo | (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
689
690 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
691 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
692
693 AssertRC(rc);
694 return rc;
695}
696
697
698/**
699 * Checks for pending guest interrupts and injects them
700 *
701 * @returns VBox status code.
702 * @param pVM The VM to operate on.
703 * @param pVCpu The VMCPU to operate on.
704 * @param pCtx CPU Context
705 */
706static int VMXR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, CPUMCTX *pCtx)
707{
708 int rc;
709
710 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
711 if (pVCpu->hwaccm.s.Event.fPending)
712 {
713 Log(("Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
714 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
715 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, pVCpu->hwaccm.s.Event.intInfo, 0, pVCpu->hwaccm.s.Event.errCode);
716 AssertRC(rc);
717
718 pVCpu->hwaccm.s.Event.fPending = false;
719 return VINF_SUCCESS;
720 }
721
722 if (pVM->hwaccm.s.fInjectNMI)
723 {
724 RTGCUINTPTR intInfo;
725
726 intInfo = X86_XCPT_NMI;
727 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
728 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
729
730 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0);
731 AssertRC(rc);
732
733 pVM->hwaccm.s.fInjectNMI = false;
734 return VINF_SUCCESS;
735 }
736
737 /* When external interrupts are pending, we should exit the VM when IF is set. */
738 if ( !TRPMHasTrap(pVCpu)
739 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
740 {
741 if (!(pCtx->eflags.u32 & X86_EFL_IF))
742 {
743 if (!(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
744 {
745 LogFlow(("Enable irq window exit!\n"));
746 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
747 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
748 AssertRC(rc);
749 }
750 /* else nothing to do but wait */
751 }
752 else
753 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
754 {
755 uint8_t u8Interrupt;
756
757 rc = PDMGetInterrupt(pVM, &u8Interrupt);
758 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", u8Interrupt, u8Interrupt, rc, pCtx->cs, (RTGCPTR)pCtx->rip));
759 if (RT_SUCCESS(rc))
760 {
761 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
762 AssertRC(rc);
763 }
764 else
765 {
766 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
767 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
768 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
769 /* Just continue */
770 }
771 }
772 else
773 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS!!\n", (RTGCPTR)pCtx->rip));
774 }
775
776#ifdef VBOX_STRICT
777 if (TRPMHasTrap(pVCpu))
778 {
779 uint8_t u8Vector;
780 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
781 AssertRC(rc);
782 }
783#endif
784
785 if ( pCtx->eflags.u32 & X86_EFL_IF
786 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
787 && TRPMHasTrap(pVCpu)
788 )
789 {
790 uint8_t u8Vector;
791 int rc;
792 TRPMEVENT enmType;
793 RTGCUINTPTR intInfo;
794 RTGCUINT errCode;
795
796 /* If a new event is pending, then dispatch it now. */
797 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &errCode, 0);
798 AssertRC(rc);
799 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
800 Assert(enmType != TRPM_SOFTWARE_INT);
801
802 /* Clear the pending trap. */
803 rc = TRPMResetTrap(pVCpu);
804 AssertRC(rc);
805
806 intInfo = u8Vector;
807 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
808
809 if (enmType == TRPM_TRAP)
810 {
811 switch (u8Vector) {
812 case 8:
813 case 10:
814 case 11:
815 case 12:
816 case 13:
817 case 14:
818 case 17:
819 /* Valid error codes. */
820 intInfo |= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
821 break;
822 default:
823 break;
824 }
825 if (u8Vector == X86_XCPT_BP || u8Vector == X86_XCPT_OF)
826 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
827 else
828 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
829 }
830 else
831 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
832
833 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
834 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, errCode);
835 AssertRC(rc);
836 } /* if (interrupts can be dispatched) */
837
838 return VINF_SUCCESS;
839}
840
841/**
842 * Save the host state
843 *
844 * @returns VBox status code.
845 * @param pVM The VM to operate on.
846 * @param pVCpu The VMCPU to operate on.
847 */
848VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
849{
850 int rc = VINF_SUCCESS;
851
852 /*
853 * Host CPU Context
854 */
855 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
856 {
857 RTIDTR idtr;
858 RTGDTR gdtr;
859 RTSEL SelTR;
860 PX86DESCHC pDesc;
861 uintptr_t trBase;
862 RTSEL cs;
863 RTSEL ss;
864 uint64_t cr3;
865
866 /* Control registers */
867 rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
868#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
869 if (VMX_IS_64BIT_HOST_MODE())
870 {
871 cr3 = hwaccmR0Get64bitCR3();
872 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_CR3, cr3);
873 }
874 else
875#endif
876 {
877 cr3 = ASMGetCR3();
878 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR3, cr3);
879 }
880 rc |= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
881 AssertRC(rc);
882 Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
883 Log2(("VMX_VMCS_HOST_CR3 %08RX64\n", cr3));
884 Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
885
886 /* Selector registers. */
887#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
888 if (VMX_IS_64BIT_HOST_MODE())
889 {
890 cs = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelCS;
891 ss = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelSS;
892 }
893 else
894 {
895 /* sysenter loads LDT cs & ss, VMX doesn't like this. Load the GDT ones (safe). */
896 cs = (RTSEL)(uintptr_t)&SUPR0AbsKernelCS;
897 ss = (RTSEL)(uintptr_t)&SUPR0AbsKernelSS;
898 }
899#else
900 cs = ASMGetCS();
901 ss = ASMGetSS();
902#endif
903 Assert(!(cs & X86_SEL_LDT)); Assert((cs & X86_SEL_RPL) == 0);
904 Assert(!(ss & X86_SEL_LDT)); Assert((ss & X86_SEL_RPL) == 0);
905 rc = VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_CS, cs);
906 /* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
907 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_DS, 0);
908 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_ES, 0);
909#if HC_ARCH_BITS == 32
910 if (!VMX_IS_64BIT_HOST_MODE())
911 {
912 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_FS, 0);
913 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_GS, 0);
914 }
915#endif
916 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_SS, ss);
917 SelTR = ASMGetTR();
918 rc |= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_TR, SelTR);
919 AssertRC(rc);
920 Log2(("VMX_VMCS_HOST_FIELD_CS %08x (%08x)\n", cs, ASMGetSS()));
921 Log2(("VMX_VMCS_HOST_FIELD_DS 00000000 (%08x)\n", ASMGetDS()));
922 Log2(("VMX_VMCS_HOST_FIELD_ES 00000000 (%08x)\n", ASMGetES()));
923 Log2(("VMX_VMCS_HOST_FIELD_FS 00000000 (%08x)\n", ASMGetFS()));
924 Log2(("VMX_VMCS_HOST_FIELD_GS 00000000 (%08x)\n", ASMGetGS()));
925 Log2(("VMX_VMCS_HOST_FIELD_SS %08x (%08x)\n", ss, ASMGetSS()));
926 Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
927
928 /* GDTR & IDTR */
929#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
930 if (VMX_IS_64BIT_HOST_MODE())
931 {
932 X86XDTR64 gdtr64, idtr64;
933 hwaccmR0Get64bitGDTRandIDTR(&gdtr64, &idtr64);
934 rc = VMXWriteVMCS64(VMX_VMCS_HOST_GDTR_BASE, gdtr64.uAddr);
935 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_IDTR_BASE, gdtr64.uAddr);
936 AssertRC(rc);
937 Log2(("VMX_VMCS_HOST_GDTR_BASE %RX64\n", gdtr64.uAddr));
938 Log2(("VMX_VMCS_HOST_IDTR_BASE %RX64\n", idtr64.uAddr));
939 gdtr.cbGdt = gdtr64.cb;
940 gdtr.pGdt = (uintptr_t)gdtr64.uAddr;
941 }
942 else
943#endif
944 {
945 ASMGetGDTR(&gdtr);
946 rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
947 ASMGetIDTR(&idtr);
948 rc |= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
949 AssertRC(rc);
950 Log2(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", gdtr.pGdt));
951 Log2(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", idtr.pIdt));
952 }
953
954
955 /* Save the base address of the TR selector. */
956 if (SelTR > gdtr.cbGdt)
957 {
958 AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
959 return VERR_VMX_INVALID_HOST_STATE;
960 }
961
962#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
963 if (VMX_IS_64BIT_HOST_MODE())
964 {
965 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC]; /// ????
966 uint64_t trBase64 = X86DESC64_BASE(*(PX86DESC64)pDesc);
967 rc = VMXWriteVMCS64(VMX_VMCS_HOST_TR_BASE, trBase64);
968 Log2(("VMX_VMCS_HOST_TR_BASE %RX64\n", trBase64));
969 AssertRC(rc);
970 }
971 else
972#endif
973 {
974 pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
975#if HC_ARCH_BITS == 64
976 trBase = X86DESC64_BASE(*pDesc);
977#else
978 trBase = X86DESC_BASE(*pDesc);
979#endif
980 rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
981 AssertRC(rc);
982 Log2(("VMX_VMCS_HOST_TR_BASE %RHv\n", trBase));
983 }
984
985 /* FS and GS base. */
986#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
987 if (VMX_IS_64BIT_HOST_MODE())
988 {
989 Log2(("MSR_K8_FS_BASE = %RX64\n", ASMRdMsr(MSR_K8_FS_BASE)));
990 Log2(("MSR_K8_GS_BASE = %RX64\n", ASMRdMsr(MSR_K8_GS_BASE)));
991 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
992 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
993 }
994#endif
995 AssertRC(rc);
996
997 /* Sysenter MSRs. */
998 /** @todo expensive!! */
999 rc = VMXWriteVMCS(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
1000 Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
1001#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1002 if (VMX_IS_64BIT_HOST_MODE())
1003 {
1004 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1005 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1006 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1007 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1008 }
1009 else
1010 {
1011 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1012 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1013 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1014 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1015 }
1016#elif HC_ARCH_BITS == 32
1017 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1018 rc |= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1019 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1020 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1021#else
1022 Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1023 Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1024 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1025 rc |= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1026#endif
1027 AssertRC(rc);
1028
1029#if 0 /* @todo deal with 32/64 */
1030 /* Restore the host EFER - on CPUs that support it. */
1031 if (pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1 & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1032 {
1033 uint64_t msrEFER = ASMRdMsr(MSR_IA32_EFER);
1034 rc = VMXWriteVMCS64(VMX_VMCS_HOST_FIELD_EFER_FULL, msrEFER);
1035 AssertRC(rc);
1036 }
1037#endif
1038 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
1039 }
1040 return rc;
1041}
1042
1043/**
1044 * Prefetch the 4 PDPT pointers (PAE and nested paging only)
1045 *
1046 * @param pVM The VM to operate on.
1047 * @param pVCpu The VMCPU to operate on.
1048 * @param pCtx Guest context
1049 */
1050static void vmxR0PrefetchPAEPdptrs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1051{
1052 if (CPUMIsGuestInPAEModeEx(pCtx))
1053 {
1054 X86PDPE Pdpe;
1055
1056 for (unsigned i=0;i<4;i++)
1057 {
1058 Pdpe = PGMGstGetPaePDPtr(pVCpu, i);
1059 int rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR0_FULL + i*2, Pdpe.u);
1060 AssertRC(rc);
1061 }
1062 }
1063}
1064
1065/**
1066 * Update the exception bitmap according to the current CPU state
1067 *
1068 * @param pVM The VM to operate on.
1069 * @param pVCpu The VMCPU to operate on.
1070 * @param pCtx Guest context
1071 */
1072static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1073{
1074 uint32_t u32TrapMask;
1075 Assert(pCtx);
1076
1077 u32TrapMask = HWACCM_VMX_TRAP_MASK;
1078#ifndef DEBUG
1079 if (pVM->hwaccm.s.fNestedPaging)
1080 u32TrapMask &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
1081#endif
1082
1083 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
1084 if ( CPUMIsGuestFPUStateActive(pVCpu) == true
1085 && !(pCtx->cr0 & X86_CR0_NE)
1086 && !pVCpu->hwaccm.s.fFPUOldStyleOverride)
1087 {
1088 u32TrapMask |= RT_BIT(X86_XCPT_MF);
1089 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
1090 }
1091
1092#ifdef DEBUG /* till after branching, enable it by default then. */
1093 /* Intercept X86_XCPT_DB if stepping is enabled */
1094 if (DBGFIsStepping(pVM))
1095 u32TrapMask |= RT_BIT(X86_XCPT_DB);
1096 /** @todo Don't trap it unless the debugger has armed breakpoints. */
1097 u32TrapMask |= RT_BIT(X86_XCPT_BP);
1098#endif
1099
1100#ifdef VBOX_STRICT
1101 Assert(u32TrapMask & RT_BIT(X86_XCPT_GP));
1102#endif
1103
1104# ifdef HWACCM_VMX_EMULATE_REALMODE
1105 /* Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise). */
1106 if (CPUMIsGuestInRealModeEx(pCtx) && pVM->hwaccm.s.vmx.pRealModeTSS)
1107 u32TrapMask |= HWACCM_VMX_TRAP_MASK_REALMODE;
1108# endif /* HWACCM_VMX_EMULATE_REALMODE */
1109
1110 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, u32TrapMask);
1111 AssertRC(rc);
1112}
1113
1114/**
1115 * Loads the guest state
1116 *
1117 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
1118 *
1119 * @returns VBox status code.
1120 * @param pVM The VM to operate on.
1121 * @param pVCpu The VMCPU to operate on.
1122 * @param pCtx Guest context
1123 */
1124VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1125{
1126 int rc = VINF_SUCCESS;
1127 RTGCUINTPTR val;
1128 X86EFLAGS eflags;
1129
1130 /* VMX_VMCS_CTRL_ENTRY_CONTROLS
1131 * Set required bits to one and zero according to the MSR capabilities.
1132 */
1133 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1134 /* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1135 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
1136#if 0 /* @todo deal with 32/64 */
1137 /* Required for the EFER write below, not supported on all CPUs. */
1138 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR;
1139#endif
1140 /* 64 bits guest mode? */
1141 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1142 val |= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1143 /* else Must be zero when AMD64 is not available. */
1144
1145 /* Mask away the bits that the CPU doesn't support */
1146 val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1147 rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1148 AssertRC(rc);
1149
1150 /* VMX_VMCS_CTRL_EXIT_CONTROLS
1151 * Set required bits to one and zero according to the MSR capabilities.
1152 */
1153 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
1154
1155 /* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1156#if 0 /* @todo deal with 32/64 */
1157 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG | VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR;
1158#else
1159 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
1160#endif
1161
1162#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1163 if (VMX_IS_64BIT_HOST_MODE())
1164 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
1165 /* else: Must be zero when AMD64 is not available. */
1166#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1167 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1168 val |= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64; /* our switcher goes to long mode */
1169 else
1170 Assert(!(val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64));
1171#endif
1172 val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
1173 /* Don't acknowledge external interrupts on VM-exit. */
1174 rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
1175 AssertRC(rc);
1176
1177 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1178 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
1179 {
1180#ifdef HWACCM_VMX_EMULATE_REALMODE
1181 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1182 {
1183 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
1184 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode != enmGuestMode)
1185 {
1186 /* Correct weird requirements for switching to protected mode. */
1187 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1188 && enmGuestMode >= PGMMODE_PROTECTED)
1189 {
1190 /* Flush the recompiler code cache as it's not unlikely
1191 * the guest will rewrite code it will later execute in real
1192 * mode (OpenBSD 4.0 is one such example)
1193 */
1194 REMFlushTBs(pVM);
1195
1196 /* DPL of all hidden selector registers must match the current CPL (0). */
1197 pCtx->csHid.Attr.n.u2Dpl = 0;
1198 pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE | X86_SEL_TYPE_RW_ACC;
1199
1200 pCtx->dsHid.Attr.n.u2Dpl = 0;
1201 pCtx->esHid.Attr.n.u2Dpl = 0;
1202 pCtx->fsHid.Attr.n.u2Dpl = 0;
1203 pCtx->gsHid.Attr.n.u2Dpl = 0;
1204 pCtx->ssHid.Attr.n.u2Dpl = 0;
1205
1206 /* The limit must correspond to the granularity bit. */
1207 if (!pCtx->csHid.Attr.n.u1Granularity)
1208 pCtx->csHid.u32Limit &= 0xffff;
1209 if (!pCtx->dsHid.Attr.n.u1Granularity)
1210 pCtx->dsHid.u32Limit &= 0xffff;
1211 if (!pCtx->esHid.Attr.n.u1Granularity)
1212 pCtx->esHid.u32Limit &= 0xffff;
1213 if (!pCtx->fsHid.Attr.n.u1Granularity)
1214 pCtx->fsHid.u32Limit &= 0xffff;
1215 if (!pCtx->gsHid.Attr.n.u1Granularity)
1216 pCtx->gsHid.u32Limit &= 0xffff;
1217 if (!pCtx->ssHid.Attr.n.u1Granularity)
1218 pCtx->ssHid.u32Limit &= 0xffff;
1219 }
1220 else
1221 /* Switching from protected mode to real mode. */
1222 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode >= PGMMODE_PROTECTED
1223 && enmGuestMode == PGMMODE_REAL)
1224 {
1225 /* The limit must also be set to 0xffff. */
1226 pCtx->csHid.u32Limit = 0xffff;
1227 pCtx->dsHid.u32Limit = 0xffff;
1228 pCtx->esHid.u32Limit = 0xffff;
1229 pCtx->fsHid.u32Limit = 0xffff;
1230 pCtx->gsHid.u32Limit = 0xffff;
1231 pCtx->ssHid.u32Limit = 0xffff;
1232
1233 Assert(pCtx->csHid.u64Base <= 0xfffff);
1234 Assert(pCtx->dsHid.u64Base <= 0xfffff);
1235 Assert(pCtx->esHid.u64Base <= 0xfffff);
1236 Assert(pCtx->fsHid.u64Base <= 0xfffff);
1237 Assert(pCtx->gsHid.u64Base <= 0xfffff);
1238 }
1239 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = enmGuestMode;
1240 }
1241 else
1242 /* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
1243 if ( CPUMIsGuestInRealModeEx(pCtx)
1244 && pCtx->csHid.u64Base == 0xffff0000)
1245 {
1246 pCtx->csHid.u64Base = 0xf0000;
1247 pCtx->cs = 0xf000;
1248 }
1249 }
1250#endif /* HWACCM_VMX_EMULATE_REALMODE */
1251
1252 VMX_WRITE_SELREG(ES, es);
1253 AssertRC(rc);
1254
1255 VMX_WRITE_SELREG(CS, cs);
1256 AssertRC(rc);
1257
1258 VMX_WRITE_SELREG(SS, ss);
1259 AssertRC(rc);
1260
1261 VMX_WRITE_SELREG(DS, ds);
1262 AssertRC(rc);
1263
1264 /* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
1265 VMX_WRITE_SELREG(FS, fs);
1266 AssertRC(rc);
1267
1268 VMX_WRITE_SELREG(GS, gs);
1269 AssertRC(rc);
1270 }
1271
1272 /* Guest CPU context: LDTR. */
1273 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
1274 {
1275 if (pCtx->ldtr == 0)
1276 {
1277 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, 0);
1278 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, 0);
1279 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, 0);
1280 /* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
1281 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
1282 }
1283 else
1284 {
1285 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, pCtx->ldtr);
1286 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
1287 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
1288 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
1289 }
1290 AssertRC(rc);
1291 }
1292 /* Guest CPU context: TR. */
1293 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
1294 {
1295#ifdef HWACCM_VMX_EMULATE_REALMODE
1296 /* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1297 if (CPUMIsGuestInRealModeEx(pCtx))
1298 {
1299 RTGCPHYS GCPhys;
1300
1301 /* We convert it here every time as pci regions could be reconfigured. */
1302 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1303 AssertRC(rc);
1304
1305 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, 0);
1306 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, HWACCM_VTX_TSS_SIZE);
1307 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
1308
1309 X86DESCATTR attr;
1310
1311 attr.u = 0;
1312 attr.n.u1Present = 1;
1313 attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1314 val = attr.u;
1315 }
1316 else
1317#endif /* HWACCM_VMX_EMULATE_REALMODE */
1318 {
1319 rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, pCtx->tr);
1320 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
1321 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, pCtx->trHid.u64Base);
1322
1323 val = pCtx->trHid.Attr.u;
1324
1325 /* The TSS selector must be busy. */
1326 if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
1327 val = (val & ~0xF) | X86_SEL_TYPE_SYS_286_TSS_BUSY;
1328 else
1329 /* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
1330 val = (val & ~0xF) | X86_SEL_TYPE_SYS_386_TSS_BUSY;
1331
1332 }
1333 rc |= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, val);
1334 AssertRC(rc);
1335 }
1336 /* Guest CPU context: GDTR. */
1337 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
1338 {
1339 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
1340 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
1341 AssertRC(rc);
1342 }
1343 /* Guest CPU context: IDTR. */
1344 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
1345 {
1346 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
1347 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
1348 AssertRC(rc);
1349 }
1350
1351 /*
1352 * Sysenter MSRs (unconditional)
1353 */
1354 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
1355 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
1356 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
1357 AssertRC(rc);
1358
1359 /* Control registers */
1360 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
1361 {
1362 val = pCtx->cr0;
1363 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
1364 Log2(("Guest CR0-shadow %08x\n", val));
1365 if (CPUMIsGuestFPUStateActive(pVCpu) == false)
1366 {
1367 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
1368 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
1369 }
1370 else
1371 {
1372 /** @todo check if we support the old style mess correctly. */
1373 if (!(val & X86_CR0_NE))
1374 Log(("Forcing X86_CR0_NE!!!\n"));
1375
1376 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
1377 }
1378 /* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
1379 val |= X86_CR0_PE | X86_CR0_PG;
1380 if (pVM->hwaccm.s.fNestedPaging)
1381 {
1382 if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
1383 {
1384 /* Disable cr3 read/write monitoring as we don't need it for EPT. */
1385 pVCpu->hwaccm.s.vmx.proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1386 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
1387 }
1388 else
1389 {
1390 /* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
1391 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1392 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1393 }
1394 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1395 AssertRC(rc);
1396 }
1397 else
1398 {
1399 /* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
1400 val |= X86_CR0_WP;
1401 }
1402
1403 /* Always enable caching. */
1404 val &= ~(X86_CR0_CD|X86_CR0_NW);
1405
1406 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR0, val);
1407 Log2(("Guest CR0 %08x\n", val));
1408 /* CR0 flags owned by the host; if the guests attempts to change them, then
1409 * the VM will exit.
1410 */
1411 val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
1412 | X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
1413 | X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
1414 | X86_CR0_TS
1415 | X86_CR0_ET /* Bit not restored during VM-exit! */
1416 | X86_CR0_CD /* Bit not restored during VM-exit! */
1417 | X86_CR0_NW /* Bit not restored during VM-exit! */
1418 | X86_CR0_NE
1419 | X86_CR0_MP;
1420 pVCpu->hwaccm.s.vmx.cr0_mask = val;
1421
1422 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
1423 Log2(("Guest CR0-mask %08x\n", val));
1424 AssertRC(rc);
1425 }
1426 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
1427 {
1428 /* CR4 */
1429 rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
1430 Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
1431 /* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
1432 val = pCtx->cr4 | (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1433
1434 if (!pVM->hwaccm.s.fNestedPaging)
1435 {
1436 switch(pVCpu->hwaccm.s.enmShadowMode)
1437 {
1438 case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
1439 case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
1440 case PGMMODE_32_BIT: /* 32-bit paging. */
1441 val &= ~X86_CR4_PAE;
1442 break;
1443
1444 case PGMMODE_PAE: /* PAE paging. */
1445 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1446 /** @todo use normal 32 bits paging */
1447 val |= X86_CR4_PAE;
1448 break;
1449
1450 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1451 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1452#ifdef VBOX_ENABLE_64_BITS_GUESTS
1453 break;
1454#else
1455 AssertFailed();
1456 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1457#endif
1458 default: /* shut up gcc */
1459 AssertFailed();
1460 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1461 }
1462 }
1463 else
1464 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1465 {
1466 /* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
1467 val |= X86_CR4_PSE;
1468 /* Our identity mapping is a 32 bits page directory. */
1469 val &= ~X86_CR4_PAE;
1470 }
1471
1472 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR4, val);
1473 Log2(("Guest CR4 %08x\n", val));
1474 /* CR4 flags owned by the host; if the guests attempts to change them, then
1475 * the VM will exit.
1476 */
1477 val = 0
1478 | X86_CR4_PAE
1479 | X86_CR4_PGE
1480 | X86_CR4_PSE
1481 | X86_CR4_VMXE;
1482 pVCpu->hwaccm.s.vmx.cr4_mask = val;
1483
1484 rc |= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
1485 Log2(("Guest CR4-mask %08x\n", val));
1486 AssertRC(rc);
1487 }
1488
1489 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
1490 {
1491 if (pVM->hwaccm.s.fNestedPaging)
1492 {
1493 Assert(PGMGetHyperCR3(pVCpu));
1494 pVCpu->hwaccm.s.vmx.GCPhysEPTP = PGMGetHyperCR3(pVCpu);
1495
1496 Assert(!(pVCpu->hwaccm.s.vmx.GCPhysEPTP & 0xfff));
1497 /** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
1498 pVCpu->hwaccm.s.vmx.GCPhysEPTP |= VMX_EPT_MEMTYPE_WB
1499 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
1500
1501 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_EPTP_FULL, pVCpu->hwaccm.s.vmx.GCPhysEPTP);
1502 AssertRC(rc);
1503
1504 if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1505 {
1506 RTGCPHYS GCPhys;
1507
1508 /* We convert it here every time as pci regions could be reconfigured. */
1509 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1510 AssertRC(rc);
1511
1512 /* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
1513 * take care of the translation to host physical addresses.
1514 */
1515 val = GCPhys;
1516 }
1517 else
1518 {
1519 /* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
1520 val = pCtx->cr3;
1521 /* Prefetch the four PDPT entries in PAE mode. */
1522 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1523 }
1524 }
1525 else
1526 {
1527 val = PGMGetHyperCR3(pVCpu);
1528 Assert(val || VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL));
1529 }
1530
1531 /* Save our shadow CR3 register. */
1532 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_CR3, val);
1533 AssertRC(rc);
1534 }
1535
1536 /* Debug registers. */
1537 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
1538 {
1539 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
1540 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
1541
1542 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1543 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
1544 pCtx->dr[7] |= 0x400; /* must be one */
1545
1546 /* Resync DR7 */
1547 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
1548 AssertRC(rc);
1549
1550 /* Sync the debug state now if any breakpoint is armed. */
1551 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
1552 && !CPUMIsGuestDebugStateActive(pVCpu)
1553 && !DBGFIsStepping(pVM))
1554 {
1555 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
1556
1557 /* Disable drx move intercepts. */
1558 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
1559 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1560 AssertRC(rc);
1561
1562 /* Save the host and load the guest debug state. */
1563 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1564 AssertRC(rc);
1565 }
1566
1567 /* IA32_DEBUGCTL MSR. */
1568 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1569 AssertRC(rc);
1570
1571 /** @todo do we really ever need this? */
1572 rc |= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1573 AssertRC(rc);
1574 }
1575
1576 /* EIP, ESP and EFLAGS */
1577 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_RIP, pCtx->rip);
1578 rc |= VMXWriteVMCS64(VMX_VMCS64_GUEST_RSP, pCtx->rsp);
1579 AssertRC(rc);
1580
1581 /* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1582 eflags = pCtx->eflags;
1583 eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1584 eflags.u32 |= VMX_EFLAGS_RESERVED_1;
1585
1586#ifdef HWACCM_VMX_EMULATE_REALMODE
1587 /* Real mode emulation using v86 mode. */
1588 if (CPUMIsGuestInRealModeEx(pCtx))
1589 {
1590 pVCpu->hwaccm.s.vmx.RealMode.eflags = eflags;
1591
1592 eflags.Bits.u1VM = 1;
1593 eflags.Bits.u2IOPL = 0; /* must always be 0 or else certain instructions won't cause faults. */
1594 }
1595#endif /* HWACCM_VMX_EMULATE_REALMODE */
1596 rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1597 AssertRC(rc);
1598
1599 /* TSC offset. */
1600 uint64_t u64TSCOffset;
1601
1602 if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
1603 {
1604 /* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1605 rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1606 AssertRC(rc);
1607
1608 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1609 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1610 AssertRC(rc);
1611 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
1612 }
1613 else
1614 {
1615 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1616 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1617 AssertRC(rc);
1618 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
1619 }
1620
1621 /* 64 bits guest mode? */
1622 if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1623 {
1624#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
1625 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1626#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1627 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
1628#else
1629# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1630 if (!pVM->hwaccm.s.fAllow64BitGuests)
1631 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1632# endif
1633 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1634#endif
1635 /* Unconditionally update these as wrmsr might have changed them. */
1636 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1637 AssertRC(rc);
1638 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1639 AssertRC(rc);
1640 }
1641 else
1642 {
1643 pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1644 }
1645
1646#if 0 /* @todo deal with 32/64 */
1647 /* Unconditionally update the guest EFER - on CPUs that supports it. */
1648 if (pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1 & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
1649 {
1650 rc = VMXWriteVMCS64(VMX_VMCS_GUEST_EFER_FULL, pCtx->msrEFER);
1651 AssertRC(rc);
1652 }
1653#endif
1654
1655 vmxR0UpdateExceptionBitmap(pVM, pVCpu, pCtx);
1656
1657 /* Done. */
1658 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1659
1660 return rc;
1661}
1662
1663/**
1664 * Syncs back the guest state
1665 *
1666 * @returns VBox status code.
1667 * @param pVM The VM to operate on.
1668 * @param pVCpu The VMCPU to operate on.
1669 * @param pCtx Guest context
1670 */
1671DECLINLINE(int) VMXR0SaveGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1672{
1673 RTGCUINTREG val, valShadow;
1674 RTGCUINTPTR uInterruptState;
1675 int rc;
1676
1677 /* Let's first sync back eip, esp, and eflags. */
1678 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RIP, &val);
1679 AssertRC(rc);
1680 pCtx->rip = val;
1681 rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RSP, &val);
1682 AssertRC(rc);
1683 pCtx->rsp = val;
1684 rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1685 AssertRC(rc);
1686 pCtx->eflags.u32 = val;
1687
1688 /* Take care of instruction fusing (sti, mov ss) */
1689 rc |= VMXReadCachedVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &val);
1690 uInterruptState = val;
1691 if (uInterruptState != 0)
1692 {
1693 Assert(uInterruptState <= 2); /* only sti & mov ss */
1694 Log(("uInterruptState %x eip=%RGv\n", uInterruptState, pCtx->rip));
1695 EMSetInhibitInterruptsPC(pVM, pVCpu, pCtx->rip);
1696 }
1697 else
1698 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1699
1700 /* Control registers. */
1701 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1702 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR0, &val);
1703 val = (valShadow & pVCpu->hwaccm.s.vmx.cr0_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr0_mask);
1704 CPUMSetGuestCR0(pVCpu, val);
1705
1706 VMXReadCachedVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1707 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR4, &val);
1708 val = (valShadow & pVCpu->hwaccm.s.vmx.cr4_mask) | (val & ~pVCpu->hwaccm.s.vmx.cr4_mask);
1709 CPUMSetGuestCR4(pVCpu, val);
1710
1711 /* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
1712 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1713 if ( pVM->hwaccm.s.fNestedPaging
1714 && CPUMIsGuestInPagedProtectedModeEx(pCtx))
1715 {
1716 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1717
1718 /* Can be updated behind our back in the nested paging case. */
1719 CPUMSetGuestCR2(pVCpu, pCache->cr2);
1720
1721 VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR3, &val);
1722
1723 if (val != pCtx->cr3)
1724 {
1725 CPUMSetGuestCR3(pVCpu, val);
1726 PGMUpdateCR3(pVCpu, val);
1727 }
1728 /* Prefetch the four PDPT entries in PAE mode. */
1729 vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1730 }
1731
1732 /* Sync back DR7 here. */
1733 VMXReadCachedVMCS(VMX_VMCS64_GUEST_DR7, &val);
1734 pCtx->dr[7] = val;
1735
1736 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1737 VMX_READ_SELREG(ES, es);
1738 VMX_READ_SELREG(SS, ss);
1739 VMX_READ_SELREG(CS, cs);
1740 VMX_READ_SELREG(DS, ds);
1741 VMX_READ_SELREG(FS, fs);
1742 VMX_READ_SELREG(GS, gs);
1743
1744 /*
1745 * System MSRs
1746 */
1747 VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, &val);
1748 pCtx->SysEnter.cs = val;
1749 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_EIP, &val);
1750 pCtx->SysEnter.eip = val;
1751 VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_ESP, &val);
1752 pCtx->SysEnter.esp = val;
1753
1754 /* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1755 VMX_READ_SELREG(LDTR, ldtr);
1756
1757 VMXReadCachedVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, &val);
1758 pCtx->gdtr.cbGdt = val;
1759 VMXReadCachedVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
1760 pCtx->gdtr.pGdt = val;
1761
1762 VMXReadCachedVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, &val);
1763 pCtx->idtr.cbIdt = val;
1764 VMXReadCachedVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
1765 pCtx->idtr.pIdt = val;
1766
1767#ifdef HWACCM_VMX_EMULATE_REALMODE
1768 /* Real mode emulation using v86 mode. */
1769 if (CPUMIsGuestInRealModeEx(pCtx))
1770 {
1771 /* Hide our emulation flags */
1772 pCtx->eflags.Bits.u1VM = 0;
1773
1774 /* Restore original IOPL setting as we always use 0. */
1775 pCtx->eflags.Bits.u2IOPL = pVCpu->hwaccm.s.vmx.RealMode.eflags.Bits.u2IOPL;
1776
1777 /* Force a TR resync every time in case we switch modes. */
1778 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_TR;
1779 }
1780 else
1781#endif /* HWACCM_VMX_EMULATE_REALMODE */
1782 {
1783 /* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
1784 VMX_READ_SELREG(TR, tr);
1785 }
1786 return VINF_SUCCESS;
1787}
1788
1789/**
1790 * Dummy placeholder
1791 *
1792 * @param pVM The VM to operate on.
1793 * @param pVCpu The VMCPU to operate on.
1794 */
1795static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu)
1796{
1797 NOREF(pVM);
1798 NOREF(pVCpu);
1799 return;
1800}
1801
1802/**
1803 * Setup the tagged TLB for EPT
1804 *
1805 * @returns VBox status code.
1806 * @param pVM The VM to operate on.
1807 * @param pVCpu The VMCPU to operate on.
1808 */
1809static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu)
1810{
1811 PHWACCM_CPUINFO pCpu;
1812
1813 Assert(pVM->hwaccm.s.fNestedPaging);
1814 Assert(!pVM->hwaccm.s.vmx.fVPID);
1815
1816 /* Deal with tagged TLBs if VPID or EPT is supported. */
1817 pCpu = HWACCMR0GetCurrentCpu();
1818 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1819 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1820 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1821 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1822 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1823 {
1824 /* Force a TLB flush on VM entry. */
1825 pVCpu->hwaccm.s.fForceTLBFlush = true;
1826 }
1827 else
1828 Assert(!pCpu->fFlushTLB);
1829
1830 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1831 pCpu->fFlushTLB = false;
1832
1833 if (pVCpu->hwaccm.s.fForceTLBFlush)
1834 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1835
1836#ifdef VBOX_WITH_STATISTICS
1837 if (pVCpu->hwaccm.s.fForceTLBFlush)
1838 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1839 else
1840 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1841#endif
1842}
1843
1844#ifdef HWACCM_VTX_WITH_VPID
1845/**
1846 * Setup the tagged TLB for VPID
1847 *
1848 * @returns VBox status code.
1849 * @param pVM The VM to operate on.
1850 * @param pVCpu The VMCPU to operate on.
1851 */
1852static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu)
1853{
1854 PHWACCM_CPUINFO pCpu;
1855
1856 Assert(pVM->hwaccm.s.vmx.fVPID);
1857 Assert(!pVM->hwaccm.s.fNestedPaging);
1858
1859 /* Deal with tagged TLBs if VPID or EPT is supported. */
1860 pCpu = HWACCMR0GetCurrentCpu();
1861 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1862 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1863 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1864 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1865 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1866 {
1867 /* Force a TLB flush on VM entry. */
1868 pVCpu->hwaccm.s.fForceTLBFlush = true;
1869 }
1870 else
1871 Assert(!pCpu->fFlushTLB);
1872
1873 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1874
1875 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1876 if (pVCpu->hwaccm.s.fForceTLBFlush)
1877 {
1878 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1879 || pCpu->fFlushTLB)
1880 {
1881 pCpu->fFlushTLB = false;
1882 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1883 pCpu->cTLBFlushes++;
1884 }
1885 else
1886 {
1887 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1888 pVCpu->hwaccm.s.fForceTLBFlush = false;
1889 }
1890
1891 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1892 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1893 }
1894 else
1895 {
1896 Assert(!pCpu->fFlushTLB);
1897
1898 if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)
1899 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1900 }
1901 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1902 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1903 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1904
1905 int rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hwaccm.s.uCurrentASID);
1906 AssertRC(rc);
1907
1908 if (pVCpu->hwaccm.s.fForceTLBFlush)
1909 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1910
1911#ifdef VBOX_WITH_STATISTICS
1912 if (pVCpu->hwaccm.s.fForceTLBFlush)
1913 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1914 else
1915 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1916#endif
1917}
1918#endif /* HWACCM_VTX_WITH_VPID */
1919
1920/**
1921 * Runs guest code in a VT-x VM.
1922 *
1923 * @returns VBox status code.
1924 * @param pVM The VM to operate on.
1925 * @param pVCpu The VMCPU to operate on.
1926 * @param pCtx Guest context
1927 */
1928VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1929{
1930 int rc = VINF_SUCCESS;
1931 RTGCUINTREG val;
1932 RTGCUINTREG exitReason = VMX_EXIT_INVALID;
1933 RTGCUINTREG instrError, cbInstr;
1934 RTGCUINTPTR exitQualification;
1935 RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1936 RTGCUINTPTR errCode, instrInfo;
1937 bool fSyncTPR = false;
1938 PHWACCM_CPUINFO pCpu = 0;
1939 unsigned cResume = 0;
1940#ifdef VBOX_STRICT
1941 RTCPUID idCpuCheck;
1942#endif
1943#ifdef VBOX_WITH_STATISTICS
1944 bool fStatEntryStarted = true;
1945 bool fStatExit2Started = false;
1946#endif
1947
1948 Log2(("\nE"));
1949
1950 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
1951
1952#ifdef VBOX_STRICT
1953 {
1954 RTCCUINTREG val;
1955
1956 rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1957 AssertRC(rc);
1958 Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1959
1960 /* allowed zero */
1961 if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1962 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1963
1964 /* allowed one */
1965 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1966 Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1967
1968 rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1969 AssertRC(rc);
1970 Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1971
1972 /* Must be set according to the MSR, but can be cleared in case of EPT. */
1973 if (pVM->hwaccm.s.fNestedPaging)
1974 val |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
1975 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1976 | VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1977
1978 /* allowed zero */
1979 if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
1980 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1981
1982 /* allowed one */
1983 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
1984 Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1985
1986 rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1987 AssertRC(rc);
1988 Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1989
1990 /* allowed zero */
1991 if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
1992 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1993
1994 /* allowed one */
1995 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
1996 Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1997
1998 rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1999 AssertRC(rc);
2000 Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
2001
2002 /* allowed zero */
2003 if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
2004 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
2005
2006 /* allowed one */
2007 if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
2008 Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
2009 }
2010#endif
2011
2012#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2013 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeEntry = RTTimeNanoTS();
2014#endif
2015
2016 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
2017 */
2018ResumeExecution:
2019 STAM_STATS({
2020 if (fStatExit2Started) { STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = false; }
2021 if (!fStatEntryStarted) { STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = true; }
2022 });
2023 AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == RTMpCpuId(),
2024 ("Expected %d, I'm %d; cResume=%d exitReason=%RGv exitQualification=%RGv\n",
2025 (int)pVCpu->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
2026 Assert(!HWACCMR0SuspendPending());
2027
2028 /* Safety precaution; looping for too long here can have a very bad effect on the host */
2029 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
2030 {
2031 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
2032 rc = VINF_EM_RAW_INTERRUPT;
2033 goto end;
2034 }
2035
2036 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
2037 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
2038 {
2039 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVM, pVCpu)));
2040 if (pCtx->rip != EMGetInhibitInterruptsPC(pVM, pVCpu))
2041 {
2042 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
2043 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
2044 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
2045 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
2046 */
2047 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
2048 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2049 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2050 AssertRC(rc);
2051 }
2052 }
2053 else
2054 {
2055 /* Irq inhibition is no longer active; clear the corresponding VMX state. */
2056 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2057 AssertRC(rc);
2058 }
2059
2060 /* Check for pending actions that force us to go back to ring 3. */
2061 if (VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK))
2062 {
2063 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
2064 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
2065 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2066 goto end;
2067 }
2068 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
2069 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
2070 {
2071 rc = VINF_EM_PENDING_REQUEST;
2072 goto end;
2073 }
2074
2075 /* When external interrupts are pending, we should exit the VM when IF is set. */
2076 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
2077 rc = VMXR0CheckPendingInterrupt(pVM, pVCpu, pCtx);
2078 if (RT_FAILURE(rc))
2079 goto end;
2080
2081 /** @todo check timers?? */
2082
2083 /* TPR caching using CR8 is only available in 64 bits mode */
2084 /* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
2085 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
2086 /**
2087 * @todo reduce overhead
2088 */
2089 if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
2090 && pVM->hwaccm.s.vmx.pAPIC)
2091 {
2092 /* TPR caching in CR8 */
2093 uint8_t u8TPR;
2094 bool fPending;
2095
2096 int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
2097 AssertRC(rc);
2098 /* The TPR can be found at offset 0x80 in the APIC mmio page. */
2099 pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
2100
2101 /* Two options here:
2102 * - external interrupt pending, but masked by the TPR value.
2103 * -> a CR8 update that lower the current TPR value should cause an exit
2104 * - no pending interrupts
2105 * -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
2106 */
2107 rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
2108 AssertRC(rc);
2109
2110 /* Always sync back the TPR; we should optimize this though */ /** @todo optimize TPR sync. */
2111 fSyncTPR = true;
2112 }
2113
2114#if defined(HWACCM_VTX_WITH_EPT) && defined(LOG_ENABLED)
2115 if ( pVM->hwaccm.s.fNestedPaging
2116# ifdef HWACCM_VTX_WITH_VPID
2117 || pVM->hwaccm.s.vmx.fVPID
2118# endif /* HWACCM_VTX_WITH_VPID */
2119 )
2120 {
2121 pCpu = HWACCMR0GetCurrentCpu();
2122 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
2123 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
2124 {
2125 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
2126 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
2127 else
2128 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
2129 }
2130 if (pCpu->fFlushTLB)
2131 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
2132 else
2133 if (pVCpu->hwaccm.s.fForceTLBFlush)
2134 LogFlow(("Manual TLB flush\n"));
2135 }
2136#endif
2137#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2138 PGMDynMapFlushAutoSet(pVCpu);
2139#endif
2140
2141 /*
2142 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
2143 * (until the actual world switch)
2144 */
2145#ifdef VBOX_STRICT
2146 idCpuCheck = RTMpCpuId();
2147#endif
2148#ifdef LOG_LOGGING
2149 VMMR0LogFlushDisable(pVCpu);
2150#endif
2151 /* Save the host state first. */
2152 rc = VMXR0SaveHostState(pVM, pVCpu);
2153 if (rc != VINF_SUCCESS)
2154 goto end;
2155 /* Load the guest state */
2156 rc = VMXR0LoadGuestState(pVM, pVCpu, pCtx);
2157 if (rc != VINF_SUCCESS)
2158 goto end;
2159
2160 /* Deal with tagged TLB setup and invalidation. */
2161 pVM->hwaccm.s.vmx.pfnSetupTaggedTLB(pVM, pVCpu);
2162
2163 /* Non-register state Guest Context */
2164 /** @todo change me according to cpu state */
2165 rc = VMXWriteVMCS(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
2166 AssertRC(rc);
2167
2168 STAM_STATS({ STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = false; });
2169
2170 /* Manual save and restore:
2171 * - General purpose registers except RIP, RSP
2172 *
2173 * Trashed:
2174 * - CR2 (we don't care)
2175 * - LDTR (reset to 0)
2176 * - DRx (presumably not changed at all)
2177 * - DR7 (reset to 0x400)
2178 * - EFLAGS (reset to RT_BIT(1); not relevant)
2179 *
2180 */
2181
2182
2183 /* All done! Let's start VM execution. */
2184 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, z);
2185#ifdef VBOX_STRICT
2186 Assert(idCpuCheck == RTMpCpuId());
2187#endif
2188
2189#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2190 pVCpu->hwaccm.s.vmx.VMCSCache.cResume = cResume;
2191 pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeSwitch = RTTimeNanoTS();
2192#endif
2193
2194 TMNotifyStartOfExecution(pVM);
2195 rc = pVCpu->hwaccm.s.vmx.pfnStartVM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu);
2196 TMNotifyEndOfExecution(pVM);
2197
2198 AssertMsg(!pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries, ("pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries=%d\n", pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries));
2199
2200 /* In case we execute a goto ResumeExecution later on. */
2201 pVCpu->hwaccm.s.fResumeVM = true;
2202 pVCpu->hwaccm.s.fForceTLBFlush = false;
2203
2204 /*
2205 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2206 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
2207 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2208 */
2209 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, z);
2210 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, v);
2211
2212 if (rc != VINF_SUCCESS)
2213 {
2214 VMXR0ReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
2215 goto end;
2216 }
2217
2218 /* Success. Query the guest state and figure out what has happened. */
2219
2220 /* Investigate why there was a VM-exit. */
2221 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
2222 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
2223
2224 exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
2225 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
2226 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr);
2227 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo);
2228 /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
2229 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode);
2230 rc |= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo);
2231 rc |= VMXReadCachedVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification);
2232 AssertRC(rc);
2233
2234 /* Sync back the guest state */
2235 rc = VMXR0SaveGuestState(pVM, pVCpu, pCtx);
2236 AssertRC(rc);
2237
2238 /* Note! NOW IT'S SAFE FOR LOGGING! */
2239#ifdef LOG_LOGGING
2240 VMMR0LogFlushEnable(pVCpu);
2241#endif
2242 Log2(("Raw exit reason %08x\n", exitReason));
2243
2244 /* Check if an injected event was interrupted prematurely. */
2245 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_INFO, &val);
2246 AssertRC(rc);
2247 pVCpu->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
2248 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2249 /* Ignore 'int xx' as they'll be restarted anyway. */
2250 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
2251 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2252 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2253 {
2254 pVCpu->hwaccm.s.Event.fPending = true;
2255 /* Error code present? */
2256 if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hwaccm.s.Event.intInfo))
2257 {
2258 rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_ERRCODE, &val);
2259 AssertRC(rc);
2260 pVCpu->hwaccm.s.Event.errCode = val;
2261 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
2262 }
2263 else
2264 {
2265 Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2266 pVCpu->hwaccm.s.Event.errCode = 0;
2267 }
2268 }
2269#ifdef VBOX_STRICT
2270 else
2271 if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2272 /* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2273 && VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2274 {
2275 Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2276 }
2277
2278 if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
2279 HWACCMDumpRegs(pVM, pVCpu, pCtx);
2280#endif
2281
2282 Log2(("E%d: New EIP=%RGv\n", exitReason, (RTGCPTR)pCtx->rip));
2283 Log2(("Exit reason %d, exitQualification %RGv\n", (uint32_t)exitReason, exitQualification));
2284 Log2(("instrInfo=%d instrError=%d instr length=%d\n", (uint32_t)instrInfo, (uint32_t)instrError, (uint32_t)cbInstr));
2285 Log2(("Interruption error code %d\n", (uint32_t)errCode));
2286 Log2(("IntInfo = %08x\n", (uint32_t)intInfo));
2287
2288 if (fSyncTPR)
2289 {
2290 rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
2291 AssertRC(rc);
2292 }
2293
2294 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, v);
2295 STAM_STATS({ STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = true; });
2296
2297 /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
2298 switch (exitReason)
2299 {
2300 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2301 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2302 {
2303 uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
2304
2305 if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2306 {
2307 Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
2308 /* External interrupt; leave to allow it to be dispatched again. */
2309 rc = VINF_EM_RAW_INTERRUPT;
2310 break;
2311 }
2312 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2313 switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
2314 {
2315 case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
2316 /* External interrupt; leave to allow it to be dispatched again. */
2317 rc = VINF_EM_RAW_INTERRUPT;
2318 break;
2319
2320 case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
2321 AssertFailed(); /* can't come here; fails the first check. */
2322 break;
2323
2324 case VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT: /* Unknown why we get this type for #DB */
2325 case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
2326 Assert(vector == 1 || vector == 3 || vector == 4);
2327 /* no break */
2328 case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
2329 Log2(("Hardware/software interrupt %d\n", vector));
2330 switch (vector)
2331 {
2332 case X86_XCPT_NM:
2333 {
2334 Log(("#NM fault at %RGv error code %x\n", (RTGCPTR)pCtx->rip, errCode));
2335
2336 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
2337 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
2338 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
2339 if (rc == VINF_SUCCESS)
2340 {
2341 Assert(CPUMIsGuestFPUStateActive(pVCpu));
2342
2343 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
2344
2345 /* Continue execution. */
2346 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2347
2348 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2349 goto ResumeExecution;
2350 }
2351
2352 Log(("Forward #NM fault to the guest\n"));
2353 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
2354 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
2355 AssertRC(rc);
2356 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2357 goto ResumeExecution;
2358 }
2359
2360 case X86_XCPT_PF: /* Page fault */
2361 {
2362#ifdef DEBUG
2363 if (pVM->hwaccm.s.fNestedPaging)
2364 { /* A genuine pagefault.
2365 * Forward the trap to the guest by injecting the exception and resuming execution.
2366 */
2367 Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
2368
2369 Assert(CPUMIsGuestInPagedProtectedModeEx(pCtx));
2370
2371 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2372
2373 /* Now we must update CR2. */
2374 pCtx->cr2 = exitQualification;
2375 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2376 AssertRC(rc);
2377
2378 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2379 goto ResumeExecution;
2380 }
2381#endif
2382 Assert(!pVM->hwaccm.s.fNestedPaging);
2383
2384 Log2(("Page fault at %RGv error code %x\n", exitQualification, errCode));
2385 /* Exit qualification contains the linear address of the page fault. */
2386 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
2387 TRPMSetErrorCode(pVCpu, errCode);
2388 TRPMSetFaultAddress(pVCpu, exitQualification);
2389
2390 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
2391 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
2392 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2393 if (rc == VINF_SUCCESS)
2394 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2395 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, exitQualification ,errCode));
2396 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
2397
2398 TRPMResetTrap(pVCpu);
2399
2400 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2401 goto ResumeExecution;
2402 }
2403 else
2404 if (rc == VINF_EM_RAW_GUEST_TRAP)
2405 { /* A genuine pagefault.
2406 * Forward the trap to the guest by injecting the exception and resuming execution.
2407 */
2408 Log2(("Forward page fault to the guest\n"));
2409
2410 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2411 /* The error code might have been changed. */
2412 errCode = TRPMGetErrorCode(pVCpu);
2413
2414 TRPMResetTrap(pVCpu);
2415
2416 /* Now we must update CR2. */
2417 pCtx->cr2 = exitQualification;
2418 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2419 AssertRC(rc);
2420
2421 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2422 goto ResumeExecution;
2423 }
2424#ifdef VBOX_STRICT
2425 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
2426 Log2(("PGMTrap0eHandler failed with %d\n", rc));
2427#endif
2428 /* Need to go back to the recompiler to emulate the instruction. */
2429 TRPMResetTrap(pVCpu);
2430 break;
2431 }
2432
2433 case X86_XCPT_MF: /* Floating point exception. */
2434 {
2435 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
2436 if (!(pCtx->cr0 & X86_CR0_NE))
2437 {
2438 /* old style FPU error reporting needs some extra work. */
2439 /** @todo don't fall back to the recompiler, but do it manually. */
2440 rc = VINF_EM_RAW_EMULATE_INSTR;
2441 break;
2442 }
2443 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2444 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2445 AssertRC(rc);
2446
2447 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2448 goto ResumeExecution;
2449 }
2450
2451 case X86_XCPT_DB: /* Debug exception. */
2452 {
2453 uint64_t uDR6;
2454
2455 /* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
2456 *
2457 * Exit qualification bits:
2458 * 3:0 B0-B3 which breakpoint condition was met
2459 * 12:4 Reserved (0)
2460 * 13 BD - debug register access detected
2461 * 14 BS - single step execution or branch taken
2462 * 63:15 Reserved (0)
2463 */
2464 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
2465
2466 /* Note that we don't support guest and host-initiated debugging at the same time. */
2467 Assert(DBGFIsStepping(pVM) || CPUMIsGuestInRealModeEx(pCtx));
2468
2469 uDR6 = X86_DR6_INIT_VAL;
2470 uDR6 |= (exitQualification & (X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3|X86_DR6_BD|X86_DR6_BS));
2471 rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), uDR6);
2472 if (rc == VINF_EM_RAW_GUEST_TRAP)
2473 {
2474 /** @todo this isn't working, but we'll never get here normally. */
2475
2476 /* Update DR6 here. */
2477 pCtx->dr[6] = uDR6;
2478
2479 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2480 pCtx->dr[7] &= ~X86_DR7_GD;
2481
2482 /* Paranoia. */
2483 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2484 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2485 pCtx->dr[7] |= 0x400; /* must be one */
2486
2487 /* Resync DR7 */
2488 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
2489 AssertRC(rc);
2490
2491 Log(("Trap %x (debug) at %RGv exit qualification %RX64\n", vector, (RTGCPTR)pCtx->rip, exitQualification));
2492 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2493 AssertRC(rc);
2494
2495 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2496 goto ResumeExecution;
2497 }
2498 /* Return to ring 3 to deal with the debug exit code. */
2499 break;
2500 }
2501
2502#ifdef DEBUG /* till after branching, enable by default after that. */
2503 case X86_XCPT_BP: /* Breakpoint. */
2504 {
2505 rc = DBGFR0Trap03Handler(pVM, CPUMCTX2CORE(pCtx));
2506 if (rc == VINF_EM_RAW_GUEST_TRAP)
2507 {
2508 Log(("Guest #BP at %04x:%RGv\n", pCtx->cs, pCtx->rip));
2509 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2510 AssertRC(rc);
2511 goto ResumeExecution;
2512 }
2513 if (rc == VINF_SUCCESS)
2514 goto ResumeExecution;
2515 Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
2516 break;
2517 }
2518#endif
2519
2520 case X86_XCPT_GP: /* General protection failure exception.*/
2521 {
2522 uint32_t cbOp;
2523 uint32_t cbSize;
2524 DISCPUSTATE Cpu;
2525
2526 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
2527#ifdef VBOX_STRICT
2528 if (!CPUMIsGuestInRealModeEx(pCtx))
2529 {
2530 Log(("Trap %x at %04X:%RGv errorCode=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, errCode));
2531 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2532 AssertRC(rc);
2533 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2534 goto ResumeExecution;
2535 }
2536#endif
2537 Assert(CPUMIsGuestInRealModeEx(pCtx));
2538
2539 LogFlow(("Real mode X86_XCPT_GP instruction emulation at %RGv\n", (RTGCPTR)pCtx->rip));
2540
2541 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
2542 if (RT_SUCCESS(rc))
2543 {
2544 bool fUpdateRIP = true;
2545
2546 Assert(cbOp == Cpu.opsize);
2547 switch (Cpu.pCurInstr->opcode)
2548 {
2549 case OP_CLI:
2550 pCtx->eflags.Bits.u1IF = 0;
2551 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCli);
2552 break;
2553
2554 case OP_STI:
2555 pCtx->eflags.Bits.u1IF = 1;
2556 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitSti);
2557 break;
2558
2559 case OP_HLT:
2560 fUpdateRIP = false;
2561 rc = VINF_EM_HALT;
2562 pCtx->rip += Cpu.opsize;
2563 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2564 break;
2565
2566 case OP_POPF:
2567 {
2568 RTGCPTR GCPtrStack;
2569 uint32_t cbParm;
2570 uint32_t uMask;
2571 X86EFLAGS eflags;
2572
2573 if (Cpu.prefix & PREFIX_OPSIZE)
2574 {
2575 cbParm = 4;
2576 uMask = 0xffffffff;
2577 }
2578 else
2579 {
2580 cbParm = 2;
2581 uMask = 0xffff;
2582 }
2583
2584 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
2585 if (RT_FAILURE(rc))
2586 {
2587 rc = VERR_EM_INTERPRETER;
2588 break;
2589 }
2590 eflags.u = 0;
2591 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
2592 if (RT_FAILURE(rc))
2593 {
2594 rc = VERR_EM_INTERPRETER;
2595 break;
2596 }
2597 LogFlow(("POPF %x -> %RGv mask=%x\n", eflags.u, pCtx->rsp, uMask));
2598 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (eflags.u & X86_EFL_POPF_BITS & uMask);
2599 /* RF cleared when popped in real mode; see pushf description in AMD manual. */
2600 pCtx->eflags.Bits.u1RF = 0;
2601 pCtx->esp += cbParm;
2602 pCtx->esp &= uMask;
2603
2604 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPopf);
2605 break;
2606 }
2607
2608 case OP_PUSHF:
2609 {
2610 RTGCPTR GCPtrStack;
2611 uint32_t cbParm;
2612 uint32_t uMask;
2613 X86EFLAGS eflags;
2614
2615 if (Cpu.prefix & PREFIX_OPSIZE)
2616 {
2617 cbParm = 4;
2618 uMask = 0xffffffff;
2619 }
2620 else
2621 {
2622 cbParm = 2;
2623 uMask = 0xffff;
2624 }
2625
2626 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0, &GCPtrStack);
2627 if (RT_FAILURE(rc))
2628 {
2629 rc = VERR_EM_INTERPRETER;
2630 break;
2631 }
2632 eflags = pCtx->eflags;
2633 /* RF & VM cleared when pushed in real mode; see pushf description in AMD manual. */
2634 eflags.Bits.u1RF = 0;
2635 eflags.Bits.u1VM = 0;
2636
2637 rc = PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
2638 if (RT_FAILURE(rc))
2639 {
2640 rc = VERR_EM_INTERPRETER;
2641 break;
2642 }
2643 LogFlow(("PUSHF %x -> %RGv\n", eflags.u, GCPtrStack));
2644 pCtx->esp -= cbParm;
2645 pCtx->esp &= uMask;
2646 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPushf);
2647 break;
2648 }
2649
2650 case OP_IRET:
2651 {
2652 RTGCPTR GCPtrStack;
2653 uint32_t uMask = 0xffff;
2654 uint16_t aIretFrame[3];
2655
2656 if (Cpu.prefix & (PREFIX_OPSIZE | PREFIX_ADDRSIZE))
2657 {
2658 rc = VERR_EM_INTERPRETER;
2659 break;
2660 }
2661
2662 rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
2663 if (RT_FAILURE(rc))
2664 {
2665 rc = VERR_EM_INTERPRETER;
2666 break;
2667 }
2668 rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame));
2669 if (RT_FAILURE(rc))
2670 {
2671 rc = VERR_EM_INTERPRETER;
2672 break;
2673 }
2674 pCtx->ip = aIretFrame[0];
2675 pCtx->cs = aIretFrame[1];
2676 pCtx->csHid.u64Base = pCtx->cs << 4;
2677 pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) | (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
2678 pCtx->sp += sizeof(aIretFrame);
2679
2680 LogFlow(("iret to %04x:%x\n", pCtx->cs, pCtx->ip));
2681 fUpdateRIP = false;
2682 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIret);
2683 break;
2684 }
2685
2686 case OP_INT:
2687 {
2688 RTGCUINTPTR intInfo;
2689
2690 LogFlow(("Realmode: INT %x\n", Cpu.param1.parval & 0xff));
2691 intInfo = Cpu.param1.parval & 0xff;
2692 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2693 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2694
2695 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2696 AssertRC(rc);
2697 fUpdateRIP = false;
2698 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2699 break;
2700 }
2701
2702 case OP_INTO:
2703 {
2704 if (pCtx->eflags.Bits.u1OF)
2705 {
2706 RTGCUINTPTR intInfo;
2707
2708 LogFlow(("Realmode: INTO\n"));
2709 intInfo = X86_XCPT_OF;
2710 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2711 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2712
2713 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2714 AssertRC(rc);
2715 fUpdateRIP = false;
2716 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2717 }
2718 break;
2719 }
2720
2721 case OP_INT3:
2722 {
2723 RTGCUINTPTR intInfo;
2724
2725 LogFlow(("Realmode: INT 3\n"));
2726 intInfo = 3;
2727 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2728 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2729
2730 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2731 AssertRC(rc);
2732 fUpdateRIP = false;
2733 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2734 break;
2735 }
2736
2737 default:
2738 rc = EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2739 break;
2740 }
2741
2742 if (rc == VINF_SUCCESS)
2743 {
2744 if (fUpdateRIP)
2745 pCtx->rip += cbOp; /* Move on to the next instruction. */
2746
2747 /* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
2748 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2749
2750 /* Only resume if successful. */
2751 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2752 goto ResumeExecution;
2753 }
2754 }
2755 else
2756 rc = VERR_EM_INTERPRETER;
2757
2758 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_EM_HALT, ("Unexpected rc=%Rrc\n", rc));
2759 break;
2760 }
2761
2762#ifdef VBOX_STRICT
2763 case X86_XCPT_DE: /* Divide error. */
2764 case X86_XCPT_UD: /* Unknown opcode exception. */
2765 case X86_XCPT_SS: /* Stack segment exception. */
2766 case X86_XCPT_NP: /* Segment not present exception. */
2767 {
2768 switch(vector)
2769 {
2770 case X86_XCPT_DE:
2771 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
2772 break;
2773 case X86_XCPT_UD:
2774 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
2775 break;
2776 case X86_XCPT_SS:
2777 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
2778 break;
2779 case X86_XCPT_NP:
2780 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
2781 break;
2782 }
2783
2784 Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2785 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2786 AssertRC(rc);
2787
2788 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2789 goto ResumeExecution;
2790 }
2791#endif
2792 default:
2793#ifdef HWACCM_VMX_EMULATE_REALMODE
2794 if (CPUMIsGuestInRealModeEx(pCtx))
2795 {
2796 Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs, pCtx->eip, errCode));
2797 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2798 AssertRC(rc);
2799
2800 /* Go back to ring 3 in case of a triple fault. */
2801 if ( vector == X86_XCPT_DF
2802 && rc == VINF_EM_RESET)
2803 break;
2804
2805 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2806 goto ResumeExecution;
2807 }
2808#endif
2809 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
2810 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
2811 break;
2812 } /* switch (vector) */
2813
2814 break;
2815
2816 default:
2817 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
2818 AssertMsgFailed(("Unexpected interuption code %x\n", intInfo));
2819 break;
2820 }
2821
2822 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2823 break;
2824 }
2825
2826 case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
2827 {
2828 RTGCPHYS GCPhys;
2829
2830 Assert(pVM->hwaccm.s.fNestedPaging);
2831
2832 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
2833 AssertRC(rc);
2834 Assert(((exitQualification >> 7) & 3) != 2);
2835
2836 /* Determine the kind of violation. */
2837 errCode = 0;
2838 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
2839 errCode |= X86_TRAP_PF_ID;
2840
2841 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
2842 errCode |= X86_TRAP_PF_RW;
2843
2844 /* If the page is present, then it's a page level protection fault. */
2845 if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
2846 errCode |= X86_TRAP_PF_P;
2847
2848 Log(("EPT Page fault %x at %RGp error code %x\n", (uint32_t)exitQualification, GCPhys, errCode));
2849
2850 /* GCPhys contains the guest physical address of the page fault. */
2851 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
2852 TRPMSetErrorCode(pVCpu, errCode);
2853 TRPMSetFaultAddress(pVCpu, GCPhys);
2854
2855 /* Handle the pagefault trap for the nested shadow table. */
2856 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys);
2857 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2858 if (rc == VINF_SUCCESS)
2859 { /* We've successfully synced our shadow pages, so let's just continue execution. */
2860 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, exitQualification , errCode));
2861 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
2862
2863 TRPMResetTrap(pVCpu);
2864
2865 goto ResumeExecution;
2866 }
2867
2868#ifdef VBOX_STRICT
2869 if (rc != VINF_EM_RAW_EMULATE_INSTR)
2870 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
2871#endif
2872 /* Need to go back to the recompiler to emulate the instruction. */
2873 TRPMResetTrap(pVCpu);
2874 break;
2875 }
2876
2877 case VMX_EXIT_EPT_MISCONFIG:
2878 {
2879 RTGCPHYS GCPhys;
2880
2881 Assert(pVM->hwaccm.s.fNestedPaging);
2882
2883 rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
2884 AssertRC(rc);
2885
2886 Log(("VMX_EXIT_EPT_MISCONFIG for %VGp\n", GCPhys));
2887 break;
2888 }
2889
2890 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2891 /* Clear VM-exit on IF=1 change. */
2892 LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip, VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
2893 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
2894 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
2895 AssertRC(rc);
2896 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIrqWindow);
2897 goto ResumeExecution; /* we check for pending guest interrupts there */
2898
2899 case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
2900 case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
2901 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
2902 /* Skip instruction and continue directly. */
2903 pCtx->rip += cbInstr;
2904 /* Continue execution.*/
2905 goto ResumeExecution;
2906
2907 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2908 {
2909 Log2(("VMX: Cpuid %x\n", pCtx->eax));
2910 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
2911 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2912 if (rc == VINF_SUCCESS)
2913 {
2914 /* Update EIP and continue execution. */
2915 Assert(cbInstr == 2);
2916 pCtx->rip += cbInstr;
2917 goto ResumeExecution;
2918 }
2919 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
2920 rc = VINF_EM_RAW_EMULATE_INSTR;
2921 break;
2922 }
2923
2924 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
2925 {
2926 Log2(("VMX: Rdpmc %x\n", pCtx->ecx));
2927 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
2928 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2929 if (rc == VINF_SUCCESS)
2930 {
2931 /* Update EIP and continue execution. */
2932 Assert(cbInstr == 2);
2933 pCtx->rip += cbInstr;
2934 goto ResumeExecution;
2935 }
2936 rc = VINF_EM_RAW_EMULATE_INSTR;
2937 break;
2938 }
2939
2940 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2941 {
2942 Log2(("VMX: Rdtsc\n"));
2943 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
2944 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2945 if (rc == VINF_SUCCESS)
2946 {
2947 /* Update EIP and continue execution. */
2948 Assert(cbInstr == 2);
2949 pCtx->rip += cbInstr;
2950 goto ResumeExecution;
2951 }
2952 rc = VINF_EM_RAW_EMULATE_INSTR;
2953 break;
2954 }
2955
2956 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2957 {
2958 Log2(("VMX: invlpg\n"));
2959 Assert(!pVM->hwaccm.s.fNestedPaging);
2960
2961 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
2962 rc = EMInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), exitQualification);
2963 if (rc == VINF_SUCCESS)
2964 {
2965 /* Update EIP and continue execution. */
2966 pCtx->rip += cbInstr;
2967 goto ResumeExecution;
2968 }
2969 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %RGv failed with %Rrc\n", exitQualification, rc));
2970 break;
2971 }
2972
2973 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2974 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2975 {
2976 uint32_t cbSize;
2977
2978 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2979 Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
2980 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2981 if (rc == VINF_SUCCESS)
2982 {
2983 /* EIP has been updated already. */
2984
2985 /* Only resume if successful. */
2986 goto ResumeExecution;
2987 }
2988 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
2989 break;
2990 }
2991
2992 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2993 {
2994 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
2995
2996 switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
2997 {
2998 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
2999 Log2(("VMX: %RGv mov cr%d, x\n", (RTGCPTR)pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
3000 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3001 rc = EMInterpretCRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3002 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
3003 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
3004
3005 switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
3006 {
3007 case 0:
3008 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0 | HWACCM_CHANGED_GUEST_CR3;
3009 break;
3010 case 2:
3011 break;
3012 case 3:
3013 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx));
3014 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
3015 break;
3016 case 4:
3017 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
3018 break;
3019 case 8:
3020 /* CR8 contains the APIC TPR */
3021 Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3022 break;
3023
3024 default:
3025 AssertFailed();
3026 break;
3027 }
3028 /* Check if a sync operation is pending. */
3029 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
3030 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
3031 {
3032 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
3033 AssertRC(rc);
3034 }
3035 break;
3036
3037 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
3038 Log2(("VMX: mov x, crx\n"));
3039 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3040
3041 Assert(!pVM->hwaccm.s.fNestedPaging || !CPUMIsGuestInPagedProtectedModeEx(pCtx) || VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
3042
3043 /* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
3044 Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 || !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3045
3046 rc = EMInterpretCRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3047 VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
3048 VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
3049 break;
3050
3051 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
3052 Log2(("VMX: clts\n"));
3053 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCLTS);
3054 rc = EMInterpretCLTS(pVM, pVCpu);
3055 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
3056 break;
3057
3058 case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
3059 Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
3060 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitLMSW);
3061 rc = EMInterpretLMSW(pVM, pVCpu, CPUMCTX2CORE(pCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
3062 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
3063 break;
3064 }
3065
3066 /* Update EIP if no error occurred. */
3067 if (RT_SUCCESS(rc))
3068 pCtx->rip += cbInstr;
3069
3070 if (rc == VINF_SUCCESS)
3071 {
3072 /* Only resume if successful. */
3073 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3074 goto ResumeExecution;
3075 }
3076 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
3077 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3078 break;
3079 }
3080
3081 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3082 {
3083 if (!DBGFIsStepping(pVM))
3084 {
3085 /* Disable drx move intercepts. */
3086 pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3087 rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3088 AssertRC(rc);
3089
3090 /* Save the host and load the guest debug state. */
3091 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
3092 AssertRC(rc);
3093
3094#ifdef VBOX_WITH_STATISTICS
3095 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
3096 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3097 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3098 else
3099 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3100#endif
3101
3102 goto ResumeExecution;
3103 }
3104
3105 /** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
3106 if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3107 {
3108 Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
3109 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3110 rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3111 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
3112 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
3113 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3114 Log2(("DR7=%08x\n", pCtx->dr[7]));
3115 }
3116 else
3117 {
3118 Log2(("VMX: mov x, drx\n"));
3119 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3120 rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3121 VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
3122 VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
3123 }
3124 /* Update EIP if no error occurred. */
3125 if (RT_SUCCESS(rc))
3126 pCtx->rip += cbInstr;
3127
3128 if (rc == VINF_SUCCESS)
3129 {
3130 /* Only resume if successful. */
3131 goto ResumeExecution;
3132 }
3133 Assert(rc == VERR_EM_INTERPRETER);
3134 break;
3135 }
3136
3137 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
3138 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3139 {
3140 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3141 uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
3142 uint32_t uPort;
3143 bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
3144
3145 /** @todo necessary to make the distinction? */
3146 if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
3147 {
3148 uPort = pCtx->edx & 0xffff;
3149 }
3150 else
3151 uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
3152
3153 /* paranoia */
3154 if (RT_UNLIKELY(uIOWidth == 2 || uIOWidth >= 4))
3155 {
3156 rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
3157 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3158 break;
3159 }
3160
3161 uint32_t cbSize = g_aIOSize[uIOWidth];
3162
3163 if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
3164 {
3165 /* ins/outs */
3166 DISCPUSTATE Cpu;
3167
3168 /* Disassemble manually to deal with segment prefixes. */
3169 /** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */
3170 /** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */
3171 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), &Cpu, NULL);
3172 if (rc == VINF_SUCCESS)
3173 {
3174 if (fIOWrite)
3175 {
3176 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3177 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
3178 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, Cpu.prefix, cbSize);
3179 }
3180 else
3181 {
3182 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3183 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
3184 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, Cpu.prefix, cbSize);
3185 }
3186 }
3187 else
3188 rc = VINF_EM_RAW_EMULATE_INSTR;
3189 }
3190 else
3191 {
3192 /* normal in/out */
3193 uint32_t uAndVal = g_aIOOpAnd[uIOWidth];
3194
3195 Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
3196
3197 if (fIOWrite)
3198 {
3199 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
3200 rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
3201 }
3202 else
3203 {
3204 uint32_t u32Val = 0;
3205
3206 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
3207 rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
3208 if (IOM_SUCCESS(rc))
3209 {
3210 /* Write back to the EAX register. */
3211 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
3212 }
3213 }
3214 }
3215 /*
3216 * Handled the I/O return codes.
3217 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
3218 */
3219 if (IOM_SUCCESS(rc))
3220 {
3221 /* Update EIP and continue execution. */
3222 pCtx->rip += cbInstr;
3223 if (RT_LIKELY(rc == VINF_SUCCESS))
3224 {
3225 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
3226 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
3227 {
3228 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
3229 for (unsigned i=0;i<4;i++)
3230 {
3231 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
3232
3233 if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
3234 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
3235 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
3236 {
3237 uint64_t uDR6;
3238
3239 Assert(CPUMIsGuestDebugStateActive(pVCpu));
3240
3241 uDR6 = ASMGetDR6();
3242
3243 /* Clear all breakpoint status flags and set the one we just hit. */
3244 uDR6 &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
3245 uDR6 |= (uint64_t)RT_BIT(i);
3246
3247 /* Note: AMD64 Architecture Programmer's Manual 13.1:
3248 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
3249 * the contents have been read.
3250 */
3251 ASMSetDR6(uDR6);
3252
3253 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
3254 pCtx->dr[7] &= ~X86_DR7_GD;
3255
3256 /* Paranoia. */
3257 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
3258 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
3259 pCtx->dr[7] |= 0x400; /* must be one */
3260
3261 /* Resync DR7 */
3262 rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
3263 AssertRC(rc);
3264
3265 /* Construct inject info. */
3266 intInfo = X86_XCPT_DB;
3267 intInfo |= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
3268 intInfo |= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
3269
3270 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
3271 rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
3272 AssertRC(rc);
3273
3274 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3275 goto ResumeExecution;
3276 }
3277 }
3278 }
3279
3280 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3281 goto ResumeExecution;
3282 }
3283 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3284 break;
3285 }
3286
3287#ifdef VBOX_STRICT
3288 if (rc == VINF_IOM_HC_IOPORT_READ)
3289 Assert(!fIOWrite);
3290 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
3291 Assert(fIOWrite);
3292 else
3293 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
3294#endif
3295 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3296 break;
3297 }
3298
3299 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3300 LogFlow(("VMX_EXIT_TPR\n"));
3301 /* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
3302 goto ResumeExecution;
3303
3304 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3305 goto ResumeExecution;
3306
3307 default:
3308 /* The rest is handled after syncing the entire CPU state. */
3309 break;
3310 }
3311
3312 /* Note: the guest state isn't entirely synced back at this stage. */
3313
3314 /* Investigate why there was a VM-exit. (part 2) */
3315 switch (exitReason)
3316 {
3317 case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
3318 case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
3319 case VMX_EXIT_EPT_VIOLATION:
3320 case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3321 /* Already handled above. */
3322 break;
3323
3324 case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
3325 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
3326 break;
3327
3328 case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
3329 case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
3330 rc = VINF_EM_RAW_INTERRUPT;
3331 AssertFailed(); /* Can't happen. Yet. */
3332 break;
3333
3334 case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
3335 case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
3336 rc = VINF_EM_RAW_INTERRUPT;
3337 AssertFailed(); /* Can't happen afaik. */
3338 break;
3339
3340 case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
3341 rc = VERR_EM_INTERPRETER;
3342 break;
3343
3344 case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
3345 /** Check if external interrupts are pending; if so, don't switch back. */
3346 pCtx->rip++; /* skip hlt */
3347 if ( pCtx->eflags.Bits.u1IF
3348 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
3349 goto ResumeExecution;
3350
3351 rc = VINF_EM_HALT;
3352 break;
3353
3354 case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
3355 AssertFailed(); /* can't happen. */
3356 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3357 break;
3358
3359 case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
3360 case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
3361 case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
3362 case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
3363 case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
3364 case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
3365 case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
3366 case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
3367 case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
3368 case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
3369 /** @todo inject #UD immediately */
3370 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3371 break;
3372
3373 case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3374 case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3375 case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3376 case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3377 case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3378 case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3379 case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3380 /* already handled above */
3381 AssertMsg( rc == VINF_PGM_CHANGE_MODE
3382 || rc == VINF_EM_RAW_INTERRUPT
3383 || rc == VERR_EM_INTERPRETER
3384 || rc == VINF_EM_RAW_EMULATE_INSTR
3385 || rc == VINF_PGM_SYNC_CR3
3386 || rc == VINF_IOM_HC_IOPORT_READ
3387 || rc == VINF_IOM_HC_IOPORT_WRITE
3388 || rc == VINF_EM_RAW_GUEST_TRAP
3389 || rc == VINF_TRPM_XCPT_DISPATCHED
3390 || rc == VINF_EM_RESCHEDULE_REM,
3391 ("rc = %d\n", rc));
3392 break;
3393
3394 case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3395 case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3396 case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3397 /* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
3398 rc = VERR_EM_INTERPRETER;
3399 break;
3400
3401 case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
3402 case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
3403 case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
3404 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3405 break;
3406
3407 case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3408 Assert(rc == VINF_EM_RAW_INTERRUPT);
3409 break;
3410
3411 case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
3412 {
3413#ifdef VBOX_STRICT
3414 RTCCUINTREG val = 0;
3415
3416 Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
3417
3418 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3419 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3420
3421 VMXReadVMCS(VMX_VMCS64_GUEST_CR0, &val);
3422 Log(("VMX_VMCS_GUEST_CR0 %RX64\n", (uint64_t)val));
3423
3424 VMXReadVMCS(VMX_VMCS64_GUEST_CR3, &val);
3425 Log(("VMX_VMCS_GUEST_CR3 %RX64\n", (uint64_t)val));
3426
3427 VMXReadVMCS(VMX_VMCS64_GUEST_CR4, &val);
3428 Log(("VMX_VMCS_GUEST_CR4 %RX64\n", (uint64_t)val));
3429
3430 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3431 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3432
3433 VMX_LOG_SELREG(CS, "CS");
3434 VMX_LOG_SELREG(DS, "DS");
3435 VMX_LOG_SELREG(ES, "ES");
3436 VMX_LOG_SELREG(FS, "FS");
3437 VMX_LOG_SELREG(GS, "GS");
3438 VMX_LOG_SELREG(SS, "SS");
3439 VMX_LOG_SELREG(TR, "TR");
3440 VMX_LOG_SELREG(LDTR, "LDTR");
3441
3442 VMXReadVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
3443 Log(("VMX_VMCS_GUEST_GDTR_BASE %RX64\n", (uint64_t)val));
3444 VMXReadVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
3445 Log(("VMX_VMCS_GUEST_IDTR_BASE %RX64\n", (uint64_t)val));
3446#endif /* VBOX_STRICT */
3447 rc = VERR_VMX_INVALID_GUEST_STATE;
3448 break;
3449 }
3450
3451 case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
3452 case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
3453 default:
3454 rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
3455 AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
3456 break;
3457
3458 }
3459end:
3460
3461 /* Signal changes for the recompiler. */
3462 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
3463
3464 /* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
3465 if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
3466 && !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
3467 {
3468 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
3469 /* On the next entry we'll only sync the host context. */
3470 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
3471 }
3472 else
3473 {
3474 /* On the next entry we'll sync everything. */
3475 /** @todo we can do better than this */
3476 /* Not in the VINF_PGM_CHANGE_MODE though! */
3477 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
3478 }
3479
3480 /* translate into a less severe return code */
3481 if (rc == VERR_EM_INTERPRETER)
3482 rc = VINF_EM_RAW_EMULATE_INSTR;
3483 else
3484 /* Try to extract more information about what might have gone wrong here. */
3485 if (rc == VERR_VMX_INVALID_VMCS_PTR)
3486 {
3487 VMXGetActivateVMCS(&pVCpu->hwaccm.s.vmx.lasterror.u64VMCSPhys);
3488 pVCpu->hwaccm.s.vmx.lasterror.ulVMCSRevision = *(uint32_t *)pVCpu->hwaccm.s.vmx.pVMCS;
3489 pVCpu->hwaccm.s.vmx.lasterror.idEnteredCpu = pVCpu->hwaccm.s.idEnteredCpu;
3490 pVCpu->hwaccm.s.vmx.lasterror.idCurrentCpu = RTMpCpuId();
3491 }
3492
3493 STAM_STATS({
3494 if (fStatExit2Started) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y);
3495 else if (fStatEntryStarted) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
3496 });
3497 Log2(("X"));
3498 return rc;
3499}
3500
3501
3502/**
3503 * Enters the VT-x session
3504 *
3505 * @returns VBox status code.
3506 * @param pVM The VM to operate on.
3507 * @param pVCpu The VMCPU to operate on.
3508 * @param pCpu CPU info struct
3509 */
3510VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
3511{
3512 Assert(pVM->hwaccm.s.vmx.fSupported);
3513
3514 unsigned cr4 = ASMGetCR4();
3515 if (!(cr4 & X86_CR4_VMXE))
3516 {
3517 AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
3518 return VERR_VMX_X86_CR4_VMXE_CLEARED;
3519 }
3520
3521 /* Activate the VM Control Structure. */
3522 int rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3523 if (RT_FAILURE(rc))
3524 return rc;
3525
3526 pVCpu->hwaccm.s.fResumeVM = false;
3527 return VINF_SUCCESS;
3528}
3529
3530
3531/**
3532 * Leaves the VT-x session
3533 *
3534 * @returns VBox status code.
3535 * @param pVM The VM to operate on.
3536 * @param pVCpu The VMCPU to operate on.
3537 * @param pCtx CPU context
3538 */
3539VMMR0DECL(int) VMXR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3540{
3541 Assert(pVM->hwaccm.s.vmx.fSupported);
3542
3543 /* Save the guest debug state if necessary. */
3544 if (CPUMIsGuestDebugStateActive(pVCpu))
3545 {
3546 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
3547
3548 /* Enable drx move intercepts again. */
3549 pVCpu->hwaccm.s.vmx.proc_ctls |= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3550 int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3551 AssertRC(rc);
3552
3553 /* Resync the debug registers the next time. */
3554 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
3555 }
3556 else
3557 Assert(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
3558
3559 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3560 int rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3561 AssertRC(rc);
3562
3563 return VINF_SUCCESS;
3564}
3565
3566/**
3567 * Flush the TLB (EPT)
3568 *
3569 * @returns VBox status code.
3570 * @param pVM The VM to operate on.
3571 * @param pVCpu The VM CPU to operate on.
3572 * @param enmFlush Type of flush
3573 * @param GCPhys Physical address of the page to flush
3574 */
3575static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
3576{
3577 uint64_t descriptor[2];
3578
3579 LogFlow(("vmxR0FlushEPT %d %RGv\n", enmFlush, GCPhys));
3580 Assert(pVM->hwaccm.s.fNestedPaging);
3581 descriptor[0] = pVCpu->hwaccm.s.vmx.GCPhysEPTP;
3582 descriptor[1] = GCPhys;
3583 int rc = VMXR0InvEPT(enmFlush, &descriptor[0]);
3584 AssertRC(rc);
3585}
3586
3587#ifdef HWACCM_VTX_WITH_VPID
3588/**
3589 * Flush the TLB (EPT)
3590 *
3591 * @returns VBox status code.
3592 * @param pVM The VM to operate on.
3593 * @param pVCpu The VM CPU to operate on.
3594 * @param enmFlush Type of flush
3595 * @param GCPtr Virtual address of the page to flush
3596 */
3597static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
3598{
3599#if HC_ARCH_BITS == 32
3600 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invvpid probably takes only 32 bits addresses. (@todo) */
3601 if ( CPUMIsGuestInLongMode(pVCpu)
3602 && !VMX_IS_64BIT_HOST_MODE())
3603 {
3604 pVCpu->hwaccm.s.fForceTLBFlush = true;
3605 }
3606 else
3607#endif
3608 {
3609 uint64_t descriptor[2];
3610
3611 Assert(pVM->hwaccm.s.vmx.fVPID);
3612 descriptor[0] = pVCpu->hwaccm.s.uCurrentASID;
3613 descriptor[1] = GCPtr;
3614 int rc = VMXR0InvVPID(enmFlush, &descriptor[0]);
3615 AssertRC(rc);
3616 }
3617}
3618#endif /* HWACCM_VTX_WITH_VPID */
3619
3620/**
3621 * Invalidates a guest page
3622 *
3623 * @returns VBox status code.
3624 * @param pVM The VM to operate on.
3625 * @param pVCpu The VM CPU to operate on.
3626 * @param GCVirt Page to invalidate
3627 */
3628VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
3629{
3630 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3631
3632 Log2(("VMXR0InvalidatePage %RGv\n", GCVirt));
3633
3634 /* Only relevant if we want to use VPID.
3635 * In the nested paging case we still see such calls, but
3636 * can safely ignore them. (e.g. after cr3 updates)
3637 */
3638#ifdef HWACCM_VTX_WITH_VPID
3639 /* Skip it if a TLB flush is already pending. */
3640 if ( !fFlushPending
3641 && pVM->hwaccm.s.vmx.fVPID)
3642 vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
3643#endif /* HWACCM_VTX_WITH_VPID */
3644
3645 return VINF_SUCCESS;
3646}
3647
3648/**
3649 * Invalidates a guest page by physical address
3650 *
3651 * NOTE: Assumes the current instruction references this physical page though a virtual address!!
3652 *
3653 * @returns VBox status code.
3654 * @param pVM The VM to operate on.
3655 * @param pVCpu The VM CPU to operate on.
3656 * @param GCPhys Page to invalidate
3657 */
3658VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
3659{
3660 bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3661
3662 Assert(pVM->hwaccm.s.fNestedPaging);
3663
3664 LogFlow(("VMXR0InvalidatePhysPage %RGp\n", GCPhys));
3665
3666 /* Skip it if a TLB flush is already pending. */
3667 if (!fFlushPending)
3668 vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
3669
3670 return VINF_SUCCESS;
3671}
3672
3673/**
3674 * Report world switch error and dump some useful debug info
3675 *
3676 * @param pVM The VM to operate on.
3677 * @param pVCpu The VMCPU to operate on.
3678 * @param rc Return code
3679 * @param pCtx Current CPU context (not updated)
3680 */
3681static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx)
3682{
3683 switch (rc)
3684 {
3685 case VERR_VMX_INVALID_VMXON_PTR:
3686 AssertFailed();
3687 break;
3688
3689 case VERR_VMX_UNABLE_TO_START_VM:
3690 case VERR_VMX_UNABLE_TO_RESUME_VM:
3691 {
3692 int rc;
3693 RTCCUINTREG exitReason, instrError;
3694
3695 rc = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
3696 rc |= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
3697 AssertRC(rc);
3698 if (rc == VINF_SUCCESS)
3699 {
3700 Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
3701 Log(("Current stack %08x\n", &rc));
3702
3703 pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
3704 pVCpu->hwaccm.s.vmx.lasterror.ulExitReason = exitReason;
3705
3706#ifdef VBOX_STRICT
3707 RTGDTR gdtr;
3708 PX86DESCHC pDesc;
3709 RTCCUINTREG val;
3710
3711 ASMGetGDTR(&gdtr);
3712
3713 VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3714 Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3715 VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
3716 Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
3717 VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
3718 Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
3719 VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
3720 Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
3721 VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
3722 Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
3723
3724 VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
3725 Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
3726
3727 VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
3728 Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
3729
3730 VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
3731 Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
3732
3733 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_CS, &val);
3734 Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
3735
3736 VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3737 Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3738
3739 if (val < gdtr.cbGdt)
3740 {
3741 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3742 HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
3743 }
3744
3745 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_DS, &val);
3746 Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
3747 if (val < gdtr.cbGdt)
3748 {
3749 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3750 HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
3751 }
3752
3753 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_ES, &val);
3754 Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
3755 if (val < gdtr.cbGdt)
3756 {
3757 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3758 HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
3759 }
3760
3761 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_FS, &val);
3762 Log(("VMX_VMCS16_HOST_FIELD_FS %08x\n", val));
3763 if (val < gdtr.cbGdt)
3764 {
3765 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3766 HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
3767 }
3768
3769 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_GS, &val);
3770 Log(("VMX_VMCS16_HOST_FIELD_GS %08x\n", val));
3771 if (val < gdtr.cbGdt)
3772 {
3773 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3774 HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
3775 }
3776
3777 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_SS, &val);
3778 Log(("VMX_VMCS16_HOST_FIELD_SS %08x\n", val));
3779 if (val < gdtr.cbGdt)
3780 {
3781 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3782 HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
3783 }
3784
3785 VMXReadVMCS(VMX_VMCS16_HOST_FIELD_TR, &val);
3786 Log(("VMX_VMCS16_HOST_FIELD_TR %08x\n", val));
3787 if (val < gdtr.cbGdt)
3788 {
3789 pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3790 HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
3791 }
3792
3793 VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
3794 Log(("VMX_VMCS_HOST_TR_BASE %RHv\n", val));
3795
3796 VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
3797 Log(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", val));
3798 VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
3799 Log(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", val));
3800
3801 VMXReadVMCS(VMX_VMCS32_HOST_SYSENTER_CS, &val);
3802 Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
3803
3804 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
3805 Log(("VMX_VMCS_HOST_SYSENTER_EIP %RHv\n", val));
3806
3807 VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
3808 Log(("VMX_VMCS_HOST_SYSENTER_ESP %RHv\n", val));
3809
3810 VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
3811 Log(("VMX_VMCS_HOST_RSP %RHv\n", val));
3812 VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
3813 Log(("VMX_VMCS_HOST_RIP %RHv\n", val));
3814
3815# if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3816 if (VMX_IS_64BIT_HOST_MODE())
3817 {
3818 Log(("MSR_K6_EFER = %RX64\n", ASMRdMsr(MSR_K6_EFER)));
3819 Log(("MSR_K6_STAR = %RX64\n", ASMRdMsr(MSR_K6_STAR)));
3820 Log(("MSR_K8_LSTAR = %RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
3821 Log(("MSR_K8_CSTAR = %RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
3822 Log(("MSR_K8_SF_MASK = %RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
3823 }
3824# endif
3825#endif /* VBOX_STRICT */
3826 }
3827 break;
3828 }
3829
3830 default:
3831 /* impossible */
3832 AssertMsgFailed(("%Rrc (%#x)\n", rc, rc));
3833 break;
3834 }
3835}
3836
3837#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3838/**
3839 * Prepares for and executes VMLAUNCH (64 bits guest mode)
3840 *
3841 * @returns VBox status code
3842 * @param fResume vmlauch/vmresume
3843 * @param pCtx Guest context
3844 * @param pCache VMCS cache
3845 * @param pVM The VM to operate on.
3846 * @param pVCpu The VMCPU to operate on.
3847 */
3848DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
3849{
3850 uint32_t aParam[6];
3851 PHWACCM_CPUINFO pCpu;
3852 RTHCPHYS pPageCpuPhys;
3853 int rc;
3854
3855 pCpu = HWACCMR0GetCurrentCpu();
3856 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
3857
3858#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3859 pCache->uPos = 1;
3860 pCache->interPD = PGMGetInterPaeCR3(pVM);
3861 pCache->pSwitcher = (uint64_t)pVM->hwaccm.s.pfnHost32ToGuest64R0;
3862#endif
3863
3864#ifdef DEBUG
3865 pCache->TestIn.pPageCpuPhys = 0;
3866 pCache->TestIn.pVMCSPhys = 0;
3867 pCache->TestIn.pCache = 0;
3868 pCache->TestOut.pVMCSPhys = 0;
3869 pCache->TestOut.pCache = 0;
3870 pCache->TestOut.pCtx = 0;
3871 pCache->TestOut.eflags = 0;
3872#endif
3873
3874 aParam[0] = (uint32_t)(pPageCpuPhys); /* Param 1: VMXON physical address - Lo. */
3875 aParam[1] = (uint32_t)(pPageCpuPhys >> 32); /* Param 1: VMXON physical address - Hi. */
3876 aParam[2] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys); /* Param 2: VMCS physical address - Lo. */
3877 aParam[3] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys >> 32); /* Param 2: VMCS physical address - Hi. */
3878 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache);
3879 aParam[5] = 0;
3880
3881#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3882 pCtx->dr[4] = pVM->hwaccm.s.vmx.pScratchPhys + 16 + 8;
3883 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 1;
3884#endif
3885 rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnVMXGCStartVM64, 6, &aParam[0]);
3886
3887#ifdef VBOX_WITH_CRASHDUMP_MAGIC
3888 Assert(*(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) == 5);
3889 Assert(pCtx->dr[4] == 10);
3890 *(uint32_t *)(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 0xff;
3891#endif
3892
3893#ifdef DEBUG
3894 AssertMsg(pCache->TestIn.pPageCpuPhys == pPageCpuPhys, ("%RHp vs %RHp\n", pCache->TestIn.pPageCpuPhys, pPageCpuPhys));
3895 AssertMsg(pCache->TestIn.pVMCSPhys == pVCpu->hwaccm.s.vmx.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pVCpu->hwaccm.s.vmx.pVMCSPhys));
3896 AssertMsg(pCache->TestIn.pVMCSPhys == pCache->TestOut.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pCache->TestOut.pVMCSPhys));
3897 AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache, pCache->TestOut.pCache));
3898 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache), ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache)));
3899 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx, pCache->TestOut.pCtx));
3900 Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
3901#endif
3902 return rc;
3903}
3904
3905/**
3906 * Executes the specified handler in 64 mode
3907 *
3908 * @returns VBox status code.
3909 * @param pVM The VM to operate on.
3910 * @param pVCpu The VMCPU to operate on.
3911 * @param pCtx Guest context
3912 * @param pfnHandler RC handler
3913 * @param cbParam Number of parameters
3914 * @param paParam Array of 32 bits parameters
3915 */
3916VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
3917{
3918 int rc, rc2;
3919 PHWACCM_CPUINFO pCpu;
3920 RTHCPHYS pPageCpuPhys;
3921
3922 /* @todo This code is not guest SMP safe (hyper stack) */
3923 AssertReturn(pVM->cCPUs == 1, VERR_ACCESS_DENIED);
3924 AssertReturn(pVM->hwaccm.s.pfnHost32ToGuest64R0, VERR_INTERNAL_ERROR);
3925 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField));
3926 Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField));
3927
3928#ifdef VBOX_STRICT
3929 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries;i++)
3930 Assert(vmxR0IsValidWriteField(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField[i]));
3931
3932 for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries;i++)
3933 Assert(vmxR0IsValidReadField(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField[i]));
3934#endif
3935
3936 pCpu = HWACCMR0GetCurrentCpu();
3937 pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
3938
3939 /* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3940 VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3941
3942 /* Leave VMX Root Mode. */
3943 VMXDisable();
3944
3945 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
3946
3947 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVM));
3948 CPUMSetHyperEIP(pVCpu, pfnHandler);
3949 for (int i=(int)cbParam-1;i>=0;i--)
3950 CPUMPushHyper(pVCpu, paParam[i]);
3951
3952 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
3953 /* Call switcher. */
3954 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
3955 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
3956
3957 /* Make sure the VMX instructions don't cause #UD faults. */
3958 ASMSetCR4(ASMGetCR4() | X86_CR4_VMXE);
3959
3960 /* Enter VMX Root Mode */
3961 rc2 = VMXEnable(pPageCpuPhys);
3962 if (RT_FAILURE(rc2))
3963 {
3964 if (pVM)
3965 VMXR0CheckError(pVM, pVCpu, rc2);
3966 ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
3967 return VERR_VMX_VMXON_FAILED;
3968 }
3969
3970 rc2 = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3971 AssertRCReturn(rc2, rc2);
3972#ifdef RT_OS_WINDOWS
3973 Assert(ASMGetFlags() & X86_EFL_IF);
3974#else
3975 Assert(!(ASMGetFlags() & X86_EFL_IF));
3976#endif
3977 return rc;
3978}
3979
3980#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
3981
3982
3983#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3984/**
3985 * Executes VMWRITE
3986 *
3987 * @returns VBox status code
3988 * @param pVCpu The VMCPU to operate on.
3989 * @param idxField VMCS index
3990 * @param u64Val 16, 32 or 64 bits value
3991 */
3992VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
3993{
3994 int rc;
3995
3996 switch (idxField)
3997 {
3998 case VMX_VMCS_CTRL_TSC_OFFSET_FULL:
3999 case VMX_VMCS_CTRL_IO_BITMAP_A_FULL:
4000 case VMX_VMCS_CTRL_IO_BITMAP_B_FULL:
4001 case VMX_VMCS_CTRL_MSR_BITMAP_FULL:
4002 case VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL:
4003 case VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL:
4004 case VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL:
4005 case VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL:
4006 case VMX_VMCS_GUEST_LINK_PTR_FULL:
4007 case VMX_VMCS_GUEST_PDPTR0_FULL:
4008 case VMX_VMCS_GUEST_PDPTR1_FULL:
4009 case VMX_VMCS_GUEST_PDPTR2_FULL:
4010 case VMX_VMCS_GUEST_PDPTR3_FULL:
4011 case VMX_VMCS_GUEST_DEBUGCTL_FULL:
4012 case VMX_VMCS_GUEST_EFER_FULL:
4013 case VMX_VMCS_CTRL_EPTP_FULL:
4014 /* These fields consist of two parts, which are both writable in 32 bits mode. */
4015 rc = VMXWriteVMCS32(idxField, u64Val);
4016 rc |= VMXWriteVMCS32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
4017 AssertRC(rc);
4018 return rc;
4019
4020 case VMX_VMCS64_GUEST_LDTR_BASE:
4021 case VMX_VMCS64_GUEST_TR_BASE:
4022 case VMX_VMCS64_GUEST_GDTR_BASE:
4023 case VMX_VMCS64_GUEST_IDTR_BASE:
4024 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4025 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4026 case VMX_VMCS64_GUEST_CR0:
4027 case VMX_VMCS64_GUEST_CR4:
4028 case VMX_VMCS64_GUEST_CR3:
4029 case VMX_VMCS64_GUEST_DR7:
4030 case VMX_VMCS64_GUEST_RIP:
4031 case VMX_VMCS64_GUEST_RSP:
4032 case VMX_VMCS64_GUEST_CS_BASE:
4033 case VMX_VMCS64_GUEST_DS_BASE:
4034 case VMX_VMCS64_GUEST_ES_BASE:
4035 case VMX_VMCS64_GUEST_FS_BASE:
4036 case VMX_VMCS64_GUEST_GS_BASE:
4037 case VMX_VMCS64_GUEST_SS_BASE:
4038 /* Queue a 64 bits value as we can't set it in 32 bits host mode. */
4039 if (u64Val >> 32ULL)
4040 rc = VMXWriteCachedVMCSEx(pVCpu, idxField, u64Val);
4041 else
4042 rc = VMXWriteVMCS32(idxField, (uint32_t)u64Val);
4043
4044 return rc;
4045
4046 default:
4047 AssertMsgFailed(("Unexpected field %x\n", idxField));
4048 return VERR_INVALID_PARAMETER;
4049 }
4050}
4051
4052/**
4053 * Cache VMCS writes for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
4054 *
4055 * @param pVCpu The VMCPU to operate on.
4056 * @param idxField VMCS field
4057 * @param u64Val Value
4058 */
4059VMMR0DECL(int) VMXWriteCachedVMCSEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4060{
4061 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
4062
4063 AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1, ("entries=%x\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
4064
4065 /* Make sure there are no duplicates. */
4066 for (unsigned i=0;i<pCache->Write.cValidEntries;i++)
4067 {
4068 if (pCache->Write.aField[i] == idxField)
4069 {
4070 pCache->Write.aFieldVal[i] = u64Val;
4071 return VINF_SUCCESS;
4072 }
4073 }
4074
4075 pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
4076 pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
4077 pCache->Write.cValidEntries++;
4078 return VINF_SUCCESS;
4079}
4080
4081#endif /* HC_ARCH_BITS == 32 && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
4082
4083#ifdef VBOX_STRICT
4084static bool vmxR0IsValidReadField(uint32_t idxField)
4085{
4086 switch(idxField)
4087 {
4088 case VMX_VMCS64_GUEST_RIP:
4089 case VMX_VMCS64_GUEST_RSP:
4090 case VMX_VMCS_GUEST_RFLAGS:
4091 case VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE:
4092 case VMX_VMCS_CTRL_CR0_READ_SHADOW:
4093 case VMX_VMCS64_GUEST_CR0:
4094 case VMX_VMCS_CTRL_CR4_READ_SHADOW:
4095 case VMX_VMCS64_GUEST_CR4:
4096 case VMX_VMCS64_GUEST_DR7:
4097 case VMX_VMCS32_GUEST_SYSENTER_CS:
4098 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4099 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4100 case VMX_VMCS32_GUEST_GDTR_LIMIT:
4101 case VMX_VMCS64_GUEST_GDTR_BASE:
4102 case VMX_VMCS32_GUEST_IDTR_LIMIT:
4103 case VMX_VMCS64_GUEST_IDTR_BASE:
4104 case VMX_VMCS16_GUEST_FIELD_CS:
4105 case VMX_VMCS32_GUEST_CS_LIMIT:
4106 case VMX_VMCS64_GUEST_CS_BASE:
4107 case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
4108 case VMX_VMCS16_GUEST_FIELD_DS:
4109 case VMX_VMCS32_GUEST_DS_LIMIT:
4110 case VMX_VMCS64_GUEST_DS_BASE:
4111 case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
4112 case VMX_VMCS16_GUEST_FIELD_ES:
4113 case VMX_VMCS32_GUEST_ES_LIMIT:
4114 case VMX_VMCS64_GUEST_ES_BASE:
4115 case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
4116 case VMX_VMCS16_GUEST_FIELD_FS:
4117 case VMX_VMCS32_GUEST_FS_LIMIT:
4118 case VMX_VMCS64_GUEST_FS_BASE:
4119 case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
4120 case VMX_VMCS16_GUEST_FIELD_GS:
4121 case VMX_VMCS32_GUEST_GS_LIMIT:
4122 case VMX_VMCS64_GUEST_GS_BASE:
4123 case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
4124 case VMX_VMCS16_GUEST_FIELD_SS:
4125 case VMX_VMCS32_GUEST_SS_LIMIT:
4126 case VMX_VMCS64_GUEST_SS_BASE:
4127 case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
4128 case VMX_VMCS16_GUEST_FIELD_LDTR:
4129 case VMX_VMCS32_GUEST_LDTR_LIMIT:
4130 case VMX_VMCS64_GUEST_LDTR_BASE:
4131 case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
4132 case VMX_VMCS16_GUEST_FIELD_TR:
4133 case VMX_VMCS32_GUEST_TR_LIMIT:
4134 case VMX_VMCS64_GUEST_TR_BASE:
4135 case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
4136 case VMX_VMCS32_RO_EXIT_REASON:
4137 case VMX_VMCS32_RO_VM_INSTR_ERROR:
4138 case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
4139 case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE:
4140 case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
4141 case VMX_VMCS32_RO_EXIT_INSTR_INFO:
4142 case VMX_VMCS_RO_EXIT_QUALIFICATION:
4143 case VMX_VMCS32_RO_IDT_INFO:
4144 case VMX_VMCS32_RO_IDT_ERRCODE:
4145 case VMX_VMCS64_GUEST_CR3:
4146 case VMX_VMCS_EXIT_PHYS_ADDR_FULL:
4147 return true;
4148 }
4149 return false;
4150}
4151
4152static bool vmxR0IsValidWriteField(uint32_t idxField)
4153{
4154 switch(idxField)
4155 {
4156 case VMX_VMCS64_GUEST_LDTR_BASE:
4157 case VMX_VMCS64_GUEST_TR_BASE:
4158 case VMX_VMCS64_GUEST_GDTR_BASE:
4159 case VMX_VMCS64_GUEST_IDTR_BASE:
4160 case VMX_VMCS64_GUEST_SYSENTER_EIP:
4161 case VMX_VMCS64_GUEST_SYSENTER_ESP:
4162 case VMX_VMCS64_GUEST_CR0:
4163 case VMX_VMCS64_GUEST_CR4:
4164 case VMX_VMCS64_GUEST_CR3:
4165 case VMX_VMCS64_GUEST_DR7:
4166 case VMX_VMCS64_GUEST_RIP:
4167 case VMX_VMCS64_GUEST_RSP:
4168 case VMX_VMCS64_GUEST_CS_BASE:
4169 case VMX_VMCS64_GUEST_DS_BASE:
4170 case VMX_VMCS64_GUEST_ES_BASE:
4171 case VMX_VMCS64_GUEST_FS_BASE:
4172 case VMX_VMCS64_GUEST_GS_BASE:
4173 case VMX_VMCS64_GUEST_SS_BASE:
4174 return true;
4175 }
4176 return false;
4177}
4178
4179#endif
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