HWVMXR0.cpp@ 552

Last change on this file since 552 was 138, checked in by vboxsync, 18 years ago
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1	/* $Id: HWVMXR0.cpp 138 2007-01-18 14:59:18Z vboxsync $ */
2	/** @file
3	* HWACCM VMX - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/pgm.h>
32	#include <VBox/pdm.h>
33	#include <VBox/err.h>
34	#include <VBox/log.h>
35	#include <VBox/selm.h>
36	#include <VBox/iom.h>
37	#include <iprt/param.h>
38	#include <iprt/assert.h>
39	#include <iprt/asm.h>
40	#include "HWVMXR0.h"
41
42
43	/* IO operation lookup arrays. */
44	static uint32_t aIOSize[4] = {1, 2, 0, 4};
45	static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
46
47
48	/**
49	* Sets up and activates VMX
50	*
51	* @returns VBox status code.
52	* @param pVM The VM to operate on.
53	*/
54	HWACCMR0DECL(int) VMXR0Setup(PVM pVM)
55	{
56	int rc = VINF_SUCCESS;
57	uint32_t val;
58
59	if (pVM == NULL)
60	return VERR_INVALID_PARAMETER;
61
62	/* Setup Intel VMX. */
63	Assert(pVM->hwaccm.s.vmx.fSupported);
64
65	/* Set revision dword at the beginning of both structures. */
66	(uint32_t )pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
67	(uint32_t )pVM->hwaccm.s.vmx.pVMXON = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
68
69	/* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
70	* (which can have very bad consequences!!!)
71	*/
72
73	/* Make sure the VMX instructions don't cause #UD faults. */
74	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
75
76	/* Enter VMX Root Mode */
77	rc = VMXEnable(pVM->hwaccm.s.vmx.pVMXONPhys);
78	if (VBOX_FAILURE(rc))
79	{
80	return rc;
81	}
82
83	/* Clear VM Control Structure. */
84	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
85	if (VBOX_FAILURE(rc))
86	goto vmx_end;
87
88	/* Activate the VM Control Structure. */
89	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
90	if (VBOX_FAILURE(rc))
91	goto vmx_end;
92
93	/* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
94	* Set required bits to one and zero according to the MSR capabilities.
95	*/
96	val = (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF);
97	/* External and non-maskable interrupts cause VM-exits. */
98	val = val \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
99	val &= (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL);
100
101	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
102	AssertRC(rc);
103
104	/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
105	* Set required bits to one and zero according to the MSR capabilities.
106	*/
107	val = (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF);
108	/* Program which event cause VM-exits and which features we want to use. */
109	val = val \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
110	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
111	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
112	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
113	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
114	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
115
116	/** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
117
118	/*
119	if AMD64 guest mode
120	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT
121	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT;
122	*/
123	/* Mask away the bits that the CPU doesn't support */
124	/** @todo make sure they don't conflict with the above requirements. */
125	val &= (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL);
126	pVM->hwaccm.s.vmx.proc_ctls = val;
127
128	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
129	AssertRC(rc);
130
131	/* VMX_VMCS_CTRL_CR3_TARGET_COUNT
132	* Set required bits to one and zero according to the MSR capabilities.
133	*/
134	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
135	AssertRC(rc);
136
137	/* VMX_VMCS_CTRL_ENTRY_CONTROLS
138	* Set required bits to one and zero according to the MSR capabilities.
139	*/
140	val = (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF);
141	if (pVM->hwaccm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
142	{
143	/** @todo 32 bits guest mode only for now. */
144	/* val \|= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE; */
145	}
146	/* Mask away the bits that the CPU doesn't support */
147	/** @todo make sure they don't conflict with the above requirements. */
148	val &= (pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL);
149	/* else Must be zero when AMD64 is not available. */
150	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
151	AssertRC(rc);
152
153	/* VMX_VMCS_CTRL_EXIT_CONTROLS
154	* Set required bits to one and zero according to the MSR capabilities.
155	*/
156	val = (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF);
157	#if HC_ARCH_BITS == 64
158	val \|= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
159	#else
160	/* else Must be zero when AMD64 is not available. */
161	#endif
162	val &= (pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL);
163	/* Don't acknowledge external interrupts on VM-exit. */
164	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
165	AssertRC(rc);
166
167	/* Forward all exception except #NM & #PF to the guest.
168	* We always need to check pagefaults since our shadow page table can be out of sync.
169	* And we always lazily sync the FPU & XMM state.
170	*/
171
172	/*
173	* @todo Possible optimization:
174	* Keep the FPU and XMM state current in the EM thread. That way there's no need to
175	* lazily sync anything, but the downside is that we can't use the FPU stack or XMM
176	* registers ourselves of course.
177	*
178	* @note only possible if the current state is actually ours (X86_CR0_TS flag)
179	*/
180	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
181	AssertRC(rc);
182
183	/* Don't filter page faults; all of them should cause a switch. */
184	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
185	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
186	AssertRC(rc);
187
188	/* Init TSC offset to zero. */
189	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
190	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
191	AssertRC(rc);
192
193	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
194	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
195	AssertRC(rc);
196
197	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
198	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
199	AssertRC(rc);
200
201	/* Clear MSR controls. */
202	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
203	{
204	/* Optional */
205	rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, 0);
206	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, 0);
207	AssertRC(rc);
208	}
209	rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
210	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
211	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
212	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
213	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
214	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_HIGH, 0);
215	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
216	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
217	AssertRC(rc);
218
219	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
220	{
221	/* Optional */
222	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_TRESHOLD, 0);
223	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, 0);
224	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, 0);
225	AssertRC(rc);
226	}
227
228	/* Set link pointer to -1. Not currently used. */
229	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
230	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
231	AssertRC(rc);
232
233	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
234	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
235	AssertRC(rc);
236
237	vmx_end:
238	/* Leave VMX Root Mode. */
239	VMXDisable();
240	return rc;
241	}
242
243
244	/**
245	* Injects an event (trap or external interrupt)
246	*
247	* @returns VBox status code.
248	* @param pVM The VM to operate on.
249	* @param pCtx CPU Context
250	* @param intInfo VMX interrupt info
251	* @param cbInstr Opcode length of faulting instruction
252	* @param errCode Error code (optional)
253	*/
254	static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
255	{
256	int rc;
257
258	#ifdef VBOX_STRICT
259	uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
260	if (iGate == 0xE)
261	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->eip, errCode, pCtx->cr2, intInfo));
262	else
263	if (iGate < 0x20)
264	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->eip, errCode));
265	else
266	{
267	Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->eip));
268	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
269	Assert(pCtx->eflags.u32 & X86_EFL_IF);
270	}
271	#endif
272
273	/* Set event injection state. */
274	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
275	intInfo \| (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
276	);
277
278	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
279	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
280
281	AssertRC(rc);
282	return rc;
283	}
284
285
286	/**
287	* Checks for pending guest interrupts and injects them
288	*
289	* @returns VBox status code.
290	* @param pVM The VM to operate on.
291	* @param pCtx CPU Context
292	*/
293	static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
294	{
295	int rc;
296
297	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
298	if (pVM->hwaccm.s.Event.fPending)
299	{
300	Log(("Reinjecting event %VX64 %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
301	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
302	rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
303	AssertRC(rc);
304
305	pVM->hwaccm.s.Event.fPending = false;
306	return VINF_SUCCESS;
307	}
308
309	/* When external interrupts are pending, we should exit the VM when IF is set. */
310	if ( !TRPMHasTrap(pVM)
311	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
312	{
313	if (!(pCtx->eflags.u32 & X86_EFL_IF))
314	{
315	Log2(("Enable irq window exit!\n"));
316	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT);
317	AssertRC(rc);
318	}
319	else
320	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
321	{
322	uint8_t u8Interrupt;
323
324	rc = PDMGetInterrupt(pVM, &u8Interrupt);
325	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
326	if (VBOX_SUCCESS(rc))
327	{
328	rc = TRPMAssertTrap(pVM, u8Interrupt, false);
329	AssertRC(rc);
330	}
331	else
332	{
333	/* can't happen... */
334	AssertFailed();
335	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
336	return VINF_EM_RAW_INTERRUPT_PENDING;
337	}
338	}
339	else
340	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
341	}
342
343	#ifdef VBOX_STRICT
344	if (TRPMHasTrap(pVM))
345	{
346	uint8_t u8Vector;
347	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
348	AssertRC(rc);
349	Assert(u8Vector >= 0x20);
350	}
351	#endif
352
353	if ( pCtx->eflags.u32 & X86_EFL_IF
354	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
355	&& TRPMHasTrap(pVM)
356	)
357	{
358	uint8_t u8Vector;
359	int rc;
360	bool fSoftwareInt;
361	RTGCUINTPTR intInfo, errCode;
362
363	/* If a new event is pending, then dispatch it now. */
364	rc = TRPMQueryTrapAll(pVM, &u8Vector, &fSoftwareInt, &errCode, 0);
365	AssertRC(rc);
366	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| u8Vector < 0x20);
367	Assert(fSoftwareInt == false);
368
369	/* Clear the pending trap. */
370	rc = TRPMResetTrap(pVM);
371	AssertRC(rc);
372
373	intInfo = u8Vector;
374	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
375
376	switch (u8Vector) {
377	case 8:
378	case 10:
379	case 11:
380	case 12:
381	case 13:
382	case 14:
383	case 17:
384	/* Valid error codes. */
385	intInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
386	break;
387	default:
388	break;
389	}
390
391	if (u8Vector == X86_XCPT_BP \|\| u8Vector == X86_XCPT_OF)
392	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
393	else
394	if (u8Vector < 0x20)
395	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
396	else
397	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
398
399	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
400	rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
401	AssertRC(rc);
402	} /* if (interrupts can be dispatched) */
403
404	return VINF_SUCCESS;
405	}
406
407	/**
408	* Save the host state
409	*
410	* @returns VBox status code.
411	* @param pVM The VM to operate on.
412	*/
413	HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
414	{
415	int rc = VINF_SUCCESS;
416
417	/*
418	* Host CPU Context
419	*/
420	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
421	{
422	RTIDTR idtr;
423	RTGDTR gdtr;
424	RTSEL SelTR;
425	PVBOXDESC pDesc;
426	uintptr_t trBase;
427
428	/* Control registers */
429	rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
430	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
431	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
432	AssertRC(rc);
433	Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
434	Log2(("VMX_VMCS_HOST_CR3 %08x\n", ASMGetCR3()));
435	Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
436
437	/* Selector registers. */
438	rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
439	/** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
440	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
441	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
442	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
443	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
444	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
445	SelTR = ASMGetTR();
446	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
447	AssertRC(rc);
448	Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
449	Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
450	Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
451	Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
452	Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
453	Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
454	Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
455
456	/* GDTR & IDTR */
457	ASMGetGDTR(&gdtr);
458	rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
459	ASMGetIDTR(&idtr);
460	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
461	AssertRC(rc);
462	Log2(("VMX_VMCS_HOST_GDTR_BASE %VGv\n", gdtr.pGdt));
463	Log2(("VMX_VMCS_HOST_IDTR_BASE %VGv\n", idtr.pIdt));
464
465	/* Save the base address of the TR selector. */
466	if (SelTR > gdtr.cbGdt)
467	{
468	AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
469	return VERR_VMX_INVALID_HOST_STATE;
470	}
471
472	pDesc = &((PVBOXDESC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT];
473	trBase = pDesc->Gen.u16BaseLow \| (pDesc->Gen.u8BaseHigh1 << 16) \| (pDesc->Gen.u8BaseHigh2 << 24);
474	rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
475	AssertRC(rc);
476	Log2(("VMX_VMCS_HOST_TR_BASE %VGv\n", trBase));
477
478	/* FS and GS base. */
479	#if HC_ARCH_BITS == 32
480	rc = VMXWriteVMCS(VMX_VMCS_HOST_FS_BASE, 0);
481	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_GS_BASE, 0);
482	#else
483	rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
484	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
485	#endif
486	AssertRC(rc);
487
488	/* Sysenter MSRs. */
489	/** @todo expensive!! */
490	rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
491	#if HC_ARCH_BITS == 32
492	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
493	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
494	Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
495	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VGv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
496	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VGv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
497	#else
498	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
499	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
500	#endif
501	AssertRC(rc);
502
503	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
504	}
505	return rc;
506	}
507
508
509	/**
510	* Loads the guest state
511	*
512	* @returns VBox status code.
513	* @param pVM The VM to operate on.
514	* @param pCtx Guest context
515	*/
516	HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
517	{
518	int rc = VINF_SUCCESS;
519	RTGCUINTPTR val;
520
521	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
522	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
523	{
524	VMX_WRITE_SELREG(ES, es);
525	AssertRC(rc);
526
527	VMX_WRITE_SELREG(CS, cs);
528	AssertRC(rc);
529
530	VMX_WRITE_SELREG(SS, ss);
531	AssertRC(rc);
532
533	VMX_WRITE_SELREG(DS, ds);
534	AssertRC(rc);
535
536	VMX_WRITE_SELREG(FS, fs);
537	AssertRC(rc);
538
539	VMX_WRITE_SELREG(GS, gs);
540	AssertRC(rc);
541	}
542
543	/* Guest CPU context: LDTR. */
544	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
545	{
546	if (pCtx->ldtr == 0)
547	{
548	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
549	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
550	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
551	/** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
552	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
553	}
554	else
555	{
556	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
557	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
558	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u32Base);
559	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
560	}
561	AssertRC(rc);
562	}
563	/* Guest CPU context: TR. */
564	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
565	{
566	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
567	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
568	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u32Base);
569	val = pCtx->trHid.Attr.u;
570
571	/* The TSS selector must be busy. */
572	if ((val & 0xF) == X86_SEL_TYPE_SYS_386_TSS_AVAIL)
573	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_386_TSS_BUSY;
574	else
575	if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
576	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_286_TSS_BUSY;
577
578	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
579	AssertRC(rc);
580	}
581	/* Guest CPU context: GDTR. */
582	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
583	{
584	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
585	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
586	AssertRC(rc);
587	}
588	/* Guest CPU context: IDTR. */
589	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
590	{
591	rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
592	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
593	AssertRC(rc);
594	}
595
596	/*
597	* Sysenter MSRs
598	*/
599	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
600	{
601	rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
602	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
603	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
604	AssertRC(rc);
605	}
606
607	/* Control registers */
608	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
609	{
610	val = pCtx->cr0;
611	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
612	Log2(("Guest CR0-shadow %08x\n", val));
613	if (CPUMIsGuestFPUStateActive(pVM) == false)
614	{
615	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
616	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
617	}
618	else
619	{
620	Assert(pVM->hwaccm.s.vmx.fResumeVM == true);
621	/** @todo check if we support the old style mess correctly. */
622	if (!(val & X86_CR0_NE))
623	{
624	Log(("Forcing X86_CR0_NE!!!\n"));
625
626	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
627	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
628	{
629	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK \| BIT(16));
630	AssertRC(rc);
631	pVM->hwaccm.s.fFPUOldStyleOverride = true;
632	}
633	}
634
635	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
636	}
637	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
638	Log2(("Guest CR0 %08x\n", val));
639	/* CR0 flags owned by the host; if the guests attempts to change them, then
640	* the VM will exit.
641	*/
642	val = X86_CR0_PE
643	\| X86_CR0_WP /** @todo do we care? (we do if we start patching the guest) */
644	\| X86_CR0_PG
645	\| X86_CR0_TS
646	\| X86_CR0_ET
647	\| X86_CR0_NE
648	\| X86_CR0_MP;
649	pVM->hwaccm.s.vmx.cr0_mask = val;
650
651	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
652	Log2(("Guest CR0-mask %08x\n", val));
653	AssertRC(rc);
654	}
655	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
656	{
657	/* CR4 */
658	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
659	Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
660	/* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
661	val = pCtx->cr4 \| (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
662	switch(pVM->hwaccm.s.enmShadowMode)
663	{
664	case PGMMODE_REAL:
665	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
666	AssertFailed();
667	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
668
669	case PGMMODE_32_BIT: /* 32-bit paging. */
670	break;
671
672	case PGMMODE_PAE: /* PAE paging. */
673	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
674	/** @todo use normal 32 bits paging */
675	val \|= X86_CR4_PAE;
676	break;
677
678	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
679	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
680	AssertFailed();
681	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
682
683	default: /* shut up gcc */
684	AssertFailed();
685	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
686	}
687	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
688	Log2(("Guest CR4 %08x\n", val));
689	/* CR4 flags owned by the host; if the guests attempts to change them, then
690	* the VM will exit.
691	*/
692	val = X86_CR4_PAE
693	\| X86_CR4_PGE
694	\| X86_CR4_PSE
695	\| X86_CR4_VMXE;
696	pVM->hwaccm.s.vmx.cr4_mask = val;
697
698	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
699	Log2(("Guest CR4-mask %08x\n", val));
700	AssertRC(rc);
701	}
702
703	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
704	{
705	/* Save our shadow CR3 register. */
706	val = PGMGetHyperCR3(pVM);
707	rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
708	AssertRC(rc);
709	}
710
711	/* Debug registers. */
712	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
713	{
714	/** @todo DR0-6 */
715	val = pCtx->dr7;
716	val &= ~(BIT(11) \| BIT(12) \| BIT(14) \| BIT(15)); /* must be zero */
717	val \|= 0x400; /* must be one */
718	#ifdef VBOX_STRICT
719	val = 0x400;
720	#endif
721	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
722	AssertRC(rc);
723
724	/* IA32_DEBUGCTL MSR. */
725	rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
726	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
727	AssertRC(rc);
728
729	/** @todo */
730	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
731	AssertRC(rc);
732	}
733
734	/* EIP, ESP and EFLAGS */
735	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->eip);
736	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->esp);
737	AssertRC(rc);
738
739	/* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
740	val = pCtx->eflags.u32;
741	val &= VMX_EFLAGS_RESERVED_0;
742	val \|= VMX_EFLAGS_RESERVED_1;
743	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, val);
744	AssertRC(rc);
745
746	/** @todo TSC offset. */
747
748	/* Done. */
749	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
750
751	return rc;
752	}
753
754	/**
755	* Runs guest code in a VMX VM.
756	*
757	* @note NEVER EVER turn on interrupts here. Due to our illegal entry into the kernel, it might mess things up. (XP kernel traps have been frequently observed)
758	*
759	* @returns VBox status code.
760	* @param pVM The VM to operate on.
761	* @param pCtx Guest context
762	*/
763	HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
764	{
765	int rc = VINF_SUCCESS;
766	RTCCUINTREG val, valShadow;
767	RTCCUINTREG exitReason, instrError, cbInstr;
768	RTGCUINTPTR exitQualification;
769	RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
770	RTGCUINTPTR errCode, instrInfo, uInterruptState;
771
772	Log2(("\nE"));
773
774	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
775
776	#ifdef VBOX_STRICT
777	rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
778	AssertRC(rc);
779	Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
780
781	/* allowed zero */
782	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_pin_ctls & 0xFFFFFFFF))
783	{
784	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
785	}
786	/* allowed one */
787	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_pin_ctls >> 32ULL)) != 0)
788	{
789	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
790	}
791
792	rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
793	AssertRC(rc);
794	Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
795
796	/* allowed zero */
797	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls & 0xFFFFFFFF))
798	{
799	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
800	}
801	/* allowed one */
802	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls >> 32ULL)) != 0)
803	{
804	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
805	}
806
807	rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
808	AssertRC(rc);
809	Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
810
811	/* allowed zero */
812	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_entry & 0xFFFFFFFF))
813	{
814	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
815	}
816	/* allowed one */
817	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_entry >> 32ULL)) != 0)
818	{
819	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
820	}
821
822	rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
823	AssertRC(rc);
824	Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
825
826	/* allowed zero */
827	if ((val & (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF)) != (pVM->hwaccm.s.vmx.msr.vmx_exit & 0xFFFFFFFF))
828	{
829	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
830	}
831	/* allowed one */
832	if ((val & ~(pVM->hwaccm.s.vmx.msr.vmx_exit >> 32ULL)) != 0)
833	{
834	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
835	}
836	#endif
837
838	#if 0
839	/*
840	* Check if debug registers are armed.
841	*/
842	uint32_t u32DR7 = ASMGetDR7();
843	if (u32DR7 & X86_DR7_ENABLED_MASK)
844	{
845	pVM->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
846	}
847	else
848	pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
849	#endif
850
851	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
852	*/
853	ResumeExecution:
854
855	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
856	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
857	{
858	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
859	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
860	{
861	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
862	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
863	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
864	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
865	*/
866	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
867	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
868	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
869	AssertRC(rc);
870	}
871	}
872	else
873	{
874	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
875	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
876	AssertRC(rc);
877	}
878
879	/* Check for pending actions that force us to go back to ring 3. */
880	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
881	{
882	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
883	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
884	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
885	rc = VINF_EM_RAW_TO_R3;
886	goto end;
887	}
888	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
889	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
890	{
891	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
892	rc = VINF_EM_PENDING_REQUEST;
893	goto end;
894	}
895
896	/* When external interrupts are pending, we should exit the VM when IF is set. */
897	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
898	rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
899	if (VBOX_FAILURE(rc))
900	{
901	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
902	goto end;
903	}
904
905	/** @todo check timers?? */
906
907	/* Save the host state first. */
908	rc = VMXR0SaveHostState(pVM);
909	if (rc != VINF_SUCCESS)
910	{
911	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
912	goto end;
913	}
914	/* Load the guest state */
915	rc = VMXR0LoadGuestState(pVM, pCtx);
916	if (rc != VINF_SUCCESS)
917	{
918	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
919	goto end;
920	}
921
922	/* Non-register state Guest Context */
923	/** @todo change me according to cpu state */
924	rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
925	AssertRC(rc);
926
927	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
928
929	/* Manual save and restore:
930	* - General purpose registers except RIP, RSP
931	*
932	* Trashed:
933	* - CR2 (we don't care)
934	* - LDTR (reset to 0)
935	* - DRx (presumably not changed at all)
936	* - DR7 (reset to 0x400)
937	* - EFLAGS (reset to BIT(1); not relevant)
938	*
939	*/
940
941	/* All done! Let's start VM execution. */
942	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
943	if (pVM->hwaccm.s.vmx.fResumeVM == false)
944	{
945	rc = VMXStartVM(pCtx);
946	}
947	else
948	{
949	rc = VMXResumeVM(pCtx);
950	}
951
952	/* In case we execute a goto ResumeExecution later on. */
953	pVM->hwaccm.s.vmx.fResumeVM = true;
954
955	/**
956	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
957	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
958	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
959	*/
960
961	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
962	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
963
964	switch (rc)
965	{
966	case VINF_SUCCESS:
967	break;
968
969	case VERR_VMX_INVALID_VMXON_PTR:
970	AssertFailed();
971	goto end;
972
973	case VERR_VMX_UNABLE_TO_START_VM:
974	case VERR_VMX_UNABLE_TO_RESUME_VM:
975	{
976	#ifdef VBOX_STRICT
977	int rc1;
978
979	rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
980	rc1 \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
981	AssertRC(rc1);
982	if (rc1 == VINF_SUCCESS)
983	{
984	RTGDTR gdtr;
985	PVBOXDESC pDesc;
986
987	ASMGetGDTR(&gdtr);
988	VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
989
990	Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
991	Log(("Current stack %08x\n", &rc1));
992
993	VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
994	Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
995
996	VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
997	Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
998
999	VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1000	Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1001
1002	VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1003	Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1004	if (val < gdtr.cbGdt)
1005	{
1006	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1007	HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1008	}
1009
1010	VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1011	Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1012	if (val < gdtr.cbGdt)
1013	{
1014	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1015	HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1016	}
1017
1018	VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1019	Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1020	if (val < gdtr.cbGdt)
1021	{
1022	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1023	HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1024	}
1025
1026	VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1027	Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1028	if (val < gdtr.cbGdt)
1029	{
1030	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1031	HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1032	}
1033
1034	VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1035	Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1036	if (val < gdtr.cbGdt)
1037	{
1038	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1039	HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1040	}
1041
1042	VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1043	Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1044	if (val < gdtr.cbGdt)
1045	{
1046	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1047	HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1048	}
1049
1050	VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1051	Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1052	if (val < gdtr.cbGdt)
1053	{
1054	pDesc = &((PVBOXDESC)gdtr.pGdt)[val >> X86_SEL_SHIFT];
1055	HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1056	}
1057
1058	VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1059	Log(("VMX_VMCS_HOST_TR_BASE %VGv\n", val));
1060
1061	VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1062	Log(("VMX_VMCS_HOST_GDTR_BASE %VGv\n", val));
1063	VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1064	Log(("VMX_VMCS_HOST_IDTR_BASE %VGv\n", val));
1065
1066	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1067	Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1068
1069	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1070	Log(("VMX_VMCS_HOST_SYSENTER_EIP %VGv\n", val));
1071
1072	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1073	Log(("VMX_VMCS_HOST_SYSENTER_ESP %VGv\n", val));
1074
1075	VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1076	Log(("VMX_VMCS_HOST_RSP %VGv\n", val));
1077	VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1078	Log(("VMX_VMCS_HOST_RIP %VGv\n", val));
1079	}
1080	#endif /* VBOX_STRICT */
1081	goto end;
1082	}
1083
1084	default:
1085	/* impossible */
1086	AssertFailed();
1087	goto end;
1088	}
1089	/* Success. Query the guest state and figure out what has happened. */
1090
1091	/* Investigate why there was a VM-exit. */
1092	rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1093	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReason[exitReason & MASK_EXITREASON_STAT]);
1094
1095	exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1096	rc \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1097	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1098	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1099	intInfo = val;
1100	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1101	errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1102	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1103	instrInfo = val;
1104	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1105	exitQualification = val;
1106	AssertRC(rc);
1107
1108	/* Take care of instruction fusing (sti, mov ss) */
1109	rc \|= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1110	uInterruptState = val;
1111	if (uInterruptState != 0)
1112	{
1113	Assert(uInterruptState <= 2); /* only sti & mov ss */
1114	Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->eip));
1115	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
1116	}
1117	else
1118	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1119
1120	/* Let's first sync back eip, esp, and eflags. */
1121	rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1122	AssertRC(rc);
1123	pCtx->eip = val;
1124	rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1125	AssertRC(rc);
1126	pCtx->esp = val;
1127	rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1128	AssertRC(rc);
1129	pCtx->eflags.u32 = val;
1130
1131	/* Control registers. */
1132	VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1133	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1134	val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) \| (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1135	CPUMSetGuestCR0(pVM, val);
1136
1137	VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1138	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1139	val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) \| (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1140	CPUMSetGuestCR4(pVM, val);
1141
1142	CPUMSetGuestCR2(pVM, ASMGetCR2());
1143
1144	VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1145	CPUMSetGuestDR7(pVM, val);
1146
1147	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1148	VMX_READ_SELREG(ES, es);
1149	VMX_READ_SELREG(SS, ss);
1150	VMX_READ_SELREG(CS, cs);
1151	VMX_READ_SELREG(DS, ds);
1152	VMX_READ_SELREG(FS, fs);
1153	VMX_READ_SELREG(GS, gs);
1154
1155	/** @note NOW IT'S SAFE FOR LOGGING! */
1156	Log2(("Raw exit reason %08x\n", exitReason));
1157
1158	/* Check if an injected event was interrupted prematurely. */
1159	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1160	AssertRC(rc);
1161	pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1162	if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1163	&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1164	{
1165	Log(("Pending inject %VX64 at %08x exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitReason, intInfo, exitQualification));
1166	pVM->hwaccm.s.Event.fPending = true;
1167	/* Error code present? */
1168	if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1169	{
1170	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1171	AssertRC(rc);
1172	pVM->hwaccm.s.Event.errCode = val;
1173	}
1174	else
1175	pVM->hwaccm.s.Event.errCode = 0;
1176	}
1177
1178	#ifdef VBOX_STRICT
1179	if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1180	HWACCMDumpRegs(pCtx);
1181	#endif
1182
1183	Log2(("E%d", exitReason));
1184	Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1185	Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1186	Log2(("Interruption error code %d\n", errCode));
1187	Log2(("IntInfo = %08x\n", intInfo));
1188	Log2(("New EIP=%VGv\n", pCtx->eip));
1189
1190	/* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1191	switch (exitReason)
1192	{
1193	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1194	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1195	{
1196	uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1197
1198	if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1199	{
1200	Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1201	/* External interrupt; leave to allow it to be dispatched again. */
1202	rc = VINF_EM_RAW_INTERRUPT;
1203	break;
1204	}
1205	switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1206	{
1207	case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1208	/* External interrupt; leave to allow it to be dispatched again. */
1209	rc = VINF_EM_RAW_INTERRUPT;
1210	break;
1211
1212	case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1213	AssertFailed(); /* can't come here; fails the first check. */
1214	break;
1215
1216	case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1217	Assert(vector == 3 \|\| vector == 4);
1218	/* no break */
1219	case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1220	Log2(("Hardware/software interrupt %d\n", vector));
1221	switch (vector)
1222	{
1223	case X86_XCPT_NM:
1224	{
1225	uint32_t oldCR0;
1226
1227	Log(("#NM fault at %VGv error code %x\n", pCtx->eip, errCode));
1228
1229	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1230	oldCR0 = ASMGetCR0();
1231	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1232	rc = CPUMHandleLazyFPU(pVM);
1233	if (rc == VINF_SUCCESS)
1234	{
1235	Assert(CPUMIsGuestFPUStateActive(pVM));
1236
1237	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
1238	ASMSetCR0(oldCR0);
1239
1240	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1241
1242	/* Continue execution. */
1243	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1244	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1245
1246	goto ResumeExecution;
1247	}
1248
1249	Log(("Forward #NM fault to the guest\n"));
1250	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1251	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1252	AssertRC(rc);
1253	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1254	goto ResumeExecution;
1255	}
1256
1257	case X86_XCPT_PF: /* Page fault */
1258	{
1259	Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1260	/* Exit qualification contains the linear address of the page fault. */
1261	TRPMAssertTrap(pVM, X86_XCPT_PF, false);
1262	TRPMSetErrorCode(pVM, errCode);
1263	TRPMSetFaultAddress(pVM, exitQualification);
1264
1265	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1266	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1267	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
1268	if (rc == VINF_SUCCESS)
1269	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1270	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, exitQualification ,errCode));
1271	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1272
1273	TRPMResetTrap(pVM);
1274
1275	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1276	goto ResumeExecution;
1277	}
1278	else
1279	if (rc == VINF_EM_RAW_GUEST_TRAP)
1280	{ /* A genuine pagefault.
1281	* Forward the trap to the guest by injecting the exception and resuming execution.
1282	*/
1283	Log2(("Forward page fault to the guest\n"));
1284	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1285	/* The error code might have been changed. */
1286	errCode = TRPMGetErrorCode(pVM);
1287
1288	TRPMResetTrap(pVM);
1289
1290	/* Now we must update CR2. */
1291	pCtx->cr2 = exitQualification;
1292	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1293	AssertRC(rc);
1294
1295	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1296	goto ResumeExecution;
1297	}
1298	#ifdef VBOX_STRICT
1299	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1300	Log(("PGMTrap0eHandler failed with %d\n", rc));
1301	#endif
1302	/* Need to go back to the recompiler to emulate the instruction. */
1303	TRPMResetTrap(pVM);
1304	break;
1305	}
1306
1307	case X86_XCPT_MF: /* Floating point exception. */
1308	{
1309	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1310	if (!(pCtx->cr0 & X86_CR0_NE))
1311	{
1312	/* old style FPU error reporting needs some extra work. */
1313	/** @todo don't fall back to the recompiler, but do it manually. */
1314	rc = VINF_EM_RAW_EMULATE_INSTR;
1315	break;
1316	}
1317	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1318	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1319	AssertRC(rc);
1320
1321	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1322	goto ResumeExecution;
1323	}
1324
1325	#ifdef VBOX_STRICT
1326	case X86_XCPT_GP: /* General protection failure exception.*/
1327	case X86_XCPT_UD: /* Unknown opcode exception. */
1328	case X86_XCPT_DE: /* Debug exception. */
1329	case X86_XCPT_SS: /* Stack segment exception. */
1330	case X86_XCPT_NP: /* Segment not present exception. */
1331	{
1332	switch(vector)
1333	{
1334	case X86_XCPT_DE:
1335	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1336	break;
1337	case X86_XCPT_UD:
1338	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1339	break;
1340	case X86_XCPT_SS:
1341	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1342	break;
1343	case X86_XCPT_NP:
1344	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1345	break;
1346	case X86_XCPT_GP:
1347	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1348	break;
1349	}
1350
1351	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1352	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1353	AssertRC(rc);
1354
1355	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1356	goto ResumeExecution;
1357	}
1358	#endif
1359	default:
1360	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1361	rc = VERR_EM_INTERNAL_ERROR;
1362	break;
1363	} /* switch (vector) */
1364
1365	break;
1366
1367	default:
1368	rc = VERR_EM_INTERNAL_ERROR;
1369	AssertFailed();
1370	break;
1371	}
1372
1373	break;
1374	}
1375
1376	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1377	/* Clear VM-exit on IF=1 change. */
1378	Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->eip));
1379	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1380	AssertRC(rc);
1381	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1382	goto ResumeExecution; /* we check for pending guest interrupts there */
1383
1384	case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. */
1385	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1386	/* Skip instruction and continue directly. */
1387	pCtx->eip += cbInstr;
1388	/* Continue execution.*/
1389	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1390	goto ResumeExecution;
1391
1392	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1393	{
1394	Log2(("VMX: Cpuid %x\n", pCtx->eax));
1395	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1396	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1397	if (rc == VINF_SUCCESS)
1398	{
1399	/* Update EIP and continue execution. */
1400	pCtx->eip += cbInstr;
1401	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1402	goto ResumeExecution;
1403	}
1404	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1405	rc = VINF_EM_RAW_EMULATE_INSTR;
1406	break;
1407	}
1408
1409	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1410	{
1411	Log2(("VMX: invlpg\n"));
1412	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1413	rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1414	if (rc == VINF_SUCCESS)
1415	{
1416	/* Update EIP and continue execution. */
1417	pCtx->eip += cbInstr;
1418	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1419	goto ResumeExecution;
1420	}
1421	AssertMsgFailed(("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1422	rc = VINF_EM_RAW_EMULATE_INSTR;
1423	break;
1424	}
1425
1426	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1427	{
1428	switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1429	{
1430	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1431	Log2(("VMX: %VGv mov cr%d, x\n", pCtx->eip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1432	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1433	rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1434	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1435	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1436
1437	switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1438	{
1439	case 0:
1440	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1441	break;
1442	case 2:
1443	break;
1444	case 3:
1445	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1446	break;
1447	case 4:
1448	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1449	break;
1450	default:
1451	AssertFailed();
1452	}
1453	/* Check if a sync operation is pending. */
1454	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1455	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1456	{
1457	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1458	AssertRC(rc);
1459	}
1460	break;
1461
1462	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1463	Log2(("VMX: mov x, crx\n"));
1464	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1465	rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1466	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1467	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1468	break;
1469
1470	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1471	Log2(("VMX: clts\n"));
1472	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1473	rc = EMInterpretCLTS(pVM);
1474	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1475	break;
1476
1477	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1478	Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1479	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1480	rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1481	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1482	break;
1483	}
1484
1485	/* Update EIP if no error occurred. */
1486	if (VBOX_SUCCESS(rc))
1487	pCtx->eip += cbInstr;
1488
1489	if (rc == VINF_SUCCESS)
1490	{
1491	/* Only resume if successful. */
1492	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1493	goto ResumeExecution;
1494	}
1495	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1496	if (rc == VERR_EM_INTERPRETER)
1497	rc = VINF_EM_RAW_EMULATE_INSTR;
1498	break;
1499	}
1500
1501	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1502	{
1503	/** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1504	if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1505	{
1506	Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1507	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1508	rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1509	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1510	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1511	Log2(("DR7=%08x\n", pCtx->dr7));
1512	}
1513	else
1514	{
1515	Log2(("VMX: mov x, drx\n"));
1516	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1517	rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1518	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1519	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1520	}
1521	/* Update EIP if no error occurred. */
1522	if (VBOX_SUCCESS(rc))
1523	pCtx->eip += cbInstr;
1524
1525	if (rc == VINF_SUCCESS)
1526	{
1527	/* Only resume if successful. */
1528	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1529	goto ResumeExecution;
1530	}
1531	Assert(rc == VERR_EM_INTERPRETER);
1532	rc = VINF_EM_RAW_EMULATE_INSTR;
1533	break;
1534	}
1535
1536	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1537	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1538	{
1539	uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1540	uint32_t uPort;
1541
1542	/** @todo necessary to make the distinction? */
1543	if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1544	{
1545	uPort = pCtx->edx & 0xffff;
1546	}
1547	else
1548	uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1549
1550	/* First simple in and out instructions. */
1551	/** @todo str & rep */
1552	if ( !VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification)
1553	&& !VMX_EXIT_QUALIFICATION_IO_REP(exitQualification)
1554	/* paranoid checks ahead */
1555	&& uIOWidth != 2
1556	&& uIOWidth < 4
1557	)
1558	{
1559	uint32_t cbSize = aIOSize[uIOWidth];
1560	uint32_t uAndVal = aIOOpAnd[uIOWidth];
1561
1562	if (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT)
1563	{
1564	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1565	rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
1566	}
1567	else
1568	{
1569	uint32_t u32Val = 0;
1570
1571	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1572	rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
1573	if (rc == VINF_SUCCESS)
1574	{
1575	/* Write back to the EAX register. */
1576	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1577	}
1578	}
1579	if (rc == VINF_SUCCESS)
1580	{
1581	/* Update EIP and continue execution. */
1582	pCtx->eip += cbInstr;
1583	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1584	goto ResumeExecution;
1585	}
1586	Assert(rc == VINF_IOM_HC_IOPORT_READ \|\| rc == VINF_IOM_HC_IOPORT_WRITE);
1587	rc = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT)
1588	? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1589	}
1590	else
1591	rc = VINF_IOM_HC_IOPORT_READWRITE;
1592
1593	break;
1594	}
1595
1596	default:
1597	/* The rest is handled after syncing the entire CPU state. */
1598	break;
1599	}
1600
1601	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1602	VMX_READ_SELREG(LDTR, ldtr);
1603	VMX_READ_SELREG(TR, tr);
1604
1605	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
1606	pCtx->gdtr.cbGdt = val;
1607	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
1608	pCtx->gdtr.pGdt = val;
1609
1610	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
1611	pCtx->idtr.cbIdt = val;
1612	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
1613	pCtx->idtr.pIdt = val;
1614
1615	/*
1616	* System MSRs
1617	*/
1618	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
1619	pCtx->SysEnter.cs = val;
1620	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
1621	pCtx->SysEnter.eip = val;
1622	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
1623	pCtx->SysEnter.esp = val;
1624
1625	/* Signal changes for the recompiler. */
1626	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1627
1628	/* Investigate why there was a VM-exit. (part 2) */
1629	switch (exitReason)
1630	{
1631	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1632	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1633	/* Already handled above. */
1634	break;
1635
1636	case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
1637	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1638	break;
1639
1640	case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
1641	case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
1642	rc = VINF_EM_RAW_INTERRUPT;
1643	AssertFailed(); /* Can't happen. Yet. */
1644	break;
1645
1646	case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
1647	case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
1648	rc = VINF_EM_RAW_INTERRUPT;
1649	AssertFailed(); /* Can't happen afaik. */
1650	break;
1651
1652	case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
1653	rc = VINF_EM_RAW_RING_SWITCH_INT;
1654	break;
1655
1656	case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
1657	/** Check if external interrupts are pending; if so, don't switch back. */
1658	if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1659	{
1660	pCtx->eip++; /* skip hlt */
1661	goto ResumeExecution;
1662	}
1663
1664	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1665	break;
1666
1667	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1668	rc = VERR_EM_INTERNAL_ERROR;
1669	AssertFailed(); /* we don't let it fault. */
1670	break;
1671
1672	case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
1673	AssertFailed(); /* can't happen. */
1674	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1675	break;
1676
1677	case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
1678	case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
1679	case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
1680	case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
1681	case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
1682	case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
1683	case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
1684	case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
1685	case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
1686	case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
1687	/** @todo inject #UD immediately */
1688	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1689	break;
1690
1691	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1692	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1693	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1694	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1695	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1696	/* already handled above */
1697	AssertMsg(rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_EM_RAW_INTERRUPT \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_PGM_SYNC_CR3 \|\| rc == VINF_IOM_HC_IOPORT_READ \|\| rc == VINF_IOM_HC_IOPORT_WRITE \|\| rc == VINF_IOM_HC_IOPORT_READWRITE, ("rc = %d\n", rc));
1698	break;
1699
1700	case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
1701	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1702	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1703	case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
1704	case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
1705	case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
1706	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1707	break;
1708
1709	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1710	Assert(rc == VINF_EM_RAW_INTERRUPT);
1711	break;
1712
1713	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
1714	case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
1715	case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
1716	case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
1717	default:
1718	rc = VERR_EM_INTERNAL_ERROR;
1719	AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
1720	break;
1721
1722	}
1723	end:
1724
1725	/* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
1726	if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
1727	&& !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1728	{
1729	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1730	/* On the next entry we'll only sync the host context. */
1731	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1732	}
1733	else
1734	{
1735	/* On the next entry we'll sync everything. */
1736	/** @todo we can do better than this */
1737	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1738	}
1739
1740	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1741	Log2(("X"));
1742	return rc;
1743	}
1744
1745
1746	/**
1747	* Enable VMX
1748	*
1749	* @returns VBox status code.
1750	* @param pVM The VM to operate on.
1751	*/
1752	HWACCMR0DECL(int) VMXR0Enable(PVM pVM)
1753	{
1754	Assert(pVM->hwaccm.s.vmx.fSupported);
1755
1756	/* Make sure the VMX instructions don't cause #UD faults. */
1757	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
1758
1759	/* Enter VMX Root Mode */
1760	int rc = VMXEnable(pVM->hwaccm.s.vmx.pVMXONPhys);
1761	if (VBOX_FAILURE(rc))
1762	return rc;
1763
1764	/* Activate the VM Control Structure. */
1765	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
1766	if (VBOX_FAILURE(rc))
1767	{
1768	/* Leave VMX Root Mode. */
1769	VMXDisable();
1770	return rc;
1771	}
1772	pVM->hwaccm.s.vmx.fResumeVM = false;
1773	return VINF_SUCCESS;
1774	}
1775
1776
1777	/**
1778	* Disable VMX
1779	*
1780	* @returns VBox status code.
1781	* @param pVM The VM to operate on.
1782	*/
1783	HWACCMR0DECL(int) VMXR0Disable(PVM pVM)
1784	{
1785	Assert(pVM->hwaccm.s.vmx.fSupported);
1786
1787	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
1788	int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
1789	AssertRC(rc);
1790
1791	/* Leave VMX Root Mode. */
1792	VMXDisable();
1793
1794	return VINF_SUCCESS;
1795	}
1796

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 552

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