HWVMXR0.cpp@ 20543

Last change on this file since 20543 was 20530, checked in by vboxsync, 15 years ago
VMM: remove DISCPUSTATE from the stack.
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1	/* $Id: HWVMXR0.cpp 20530 2009-06-13 20:53:44Z vboxsync $ */
2	/** @file
3	* HWACCM VMX - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/pgm.h>
32	#include <VBox/pdm.h>
33	#include <VBox/err.h>
34	#include <VBox/log.h>
35	#include <VBox/selm.h>
36	#include <VBox/iom.h>
37	#include <VBox/rem.h>
38	#include <iprt/asm.h>
39	#include <iprt/assert.h>
40	#include <iprt/param.h>
41	#include <iprt/string.h>
42	#include <iprt/time.h>
43	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
44	# include <iprt/thread.h>
45	#endif
46	#include "HWVMXR0.h"
47
48	/*******************************************************************************
49	* Defined Constants And Macros *
50	*******************************************************************************/
51	#if defined(RT_ARCH_AMD64)
52	# define VMX_IS_64BIT_HOST_MODE() (true)
53	#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
54	# define VMX_IS_64BIT_HOST_MODE() (g_fVMXIs64bitHost != 0)
55	#else
56	# define VMX_IS_64BIT_HOST_MODE() (false)
57	#endif
58
59	/*******************************************************************************
60	* Global Variables *
61	*******************************************************************************/
62	/* IO operation lookup arrays. */
63	static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
64	static uint32_t const g_aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
65
66	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
67	/** See HWACCMR0A.asm. */
68	extern "C" uint32_t g_fVMXIs64bitHost;
69	#endif
70
71	/*******************************************************************************
72	* Local Functions *
73	*******************************************************************************/
74	static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx);
75	static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu);
76	static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu);
77	static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu);
78	static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys);
79	static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr);
80	static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
81	#ifdef VBOX_STRICT
82	static bool vmxR0IsValidReadField(uint32_t idxField);
83	static bool vmxR0IsValidWriteField(uint32_t idxField);
84	#endif
85
86	static void VMXR0CheckError(PVM pVM, PVMCPU pVCpu, int rc)
87	{
88	if (rc == VERR_VMX_GENERIC)
89	{
90	RTCCUINTREG instrError;
91
92	VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
93	pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
94	}
95	pVM->hwaccm.s.lLastError = rc;
96	}
97
98	/**
99	* Sets up and activates VT-x on the current CPU
100	*
101	* @returns VBox status code.
102	* @param pCpu CPU info struct
103	* @param pVM The VM to operate on. (can be NULL after a resume!!)
104	* @param pvPageCpu Pointer to the global cpu page
105	* @param pPageCpuPhys Physical address of the global cpu page
106	*/
107	VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
108	{
109	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
110	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
111
112	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
113	SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
114	#endif
115	if (pVM)
116	{
117	/* Set revision dword at the beginning of the VMXON structure. */
118	(uint32_t )pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
119	}
120
121	/** @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
122	* (which can have very bad consequences!!!)
123	*/
124
125	/* Make sure the VMX instructions don't cause #UD faults. */
126	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
127
128	/* Enter VMX Root Mode */
129	int rc = VMXEnable(pPageCpuPhys);
130	if (RT_FAILURE(rc))
131	{
132	if (pVM)
133	VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
134	ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
135	return VERR_VMX_VMXON_FAILED;
136	}
137	return VINF_SUCCESS;
138	}
139
140	/**
141	* Deactivates VT-x on the current CPU
142	*
143	* @returns VBox status code.
144	* @param pCpu CPU info struct
145	* @param pvPageCpu Pointer to the global cpu page
146	* @param pPageCpuPhys Physical address of the global cpu page
147	*/
148	VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
149	{
150	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
151	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
152
153	/* Leave VMX Root Mode. */
154	VMXDisable();
155
156	/* And clear the X86_CR4_VMXE bit */
157	ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
158
159	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
160	SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
161	#endif
162	return VINF_SUCCESS;
163	}
164
165	/**
166	* Does Ring-0 per VM VT-x init.
167	*
168	* @returns VBox status code.
169	* @param pVM The VM to operate on.
170	*/
171	VMMR0DECL(int) VMXR0InitVM(PVM pVM)
172	{
173	int rc;
174
175	#ifdef LOG_ENABLED
176	SUPR0Printf("VMXR0InitVM %x\n", pVM);
177	#endif
178
179	pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
180
181	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
182	{
183	/* Allocate one page for the APIC physical page (serves for filtering accesses). */
184	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
185	AssertRC(rc);
186	if (RT_FAILURE(rc))
187	return rc;
188
189	pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
190	pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
191	ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
192	}
193	else
194	{
195	pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
196	pVM->hwaccm.s.vmx.pAPIC = 0;
197	pVM->hwaccm.s.vmx.pAPICPhys = 0;
198	}
199
200	/* Allocate the MSR bitmap if this feature is supported. */
201	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
202	{
203	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
204	AssertRC(rc);
205	if (RT_FAILURE(rc))
206	return rc;
207
208	pVM->hwaccm.s.vmx.pMSRBitmap = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjMSRBitmap);
209	pVM->hwaccm.s.vmx.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, 0);
210	memset(pVM->hwaccm.s.vmx.pMSRBitmap, 0xff, PAGE_SIZE);
211	}
212
213	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
214	{
215	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjScratch, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
216	AssertRC(rc);
217	if (RT_FAILURE(rc))
218	return rc;
219
220	pVM->hwaccm.s.vmx.pScratch = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjScratch);
221	pVM->hwaccm.s.vmx.pScratchPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjScratch, 0);
222
223	ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
224	strcpy((char *)pVM->hwaccm.s.vmx.pScratch, "SCRATCH Magic");
225	(uint64_t )(pVM->hwaccm.s.vmx.pScratch + 16) = UINT64_C(0xDEADBEEFDEADBEEF);
226	}
227	#endif
228
229	/* Allocate VMCBs for all guest CPUs. */
230	for (unsigned i=0;i<pVM->cCPUs;i++)
231	{
232	PVMCPU pVCpu = &pVM->aCpus[i];
233
234	pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
235
236	/* Allocate one page for the VM control structure (VMCS). */
237	rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
238	AssertRC(rc);
239	if (RT_FAILURE(rc))
240	return rc;
241
242	pVCpu->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVMCS);
243	pVCpu->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVMCS, 0);
244	ASMMemZero32(pVCpu->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
245
246	pVCpu->hwaccm.s.vmx.cr0_mask = 0;
247	pVCpu->hwaccm.s.vmx.cr4_mask = 0;
248
249	/* Allocate one page for the virtual APIC page for TPR caching. */
250	rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.vmx.pMemObjVAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
251	AssertRC(rc);
252	if (RT_FAILURE(rc))
253	return rc;
254
255	pVCpu->hwaccm.s.vmx.pVAPIC = (uint8_t *)RTR0MemObjAddress(pVCpu->hwaccm.s.vmx.pMemObjVAPIC);
256	pVCpu->hwaccm.s.vmx.pVAPICPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.vmx.pMemObjVAPIC, 0);
257	ASMMemZero32(pVCpu->hwaccm.s.vmx.pVAPIC, PAGE_SIZE);
258
259	/* Current guest paging mode. */
260	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
261
262	#ifdef LOG_ENABLED
263	SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x)\n", pVM, pVCpu->hwaccm.s.vmx.pVMCS, (uint32_t)pVCpu->hwaccm.s.vmx.pVMCSPhys);
264	#endif
265	}
266
267	return VINF_SUCCESS;
268	}
269
270	/**
271	* Does Ring-0 per VM VT-x termination.
272	*
273	* @returns VBox status code.
274	* @param pVM The VM to operate on.
275	*/
276	VMMR0DECL(int) VMXR0TermVM(PVM pVM)
277	{
278	for (unsigned i=0;i<pVM->cCPUs;i++)
279	{
280	PVMCPU pVCpu = &pVM->aCpus[i];
281
282	if (pVCpu->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
283	{
284	RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjVMCS, false);
285	pVCpu->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
286	pVCpu->hwaccm.s.vmx.pVMCS = 0;
287	pVCpu->hwaccm.s.vmx.pVMCSPhys = 0;
288	}
289	if (pVCpu->hwaccm.s.vmx.pMemObjVAPIC != NIL_RTR0MEMOBJ)
290	{
291	RTR0MemObjFree(pVCpu->hwaccm.s.vmx.pMemObjVAPIC, false);
292	pVCpu->hwaccm.s.vmx.pMemObjVAPIC = NIL_RTR0MEMOBJ;
293	pVCpu->hwaccm.s.vmx.pVAPIC = 0;
294	pVCpu->hwaccm.s.vmx.pVAPICPhys = 0;
295	}
296	}
297	if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
298	{
299	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
300	pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
301	pVM->hwaccm.s.vmx.pAPIC = 0;
302	pVM->hwaccm.s.vmx.pAPICPhys = 0;
303	}
304	if (pVM->hwaccm.s.vmx.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
305	{
306	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjMSRBitmap, false);
307	pVM->hwaccm.s.vmx.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
308	pVM->hwaccm.s.vmx.pMSRBitmap = 0;
309	pVM->hwaccm.s.vmx.pMSRBitmapPhys = 0;
310	}
311	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
312	if (pVM->hwaccm.s.vmx.pMemObjScratch != NIL_RTR0MEMOBJ)
313	{
314	ASMMemZero32(pVM->hwaccm.s.vmx.pScratch, PAGE_SIZE);
315	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjScratch, false);
316	pVM->hwaccm.s.vmx.pMemObjScratch = NIL_RTR0MEMOBJ;
317	pVM->hwaccm.s.vmx.pScratch = 0;
318	pVM->hwaccm.s.vmx.pScratchPhys = 0;
319	}
320	#endif
321	return VINF_SUCCESS;
322	}
323
324	/**
325	* Sets up VT-x for the specified VM
326	*
327	* @returns VBox status code.
328	* @param pVM The VM to operate on.
329	*/
330	VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
331	{
332	int rc = VINF_SUCCESS;
333	uint32_t val;
334
335	AssertReturn(pVM, VERR_INVALID_PARAMETER);
336
337	for (unsigned i=0;i<pVM->cCPUs;i++)
338	{
339	PVMCPU pVCpu = &pVM->aCpus[i];
340
341	Assert(pVCpu->hwaccm.s.vmx.pVMCS);
342
343	/* Set revision dword at the beginning of the VMCS structure. */
344	(uint32_t )pVCpu->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
345
346	/* Clear VM Control Structure. */
347	Log(("pVMCSPhys = %RHp\n", pVCpu->hwaccm.s.vmx.pVMCSPhys));
348	rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
349	if (RT_FAILURE(rc))
350	goto vmx_end;
351
352	/* Activate the VM Control Structure. */
353	rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
354	if (RT_FAILURE(rc))
355	goto vmx_end;
356
357	/* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
358	* Set required bits to one and zero according to the MSR capabilities.
359	*/
360	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
361	/* External and non-maskable interrupts cause VM-exits. */
362	val = val \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
363	val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
364
365	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
366	AssertRC(rc);
367
368	/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
369	* Set required bits to one and zero according to the MSR capabilities.
370	*/
371	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
372	/* Program which event cause VM-exits and which features we want to use. */
373	val = val \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
374	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
375	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
376	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
377	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT
378	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
379
380	/* Without nested paging we should intercept invlpg and cr3 mov instructions. */
381	if (!pVM->hwaccm.s.fNestedPaging)
382	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
383	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
384	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
385
386	/* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
387	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
388	{
389	/* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
390	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
391	Assert(pVM->hwaccm.s.vmx.pAPIC);
392	}
393	else
394	/* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
395	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
396
397	#ifdef VBOX_WITH_VTX_MSR_BITMAPS
398	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
399	{
400	Assert(pVM->hwaccm.s.vmx.pMSRBitmapPhys);
401	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS;
402	}
403	#endif
404
405	/* We will use the secondary control if it's present. */
406	val \|= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
407
408	/* Mask away the bits that the CPU doesn't support */
409	/** @todo make sure they don't conflict with the above requirements. */
410	val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
411	pVCpu->hwaccm.s.vmx.proc_ctls = val;
412
413	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
414	AssertRC(rc);
415
416	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
417	{
418	/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2
419	* Set required bits to one and zero according to the MSR capabilities.
420	*/
421	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
422	val \|= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
423
424	#ifdef HWACCM_VTX_WITH_EPT
425	if (pVM->hwaccm.s.fNestedPaging)
426	val \|= VMX_VMCS_CTRL_PROC_EXEC2_EPT;
427	#endif /* HWACCM_VTX_WITH_EPT */
428	#ifdef HWACCM_VTX_WITH_VPID
429	else
430	if (pVM->hwaccm.s.vmx.fVPID)
431	val \|= VMX_VMCS_CTRL_PROC_EXEC2_VPID;
432	#endif /* HWACCM_VTX_WITH_VPID */
433
434	if (pVM->hwaccm.s.fHasIoApic)
435	val \|= VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC;
436
437	/* Mask away the bits that the CPU doesn't support */
438	/** @todo make sure they don't conflict with the above requirements. */
439	val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
440	pVCpu->hwaccm.s.vmx.proc_ctls2 = val;
441	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS2, val);
442	AssertRC(rc);
443	}
444
445	/* VMX_VMCS_CTRL_CR3_TARGET_COUNT
446	* Set required bits to one and zero according to the MSR capabilities.
447	*/
448	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
449	AssertRC(rc);
450
451	/* Forward all exception except #NM & #PF to the guest.
452	* We always need to check pagefaults since our shadow page table can be out of sync.
453	* And we always lazily sync the FPU & XMM state.
454	*/
455
456	/** @todo Possible optimization:
457	* Keep the FPU and XMM state current in the EM thread. That way there's no need to
458	* lazily sync anything, but the downside is that we can't use the FPU stack or XMM
459	* registers ourselves of course.
460	*
461	* Note: only possible if the current state is actually ours (X86_CR0_TS flag)
462	*/
463
464	/* Don't filter page faults; all of them should cause a switch. */
465	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
466	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
467	AssertRC(rc);
468
469	/* Init TSC offset to zero. */
470	rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
471	AssertRC(rc);
472
473	rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
474	AssertRC(rc);
475
476	rc = VMXWriteVMCS64(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
477	AssertRC(rc);
478
479	/* Set the MSR bitmap address. */
480	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
481	{
482	/* Optional */
483	rc = VMXWriteVMCS64(VMX_VMCS_CTRL_MSR_BITMAP_FULL, pVM->hwaccm.s.vmx.pMSRBitmapPhys);
484	AssertRC(rc);
485	}
486
487	/* Clear MSR controls. */
488	rc = VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
489	rc \|= VMXWriteVMCS64(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
490	rc \|= VMXWriteVMCS64(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
491	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
492	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
493	AssertRC(rc);
494
495	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
496	{
497	Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
498	/* Optional */
499	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
500	rc \|= VMXWriteVMCS64(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hwaccm.s.vmx.pVAPICPhys);
501
502	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
503	rc \|= VMXWriteVMCS64(VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
504
505	AssertRC(rc);
506	}
507
508	/* Set link pointer to -1. Not currently used. */
509	rc = VMXWriteVMCS64(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFFULL);
510	AssertRC(rc);
511
512	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
513	rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
514	AssertRC(rc);
515
516	/* Configure the VMCS read cache. */
517	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
518
519	VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RIP);
520	VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_RSP);
521	VMXSetupCachedReadVMCS(pCache, VMX_VMCS_GUEST_RFLAGS);
522	VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE);
523	VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR0_READ_SHADOW);
524	VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR0);
525	VMXSetupCachedReadVMCS(pCache, VMX_VMCS_CTRL_CR4_READ_SHADOW);
526	VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR4);
527	VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_DR7);
528	VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_SYSENTER_CS);
529	VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_EIP);
530	VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_SYSENTER_ESP);
531	VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_GDTR_LIMIT);
532	VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_GDTR_BASE);
533	VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_GUEST_IDTR_LIMIT);
534	VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_IDTR_BASE);
535
536	VMX_SETUP_SELREG(ES, pCache);
537	VMX_SETUP_SELREG(SS, pCache);
538	VMX_SETUP_SELREG(CS, pCache);
539	VMX_SETUP_SELREG(DS, pCache);
540	VMX_SETUP_SELREG(FS, pCache);
541	VMX_SETUP_SELREG(GS, pCache);
542	VMX_SETUP_SELREG(LDTR, pCache);
543	VMX_SETUP_SELREG(TR, pCache);
544
545	/* Status code VMCS reads. */
546	VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_REASON);
547	VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_VM_INSTR_ERROR);
548	VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_LENGTH);
549	VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE);
550	VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO);
551	VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_EXIT_INSTR_INFO);
552	VMXSetupCachedReadVMCS(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
553	VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_INFO);
554	VMXSetupCachedReadVMCS(pCache, VMX_VMCS32_RO_IDT_ERRCODE);
555
556	if (pVM->hwaccm.s.fNestedPaging)
557	{
558	VMXSetupCachedReadVMCS(pCache, VMX_VMCS64_GUEST_CR3);
559	VMXSetupCachedReadVMCS(pCache, VMX_VMCS_EXIT_PHYS_ADDR_FULL);
560	pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
561	}
562	else
563	pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
564	} /* for each VMCPU */
565
566	/* Choose the right TLB setup function. */
567	if (pVM->hwaccm.s.fNestedPaging)
568	{
569	pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBEPT;
570
571	/* Default values for flushing. */
572	pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
573	pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
574
575	/* If the capabilities specify we can do more, then make use of it. */
576	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
577	pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
578	else
579	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
580	pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
581
582	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
583	pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
584	}
585	#ifdef HWACCM_VTX_WITH_VPID
586	else
587	if (pVM->hwaccm.s.vmx.fVPID)
588	{
589	pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBVPID;
590
591	/* Default values for flushing. */
592	pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_ALL_CONTEXTS;
593	pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_ALL_CONTEXTS;
594
595	/* If the capabilities specify we can do more, then make use of it. */
596	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
597	pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_PAGE;
598	else
599	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
600	pVM->hwaccm.s.vmx.enmFlushPage = VMX_FLUSH_SINGLE_CONTEXT;
601
602	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
603	pVM->hwaccm.s.vmx.enmFlushContext = VMX_FLUSH_SINGLE_CONTEXT;
604	}
605	#endif /* HWACCM_VTX_WITH_VPID */
606	else
607	pVM->hwaccm.s.vmx.pfnSetupTaggedTLB = vmxR0SetupTLBDummy;
608
609	vmx_end:
610	VMXR0CheckError(pVM, &pVM->aCpus[0], rc);
611	return rc;
612	}
613
614
615	/**
616	* Injects an event (trap or external interrupt)
617	*
618	* @returns VBox status code.
619	* @param pVM The VM to operate on.
620	* @param pVCpu The VMCPU to operate on.
621	* @param pCtx CPU Context
622	* @param intInfo VMX interrupt info
623	* @param cbInstr Opcode length of faulting instruction
624	* @param errCode Error code (optional)
625	*/
626	static int VMXR0InjectEvent(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
627	{
628	int rc;
629	uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
630
631	#ifdef VBOX_WITH_STATISTICS
632	STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[iGate & MASK_INJECT_IRQ_STAT]);
633	#endif
634
635	#ifdef VBOX_STRICT
636	if (iGate == 0xE)
637	LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x CR2=%RGv intInfo=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode, pCtx->cr2, intInfo));
638	else
639	if (iGate < 0x20)
640	LogFlow(("VMXR0InjectEvent: Injecting interrupt %d at %RGv error code=%08x\n", iGate, (RTGCPTR)pCtx->rip, errCode));
641	else
642	{
643	LogFlow(("INJ-EI: %x at %RGv\n", iGate, (RTGCPTR)pCtx->rip));
644	Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW \|\| !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
645	Assert(VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW \|\| pCtx->eflags.u32 & X86_EFL_IF);
646	}
647	#endif
648
649	#ifdef HWACCM_VMX_EMULATE_REALMODE
650	if (CPUMIsGuestInRealModeEx(pCtx))
651	{
652	RTGCPHYS GCPhysHandler;
653	uint16_t offset, ip;
654	RTSEL sel;
655
656	/* Injecting events doesn't work right with real mode emulation.
657	* (#GP if we try to inject external hardware interrupts)
658	* Inject the interrupt or trap directly instead.
659	*
660	* ASSUMES no access handlers for the bits we read or write below (should be safe).
661	*/
662	Log(("Manual interrupt/trap '%x' inject (real mode)\n", iGate));
663
664	/* Check if the interrupt handler is present. */
665	if (iGate * 4 + 3 > pCtx->idtr.cbIdt)
666	{
667	Log(("IDT cbIdt violation\n"));
668	if (iGate != X86_XCPT_DF)
669	{
670	RTGCUINTPTR intInfo;
671
672	intInfo = (iGate == X86_XCPT_GP) ? (uint32_t)X86_XCPT_DF : iGate;
673	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
674	intInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
675	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
676
677	return VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0 /* no error code according to the Intel docs */);
678	}
679	Log(("Triple fault -> reset the VM!\n"));
680	return VINF_EM_RESET;
681	}
682	if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
683	\|\| iGate == 3 /* Both #BP and #OF point to the instruction after. */
684	\|\| iGate == 4)
685	{
686	ip = pCtx->ip + cbInstr;
687	}
688	else
689	ip = pCtx->ip;
690
691	/* Read the selector:offset pair of the interrupt handler. */
692	GCPhysHandler = (RTGCPHYS)pCtx->idtr.pIdt + iGate * 4;
693	rc = PGMPhysSimpleReadGCPhys(pVM, &offset, GCPhysHandler, sizeof(offset)); AssertRC(rc);
694	rc = PGMPhysSimpleReadGCPhys(pVM, &sel, GCPhysHandler + 2, sizeof(sel)); AssertRC(rc);
695
696	LogFlow(("IDT handler %04X:%04X\n", sel, offset));
697
698	/* Construct the stack frame. */
699	/** @todo should check stack limit. */
700	pCtx->sp -= 2;
701	LogFlow(("ss:sp %04X:%04X eflags=%x\n", pCtx->ss, pCtx->sp, pCtx->eflags.u));
702	rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->eflags, sizeof(uint16_t)); AssertRC(rc);
703	pCtx->sp -= 2;
704	LogFlow(("ss:sp %04X:%04X cs=%x\n", pCtx->ss, pCtx->sp, pCtx->cs));
705	rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &pCtx->cs, sizeof(uint16_t)); AssertRC(rc);
706	pCtx->sp -= 2;
707	LogFlow(("ss:sp %04X:%04X ip=%x\n", pCtx->ss, pCtx->sp, ip));
708	rc = PGMPhysSimpleWriteGCPhys(pVM, pCtx->ssHid.u64Base + pCtx->sp, &ip, sizeof(ip)); AssertRC(rc);
709
710	/* Update the CPU state for executing the handler. */
711	pCtx->rip = offset;
712	pCtx->cs = sel;
713	pCtx->csHid.u64Base = sel << 4;
714	pCtx->eflags.u &= ~(X86_EFL_IF\|X86_EFL_TF\|X86_EFL_RF\|X86_EFL_AC);
715
716	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_SEGMENT_REGS;
717	return VINF_SUCCESS;
718	}
719	#endif /* HWACCM_VMX_EMULATE_REALMODE */
720
721	/* Set event injection state. */
722	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO, intInfo \| (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT));
723
724	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
725	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
726
727	AssertRC(rc);
728	return rc;
729	}
730
731
732	/**
733	* Checks for pending guest interrupts and injects them
734	*
735	* @returns VBox status code.
736	* @param pVM The VM to operate on.
737	* @param pVCpu The VMCPU to operate on.
738	* @param pCtx CPU Context
739	*/
740	static int VMXR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, CPUMCTX *pCtx)
741	{
742	int rc;
743
744	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
745	if (pVCpu->hwaccm.s.Event.fPending)
746	{
747	Log(("CPU%d: Reinjecting event %RX64 %08x at %RGv cr2=%RX64\n", pVCpu->idCpu, pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip, pCtx->cr2));
748	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
749	rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, pVCpu->hwaccm.s.Event.intInfo, 0, pVCpu->hwaccm.s.Event.errCode);
750	AssertRC(rc);
751
752	pVCpu->hwaccm.s.Event.fPending = false;
753	return VINF_SUCCESS;
754	}
755
756	if (pVM->hwaccm.s.fInjectNMI)
757	{
758	RTGCUINTPTR intInfo;
759
760	intInfo = X86_XCPT_NMI;
761	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
762	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
763
764	rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, 0);
765	AssertRC(rc);
766
767	pVM->hwaccm.s.fInjectNMI = false;
768	return VINF_SUCCESS;
769	}
770
771	/* When external interrupts are pending, we should exit the VM when IF is set. */
772	if ( !TRPMHasTrap(pVCpu)
773	&& VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC\|VMCPU_FF_INTERRUPT_PIC)))
774	{
775	if (!(pCtx->eflags.u32 & X86_EFL_IF))
776	{
777	if (!(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT))
778	{
779	LogFlow(("Enable irq window exit!\n"));
780	pVCpu->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
781	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
782	AssertRC(rc);
783	}
784	/* else nothing to do but wait */
785	}
786	else
787	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
788	{
789	uint8_t u8Interrupt;
790
791	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
792	Log(("CPU%d: Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc cs:rip=%04X:%RGv\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc, pCtx->cs, (RTGCPTR)pCtx->rip));
793	if (RT_SUCCESS(rc))
794	{
795	rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
796	AssertRC(rc);
797	}
798	else
799	{
800	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
801	Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC\|VMCPU_FF_INTERRUPT_PIC)));
802	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
803	/* Just continue */
804	}
805	}
806	else
807	Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS!!\n", (RTGCPTR)pCtx->rip));
808	}
809
810	#ifdef VBOX_STRICT
811	if (TRPMHasTrap(pVCpu))
812	{
813	uint8_t u8Vector;
814	rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
815	AssertRC(rc);
816	}
817	#endif
818
819	if ( (pCtx->eflags.u32 & X86_EFL_IF)
820	&& (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
821	&& TRPMHasTrap(pVCpu)
822	)
823	{
824	uint8_t u8Vector;
825	int rc;
826	TRPMEVENT enmType;
827	RTGCUINTPTR intInfo;
828	RTGCUINT errCode;
829
830	/* If a new event is pending, then dispatch it now. */
831	rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &errCode, 0);
832	AssertRC(rc);
833	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
834	Assert(enmType != TRPM_SOFTWARE_INT);
835
836	/* Clear the pending trap. */
837	rc = TRPMResetTrap(pVCpu);
838	AssertRC(rc);
839
840	intInfo = u8Vector;
841	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
842
843	if (enmType == TRPM_TRAP)
844	{
845	switch (u8Vector) {
846	case 8:
847	case 10:
848	case 11:
849	case 12:
850	case 13:
851	case 14:
852	case 17:
853	/* Valid error codes. */
854	intInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
855	break;
856	default:
857	break;
858	}
859	if (u8Vector == X86_XCPT_BP \|\| u8Vector == X86_XCPT_OF)
860	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
861	else
862	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
863	}
864	else
865	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
866
867	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
868	rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, 0, errCode);
869	AssertRC(rc);
870	} /* if (interrupts can be dispatched) */
871
872	return VINF_SUCCESS;
873	}
874
875	/**
876	* Save the host state
877	*
878	* @returns VBox status code.
879	* @param pVM The VM to operate on.
880	* @param pVCpu The VMCPU to operate on.
881	*/
882	VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
883	{
884	int rc = VINF_SUCCESS;
885
886	/*
887	* Host CPU Context
888	*/
889	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
890	{
891	RTIDTR idtr;
892	RTGDTR gdtr;
893	RTSEL SelTR;
894	PX86DESCHC pDesc;
895	uintptr_t trBase;
896	RTSEL cs;
897	RTSEL ss;
898	uint64_t cr3;
899
900	/* Control registers */
901	rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
902	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
903	if (VMX_IS_64BIT_HOST_MODE())
904	{
905	cr3 = hwaccmR0Get64bitCR3();
906	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_CR3, cr3);
907	}
908	else
909	#endif
910	{
911	cr3 = ASMGetCR3();
912	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR3, cr3);
913	}
914	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
915	AssertRC(rc);
916	Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
917	Log2(("VMX_VMCS_HOST_CR3 %08RX64\n", cr3));
918	Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
919
920	/* Selector registers. */
921	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
922	if (VMX_IS_64BIT_HOST_MODE())
923	{
924	cs = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelCS;
925	ss = (RTSEL)(uintptr_t)&SUPR0Abs64bitKernelSS;
926	}
927	else
928	{
929	/* sysenter loads LDT cs & ss, VMX doesn't like this. Load the GDT ones (safe). */
930	cs = (RTSEL)(uintptr_t)&SUPR0AbsKernelCS;
931	ss = (RTSEL)(uintptr_t)&SUPR0AbsKernelSS;
932	}
933	#else
934	cs = ASMGetCS();
935	ss = ASMGetSS();
936	#endif
937	Assert(!(cs & X86_SEL_LDT)); Assert((cs & X86_SEL_RPL) == 0);
938	Assert(!(ss & X86_SEL_LDT)); Assert((ss & X86_SEL_RPL) == 0);
939	rc = VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_CS, cs);
940	/* Note: VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
941	rc \|= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_DS, 0);
942	rc \|= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_ES, 0);
943	#if HC_ARCH_BITS == 32
944	if (!VMX_IS_64BIT_HOST_MODE())
945	{
946	rc \|= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_FS, 0);
947	rc \|= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_GS, 0);
948	}
949	#endif
950	rc \|= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_SS, ss);
951	SelTR = ASMGetTR();
952	rc \|= VMXWriteVMCS(VMX_VMCS16_HOST_FIELD_TR, SelTR);
953	AssertRC(rc);
954	Log2(("VMX_VMCS_HOST_FIELD_CS %08x (%08x)\n", cs, ASMGetSS()));
955	Log2(("VMX_VMCS_HOST_FIELD_DS 00000000 (%08x)\n", ASMGetDS()));
956	Log2(("VMX_VMCS_HOST_FIELD_ES 00000000 (%08x)\n", ASMGetES()));
957	Log2(("VMX_VMCS_HOST_FIELD_FS 00000000 (%08x)\n", ASMGetFS()));
958	Log2(("VMX_VMCS_HOST_FIELD_GS 00000000 (%08x)\n", ASMGetGS()));
959	Log2(("VMX_VMCS_HOST_FIELD_SS %08x (%08x)\n", ss, ASMGetSS()));
960	Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
961
962	/* GDTR & IDTR */
963	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
964	if (VMX_IS_64BIT_HOST_MODE())
965	{
966	X86XDTR64 gdtr64, idtr64;
967	hwaccmR0Get64bitGDTRandIDTR(&gdtr64, &idtr64);
968	rc = VMXWriteVMCS64(VMX_VMCS_HOST_GDTR_BASE, gdtr64.uAddr);
969	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_IDTR_BASE, gdtr64.uAddr);
970	AssertRC(rc);
971	Log2(("VMX_VMCS_HOST_GDTR_BASE %RX64\n", gdtr64.uAddr));
972	Log2(("VMX_VMCS_HOST_IDTR_BASE %RX64\n", idtr64.uAddr));
973	gdtr.cbGdt = gdtr64.cb;
974	gdtr.pGdt = (uintptr_t)gdtr64.uAddr;
975	}
976	else
977	#endif
978	{
979	ASMGetGDTR(&gdtr);
980	rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
981	ASMGetIDTR(&idtr);
982	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
983	AssertRC(rc);
984	Log2(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", gdtr.pGdt));
985	Log2(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", idtr.pIdt));
986	}
987
988
989	/* Save the base address of the TR selector. */
990	if (SelTR > gdtr.cbGdt)
991	{
992	AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
993	return VERR_VMX_INVALID_HOST_STATE;
994	}
995
996	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
997	if (VMX_IS_64BIT_HOST_MODE())
998	{
999	pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC]; /// ????
1000	uint64_t trBase64 = X86DESC64_BASE(*(PX86DESC64)pDesc);
1001	rc = VMXWriteVMCS64(VMX_VMCS_HOST_TR_BASE, trBase64);
1002	Log2(("VMX_VMCS_HOST_TR_BASE %RX64\n", trBase64));
1003	AssertRC(rc);
1004	}
1005	else
1006	#endif
1007	{
1008	pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
1009	#if HC_ARCH_BITS == 64
1010	trBase = X86DESC64_BASE(*pDesc);
1011	#else
1012	trBase = X86DESC_BASE(*pDesc);
1013	#endif
1014	rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
1015	AssertRC(rc);
1016	Log2(("VMX_VMCS_HOST_TR_BASE %RHv\n", trBase));
1017	}
1018
1019	/* FS and GS base. */
1020	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1021	if (VMX_IS_64BIT_HOST_MODE())
1022	{
1023	Log2(("MSR_K8_FS_BASE = %RX64\n", ASMRdMsr(MSR_K8_FS_BASE)));
1024	Log2(("MSR_K8_GS_BASE = %RX64\n", ASMRdMsr(MSR_K8_GS_BASE)));
1025	rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
1026	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
1027	}
1028	#endif
1029	AssertRC(rc);
1030
1031	/* Sysenter MSRs. */
1032	/** @todo expensive!! */
1033	rc = VMXWriteVMCS(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
1034	Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
1035	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1036	if (VMX_IS_64BIT_HOST_MODE())
1037	{
1038	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1039	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1040	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1041	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1042	}
1043	else
1044	{
1045	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1046	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1047	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1048	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1049	}
1050	#elif HC_ARCH_BITS == 32
1051	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
1052	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
1053	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
1054	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX32\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
1055	#else
1056	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
1057	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %RX64\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
1058	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
1059	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
1060	#endif
1061	AssertRC(rc);
1062
1063	#if 0 /* @todo deal with 32/64 */
1064	/* Restore the host EFER - on CPUs that support it. */
1065	if (pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1 & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1066	{
1067	uint64_t msrEFER = ASMRdMsr(MSR_IA32_EFER);
1068	rc = VMXWriteVMCS64(VMX_VMCS_HOST_FIELD_EFER_FULL, msrEFER);
1069	AssertRC(rc);
1070	}
1071	#endif
1072	pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
1073	}
1074	return rc;
1075	}
1076
1077	/**
1078	* Prefetch the 4 PDPT pointers (PAE and nested paging only)
1079	*
1080	* @param pVM The VM to operate on.
1081	* @param pVCpu The VMCPU to operate on.
1082	* @param pCtx Guest context
1083	*/
1084	static void vmxR0PrefetchPAEPdptrs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1085	{
1086	if (CPUMIsGuestInPAEModeEx(pCtx))
1087	{
1088	X86PDPE Pdpe;
1089
1090	for (unsigned i=0;i<4;i++)
1091	{
1092	Pdpe = PGMGstGetPaePDPtr(pVCpu, i);
1093	int rc = VMXWriteVMCS64(VMX_VMCS_GUEST_PDPTR0_FULL + i*2, Pdpe.u);
1094	AssertRC(rc);
1095	}
1096	}
1097	}
1098
1099	/**
1100	* Update the exception bitmap according to the current CPU state
1101	*
1102	* @param pVM The VM to operate on.
1103	* @param pVCpu The VMCPU to operate on.
1104	* @param pCtx Guest context
1105	*/
1106	static void vmxR0UpdateExceptionBitmap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1107	{
1108	uint32_t u32TrapMask;
1109	Assert(pCtx);
1110
1111	u32TrapMask = HWACCM_VMX_TRAP_MASK;
1112	#ifndef DEBUG
1113	if (pVM->hwaccm.s.fNestedPaging)
1114	u32TrapMask &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
1115	#endif
1116
1117	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
1118	if ( CPUMIsGuestFPUStateActive(pVCpu) == true
1119	&& !(pCtx->cr0 & X86_CR0_NE)
1120	&& !pVCpu->hwaccm.s.fFPUOldStyleOverride)
1121	{
1122	u32TrapMask \|= RT_BIT(X86_XCPT_MF);
1123	pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
1124	}
1125
1126	#ifdef DEBUG /* till after branching, enable it by default then. */
1127	/* Intercept X86_XCPT_DB if stepping is enabled */
1128	if (DBGFIsStepping(pVCpu))
1129	u32TrapMask \|= RT_BIT(X86_XCPT_DB);
1130	/** @todo Don't trap it unless the debugger has armed breakpoints. */
1131	u32TrapMask \|= RT_BIT(X86_XCPT_BP);
1132	#endif
1133
1134	#ifdef VBOX_STRICT
1135	Assert(u32TrapMask & RT_BIT(X86_XCPT_GP));
1136	#endif
1137
1138	# ifdef HWACCM_VMX_EMULATE_REALMODE
1139	/* Intercept all exceptions in real mode as none of them can be injected directly (#GP otherwise). */
1140	if (CPUMIsGuestInRealModeEx(pCtx) && pVM->hwaccm.s.vmx.pRealModeTSS)
1141	u32TrapMask \|= HWACCM_VMX_TRAP_MASK_REALMODE;
1142	# endif /* HWACCM_VMX_EMULATE_REALMODE */
1143
1144	int rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, u32TrapMask);
1145	AssertRC(rc);
1146	}
1147
1148	/**
1149	* Loads the guest state
1150	*
1151	* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
1152	*
1153	* @returns VBox status code.
1154	* @param pVM The VM to operate on.
1155	* @param pVCpu The VMCPU to operate on.
1156	* @param pCtx Guest context
1157	*/
1158	VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1159	{
1160	int rc = VINF_SUCCESS;
1161	RTGCUINTPTR val;
1162	X86EFLAGS eflags;
1163
1164	/* VMX_VMCS_CTRL_ENTRY_CONTROLS
1165	* Set required bits to one and zero according to the MSR capabilities.
1166	*/
1167	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
1168	/* Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1169	val \|= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG;
1170	#if 0 /* @todo deal with 32/64 */
1171	/* Required for the EFER write below, not supported on all CPUs. */
1172	val \|= VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR;
1173	#endif
1174	/* 64 bits guest mode? */
1175	if (CPUMIsGuestInLongModeEx(pCtx))
1176	val \|= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
1177	/* else Must be zero when AMD64 is not available. */
1178
1179	/* Mask away the bits that the CPU doesn't support */
1180	val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
1181	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
1182	AssertRC(rc);
1183
1184	/* VMX_VMCS_CTRL_EXIT_CONTROLS
1185	* Set required bits to one and zero according to the MSR capabilities.
1186	*/
1187	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
1188
1189	/* Save debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the 'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
1190	#if 0 /* @todo deal with 32/64 */
1191	val \|= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG \| VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR;
1192	#else
1193	val \|= VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG;
1194	#endif
1195
1196	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1197	if (VMX_IS_64BIT_HOST_MODE())
1198	val \|= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
1199	/* else: Must be zero when AMD64 is not available. */
1200	#elif HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1201	if (CPUMIsGuestInLongModeEx(pCtx))
1202	val \|= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64; /* our switcher goes to long mode */
1203	else
1204	Assert(!(val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64));
1205	#endif
1206	val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
1207	/* Don't acknowledge external interrupts on VM-exit. */
1208	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
1209	AssertRC(rc);
1210
1211	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1212	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
1213	{
1214	#ifdef HWACCM_VMX_EMULATE_REALMODE
1215	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1216	{
1217	PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
1218	if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode != enmGuestMode)
1219	{
1220	/* Correct weird requirements for switching to protected mode. */
1221	if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1222	&& enmGuestMode >= PGMMODE_PROTECTED)
1223	{
1224	/* Flush the recompiler code cache as it's not unlikely
1225	* the guest will rewrite code it will later execute in real
1226	* mode (OpenBSD 4.0 is one such example)
1227	*/
1228	REMFlushTBs(pVM);
1229
1230	/* DPL of all hidden selector registers must match the current CPL (0). */
1231	pCtx->csHid.Attr.n.u2Dpl = 0;
1232	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_CODE \| X86_SEL_TYPE_RW_ACC;
1233
1234	pCtx->dsHid.Attr.n.u2Dpl = 0;
1235	pCtx->esHid.Attr.n.u2Dpl = 0;
1236	pCtx->fsHid.Attr.n.u2Dpl = 0;
1237	pCtx->gsHid.Attr.n.u2Dpl = 0;
1238	pCtx->ssHid.Attr.n.u2Dpl = 0;
1239
1240	/* The limit must correspond to the granularity bit. */
1241	if (!pCtx->csHid.Attr.n.u1Granularity)
1242	pCtx->csHid.u32Limit &= 0xffff;
1243	if (!pCtx->dsHid.Attr.n.u1Granularity)
1244	pCtx->dsHid.u32Limit &= 0xffff;
1245	if (!pCtx->esHid.Attr.n.u1Granularity)
1246	pCtx->esHid.u32Limit &= 0xffff;
1247	if (!pCtx->fsHid.Attr.n.u1Granularity)
1248	pCtx->fsHid.u32Limit &= 0xffff;
1249	if (!pCtx->gsHid.Attr.n.u1Granularity)
1250	pCtx->gsHid.u32Limit &= 0xffff;
1251	if (!pCtx->ssHid.Attr.n.u1Granularity)
1252	pCtx->ssHid.u32Limit &= 0xffff;
1253	}
1254	else
1255	/* Switching from protected mode to real mode. */
1256	if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode >= PGMMODE_PROTECTED
1257	&& enmGuestMode == PGMMODE_REAL)
1258	{
1259	/* The limit must also be set to 0xffff. */
1260	pCtx->csHid.u32Limit = 0xffff;
1261	pCtx->dsHid.u32Limit = 0xffff;
1262	pCtx->esHid.u32Limit = 0xffff;
1263	pCtx->fsHid.u32Limit = 0xffff;
1264	pCtx->gsHid.u32Limit = 0xffff;
1265	pCtx->ssHid.u32Limit = 0xffff;
1266
1267	Assert(pCtx->csHid.u64Base <= 0xfffff);
1268	Assert(pCtx->dsHid.u64Base <= 0xfffff);
1269	Assert(pCtx->esHid.u64Base <= 0xfffff);
1270	Assert(pCtx->fsHid.u64Base <= 0xfffff);
1271	Assert(pCtx->gsHid.u64Base <= 0xfffff);
1272	}
1273	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = enmGuestMode;
1274	}
1275	else
1276	/* VT-x will fail with a guest invalid state otherwise... (CPU state after a reset) */
1277	if ( CPUMIsGuestInRealModeEx(pCtx)
1278	&& pCtx->csHid.u64Base == 0xffff0000)
1279	{
1280	pCtx->csHid.u64Base = 0xf0000;
1281	pCtx->cs = 0xf000;
1282	}
1283	}
1284	#endif /* HWACCM_VMX_EMULATE_REALMODE */
1285
1286	VMX_WRITE_SELREG(ES, es);
1287	AssertRC(rc);
1288
1289	VMX_WRITE_SELREG(CS, cs);
1290	AssertRC(rc);
1291
1292	VMX_WRITE_SELREG(SS, ss);
1293	AssertRC(rc);
1294
1295	VMX_WRITE_SELREG(DS, ds);
1296	AssertRC(rc);
1297
1298	/* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
1299	VMX_WRITE_SELREG(FS, fs);
1300	AssertRC(rc);
1301
1302	VMX_WRITE_SELREG(GS, gs);
1303	AssertRC(rc);
1304	}
1305
1306	/* Guest CPU context: LDTR. */
1307	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
1308	{
1309	if (pCtx->ldtr == 0)
1310	{
1311	rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, 0);
1312	rc \|= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, 0);
1313	rc \|= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, 0);
1314	/* Note: vmlaunch will fail with 0 or just 0x02. No idea why. */
1315	rc \|= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
1316	}
1317	else
1318	{
1319	rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_LDTR, pCtx->ldtr);
1320	rc \|= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
1321	rc \|= VMXWriteVMCS64(VMX_VMCS64_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
1322	rc \|= VMXWriteVMCS(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
1323	}
1324	AssertRC(rc);
1325	}
1326	/* Guest CPU context: TR. */
1327	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
1328	{
1329	#ifdef HWACCM_VMX_EMULATE_REALMODE
1330	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1331	if (CPUMIsGuestInRealModeEx(pCtx))
1332	{
1333	RTGCPHYS GCPhys;
1334
1335	/* We convert it here every time as pci regions could be reconfigured. */
1336	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1337	AssertRC(rc);
1338
1339	rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, 0);
1340	rc \|= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, HWACCM_VTX_TSS_SIZE);
1341	rc \|= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, GCPhys /* phys = virt in this mode */);
1342
1343	X86DESCATTR attr;
1344
1345	attr.u = 0;
1346	attr.n.u1Present = 1;
1347	attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1348	val = attr.u;
1349	}
1350	else
1351	#endif /* HWACCM_VMX_EMULATE_REALMODE */
1352	{
1353	rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_TR, pCtx->tr);
1354	rc \|= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
1355	rc \|= VMXWriteVMCS64(VMX_VMCS64_GUEST_TR_BASE, pCtx->trHid.u64Base);
1356
1357	val = pCtx->trHid.Attr.u;
1358
1359	/* The TSS selector must be busy. */
1360	if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
1361	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_286_TSS_BUSY;
1362	else
1363	/* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
1364	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_386_TSS_BUSY;
1365
1366	}
1367	rc \|= VMXWriteVMCS(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, val);
1368	AssertRC(rc);
1369	}
1370	/* Guest CPU context: GDTR. */
1371	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
1372	{
1373	rc = VMXWriteVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
1374	rc \|= VMXWriteVMCS64(VMX_VMCS64_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
1375	AssertRC(rc);
1376	}
1377	/* Guest CPU context: IDTR. */
1378	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
1379	{
1380	rc = VMXWriteVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
1381	rc \|= VMXWriteVMCS64(VMX_VMCS64_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
1382	AssertRC(rc);
1383	}
1384
1385	/*
1386	* Sysenter MSRs (unconditional)
1387	*/
1388	rc = VMXWriteVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
1389	rc \|= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
1390	rc \|= VMXWriteVMCS64(VMX_VMCS64_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
1391	AssertRC(rc);
1392
1393	/* Control registers */
1394	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
1395	{
1396	val = pCtx->cr0;
1397	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
1398	Log2(("Guest CR0-shadow %08x\n", val));
1399	if (CPUMIsGuestFPUStateActive(pVCpu) == false)
1400	{
1401	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
1402	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
1403	}
1404	else
1405	{
1406	/** @todo check if we support the old style mess correctly. */
1407	if (!(val & X86_CR0_NE))
1408	Log(("Forcing X86_CR0_NE!!!\n"));
1409
1410	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
1411	}
1412	/* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
1413	val \|= X86_CR0_PE \| X86_CR0_PG;
1414	if (pVM->hwaccm.s.fNestedPaging)
1415	{
1416	if (CPUMIsGuestInPagedProtectedModeEx(pCtx))
1417	{
1418	/* Disable cr3 read/write monitoring as we don't need it for EPT. */
1419	pVCpu->hwaccm.s.vmx.proc_ctls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1420	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
1421	}
1422	else
1423	{
1424	/* Reenable cr3 read/write monitoring as our identity mapped page table is active. */
1425	pVCpu->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
1426	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
1427	}
1428	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1429	AssertRC(rc);
1430	}
1431	else
1432	{
1433	/* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
1434	val \|= X86_CR0_WP;
1435	}
1436
1437	/* Always enable caching. */
1438	val &= ~(X86_CR0_CD\|X86_CR0_NW);
1439
1440	rc \|= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR0, val);
1441	Log2(("Guest CR0 %08x\n", val));
1442	/* CR0 flags owned by the host; if the guests attempts to change them, then
1443	* the VM will exit.
1444	*/
1445	val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
1446	\| X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
1447	\| X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
1448	\| X86_CR0_TS
1449	\| X86_CR0_ET /* Bit not restored during VM-exit! */
1450	\| X86_CR0_CD /* Bit not restored during VM-exit! */
1451	\| X86_CR0_NW /* Bit not restored during VM-exit! */
1452	\| X86_CR0_NE
1453	\| X86_CR0_MP;
1454	pVCpu->hwaccm.s.vmx.cr0_mask = val;
1455
1456	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
1457	Log2(("Guest CR0-mask %08x\n", val));
1458	AssertRC(rc);
1459	}
1460	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
1461	{
1462	/* CR4 */
1463	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
1464	Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
1465	/* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
1466	val = pCtx->cr4 \| (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
1467
1468	if (!pVM->hwaccm.s.fNestedPaging)
1469	{
1470	switch(pVCpu->hwaccm.s.enmShadowMode)
1471	{
1472	case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
1473	case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
1474	case PGMMODE_32_BIT: /* 32-bit paging. */
1475	val &= ~X86_CR4_PAE;
1476	break;
1477
1478	case PGMMODE_PAE: /* PAE paging. */
1479	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1480	/** @todo use normal 32 bits paging */
1481	val \|= X86_CR4_PAE;
1482	break;
1483
1484	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1485	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1486	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1487	break;
1488	#else
1489	AssertFailed();
1490	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1491	#endif
1492	default: /* shut up gcc */
1493	AssertFailed();
1494	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1495	}
1496	}
1497	else
1498	if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1499	{
1500	/* We use 4 MB pages in our identity mapping page table for real and protected mode without paging. */
1501	val \|= X86_CR4_PSE;
1502	/* Our identity mapping is a 32 bits page directory. */
1503	val &= ~X86_CR4_PAE;
1504	}
1505
1506	rc \|= VMXWriteVMCS64(VMX_VMCS64_GUEST_CR4, val);
1507	Log2(("Guest CR4 %08x\n", val));
1508	/* CR4 flags owned by the host; if the guests attempts to change them, then
1509	* the VM will exit.
1510	*/
1511	val = 0
1512	\| X86_CR4_PAE
1513	\| X86_CR4_PGE
1514	\| X86_CR4_PSE
1515	\| X86_CR4_VMXE;
1516	pVCpu->hwaccm.s.vmx.cr4_mask = val;
1517
1518	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
1519	Log2(("Guest CR4-mask %08x\n", val));
1520	AssertRC(rc);
1521	}
1522
1523	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
1524	{
1525	if (pVM->hwaccm.s.fNestedPaging)
1526	{
1527	Assert(PGMGetHyperCR3(pVCpu));
1528	pVCpu->hwaccm.s.vmx.GCPhysEPTP = PGMGetHyperCR3(pVCpu);
1529
1530	Assert(!(pVCpu->hwaccm.s.vmx.GCPhysEPTP & 0xfff));
1531	/** @todo Check the IA32_VMX_EPT_VPID_CAP MSR for other supported memory types. */
1532	pVCpu->hwaccm.s.vmx.GCPhysEPTP \|= VMX_EPT_MEMTYPE_WB
1533	\| (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
1534
1535	rc = VMXWriteVMCS64(VMX_VMCS_CTRL_EPTP_FULL, pVCpu->hwaccm.s.vmx.GCPhysEPTP);
1536	AssertRC(rc);
1537
1538	if (!CPUMIsGuestInPagedProtectedModeEx(pCtx))
1539	{
1540	RTGCPHYS GCPhys;
1541
1542	/* We convert it here every time as pci regions could be reconfigured. */
1543	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1544	AssertRC(rc);
1545
1546	/* We use our identity mapping page table here as we need to map guest virtual to guest physical addresses; EPT will
1547	* take care of the translation to host physical addresses.
1548	*/
1549	val = GCPhys;
1550	}
1551	else
1552	{
1553	/* Save the real guest CR3 in VMX_VMCS_GUEST_CR3 */
1554	val = pCtx->cr3;
1555	/* Prefetch the four PDPT entries in PAE mode. */
1556	vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1557	}
1558	}
1559	else
1560	{
1561	val = PGMGetHyperCR3(pVCpu);
1562	Assert(val \|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1563	}
1564
1565	/* Save our shadow CR3 register. */
1566	rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_CR3, val);
1567	AssertRC(rc);
1568	}
1569
1570	/* Debug registers. */
1571	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
1572	{
1573	pCtx->dr[6] \|= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
1574	pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
1575
1576	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1577	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
1578	pCtx->dr[7] \|= 0x400; /* must be one */
1579
1580	/* Resync DR7 */
1581	rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
1582	AssertRC(rc);
1583
1584	/* Sync the debug state now if any breakpoint is armed. */
1585	if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK\|X86_DR7_GD))
1586	&& !CPUMIsGuestDebugStateActive(pVCpu)
1587	&& !DBGFIsStepping(pVCpu))
1588	{
1589	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
1590
1591	/* Disable drx move intercepts. */
1592	pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
1593	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1594	AssertRC(rc);
1595
1596	/* Save the host and load the guest debug state. */
1597	rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
1598	AssertRC(rc);
1599	}
1600
1601	/* IA32_DEBUGCTL MSR. */
1602	rc = VMXWriteVMCS64(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
1603	AssertRC(rc);
1604
1605	/** @todo do we really ever need this? */
1606	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
1607	AssertRC(rc);
1608	}
1609
1610	/* EIP, ESP and EFLAGS */
1611	rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_RIP, pCtx->rip);
1612	rc \|= VMXWriteVMCS64(VMX_VMCS64_GUEST_RSP, pCtx->rsp);
1613	AssertRC(rc);
1614
1615	/* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
1616	eflags = pCtx->eflags;
1617	eflags.u32 &= VMX_EFLAGS_RESERVED_0;
1618	eflags.u32 \|= VMX_EFLAGS_RESERVED_1;
1619
1620	#ifdef HWACCM_VMX_EMULATE_REALMODE
1621	/* Real mode emulation using v86 mode. */
1622	if (CPUMIsGuestInRealModeEx(pCtx))
1623	{
1624	pVCpu->hwaccm.s.vmx.RealMode.eflags = eflags;
1625
1626	eflags.Bits.u1VM = 1;
1627	eflags.Bits.u2IOPL = 0; /* must always be 0 or else certain instructions won't cause faults. */
1628	}
1629	#endif /* HWACCM_VMX_EMULATE_REALMODE */
1630	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
1631	AssertRC(rc);
1632
1633	/* TSC offset. */
1634	uint64_t u64TSCOffset;
1635
1636	if (TMCpuTickCanUseRealTSC(pVCpu, &u64TSCOffset))
1637	{
1638	/* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
1639	rc = VMXWriteVMCS64(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
1640	AssertRC(rc);
1641
1642	pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1643	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1644	AssertRC(rc);
1645	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
1646	}
1647	else
1648	{
1649	pVCpu->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
1650	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
1651	AssertRC(rc);
1652	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
1653	}
1654
1655	/* 64 bits guest mode? */
1656	if (CPUMIsGuestInLongModeEx(pCtx))
1657	{
1658	#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
1659	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1660	#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1661	pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
1662	#else
1663	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1664	if (!pVM->hwaccm.s.fAllow64BitGuests)
1665	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1666	# endif
1667	pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
1668	#endif
1669	/* Unconditionally update these as wrmsr might have changed them. */
1670	rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1671	AssertRC(rc);
1672	rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1673	AssertRC(rc);
1674	}
1675	else
1676	{
1677	pVCpu->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1678	}
1679
1680	#if 0 /* @todo deal with 32/64 */
1681	/* Unconditionally update the guest EFER - on CPUs that supports it. */
1682	if (pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1 & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
1683	{
1684	rc = VMXWriteVMCS64(VMX_VMCS_GUEST_EFER_FULL, pCtx->msrEFER);
1685	AssertRC(rc);
1686	}
1687	#endif
1688
1689	vmxR0UpdateExceptionBitmap(pVM, pVCpu, pCtx);
1690
1691	/* Done. */
1692	pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1693
1694	return rc;
1695	}
1696
1697	/**
1698	* Syncs back the guest state
1699	*
1700	* @returns VBox status code.
1701	* @param pVM The VM to operate on.
1702	* @param pVCpu The VMCPU to operate on.
1703	* @param pCtx Guest context
1704	*/
1705	DECLINLINE(int) VMXR0SaveGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1706	{
1707	RTGCUINTREG val, valShadow;
1708	RTGCUINTPTR uInterruptState;
1709	int rc;
1710
1711	/* Let's first sync back eip, esp, and eflags. */
1712	rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RIP, &val);
1713	AssertRC(rc);
1714	pCtx->rip = val;
1715	rc = VMXReadCachedVMCS(VMX_VMCS64_GUEST_RSP, &val);
1716	AssertRC(rc);
1717	pCtx->rsp = val;
1718	rc = VMXReadCachedVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1719	AssertRC(rc);
1720	pCtx->eflags.u32 = val;
1721
1722	/* Take care of instruction fusing (sti, mov ss) */
1723	rc \|= VMXReadCachedVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &val);
1724	uInterruptState = val;
1725	if (uInterruptState != 0)
1726	{
1727	Assert(uInterruptState <= 2); /* only sti & mov ss */
1728	Log(("uInterruptState %x eip=%RGv\n", uInterruptState, pCtx->rip));
1729	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1730	}
1731	else
1732	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1733
1734	/* Control registers. */
1735	VMXReadCachedVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1736	VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR0, &val);
1737	val = (valShadow & pVCpu->hwaccm.s.vmx.cr0_mask) \| (val & ~pVCpu->hwaccm.s.vmx.cr0_mask);
1738	CPUMSetGuestCR0(pVCpu, val);
1739
1740	VMXReadCachedVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1741	VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR4, &val);
1742	val = (valShadow & pVCpu->hwaccm.s.vmx.cr4_mask) \| (val & ~pVCpu->hwaccm.s.vmx.cr4_mask);
1743	CPUMSetGuestCR4(pVCpu, val);
1744
1745	/* Note: no reason to sync back the CRx registers. They can't be changed by the guest. */
1746	/* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1747	if ( pVM->hwaccm.s.fNestedPaging
1748	&& CPUMIsGuestInPagedProtectedModeEx(pCtx))
1749	{
1750	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1751
1752	/* Can be updated behind our back in the nested paging case. */
1753	CPUMSetGuestCR2(pVCpu, pCache->cr2);
1754
1755	VMXReadCachedVMCS(VMX_VMCS64_GUEST_CR3, &val);
1756
1757	if (val != pCtx->cr3)
1758	{
1759	CPUMSetGuestCR3(pVCpu, val);
1760	PGMUpdateCR3(pVCpu, val);
1761	}
1762	/* Prefetch the four PDPT entries in PAE mode. */
1763	vmxR0PrefetchPAEPdptrs(pVM, pVCpu, pCtx);
1764	}
1765
1766	/* Sync back DR7 here. */
1767	VMXReadCachedVMCS(VMX_VMCS64_GUEST_DR7, &val);
1768	pCtx->dr[7] = val;
1769
1770	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1771	VMX_READ_SELREG(ES, es);
1772	VMX_READ_SELREG(SS, ss);
1773	VMX_READ_SELREG(CS, cs);
1774	VMX_READ_SELREG(DS, ds);
1775	VMX_READ_SELREG(FS, fs);
1776	VMX_READ_SELREG(GS, gs);
1777
1778	/*
1779	* System MSRs
1780	*/
1781	VMXReadCachedVMCS(VMX_VMCS32_GUEST_SYSENTER_CS, &val);
1782	pCtx->SysEnter.cs = val;
1783	VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_EIP, &val);
1784	pCtx->SysEnter.eip = val;
1785	VMXReadCachedVMCS(VMX_VMCS64_GUEST_SYSENTER_ESP, &val);
1786	pCtx->SysEnter.esp = val;
1787
1788	/* Misc. registers; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1789	VMX_READ_SELREG(LDTR, ldtr);
1790
1791	VMXReadCachedVMCS(VMX_VMCS32_GUEST_GDTR_LIMIT, &val);
1792	pCtx->gdtr.cbGdt = val;
1793	VMXReadCachedVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
1794	pCtx->gdtr.pGdt = val;
1795
1796	VMXReadCachedVMCS(VMX_VMCS32_GUEST_IDTR_LIMIT, &val);
1797	pCtx->idtr.cbIdt = val;
1798	VMXReadCachedVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
1799	pCtx->idtr.pIdt = val;
1800
1801	#ifdef HWACCM_VMX_EMULATE_REALMODE
1802	/* Real mode emulation using v86 mode. */
1803	if (CPUMIsGuestInRealModeEx(pCtx))
1804	{
1805	/* Hide our emulation flags */
1806	pCtx->eflags.Bits.u1VM = 0;
1807
1808	/* Restore original IOPL setting as we always use 0. */
1809	pCtx->eflags.Bits.u2IOPL = pVCpu->hwaccm.s.vmx.RealMode.eflags.Bits.u2IOPL;
1810
1811	/* Force a TR resync every time in case we switch modes. */
1812	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_TR;
1813	}
1814	else
1815	#endif /* HWACCM_VMX_EMULATE_REALMODE */
1816	{
1817	/* In real mode we have a fake TSS, so only sync it back when it's supposed to be valid. */
1818	VMX_READ_SELREG(TR, tr);
1819	}
1820	return VINF_SUCCESS;
1821	}
1822
1823	/**
1824	* Dummy placeholder
1825	*
1826	* @param pVM The VM to operate on.
1827	* @param pVCpu The VMCPU to operate on.
1828	*/
1829	static void vmxR0SetupTLBDummy(PVM pVM, PVMCPU pVCpu)
1830	{
1831	NOREF(pVM);
1832	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
1833	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1834	pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1835	return;
1836	}
1837
1838	/**
1839	* Setup the tagged TLB for EPT
1840	*
1841	* @returns VBox status code.
1842	* @param pVM The VM to operate on.
1843	* @param pVCpu The VMCPU to operate on.
1844	*/
1845	static void vmxR0SetupTLBEPT(PVM pVM, PVMCPU pVCpu)
1846	{
1847	PHWACCM_CPUINFO pCpu;
1848
1849	Assert(pVM->hwaccm.s.fNestedPaging);
1850	Assert(!pVM->hwaccm.s.vmx.fVPID);
1851
1852	/* Deal with tagged TLBs if VPID or EPT is supported. */
1853	pCpu = HWACCMR0GetCurrentCpu();
1854	/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1855	/* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1856	if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1857	/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1858	\|\| pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1859	{
1860	/* Force a TLB flush on VM entry. */
1861	pVCpu->hwaccm.s.fForceTLBFlush = true;
1862	}
1863	else
1864	Assert(!pCpu->fFlushTLB);
1865
1866	/* Check for tlb shootdown flushes. */
1867	if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
1868	pVCpu->hwaccm.s.fForceTLBFlush = true;
1869
1870	pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1871	pCpu->fFlushTLB = false;
1872
1873	if (pVCpu->hwaccm.s.fForceTLBFlush)
1874	{
1875	vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1876	}
1877	else
1878	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1879	{
1880	/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1881	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1882
1883	for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1884	{
1885	/* aTlbShootdownPages contains physical addresses in this case. */
1886	vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
1887	}
1888	}
1889	pVCpu->hwaccm.s.TlbShootdown.cPages= 0;
1890	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1891
1892	#ifdef VBOX_WITH_STATISTICS
1893	if (pVCpu->hwaccm.s.fForceTLBFlush)
1894	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1895	else
1896	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1897	#endif
1898	}
1899
1900	#ifdef HWACCM_VTX_WITH_VPID
1901	/**
1902	* Setup the tagged TLB for VPID
1903	*
1904	* @returns VBox status code.
1905	* @param pVM The VM to operate on.
1906	* @param pVCpu The VMCPU to operate on.
1907	*/
1908	static void vmxR0SetupTLBVPID(PVM pVM, PVMCPU pVCpu)
1909	{
1910	PHWACCM_CPUINFO pCpu;
1911
1912	Assert(pVM->hwaccm.s.vmx.fVPID);
1913	Assert(!pVM->hwaccm.s.fNestedPaging);
1914
1915	/* Deal with tagged TLBs if VPID or EPT is supported. */
1916	pCpu = HWACCMR0GetCurrentCpu();
1917	/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1918	/* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1919	if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1920	/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1921	\|\| pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1922	{
1923	/* Force a TLB flush on VM entry. */
1924	pVCpu->hwaccm.s.fForceTLBFlush = true;
1925	}
1926	else
1927	Assert(!pCpu->fFlushTLB);
1928
1929	pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1930
1931	/* Check for tlb shootdown flushes. */
1932	if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH_BIT))
1933	pVCpu->hwaccm.s.fForceTLBFlush = true;
1934
1935	/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1936	if (pVCpu->hwaccm.s.fForceTLBFlush)
1937	{
1938	if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1939	\|\| pCpu->fFlushTLB)
1940	{
1941	pCpu->fFlushTLB = false;
1942	pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1943	pCpu->cTLBFlushes++;
1944	}
1945	else
1946	{
1947	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1948	pVCpu->hwaccm.s.fForceTLBFlush = false;
1949	}
1950
1951	pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1952	pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1953	}
1954	else
1955	{
1956	Assert(!pCpu->fFlushTLB);
1957	Assert(pVCpu->hwaccm.s.uCurrentASID && pCpu->uCurrentASID);
1958
1959	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1960	{
1961	/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1962	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1963	for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1964	vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, pVCpu->hwaccm.s.TlbShootdown.aPages[i]);
1965	}
1966	}
1967	pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1968	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1969
1970	AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1971	AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1972	AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1973
1974	int rc = VMXWriteVMCS(VMX_VMCS16_GUEST_FIELD_VPID, pVCpu->hwaccm.s.uCurrentASID);
1975	AssertRC(rc);
1976
1977	if (pVCpu->hwaccm.s.fForceTLBFlush)
1978	vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushContext, 0);
1979
1980	#ifdef VBOX_WITH_STATISTICS
1981	if (pVCpu->hwaccm.s.fForceTLBFlush)
1982	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1983	else
1984	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1985	#endif
1986	}
1987	#endif /* HWACCM_VTX_WITH_VPID */
1988
1989	/**
1990	* Runs guest code in a VT-x VM.
1991	*
1992	* @returns VBox status code.
1993	* @param pVM The VM to operate on.
1994	* @param pVCpu The VMCPU to operate on.
1995	* @param pCtx Guest context
1996	*/
1997	VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1998	{
1999	int rc = VINF_SUCCESS;
2000	RTGCUINTREG val;
2001	RTGCUINTREG exitReason = VMX_EXIT_INVALID;
2002	RTGCUINTREG instrError, cbInstr;
2003	RTGCUINTPTR exitQualification;
2004	RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
2005	RTGCUINTPTR errCode, instrInfo;
2006	bool fSyncTPR = false;
2007	bool fSetupTPRCaching = false;
2008	PHWACCM_CPUINFO pCpu = 0;
2009	RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
2010	unsigned cResume = 0;
2011	#ifdef VBOX_STRICT
2012	RTCPUID idCpuCheck;
2013	#endif
2014	#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
2015	uint64_t u64LastTime = RTTimeMilliTS();
2016	#endif
2017	#ifdef VBOX_WITH_STATISTICS
2018	bool fStatEntryStarted = true;
2019	bool fStatExit2Started = false;
2020	#endif
2021
2022	Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC) \|\| (pVCpu->hwaccm.s.vmx.pVAPIC && pVM->hwaccm.s.vmx.pAPIC));
2023
2024	/* Check if we need to use TPR shadowing. */
2025	if ( CPUMIsGuestInLongModeEx(pCtx)
2026	\|\| ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
2027	&& pVM->hwaccm.s.fHasIoApic)
2028	)
2029	{
2030	fSetupTPRCaching = true;
2031	}
2032
2033	Log2(("\nE"));
2034
2035	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
2036
2037	#ifdef VBOX_STRICT
2038	{
2039	RTCCUINTREG val;
2040
2041	rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
2042	AssertRC(rc);
2043	Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
2044
2045	/* allowed zero */
2046	if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
2047	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
2048
2049	/* allowed one */
2050	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
2051	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
2052
2053	rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
2054	AssertRC(rc);
2055	Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
2056
2057	/* Must be set according to the MSR, but can be cleared in case of EPT. */
2058	if (pVM->hwaccm.s.fNestedPaging)
2059	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
2060	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT
2061	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT;
2062
2063	/* allowed zero */
2064	if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
2065	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
2066
2067	/* allowed one */
2068	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
2069	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
2070
2071	rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
2072	AssertRC(rc);
2073	Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
2074
2075	/* allowed zero */
2076	if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
2077	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
2078
2079	/* allowed one */
2080	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
2081	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
2082
2083	rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
2084	AssertRC(rc);
2085	Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
2086
2087	/* allowed zero */
2088	if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
2089	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
2090
2091	/* allowed one */
2092	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
2093	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
2094	}
2095	#endif
2096
2097	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2098	pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeEntry = RTTimeNanoTS();
2099	#endif
2100
2101	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
2102	*/
2103	ResumeExecution:
2104	STAM_STATS({
2105	if (fStatExit2Started) { STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = false; }
2106	if (!fStatEntryStarted) { STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = true; }
2107	});
2108	AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == RTMpCpuId(),
2109	("Expected %d, I'm %d; cResume=%d exitReason=%RGv exitQualification=%RGv\n",
2110	(int)pVCpu->hwaccm.s.idEnteredCpu, (int)RTMpCpuId(), cResume, exitReason, exitQualification));
2111	Assert(!HWACCMR0SuspendPending());
2112
2113	/* Safety precaution; looping for too long here can have a very bad effect on the host */
2114	if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
2115	{
2116	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
2117	rc = VINF_EM_RAW_INTERRUPT;
2118	goto end;
2119	}
2120
2121	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
2122	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2123	{
2124	Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
2125	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2126	{
2127	/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
2128	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
2129	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
2130	* break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
2131	*/
2132	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2133	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
2134	rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2135	AssertRC(rc);
2136	}
2137	}
2138	else
2139	{
2140	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
2141	rc = VMXWriteVMCS(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, 0);
2142	AssertRC(rc);
2143	}
2144
2145	#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
2146	if (RT_UNLIKELY(cResume & 0xf) == 0)
2147	{
2148	uint64_t u64CurTime = RTTimeMilliTS();
2149
2150	if (RT_UNLIKELY(u64CurTime > u64LastTime))
2151	{
2152	u64LastTime = u64CurTime;
2153	TMTimerPollVoid(pVM, pVCpu);
2154	}
2155	}
2156	#endif
2157
2158	/* Check for pending actions that force us to go back to ring 3. */
2159	#ifdef DEBUG
2160	/* Intercept X86_XCPT_DB if stepping is enabled */
2161	if (!DBGFIsStepping(pVCpu))
2162	#endif
2163	{
2164	if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
2165	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
2166	{
2167	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2168	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
2169	rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2170	goto end;
2171	}
2172	}
2173
2174	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
2175	if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
2176	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
2177	{
2178	rc = VINF_EM_PENDING_REQUEST;
2179	goto end;
2180	}
2181
2182	/* When external interrupts are pending, we should exit the VM when IF is set. */
2183	/* Note! After VM_FF_INHIBIT_INTERRUPTS check!!! */
2184	rc = VMXR0CheckPendingInterrupt(pVM, pVCpu, pCtx);
2185	if (RT_FAILURE(rc))
2186	goto end;
2187
2188	/** @todo check timers?? */
2189
2190	/* TPR caching using CR8 is only available in 64 bits mode */
2191	/* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
2192	/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
2193	/**
2194	* @todo reduce overhead
2195	*/
2196	if (fSetupTPRCaching)
2197	{
2198	/* TPR caching in CR8 */
2199	uint8_t u8TPR;
2200	bool fPending;
2201
2202	int rc = PDMApicGetTPR(pVCpu, &u8TPR, &fPending);
2203	AssertRC(rc);
2204	/* The TPR can be found at offset 0x80 in the APIC mmio page. */
2205	pVCpu->hwaccm.s.vmx.pVAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
2206
2207	/* Two options here:
2208	* - external interrupt pending, but masked by the TPR value.
2209	* -> a CR8 update that lower the current TPR value should cause an exit
2210	* - no pending interrupts
2211	* -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
2212	*/
2213	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
2214	AssertRC(rc);
2215
2216	/* Always sync back the TPR; we should optimize this though / /* @todo optimize TPR sync. */
2217	fSyncTPR = true;
2218	}
2219
2220	#if defined(HWACCM_VTX_WITH_EPT) && defined(LOG_ENABLED)
2221	if ( pVM->hwaccm.s.fNestedPaging
2222	# ifdef HWACCM_VTX_WITH_VPID
2223	\|\| pVM->hwaccm.s.vmx.fVPID
2224	# endif /* HWACCM_VTX_WITH_VPID */
2225	)
2226	{
2227	pCpu = HWACCMR0GetCurrentCpu();
2228	if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
2229	\|\| pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
2230	{
2231	if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
2232	Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
2233	else
2234	Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
2235	}
2236	if (pCpu->fFlushTLB)
2237	Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
2238	else
2239	if (pVCpu->hwaccm.s.fForceTLBFlush)
2240	LogFlow(("Manual TLB flush\n"));
2241	}
2242	#endif
2243	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
2244	PGMDynMapFlushAutoSet(pVCpu);
2245	#endif
2246
2247	/*
2248	* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
2249	* (until the actual world switch)
2250	*/
2251	#ifdef VBOX_STRICT
2252	idCpuCheck = RTMpCpuId();
2253	#endif
2254	#ifdef LOG_ENABLED
2255	VMMR0LogFlushDisable(pVCpu);
2256	#endif
2257	/* Save the host state first. */
2258	rc = VMXR0SaveHostState(pVM, pVCpu);
2259	if (rc != VINF_SUCCESS)
2260	goto end;
2261	/* Load the guest state */
2262	rc = VMXR0LoadGuestState(pVM, pVCpu, pCtx);
2263	if (rc != VINF_SUCCESS)
2264	goto end;
2265
2266	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2267	/*
2268	* Exit to ring-3 preemption/work is pending.
2269	*
2270	* Interrupts are disabled before the call to make sure we don't miss any interrupt
2271	* that would flag preemption (IPI, timer tick, ++).
2272	*
2273	* Note! Interrupts must be disabled done before we check for TLB flushes; TLB
2274	* shootdowns rely on this.
2275	*/
2276	uOldEFlags = ASMIntDisableFlags();
2277	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
2278	{
2279	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
2280	rc = VINF_EM_RAW_INTERRUPT;
2281	goto end;
2282	}
2283	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2284	#else
2285	/* Disable interrupts to make sure a poke will interrupt execution.
2286	* This must be done before we check for TLB flushes; TLB shootdowns rely on this.
2287	*/
2288	uOldEFlags = ASMIntDisableFlags();
2289	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
2290	#endif
2291
2292	/* Deal with tagged TLB setup and invalidation. */
2293	pVM->hwaccm.s.vmx.pfnSetupTaggedTLB(pVM, pVCpu);
2294
2295	/* Non-register state Guest Context */
2296	/** @todo change me according to cpu state */
2297	rc = VMXWriteVMCS(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
2298	AssertRC(rc);
2299
2300	STAM_STATS({ STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x); fStatEntryStarted = false; });
2301
2302	/* Manual save and restore:
2303	* - General purpose registers except RIP, RSP
2304	*
2305	* Trashed:
2306	* - CR2 (we don't care)
2307	* - LDTR (reset to 0)
2308	* - DRx (presumably not changed at all)
2309	* - DR7 (reset to 0x400)
2310	* - EFLAGS (reset to RT_BIT(1); not relevant)
2311	*
2312	*/
2313
2314
2315	/* All done! Let's start VM execution. */
2316	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, z);
2317	Assert(idCpuCheck == RTMpCpuId());
2318
2319	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2320	pVCpu->hwaccm.s.vmx.VMCSCache.cResume = cResume;
2321	pVCpu->hwaccm.s.vmx.VMCSCache.u64TimeSwitch = RTTimeNanoTS();
2322	#endif
2323
2324	TMNotifyStartOfExecution(pVCpu);
2325	rc = pVCpu->hwaccm.s.vmx.pfnStartVM(pVCpu->hwaccm.s.fResumeVM, pCtx, &pVCpu->hwaccm.s.vmx.VMCSCache, pVM, pVCpu);
2326	TMNotifyEndOfExecution(pVCpu);
2327	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
2328	Assert(!(ASMGetFlags() & X86_EFL_IF));
2329	ASMSetFlags(uOldEFlags);
2330	#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2331	uOldEFlags = ~(RTCCUINTREG)0;
2332	#endif
2333
2334	AssertMsg(!pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries, ("pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries=%d\n", pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries));
2335
2336	/* In case we execute a goto ResumeExecution later on. */
2337	pVCpu->hwaccm.s.fResumeVM = true;
2338	pVCpu->hwaccm.s.fForceTLBFlush = false;
2339
2340	/*
2341	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2342	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
2343	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2344	*/
2345	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, z);
2346	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, v);
2347
2348	if (rc != VINF_SUCCESS)
2349	{
2350	VMXR0ReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
2351	goto end;
2352	}
2353
2354	/* Success. Query the guest state and figure out what has happened. */
2355
2356	/* Investigate why there was a VM-exit. */
2357	rc = VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
2358	STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
2359
2360	exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
2361	rc \|= VMXReadCachedVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
2362	rc \|= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &cbInstr);
2363	rc \|= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &intInfo);
2364	/* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
2365	rc \|= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE, &errCode);
2366	rc \|= VMXReadCachedVMCS(VMX_VMCS32_RO_EXIT_INSTR_INFO, &instrInfo);
2367	rc \|= VMXReadCachedVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &exitQualification);
2368	AssertRC(rc);
2369
2370	/* Sync back the guest state */
2371	rc = VMXR0SaveGuestState(pVM, pVCpu, pCtx);
2372	AssertRC(rc);
2373
2374	/* Note! NOW IT'S SAFE FOR LOGGING! */
2375	#ifdef LOG_ENABLED
2376	VMMR0LogFlushEnable(pVCpu);
2377	#endif
2378	Log2(("Raw exit reason %08x\n", exitReason));
2379
2380	/* Check if an injected event was interrupted prematurely. */
2381	rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_INFO, &val);
2382	AssertRC(rc);
2383	pVCpu->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
2384	if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2385	/* Ignore 'int xx' as they'll be restarted anyway. */
2386	&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW
2387	/* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2388	&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2389	{
2390	Assert(!pVCpu->hwaccm.s.Event.fPending);
2391	pVCpu->hwaccm.s.Event.fPending = true;
2392	/* Error code present? */
2393	if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVCpu->hwaccm.s.Event.intInfo))
2394	{
2395	rc = VMXReadCachedVMCS(VMX_VMCS32_RO_IDT_ERRCODE, &val);
2396	AssertRC(rc);
2397	pVCpu->hwaccm.s.Event.errCode = val;
2398	Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv pending error=%RX64\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification, val));
2399	}
2400	else
2401	{
2402	Log(("Pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2403	pVCpu->hwaccm.s.Event.errCode = 0;
2404	}
2405	}
2406	#ifdef VBOX_STRICT
2407	else
2408	if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVCpu->hwaccm.s.Event.intInfo)
2409	/* Ignore software exceptions (such as int3) as they're reoccur when we restart the instruction anyway. */
2410	&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hwaccm.s.Event.intInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT)
2411	{
2412	Log(("Ignore pending inject %RX64 at %RGv exit=%08x intInfo=%08x exitQualification=%RGv\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitReason, intInfo, exitQualification));
2413	}
2414
2415	if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
2416	HWACCMDumpRegs(pVM, pVCpu, pCtx);
2417	#endif
2418
2419	Log2(("E%d: New EIP=%RGv\n", exitReason, (RTGCPTR)pCtx->rip));
2420	Log2(("Exit reason %d, exitQualification %RGv\n", (uint32_t)exitReason, exitQualification));
2421	Log2(("instrInfo=%d instrError=%d instr length=%d\n", (uint32_t)instrInfo, (uint32_t)instrError, (uint32_t)cbInstr));
2422	Log2(("Interruption error code %d\n", (uint32_t)errCode));
2423	Log2(("IntInfo = %08x\n", (uint32_t)intInfo));
2424
2425	if (fSyncTPR)
2426	{
2427	rc = PDMApicSetTPR(pVCpu, pVCpu->hwaccm.s.vmx.pVAPIC[0x80] >> 4);
2428	AssertRC(rc);
2429	}
2430
2431	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, v);
2432	STAM_STATS({ STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2, y); fStatExit2Started = true; });
2433
2434	/* Some cases don't need a complete resync of the guest CPU state; handle them here. */
2435	switch (exitReason)
2436	{
2437	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2438	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2439	{
2440	uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
2441
2442	if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2443	{
2444	Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
2445	/* External interrupt; leave to allow it to be dispatched again. */
2446	rc = VINF_EM_RAW_INTERRUPT;
2447	break;
2448	}
2449	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2450	switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
2451	{
2452	case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
2453	/* External interrupt; leave to allow it to be dispatched again. */
2454	rc = VINF_EM_RAW_INTERRUPT;
2455	break;
2456
2457	case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
2458	AssertFailed(); /* can't come here; fails the first check. */
2459	break;
2460
2461	case VMX_EXIT_INTERRUPTION_INFO_TYPE_DBEXCPT: /* Unknown why we get this type for #DB */
2462	case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
2463	Assert(vector == 1 \|\| vector == 3 \|\| vector == 4);
2464	/* no break */
2465	case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
2466	Log2(("Hardware/software interrupt %d\n", vector));
2467	switch (vector)
2468	{
2469	case X86_XCPT_NM:
2470	{
2471	Log(("#NM fault at %RGv error code %x\n", (RTGCPTR)pCtx->rip, errCode));
2472
2473	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
2474	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
2475	rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
2476	if (rc == VINF_SUCCESS)
2477	{
2478	Assert(CPUMIsGuestFPUStateActive(pVCpu));
2479
2480	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
2481
2482	/* Continue execution. */
2483	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
2484
2485	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2486	goto ResumeExecution;
2487	}
2488
2489	Log(("Forward #NM fault to the guest\n"));
2490	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
2491	rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
2492	AssertRC(rc);
2493	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2494	goto ResumeExecution;
2495	}
2496
2497	case X86_XCPT_PF: /* Page fault */
2498	{
2499	#ifdef DEBUG
2500	if (pVM->hwaccm.s.fNestedPaging)
2501	{ /* A genuine pagefault.
2502	* Forward the trap to the guest by injecting the exception and resuming execution.
2503	*/
2504	Log(("Guest page fault at %RGv cr2=%RGv error code %x rsp=%RGv\n", (RTGCPTR)pCtx->rip, exitQualification, errCode, (RTGCPTR)pCtx->rsp));
2505
2506	Assert(CPUMIsGuestInPagedProtectedModeEx(pCtx));
2507
2508	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2509
2510	/* Now we must update CR2. */
2511	pCtx->cr2 = exitQualification;
2512	rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2513	AssertRC(rc);
2514
2515	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2516	goto ResumeExecution;
2517	}
2518	#endif
2519	Assert(!pVM->hwaccm.s.fNestedPaging);
2520
2521	Log2(("Page fault at %RGv error code %x\n", exitQualification, errCode));
2522	/* Exit qualification contains the linear address of the page fault. */
2523	TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
2524	TRPMSetErrorCode(pVCpu, errCode);
2525	TRPMSetFaultAddress(pVCpu, exitQualification);
2526
2527	/* Shortcut for APIC TPR reads and writes. */
2528	if ( (exitQualification & 0xfff) == 0x080
2529	&& !(errCode & X86_TRAP_PF_P) /* not present */
2530	&& fSetupTPRCaching
2531	&& (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
2532	{
2533	RTGCPHYS GCPhysApicBase, GCPhys;
2534	PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
2535	GCPhysApicBase &= PAGE_BASE_GC_MASK;
2536
2537	rc = PGMGstGetPage(pVCpu, (RTGCPTR)exitQualification, NULL, &GCPhys);
2538	if ( rc == VINF_SUCCESS
2539	&& GCPhys == GCPhysApicBase)
2540	{
2541	Log(("Enable VT-x virtual APIC access filtering\n"));
2542	rc = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW \| X86_PTE_P);
2543	AssertRC(rc);
2544	}
2545	}
2546
2547	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
2548	rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
2549	Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
2550	if (rc == VINF_SUCCESS)
2551	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
2552	Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, exitQualification ,errCode));
2553	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
2554
2555	TRPMResetTrap(pVCpu);
2556
2557	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2558	goto ResumeExecution;
2559	}
2560	else
2561	if (rc == VINF_EM_RAW_GUEST_TRAP)
2562	{ /* A genuine pagefault.
2563	* Forward the trap to the guest by injecting the exception and resuming execution.
2564	*/
2565	Log2(("Forward page fault to the guest\n"));
2566
2567	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
2568	/* The error code might have been changed. */
2569	errCode = TRPMGetErrorCode(pVCpu);
2570
2571	TRPMResetTrap(pVCpu);
2572
2573	/* Now we must update CR2. */
2574	pCtx->cr2 = exitQualification;
2575	rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2576	AssertRC(rc);
2577
2578	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2579	goto ResumeExecution;
2580	}
2581	#ifdef VBOX_STRICT
2582	if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
2583	Log2(("PGMTrap0eHandler failed with %d\n", rc));
2584	#endif
2585	/* Need to go back to the recompiler to emulate the instruction. */
2586	TRPMResetTrap(pVCpu);
2587	break;
2588	}
2589
2590	case X86_XCPT_MF: /* Floating point exception. */
2591	{
2592	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
2593	if (!(pCtx->cr0 & X86_CR0_NE))
2594	{
2595	/* old style FPU error reporting needs some extra work. */
2596	/** @todo don't fall back to the recompiler, but do it manually. */
2597	rc = VINF_EM_RAW_EMULATE_INSTR;
2598	break;
2599	}
2600	Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2601	rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2602	AssertRC(rc);
2603
2604	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2605	goto ResumeExecution;
2606	}
2607
2608	case X86_XCPT_DB: /* Debug exception. */
2609	{
2610	uint64_t uDR6;
2611
2612	/* DR6, DR7.GD and IA32_DEBUGCTL.LBR are not updated yet.
2613	*
2614	* Exit qualification bits:
2615	* 3:0 B0-B3 which breakpoint condition was met
2616	* 12:4 Reserved (0)
2617	* 13 BD - debug register access detected
2618	* 14 BS - single step execution or branch taken
2619	* 63:15 Reserved (0)
2620	*/
2621	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
2622
2623	/* Note that we don't support guest and host-initiated debugging at the same time. */
2624	Assert(DBGFIsStepping(pVCpu) \|\| CPUMIsGuestInRealModeEx(pCtx));
2625
2626	uDR6 = X86_DR6_INIT_VAL;
2627	uDR6 \|= (exitQualification & (X86_DR6_B0\|X86_DR6_B1\|X86_DR6_B2\|X86_DR6_B3\|X86_DR6_BD\|X86_DR6_BS));
2628	rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), uDR6);
2629	if (rc == VINF_EM_RAW_GUEST_TRAP)
2630	{
2631	/** @todo this isn't working, but we'll never get here normally. */
2632
2633	/* Update DR6 here. */
2634	pCtx->dr[6] = uDR6;
2635
2636	/* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2637	pCtx->dr[7] &= ~X86_DR7_GD;
2638
2639	/* Paranoia. */
2640	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2641	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
2642	pCtx->dr[7] \|= 0x400; /* must be one */
2643
2644	/* Resync DR7 */
2645	rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
2646	AssertRC(rc);
2647
2648	Log(("Trap %x (debug) at %RGv exit qualification %RX64\n", vector, (RTGCPTR)pCtx->rip, exitQualification));
2649	rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2650	AssertRC(rc);
2651
2652	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2653	goto ResumeExecution;
2654	}
2655	/* Return to ring 3 to deal with the debug exit code. */
2656	break;
2657	}
2658
2659	case X86_XCPT_BP: /* Breakpoint. */
2660	{
2661	rc = DBGFRZTrap03Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2662	if (rc == VINF_EM_RAW_GUEST_TRAP)
2663	{
2664	Log(("Guest #BP at %04x:%RGv\n", pCtx->cs, pCtx->rip));
2665	rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2666	AssertRC(rc);
2667	goto ResumeExecution;
2668	}
2669	if (rc == VINF_SUCCESS)
2670	goto ResumeExecution;
2671	Log(("Debugger BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
2672	break;
2673	}
2674
2675	case X86_XCPT_GP: /* General protection failure exception.*/
2676	{
2677	uint32_t cbOp;
2678	uint32_t cbSize;
2679	PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2680
2681	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
2682	#ifdef VBOX_STRICT
2683	if (!CPUMIsGuestInRealModeEx(pCtx))
2684	{
2685	Log(("Trap %x at %04X:%RGv errorCode=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, errCode));
2686	rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2687	AssertRC(rc);
2688	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2689	goto ResumeExecution;
2690	}
2691	#endif
2692	Assert(CPUMIsGuestInRealModeEx(pCtx));
2693
2694	LogFlow(("Real mode X86_XCPT_GP instruction emulation at %RGv\n", (RTGCPTR)pCtx->rip));
2695
2696	rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
2697	if (RT_SUCCESS(rc))
2698	{
2699	bool fUpdateRIP = true;
2700
2701	Assert(cbOp == pDis->opsize);
2702	switch (pDis->pCurInstr->opcode)
2703	{
2704	case OP_CLI:
2705	pCtx->eflags.Bits.u1IF = 0;
2706	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCli);
2707	break;
2708
2709	case OP_STI:
2710	pCtx->eflags.Bits.u1IF = 1;
2711	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitSti);
2712	break;
2713
2714	case OP_HLT:
2715	fUpdateRIP = false;
2716	rc = VINF_EM_HALT;
2717	pCtx->rip += pDis->opsize;
2718	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2719	break;
2720
2721	case OP_POPF:
2722	{
2723	RTGCPTR GCPtrStack;
2724	uint32_t cbParm;
2725	uint32_t uMask;
2726	X86EFLAGS eflags;
2727
2728	if (pDis->prefix & PREFIX_OPSIZE)
2729	{
2730	cbParm = 4;
2731	uMask = 0xffffffff;
2732	}
2733	else
2734	{
2735	cbParm = 2;
2736	uMask = 0xffff;
2737	}
2738
2739	rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
2740	if (RT_FAILURE(rc))
2741	{
2742	rc = VERR_EM_INTERPRETER;
2743	break;
2744	}
2745	eflags.u = 0;
2746	rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
2747	if (RT_FAILURE(rc))
2748	{
2749	rc = VERR_EM_INTERPRETER;
2750	break;
2751	}
2752	LogFlow(("POPF %x -> %RGv mask=%x\n", eflags.u, pCtx->rsp, uMask));
2753	pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) \| (eflags.u & X86_EFL_POPF_BITS & uMask);
2754	/* RF cleared when popped in real mode; see pushf description in AMD manual. */
2755	pCtx->eflags.Bits.u1RF = 0;
2756	pCtx->esp += cbParm;
2757	pCtx->esp &= uMask;
2758
2759	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPopf);
2760	break;
2761	}
2762
2763	case OP_PUSHF:
2764	{
2765	RTGCPTR GCPtrStack;
2766	uint32_t cbParm;
2767	uint32_t uMask;
2768	X86EFLAGS eflags;
2769
2770	if (pDis->prefix & PREFIX_OPSIZE)
2771	{
2772	cbParm = 4;
2773	uMask = 0xffffffff;
2774	}
2775	else
2776	{
2777	cbParm = 2;
2778	uMask = 0xffff;
2779	}
2780
2781	rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), (pCtx->esp - cbParm) & uMask, 0, &GCPtrStack);
2782	if (RT_FAILURE(rc))
2783	{
2784	rc = VERR_EM_INTERPRETER;
2785	break;
2786	}
2787	eflags = pCtx->eflags;
2788	/* RF & VM cleared when pushed in real mode; see pushf description in AMD manual. */
2789	eflags.Bits.u1RF = 0;
2790	eflags.Bits.u1VM = 0;
2791
2792	rc = PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &eflags.u, cbParm);
2793	if (RT_FAILURE(rc))
2794	{
2795	rc = VERR_EM_INTERPRETER;
2796	break;
2797	}
2798	LogFlow(("PUSHF %x -> %RGv\n", eflags.u, GCPtrStack));
2799	pCtx->esp -= cbParm;
2800	pCtx->esp &= uMask;
2801	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPushf);
2802	break;
2803	}
2804
2805	case OP_IRET:
2806	{
2807	RTGCPTR GCPtrStack;
2808	uint32_t uMask = 0xffff;
2809	uint16_t aIretFrame[3];
2810
2811	if (pDis->prefix & (PREFIX_OPSIZE \| PREFIX_ADDRSIZE))
2812	{
2813	rc = VERR_EM_INTERPRETER;
2814	break;
2815	}
2816
2817	rc = SELMToFlatEx(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp & uMask, 0, &GCPtrStack);
2818	if (RT_FAILURE(rc))
2819	{
2820	rc = VERR_EM_INTERPRETER;
2821	break;
2822	}
2823	rc = PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame));
2824	if (RT_FAILURE(rc))
2825	{
2826	rc = VERR_EM_INTERPRETER;
2827	break;
2828	}
2829	pCtx->ip = aIretFrame[0];
2830	pCtx->cs = aIretFrame[1];
2831	pCtx->csHid.u64Base = pCtx->cs << 4;
2832	pCtx->eflags.u = (pCtx->eflags.u & ~(X86_EFL_POPF_BITS & uMask)) \| (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
2833	pCtx->sp += sizeof(aIretFrame);
2834
2835	LogFlow(("iret to %04x:%x\n", pCtx->cs, pCtx->ip));
2836	fUpdateRIP = false;
2837	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIret);
2838	break;
2839	}
2840
2841	case OP_INT:
2842	{
2843	RTGCUINTPTR intInfo;
2844
2845	LogFlow(("Realmode: INT %x\n", pDis->param1.parval & 0xff));
2846	intInfo = pDis->param1.parval & 0xff;
2847	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2848	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2849
2850	rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2851	AssertRC(rc);
2852	fUpdateRIP = false;
2853	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2854	break;
2855	}
2856
2857	case OP_INTO:
2858	{
2859	if (pCtx->eflags.Bits.u1OF)
2860	{
2861	RTGCUINTPTR intInfo;
2862
2863	LogFlow(("Realmode: INTO\n"));
2864	intInfo = X86_XCPT_OF;
2865	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2866	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2867
2868	rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2869	AssertRC(rc);
2870	fUpdateRIP = false;
2871	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2872	}
2873	break;
2874	}
2875
2876	case OP_INT3:
2877	{
2878	RTGCUINTPTR intInfo;
2879
2880	LogFlow(("Realmode: INT 3\n"));
2881	intInfo = 3;
2882	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
2883	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
2884
2885	rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, intInfo, cbOp, 0);
2886	AssertRC(rc);
2887	fUpdateRIP = false;
2888	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInt);
2889	break;
2890	}
2891
2892	default:
2893	rc = EMInterpretInstructionCPU(pVM, pVCpu, pDis, CPUMCTX2CORE(pCtx), 0, &cbSize);
2894	break;
2895	}
2896
2897	if (rc == VINF_SUCCESS)
2898	{
2899	if (fUpdateRIP)
2900	pCtx->rip += cbOp; /* Move on to the next instruction. */
2901
2902	/* lidt, lgdt can end up here. In the future crx changes as well. Just reload the whole context to be done with it. */
2903	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
2904
2905	/* Only resume if successful. */
2906	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2907	goto ResumeExecution;
2908	}
2909	}
2910	else
2911	rc = VERR_EM_INTERPRETER;
2912
2913	AssertMsg(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_EM_HALT, ("Unexpected rc=%Rrc\n", rc));
2914	break;
2915	}
2916
2917	#ifdef VBOX_STRICT
2918	case X86_XCPT_DE: /* Divide error. */
2919	case X86_XCPT_UD: /* Unknown opcode exception. */
2920	case X86_XCPT_SS: /* Stack segment exception. */
2921	case X86_XCPT_NP: /* Segment not present exception. */
2922	{
2923	switch(vector)
2924	{
2925	case X86_XCPT_DE:
2926	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
2927	break;
2928	case X86_XCPT_UD:
2929	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
2930	break;
2931	case X86_XCPT_SS:
2932	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
2933	break;
2934	case X86_XCPT_NP:
2935	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
2936	break;
2937	}
2938
2939	Log(("Trap %x at %04X:%RGv\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip));
2940	rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2941	AssertRC(rc);
2942
2943	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2944	goto ResumeExecution;
2945	}
2946	#endif
2947	default:
2948	#ifdef HWACCM_VMX_EMULATE_REALMODE
2949	if (CPUMIsGuestInRealModeEx(pCtx))
2950	{
2951	Log(("Real Mode Trap %x at %04x:%04X error code %x\n", vector, pCtx->cs, pCtx->eip, errCode));
2952	rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
2953	AssertRC(rc);
2954
2955	/* Go back to ring 3 in case of a triple fault. */
2956	if ( vector == X86_XCPT_DF
2957	&& rc == VINF_EM_RESET)
2958	break;
2959
2960	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2961	goto ResumeExecution;
2962	}
2963	#endif
2964	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
2965	rc = VERR_VMX_UNEXPECTED_EXCEPTION;
2966	break;
2967	} /* switch (vector) */
2968
2969	break;
2970
2971	default:
2972	rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE;
2973	AssertMsgFailed(("Unexpected interuption code %x\n", intInfo));
2974	break;
2975	}
2976
2977	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub3, y3);
2978	break;
2979	}
2980
2981	case VMX_EXIT_EPT_VIOLATION: /* 48 EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures. */
2982	{
2983	RTGCPHYS GCPhys;
2984
2985	Assert(pVM->hwaccm.s.fNestedPaging);
2986
2987	rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
2988	AssertRC(rc);
2989	Assert(((exitQualification >> 7) & 3) != 2);
2990
2991	/* Determine the kind of violation. */
2992	errCode = 0;
2993	if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
2994	errCode \|= X86_TRAP_PF_ID;
2995
2996	if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
2997	errCode \|= X86_TRAP_PF_RW;
2998
2999	/* If the page is present, then it's a page level protection fault. */
3000	if (exitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
3001	{
3002	errCode \|= X86_TRAP_PF_P;
3003	}
3004	else {
3005	/* Shortcut for APIC TPR reads and writes. */
3006	if ( (GCPhys & 0xfff) == 0x080
3007	&& GCPhys > 0x1000000 /* to skip VGA frame buffer accesses */
3008	&& fSetupTPRCaching
3009	&& (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
3010	{
3011	RTGCPHYS GCPhysApicBase;
3012	PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
3013	GCPhysApicBase &= PAGE_BASE_GC_MASK;
3014	if (GCPhys == GCPhysApicBase + 0x80)
3015	{
3016	Log(("Enable VT-x virtual APIC access filtering\n"));
3017	rc = IOMMMIOMapMMIOHCPage(pVM, GCPhysApicBase, pVM->hwaccm.s.vmx.pAPICPhys, X86_PTE_RW \| X86_PTE_P);
3018	AssertRC(rc);
3019	}
3020	}
3021	}
3022	Log(("EPT Page fault %x at %RGp error code %x\n", (uint32_t)exitQualification, GCPhys, errCode));
3023
3024	/* GCPhys contains the guest physical address of the page fault. */
3025	TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
3026	TRPMSetErrorCode(pVCpu, errCode);
3027	TRPMSetFaultAddress(pVCpu, GCPhys);
3028
3029	/* Handle the pagefault trap for the nested shadow table. */
3030	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, errCode, CPUMCTX2CORE(pCtx), GCPhys);
3031	Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
3032	if (rc == VINF_SUCCESS)
3033	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
3034	Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, exitQualification , errCode));
3035	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
3036
3037	TRPMResetTrap(pVCpu);
3038
3039	goto ResumeExecution;
3040	}
3041
3042	#ifdef VBOX_STRICT
3043	if (rc != VINF_EM_RAW_EMULATE_INSTR)
3044	LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
3045	#endif
3046	/* Need to go back to the recompiler to emulate the instruction. */
3047	TRPMResetTrap(pVCpu);
3048	break;
3049	}
3050
3051	case VMX_EXIT_EPT_MISCONFIG:
3052	{
3053	RTGCPHYS GCPhys;
3054
3055	Assert(pVM->hwaccm.s.fNestedPaging);
3056
3057	rc = VMXReadVMCS64(VMX_VMCS_EXIT_PHYS_ADDR_FULL, &GCPhys);
3058	AssertRC(rc);
3059
3060	Log(("VMX_EXIT_EPT_MISCONFIG for %VGp\n", GCPhys));
3061	break;
3062	}
3063
3064	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3065	/* Clear VM-exit on IF=1 change. */
3066	LogFlow(("VMX_EXIT_IRQ_WINDOW %RGv pending=%d IF=%d\n", (RTGCPTR)pCtx->rip, VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC\|VMCPU_FF_INTERRUPT_PIC)), pCtx->eflags.Bits.u1IF));
3067	pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
3068	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3069	AssertRC(rc);
3070	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIrqWindow);
3071	goto ResumeExecution; /* we check for pending guest interrupts there */
3072
3073	case VMX_EXIT_WBINVD: /* 54 Guest software attempted to execute WBINVD. (conditional) */
3074	case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. (unconditional) */
3075	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
3076	/* Skip instruction and continue directly. */
3077	pCtx->rip += cbInstr;
3078	/* Continue execution.*/
3079	goto ResumeExecution;
3080
3081	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3082	{
3083	Log2(("VMX: Cpuid %x\n", pCtx->eax));
3084	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
3085	rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3086	if (rc == VINF_SUCCESS)
3087	{
3088	/* Update EIP and continue execution. */
3089	Assert(cbInstr == 2);
3090	pCtx->rip += cbInstr;
3091	goto ResumeExecution;
3092	}
3093	AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
3094	rc = VINF_EM_RAW_EMULATE_INSTR;
3095	break;
3096	}
3097
3098	case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3099	{
3100	Log2(("VMX: Rdpmc %x\n", pCtx->ecx));
3101	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
3102	rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3103	if (rc == VINF_SUCCESS)
3104	{
3105	/* Update EIP and continue execution. */
3106	Assert(cbInstr == 2);
3107	pCtx->rip += cbInstr;
3108	goto ResumeExecution;
3109	}
3110	rc = VINF_EM_RAW_EMULATE_INSTR;
3111	break;
3112	}
3113
3114	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3115	{
3116	Log2(("VMX: Rdtsc\n"));
3117	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
3118	rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3119	if (rc == VINF_SUCCESS)
3120	{
3121	/* Update EIP and continue execution. */
3122	Assert(cbInstr == 2);
3123	pCtx->rip += cbInstr;
3124	goto ResumeExecution;
3125	}
3126	rc = VINF_EM_RAW_EMULATE_INSTR;
3127	break;
3128	}
3129
3130	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3131	{
3132	Log2(("VMX: invlpg\n"));
3133	Assert(!pVM->hwaccm.s.fNestedPaging);
3134
3135	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
3136	rc = EMInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), exitQualification);
3137	if (rc == VINF_SUCCESS)
3138	{
3139	/* Update EIP and continue execution. */
3140	pCtx->rip += cbInstr;
3141	goto ResumeExecution;
3142	}
3143	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %RGv failed with %Rrc\n", exitQualification, rc));
3144	break;
3145	}
3146
3147	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3148	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3149	{
3150	uint32_t cbSize;
3151
3152	STAM_COUNTER_INC((exitReason == VMX_EXIT_RDMSR) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
3153
3154	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
3155	Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
3156	rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
3157	if (rc == VINF_SUCCESS)
3158	{
3159	/* EIP has been updated already. */
3160
3161	/* Only resume if successful. */
3162	goto ResumeExecution;
3163	}
3164	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
3165	break;
3166	}
3167
3168	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3169	{
3170	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3171
3172	switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
3173	{
3174	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
3175	Log2(("VMX: %RGv mov cr%d, x\n", (RTGCPTR)pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
3176	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3177	rc = EMInterpretCRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3178	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
3179	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
3180
3181	switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
3182	{
3183	case 0:
3184	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_GUEST_CR3;
3185	break;
3186	case 2:
3187	break;
3188	case 3:
3189	Assert(!pVM->hwaccm.s.fNestedPaging \|\| !CPUMIsGuestInPagedProtectedModeEx(pCtx));
3190	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
3191	break;
3192	case 4:
3193	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
3194	break;
3195	case 8:
3196	/* CR8 contains the APIC TPR */
3197	Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3198	break;
3199
3200	default:
3201	AssertFailed();
3202	break;
3203	}
3204	/* Check if a sync operation is pending. */
3205	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
3206	&& VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3207	{
3208	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3209	AssertRC(rc);
3210	}
3211	break;
3212
3213	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
3214	Log2(("VMX: mov x, crx\n"));
3215	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)]);
3216
3217	Assert(!pVM->hwaccm.s.fNestedPaging \|\| !CPUMIsGuestInPagedProtectedModeEx(pCtx) \|\| VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != USE_REG_CR3);
3218
3219	/* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
3220	Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 \|\| !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
3221
3222	rc = EMInterpretCRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3223	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
3224	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
3225	break;
3226
3227	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
3228	Log2(("VMX: clts\n"));
3229	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCLTS);
3230	rc = EMInterpretCLTS(pVM, pVCpu);
3231	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
3232	break;
3233
3234	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
3235	Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
3236	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitLMSW);
3237	rc = EMInterpretLMSW(pVM, pVCpu, CPUMCTX2CORE(pCtx), VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
3238	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
3239	break;
3240	}
3241
3242	/* Update EIP if no error occurred. */
3243	if (RT_SUCCESS(rc))
3244	pCtx->rip += cbInstr;
3245
3246	if (rc == VINF_SUCCESS)
3247	{
3248	/* Only resume if successful. */
3249	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3250	goto ResumeExecution;
3251	}
3252	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
3253	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub2, y2);
3254	break;
3255	}
3256
3257	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3258	{
3259	if (!DBGFIsStepping(pVCpu))
3260	{
3261	/* Disable drx move intercepts. */
3262	pVCpu->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3263	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3264	AssertRC(rc);
3265
3266	/* Save the host and load the guest debug state. */
3267	rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, true /* include DR6 */);
3268	AssertRC(rc);
3269
3270	#ifdef VBOX_WITH_STATISTICS
3271	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
3272	if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3273	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3274	else
3275	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3276	#endif
3277
3278	goto ResumeExecution;
3279	}
3280
3281	/** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
3282	if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
3283	{
3284	Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
3285	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
3286	rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3287	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
3288	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
3289	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
3290	Log2(("DR7=%08x\n", pCtx->dr[7]));
3291	}
3292	else
3293	{
3294	Log2(("VMX: mov x, drx\n"));
3295	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
3296	rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
3297	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
3298	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
3299	}
3300	/* Update EIP if no error occurred. */
3301	if (RT_SUCCESS(rc))
3302	pCtx->rip += cbInstr;
3303
3304	if (rc == VINF_SUCCESS)
3305	{
3306	/* Only resume if successful. */
3307	goto ResumeExecution;
3308	}
3309	Assert(rc == VERR_EM_INTERPRETER);
3310	break;
3311	}
3312
3313	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
3314	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3315	{
3316	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3317	uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
3318	uint32_t uPort;
3319	bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
3320
3321	/** @todo necessary to make the distinction? */
3322	if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
3323	{
3324	uPort = pCtx->edx & 0xffff;
3325	}
3326	else
3327	uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
3328
3329	/* paranoia */
3330	if (RT_UNLIKELY(uIOWidth == 2 \|\| uIOWidth >= 4))
3331	{
3332	rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
3333	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3334	break;
3335	}
3336
3337	uint32_t cbSize = g_aIOSize[uIOWidth];
3338
3339	if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
3340	{
3341	/* ins/outs */
3342	PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
3343
3344	/* Disassemble manually to deal with segment prefixes. */
3345	/** @todo VMX_VMCS_EXIT_GUEST_LINEAR_ADDR contains the flat pointer operand of the instruction. */
3346	/** @todo VMX_VMCS32_RO_EXIT_INSTR_INFO also contains segment prefix info. */
3347	rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
3348	if (rc == VINF_SUCCESS)
3349	{
3350	if (fIOWrite)
3351	{
3352	Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3353	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
3354	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize);
3355	}
3356	else
3357	{
3358	Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, uPort, cbSize));
3359	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
3360	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, pDis->prefix, cbSize);
3361	}
3362	}
3363	else
3364	rc = VINF_EM_RAW_EMULATE_INSTR;
3365	}
3366	else
3367	{
3368	/* normal in/out */
3369	uint32_t uAndVal = g_aIOOpAnd[uIOWidth];
3370
3371	Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
3372
3373	if (fIOWrite)
3374	{
3375	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
3376	rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
3377	}
3378	else
3379	{
3380	uint32_t u32Val = 0;
3381
3382	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
3383	rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
3384	if (IOM_SUCCESS(rc))
3385	{
3386	/* Write back to the EAX register. */
3387	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
3388	}
3389	}
3390	}
3391	/*
3392	* Handled the I/O return codes.
3393	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
3394	*/
3395	if (IOM_SUCCESS(rc))
3396	{
3397	/* Update EIP and continue execution. */
3398	pCtx->rip += cbInstr;
3399	if (RT_LIKELY(rc == VINF_SUCCESS))
3400	{
3401	/* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
3402	if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
3403	{
3404	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
3405	for (unsigned i=0;i<4;i++)
3406	{
3407	unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
3408
3409	if ( (uPort >= pCtx->dr[i] && uPort < pCtx->dr[i] + uBPLen)
3410	&& (pCtx->dr[7] & (X86_DR7_L(i) \| X86_DR7_G(i)))
3411	&& (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
3412	{
3413	uint64_t uDR6;
3414
3415	Assert(CPUMIsGuestDebugStateActive(pVCpu));
3416
3417	uDR6 = ASMGetDR6();
3418
3419	/* Clear all breakpoint status flags and set the one we just hit. */
3420	uDR6 &= ~(X86_DR6_B0\|X86_DR6_B1\|X86_DR6_B2\|X86_DR6_B3);
3421	uDR6 \|= (uint64_t)RT_BIT(i);
3422
3423	/* Note: AMD64 Architecture Programmer's Manual 13.1:
3424	* Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
3425	* the contents have been read.
3426	*/
3427	ASMSetDR6(uDR6);
3428
3429	/* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
3430	pCtx->dr[7] &= ~X86_DR7_GD;
3431
3432	/* Paranoia. */
3433	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
3434	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
3435	pCtx->dr[7] \|= 0x400; /* must be one */
3436
3437	/* Resync DR7 */
3438	rc = VMXWriteVMCS64(VMX_VMCS64_GUEST_DR7, pCtx->dr[7]);
3439	AssertRC(rc);
3440
3441	/* Construct inject info. */
3442	intInfo = X86_XCPT_DB;
3443	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
3444	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
3445
3446	Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
3447	rc = VMXR0InjectEvent(pVM, pVCpu, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), 0, 0);
3448	AssertRC(rc);
3449
3450	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3451	goto ResumeExecution;
3452	}
3453	}
3454	}
3455
3456	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3457	goto ResumeExecution;
3458	}
3459	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3460	break;
3461	}
3462
3463	#ifdef VBOX_STRICT
3464	if (rc == VINF_IOM_HC_IOPORT_READ)
3465	Assert(!fIOWrite);
3466	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
3467	Assert(fIOWrite);
3468	else
3469	AssertMsg(RT_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
3470	#endif
3471	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3472	break;
3473	}
3474
3475	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3476	LogFlow(("VMX_EXIT_TPR\n"));
3477	/* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
3478	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3479	goto ResumeExecution;
3480
3481	case VMX_EXIT_APIC_ACCESS: /* 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
3482	{
3483	LogFlow(("VMX_EXIT_APIC_ACCESS\n"));
3484	unsigned uAccessType = VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(exitQualification);
3485
3486	switch(uAccessType)
3487	{
3488	case VMX_APIC_ACCESS_TYPE_LINEAR_READ:
3489	case VMX_APIC_ACCESS_TYPE_LINEAR_WRITE:
3490	{
3491	RTGCPHYS GCPhys;
3492	PDMApicGetBase(pVM, &GCPhys);
3493	GCPhys &= PAGE_BASE_GC_MASK;
3494	GCPhys += VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(exitQualification);
3495
3496	LogFlow(("Apic access at %RGp\n", GCPhys));
3497	rc = IOMMMIOPhysHandler(pVM, (uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ) ? 0 : X86_TRAP_PF_RW, CPUMCTX2CORE(pCtx), GCPhys);
3498	if (rc == VINF_SUCCESS)
3499	{
3500	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3501	goto ResumeExecution; /* rip already updated */
3502	}
3503	break;
3504	}
3505
3506	default:
3507	rc = VINF_EM_RAW_EMULATE_INSTR;
3508	break;
3509	}
3510	break;
3511	}
3512
3513	case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3514	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2Sub1, y1);
3515	goto ResumeExecution;
3516
3517	default:
3518	/* The rest is handled after syncing the entire CPU state. */
3519	break;
3520	}
3521
3522	/* Note: the guest state isn't entirely synced back at this stage. */
3523
3524	/* Investigate why there was a VM-exit. (part 2) */
3525	switch (exitReason)
3526	{
3527	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
3528	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
3529	case VMX_EXIT_EPT_VIOLATION:
3530	case VMX_EXIT_PREEMPTION_TIMER: /* 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
3531	/* Already handled above. */
3532	break;
3533
3534	case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
3535	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
3536	break;
3537
3538	case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
3539	case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
3540	rc = VINF_EM_RAW_INTERRUPT;
3541	AssertFailed(); /* Can't happen. Yet. */
3542	break;
3543
3544	case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
3545	case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
3546	rc = VINF_EM_RAW_INTERRUPT;
3547	AssertFailed(); /* Can't happen afaik. */
3548	break;
3549
3550	case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
3551	rc = VERR_EM_INTERPRETER;
3552	break;
3553
3554	case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
3555	/** Check if external interrupts are pending; if so, don't switch back. */
3556	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
3557	pCtx->rip++; /* skip hlt */
3558	if ( pCtx->eflags.Bits.u1IF
3559	&& VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC\|VMCPU_FF_INTERRUPT_PIC)))
3560	goto ResumeExecution;
3561
3562	rc = VINF_EM_HALT;
3563	break;
3564
3565	case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
3566	Log2(("VMX: mwait\n"));
3567	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
3568	rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
3569	if ( rc == VINF_EM_HALT
3570	\|\| rc == VINF_SUCCESS)
3571	{
3572	/* Update EIP and continue execution. */
3573	pCtx->rip += cbInstr;
3574
3575	/** Check if external interrupts are pending; if so, don't switch back. */
3576	if ( rc == VINF_SUCCESS
3577	\|\| ( rc == VINF_EM_HALT
3578	&& pCtx->eflags.Bits.u1IF
3579	&& VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC\|VMCPU_FF_INTERRUPT_PIC)))
3580	)
3581	goto ResumeExecution;
3582	}
3583	AssertMsg(rc == VERR_EM_INTERPRETER \|\| rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
3584	break;
3585
3586	case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
3587	AssertFailed(); /* can't happen. */
3588	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3589	break;
3590
3591	case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
3592	case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
3593	case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
3594	case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
3595	case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
3596	case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
3597	case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
3598	case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
3599	case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
3600	case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
3601	/** @todo inject #UD immediately */
3602	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3603	break;
3604
3605	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
3606	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
3607	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
3608	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
3609	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
3610	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
3611	case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
3612	/* already handled above */
3613	AssertMsg( rc == VINF_PGM_CHANGE_MODE
3614	\|\| rc == VINF_EM_RAW_INTERRUPT
3615	\|\| rc == VERR_EM_INTERPRETER
3616	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
3617	\|\| rc == VINF_PGM_SYNC_CR3
3618	\|\| rc == VINF_IOM_HC_IOPORT_READ
3619	\|\| rc == VINF_IOM_HC_IOPORT_WRITE
3620	\|\| rc == VINF_EM_RAW_GUEST_TRAP
3621	\|\| rc == VINF_TRPM_XCPT_DISPATCHED
3622	\|\| rc == VINF_EM_RESCHEDULE_REM,
3623	("rc = %d\n", rc));
3624	break;
3625
3626	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
3627	case VMX_EXIT_APIC_ACCESS: /* 44 APIC access. Guest software attempted to access memory at a physical address on the APIC-access page. */
3628	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
3629	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
3630	/* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
3631	rc = VERR_EM_INTERPRETER;
3632	break;
3633
3634	case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
3635	case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
3636	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
3637	break;
3638
3639	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
3640	Assert(rc == VINF_EM_RAW_INTERRUPT);
3641	break;
3642
3643	case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
3644	{
3645	#ifdef VBOX_STRICT
3646	RTCCUINTREG val = 0;
3647
3648	Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
3649
3650	VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3651	Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3652
3653	VMXReadVMCS(VMX_VMCS64_GUEST_CR0, &val);
3654	Log(("VMX_VMCS_GUEST_CR0 %RX64\n", (uint64_t)val));
3655
3656	VMXReadVMCS(VMX_VMCS64_GUEST_CR3, &val);
3657	Log(("VMX_VMCS_GUEST_CR3 %RX64\n", (uint64_t)val));
3658
3659	VMXReadVMCS(VMX_VMCS64_GUEST_CR4, &val);
3660	Log(("VMX_VMCS_GUEST_CR4 %RX64\n", (uint64_t)val));
3661
3662	VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3663	Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3664
3665	VMX_LOG_SELREG(CS, "CS");
3666	VMX_LOG_SELREG(DS, "DS");
3667	VMX_LOG_SELREG(ES, "ES");
3668	VMX_LOG_SELREG(FS, "FS");
3669	VMX_LOG_SELREG(GS, "GS");
3670	VMX_LOG_SELREG(SS, "SS");
3671	VMX_LOG_SELREG(TR, "TR");
3672	VMX_LOG_SELREG(LDTR, "LDTR");
3673
3674	VMXReadVMCS(VMX_VMCS64_GUEST_GDTR_BASE, &val);
3675	Log(("VMX_VMCS_GUEST_GDTR_BASE %RX64\n", (uint64_t)val));
3676	VMXReadVMCS(VMX_VMCS64_GUEST_IDTR_BASE, &val);
3677	Log(("VMX_VMCS_GUEST_IDTR_BASE %RX64\n", (uint64_t)val));
3678	#endif /* VBOX_STRICT */
3679	rc = VERR_VMX_INVALID_GUEST_STATE;
3680	break;
3681	}
3682
3683	case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
3684	case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
3685	default:
3686	rc = VERR_VMX_UNEXPECTED_EXIT_CODE;
3687	AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
3688	break;
3689
3690	}
3691	end:
3692
3693	/* Signal changes for the recompiler. */
3694	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
3695
3696	/* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
3697	if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
3698	&& !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
3699	{
3700	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
3701	/* On the next entry we'll only sync the host context. */
3702	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
3703	}
3704	else
3705	{
3706	/* On the next entry we'll sync everything. */
3707	/** @todo we can do better than this */
3708	/* Not in the VINF_PGM_CHANGE_MODE though! */
3709	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
3710	}
3711
3712	/* translate into a less severe return code */
3713	if (rc == VERR_EM_INTERPRETER)
3714	rc = VINF_EM_RAW_EMULATE_INSTR;
3715	else
3716	/* Try to extract more information about what might have gone wrong here. */
3717	if (rc == VERR_VMX_INVALID_VMCS_PTR)
3718	{
3719	VMXGetActivateVMCS(&pVCpu->hwaccm.s.vmx.lasterror.u64VMCSPhys);
3720	pVCpu->hwaccm.s.vmx.lasterror.ulVMCSRevision = (uint32_t )pVCpu->hwaccm.s.vmx.pVMCS;
3721	pVCpu->hwaccm.s.vmx.lasterror.idEnteredCpu = pVCpu->hwaccm.s.idEnteredCpu;
3722	pVCpu->hwaccm.s.vmx.lasterror.idCurrentCpu = RTMpCpuId();
3723	}
3724
3725	/* Just set the correct state here instead of trying to catch every goto above. */
3726	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
3727
3728	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
3729	/* Restore interrupts if we exitted after disabling them. */
3730	if (uOldEFlags != ~(RTCCUINTREG)0)
3731	ASMSetFlags(uOldEFlags);
3732	#endif
3733
3734	STAM_STATS({
3735	if (fStatExit2Started) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, y);
3736	else if (fStatEntryStarted) STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
3737	});
3738	Log2(("X"));
3739	return rc;
3740	}
3741
3742
3743	/**
3744	* Enters the VT-x session
3745	*
3746	* @returns VBox status code.
3747	* @param pVM The VM to operate on.
3748	* @param pVCpu The VMCPU to operate on.
3749	* @param pCpu CPU info struct
3750	*/
3751	VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
3752	{
3753	Assert(pVM->hwaccm.s.vmx.fSupported);
3754
3755	unsigned cr4 = ASMGetCR4();
3756	if (!(cr4 & X86_CR4_VMXE))
3757	{
3758	AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
3759	return VERR_VMX_X86_CR4_VMXE_CLEARED;
3760	}
3761
3762	/* Activate the VM Control Structure. */
3763	int rc = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3764	if (RT_FAILURE(rc))
3765	return rc;
3766
3767	pVCpu->hwaccm.s.fResumeVM = false;
3768	return VINF_SUCCESS;
3769	}
3770
3771
3772	/**
3773	* Leaves the VT-x session
3774	*
3775	* @returns VBox status code.
3776	* @param pVM The VM to operate on.
3777	* @param pVCpu The VMCPU to operate on.
3778	* @param pCtx CPU context
3779	*/
3780	VMMR0DECL(int) VMXR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3781	{
3782	Assert(pVM->hwaccm.s.vmx.fSupported);
3783
3784	/* Save the guest debug state if necessary. */
3785	if (CPUMIsGuestDebugStateActive(pVCpu))
3786	{
3787	CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, true /* save DR6 */);
3788
3789	/* Enable drx move intercepts again. */
3790	pVCpu->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT;
3791	int rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVCpu->hwaccm.s.vmx.proc_ctls);
3792	AssertRC(rc);
3793
3794	/* Resync the debug registers the next time. */
3795	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
3796	}
3797	else
3798	Assert(pVCpu->hwaccm.s.vmx.proc_ctls & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
3799
3800	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
3801	int rc = VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
3802	AssertRC(rc);
3803
3804	return VINF_SUCCESS;
3805	}
3806
3807	/**
3808	* Flush the TLB (EPT)
3809	*
3810	* @returns VBox status code.
3811	* @param pVM The VM to operate on.
3812	* @param pVCpu The VM CPU to operate on.
3813	* @param enmFlush Type of flush
3814	* @param GCPhys Physical address of the page to flush
3815	*/
3816	static void vmxR0FlushEPT(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPHYS GCPhys)
3817	{
3818	uint64_t descriptor[2];
3819
3820	LogFlow(("vmxR0FlushEPT %d %RGv\n", enmFlush, GCPhys));
3821	Assert(pVM->hwaccm.s.fNestedPaging);
3822	descriptor[0] = pVCpu->hwaccm.s.vmx.GCPhysEPTP;
3823	descriptor[1] = GCPhys;
3824	int rc = VMXR0InvEPT(enmFlush, &descriptor[0]);
3825	AssertRC(rc);
3826	}
3827
3828	#ifdef HWACCM_VTX_WITH_VPID
3829	/**
3830	* Flush the TLB (EPT)
3831	*
3832	* @returns VBox status code.
3833	* @param pVM The VM to operate on.
3834	* @param pVCpu The VM CPU to operate on.
3835	* @param enmFlush Type of flush
3836	* @param GCPtr Virtual address of the page to flush
3837	*/
3838	static void vmxR0FlushVPID(PVM pVM, PVMCPU pVCpu, VMX_FLUSH enmFlush, RTGCPTR GCPtr)
3839	{
3840	#if HC_ARCH_BITS == 32
3841	/* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invvpid probably takes only 32 bits addresses. (@todo) */
3842	if ( CPUMIsGuestInLongMode(pVCpu)
3843	&& !VMX_IS_64BIT_HOST_MODE())
3844	{
3845	pVCpu->hwaccm.s.fForceTLBFlush = true;
3846	}
3847	else
3848	#endif
3849	{
3850	uint64_t descriptor[2];
3851
3852	Assert(pVM->hwaccm.s.vmx.fVPID);
3853	descriptor[0] = pVCpu->hwaccm.s.uCurrentASID;
3854	descriptor[1] = GCPtr;
3855	int rc = VMXR0InvVPID(enmFlush, &descriptor[0]);
3856	AssertRC(rc);
3857	}
3858	}
3859	#endif /* HWACCM_VTX_WITH_VPID */
3860
3861	/**
3862	* Invalidates a guest page
3863	*
3864	* @returns VBox status code.
3865	* @param pVM The VM to operate on.
3866	* @param pVCpu The VM CPU to operate on.
3867	* @param GCVirt Page to invalidate
3868	*/
3869	VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
3870	{
3871	bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3872
3873	Log2(("VMXR0InvalidatePage %RGv\n", GCVirt));
3874
3875	/* Only relevant if we want to use VPID.
3876	* In the nested paging case we still see such calls, but
3877	* can safely ignore them. (e.g. after cr3 updates)
3878	*/
3879	#ifdef HWACCM_VTX_WITH_VPID
3880	/* Skip it if a TLB flush is already pending. */
3881	if ( !fFlushPending
3882	&& pVM->hwaccm.s.vmx.fVPID)
3883	vmxR0FlushVPID(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCVirt);
3884	#endif /* HWACCM_VTX_WITH_VPID */
3885
3886	return VINF_SUCCESS;
3887	}
3888
3889	/**
3890	* Invalidates a guest page by physical address
3891	*
3892	* NOTE: Assumes the current instruction references this physical page though a virtual address!!
3893	*
3894	* @returns VBox status code.
3895	* @param pVM The VM to operate on.
3896	* @param pVCpu The VM CPU to operate on.
3897	* @param GCPhys Page to invalidate
3898	*/
3899	VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
3900	{
3901	bool fFlushPending = pVCpu->hwaccm.s.fForceTLBFlush;
3902
3903	Assert(pVM->hwaccm.s.fNestedPaging);
3904
3905	LogFlow(("VMXR0InvalidatePhysPage %RGp\n", GCPhys));
3906
3907	/* Skip it if a TLB flush is already pending. */
3908	if (!fFlushPending)
3909	vmxR0FlushEPT(pVM, pVCpu, pVM->hwaccm.s.vmx.enmFlushPage, GCPhys);
3910
3911	return VINF_SUCCESS;
3912	}
3913
3914	/**
3915	* Report world switch error and dump some useful debug info
3916	*
3917	* @param pVM The VM to operate on.
3918	* @param pVCpu The VMCPU to operate on.
3919	* @param rc Return code
3920	* @param pCtx Current CPU context (not updated)
3921	*/
3922	static void VMXR0ReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTX pCtx)
3923	{
3924	switch (rc)
3925	{
3926	case VERR_VMX_INVALID_VMXON_PTR:
3927	AssertFailed();
3928	break;
3929
3930	case VERR_VMX_UNABLE_TO_START_VM:
3931	case VERR_VMX_UNABLE_TO_RESUME_VM:
3932	{
3933	int rc;
3934	RTCCUINTREG exitReason, instrError;
3935
3936	rc = VMXReadVMCS(VMX_VMCS32_RO_EXIT_REASON, &exitReason);
3937	rc \|= VMXReadVMCS(VMX_VMCS32_RO_VM_INSTR_ERROR, &instrError);
3938	AssertRC(rc);
3939	if (rc == VINF_SUCCESS)
3940	{
3941	Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
3942	Log(("Current stack %08x\n", &rc));
3943
3944	pVCpu->hwaccm.s.vmx.lasterror.ulInstrError = instrError;
3945	pVCpu->hwaccm.s.vmx.lasterror.ulExitReason = exitReason;
3946
3947	#ifdef VBOX_STRICT
3948	RTGDTR gdtr;
3949	PX86DESCHC pDesc;
3950	RTCCUINTREG val;
3951
3952	ASMGetGDTR(&gdtr);
3953
3954	VMXReadVMCS(VMX_VMCS64_GUEST_RIP, &val);
3955	Log(("Old eip %RGv new %RGv\n", (RTGCPTR)pCtx->rip, (RTGCPTR)val));
3956	VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
3957	Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
3958	VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
3959	Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
3960	VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
3961	Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
3962	VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
3963	Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
3964
3965	VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
3966	Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
3967
3968	VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
3969	Log(("VMX_VMCS_HOST_CR3 %08x\n", val));
3970
3971	VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
3972	Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
3973
3974	VMXReadVMCS(VMX_VMCS16_HOST_FIELD_CS, &val);
3975	Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
3976
3977	VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
3978	Log(("VMX_VMCS_GUEST_RFLAGS %08x\n", val));
3979
3980	if (val < gdtr.cbGdt)
3981	{
3982	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3983	HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
3984	}
3985
3986	VMXReadVMCS(VMX_VMCS16_HOST_FIELD_DS, &val);
3987	Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
3988	if (val < gdtr.cbGdt)
3989	{
3990	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3991	HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
3992	}
3993
3994	VMXReadVMCS(VMX_VMCS16_HOST_FIELD_ES, &val);
3995	Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
3996	if (val < gdtr.cbGdt)
3997	{
3998	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
3999	HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
4000	}
4001
4002	VMXReadVMCS(VMX_VMCS16_HOST_FIELD_FS, &val);
4003	Log(("VMX_VMCS16_HOST_FIELD_FS %08x\n", val));
4004	if (val < gdtr.cbGdt)
4005	{
4006	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4007	HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
4008	}
4009
4010	VMXReadVMCS(VMX_VMCS16_HOST_FIELD_GS, &val);
4011	Log(("VMX_VMCS16_HOST_FIELD_GS %08x\n", val));
4012	if (val < gdtr.cbGdt)
4013	{
4014	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4015	HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
4016	}
4017
4018	VMXReadVMCS(VMX_VMCS16_HOST_FIELD_SS, &val);
4019	Log(("VMX_VMCS16_HOST_FIELD_SS %08x\n", val));
4020	if (val < gdtr.cbGdt)
4021	{
4022	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4023	HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
4024	}
4025
4026	VMXReadVMCS(VMX_VMCS16_HOST_FIELD_TR, &val);
4027	Log(("VMX_VMCS16_HOST_FIELD_TR %08x\n", val));
4028	if (val < gdtr.cbGdt)
4029	{
4030	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
4031	HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
4032	}
4033
4034	VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
4035	Log(("VMX_VMCS_HOST_TR_BASE %RHv\n", val));
4036
4037	VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
4038	Log(("VMX_VMCS_HOST_GDTR_BASE %RHv\n", val));
4039	VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
4040	Log(("VMX_VMCS_HOST_IDTR_BASE %RHv\n", val));
4041
4042	VMXReadVMCS(VMX_VMCS32_HOST_SYSENTER_CS, &val);
4043	Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
4044
4045	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
4046	Log(("VMX_VMCS_HOST_SYSENTER_EIP %RHv\n", val));
4047
4048	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
4049	Log(("VMX_VMCS_HOST_SYSENTER_ESP %RHv\n", val));
4050
4051	VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
4052	Log(("VMX_VMCS_HOST_RSP %RHv\n", val));
4053	VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
4054	Log(("VMX_VMCS_HOST_RIP %RHv\n", val));
4055
4056	# if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4057	if (VMX_IS_64BIT_HOST_MODE())
4058	{
4059	Log(("MSR_K6_EFER = %RX64\n", ASMRdMsr(MSR_K6_EFER)));
4060	Log(("MSR_K6_STAR = %RX64\n", ASMRdMsr(MSR_K6_STAR)));
4061	Log(("MSR_K8_LSTAR = %RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
4062	Log(("MSR_K8_CSTAR = %RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
4063	Log(("MSR_K8_SF_MASK = %RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
4064	}
4065	# endif
4066	#endif /* VBOX_STRICT */
4067	}
4068	break;
4069	}
4070
4071	default:
4072	/* impossible */
4073	AssertMsgFailed(("%Rrc (%#x)\n", rc, rc));
4074	break;
4075	}
4076	}
4077
4078	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
4079	/**
4080	* Prepares for and executes VMLAUNCH (64 bits guest mode)
4081	*
4082	* @returns VBox status code
4083	* @param fResume vmlauch/vmresume
4084	* @param pCtx Guest context
4085	* @param pCache VMCS cache
4086	* @param pVM The VM to operate on.
4087	* @param pVCpu The VMCPU to operate on.
4088	*/
4089	DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
4090	{
4091	uint32_t aParam[6];
4092	PHWACCM_CPUINFO pCpu;
4093	RTHCPHYS pPageCpuPhys;
4094	int rc;
4095
4096	pCpu = HWACCMR0GetCurrentCpu();
4097	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
4098
4099	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4100	pCache->uPos = 1;
4101	pCache->interPD = PGMGetInterPaeCR3(pVM);
4102	pCache->pSwitcher = (uint64_t)pVM->hwaccm.s.pfnHost32ToGuest64R0;
4103	#endif
4104
4105	#ifdef DEBUG
4106	pCache->TestIn.pPageCpuPhys = 0;
4107	pCache->TestIn.pVMCSPhys = 0;
4108	pCache->TestIn.pCache = 0;
4109	pCache->TestOut.pVMCSPhys = 0;
4110	pCache->TestOut.pCache = 0;
4111	pCache->TestOut.pCtx = 0;
4112	pCache->TestOut.eflags = 0;
4113	#endif
4114
4115	aParam[0] = (uint32_t)(pPageCpuPhys); /* Param 1: VMXON physical address - Lo. */
4116	aParam[1] = (uint32_t)(pPageCpuPhys >> 32); /* Param 1: VMXON physical address - Hi. */
4117	aParam[2] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys); /* Param 2: VMCS physical address - Lo. */
4118	aParam[3] = (uint32_t)(pVCpu->hwaccm.s.vmx.pVMCSPhys >> 32); /* Param 2: VMCS physical address - Hi. */
4119	aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache);
4120	aParam[5] = 0;
4121
4122	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4123	pCtx->dr[4] = pVM->hwaccm.s.vmx.pScratchPhys + 16 + 8;
4124	(uint32_t )(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 1;
4125	#endif
4126	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnVMXGCStartVM64, 6, &aParam[0]);
4127
4128	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
4129	Assert((uint32_t )(pVM->hwaccm.s.vmx.pScratch + 16 + 8) == 5);
4130	Assert(pCtx->dr[4] == 10);
4131	(uint32_t )(pVM->hwaccm.s.vmx.pScratch + 16 + 8) = 0xff;
4132	#endif
4133
4134	#ifdef DEBUG
4135	AssertMsg(pCache->TestIn.pPageCpuPhys == pPageCpuPhys, ("%RHp vs %RHp\n", pCache->TestIn.pPageCpuPhys, pPageCpuPhys));
4136	AssertMsg(pCache->TestIn.pVMCSPhys == pVCpu->hwaccm.s.vmx.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pVCpu->hwaccm.s.vmx.pVMCSPhys));
4137	AssertMsg(pCache->TestIn.pVMCSPhys == pCache->TestOut.pVMCSPhys, ("%RHp vs %RHp\n", pCache->TestIn.pVMCSPhys, pCache->TestOut.pVMCSPhys));
4138	AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache, pCache->TestOut.pCache));
4139	AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache), ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hwaccm.s.vmx.VMCSCache)));
4140	AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx, pCache->TestOut.pCtx));
4141	Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
4142	#endif
4143	return rc;
4144	}
4145
4146	/**
4147	* Executes the specified handler in 64 mode
4148	*
4149	* @returns VBox status code.
4150	* @param pVM The VM to operate on.
4151	* @param pVCpu The VMCPU to operate on.
4152	* @param pCtx Guest context
4153	* @param pfnHandler RC handler
4154	* @param cbParam Number of parameters
4155	* @param paParam Array of 32 bits parameters
4156	*/
4157	VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
4158	{
4159	int rc, rc2;
4160	PHWACCM_CPUINFO pCpu;
4161	RTHCPHYS pPageCpuPhys;
4162
4163	/* @todo This code is not guest SMP safe (hyper stack and switchers) */
4164	AssertReturn(pVM->cCPUs == 1, VERR_TOO_MANY_CPUS);
4165	AssertReturn(pVM->hwaccm.s.pfnHost32ToGuest64R0, VERR_INTERNAL_ERROR);
4166	Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField));
4167	Assert(pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField));
4168
4169	#ifdef VBOX_STRICT
4170	for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Write.cValidEntries;i++)
4171	Assert(vmxR0IsValidWriteField(pVCpu->hwaccm.s.vmx.VMCSCache.Write.aField[i]));
4172
4173	for (unsigned i=0;i<pVCpu->hwaccm.s.vmx.VMCSCache.Read.cValidEntries;i++)
4174	Assert(vmxR0IsValidReadField(pVCpu->hwaccm.s.vmx.VMCSCache.Read.aField[i]));
4175	#endif
4176
4177	pCpu = HWACCMR0GetCurrentCpu();
4178	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
4179
4180	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
4181	VMXClearVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4182
4183	/* Leave VMX Root Mode. */
4184	VMXDisable();
4185
4186	ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
4187
4188	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVM));
4189	CPUMSetHyperEIP(pVCpu, pfnHandler);
4190	for (int i=(int)cbParam-1;i>=0;i--)
4191	CPUMPushHyper(pVCpu, paParam[i]);
4192
4193	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
4194	/* Call switcher. */
4195	rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
4196	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
4197
4198	/* Make sure the VMX instructions don't cause #UD faults. */
4199	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
4200
4201	/* Enter VMX Root Mode */
4202	rc2 = VMXEnable(pPageCpuPhys);
4203	if (RT_FAILURE(rc2))
4204	{
4205	if (pVM)
4206	VMXR0CheckError(pVM, pVCpu, rc2);
4207	ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
4208	return VERR_VMX_VMXON_FAILED;
4209	}
4210
4211	rc2 = VMXActivateVMCS(pVCpu->hwaccm.s.vmx.pVMCSPhys);
4212	AssertRCReturn(rc2, rc2);
4213	#ifdef RT_OS_WINDOWS
4214	Assert(ASMGetFlags() & X86_EFL_IF);
4215	#else
4216	Assert(!(ASMGetFlags() & X86_EFL_IF));
4217	#endif
4218	return rc;
4219	}
4220
4221	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
4222
4223
4224	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4225	/**
4226	* Executes VMWRITE
4227	*
4228	* @returns VBox status code
4229	* @param pVCpu The VMCPU to operate on.
4230	* @param idxField VMCS index
4231	* @param u64Val 16, 32 or 64 bits value
4232	*/
4233	VMMR0DECL(int) VMXWriteVMCS64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4234	{
4235	int rc;
4236
4237	switch (idxField)
4238	{
4239	case VMX_VMCS_CTRL_TSC_OFFSET_FULL:
4240	case VMX_VMCS_CTRL_IO_BITMAP_A_FULL:
4241	case VMX_VMCS_CTRL_IO_BITMAP_B_FULL:
4242	case VMX_VMCS_CTRL_MSR_BITMAP_FULL:
4243	case VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL:
4244	case VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL:
4245	case VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL:
4246	case VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL:
4247	case VMX_VMCS_CTRL_APIC_ACCESSADDR_FULL:
4248	case VMX_VMCS_GUEST_LINK_PTR_FULL:
4249	case VMX_VMCS_GUEST_PDPTR0_FULL:
4250	case VMX_VMCS_GUEST_PDPTR1_FULL:
4251	case VMX_VMCS_GUEST_PDPTR2_FULL:
4252	case VMX_VMCS_GUEST_PDPTR3_FULL:
4253	case VMX_VMCS_GUEST_DEBUGCTL_FULL:
4254	case VMX_VMCS_GUEST_EFER_FULL:
4255	case VMX_VMCS_CTRL_EPTP_FULL:
4256	/* These fields consist of two parts, which are both writable in 32 bits mode. */
4257	rc = VMXWriteVMCS32(idxField, u64Val);
4258	rc \|= VMXWriteVMCS32(idxField + 1, (uint32_t)(u64Val >> 32ULL));
4259	AssertRC(rc);
4260	return rc;
4261
4262	case VMX_VMCS64_GUEST_LDTR_BASE:
4263	case VMX_VMCS64_GUEST_TR_BASE:
4264	case VMX_VMCS64_GUEST_GDTR_BASE:
4265	case VMX_VMCS64_GUEST_IDTR_BASE:
4266	case VMX_VMCS64_GUEST_SYSENTER_EIP:
4267	case VMX_VMCS64_GUEST_SYSENTER_ESP:
4268	case VMX_VMCS64_GUEST_CR0:
4269	case VMX_VMCS64_GUEST_CR4:
4270	case VMX_VMCS64_GUEST_CR3:
4271	case VMX_VMCS64_GUEST_DR7:
4272	case VMX_VMCS64_GUEST_RIP:
4273	case VMX_VMCS64_GUEST_RSP:
4274	case VMX_VMCS64_GUEST_CS_BASE:
4275	case VMX_VMCS64_GUEST_DS_BASE:
4276	case VMX_VMCS64_GUEST_ES_BASE:
4277	case VMX_VMCS64_GUEST_FS_BASE:
4278	case VMX_VMCS64_GUEST_GS_BASE:
4279	case VMX_VMCS64_GUEST_SS_BASE:
4280	/* Queue a 64 bits value as we can't set it in 32 bits host mode. */
4281	if (u64Val >> 32ULL)
4282	rc = VMXWriteCachedVMCSEx(pVCpu, idxField, u64Val);
4283	else
4284	rc = VMXWriteVMCS32(idxField, (uint32_t)u64Val);
4285
4286	return rc;
4287
4288	default:
4289	AssertMsgFailed(("Unexpected field %x\n", idxField));
4290	return VERR_INVALID_PARAMETER;
4291	}
4292	}
4293
4294	/**
4295	* Cache VMCS writes for performance reasons (Darwin) and for running 64 bits guests on 32 bits hosts.
4296	*
4297	* @param pVCpu The VMCPU to operate on.
4298	* @param idxField VMCS field
4299	* @param u64Val Value
4300	*/
4301	VMMR0DECL(int) VMXWriteCachedVMCSEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
4302	{
4303	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
4304
4305	AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1, ("entries=%x\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
4306
4307	/* Make sure there are no duplicates. */
4308	for (unsigned i=0;i<pCache->Write.cValidEntries;i++)
4309	{
4310	if (pCache->Write.aField[i] == idxField)
4311	{
4312	pCache->Write.aFieldVal[i] = u64Val;
4313	return VINF_SUCCESS;
4314	}
4315	}
4316
4317	pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
4318	pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
4319	pCache->Write.cValidEntries++;
4320	return VINF_SUCCESS;
4321	}
4322
4323	#endif /* HC_ARCH_BITS == 32 && !VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0 */
4324
4325	#ifdef VBOX_STRICT
4326	static bool vmxR0IsValidReadField(uint32_t idxField)
4327	{
4328	switch(idxField)
4329	{
4330	case VMX_VMCS64_GUEST_RIP:
4331	case VMX_VMCS64_GUEST_RSP:
4332	case VMX_VMCS_GUEST_RFLAGS:
4333	case VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE:
4334	case VMX_VMCS_CTRL_CR0_READ_SHADOW:
4335	case VMX_VMCS64_GUEST_CR0:
4336	case VMX_VMCS_CTRL_CR4_READ_SHADOW:
4337	case VMX_VMCS64_GUEST_CR4:
4338	case VMX_VMCS64_GUEST_DR7:
4339	case VMX_VMCS32_GUEST_SYSENTER_CS:
4340	case VMX_VMCS64_GUEST_SYSENTER_EIP:
4341	case VMX_VMCS64_GUEST_SYSENTER_ESP:
4342	case VMX_VMCS32_GUEST_GDTR_LIMIT:
4343	case VMX_VMCS64_GUEST_GDTR_BASE:
4344	case VMX_VMCS32_GUEST_IDTR_LIMIT:
4345	case VMX_VMCS64_GUEST_IDTR_BASE:
4346	case VMX_VMCS16_GUEST_FIELD_CS:
4347	case VMX_VMCS32_GUEST_CS_LIMIT:
4348	case VMX_VMCS64_GUEST_CS_BASE:
4349	case VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS:
4350	case VMX_VMCS16_GUEST_FIELD_DS:
4351	case VMX_VMCS32_GUEST_DS_LIMIT:
4352	case VMX_VMCS64_GUEST_DS_BASE:
4353	case VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS:
4354	case VMX_VMCS16_GUEST_FIELD_ES:
4355	case VMX_VMCS32_GUEST_ES_LIMIT:
4356	case VMX_VMCS64_GUEST_ES_BASE:
4357	case VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS:
4358	case VMX_VMCS16_GUEST_FIELD_FS:
4359	case VMX_VMCS32_GUEST_FS_LIMIT:
4360	case VMX_VMCS64_GUEST_FS_BASE:
4361	case VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS:
4362	case VMX_VMCS16_GUEST_FIELD_GS:
4363	case VMX_VMCS32_GUEST_GS_LIMIT:
4364	case VMX_VMCS64_GUEST_GS_BASE:
4365	case VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS:
4366	case VMX_VMCS16_GUEST_FIELD_SS:
4367	case VMX_VMCS32_GUEST_SS_LIMIT:
4368	case VMX_VMCS64_GUEST_SS_BASE:
4369	case VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS:
4370	case VMX_VMCS16_GUEST_FIELD_LDTR:
4371	case VMX_VMCS32_GUEST_LDTR_LIMIT:
4372	case VMX_VMCS64_GUEST_LDTR_BASE:
4373	case VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS:
4374	case VMX_VMCS16_GUEST_FIELD_TR:
4375	case VMX_VMCS32_GUEST_TR_LIMIT:
4376	case VMX_VMCS64_GUEST_TR_BASE:
4377	case VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS:
4378	case VMX_VMCS32_RO_EXIT_REASON:
4379	case VMX_VMCS32_RO_VM_INSTR_ERROR:
4380	case VMX_VMCS32_RO_EXIT_INSTR_LENGTH:
4381	case VMX_VMCS32_RO_EXIT_INTERRUPTION_ERRCODE:
4382	case VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO:
4383	case VMX_VMCS32_RO_EXIT_INSTR_INFO:
4384	case VMX_VMCS_RO_EXIT_QUALIFICATION:
4385	case VMX_VMCS32_RO_IDT_INFO:
4386	case VMX_VMCS32_RO_IDT_ERRCODE:
4387	case VMX_VMCS64_GUEST_CR3:
4388	case VMX_VMCS_EXIT_PHYS_ADDR_FULL:
4389	return true;
4390	}
4391	return false;
4392	}
4393
4394	static bool vmxR0IsValidWriteField(uint32_t idxField)
4395	{
4396	switch(idxField)
4397	{
4398	case VMX_VMCS64_GUEST_LDTR_BASE:
4399	case VMX_VMCS64_GUEST_TR_BASE:
4400	case VMX_VMCS64_GUEST_GDTR_BASE:
4401	case VMX_VMCS64_GUEST_IDTR_BASE:
4402	case VMX_VMCS64_GUEST_SYSENTER_EIP:
4403	case VMX_VMCS64_GUEST_SYSENTER_ESP:
4404	case VMX_VMCS64_GUEST_CR0:
4405	case VMX_VMCS64_GUEST_CR4:
4406	case VMX_VMCS64_GUEST_CR3:
4407	case VMX_VMCS64_GUEST_DR7:
4408	case VMX_VMCS64_GUEST_RIP:
4409	case VMX_VMCS64_GUEST_RSP:
4410	case VMX_VMCS64_GUEST_CS_BASE:
4411	case VMX_VMCS64_GUEST_DS_BASE:
4412	case VMX_VMCS64_GUEST_ES_BASE:
4413	case VMX_VMCS64_GUEST_FS_BASE:
4414	case VMX_VMCS64_GUEST_GS_BASE:
4415	case VMX_VMCS64_GUEST_SS_BASE:
4416	return true;
4417	}
4418	return false;
4419	}
4420
4421	#endif

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 20543

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