HWVMXR0.cpp@ 11347

Last change on this file since 11347 was 10886, checked in by vboxsync, 16 years ago
Fixes for syncing back sysenter MSRs.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 85.3 KB

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1	/* $Id: HWVMXR0.cpp 10886 2008-07-25 11:30:55Z vboxsync $ */
2	/** @file
3	* HWACCM VMX - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/pgm.h>
32	#include <VBox/pdm.h>
33	#include <VBox/err.h>
34	#include <VBox/log.h>
35	#include <VBox/selm.h>
36	#include <VBox/iom.h>
37	#include <iprt/param.h>
38	#include <iprt/assert.h>
39	#include <iprt/asm.h>
40	#include <iprt/string.h>
41	#include "HWVMXR0.h"
42
43
44	/* IO operation lookup arrays. */
45	static uint32_t aIOSize[4] = {1, 2, 0, 4};
46	static uint32_t aIOOpAnd[4] = {0xff, 0xffff, 0, 0xffffffff};
47
48
49	static void VMXR0CheckError(PVM pVM, int rc)
50	{
51	if (rc == VERR_VMX_GENERIC)
52	{
53	RTCCUINTREG instrError;
54
55	VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
56	pVM->hwaccm.s.vmx.ulLastInstrError = instrError;
57	}
58	pVM->hwaccm.s.lLastError = rc;
59	}
60
61	/**
62	* Sets up and activates VT-x on the current CPU
63	*
64	* @returns VBox status code.
65	* @param pCpu CPU info struct
66	* @param pVM The VM to operate on.
67	* @param pvPageCpu Pointer to the global cpu page
68	* @param pPageCpuPhys Physical address of the global cpu page
69	*/
70	HWACCMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
71	{
72	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
73	AssertReturn(pVM, VERR_INVALID_PARAMETER);
74	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
75
76	/* Setup Intel VMX. */
77	Assert(pVM->hwaccm.s.vmx.fSupported);
78
79	#ifdef LOG_ENABLED
80	SUPR0Printf("VMXR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
81	#endif
82	/* Set revision dword at the beginning of the VMXON structure. */
83	(uint32_t )pvPageCpu = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
84
85	/* @todo we should unmap the two pages from the virtual address space in order to prevent accidental corruption.
86	* (which can have very bad consequences!!!)
87	*/
88
89	/* Make sure the VMX instructions don't cause #UD faults. */
90	ASMSetCR4(ASMGetCR4() \| X86_CR4_VMXE);
91
92	/* Enter VMX Root Mode */
93	int rc = VMXEnable(pPageCpuPhys);
94	if (VBOX_FAILURE(rc))
95	{
96	VMXR0CheckError(pVM, rc);
97	ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
98	return VERR_VMX_VMXON_FAILED;
99	}
100	return VINF_SUCCESS;
101	}
102
103	/**
104	* Deactivates VT-x on the current CPU
105	*
106	* @returns VBox status code.
107	* @param pCpu CPU info struct
108	* @param pvPageCpu Pointer to the global cpu page
109	* @param pPageCpuPhys Physical address of the global cpu page
110	*/
111	HWACCMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
112	{
113	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
114	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
115
116	/* Leave VMX Root Mode. */
117	VMXDisable();
118
119	/* And clear the X86_CR4_VMXE bit */
120	ASMSetCR4(ASMGetCR4() & ~X86_CR4_VMXE);
121
122	#ifdef LOG_ENABLED
123	SUPR0Printf("VMXR0DisableCpu cpu %d\n", pCpu->idCpu);
124	#endif
125	return VINF_SUCCESS;
126	}
127
128	/**
129	* Does Ring-0 per VM VT-x init.
130	*
131	* @returns VBox status code.
132	* @param pVM The VM to operate on.
133	*/
134	HWACCMR0DECL(int) VMXR0InitVM(PVM pVM)
135	{
136	int rc;
137
138	#ifdef LOG_ENABLED
139	SUPR0Printf("VMXR0InitVM %x\n", pVM);
140	#endif
141	pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
142	pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
143	pVM->hwaccm.s.vmx.pMemObjRealModeTSS = NIL_RTR0MEMOBJ;
144
145
146	/* Allocate one page for the VM control structure (VMCS). */
147	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjVMCS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
148	AssertRC(rc);
149	if (RT_FAILURE(rc))
150	return rc;
151
152	pVM->hwaccm.s.vmx.pVMCS = RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjVMCS);
153	pVM->hwaccm.s.vmx.pVMCSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjVMCS, 0);
154	ASMMemZero32(pVM->hwaccm.s.vmx.pVMCS, PAGE_SIZE);
155
156	/* Allocate one page for the TSS we need for real mode emulation. */
157	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
158	AssertRC(rc);
159	if (RT_FAILURE(rc))
160	return rc;
161
162	pVM->hwaccm.s.vmx.pRealModeTSS = (PVBOXTSS)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjRealModeTSS);
163	pVM->hwaccm.s.vmx.pRealModeTSSPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, 0);
164
165	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. Outside the TSS on purpose; the CPU will not check it
166	* for I/O operations. */
167	ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, PAGE_SIZE);
168	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
169	/* Bit set to 0 means redirection enabled. */
170	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
171
172	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
173	{
174	/* Allocate one page for the virtual APIC mmio cache. */
175	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.vmx.pMemObjAPIC, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
176	AssertRC(rc);
177	if (RT_FAILURE(rc))
178	return rc;
179
180	pVM->hwaccm.s.vmx.pAPIC = (uint8_t *)RTR0MemObjAddress(pVM->hwaccm.s.vmx.pMemObjAPIC);
181	pVM->hwaccm.s.vmx.pAPICPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.vmx.pMemObjAPIC, 0);
182	ASMMemZero32(pVM->hwaccm.s.vmx.pAPIC, PAGE_SIZE);
183	}
184	else
185	{
186	pVM->hwaccm.s.vmx.pMemObjAPIC = 0;
187	pVM->hwaccm.s.vmx.pAPIC = 0;
188	pVM->hwaccm.s.vmx.pAPICPhys = 0;
189	}
190
191	#ifdef LOG_ENABLED
192	SUPR0Printf("VMXR0InitVM %x VMCS=%x (%x) RealModeTSS=%x (%x)\n", pVM, pVM->hwaccm.s.vmx.pVMCS, (uint32_t)pVM->hwaccm.s.vmx.pVMCSPhys, pVM->hwaccm.s.vmx.pRealModeTSS, (uint32_t)pVM->hwaccm.s.vmx.pRealModeTSSPhys);
193	#endif
194	return VINF_SUCCESS;
195	}
196
197	/**
198	* Does Ring-0 per VM VT-x termination.
199	*
200	* @returns VBox status code.
201	* @param pVM The VM to operate on.
202	*/
203	HWACCMR0DECL(int) VMXR0TermVM(PVM pVM)
204	{
205	if (pVM->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
206	{
207	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjVMCS, false);
208	pVM->hwaccm.s.vmx.pMemObjVMCS = NIL_RTR0MEMOBJ;
209	pVM->hwaccm.s.vmx.pVMCS = 0;
210	pVM->hwaccm.s.vmx.pVMCSPhys = 0;
211	}
212	if (pVM->hwaccm.s.vmx.pMemObjRealModeTSS != NIL_RTR0MEMOBJ)
213	{
214	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjRealModeTSS, false);
215	pVM->hwaccm.s.vmx.pMemObjRealModeTSS = NIL_RTR0MEMOBJ;
216	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
217	pVM->hwaccm.s.vmx.pRealModeTSSPhys = 0;
218	}
219	if (pVM->hwaccm.s.vmx.pMemObjAPIC != NIL_RTR0MEMOBJ)
220	{
221	RTR0MemObjFree(pVM->hwaccm.s.vmx.pMemObjAPIC, false);
222	pVM->hwaccm.s.vmx.pMemObjAPIC = NIL_RTR0MEMOBJ;
223	pVM->hwaccm.s.vmx.pAPIC = 0;
224	pVM->hwaccm.s.vmx.pAPICPhys = 0;
225	}
226	return VINF_SUCCESS;
227	}
228
229	/**
230	* Sets up VT-x for the specified VM
231	*
232	* @returns VBox status code.
233	* @param pVM The VM to operate on.
234	*/
235	HWACCMR0DECL(int) VMXR0SetupVM(PVM pVM)
236	{
237	int rc = VINF_SUCCESS;
238	uint32_t val;
239
240	AssertReturn(pVM, VERR_INVALID_PARAMETER);
241	Assert(pVM->hwaccm.s.vmx.pVMCS);
242
243	/* Set revision dword at the beginning of the VMCS structure. */
244	(uint32_t )pVM->hwaccm.s.vmx.pVMCS = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info);
245
246	/* Clear VM Control Structure. */
247	Log(("pVMCSPhys = %VHp\n", pVM->hwaccm.s.vmx.pVMCSPhys));
248	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
249	if (VBOX_FAILURE(rc))
250	goto vmx_end;
251
252	/* Activate the VM Control Structure. */
253	rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
254	if (VBOX_FAILURE(rc))
255	goto vmx_end;
256
257	/* VMX_VMCS_CTRL_PIN_EXEC_CONTROLS
258	* Set required bits to one and zero according to the MSR capabilities.
259	*/
260	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
261	/* External and non-maskable interrupts cause VM-exits. */
262	val = val \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT \| VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT;
263	val &= pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
264
265	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, val);
266	AssertRC(rc);
267
268	/* VMX_VMCS_CTRL_PROC_EXEC_CONTROLS
269	* Set required bits to one and zero according to the MSR capabilities.
270	*/
271	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
272	/* Program which event cause VM-exits and which features we want to use. */
273	val = val \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT
274	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET
275	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT
276	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT
277	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT
278	\| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
279
280	/** @note VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT might cause a vmlaunch failure with an invalid control fields error. (combined with some other exit reasons) */
281
282	#if HC_ARCH_BITS == 64
283	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
284	{
285	/* CR8 reads from the APIC shadow page; writes cause an exit is they lower the TPR below the threshold */
286	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW;
287	Assert(pVM->hwaccm.s.vmx.pAPIC);
288	}
289	else
290	/* Exit on CR8 reads & writes in case the TPR shadow feature isn't present. */
291	val \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT \| VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT;
292	#endif
293	/* Mask away the bits that the CPU doesn't support */
294	/** @todo make sure they don't conflict with the above requirements. */
295	val &= pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
296	pVM->hwaccm.s.vmx.proc_ctls = val;
297
298	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, val);
299	AssertRC(rc);
300
301	/* VMX_VMCS_CTRL_CR3_TARGET_COUNT
302	* Set required bits to one and zero according to the MSR capabilities.
303	*/
304	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR3_TARGET_COUNT, 0);
305	AssertRC(rc);
306
307	/* VMX_VMCS_CTRL_EXIT_CONTROLS
308	* Set required bits to one and zero according to the MSR capabilities.
309	*/
310	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
311	#if HC_ARCH_BITS == 64
312	val \|= VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64;
313	#else
314	/* else Must be zero when AMD64 is not available. */
315	#endif
316	val &= pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
317	/* Don't acknowledge external interrupts on VM-exit. */
318	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, val);
319	AssertRC(rc);
320
321	/* Forward all exception except #NM & #PF to the guest.
322	* We always need to check pagefaults since our shadow page table can be out of sync.
323	* And we always lazily sync the FPU & XMM state.
324	*/
325
326	/*
327	* @todo Possible optimization:
328	* Keep the FPU and XMM state current in the EM thread. That way there's no need to
329	* lazily sync anything, but the downside is that we can't use the FPU stack or XMM
330	* registers ourselves of course.
331	*
332	* @note only possible if the current state is actually ours (X86_CR0_TS flag)
333	*/
334	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK);
335	AssertRC(rc);
336
337	/* Don't filter page faults; all of them should cause a switch. */
338	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MASK, 0);
339	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_PAGEFAULT_ERROR_MATCH, 0);
340	AssertRC(rc);
341
342	/* Init TSC offset to zero. */
343	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, 0);
344	#if HC_ARCH_BITS == 32
345	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, 0);
346	#endif
347	AssertRC(rc);
348
349	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_FULL, 0);
350	#if HC_ARCH_BITS == 32
351	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_A_HIGH, 0);
352	#endif
353	AssertRC(rc);
354
355	rc = VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_FULL, 0);
356	#if HC_ARCH_BITS == 32
357	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_IO_BITMAP_B_HIGH, 0);
358	#endif
359	AssertRC(rc);
360
361	/* Clear MSR controls. */
362	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
363	{
364	/* Optional */
365	rc = VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_FULL, 0);
366	#if HC_ARCH_BITS == 32
367	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_MSR_BITMAP_HIGH, 0);
368	#endif
369	AssertRC(rc);
370	}
371	rc = VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_FULL, 0);
372	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_FULL, 0);
373	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMENTRY_MSR_LOAD_FULL, 0);
374	#if HC_ARCH_BITS == 32
375	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_STORE_HIGH, 0);
376	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
377	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VMEXIT_MSR_LOAD_HIGH, 0);
378	#endif
379	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_STORE_COUNT, 0);
380	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_EXIT_MSR_LOAD_COUNT, 0);
381	AssertRC(rc);
382
383	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
384	{
385	Assert(pVM->hwaccm.s.vmx.pMemObjAPIC);
386	/* Optional */
387	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, 0);
388	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_FULL, pVM->hwaccm.s.vmx.pAPICPhys);
389	#if HC_ARCH_BITS == 32
390	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_VAPIC_PAGEADDR_HIGH, pVM->hwaccm.s.vmx.pAPICPhys >> 32);
391	#endif
392	AssertRC(rc);
393	}
394
395	/* Set link pointer to -1. Not currently used. */
396	#if HC_ARCH_BITS == 32
397	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFF);
398	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_HIGH, 0xFFFFFFFF);
399	#else
400	rc = VMXWriteVMCS(VMX_VMCS_GUEST_LINK_PTR_FULL, 0xFFFFFFFFFFFFFFFF);
401	#endif
402	AssertRC(rc);
403
404	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
405	rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
406	AssertRC(rc);
407
408	vmx_end:
409	VMXR0CheckError(pVM, rc);
410	return rc;
411	}
412
413
414	/**
415	* Injects an event (trap or external interrupt)
416	*
417	* @returns VBox status code.
418	* @param pVM The VM to operate on.
419	* @param pCtx CPU Context
420	* @param intInfo VMX interrupt info
421	* @param cbInstr Opcode length of faulting instruction
422	* @param errCode Error code (optional)
423	*/
424	static int VMXR0InjectEvent(PVM pVM, CPUMCTX *pCtx, uint32_t intInfo, uint32_t cbInstr, uint32_t errCode)
425	{
426	int rc;
427
428	#ifdef VBOX_STRICT
429	uint32_t iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
430	if (iGate == 0xE)
431	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->rip, errCode, pCtx->cr2, intInfo));
432	else
433	if (iGate < 0x20)
434	Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->rip, errCode));
435	else
436	{
437	Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->rip));
438	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
439	Assert(pCtx->eflags.u32 & X86_EFL_IF);
440	}
441	#endif
442
443	/* Set event injection state. */
444	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_IRQ_INFO,
445	intInfo \| (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT)
446	);
447
448	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
449	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE, errCode);
450
451	AssertRC(rc);
452	return rc;
453	}
454
455
456	/**
457	* Checks for pending guest interrupts and injects them
458	*
459	* @returns VBox status code.
460	* @param pVM The VM to operate on.
461	* @param pCtx CPU Context
462	*/
463	static int VMXR0CheckPendingInterrupt(PVM pVM, CPUMCTX *pCtx)
464	{
465	int rc;
466
467	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
468	if (pVM->hwaccm.s.Event.fPending)
469	{
470	Log(("Reinjecting event %VX64 %08x at %VGv cr2=%RX64\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip, pCtx->cr2));
471	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
472	rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
473	AssertRC(rc);
474
475	pVM->hwaccm.s.Event.fPending = false;
476	return VINF_SUCCESS;
477	}
478
479	/* When external interrupts are pending, we should exit the VM when IF is set. */
480	if ( !TRPMHasTrap(pVM)
481	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
482	{
483	if (!(pCtx->eflags.u32 & X86_EFL_IF))
484	{
485	Log2(("Enable irq window exit!\n"));
486	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
487	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
488	AssertRC(rc);
489	}
490	else
491	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
492	{
493	uint8_t u8Interrupt;
494
495	rc = PDMGetInterrupt(pVM, &u8Interrupt);
496	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
497	if (VBOX_SUCCESS(rc))
498	{
499	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
500	AssertRC(rc);
501	}
502	else
503	{
504	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
505	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
506	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
507	/* Just continue */
508	}
509	}
510	else
511	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
512	}
513
514	#ifdef VBOX_STRICT
515	if (TRPMHasTrap(pVM))
516	{
517	uint8_t u8Vector;
518	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
519	AssertRC(rc);
520	}
521	#endif
522
523	if ( pCtx->eflags.u32 & X86_EFL_IF
524	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
525	&& TRPMHasTrap(pVM)
526	)
527	{
528	uint8_t u8Vector;
529	int rc;
530	TRPMEVENT enmType;
531	RTGCUINTPTR intInfo;
532	RTGCUINT errCode;
533
534	/* If a new event is pending, then dispatch it now. */
535	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &errCode, 0);
536	AssertRC(rc);
537	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
538	Assert(enmType != TRPM_SOFTWARE_INT);
539
540	/* Clear the pending trap. */
541	rc = TRPMResetTrap(pVM);
542	AssertRC(rc);
543
544	intInfo = u8Vector;
545	intInfo \|= (1 << VMX_EXIT_INTERRUPTION_INFO_VALID_SHIFT);
546
547	if (enmType == TRPM_TRAP)
548	{
549	switch (u8Vector) {
550	case 8:
551	case 10:
552	case 11:
553	case 12:
554	case 13:
555	case 14:
556	case 17:
557	/* Valid error codes. */
558	intInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
559	break;
560	default:
561	break;
562	}
563	if (u8Vector == X86_XCPT_BP \|\| u8Vector == X86_XCPT_OF)
564	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
565	else
566	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
567	}
568	else
569	intInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
570
571	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
572	rc = VMXR0InjectEvent(pVM, pCtx, intInfo, 0, errCode);
573	AssertRC(rc);
574	} /* if (interrupts can be dispatched) */
575
576	return VINF_SUCCESS;
577	}
578
579	/**
580	* Save the host state
581	*
582	* @returns VBox status code.
583	* @param pVM The VM to operate on.
584	*/
585	HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
586	{
587	int rc = VINF_SUCCESS;
588
589	/*
590	* Host CPU Context
591	*/
592	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_HOST_CONTEXT)
593	{
594	RTIDTR idtr;
595	RTGDTR gdtr;
596	RTSEL SelTR;
597	PX86DESCHC pDesc;
598	uintptr_t trBase;
599
600	/* Control registers */
601	rc = VMXWriteVMCS(VMX_VMCS_HOST_CR0, ASMGetCR0());
602	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR3, ASMGetCR3());
603	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_CR4, ASMGetCR4());
604	AssertRC(rc);
605	Log2(("VMX_VMCS_HOST_CR0 %08x\n", ASMGetCR0()));
606	Log2(("VMX_VMCS_HOST_CR3 %VHp\n", ASMGetCR3()));
607	Log2(("VMX_VMCS_HOST_CR4 %08x\n", ASMGetCR4()));
608
609	/* Selector registers. */
610	rc = VMXWriteVMCS(VMX_VMCS_HOST_FIELD_CS, ASMGetCS());
611	/** @note VMX is (again) very picky about the RPL of the selectors here; we'll restore them manually. */
612	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_DS, 0);
613	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_ES, 0);
614	#if HC_ARCH_BITS == 32
615	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_FS, 0);
616	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_GS, 0);
617	#endif
618	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_SS, ASMGetSS());
619	SelTR = ASMGetTR();
620	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_FIELD_TR, SelTR);
621	AssertRC(rc);
622	Log2(("VMX_VMCS_HOST_FIELD_CS %08x\n", ASMGetCS()));
623	Log2(("VMX_VMCS_HOST_FIELD_DS %08x\n", ASMGetDS()));
624	Log2(("VMX_VMCS_HOST_FIELD_ES %08x\n", ASMGetES()));
625	Log2(("VMX_VMCS_HOST_FIELD_FS %08x\n", ASMGetFS()));
626	Log2(("VMX_VMCS_HOST_FIELD_GS %08x\n", ASMGetGS()));
627	Log2(("VMX_VMCS_HOST_FIELD_SS %08x\n", ASMGetSS()));
628	Log2(("VMX_VMCS_HOST_FIELD_TR %08x\n", ASMGetTR()));
629
630	/* GDTR & IDTR */
631	ASMGetGDTR(&gdtr);
632	rc = VMXWriteVMCS(VMX_VMCS_HOST_GDTR_BASE, gdtr.pGdt);
633	ASMGetIDTR(&idtr);
634	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_IDTR_BASE, idtr.pIdt);
635	AssertRC(rc);
636	Log2(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", gdtr.pGdt));
637	Log2(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", idtr.pIdt));
638
639	/* Save the base address of the TR selector. */
640	if (SelTR > gdtr.cbGdt)
641	{
642	AssertMsgFailed(("Invalid TR selector %x. GDTR.cbGdt=%x\n", SelTR, gdtr.cbGdt));
643	return VERR_VMX_INVALID_HOST_STATE;
644	}
645
646	pDesc = &((PX86DESCHC)gdtr.pGdt)[SelTR >> X86_SEL_SHIFT_HC];
647	#if HC_ARCH_BITS == 64
648	trBase = X86DESC64_BASE(*pDesc);
649	#else
650	trBase = X86DESC_BASE(*pDesc);
651	#endif
652	rc = VMXWriteVMCS(VMX_VMCS_HOST_TR_BASE, trBase);
653	AssertRC(rc);
654	Log2(("VMX_VMCS_HOST_TR_BASE %VHv\n", trBase));
655
656	/* FS and GS base. */
657	#if HC_ARCH_BITS == 64
658	Log2(("MSR_K8_FS_BASE = %VHv\n", ASMRdMsr(MSR_K8_FS_BASE)));
659	Log2(("MSR_K8_GS_BASE = %VHv\n", ASMRdMsr(MSR_K8_GS_BASE)));
660	rc = VMXWriteVMCS64(VMX_VMCS_HOST_FS_BASE, ASMRdMsr(MSR_K8_FS_BASE));
661	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_GS_BASE, ASMRdMsr(MSR_K8_GS_BASE));
662	#endif
663	AssertRC(rc);
664
665	/* Sysenter MSRs. */
666	/** @todo expensive!! */
667	rc = VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
668	Log2(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_CS)));
669	#if HC_ARCH_BITS == 32
670	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
671	rc \|= VMXWriteVMCS(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
672	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP)));
673	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP)));
674	#else
675	Log2(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_EIP)));
676	Log2(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", ASMRdMsr(MSR_IA32_SYSENTER_ESP)));
677	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
678	rc \|= VMXWriteVMCS64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
679	#endif
680	AssertRC(rc);
681
682	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_HOST_CONTEXT;
683	}
684	return rc;
685	}
686
687
688	/**
689	* Loads the guest state
690	*
691	* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
692	*
693	* @returns VBox status code.
694	* @param pVM The VM to operate on.
695	* @param pCtx Guest context
696	*/
697	HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
698	{
699	int rc = VINF_SUCCESS;
700	RTGCUINTPTR val;
701	X86EFLAGS eflags;
702
703	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
704	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
705	{
706	VMX_WRITE_SELREG(ES, es);
707	AssertRC(rc);
708
709	VMX_WRITE_SELREG(CS, cs);
710	AssertRC(rc);
711
712	VMX_WRITE_SELREG(SS, ss);
713	AssertRC(rc);
714
715	VMX_WRITE_SELREG(DS, ds);
716	AssertRC(rc);
717
718	/* The base values in the hidden fs & gs registers are not in sync with the msrs; they are cut to 32 bits. */
719	VMX_WRITE_SELREG(FS, fs);
720	AssertRC(rc);
721
722	VMX_WRITE_SELREG(GS, gs);
723	AssertRC(rc);
724	}
725
726	/* Guest CPU context: LDTR. */
727	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
728	{
729	if (pCtx->ldtr == 0)
730	{
731	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, 0);
732	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, 0);
733	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, 0);
734	/** @note vmlaunch will fail with 0 or just 0x02. No idea why. */
735	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x82 /* present, LDT */);
736	}
737	else
738	{
739	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_LDTR, pCtx->ldtr);
740	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_LIMIT, pCtx->ldtrHid.u32Limit);
741	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtrHid.u64Base);
742	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_LDTR_ACCESS_RIGHTS, pCtx->ldtrHid.Attr.u);
743	}
744	AssertRC(rc);
745	}
746	/* Guest CPU context: TR. */
747	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
748	{
749	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FIELD_TR, pCtx->tr);
750
751	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
752	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
753	{
754	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
755	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, 0);
756	}
757	else
758	{
759	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_LIMIT, pCtx->trHid.u32Limit);
760	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_BASE, pCtx->trHid.u64Base);
761	}
762	val = pCtx->trHid.Attr.u;
763
764	/* The TSS selector must be busy. */
765	if ((val & 0xF) == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
766	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_286_TSS_BUSY;
767	else
768	/* Default even if no TR selector has been set (otherwise vmlaunch will fail!) */
769	val = (val & ~0xF) \| X86_SEL_TYPE_SYS_386_TSS_BUSY;
770
771	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_TR_ACCESS_RIGHTS, val);
772	AssertRC(rc);
773	}
774	/* Guest CPU context: GDTR. */
775	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
776	{
777	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
778	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
779	AssertRC(rc);
780	}
781	/* Guest CPU context: IDTR. */
782	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
783	{
784	rc = VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
785	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
786	AssertRC(rc);
787	}
788
789	/*
790	* Sysenter MSRs (unconditional)
791	*/
792	rc = VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
793	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
794	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
795	AssertRC(rc);
796
797	/* Control registers */
798	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
799	{
800	val = pCtx->cr0;
801	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, val);
802	Log2(("Guest CR0-shadow %08x\n", val));
803	if (CPUMIsGuestFPUStateActive(pVM) == false)
804	{
805	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
806	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
807	}
808	else
809	{
810	/** @todo check if we support the old style mess correctly. */
811	if (!(val & X86_CR0_NE))
812	{
813	Log(("Forcing X86_CR0_NE!!!\n"));
814
815	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
816	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
817	{
818	rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, HWACCM_VMX_TRAP_MASK \| RT_BIT(X86_XCPT_MF));
819	AssertRC(rc);
820	pVM->hwaccm.s.fFPUOldStyleOverride = true;
821	}
822	}
823
824	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
825	}
826	/* Note: protected mode & paging are always enabled; we use them for emulating real and protected mode without paging too. */
827	val \|= X86_CR0_PE \| X86_CR0_PG;
828	/* Note: We must also set this as we rely on protecting various pages for which supervisor writes must be caught. */
829	val \|= X86_CR0_WP;
830
831	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR0, val);
832	Log2(("Guest CR0 %08x\n", val));
833	/* CR0 flags owned by the host; if the guests attempts to change them, then
834	* the VM will exit.
835	*/
836	val = X86_CR0_PE /* Must monitor this bit (assumptions are made for real mode emulation) */
837	\| X86_CR0_WP /* Must monitor this bit (it must always be enabled). */
838	\| X86_CR0_PG /* Must monitor this bit (assumptions are made for real mode & protected mode without paging emulation) */
839	\| X86_CR0_TS
840	\| X86_CR0_ET
841	\| X86_CR0_NE
842	\| X86_CR0_MP;
843	pVM->hwaccm.s.vmx.cr0_mask = val;
844
845	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR0_MASK, val);
846	Log2(("Guest CR0-mask %08x\n", val));
847	AssertRC(rc);
848	}
849	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
850	{
851	/* CR4 */
852	rc = VMXWriteVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, pCtx->cr4);
853	Log2(("Guest CR4-shadow %08x\n", pCtx->cr4));
854	/* Set the required bits in cr4 too (currently X86_CR4_VMXE). */
855	val = pCtx->cr4 \| (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
856	switch(pVM->hwaccm.s.enmShadowMode)
857	{
858	case PGMMODE_REAL: /* Real mode -> emulated using v86 mode */
859	case PGMMODE_PROTECTED: /* Protected mode, no paging -> emulated using identity mapping. */
860	case PGMMODE_32_BIT: /* 32-bit paging. */
861	break;
862
863	case PGMMODE_PAE: /* PAE paging. */
864	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
865	/** @todo use normal 32 bits paging */
866	val \|= X86_CR4_PAE;
867	break;
868
869	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
870	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
871	#ifdef VBOX_ENABLE_64_BITS_GUESTS
872	break;
873	#else
874	AssertFailed();
875	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
876	#endif
877	default: /* shut up gcc */
878	AssertFailed();
879	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
880	}
881	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
882	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
883	val \|= X86_CR4_VME;
884
885	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_CR4, val);
886	Log2(("Guest CR4 %08x\n", val));
887	/* CR4 flags owned by the host; if the guests attempts to change them, then
888	* the VM will exit.
889	*/
890	val = X86_CR4_PAE
891	\| X86_CR4_PGE
892	\| X86_CR4_PSE
893	\| X86_CR4_VMXE;
894	pVM->hwaccm.s.vmx.cr4_mask = val;
895
896	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_CR4_MASK, val);
897	Log2(("Guest CR4-mask %08x\n", val));
898	AssertRC(rc);
899	}
900
901	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
902	{
903	/* Save our shadow CR3 register. */
904	val = PGMGetHyperCR3(pVM);
905	Assert(val);
906	rc = VMXWriteVMCS(VMX_VMCS_GUEST_CR3, val);
907	AssertRC(rc);
908	}
909
910	/* Debug registers. */
911	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
912	{
913	val = pCtx->dr7 & 0xffffffff; /* upper 32 bits reserved */
914	val &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
915	val \|= 0x400; /* must be one */
916	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DR7, val);
917	AssertRC(rc);
918
919	/* IA32_DEBUGCTL MSR. */
920	rc = VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_FULL, 0);
921	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUGCTL_HIGH, 0);
922	AssertRC(rc);
923
924	/** @todo do we really ever need this? */
925	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_DEBUG_EXCEPTIONS, 0);
926	AssertRC(rc);
927	}
928
929	/* EIP, ESP and EFLAGS */
930	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RIP, pCtx->rip);
931	rc \|= VMXWriteVMCS(VMX_VMCS_GUEST_RSP, pCtx->rsp);
932	AssertRC(rc);
933
934	/* Bits 22-31, 15, 5 & 3 must be zero. Bit 1 must be 1. */
935	eflags = pCtx->eflags;
936	eflags.u32 &= VMX_EFLAGS_RESERVED_0;
937	eflags.u32 \|= VMX_EFLAGS_RESERVED_1;
938
939	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
940	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
941	{
942	eflags.Bits.u1VM = 1;
943	eflags.Bits.u1VIF = pCtx->eflags.Bits.u1IF;
944	eflags.Bits.u2IOPL = 3;
945	}
946
947	rc = VMXWriteVMCS(VMX_VMCS_GUEST_RFLAGS, eflags.u32);
948	AssertRC(rc);
949
950	/** TSC offset. */
951	uint64_t u64TSCOffset;
952
953	if (TMCpuTickCanUseRealTSC(pVM, &u64TSCOffset))
954	{
955	/* Note: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT takes precedence over TSC_OFFSET */
956	#if HC_ARCH_BITS == 64
957	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, u64TSCOffset);
958	#else
959	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_FULL, (uint32_t)u64TSCOffset);
960	rc \|= VMXWriteVMCS(VMX_VMCS_CTRL_TSC_OFFSET_HIGH, (uint32_t)(u64TSCOffset >> 32ULL));
961	#endif
962	AssertRC(rc);
963
964	pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
965	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
966	AssertRC(rc);
967	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
968	}
969	else
970	{
971	pVM->hwaccm.s.vmx.proc_ctls \|= VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT;
972	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
973	AssertRC(rc);
974	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
975	}
976
977	/* VMX_VMCS_CTRL_ENTRY_CONTROLS
978	* Set required bits to one and zero according to the MSR capabilities.
979	*/
980	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
981	/* 64 bits guest mode? */
982	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
983	val \|= VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE;
984	/* else Must be zero when AMD64 is not available. */
985
986	/* Mask away the bits that the CPU doesn't support */
987	val &= pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
988	rc = VMXWriteVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, val);
989	AssertRC(rc);
990
991	/* 64 bits guest mode? */
992	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
993	{
994	#if !defined(VBOX_WITH_64_BITS_GUESTS) \|\| HC_ARCH_BITS != 64
995	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
996	#else
997	pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM64;
998	#endif
999	/* Unconditionally update these as wrmsr might have changed them. */
1000	rc = VMXWriteVMCS(VMX_VMCS_GUEST_FS_BASE, pCtx->fsHid.u64Base);
1001	AssertRC(rc);
1002	rc = VMXWriteVMCS(VMX_VMCS_GUEST_GS_BASE, pCtx->gsHid.u64Base);
1003	AssertRC(rc);
1004	}
1005	else
1006	{
1007	pVM->hwaccm.s.vmx.pfnStartVM = VMXR0StartVM32;
1008	}
1009
1010	/* Done. */
1011	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
1012
1013	return rc;
1014	}
1015
1016	/**
1017	* Runs guest code in a VT-x VM.
1018	*
1019	* @returns VBox status code.
1020	* @param pVM The VM to operate on.
1021	* @param pCtx Guest context
1022	*/
1023	HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
1024	{
1025	int rc = VINF_SUCCESS;
1026	RTCCUINTREG val, valShadow;
1027	RTCCUINTREG exitReason, instrError, cbInstr;
1028	RTGCUINTPTR exitQualification;
1029	RTGCUINTPTR intInfo = 0; /* shut up buggy gcc 4 */
1030	RTGCUINTPTR errCode, instrInfo, uInterruptState;
1031	bool fGuestStateSynced = false;
1032	bool fSyncTPR = false;
1033	unsigned cResume = 0;
1034	#ifdef VBOX_STRICT
1035	RTCPUID idCpuCheck;
1036	#endif
1037
1038	Log2(("\nE"));
1039
1040	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
1041
1042	#ifdef VBOX_STRICT
1043	rc = VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1044	AssertRC(rc);
1045	Log2(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS = %08x\n", val));
1046
1047	/* allowed zero */
1048	if ((val & pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0)
1049	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: zero\n"));
1050
1051	/* allowed one */
1052	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1) != 0)
1053	Log(("Invalid VMX_VMCS_CTRL_PIN_EXEC_CONTROLS: one\n"));
1054
1055	rc = VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1056	AssertRC(rc);
1057	Log2(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS = %08x\n", val));
1058
1059	/* allowed zero */
1060	if ((val & pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0)
1061	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: zero\n"));
1062
1063	/* allowed one */
1064	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1) != 0)
1065	Log(("Invalid VMX_VMCS_CTRL_PROC_EXEC_CONTROLS: one\n"));
1066
1067	rc = VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1068	AssertRC(rc);
1069	Log2(("VMX_VMCS_CTRL_ENTRY_CONTROLS = %08x\n", val));
1070
1071	/* allowed zero */
1072	if ((val & pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0)
1073	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: zero\n"));
1074
1075	/* allowed one */
1076	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1) != 0)
1077	Log(("Invalid VMX_VMCS_CTRL_ENTRY_CONTROLS: one\n"));
1078
1079	rc = VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1080	AssertRC(rc);
1081	Log2(("VMX_VMCS_CTRL_EXIT_CONTROLS = %08x\n", val));
1082
1083	/* allowed zero */
1084	if ((val & pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0) != pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0)
1085	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: zero\n"));
1086
1087	/* allowed one */
1088	if ((val & ~pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1) != 0)
1089	Log(("Invalid VMX_VMCS_CTRL_EXIT_CONTROLS: one\n"));
1090	#endif
1091
1092	#if 0
1093	/*
1094	* Check if debug registers are armed.
1095	*/
1096	uint32_t u32DR7 = ASMGetDR7();
1097	if (u32DR7 & X86_DR7_ENABLED_MASK)
1098	{
1099	pVM->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
1100	}
1101	else
1102	pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HOST;
1103	#endif
1104
1105	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1106	*/
1107	ResumeExecution:
1108	/* Safety precaution; looping for too long here can have a very bad effect on the host */
1109	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
1110	{
1111	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
1112	rc = VINF_EM_RAW_INTERRUPT;
1113	goto end;
1114	}
1115
1116	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
1117	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
1118	{
1119	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
1120	if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
1121	{
1122	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1123	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1124	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1125	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
1126	*/
1127	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1128	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
1129	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1130	AssertRC(rc);
1131	}
1132	}
1133	else
1134	{
1135	/* Irq inhibition is no longer active; clear the corresponding VMX state. */
1136	rc = VMXWriteVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, 0);
1137	AssertRC(rc);
1138	}
1139
1140	/* Check for pending actions that force us to go back to ring 3. */
1141	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
1142	{
1143	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
1144	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
1145	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1146	rc = VINF_EM_RAW_TO_R3;
1147	goto end;
1148	}
1149	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1150	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
1151	{
1152	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1153	rc = VINF_EM_PENDING_REQUEST;
1154	goto end;
1155	}
1156
1157	/* When external interrupts are pending, we should exit the VM when IF is set. */
1158	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
1159	rc = VMXR0CheckPendingInterrupt(pVM, pCtx);
1160	if (VBOX_FAILURE(rc))
1161	{
1162	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1163	goto end;
1164	}
1165
1166	/** @todo check timers?? */
1167
1168	/* TPR caching using CR8 is only available in 64 bits mode */
1169	/* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
1170	/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!! */
1171	/*
1172	* @todo reduce overhead
1173	*/
1174	if ( (pCtx->msrEFER & MSR_K6_EFER_LMA)
1175	&& pVM->hwaccm.s.vmx.pAPIC)
1176	{
1177	/* TPR caching in CR8 */
1178	uint8_t u8TPR;
1179	bool fPending;
1180
1181	int rc = PDMApicGetTPR(pVM, &u8TPR, &fPending);
1182	AssertRC(rc);
1183	/* The TPR can be found at offset 0x80 in the APIC mmio page. */
1184	pVM->hwaccm.s.vmx.pAPIC[0x80] = u8TPR << 4; /* bits 7-4 contain the task priority */
1185
1186	/* Two options here:
1187	* - external interrupt pending, but masked by the TPR value.
1188	* -> CR8 updates that lower the TPR value to below the current value should cause an exit
1189	* - no pending interrupts
1190	* -> We don't need to be explicitely notified. There are enough world switches for detecting pending interrupts.
1191	*/
1192	rc = VMXWriteVMCS(VMX_VMCS_CTRL_TPR_THRESHOLD, (fPending) ? u8TPR : 0);
1193	AssertRC(rc);
1194
1195	fSyncTPR = !fPending;
1196	}
1197
1198	/*
1199	* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1200	* (until the actual world switch)
1201	*/
1202	#ifdef VBOX_STRICT
1203	idCpuCheck = RTMpCpuId();
1204	#endif
1205	/* Save the host state first. */
1206	rc = VMXR0SaveHostState(pVM);
1207	if (rc != VINF_SUCCESS)
1208	{
1209	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1210	goto end;
1211	}
1212	/* Load the guest state */
1213	rc = VMXR0LoadGuestState(pVM, pCtx);
1214	if (rc != VINF_SUCCESS)
1215	{
1216	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1217	goto end;
1218	}
1219	fGuestStateSynced = true;
1220
1221	/* Non-register state Guest Context */
1222	/** @todo change me according to cpu state */
1223	rc = VMXWriteVMCS(VMX_VMCS_GUEST_ACTIVITY_STATE, VMX_CMS_GUEST_ACTIVITY_ACTIVE);
1224	AssertRC(rc);
1225
1226	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
1227
1228	/* Manual save and restore:
1229	* - General purpose registers except RIP, RSP
1230	*
1231	* Trashed:
1232	* - CR2 (we don't care)
1233	* - LDTR (reset to 0)
1234	* - DRx (presumably not changed at all)
1235	* - DR7 (reset to 0x400)
1236	* - EFLAGS (reset to RT_BIT(1); not relevant)
1237	*
1238	*/
1239
1240	/* All done! Let's start VM execution. */
1241	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
1242	#ifdef VBOX_STRICT
1243	Assert(idCpuCheck == RTMpCpuId());
1244	#endif
1245	rc = pVM->hwaccm.s.vmx.pfnStartVM(pVM->hwaccm.s.vmx.fResumeVM, pCtx);
1246
1247	/* In case we execute a goto ResumeExecution later on. */
1248	pVM->hwaccm.s.vmx.fResumeVM = true;
1249
1250	/**
1251	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1252	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1253	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1254	*/
1255
1256	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1257	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1258
1259	switch (rc)
1260	{
1261	case VINF_SUCCESS:
1262	break;
1263
1264	case VERR_VMX_INVALID_VMXON_PTR:
1265	AssertFailed();
1266	goto end;
1267
1268	case VERR_VMX_UNABLE_TO_START_VM:
1269	case VERR_VMX_UNABLE_TO_RESUME_VM:
1270	{
1271	#ifdef VBOX_STRICT
1272	int rc1;
1273
1274	rc1 = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1275	rc1 \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1276	AssertRC(rc1);
1277	if (rc1 == VINF_SUCCESS)
1278	{
1279	RTGDTR gdtr;
1280	PX86DESCHC pDesc;
1281
1282	ASMGetGDTR(&gdtr);
1283
1284	Log(("Unable to start/resume VM for reason: %x. Instruction error %x\n", (uint32_t)exitReason, (uint32_t)instrError));
1285	Log(("Current stack %08x\n", &rc1));
1286
1287
1288	VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1289	Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
1290	VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
1291	Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS %08x\n", val));
1292	VMXReadVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, &val);
1293	Log(("VMX_VMCS_CTRL_PROC_EXEC_CONTROLS %08x\n", val));
1294	VMXReadVMCS(VMX_VMCS_CTRL_ENTRY_CONTROLS, &val);
1295	Log(("VMX_VMCS_CTRL_ENTRY_CONTROLS %08x\n", val));
1296	VMXReadVMCS(VMX_VMCS_CTRL_EXIT_CONTROLS, &val);
1297	Log(("VMX_VMCS_CTRL_EXIT_CONTROLS %08x\n", val));
1298
1299	VMXReadVMCS(VMX_VMCS_HOST_CR0, &val);
1300	Log(("VMX_VMCS_HOST_CR0 %08x\n", val));
1301
1302	VMXReadVMCS(VMX_VMCS_HOST_CR3, &val);
1303	Log(("VMX_VMCS_HOST_CR3 %VHp\n", val));
1304
1305	VMXReadVMCS(VMX_VMCS_HOST_CR4, &val);
1306	Log(("VMX_VMCS_HOST_CR4 %08x\n", val));
1307
1308	VMXReadVMCS(VMX_VMCS_HOST_FIELD_CS, &val);
1309	Log(("VMX_VMCS_HOST_FIELD_CS %08x\n", val));
1310	if (val < gdtr.cbGdt)
1311	{
1312	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1313	HWACCMR0DumpDescriptor(pDesc, val, "CS: ");
1314	}
1315
1316	VMXReadVMCS(VMX_VMCS_HOST_FIELD_DS, &val);
1317	Log(("VMX_VMCS_HOST_FIELD_DS %08x\n", val));
1318	if (val < gdtr.cbGdt)
1319	{
1320	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1321	HWACCMR0DumpDescriptor(pDesc, val, "DS: ");
1322	}
1323
1324	VMXReadVMCS(VMX_VMCS_HOST_FIELD_ES, &val);
1325	Log(("VMX_VMCS_HOST_FIELD_ES %08x\n", val));
1326	if (val < gdtr.cbGdt)
1327	{
1328	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1329	HWACCMR0DumpDescriptor(pDesc, val, "ES: ");
1330	}
1331
1332	VMXReadVMCS(VMX_VMCS_HOST_FIELD_FS, &val);
1333	Log(("VMX_VMCS_HOST_FIELD_FS %08x\n", val));
1334	if (val < gdtr.cbGdt)
1335	{
1336	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1337	HWACCMR0DumpDescriptor(pDesc, val, "FS: ");
1338	}
1339
1340	VMXReadVMCS(VMX_VMCS_HOST_FIELD_GS, &val);
1341	Log(("VMX_VMCS_HOST_FIELD_GS %08x\n", val));
1342	if (val < gdtr.cbGdt)
1343	{
1344	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1345	HWACCMR0DumpDescriptor(pDesc, val, "GS: ");
1346	}
1347
1348	VMXReadVMCS(VMX_VMCS_HOST_FIELD_SS, &val);
1349	Log(("VMX_VMCS_HOST_FIELD_SS %08x\n", val));
1350	if (val < gdtr.cbGdt)
1351	{
1352	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1353	HWACCMR0DumpDescriptor(pDesc, val, "SS: ");
1354	}
1355
1356	VMXReadVMCS(VMX_VMCS_HOST_FIELD_TR, &val);
1357	Log(("VMX_VMCS_HOST_FIELD_TR %08x\n", val));
1358	if (val < gdtr.cbGdt)
1359	{
1360	pDesc = &((PX86DESCHC)gdtr.pGdt)[val >> X86_SEL_SHIFT_HC];
1361	HWACCMR0DumpDescriptor(pDesc, val, "TR: ");
1362	}
1363
1364	VMXReadVMCS(VMX_VMCS_HOST_TR_BASE, &val);
1365	Log(("VMX_VMCS_HOST_TR_BASE %VHv\n", val));
1366
1367	VMXReadVMCS(VMX_VMCS_HOST_GDTR_BASE, &val);
1368	Log(("VMX_VMCS_HOST_GDTR_BASE %VHv\n", val));
1369	VMXReadVMCS(VMX_VMCS_HOST_IDTR_BASE, &val);
1370	Log(("VMX_VMCS_HOST_IDTR_BASE %VHv\n", val));
1371
1372	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_CS, &val);
1373	Log(("VMX_VMCS_HOST_SYSENTER_CS %08x\n", val));
1374
1375	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_EIP, &val);
1376	Log(("VMX_VMCS_HOST_SYSENTER_EIP %VHv\n", val));
1377
1378	VMXReadVMCS(VMX_VMCS_HOST_SYSENTER_ESP, &val);
1379	Log(("VMX_VMCS_HOST_SYSENTER_ESP %VHv\n", val));
1380
1381	VMXReadVMCS(VMX_VMCS_HOST_RSP, &val);
1382	Log(("VMX_VMCS_HOST_RSP %VHv\n", val));
1383	VMXReadVMCS(VMX_VMCS_HOST_RIP, &val);
1384	Log(("VMX_VMCS_HOST_RIP %VHv\n", val));
1385
1386	#if HC_ARCH_BITS == 64
1387	Log(("MSR_K6_EFER = %VX64\n", ASMRdMsr(MSR_K6_EFER)));
1388	Log(("MSR_K6_STAR = %VX64\n", ASMRdMsr(MSR_K6_STAR)));
1389	Log(("MSR_K8_LSTAR = %VX64\n", ASMRdMsr(MSR_K8_LSTAR)));
1390	Log(("MSR_K8_CSTAR = %VX64\n", ASMRdMsr(MSR_K8_CSTAR)));
1391	Log(("MSR_K8_SF_MASK = %VX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
1392	#endif
1393	}
1394	#endif /* VBOX_STRICT */
1395	goto end;
1396	}
1397
1398	default:
1399	/* impossible */
1400	AssertFailed();
1401	goto end;
1402	}
1403	/* Success. Query the guest state and figure out what has happened. */
1404
1405	/* Investigate why there was a VM-exit. */
1406	rc = VMXReadVMCS(VMX_VMCS_RO_EXIT_REASON, &exitReason);
1407	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitReason & MASK_EXITREASON_STAT]);
1408
1409	exitReason &= 0xffff; /* bit 0-15 contain the exit code. */
1410	rc \|= VMXReadVMCS(VMX_VMCS_RO_VM_INSTR_ERROR, &instrError);
1411	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_LENGTH, &cbInstr);
1412	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_INFO, &val);
1413	intInfo = val;
1414	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INTERRUPTION_ERRCODE, &val);
1415	errCode = val; /* might not be valid; depends on VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID. */
1416	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_INSTR_INFO, &val);
1417	instrInfo = val;
1418	rc \|= VMXReadVMCS(VMX_VMCS_RO_EXIT_QUALIFICATION, &val);
1419	exitQualification = val;
1420	AssertRC(rc);
1421
1422	/* Let's first sync back eip, esp, and eflags. */
1423	rc = VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
1424	AssertRC(rc);
1425	pCtx->rip = val;
1426	rc = VMXReadVMCS(VMX_VMCS_GUEST_RSP, &val);
1427	AssertRC(rc);
1428	pCtx->rsp = val;
1429	rc = VMXReadVMCS(VMX_VMCS_GUEST_RFLAGS, &val);
1430	AssertRC(rc);
1431	pCtx->eflags.u32 = val;
1432
1433	/* Take care of instruction fusing (sti, mov ss) */
1434	rc \|= VMXReadVMCS(VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE, &val);
1435	uInterruptState = val;
1436	if (uInterruptState != 0)
1437	{
1438	Assert(uInterruptState <= 2); /* only sti & mov ss */
1439	Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->rip));
1440	EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1441	}
1442	else
1443	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1444
1445	/* Real mode emulation using v86 mode with CR4.VME (interrupt redirection using the int bitmap in the TSS) */
1446	if (!(pCtx->cr0 & X86_CR0_PROTECTION_ENABLE))
1447	{
1448	/* Hide our emulation flags */
1449	pCtx->eflags.Bits.u1VM = 0;
1450	pCtx->eflags.Bits.u1IF = pCtx->eflags.Bits.u1VIF;
1451	pCtx->eflags.Bits.u1VIF = 0;
1452	pCtx->eflags.Bits.u2IOPL = 0;
1453	}
1454
1455	/* Control registers. */
1456	VMXReadVMCS(VMX_VMCS_CTRL_CR0_READ_SHADOW, &valShadow);
1457	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
1458	val = (valShadow & pVM->hwaccm.s.vmx.cr0_mask) \| (val & ~pVM->hwaccm.s.vmx.cr0_mask);
1459	CPUMSetGuestCR0(pVM, val);
1460
1461	VMXReadVMCS(VMX_VMCS_CTRL_CR4_READ_SHADOW, &valShadow);
1462	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
1463	val = (valShadow & pVM->hwaccm.s.vmx.cr4_mask) \| (val & ~pVM->hwaccm.s.vmx.cr4_mask);
1464	CPUMSetGuestCR4(pVM, val);
1465
1466	CPUMSetGuestCR2(pVM, ASMGetCR2());
1467
1468	VMXReadVMCS(VMX_VMCS_GUEST_DR7, &val);
1469	CPUMSetGuestDR7(pVM, val);
1470
1471	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1472	VMX_READ_SELREG(ES, es);
1473	VMX_READ_SELREG(SS, ss);
1474	VMX_READ_SELREG(CS, cs);
1475	VMX_READ_SELREG(DS, ds);
1476	VMX_READ_SELREG(FS, fs);
1477	VMX_READ_SELREG(GS, gs);
1478
1479	/*
1480	* System MSRs
1481	*/
1482	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_CS, &val);
1483	pCtx->SysEnter.cs = val;
1484	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_EIP, &val);
1485	pCtx->SysEnter.eip = val;
1486	VMXReadVMCS(VMX_VMCS_GUEST_SYSENTER_ESP, &val);
1487	pCtx->SysEnter.esp = val;
1488
1489	/** @note NOW IT'S SAFE FOR LOGGING! */
1490	Log2(("Raw exit reason %08x\n", exitReason));
1491
1492	/* Check if an injected event was interrupted prematurely. */
1493	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_INFO, &val);
1494	AssertRC(rc);
1495	pVM->hwaccm.s.Event.intInfo = VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(val);
1496	if ( VMX_EXIT_INTERRUPTION_INFO_VALID(pVM->hwaccm.s.Event.intInfo)
1497	&& VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
1498	{
1499	pVM->hwaccm.s.Event.fPending = true;
1500	/* Error code present? */
1501	if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVM->hwaccm.s.Event.intInfo))
1502	{
1503	rc = VMXReadVMCS(VMX_VMCS_RO_IDT_ERRCODE, &val);
1504	AssertRC(rc);
1505	pVM->hwaccm.s.Event.errCode = val;
1506	Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x pending error=%RX64\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification, val));
1507	}
1508	else
1509	{
1510	Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification));
1511	pVM->hwaccm.s.Event.errCode = 0;
1512	}
1513	}
1514
1515	#ifdef VBOX_STRICT
1516	if (exitReason == VMX_EXIT_ERR_INVALID_GUEST_STATE)
1517	HWACCMDumpRegs(pVM, pCtx);
1518	#endif
1519
1520	Log2(("E%d", exitReason));
1521	Log2(("Exit reason %d, exitQualification %08x\n", exitReason, exitQualification));
1522	Log2(("instrInfo=%d instrError=%d instr length=%d\n", instrInfo, instrError, cbInstr));
1523	Log2(("Interruption error code %d\n", errCode));
1524	Log2(("IntInfo = %08x\n", intInfo));
1525	Log2(("New EIP=%VGv\n", pCtx->rip));
1526
1527	if (fSyncTPR)
1528	{
1529	rc = PDMApicSetTPR(pVM, pVM->hwaccm.s.vmx.pAPIC[0x80] >> 4);
1530	AssertRC(rc);
1531	}
1532
1533	/* Some cases don't need a complete resync of the guest CPU state; handle them here. */
1534	switch (exitReason)
1535	{
1536	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
1537	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
1538	{
1539	uint32_t vector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
1540
1541	if (!VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
1542	{
1543	Assert(exitReason == VMX_EXIT_EXTERNAL_IRQ);
1544	/* External interrupt; leave to allow it to be dispatched again. */
1545	rc = VINF_EM_RAW_INTERRUPT;
1546	break;
1547	}
1548	switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(intInfo))
1549	{
1550	case VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI: /* Non-maskable interrupt. */
1551	/* External interrupt; leave to allow it to be dispatched again. */
1552	rc = VINF_EM_RAW_INTERRUPT;
1553	break;
1554
1555	case VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT: /* External hardware interrupt. */
1556	AssertFailed(); /* can't come here; fails the first check. */
1557	break;
1558
1559	case VMX_EXIT_INTERRUPTION_INFO_TYPE_SWEXCPT: /* Software exception. (#BP or #OF) */
1560	Assert(vector == 3 \|\| vector == 4);
1561	/* no break */
1562	case VMX_EXIT_INTERRUPTION_INFO_TYPE_HWEXCPT: /* Hardware exception. */
1563	Log2(("Hardware/software interrupt %d\n", vector));
1564	switch (vector)
1565	{
1566	case X86_XCPT_NM:
1567	{
1568	Log(("#NM fault at %VGv error code %x\n", pCtx->rip, errCode));
1569
1570	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1571	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1572	rc = CPUMR0LoadGuestFPU(pVM, pCtx);
1573	if (rc == VINF_SUCCESS)
1574	{
1575	Assert(CPUMIsGuestFPUStateActive(pVM));
1576
1577	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1578
1579	/* Continue execution. */
1580	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1581	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1582
1583	goto ResumeExecution;
1584	}
1585
1586	Log(("Forward #NM fault to the guest\n"));
1587	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1588	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, 0);
1589	AssertRC(rc);
1590	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1591	goto ResumeExecution;
1592	}
1593
1594	case X86_XCPT_PF: /* Page fault */
1595	{
1596	Log2(("Page fault at %VGv error code %x\n", exitQualification ,errCode));
1597	/* Exit qualification contains the linear address of the page fault. */
1598	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1599	TRPMSetErrorCode(pVM, errCode);
1600	TRPMSetFaultAddress(pVM, exitQualification);
1601
1602	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1603	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
1604	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1605	if (rc == VINF_SUCCESS)
1606	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1607	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, exitQualification ,errCode));
1608	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1609
1610	TRPMResetTrap(pVM);
1611
1612	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1613	goto ResumeExecution;
1614	}
1615	else
1616	if (rc == VINF_EM_RAW_GUEST_TRAP)
1617	{ /* A genuine pagefault.
1618	* Forward the trap to the guest by injecting the exception and resuming execution.
1619	*/
1620	Log2(("Forward page fault to the guest\n"));
1621	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1622	/* The error code might have been changed. */
1623	errCode = TRPMGetErrorCode(pVM);
1624
1625	TRPMResetTrap(pVM);
1626
1627	/* Now we must update CR2. */
1628	pCtx->cr2 = exitQualification;
1629	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1630	AssertRC(rc);
1631
1632	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1633	goto ResumeExecution;
1634	}
1635	#ifdef VBOX_STRICT
1636	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1637	Log2(("PGMTrap0eHandler failed with %d\n", rc));
1638	#endif
1639	/* Need to go back to the recompiler to emulate the instruction. */
1640	TRPMResetTrap(pVM);
1641	break;
1642	}
1643
1644	case X86_XCPT_MF: /* Floating point exception. */
1645	{
1646	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1647	if (!(pCtx->cr0 & X86_CR0_NE))
1648	{
1649	/* old style FPU error reporting needs some extra work. */
1650	/** @todo don't fall back to the recompiler, but do it manually. */
1651	rc = VINF_EM_RAW_EMULATE_INSTR;
1652	break;
1653	}
1654	Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1655	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1656	AssertRC(rc);
1657
1658	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1659	goto ResumeExecution;
1660	}
1661
1662	#ifdef VBOX_STRICT
1663	case X86_XCPT_GP: /* General protection failure exception.*/
1664	case X86_XCPT_UD: /* Unknown opcode exception. */
1665	case X86_XCPT_DE: /* Debug exception. */
1666	case X86_XCPT_SS: /* Stack segment exception. */
1667	case X86_XCPT_NP: /* Segment not present exception. */
1668	{
1669	switch(vector)
1670	{
1671	case X86_XCPT_DE:
1672	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1673	break;
1674	case X86_XCPT_UD:
1675	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1676	break;
1677	case X86_XCPT_SS:
1678	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1679	break;
1680	case X86_XCPT_NP:
1681	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1682	break;
1683	case X86_XCPT_GP:
1684	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1685	break;
1686	}
1687
1688	Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1689	rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
1690	AssertRC(rc);
1691
1692	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1693	goto ResumeExecution;
1694	}
1695	#endif
1696	default:
1697	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1698	rc = VERR_EM_INTERNAL_ERROR;
1699	break;
1700	} /* switch (vector) */
1701
1702	break;
1703
1704	default:
1705	rc = VERR_EM_INTERNAL_ERROR;
1706	AssertFailed();
1707	break;
1708	}
1709
1710	break;
1711	}
1712
1713	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
1714	/* Clear VM-exit on IF=1 change. */
1715	Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->rip));
1716	pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
1717	rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
1718	AssertRC(rc);
1719	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIrqWindow);
1720	goto ResumeExecution; /* we check for pending guest interrupts there */
1721
1722	case VMX_EXIT_INVD: /* 13 Guest software attempted to execute INVD. */
1723	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1724	/* Skip instruction and continue directly. */
1725	pCtx->rip += cbInstr;
1726	/* Continue execution.*/
1727	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1728	goto ResumeExecution;
1729
1730	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
1731	{
1732	Log2(("VMX: Cpuid %x\n", pCtx->eax));
1733	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1734	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1735	if (rc == VINF_SUCCESS)
1736	{
1737	/* Update EIP and continue execution. */
1738	Assert(cbInstr == 2);
1739	pCtx->rip += cbInstr;
1740	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1741	goto ResumeExecution;
1742	}
1743	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1744	rc = VINF_EM_RAW_EMULATE_INSTR;
1745	break;
1746	}
1747
1748	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
1749	{
1750	Log2(("VMX: Rdtsc\n"));
1751	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1752	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1753	if (rc == VINF_SUCCESS)
1754	{
1755	/* Update EIP and continue execution. */
1756	Assert(cbInstr == 2);
1757	pCtx->rip += cbInstr;
1758	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1759	goto ResumeExecution;
1760	}
1761	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1762	rc = VINF_EM_RAW_EMULATE_INSTR;
1763	break;
1764	}
1765
1766	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
1767	{
1768	Log2(("VMX: invlpg\n"));
1769	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1770	rc = EMInterpretInvlpg(pVM, CPUMCTX2CORE(pCtx), exitQualification);
1771	if (rc == VINF_SUCCESS)
1772	{
1773	/* Update EIP and continue execution. */
1774	pCtx->rip += cbInstr;
1775	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1776	goto ResumeExecution;
1777	}
1778	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: invlpg %VGv failed with %Vrc\n", exitQualification, rc));
1779	break;
1780	}
1781
1782	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
1783	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
1784	{
1785	uint32_t cbSize;
1786
1787	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1788	Log2(("VMX: %s\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr"));
1789	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1790	if (rc == VINF_SUCCESS)
1791	{
1792	/* EIP has been updated already. */
1793
1794	/* Only resume if successful. */
1795	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1796	goto ResumeExecution;
1797	}
1798	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (exitReason == VMX_EXIT_RDMSR) ? "rdmsr" : "wrmsr", rc));
1799	break;
1800	}
1801
1802	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
1803	{
1804	switch (VMX_EXIT_QUALIFICATION_CRX_ACCESS(exitQualification))
1805	{
1806	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
1807	Log2(("VMX: %VGv mov cr%d, x\n", pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
1808	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1809	rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
1810	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification),
1811	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification));
1812
1813	switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification))
1814	{
1815	case 0:
1816	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1817	break;
1818	case 2:
1819	break;
1820	case 3:
1821	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1822	break;
1823	case 4:
1824	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1825	break;
1826	case 8:
1827	/* CR8 contains the APIC TPR */
1828	Assert(!(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
1829	break;
1830
1831	default:
1832	AssertFailed();
1833	break;
1834	}
1835	/* Check if a sync operation is pending. */
1836	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1837	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1838	{
1839	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1840	AssertRC(rc);
1841	}
1842	break;
1843
1844	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ:
1845	Log2(("VMX: mov x, crx\n"));
1846	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1847
1848	/* CR8 reads only cause an exit when the TPR shadow feature isn't present. */
1849	Assert(VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification) != 8 \|\| !(pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW));
1850
1851	rc = EMInterpretCRxRead(pVM, CPUMCTX2CORE(pCtx),
1852	VMX_EXIT_QUALIFICATION_CRX_GENREG(exitQualification),
1853	VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification));
1854	break;
1855
1856	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS:
1857	Log2(("VMX: clts\n"));
1858	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCLTS);
1859	rc = EMInterpretCLTS(pVM);
1860	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1861	break;
1862
1863	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW:
1864	Log2(("VMX: lmsw %x\n", VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification)));
1865	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitLMSW);
1866	rc = EMInterpretLMSW(pVM, VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(exitQualification));
1867	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1868	break;
1869	}
1870
1871	/* Update EIP if no error occurred. */
1872	if (VBOX_SUCCESS(rc))
1873	pCtx->rip += cbInstr;
1874
1875	if (rc == VINF_SUCCESS)
1876	{
1877	/* Only resume if successful. */
1878	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1879	goto ResumeExecution;
1880	}
1881	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1882	break;
1883	}
1884
1885	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
1886	{
1887	/** @todo clear VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT after the first time and restore drx registers afterwards */
1888	if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
1889	{
1890	Log2(("VMX: mov drx%d, genreg%d\n", VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification), VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification)));
1891	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxWrite);
1892	rc = EMInterpretDRxWrite(pVM, CPUMCTX2CORE(pCtx),
1893	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification),
1894	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification));
1895	Log2(("DR7=%08x\n", pCtx->dr7));
1896	}
1897	else
1898	{
1899	Log2(("VMX: mov x, drx\n"));
1900	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1901	rc = EMInterpretDRxRead(pVM, CPUMCTX2CORE(pCtx),
1902	VMX_EXIT_QUALIFICATION_DRX_GENREG(exitQualification),
1903	VMX_EXIT_QUALIFICATION_DRX_REGISTER(exitQualification));
1904	}
1905	/* Update EIP if no error occurred. */
1906	if (VBOX_SUCCESS(rc))
1907	pCtx->rip += cbInstr;
1908
1909	if (rc == VINF_SUCCESS)
1910	{
1911	/* Only resume if successful. */
1912	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1913	goto ResumeExecution;
1914	}
1915	Assert(rc == VERR_EM_INTERPRETER);
1916	break;
1917	}
1918
1919	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1920	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
1921	{
1922	uint32_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(exitQualification);
1923	uint32_t uPort;
1924	bool fIOWrite = (VMX_EXIT_QUALIFICATION_IO_DIRECTION(exitQualification) == VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
1925
1926	/** @todo necessary to make the distinction? */
1927	if (VMX_EXIT_QUALIFICATION_IO_ENCODING(exitQualification) == VMX_EXIT_QUALIFICATION_IO_ENCODING_DX)
1928	{
1929	uPort = pCtx->edx & 0xffff;
1930	}
1931	else
1932	uPort = VMX_EXIT_QUALIFICATION_IO_PORT(exitQualification); /* Immediate encoding. */
1933
1934	/* paranoia */
1935	if (RT_UNLIKELY(uIOWidth == 2 \|\| uIOWidth >= 4))
1936	{
1937	rc = fIOWrite ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1938	break;
1939	}
1940
1941	uint32_t cbSize = aIOSize[uIOWidth];
1942
1943	if (VMX_EXIT_QUALIFICATION_IO_STRING(exitQualification))
1944	{
1945	/* ins/outs */
1946	uint32_t prefix = 0;
1947	if (VMX_EXIT_QUALIFICATION_IO_REP(exitQualification))
1948	prefix \|= PREFIX_REP;
1949
1950	if (fIOWrite)
1951	{
1952	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
1953	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1954	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1955	}
1956	else
1957	{
1958	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
1959	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1960	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
1961	}
1962	}
1963	else
1964	{
1965	/* normal in/out */
1966	uint32_t uAndVal = aIOOpAnd[uIOWidth];
1967
1968	Assert(!VMX_EXIT_QUALIFICATION_IO_REP(exitQualification));
1969
1970	if (fIOWrite)
1971	{
1972	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1973	rc = IOMIOPortWrite(pVM, uPort, pCtx->eax & uAndVal, cbSize);
1974	}
1975	else
1976	{
1977	uint32_t u32Val = 0;
1978
1979	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1980	rc = IOMIOPortRead(pVM, uPort, &u32Val, cbSize);
1981	if (IOM_SUCCESS(rc))
1982	{
1983	/* Write back to the EAX register. */
1984	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1985	}
1986	}
1987	}
1988	/*
1989	* Handled the I/O return codes.
1990	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1991	*/
1992	if (IOM_SUCCESS(rc))
1993	{
1994	/* Update EIP and continue execution. */
1995	pCtx->rip += cbInstr;
1996	if (RT_LIKELY(rc == VINF_SUCCESS))
1997	{
1998	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1999	goto ResumeExecution;
2000	}
2001	break;
2002	}
2003
2004	#ifdef VBOX_STRICT
2005	if (rc == VINF_IOM_HC_IOPORT_READ)
2006	Assert(!fIOWrite);
2007	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2008	Assert(fIOWrite);
2009	else
2010	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
2011	#endif
2012	break;
2013	}
2014
2015	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2016	LogFlow(("VMX_EXIT_TPR\n"));
2017	/* RIP is already set to the next instruction and the TPR has been synced back. Just resume. */
2018	goto ResumeExecution;
2019
2020	default:
2021	/* The rest is handled after syncing the entire CPU state. */
2022	break;
2023	}
2024
2025	/* Note: the guest state isn't entirely synced back at this stage. */
2026
2027	/* Investigate why there was a VM-exit. (part 2) */
2028	switch (exitReason)
2029	{
2030	case VMX_EXIT_EXCEPTION: /* 0 Exception or non-maskable interrupt (NMI). */
2031	case VMX_EXIT_EXTERNAL_IRQ: /* 1 External interrupt. */
2032	/* Already handled above. */
2033	break;
2034
2035	case VMX_EXIT_TRIPLE_FAULT: /* 2 Triple fault. */
2036	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2037	break;
2038
2039	case VMX_EXIT_INIT_SIGNAL: /* 3 INIT signal. */
2040	case VMX_EXIT_SIPI: /* 4 Start-up IPI (SIPI). */
2041	rc = VINF_EM_RAW_INTERRUPT;
2042	AssertFailed(); /* Can't happen. Yet. */
2043	break;
2044
2045	case VMX_EXIT_IO_SMI_IRQ: /* 5 I/O system-management interrupt (SMI). */
2046	case VMX_EXIT_SMI_IRQ: /* 6 Other SMI. */
2047	rc = VINF_EM_RAW_INTERRUPT;
2048	AssertFailed(); /* Can't happen afaik. */
2049	break;
2050
2051	case VMX_EXIT_TASK_SWITCH: /* 9 Task switch. */
2052	rc = VERR_EM_INTERPRETER;
2053	break;
2054
2055	case VMX_EXIT_HLT: /* 12 Guest software attempted to execute HLT. */
2056	/** Check if external interrupts are pending; if so, don't switch back. */
2057	pCtx->rip++; /* skip hlt */
2058	if ( pCtx->eflags.Bits.u1IF
2059	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
2060	goto ResumeExecution;
2061
2062	rc = VINF_EM_HALT;
2063	break;
2064
2065	case VMX_EXIT_RSM: /* 17 Guest software attempted to execute RSM in SMM. */
2066	AssertFailed(); /* can't happen. */
2067	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2068	break;
2069
2070	case VMX_EXIT_VMCALL: /* 18 Guest software executed VMCALL. */
2071	case VMX_EXIT_VMCLEAR: /* 19 Guest software executed VMCLEAR. */
2072	case VMX_EXIT_VMLAUNCH: /* 20 Guest software executed VMLAUNCH. */
2073	case VMX_EXIT_VMPTRLD: /* 21 Guest software executed VMPTRLD. */
2074	case VMX_EXIT_VMPTRST: /* 22 Guest software executed VMPTRST. */
2075	case VMX_EXIT_VMREAD: /* 23 Guest software executed VMREAD. */
2076	case VMX_EXIT_VMRESUME: /* 24 Guest software executed VMRESUME. */
2077	case VMX_EXIT_VMWRITE: /* 25 Guest software executed VMWRITE. */
2078	case VMX_EXIT_VMXOFF: /* 26 Guest software executed VMXOFF. */
2079	case VMX_EXIT_VMXON: /* 27 Guest software executed VMXON. */
2080	/** @todo inject #UD immediately */
2081	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2082	break;
2083
2084	case VMX_EXIT_CPUID: /* 10 Guest software attempted to execute CPUID. */
2085	case VMX_EXIT_RDTSC: /* 16 Guest software attempted to execute RDTSC. */
2086	case VMX_EXIT_INVPG: /* 14 Guest software attempted to execute INVPG. */
2087	case VMX_EXIT_CRX_MOVE: /* 28 Control-register accesses. */
2088	case VMX_EXIT_DRX_MOVE: /* 29 Debug-register accesses. */
2089	case VMX_EXIT_PORT_IO: /* 30 I/O instruction. */
2090	/* already handled above */
2091	AssertMsg( rc == VINF_PGM_CHANGE_MODE
2092	\|\| rc == VINF_EM_RAW_INTERRUPT
2093	\|\| rc == VERR_EM_INTERPRETER
2094	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
2095	\|\| rc == VINF_PGM_SYNC_CR3
2096	\|\| rc == VINF_IOM_HC_IOPORT_READ
2097	\|\| rc == VINF_IOM_HC_IOPORT_WRITE
2098	\|\| rc == VINF_EM_RAW_GUEST_TRAP
2099	\|\| rc == VINF_TRPM_XCPT_DISPATCHED
2100	\|\| rc == VINF_EM_RESCHEDULE_REM,
2101	("rc = %d\n", rc));
2102	break;
2103
2104	case VMX_EXIT_TPR: /* 43 TPR below threshold. Guest software executed MOV to CR8. */
2105	case VMX_EXIT_RDMSR: /* 31 RDMSR. Guest software attempted to execute RDMSR. */
2106	case VMX_EXIT_WRMSR: /* 32 WRMSR. Guest software attempted to execute WRMSR. */
2107	/* Note: If we decide to emulate them here, then we must sync the MSRs that could have been changed (sysenter, fs/gs base)!!! */
2108	rc = VERR_EM_INTERPRETER;
2109	break;
2110
2111	case VMX_EXIT_RDPMC: /* 15 Guest software attempted to execute RDPMC. */
2112	case VMX_EXIT_MWAIT: /* 36 Guest software executed MWAIT. */
2113	case VMX_EXIT_MONITOR: /* 39 Guest software attempted to execute MONITOR. */
2114	case VMX_EXIT_PAUSE: /* 40 Guest software attempted to execute PAUSE. */
2115	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2116	break;
2117
2118	case VMX_EXIT_IRQ_WINDOW: /* 7 Interrupt window. */
2119	Assert(rc == VINF_EM_RAW_INTERRUPT);
2120	break;
2121
2122	case VMX_EXIT_ERR_INVALID_GUEST_STATE: /* 33 VM-entry failure due to invalid guest state. */
2123	{
2124	#ifdef VBOX_STRICT
2125	Log(("VMX_EXIT_ERR_INVALID_GUEST_STATE\n"));
2126
2127	VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
2128	Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
2129
2130	VMXReadVMCS(VMX_VMCS_GUEST_CR0, &val);
2131	Log(("VMX_VMCS_GUEST_CR0 %RX64\n", val));
2132
2133	VMXReadVMCS(VMX_VMCS_GUEST_CR3, &val);
2134	Log(("VMX_VMCS_HOST_CR3 %VGp\n", val));
2135
2136	VMXReadVMCS(VMX_VMCS_GUEST_CR4, &val);
2137	Log(("VMX_VMCS_GUEST_CR4 %RX64\n", val));
2138
2139	VMX_LOG_SELREG(CS, "CS");
2140	VMX_LOG_SELREG(DS, "DS");
2141	VMX_LOG_SELREG(ES, "ES");
2142	VMX_LOG_SELREG(FS, "FS");
2143	VMX_LOG_SELREG(GS, "GS");
2144	VMX_LOG_SELREG(SS, "SS");
2145	VMX_LOG_SELREG(TR, "TR");
2146	VMX_LOG_SELREG(LDTR, "LDTR");
2147
2148	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2149	Log(("VMX_VMCS_GUEST_GDTR_BASE %VGv\n", val));
2150	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2151	Log(("VMX_VMCS_GUEST_IDTR_BASE %VGv\n", val));
2152	#endif /* VBOX_STRICT */
2153	rc = VERR_EM_INTERNAL_ERROR;
2154	break;
2155	}
2156
2157	case VMX_EXIT_ERR_MSR_LOAD: /* 34 VM-entry failure due to MSR loading. */
2158	case VMX_EXIT_ERR_MACHINE_CHECK: /* 41 VM-entry failure due to machine-check. */
2159	default:
2160	rc = VERR_EM_INTERNAL_ERROR;
2161	AssertMsgFailed(("Unexpected exit code %d\n", exitReason)); /* Can't happen. */
2162	break;
2163
2164	}
2165	end:
2166	if (fGuestStateSynced)
2167	{
2168	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
2169	VMX_READ_SELREG(LDTR, ldtr);
2170	VMX_READ_SELREG(TR, tr);
2171
2172	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_LIMIT, &val);
2173	pCtx->gdtr.cbGdt = val;
2174	VMXReadVMCS(VMX_VMCS_GUEST_GDTR_BASE, &val);
2175	pCtx->gdtr.pGdt = val;
2176
2177	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_LIMIT, &val);
2178	pCtx->idtr.cbIdt = val;
2179	VMXReadVMCS(VMX_VMCS_GUEST_IDTR_BASE, &val);
2180	pCtx->idtr.pIdt = val;
2181	}
2182
2183	/* Signal changes for the recompiler. */
2184	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
2185
2186	/* If we executed vmlaunch/vmresume and an external irq was pending, then we don't have to do a full sync the next time. */
2187	if ( exitReason == VMX_EXIT_EXTERNAL_IRQ
2188	&& !VMX_EXIT_INTERRUPTION_INFO_VALID(intInfo))
2189	{
2190	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2191	/* On the next entry we'll only sync the host context. */
2192	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
2193	}
2194	else
2195	{
2196	/* On the next entry we'll sync everything. */
2197	/** @todo we can do better than this */
2198	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
2199	}
2200
2201	/* translate into a less severe return code */
2202	if (rc == VERR_EM_INTERPRETER)
2203	rc = VINF_EM_RAW_EMULATE_INSTR;
2204
2205	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2206	Log2(("X"));
2207	return rc;
2208	}
2209
2210
2211	/**
2212	* Enters the VT-x session
2213	*
2214	* @returns VBox status code.
2215	* @param pVM The VM to operate on.
2216	* @param pCpu CPU info struct
2217	*/
2218	HWACCMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
2219	{
2220	Assert(pVM->hwaccm.s.vmx.fSupported);
2221
2222	unsigned cr4 = ASMGetCR4();
2223	if (!(cr4 & X86_CR4_VMXE))
2224	{
2225	AssertMsgFailed(("X86_CR4_VMXE should be set!\n"));
2226	return VERR_VMX_X86_CR4_VMXE_CLEARED;
2227	}
2228
2229	/* Activate the VM Control Structure. */
2230	int rc = VMXActivateVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2231	if (VBOX_FAILURE(rc))
2232	return rc;
2233
2234	pVM->hwaccm.s.vmx.fResumeVM = false;
2235	return VINF_SUCCESS;
2236	}
2237
2238
2239	/**
2240	* Leaves the VT-x session
2241	*
2242	* @returns VBox status code.
2243	* @param pVM The VM to operate on.
2244	*/
2245	HWACCMR0DECL(int) VMXR0Leave(PVM pVM)
2246	{
2247	Assert(pVM->hwaccm.s.vmx.fSupported);
2248
2249	/* Clear VM Control Structure. Marking it inactive, clearing implementation specific data and writing back VMCS data to memory. */
2250	int rc = VMXClearVMCS(pVM->hwaccm.s.vmx.pVMCSPhys);
2251	AssertRC(rc);
2252
2253	return VINF_SUCCESS;
2254	}
2255

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp@ 11347

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