VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 7954

Last change on this file since 7954 was 7717, checked in by vboxsync, 17 years ago

Some write protect changes
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 64.9 KB
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1/* $Id: HWSVMR0.cpp 7717 2008-04-03 09:54:12Z vboxsync $ */
2/** @file
3 * HWACCM SVM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_HWACCM
23#include <VBox/hwaccm.h>
24#include "HWACCMInternal.h"
25#include <VBox/vm.h>
26#include <VBox/x86.h>
27#include <VBox/hwacc_svm.h>
28#include <VBox/pgm.h>
29#include <VBox/pdm.h>
30#include <VBox/err.h>
31#include <VBox/log.h>
32#include <VBox/selm.h>
33#include <VBox/iom.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/disopcode.h>
37#include <iprt/param.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include "HWSVMR0.h"
41
42static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
43
44/**
45 * Sets up and activates AMD-V on the current CPU
46 *
47 * @returns VBox status code.
48 * @param idCpu The identifier for the CPU the function is called on.
49 * @param pVM The VM to operate on.
50 * @param pvPageCpu Pointer to the global cpu page
51 * @param pPageCpuPhys Physical address of the global cpu page
52 */
53HWACCMR0DECL(int) SVMR0EnableCpu(RTCPUID idCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
54{
55 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
56 AssertReturn(pVM, VERR_INVALID_PARAMETER);
57 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
58
59 /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
60
61 /* Turn on AMD-V in the EFER MSR. */
62 uint64_t val = ASMRdMsr(MSR_K6_EFER);
63 if (!(val & MSR_K6_EFER_SVME))
64 ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);
65
66 /* Write the physical page address where the CPU will store the host state while executing the VM. */
67 ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
68 return VINF_SUCCESS;
69}
70
71/**
72 * Deactivates AMD-V on the current CPU
73 *
74 * @returns VBox status code.
75 * @param idCpu The identifier for the CPU the function is called on.
76 * @param pvPageCpu Pointer to the global cpu page
77 * @param pPageCpuPhys Physical address of the global cpu page
78 */
79HWACCMR0DECL(int) SVMR0DisableCpu(RTCPUID idCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
80{
81 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
82 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
83
84 /* Turn off AMD-V in the EFER MSR. */
85 uint64_t val = ASMRdMsr(MSR_K6_EFER);
86 ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
87
88 /* Invalidate host state physical address. */
89 ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
90 return VINF_SUCCESS;
91}
92
93/**
94 * Does Ring-0 per VM AMD-V init.
95 *
96 * @returns VBox status code.
97 * @param pVM The VM to operate on.
98 */
99HWACCMR0DECL(int) SVMR0InitVM(PVM pVM)
100{
101 int rc;
102
103 /* Allocate one page for the VM control block (VMCB). */
104 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
105 if (RT_FAILURE(rc))
106 return rc;
107
108 pVM->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCB);
109 pVM->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCB, 0);
110 ASMMemZero32(pVM->hwaccm.s.svm.pVMCB, PAGE_SIZE);
111
112 /* Allocate one page for the host context */
113 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
114 if (RT_FAILURE(rc))
115 return rc;
116
117 pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
118 pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
119 ASMMemZero32(pVM->hwaccm.s.svm.pVMCBHost, PAGE_SIZE);
120
121 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
122 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
123 if (RT_FAILURE(rc))
124 return rc;
125
126 pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
127 pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
128 /* Set all bits to intercept all IO accesses. */
129 ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
130
131 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
132 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
133 if (RT_FAILURE(rc))
134 return rc;
135
136 pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
137 pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
138 /* Set all bits to intercept all MSR accesses. */
139 ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
140
141 return VINF_SUCCESS;
142}
143
144/**
145 * Does Ring-0 per VM AMD-V termination.
146 *
147 * @returns VBox status code.
148 * @param pVM The VM to operate on.
149 */
150HWACCMR0DECL(int) SVMR0TermVM(PVM pVM)
151{
152 if (pVM->hwaccm.s.svm.pMemObjVMCB)
153 {
154 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCB, false);
155 pVM->hwaccm.s.svm.pVMCB = 0;
156 pVM->hwaccm.s.svm.pVMCBPhys = 0;
157 pVM->hwaccm.s.svm.pMemObjVMCB = 0;
158 }
159 if (pVM->hwaccm.s.svm.pMemObjVMCBHost)
160 {
161 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
162 pVM->hwaccm.s.svm.pVMCBHost = 0;
163 pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
164 pVM->hwaccm.s.svm.pMemObjVMCBHost = 0;
165 }
166 if (pVM->hwaccm.s.svm.pMemObjIOBitmap)
167 {
168 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
169 pVM->hwaccm.s.svm.pIOBitmap = 0;
170 pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
171 pVM->hwaccm.s.svm.pMemObjIOBitmap = 0;
172 }
173 if (pVM->hwaccm.s.svm.pMemObjMSRBitmap)
174 {
175 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
176 pVM->hwaccm.s.svm.pMSRBitmap = 0;
177 pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
178 pVM->hwaccm.s.svm.pMemObjMSRBitmap = 0;
179 }
180 return VINF_SUCCESS;
181}
182
183/**
184 * Sets up AMD-V for the specified VM
185 *
186 * @returns VBox status code.
187 * @param pVM The VM to operate on.
188 */
189HWACCMR0DECL(int) SVMR0SetupVM(PVM pVM)
190{
191 int rc = VINF_SUCCESS;
192 SVM_VMCB *pVMCB;
193
194 AssertReturn(pVM, VERR_INVALID_PARAMETER);
195
196 Assert(pVM->hwaccm.s.svm.fSupported);
197
198 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
199 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
200
201 /* Program the control fields. Most of them never have to be changed again. */
202 /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
203 /** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
204 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4) | RT_BIT(8);
205
206 /*
207 * CR0/3/4 writes must be intercepted for obvious reasons.
208 */
209 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4) | RT_BIT(8);
210
211 /* Intercept all DRx reads and writes. */
212 pVMCB->ctrl.u16InterceptRdDRx = RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7);
213 pVMCB->ctrl.u16InterceptWrDRx = RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7);
214
215 /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
216 * All breakpoints are automatically cleared when the VM exits.
217 */
218
219 /** @todo nested paging */
220 /* Intercept #NM only; #PF is not relevant due to nested paging (we get a seperate exit code (SVM_EXIT_NPF) for
221 * pagefaults that need our attention).
222 */
223 pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
224
225 pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
226 | SVM_CTRL1_INTERCEPT_VINTR
227 | SVM_CTRL1_INTERCEPT_NMI
228 | SVM_CTRL1_INTERCEPT_SMI
229 | SVM_CTRL1_INTERCEPT_INIT
230 | SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
231 | SVM_CTRL1_INTERCEPT_RDPMC
232 | SVM_CTRL1_INTERCEPT_CPUID
233 | SVM_CTRL1_INTERCEPT_RSM
234 | SVM_CTRL1_INTERCEPT_HLT
235 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP
236 | SVM_CTRL1_INTERCEPT_MSR_SHADOW
237 | SVM_CTRL1_INTERCEPT_INVLPG
238 | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
239 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
240 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
241 ;
242 pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
243 | SVM_CTRL2_INTERCEPT_VMMCALL
244 | SVM_CTRL2_INTERCEPT_VMLOAD
245 | SVM_CTRL2_INTERCEPT_VMSAVE
246 | SVM_CTRL2_INTERCEPT_STGI
247 | SVM_CTRL2_INTERCEPT_CLGI
248 | SVM_CTRL2_INTERCEPT_SKINIT
249 | SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
250 ;
251 Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
252 Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
253 Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
254
255 /* Virtualize masking of INTR interrupts. */
256 pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
257
258 /* Set IO and MSR bitmap addresses. */
259 pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
260 pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
261
262 /* Enable nested paging. */
263 /** @todo how to detect support for this?? */
264 pVMCB->ctrl.u64NestedPaging = 0; /** @todo SVM_NESTED_PAGING_ENABLE; */
265
266 /* No LBR virtualization. */
267 pVMCB->ctrl.u64LBRVirt = 0;
268
269 return rc;
270}
271
272
273/**
274 * Injects an event (trap or external interrupt)
275 *
276 * @param pVM The VM to operate on.
277 * @param pVMCB SVM control block
278 * @param pCtx CPU Context
279 * @param pIntInfo SVM interrupt info
280 */
281inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)
282{
283#ifdef VBOX_STRICT
284 if (pEvent->n.u8Vector == 0xE)
285 Log(("SVM: Inject int %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
286 else
287 if (pEvent->n.u8Vector < 0x20)
288 Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode));
289 else
290 {
291 Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->eip));
292 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
293 Assert(pCtx->eflags.u32 & X86_EFL_IF);
294 }
295#endif
296
297 /* Set event injection state. */
298 pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
299}
300
301
302/**
303 * Checks for pending guest interrupts and injects them
304 *
305 * @returns VBox status code.
306 * @param pVM The VM to operate on.
307 * @param pVMCB SVM control block
308 * @param pCtx CPU Context
309 */
310static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
311{
312 int rc;
313
314 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
315 if (pVM->hwaccm.s.Event.fPending)
316 {
317 SVM_EVENT Event;
318
319 Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
320 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
321 Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
322 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
323
324 pVM->hwaccm.s.Event.fPending = false;
325 return VINF_SUCCESS;
326 }
327
328 /* When external interrupts are pending, we should exit the VM when IF is set. */
329 if ( !TRPMHasTrap(pVM)
330 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
331 {
332 if (!(pCtx->eflags.u32 & X86_EFL_IF))
333 {
334 Log2(("Enable irq window exit!\n"));
335 /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
336//// pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
337//// AssertRC(rc);
338 }
339 else
340 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
341 {
342 uint8_t u8Interrupt;
343
344 rc = PDMGetInterrupt(pVM, &u8Interrupt);
345 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
346 if (VBOX_SUCCESS(rc))
347 {
348 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
349 AssertRC(rc);
350 }
351 else
352 {
353 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
354 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
355 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
356 /* Just continue */
357 }
358 }
359 else
360 Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
361 }
362
363#ifdef VBOX_STRICT
364 if (TRPMHasTrap(pVM))
365 {
366 uint8_t u8Vector;
367 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
368 AssertRC(rc);
369 }
370#endif
371
372 if ( pCtx->eflags.u32 & X86_EFL_IF
373 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
374 && TRPMHasTrap(pVM)
375 )
376 {
377 uint8_t u8Vector;
378 int rc;
379 TRPMEVENT enmType;
380 SVM_EVENT Event;
381 uint32_t u32ErrorCode;
382
383 Event.au64[0] = 0;
384
385 /* If a new event is pending, then dispatch it now. */
386 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
387 AssertRC(rc);
388 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
389 Assert(enmType != TRPM_SOFTWARE_INT);
390
391 /* Clear the pending trap. */
392 rc = TRPMResetTrap(pVM);
393 AssertRC(rc);
394
395 Event.n.u8Vector = u8Vector;
396 Event.n.u1Valid = 1;
397 Event.n.u32ErrorCode = u32ErrorCode;
398
399 if (enmType == TRPM_TRAP)
400 {
401 switch (u8Vector) {
402 case 8:
403 case 10:
404 case 11:
405 case 12:
406 case 13:
407 case 14:
408 case 17:
409 /* Valid error codes. */
410 Event.n.u1ErrorCodeValid = 1;
411 break;
412 default:
413 break;
414 }
415 if (u8Vector == X86_XCPT_NMI)
416 Event.n.u3Type = SVM_EVENT_NMI;
417 else
418 Event.n.u3Type = SVM_EVENT_EXCEPTION;
419 }
420 else
421 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
422
423 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
424 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
425 } /* if (interrupts can be dispatched) */
426
427 return VINF_SUCCESS;
428}
429
430
431/**
432 * Loads the guest state
433 *
434 * @returns VBox status code.
435 * @param pVM The VM to operate on.
436 * @param pCtx Guest context
437 */
438HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
439{
440 RTGCUINTPTR val;
441 SVM_VMCB *pVMCB;
442
443 if (pVM == NULL)
444 return VERR_INVALID_PARAMETER;
445
446 /* Setup AMD SVM. */
447 Assert(pVM->hwaccm.s.svm.fSupported);
448
449 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
450 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
451
452 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
453 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
454 {
455 SVM_WRITE_SELREG(CS, cs);
456 SVM_WRITE_SELREG(SS, ss);
457 SVM_WRITE_SELREG(DS, ds);
458 SVM_WRITE_SELREG(ES, es);
459 SVM_WRITE_SELREG(FS, fs);
460 SVM_WRITE_SELREG(GS, gs);
461 }
462
463 /* Guest CPU context: LDTR. */
464 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
465 {
466 SVM_WRITE_SELREG(LDTR, ldtr);
467 }
468
469 /* Guest CPU context: TR. */
470 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
471 {
472 SVM_WRITE_SELREG(TR, tr);
473 }
474
475 /* Guest CPU context: GDTR. */
476 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
477 {
478 pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
479 pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
480 }
481
482 /* Guest CPU context: IDTR. */
483 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
484 {
485 pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
486 pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
487 }
488
489 /*
490 * Sysenter MSRs
491 */
492 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
493 {
494 pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
495 pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
496 pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
497 }
498
499 /* Control registers */
500 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
501 {
502 val = pCtx->cr0;
503 if (CPUMIsGuestFPUStateActive(pVM) == false)
504 {
505 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
506 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
507 }
508 else
509 {
510 Assert(pVM->hwaccm.s.svm.fResumeVM == true);
511 /** @todo check if we support the old style mess correctly. */
512 if (!(val & X86_CR0_NE))
513 {
514 Log(("Forcing X86_CR0_NE!!!\n"));
515
516 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
517 if (!pVM->hwaccm.s.fFPUOldStyleOverride)
518 {
519 pVMCB->ctrl.u32InterceptException |= RT_BIT(16);
520 pVM->hwaccm.s.fFPUOldStyleOverride = true;
521 }
522 }
523 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
524 }
525 if (!(val & X86_CR0_CD))
526 val &= ~X86_CR0_NW; /* Illegal when cache is turned on. */
527
528 val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
529 val |= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
530 pVMCB->guest.u64CR0 = val;
531 }
532 /* CR2 as well */
533 pVMCB->guest.u64CR2 = pCtx->cr2;
534
535 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
536 {
537 /* Save our shadow CR3 register. */
538 pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
539 }
540
541 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
542 {
543 val = pCtx->cr4;
544 switch(pVM->hwaccm.s.enmShadowMode)
545 {
546 case PGMMODE_REAL:
547 case PGMMODE_PROTECTED: /* Protected mode, no paging. */
548 AssertFailed();
549 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
550
551 case PGMMODE_32_BIT: /* 32-bit paging. */
552 break;
553
554 case PGMMODE_PAE: /* PAE paging. */
555 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
556 /** @todo use normal 32 bits paging */
557 val |= X86_CR4_PAE;
558 break;
559
560 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
561 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
562 AssertFailed();
563 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
564
565 default: /* shut up gcc */
566 AssertFailed();
567 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
568 }
569 pVMCB->guest.u64CR4 = val;
570 }
571
572 /* Debug registers. */
573 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
574 {
575 /** @todo DR0-6 */
576 val = pCtx->dr7;
577 val &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
578 val |= 0x400; /* must be one */
579#ifdef VBOX_STRICT
580 val = 0x400;
581#endif
582 pVMCB->guest.u64DR7 = val;
583
584 pVMCB->guest.u64DR6 = pCtx->dr6;
585 }
586
587 /* EIP, ESP and EFLAGS */
588 pVMCB->guest.u64RIP = pCtx->eip;
589 pVMCB->guest.u64RSP = pCtx->esp;
590 pVMCB->guest.u64RFlags = pCtx->eflags.u32;
591
592 /* Set CPL */
593 pVMCB->guest.u8CPL = pCtx->ssHid.Attr.n.u2Dpl;
594
595 /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
596 pVMCB->guest.u64RAX = pCtx->eax;
597
598 /* vmrun will fail otherwise. */
599 pVMCB->guest.u64EFER = MSR_K6_EFER_SVME;
600
601 /** @note We can do more complex things with tagged TLBs. */
602 pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
603
604 /** TSC offset. */
605 if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
606 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
607 else
608 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
609
610 /** @todo 64 bits stuff (?):
611 * - STAR
612 * - LSTAR
613 * - CSTAR
614 * - SFMASK
615 * - KernelGSBase
616 */
617
618#ifdef DEBUG
619 /* Intercept X86_XCPT_DB if stepping is enabled */
620 if (DBGFIsStepping(pVM))
621 pVMCB->ctrl.u32InterceptException |= RT_BIT(1);
622 else
623 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(1);
624#endif
625
626 /* Done. */
627 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
628
629 return VINF_SUCCESS;
630}
631
632
633/**
634 * Runs guest code in an SVM VM.
635 *
636 * @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
637 *
638 * @returns VBox status code.
639 * @param pVM The VM to operate on.
640 * @param pCtx Guest context
641 */
642HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
643{
644 int rc = VINF_SUCCESS;
645 uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
646 SVM_VMCB *pVMCB;
647 bool fForceTLBFlush = false;
648 bool fGuestStateSynced = false;
649 unsigned cResume = 0;
650
651 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
652
653 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
654 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
655
656 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
657 */
658ResumeExecution:
659 /* Safety precaution; looping for too long here can have a very bad effect on the host */
660 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
661 {
662 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
663 rc = VINF_EM_RAW_INTERRUPT;
664 goto end;
665 }
666
667 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
668 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
669 {
670 Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
671 if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
672 {
673 /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
674 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
675 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
676 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
677 */
678 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
679 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
680 pVMCB->ctrl.u64IntShadow = 0;
681 }
682 }
683 else
684 {
685 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
686 pVMCB->ctrl.u64IntShadow = 0;
687 }
688
689 /* Check for pending actions that force us to go back to ring 3. */
690#ifdef DEBUG
691 /* Intercept X86_XCPT_DB if stepping is enabled */
692 if (!DBGFIsStepping(pVM))
693#endif
694 {
695 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
696 {
697 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
698 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
699 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
700 rc = VINF_EM_RAW_TO_R3;
701 goto end;
702 }
703 }
704
705 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
706 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
707 {
708 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
709 rc = VINF_EM_PENDING_REQUEST;
710 goto end;
711 }
712
713 /* When external interrupts are pending, we should exit the VM when IF is set. */
714 /** @note *after* VM_FF_INHIBIT_INTERRUPTS check!!! */
715 rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
716 if (VBOX_FAILURE(rc))
717 {
718 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
719 goto end;
720 }
721
722 /* Load the guest state */
723 rc = SVMR0LoadGuestState(pVM, pCtx);
724 if (rc != VINF_SUCCESS)
725 {
726 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
727 goto end;
728 }
729 fGuestStateSynced = true;
730
731 /* All done! Let's start VM execution. */
732 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
733
734 /** Erratum #170 -> must force a TLB flush */
735 /** @todo supposed to be fixed in future by AMD */
736 fForceTLBFlush = true;
737
738 if ( pVM->hwaccm.s.svm.fResumeVM == false
739 || fForceTLBFlush)
740 {
741 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1;
742 }
743 else
744 {
745 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 0;
746 }
747 /* In case we execute a goto ResumeExecution later on. */
748 pVM->hwaccm.s.svm.fResumeVM = true;
749 fForceTLBFlush = false;
750
751 Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
752 Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
753 | SVM_CTRL2_INTERCEPT_VMMCALL
754 | SVM_CTRL2_INTERCEPT_VMLOAD
755 | SVM_CTRL2_INTERCEPT_VMSAVE
756 | SVM_CTRL2_INTERCEPT_STGI
757 | SVM_CTRL2_INTERCEPT_CLGI
758 | SVM_CTRL2_INTERCEPT_SKINIT
759 | SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
760 ));
761 Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
762 Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
763 Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
764 Assert(pVMCB->ctrl.u64NestedPaging == 0);
765 Assert(pVMCB->ctrl.u64LBRVirt == 0);
766
767 SVMVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
768 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
769
770 /**
771 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
772 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
773 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
774 */
775
776 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
777
778 /* Reason for the VM exit */
779 exitCode = pVMCB->ctrl.u64ExitCode;
780
781 if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
782 {
783 HWACCMDumpRegs(pCtx);
784#ifdef DEBUG
785 Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
786 Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
787 Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
788 Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
789 Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
790 Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
791 Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
792 Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
793 Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
794 Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
795
796 Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
797 Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
798 Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
799 Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
800
801 Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
802 Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
803 Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
804 Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
805 Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
806 Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
807 Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
808 Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
809 Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
810 Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
811
812 Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
813 Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
814 Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
815 Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
816 Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
817 Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
818 Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
819 Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
820 Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
821 Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
822 Log(("ctrl.u64NestedPaging %VX64\n", pVMCB->ctrl.u64NestedPaging));
823 Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
824 Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
825 Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
826 Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
827 Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
828 Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
829
830 Log(("ctrl.u64HostCR3 %VX64\n", pVMCB->ctrl.u64HostCR3));
831 Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
832
833 Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
834 Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
835 Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
836 Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
837 Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
838 Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
839 Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
840 Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
841 Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
842 Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
843 Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
844 Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
845 Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
846 Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
847 Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
848 Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
849 Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
850 Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
851 Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
852 Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
853
854 Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
855 Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
856
857 Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
858 Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
859 Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
860 Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
861
862 Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
863 Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
864
865 Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
866 Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
867 Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
868 Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
869
870 Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
871 Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
872 Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
873 Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
874 Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
875 Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
876 Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
877
878 Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
879 Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
880 Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
881 Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
882
883 Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
884 Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
885 Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
886
887 Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
888 Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
889 Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
890 Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
891 Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
892 Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
893 Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
894 Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
895 Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
896 Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
897 Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
898 Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
899
900#endif
901 rc = VERR_SVM_UNABLE_TO_START_VM;
902 goto end;
903 }
904
905 /* Let's first sync back eip, esp, and eflags. */
906 pCtx->eip = pVMCB->guest.u64RIP;
907 pCtx->esp = pVMCB->guest.u64RSP;
908 pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
909 /* eax is saved/restore across the vmrun instruction */
910 pCtx->eax = pVMCB->guest.u64RAX;
911
912 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
913 SVM_READ_SELREG(SS, ss);
914 SVM_READ_SELREG(CS, cs);
915 SVM_READ_SELREG(DS, ds);
916 SVM_READ_SELREG(ES, es);
917 SVM_READ_SELREG(FS, fs);
918 SVM_READ_SELREG(GS, gs);
919
920 /** @note no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
921
922 /** @note NOW IT'S SAFE FOR LOGGING! */
923
924 /* Take care of instruction fusing (sti, mov ss) */
925 if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
926 {
927 Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->eip));
928 EMSetInhibitInterruptsPC(pVM, pCtx->eip);
929 }
930 else
931 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
932
933 Log2(("exitCode = %x\n", exitCode));
934
935 /* Check if an injected event was interrupted prematurely. */
936 pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
937 if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
938 && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
939 {
940 Log(("Pending inject %VX64 at %08x exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitCode));
941 pVM->hwaccm.s.Event.fPending = true;
942 /* Error code present? (redundant) */
943 if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
944 {
945 pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
946 }
947 else
948 pVM->hwaccm.s.Event.errCode = 0;
949 }
950 STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
951
952 /* Deal with the reason of the VM-exit. */
953 switch (exitCode)
954 {
955 case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
956 case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
957 case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
958 case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
959 case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
960 case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
961 case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
962 case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
963 {
964 /* Pending trap. */
965 SVM_EVENT Event;
966 uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
967
968 Log2(("Hardware/software interrupt %d\n", vector));
969 switch (vector)
970 {
971#ifdef DEBUG
972 case X86_XCPT_DB:
973 rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pVMCB->guest.u64DR6);
974 Assert(rc != VINF_EM_RAW_GUEST_TRAP);
975 break;
976#endif
977
978 case X86_XCPT_NM:
979 {
980 uint32_t oldCR0;
981
982 Log(("#NM fault at %VGv\n", pCtx->eip));
983
984 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
985 oldCR0 = ASMGetCR0();
986 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
987 rc = CPUMHandleLazyFPU(pVM);
988 if (rc == VINF_SUCCESS)
989 {
990 Assert(CPUMIsGuestFPUStateActive(pVM));
991
992 /* CPUMHandleLazyFPU could have changed CR0; restore it. */
993 ASMSetCR0(oldCR0);
994
995 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
996
997 /* Continue execution. */
998 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
999 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1000
1001 goto ResumeExecution;
1002 }
1003
1004 Log(("Forward #NM fault to the guest\n"));
1005 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1006
1007 Event.au64[0] = 0;
1008 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1009 Event.n.u1Valid = 1;
1010 Event.n.u8Vector = X86_XCPT_NM;
1011
1012 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1013 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1014 goto ResumeExecution;
1015 }
1016
1017 case X86_XCPT_PF: /* Page fault */
1018 {
1019 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1020 RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1021
1022 Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
1023 /* Exit qualification contains the linear address of the page fault. */
1024 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1025 TRPMSetErrorCode(pVM, errCode);
1026 TRPMSetFaultAddress(pVM, uFaultAddress);
1027
1028 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1029 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1030 Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
1031 if (rc == VINF_SUCCESS)
1032 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1033 Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
1034 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1035
1036 TRPMResetTrap(pVM);
1037
1038 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1039 goto ResumeExecution;
1040 }
1041 else
1042 if (rc == VINF_EM_RAW_GUEST_TRAP)
1043 { /* A genuine pagefault.
1044 * Forward the trap to the guest by injecting the exception and resuming execution.
1045 */
1046 Log2(("Forward page fault to the guest\n"));
1047 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1048 /* The error code might have been changed. */
1049 errCode = TRPMGetErrorCode(pVM);
1050
1051 TRPMResetTrap(pVM);
1052
1053 /* Now we must update CR2. */
1054 pCtx->cr2 = uFaultAddress;
1055
1056 Event.au64[0] = 0;
1057 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1058 Event.n.u1Valid = 1;
1059 Event.n.u8Vector = X86_XCPT_PF;
1060 Event.n.u1ErrorCodeValid = 1;
1061 Event.n.u32ErrorCode = errCode;
1062
1063 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1064
1065 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1066 goto ResumeExecution;
1067 }
1068#ifdef VBOX_STRICT
1069 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1070 Log(("PGMTrap0eHandler failed with %d\n", rc));
1071#endif
1072 /* Need to go back to the recompiler to emulate the instruction. */
1073 TRPMResetTrap(pVM);
1074 break;
1075 }
1076
1077 case X86_XCPT_MF: /* Floating point exception. */
1078 {
1079 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1080 if (!(pCtx->cr0 & X86_CR0_NE))
1081 {
1082 /* old style FPU error reporting needs some extra work. */
1083 /** @todo don't fall back to the recompiler, but do it manually. */
1084 rc = VINF_EM_RAW_EMULATE_INSTR;
1085 break;
1086 }
1087 Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1088
1089 Event.au64[0] = 0;
1090 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1091 Event.n.u1Valid = 1;
1092 Event.n.u8Vector = X86_XCPT_MF;
1093
1094 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1095
1096 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1097 goto ResumeExecution;
1098 }
1099
1100#ifdef VBOX_STRICT
1101 case X86_XCPT_GP: /* General protection failure exception.*/
1102 case X86_XCPT_UD: /* Unknown opcode exception. */
1103 case X86_XCPT_DE: /* Debug exception. */
1104 case X86_XCPT_SS: /* Stack segment exception. */
1105 case X86_XCPT_NP: /* Segment not present exception. */
1106 {
1107 Event.au64[0] = 0;
1108 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1109 Event.n.u1Valid = 1;
1110 Event.n.u8Vector = vector;
1111
1112 switch(vector)
1113 {
1114 case X86_XCPT_GP:
1115 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1116 Event.n.u1ErrorCodeValid = 1;
1117 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1118 break;
1119 case X86_XCPT_DE:
1120 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1121 break;
1122 case X86_XCPT_UD:
1123 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1124 break;
1125 case X86_XCPT_SS:
1126 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1127 Event.n.u1ErrorCodeValid = 1;
1128 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1129 break;
1130 case X86_XCPT_NP:
1131 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1132 Event.n.u1ErrorCodeValid = 1;
1133 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1134 break;
1135 }
1136 Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1137 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1138
1139 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1140 goto ResumeExecution;
1141 }
1142#endif
1143 default:
1144 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1145 rc = VERR_EM_INTERNAL_ERROR;
1146 break;
1147
1148 } /* switch (vector) */
1149 break;
1150 }
1151
1152 case SVM_EXIT_FERR_FREEZE:
1153 case SVM_EXIT_INTR:
1154 case SVM_EXIT_NMI:
1155 case SVM_EXIT_SMI:
1156 case SVM_EXIT_INIT:
1157 case SVM_EXIT_VINTR:
1158 /* External interrupt; leave to allow it to be dispatched again. */
1159 rc = VINF_EM_RAW_INTERRUPT;
1160 break;
1161
1162 case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1163 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1164 /* Skip instruction and continue directly. */
1165 pCtx->eip += 2; /** @note hardcoded opcode size! */
1166 /* Continue execution.*/
1167 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1168 goto ResumeExecution;
1169
1170 case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1171 {
1172 Log2(("SVM: Cpuid %x\n", pCtx->eax));
1173 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1174 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1175 if (rc == VINF_SUCCESS)
1176 {
1177 /* Update EIP and continue execution. */
1178 pCtx->eip += 2; /** @note hardcoded opcode size! */
1179 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1180 goto ResumeExecution;
1181 }
1182 AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1183 rc = VINF_EM_RAW_EMULATE_INSTR;
1184 break;
1185 }
1186
1187 case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1188 {
1189 Log2(("SVM: Rdtsc\n"));
1190 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1191 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1192 if (rc == VINF_SUCCESS)
1193 {
1194 /* Update EIP and continue execution. */
1195 pCtx->eip += 2; /** @note hardcoded opcode size! */
1196 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1197 goto ResumeExecution;
1198 }
1199 AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1200 rc = VINF_EM_RAW_EMULATE_INSTR;
1201 break;
1202 }
1203
1204 case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1205 {
1206 Log2(("SVM: invlpg\n"));
1207 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1208
1209 /* Truly a pita. Why can't SVM give the same information as VMX? */
1210 rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1211 if (rc == VINF_SUCCESS)
1212 goto ResumeExecution; /* eip already updated */
1213 break;
1214 }
1215
1216 case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1217 case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1218 case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1219 case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1220 {
1221 uint32_t cbSize;
1222
1223 Log2(("SVM: %VGv mov cr%d, \n", pCtx->eip, exitCode - SVM_EXIT_WRITE_CR0));
1224 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1225 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1226
1227 switch (exitCode - SVM_EXIT_WRITE_CR0)
1228 {
1229 case 0:
1230 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1231 break;
1232 case 2:
1233 break;
1234 case 3:
1235 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
1236 break;
1237 case 4:
1238 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
1239 break;
1240 default:
1241 AssertFailed();
1242 }
1243 /* Check if a sync operation is pending. */
1244 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1245 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1246 {
1247 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1248 AssertRC(rc);
1249
1250 /** @note Force a TLB flush. SVM requires us to do it manually. */
1251 fForceTLBFlush = true;
1252 }
1253 if (rc == VINF_SUCCESS)
1254 {
1255 /* EIP has been updated already. */
1256
1257 /* Only resume if successful. */
1258 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1259 goto ResumeExecution;
1260 }
1261 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1262 break;
1263 }
1264
1265 case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1266 case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1267 case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1268 case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1269 {
1270 uint32_t cbSize;
1271
1272 Log2(("SVM: %VGv mov x, cr%d\n", pCtx->eip, exitCode - SVM_EXIT_READ_CR0));
1273 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1274 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1275 if (rc == VINF_SUCCESS)
1276 {
1277 /* EIP has been updated already. */
1278
1279 /* Only resume if successful. */
1280 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1281 goto ResumeExecution;
1282 }
1283 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1284 break;
1285 }
1286
1287 case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1288 case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1289 case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1290 case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1291 {
1292 uint32_t cbSize;
1293
1294 Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_WRITE_DR0));
1295 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1296 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1297 if (rc == VINF_SUCCESS)
1298 {
1299 /* EIP has been updated already. */
1300
1301 /* Only resume if successful. */
1302 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1303 goto ResumeExecution;
1304 }
1305 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1306 break;
1307 }
1308
1309 case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1310 case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1311 case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1312 case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1313 {
1314 uint32_t cbSize;
1315
1316 Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_READ_DR0));
1317 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1318 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1319 if (rc == VINF_SUCCESS)
1320 {
1321 /* EIP has been updated already. */
1322
1323 /* Only resume if successful. */
1324 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1325 goto ResumeExecution;
1326 }
1327 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1328 break;
1329 }
1330
1331 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1332 case SVM_EXIT_IOIO: /* I/O instruction. */
1333 {
1334 SVM_IOIO_EXIT IoExitInfo;
1335 uint32_t uIOSize, uAndVal;
1336
1337 IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1338
1339 /** @todo could use a lookup table here */
1340 if (IoExitInfo.n.u1OP8)
1341 {
1342 uIOSize = 1;
1343 uAndVal = 0xff;
1344 }
1345 else
1346 if (IoExitInfo.n.u1OP16)
1347 {
1348 uIOSize = 2;
1349 uAndVal = 0xffff;
1350 }
1351 else
1352 if (IoExitInfo.n.u1OP32)
1353 {
1354 uIOSize = 4;
1355 uAndVal = 0xffffffff;
1356 }
1357 else
1358 {
1359 AssertFailed(); /* should be fatal. */
1360 rc = VINF_EM_RAW_EMULATE_INSTR;
1361 break;
1362 }
1363
1364 if (IoExitInfo.n.u1STR)
1365 {
1366 /* ins/outs */
1367 uint32_t prefix = 0;
1368 if (IoExitInfo.n.u1REP)
1369 prefix |= PREFIX_REP;
1370
1371 if (IoExitInfo.n.u1Type == 0)
1372 {
1373 Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1374 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1375 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1376 }
1377 else
1378 {
1379 Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1380 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1381 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1382 }
1383 }
1384 else
1385 {
1386 /* normal in/out */
1387 Assert(!IoExitInfo.n.u1REP);
1388
1389 if (IoExitInfo.n.u1Type == 0)
1390 {
1391 Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1392 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1393 rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1394 }
1395 else
1396 {
1397 uint32_t u32Val = 0;
1398
1399 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1400 rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1401 if (IOM_SUCCESS(rc))
1402 {
1403 /* Write back to the EAX register. */
1404 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
1405 Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1406 }
1407 }
1408 }
1409 /*
1410 * Handled the I/O return codes.
1411 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1412 */
1413 if (IOM_SUCCESS(rc))
1414 {
1415 /* Update EIP and continue execution. */
1416 pCtx->eip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1417 if (RT_LIKELY(rc == VINF_SUCCESS))
1418 {
1419 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1420 goto ResumeExecution;
1421 }
1422 Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize, rc));
1423 break;
1424 }
1425
1426#ifdef VBOX_STRICT
1427 if (rc == VINF_IOM_HC_IOPORT_READ)
1428 Assert(IoExitInfo.n.u1Type != 0);
1429 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1430 Assert(IoExitInfo.n.u1Type == 0);
1431 else
1432 AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1433#endif
1434 Log2(("Failed IO at %VGv %x size %d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1435 break;
1436 }
1437
1438 case SVM_EXIT_HLT:
1439 /** Check if external interrupts are pending; if so, don't switch back. */
1440 if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
1441 {
1442 pCtx->eip++; /* skip hlt */
1443 goto ResumeExecution;
1444 }
1445
1446 rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1447 break;
1448
1449 case SVM_EXIT_RDPMC:
1450 case SVM_EXIT_RSM:
1451 case SVM_EXIT_INVLPGA:
1452 case SVM_EXIT_VMRUN:
1453 case SVM_EXIT_VMMCALL:
1454 case SVM_EXIT_VMLOAD:
1455 case SVM_EXIT_VMSAVE:
1456 case SVM_EXIT_STGI:
1457 case SVM_EXIT_CLGI:
1458 case SVM_EXIT_SKINIT:
1459 case SVM_EXIT_RDTSCP:
1460 {
1461 /* Unsupported instructions. */
1462 SVM_EVENT Event;
1463
1464 Event.au64[0] = 0;
1465 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1466 Event.n.u1Valid = 1;
1467 Event.n.u8Vector = X86_XCPT_UD;
1468
1469 Log(("Forced #UD trap at %VGv\n", pCtx->eip));
1470 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1471
1472 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1473 goto ResumeExecution;
1474 }
1475
1476 /* Emulate RDMSR & WRMSR in ring 3. */
1477 case SVM_EXIT_MSR:
1478 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1479 break;
1480
1481 case SVM_EXIT_NPF:
1482 AssertFailed(); /* unexpected */
1483 break;
1484
1485 case SVM_EXIT_SHUTDOWN:
1486 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1487 break;
1488
1489 case SVM_EXIT_PAUSE:
1490 case SVM_EXIT_IDTR_READ:
1491 case SVM_EXIT_GDTR_READ:
1492 case SVM_EXIT_LDTR_READ:
1493 case SVM_EXIT_TR_READ:
1494 case SVM_EXIT_IDTR_WRITE:
1495 case SVM_EXIT_GDTR_WRITE:
1496 case SVM_EXIT_LDTR_WRITE:
1497 case SVM_EXIT_TR_WRITE:
1498 case SVM_EXIT_CR0_SEL_WRITE:
1499 default:
1500 /* Unexpected exit codes. */
1501 rc = VERR_EM_INTERNAL_ERROR;
1502 AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1503 break;
1504 }
1505
1506end:
1507 if (fGuestStateSynced)
1508 {
1509 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1510 SVM_READ_SELREG(LDTR, ldtr);
1511 SVM_READ_SELREG(TR, tr);
1512
1513 pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1514 pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1515
1516 pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1517 pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1518
1519 /*
1520 * System MSRs
1521 */
1522 pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1523 pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1524 pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1525 }
1526
1527 /* Signal changes for the recompiler. */
1528 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
1529
1530 /* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1531 if (exitCode == SVM_EXIT_INTR)
1532 {
1533 STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1534 /* On the next entry we'll only sync the host context. */
1535 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
1536 }
1537 else
1538 {
1539 /* On the next entry we'll sync everything. */
1540 /** @todo we can do better than this */
1541 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
1542 }
1543
1544 /* translate into a less severe return code */
1545 if (rc == VERR_EM_INTERPRETER)
1546 rc = VINF_EM_RAW_EMULATE_INSTR;
1547
1548 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1549 return rc;
1550}
1551
1552/**
1553 * Enters the AMD-V session
1554 *
1555 * @returns VBox status code.
1556 * @param pVM The VM to operate on.
1557 */
1558HWACCMR0DECL(int) SVMR0Enter(PVM pVM)
1559{
1560 Assert(pVM->hwaccm.s.svm.fSupported);
1561
1562 /* Force a TLB flush on VM entry. */
1563 pVM->hwaccm.s.svm.fResumeVM = false;
1564
1565 /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1566 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_LDTR;
1567
1568 return VINF_SUCCESS;
1569}
1570
1571
1572/**
1573 * Leaves the AMD-V session
1574 *
1575 * @returns VBox status code.
1576 * @param pVM The VM to operate on.
1577 */
1578HWACCMR0DECL(int) SVMR0Leave(PVM pVM)
1579{
1580 Assert(pVM->hwaccm.s.svm.fSupported);
1581 return VINF_SUCCESS;
1582}
1583
1584
1585static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1586{
1587 OP_PARAMVAL param1;
1588 RTGCPTR addr;
1589
1590 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1591 if(VBOX_FAILURE(rc))
1592 return VERR_EM_INTERPRETER;
1593
1594 switch(param1.type)
1595 {
1596 case PARMTYPE_IMMEDIATE:
1597 case PARMTYPE_ADDRESS:
1598 if(!(param1.flags & PARAM_VAL32))
1599 return VERR_EM_INTERPRETER;
1600 addr = (RTGCPTR)param1.val.val32;
1601 break;
1602
1603 default:
1604 return VERR_EM_INTERPRETER;
1605 }
1606
1607 /** @todo is addr always a flat linear address or ds based
1608 * (in absence of segment override prefixes)????
1609 */
1610 rc = PGMInvalidatePage(pVM, addr);
1611 if (VBOX_SUCCESS(rc))
1612 {
1613 /* Manually invalidate the page for the VM's TLB. */
1614 SVMInvlpgA(addr, uASID);
1615 return VINF_SUCCESS;
1616 }
1617 /** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1618 return VERR_EM_INTERPRETER;
1619}
1620
1621/**
1622 * Interprets INVLPG
1623 *
1624 * @returns VBox status code.
1625 * @retval VINF_* Scheduling instructions.
1626 * @retval VERR_EM_INTERPRETER Something we can't cope with.
1627 * @retval VERR_* Fatal errors.
1628 *
1629 * @param pVM The VM handle.
1630 * @param pRegFrame The register frame.
1631 * @param ASID Tagged TLB id for the guest
1632 *
1633 * Updates the EIP if an instruction was executed successfully.
1634 */
1635static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1636{
1637 /*
1638 * Only allow 32-bit code.
1639 */
1640 if (SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
1641 {
1642 RTGCPTR pbCode;
1643 int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pbCode);
1644 if (VBOX_SUCCESS(rc))
1645 {
1646 uint32_t cbOp;
1647 DISCPUSTATE Cpu;
1648
1649 Cpu.mode = CPUMODE_32BIT;
1650 rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1651 Assert(VBOX_FAILURE(rc) || Cpu.pCurInstr->opcode == OP_INVLPG);
1652 if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1653 {
1654 Assert(cbOp == Cpu.opsize);
1655 rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1656 if (VBOX_SUCCESS(rc))
1657 {
1658 pRegFrame->eip += cbOp; /* Move on to the next instruction. */
1659 }
1660 return rc;
1661 }
1662 }
1663 }
1664 return VERR_EM_INTERPRETER;
1665}
1666
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