VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 7692

Last change on this file since 7692 was 7496, checked in by vboxsync, 17 years ago

Moved VMCS allocation to ring 0.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 64.8 KB
Line 
1/* $Id: HWSVMR0.cpp 7496 2008-03-19 10:22:50Z vboxsync $ */
2/** @file
3 * HWACCM SVM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 innotek GmbH
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_HWACCM
23#include <VBox/hwaccm.h>
24#include "HWACCMInternal.h"
25#include <VBox/vm.h>
26#include <VBox/x86.h>
27#include <VBox/hwacc_svm.h>
28#include <VBox/pgm.h>
29#include <VBox/pdm.h>
30#include <VBox/err.h>
31#include <VBox/log.h>
32#include <VBox/selm.h>
33#include <VBox/iom.h>
34#include <VBox/dis.h>
35#include <VBox/dbgf.h>
36#include <VBox/disopcode.h>
37#include <iprt/param.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include "HWSVMR0.h"
41
42static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
43
44/**
45 * Sets up and activates AMD-V on the current CPU
46 *
47 * @returns VBox status code.
48 * @param idCpu The identifier for the CPU the function is called on.
49 * @param pVM The VM to operate on.
50 * @param pvPageCpu Pointer to the global cpu page
51 * @param pPageCpuPhys Physical address of the global cpu page
52 */
53HWACCMR0DECL(int) SVMR0EnableCpu(RTCPUID idCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
54{
55 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
56 AssertReturn(pVM, VERR_INVALID_PARAMETER);
57 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
58
59 /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
60
61 /* Turn on AMD-V in the EFER MSR. */
62 uint64_t val = ASMRdMsr(MSR_K6_EFER);
63 if (!(val & MSR_K6_EFER_SVME))
64 ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);
65
66 /* Write the physical page address where the CPU will store the host state while executing the VM. */
67 ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
68 return VINF_SUCCESS;
69}
70
71/**
72 * Deactivates AMD-V on the current CPU
73 *
74 * @returns VBox status code.
75 * @param idCpu The identifier for the CPU the function is called on.
76 * @param pvPageCpu Pointer to the global cpu page
77 * @param pPageCpuPhys Physical address of the global cpu page
78 */
79HWACCMR0DECL(int) SVMR0DisableCpu(RTCPUID idCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
80{
81 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
82 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
83
84 /* Turn off AMD-V in the EFER MSR. */
85 uint64_t val = ASMRdMsr(MSR_K6_EFER);
86 ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
87
88 /* Invalidate host state physical address. */
89 ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
90 return VINF_SUCCESS;
91}
92
93/**
94 * Does Ring-0 per VM AMD-V init.
95 *
96 * @returns VBox status code.
97 * @param pVM The VM to operate on.
98 */
99HWACCMR0DECL(int) SVMR0InitVM(PVM pVM)
100{
101 int rc;
102
103 /* Allocate one page for the VM control block (VMCB). */
104 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
105 if (RT_FAILURE(rc))
106 return rc;
107
108 pVM->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCB);
109 pVM->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCB, 0);
110 ASMMemZero32(pVM->hwaccm.s.svm.pVMCB, PAGE_SIZE);
111
112 /* Allocate one page for the host context */
113 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
114 if (RT_FAILURE(rc))
115 return rc;
116
117 pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
118 pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
119 ASMMemZero32(pVM->hwaccm.s.svm.pVMCBHost, PAGE_SIZE);
120
121 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
122 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
123 if (RT_FAILURE(rc))
124 return rc;
125
126 pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
127 pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
128 /* Set all bits to intercept all IO accesses. */
129 ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
130
131 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
132 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
133 if (RT_FAILURE(rc))
134 return rc;
135
136 pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
137 pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
138 /* Set all bits to intercept all MSR accesses. */
139 ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
140
141 return VINF_SUCCESS;
142}
143
144/**
145 * Does Ring-0 per VM AMD-V termination.
146 *
147 * @returns VBox status code.
148 * @param pVM The VM to operate on.
149 */
150HWACCMR0DECL(int) SVMR0TermVM(PVM pVM)
151{
152 if (pVM->hwaccm.s.svm.pMemObjVMCB)
153 {
154 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCB, false);
155 pVM->hwaccm.s.svm.pVMCB = 0;
156 pVM->hwaccm.s.svm.pVMCBPhys = 0;
157 pVM->hwaccm.s.svm.pMemObjVMCB = 0;
158 }
159 if (pVM->hwaccm.s.svm.pMemObjVMCBHost)
160 {
161 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
162 pVM->hwaccm.s.svm.pVMCBHost = 0;
163 pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
164 pVM->hwaccm.s.svm.pMemObjVMCBHost = 0;
165 }
166 if (pVM->hwaccm.s.svm.pMemObjIOBitmap)
167 {
168 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
169 pVM->hwaccm.s.svm.pIOBitmap = 0;
170 pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
171 pVM->hwaccm.s.svm.pMemObjIOBitmap = 0;
172 }
173 if (pVM->hwaccm.s.svm.pMemObjMSRBitmap)
174 {
175 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
176 pVM->hwaccm.s.svm.pMSRBitmap = 0;
177 pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
178 pVM->hwaccm.s.svm.pMemObjMSRBitmap = 0;
179 }
180 return VINF_SUCCESS;
181}
182
183/**
184 * Sets up AMD-V for the specified VM
185 *
186 * @returns VBox status code.
187 * @param pVM The VM to operate on.
188 */
189HWACCMR0DECL(int) SVMR0SetupVM(PVM pVM)
190{
191 int rc = VINF_SUCCESS;
192 SVM_VMCB *pVMCB;
193
194 AssertReturn(pVM, VERR_INVALID_PARAMETER);
195
196 Assert(pVM->hwaccm.s.svm.fSupported);
197
198 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
199 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
200
201 /* Program the control fields. Most of them never have to be changed again. */
202 /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
203 /** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
204 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4) | RT_BIT(8);
205
206 /*
207 * CR0/3/4 writes must be intercepted for obvious reasons.
208 */
209 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4) | RT_BIT(8);
210
211 /* Intercept all DRx reads and writes. */
212 pVMCB->ctrl.u16InterceptRdDRx = RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7);
213 pVMCB->ctrl.u16InterceptWrDRx = RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7);
214
215 /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
216 * All breakpoints are automatically cleared when the VM exits.
217 */
218
219 /** @todo nested paging */
220 /* Intercept #NM only; #PF is not relevant due to nested paging (we get a seperate exit code (SVM_EXIT_NPF) for
221 * pagefaults that need our attention).
222 */
223 pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
224
225 pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
226 | SVM_CTRL1_INTERCEPT_VINTR
227 | SVM_CTRL1_INTERCEPT_NMI
228 | SVM_CTRL1_INTERCEPT_SMI
229 | SVM_CTRL1_INTERCEPT_INIT
230 | SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
231 | SVM_CTRL1_INTERCEPT_RDPMC
232 | SVM_CTRL1_INTERCEPT_CPUID
233 | SVM_CTRL1_INTERCEPT_RSM
234 | SVM_CTRL1_INTERCEPT_HLT
235 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP
236 | SVM_CTRL1_INTERCEPT_MSR_SHADOW
237 | SVM_CTRL1_INTERCEPT_INVLPG
238 | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
239 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
240 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
241 ;
242 pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
243 | SVM_CTRL2_INTERCEPT_VMMCALL
244 | SVM_CTRL2_INTERCEPT_VMLOAD
245 | SVM_CTRL2_INTERCEPT_VMSAVE
246 | SVM_CTRL2_INTERCEPT_STGI
247 | SVM_CTRL2_INTERCEPT_CLGI
248 | SVM_CTRL2_INTERCEPT_SKINIT
249 | SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
250 ;
251 Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
252 Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
253 Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
254
255 /* Virtualize masking of INTR interrupts. */
256 pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
257
258 /* Set IO and MSR bitmap addresses. */
259 pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
260 pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
261
262 /* Enable nested paging. */
263 /** @todo how to detect support for this?? */
264 pVMCB->ctrl.u64NestedPaging = 0; /** @todo SVM_NESTED_PAGING_ENABLE; */
265
266 /* No LBR virtualization. */
267 pVMCB->ctrl.u64LBRVirt = 0;
268
269 return rc;
270}
271
272
273/**
274 * Injects an event (trap or external interrupt)
275 *
276 * @param pVM The VM to operate on.
277 * @param pVMCB SVM control block
278 * @param pCtx CPU Context
279 * @param pIntInfo SVM interrupt info
280 */
281inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)
282{
283#ifdef VBOX_STRICT
284 if (pEvent->n.u8Vector == 0xE)
285 Log(("SVM: Inject int %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
286 else
287 if (pEvent->n.u8Vector < 0x20)
288 Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode));
289 else
290 {
291 Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->eip));
292 Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
293 Assert(pCtx->eflags.u32 & X86_EFL_IF);
294 }
295#endif
296
297 /* Set event injection state. */
298 pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
299}
300
301
302/**
303 * Checks for pending guest interrupts and injects them
304 *
305 * @returns VBox status code.
306 * @param pVM The VM to operate on.
307 * @param pVMCB SVM control block
308 * @param pCtx CPU Context
309 */
310static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
311{
312 int rc;
313
314 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
315 if (pVM->hwaccm.s.Event.fPending)
316 {
317 SVM_EVENT Event;
318
319 Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
320 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
321 Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
322 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
323
324 pVM->hwaccm.s.Event.fPending = false;
325 return VINF_SUCCESS;
326 }
327
328 /* When external interrupts are pending, we should exit the VM when IF is set. */
329 if ( !TRPMHasTrap(pVM)
330 && VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
331 {
332 if (!(pCtx->eflags.u32 & X86_EFL_IF))
333 {
334 Log2(("Enable irq window exit!\n"));
335 /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
336//// pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
337//// AssertRC(rc);
338 }
339 else
340 if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
341 {
342 uint8_t u8Interrupt;
343
344 rc = PDMGetInterrupt(pVM, &u8Interrupt);
345 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
346 if (VBOX_SUCCESS(rc))
347 {
348 rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
349 AssertRC(rc);
350 }
351 else
352 {
353 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
354 Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)));
355 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
356 /* Just continue */
357 }
358 }
359 else
360 Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
361 }
362
363#ifdef VBOX_STRICT
364 if (TRPMHasTrap(pVM))
365 {
366 uint8_t u8Vector;
367 rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
368 AssertRC(rc);
369 }
370#endif
371
372 if ( pCtx->eflags.u32 & X86_EFL_IF
373 && (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
374 && TRPMHasTrap(pVM)
375 )
376 {
377 uint8_t u8Vector;
378 int rc;
379 TRPMEVENT enmType;
380 SVM_EVENT Event;
381 uint32_t u32ErrorCode;
382
383 Event.au64[0] = 0;
384
385 /* If a new event is pending, then dispatch it now. */
386 rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
387 AssertRC(rc);
388 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
389 Assert(enmType != TRPM_SOFTWARE_INT);
390
391 /* Clear the pending trap. */
392 rc = TRPMResetTrap(pVM);
393 AssertRC(rc);
394
395 Event.n.u8Vector = u8Vector;
396 Event.n.u1Valid = 1;
397 Event.n.u32ErrorCode = u32ErrorCode;
398
399 if (enmType == TRPM_TRAP)
400 {
401 switch (u8Vector) {
402 case 8:
403 case 10:
404 case 11:
405 case 12:
406 case 13:
407 case 14:
408 case 17:
409 /* Valid error codes. */
410 Event.n.u1ErrorCodeValid = 1;
411 break;
412 default:
413 break;
414 }
415 if (u8Vector == X86_XCPT_NMI)
416 Event.n.u3Type = SVM_EVENT_NMI;
417 else
418 Event.n.u3Type = SVM_EVENT_EXCEPTION;
419 }
420 else
421 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
422
423 STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
424 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
425 } /* if (interrupts can be dispatched) */
426
427 return VINF_SUCCESS;
428}
429
430
431/**
432 * Loads the guest state
433 *
434 * @returns VBox status code.
435 * @param pVM The VM to operate on.
436 * @param pCtx Guest context
437 */
438HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
439{
440 RTGCUINTPTR val;
441 SVM_VMCB *pVMCB;
442
443 if (pVM == NULL)
444 return VERR_INVALID_PARAMETER;
445
446 /* Setup AMD SVM. */
447 Assert(pVM->hwaccm.s.svm.fSupported);
448
449 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
450 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
451
452 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
453 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
454 {
455 SVM_WRITE_SELREG(CS, cs);
456 SVM_WRITE_SELREG(SS, ss);
457 SVM_WRITE_SELREG(DS, ds);
458 SVM_WRITE_SELREG(ES, es);
459 SVM_WRITE_SELREG(FS, fs);
460 SVM_WRITE_SELREG(GS, gs);
461 }
462
463 /* Guest CPU context: LDTR. */
464 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
465 {
466 SVM_WRITE_SELREG(LDTR, ldtr);
467 }
468
469 /* Guest CPU context: TR. */
470 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
471 {
472 SVM_WRITE_SELREG(TR, tr);
473 }
474
475 /* Guest CPU context: GDTR. */
476 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
477 {
478 pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
479 pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
480 }
481
482 /* Guest CPU context: IDTR. */
483 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
484 {
485 pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
486 pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
487 }
488
489 /*
490 * Sysenter MSRs
491 */
492 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
493 {
494 pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
495 pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
496 pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
497 }
498
499 /* Control registers */
500 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
501 {
502 val = pCtx->cr0;
503 if (CPUMIsGuestFPUStateActive(pVM) == false)
504 {
505 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
506 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
507 }
508 else
509 {
510 Assert(pVM->hwaccm.s.svm.fResumeVM == true);
511 /** @todo check if we support the old style mess correctly. */
512 if (!(val & X86_CR0_NE))
513 {
514 Log(("Forcing X86_CR0_NE!!!\n"));
515
516 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
517 if (!pVM->hwaccm.s.fFPUOldStyleOverride)
518 {
519 pVMCB->ctrl.u32InterceptException |= RT_BIT(16);
520 pVM->hwaccm.s.fFPUOldStyleOverride = true;
521 }
522 }
523 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
524 }
525 if (!(val & X86_CR0_CD))
526 val &= ~X86_CR0_NW; /* Illegal when cache is turned on. */
527
528 val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
529 pVMCB->guest.u64CR0 = val;
530 }
531 /* CR2 as well */
532 pVMCB->guest.u64CR2 = pCtx->cr2;
533
534 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
535 {
536 /* Save our shadow CR3 register. */
537 pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
538 }
539
540 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
541 {
542 val = pCtx->cr4;
543 switch(pVM->hwaccm.s.enmShadowMode)
544 {
545 case PGMMODE_REAL:
546 case PGMMODE_PROTECTED: /* Protected mode, no paging. */
547 AssertFailed();
548 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
549
550 case PGMMODE_32_BIT: /* 32-bit paging. */
551 break;
552
553 case PGMMODE_PAE: /* PAE paging. */
554 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
555 /** @todo use normal 32 bits paging */
556 val |= X86_CR4_PAE;
557 break;
558
559 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
560 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
561 AssertFailed();
562 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
563
564 default: /* shut up gcc */
565 AssertFailed();
566 return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
567 }
568 pVMCB->guest.u64CR4 = val;
569 }
570
571 /* Debug registers. */
572 if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
573 {
574 /** @todo DR0-6 */
575 val = pCtx->dr7;
576 val &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
577 val |= 0x400; /* must be one */
578#ifdef VBOX_STRICT
579 val = 0x400;
580#endif
581 pVMCB->guest.u64DR7 = val;
582
583 pVMCB->guest.u64DR6 = pCtx->dr6;
584 }
585
586 /* EIP, ESP and EFLAGS */
587 pVMCB->guest.u64RIP = pCtx->eip;
588 pVMCB->guest.u64RSP = pCtx->esp;
589 pVMCB->guest.u64RFlags = pCtx->eflags.u32;
590
591 /* Set CPL */
592 pVMCB->guest.u8CPL = pCtx->ssHid.Attr.n.u2Dpl;
593
594 /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
595 pVMCB->guest.u64RAX = pCtx->eax;
596
597 /* vmrun will fail otherwise. */
598 pVMCB->guest.u64EFER = MSR_K6_EFER_SVME;
599
600 /** @note We can do more complex things with tagged TLBs. */
601 pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
602
603 /** TSC offset. */
604 if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
605 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
606 else
607 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
608
609 /** @todo 64 bits stuff (?):
610 * - STAR
611 * - LSTAR
612 * - CSTAR
613 * - SFMASK
614 * - KernelGSBase
615 */
616
617#ifdef DEBUG
618 /* Intercept X86_XCPT_DB if stepping is enabled */
619 if (DBGFIsStepping(pVM))
620 pVMCB->ctrl.u32InterceptException |= RT_BIT(1);
621 else
622 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(1);
623#endif
624
625 /* Done. */
626 pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
627
628 return VINF_SUCCESS;
629}
630
631
632/**
633 * Runs guest code in an SVM VM.
634 *
635 * @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
636 *
637 * @returns VBox status code.
638 * @param pVM The VM to operate on.
639 * @param pCtx Guest context
640 */
641HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
642{
643 int rc = VINF_SUCCESS;
644 uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
645 SVM_VMCB *pVMCB;
646 bool fForceTLBFlush = false;
647 bool fGuestStateSynced = false;
648 unsigned cResume = 0;
649
650 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
651
652 pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
653 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
654
655 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
656 */
657ResumeExecution:
658 /* Safety precaution; looping for too long here can have a very bad effect on the host */
659 if (++cResume > HWACCM_MAX_RESUME_LOOPS)
660 {
661 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
662 rc = VINF_EM_RAW_INTERRUPT;
663 goto end;
664 }
665
666 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
667 if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
668 {
669 Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
670 if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
671 {
672 /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
673 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
674 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
675 * break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
676 */
677 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
678 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
679 pVMCB->ctrl.u64IntShadow = 0;
680 }
681 }
682 else
683 {
684 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
685 pVMCB->ctrl.u64IntShadow = 0;
686 }
687
688 /* Check for pending actions that force us to go back to ring 3. */
689#ifdef DEBUG
690 /* Intercept X86_XCPT_DB if stepping is enabled */
691 if (!DBGFIsStepping(pVM))
692#endif
693 {
694 if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 | VM_FF_TIMER))
695 {
696 VM_FF_CLEAR(pVM, VM_FF_TO_R3);
697 STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
698 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
699 rc = VINF_EM_RAW_TO_R3;
700 goto end;
701 }
702 }
703
704 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
705 if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
706 {
707 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
708 rc = VINF_EM_PENDING_REQUEST;
709 goto end;
710 }
711
712 /* When external interrupts are pending, we should exit the VM when IF is set. */
713 /** @note *after* VM_FF_INHIBIT_INTERRUPTS check!!! */
714 rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
715 if (VBOX_FAILURE(rc))
716 {
717 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
718 goto end;
719 }
720
721 /* Load the guest state */
722 rc = SVMR0LoadGuestState(pVM, pCtx);
723 if (rc != VINF_SUCCESS)
724 {
725 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
726 goto end;
727 }
728 fGuestStateSynced = true;
729
730 /* All done! Let's start VM execution. */
731 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
732
733 /** Erratum #170 -> must force a TLB flush */
734 /** @todo supposed to be fixed in future by AMD */
735 fForceTLBFlush = true;
736
737 if ( pVM->hwaccm.s.svm.fResumeVM == false
738 || fForceTLBFlush)
739 {
740 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1;
741 }
742 else
743 {
744 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 0;
745 }
746 /* In case we execute a goto ResumeExecution later on. */
747 pVM->hwaccm.s.svm.fResumeVM = true;
748 fForceTLBFlush = false;
749
750 Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
751 Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
752 | SVM_CTRL2_INTERCEPT_VMMCALL
753 | SVM_CTRL2_INTERCEPT_VMLOAD
754 | SVM_CTRL2_INTERCEPT_VMSAVE
755 | SVM_CTRL2_INTERCEPT_STGI
756 | SVM_CTRL2_INTERCEPT_CLGI
757 | SVM_CTRL2_INTERCEPT_SKINIT
758 | SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
759 ));
760 Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
761 Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
762 Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
763 Assert(pVMCB->ctrl.u64NestedPaging == 0);
764 Assert(pVMCB->ctrl.u64LBRVirt == 0);
765
766 SVMVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
767 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
768
769 /**
770 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
771 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
772 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
773 */
774
775 STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
776
777 /* Reason for the VM exit */
778 exitCode = pVMCB->ctrl.u64ExitCode;
779
780 if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
781 {
782 HWACCMDumpRegs(pCtx);
783#ifdef DEBUG
784 Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
785 Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
786 Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
787 Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
788 Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
789 Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
790 Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
791 Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
792 Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
793 Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
794
795 Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
796 Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
797 Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
798 Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
799
800 Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
801 Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
802 Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
803 Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
804 Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
805 Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
806 Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
807 Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
808 Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
809 Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
810
811 Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
812 Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
813 Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
814 Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
815 Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
816 Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
817 Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
818 Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
819 Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
820 Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
821 Log(("ctrl.u64NestedPaging %VX64\n", pVMCB->ctrl.u64NestedPaging));
822 Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
823 Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
824 Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
825 Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
826 Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
827 Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
828
829 Log(("ctrl.u64HostCR3 %VX64\n", pVMCB->ctrl.u64HostCR3));
830 Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
831
832 Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
833 Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
834 Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
835 Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
836 Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
837 Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
838 Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
839 Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
840 Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
841 Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
842 Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
843 Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
844 Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
845 Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
846 Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
847 Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
848 Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
849 Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
850 Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
851 Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
852
853 Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
854 Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
855
856 Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
857 Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
858 Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
859 Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
860
861 Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
862 Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
863
864 Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
865 Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
866 Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
867 Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
868
869 Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
870 Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
871 Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
872 Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
873 Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
874 Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
875 Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
876
877 Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
878 Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
879 Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
880 Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
881
882 Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
883 Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
884 Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
885
886 Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
887 Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
888 Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
889 Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
890 Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
891 Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
892 Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
893 Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
894 Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
895 Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
896 Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
897 Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
898
899#endif
900 rc = VERR_SVM_UNABLE_TO_START_VM;
901 goto end;
902 }
903
904 /* Let's first sync back eip, esp, and eflags. */
905 pCtx->eip = pVMCB->guest.u64RIP;
906 pCtx->esp = pVMCB->guest.u64RSP;
907 pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
908 /* eax is saved/restore across the vmrun instruction */
909 pCtx->eax = pVMCB->guest.u64RAX;
910
911 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
912 SVM_READ_SELREG(SS, ss);
913 SVM_READ_SELREG(CS, cs);
914 SVM_READ_SELREG(DS, ds);
915 SVM_READ_SELREG(ES, es);
916 SVM_READ_SELREG(FS, fs);
917 SVM_READ_SELREG(GS, gs);
918
919 /** @note no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
920
921 /** @note NOW IT'S SAFE FOR LOGGING! */
922
923 /* Take care of instruction fusing (sti, mov ss) */
924 if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
925 {
926 Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->eip));
927 EMSetInhibitInterruptsPC(pVM, pCtx->eip);
928 }
929 else
930 VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
931
932 Log2(("exitCode = %x\n", exitCode));
933
934 /* Check if an injected event was interrupted prematurely. */
935 pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
936 if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
937 && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
938 {
939 Log(("Pending inject %VX64 at %08x exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitCode));
940 pVM->hwaccm.s.Event.fPending = true;
941 /* Error code present? (redundant) */
942 if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
943 {
944 pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
945 }
946 else
947 pVM->hwaccm.s.Event.errCode = 0;
948 }
949 STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
950
951 /* Deal with the reason of the VM-exit. */
952 switch (exitCode)
953 {
954 case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
955 case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
956 case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
957 case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
958 case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
959 case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
960 case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
961 case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
962 {
963 /* Pending trap. */
964 SVM_EVENT Event;
965 uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
966
967 Log2(("Hardware/software interrupt %d\n", vector));
968 switch (vector)
969 {
970#ifdef DEBUG
971 case X86_XCPT_DB:
972 rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pVMCB->guest.u64DR6);
973 Assert(rc != VINF_EM_RAW_GUEST_TRAP);
974 break;
975#endif
976
977 case X86_XCPT_NM:
978 {
979 uint32_t oldCR0;
980
981 Log(("#NM fault at %VGv\n", pCtx->eip));
982
983 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
984 oldCR0 = ASMGetCR0();
985 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
986 rc = CPUMHandleLazyFPU(pVM);
987 if (rc == VINF_SUCCESS)
988 {
989 Assert(CPUMIsGuestFPUStateActive(pVM));
990
991 /* CPUMHandleLazyFPU could have changed CR0; restore it. */
992 ASMSetCR0(oldCR0);
993
994 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
995
996 /* Continue execution. */
997 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
998 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
999
1000 goto ResumeExecution;
1001 }
1002
1003 Log(("Forward #NM fault to the guest\n"));
1004 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1005
1006 Event.au64[0] = 0;
1007 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1008 Event.n.u1Valid = 1;
1009 Event.n.u8Vector = X86_XCPT_NM;
1010
1011 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1012 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1013 goto ResumeExecution;
1014 }
1015
1016 case X86_XCPT_PF: /* Page fault */
1017 {
1018 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1019 RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1020
1021 Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
1022 /* Exit qualification contains the linear address of the page fault. */
1023 TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1024 TRPMSetErrorCode(pVM, errCode);
1025 TRPMSetFaultAddress(pVM, uFaultAddress);
1026
1027 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1028 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1029 Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
1030 if (rc == VINF_SUCCESS)
1031 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1032 Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
1033 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1034
1035 TRPMResetTrap(pVM);
1036
1037 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1038 goto ResumeExecution;
1039 }
1040 else
1041 if (rc == VINF_EM_RAW_GUEST_TRAP)
1042 { /* A genuine pagefault.
1043 * Forward the trap to the guest by injecting the exception and resuming execution.
1044 */
1045 Log2(("Forward page fault to the guest\n"));
1046 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1047 /* The error code might have been changed. */
1048 errCode = TRPMGetErrorCode(pVM);
1049
1050 TRPMResetTrap(pVM);
1051
1052 /* Now we must update CR2. */
1053 pCtx->cr2 = uFaultAddress;
1054
1055 Event.au64[0] = 0;
1056 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1057 Event.n.u1Valid = 1;
1058 Event.n.u8Vector = X86_XCPT_PF;
1059 Event.n.u1ErrorCodeValid = 1;
1060 Event.n.u32ErrorCode = errCode;
1061
1062 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1063
1064 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1065 goto ResumeExecution;
1066 }
1067#ifdef VBOX_STRICT
1068 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1069 Log(("PGMTrap0eHandler failed with %d\n", rc));
1070#endif
1071 /* Need to go back to the recompiler to emulate the instruction. */
1072 TRPMResetTrap(pVM);
1073 break;
1074 }
1075
1076 case X86_XCPT_MF: /* Floating point exception. */
1077 {
1078 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1079 if (!(pCtx->cr0 & X86_CR0_NE))
1080 {
1081 /* old style FPU error reporting needs some extra work. */
1082 /** @todo don't fall back to the recompiler, but do it manually. */
1083 rc = VINF_EM_RAW_EMULATE_INSTR;
1084 break;
1085 }
1086 Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1087
1088 Event.au64[0] = 0;
1089 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1090 Event.n.u1Valid = 1;
1091 Event.n.u8Vector = X86_XCPT_MF;
1092
1093 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1094
1095 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1096 goto ResumeExecution;
1097 }
1098
1099#ifdef VBOX_STRICT
1100 case X86_XCPT_GP: /* General protection failure exception.*/
1101 case X86_XCPT_UD: /* Unknown opcode exception. */
1102 case X86_XCPT_DE: /* Debug exception. */
1103 case X86_XCPT_SS: /* Stack segment exception. */
1104 case X86_XCPT_NP: /* Segment not present exception. */
1105 {
1106 Event.au64[0] = 0;
1107 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1108 Event.n.u1Valid = 1;
1109 Event.n.u8Vector = vector;
1110
1111 switch(vector)
1112 {
1113 case X86_XCPT_GP:
1114 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1115 Event.n.u1ErrorCodeValid = 1;
1116 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1117 break;
1118 case X86_XCPT_DE:
1119 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1120 break;
1121 case X86_XCPT_UD:
1122 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1123 break;
1124 case X86_XCPT_SS:
1125 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1126 Event.n.u1ErrorCodeValid = 1;
1127 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1128 break;
1129 case X86_XCPT_NP:
1130 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1131 Event.n.u1ErrorCodeValid = 1;
1132 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1133 break;
1134 }
1135 Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1136 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1137
1138 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1139 goto ResumeExecution;
1140 }
1141#endif
1142 default:
1143 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1144 rc = VERR_EM_INTERNAL_ERROR;
1145 break;
1146
1147 } /* switch (vector) */
1148 break;
1149 }
1150
1151 case SVM_EXIT_FERR_FREEZE:
1152 case SVM_EXIT_INTR:
1153 case SVM_EXIT_NMI:
1154 case SVM_EXIT_SMI:
1155 case SVM_EXIT_INIT:
1156 case SVM_EXIT_VINTR:
1157 /* External interrupt; leave to allow it to be dispatched again. */
1158 rc = VINF_EM_RAW_INTERRUPT;
1159 break;
1160
1161 case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1162 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1163 /* Skip instruction and continue directly. */
1164 pCtx->eip += 2; /** @note hardcoded opcode size! */
1165 /* Continue execution.*/
1166 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1167 goto ResumeExecution;
1168
1169 case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1170 {
1171 Log2(("SVM: Cpuid %x\n", pCtx->eax));
1172 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1173 rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1174 if (rc == VINF_SUCCESS)
1175 {
1176 /* Update EIP and continue execution. */
1177 pCtx->eip += 2; /** @note hardcoded opcode size! */
1178 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1179 goto ResumeExecution;
1180 }
1181 AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1182 rc = VINF_EM_RAW_EMULATE_INSTR;
1183 break;
1184 }
1185
1186 case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1187 {
1188 Log2(("SVM: Rdtsc\n"));
1189 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1190 rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1191 if (rc == VINF_SUCCESS)
1192 {
1193 /* Update EIP and continue execution. */
1194 pCtx->eip += 2; /** @note hardcoded opcode size! */
1195 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1196 goto ResumeExecution;
1197 }
1198 AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1199 rc = VINF_EM_RAW_EMULATE_INSTR;
1200 break;
1201 }
1202
1203 case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1204 {
1205 Log2(("SVM: invlpg\n"));
1206 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1207
1208 /* Truly a pita. Why can't SVM give the same information as VMX? */
1209 rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1210 if (rc == VINF_SUCCESS)
1211 goto ResumeExecution; /* eip already updated */
1212 break;
1213 }
1214
1215 case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1216 case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1217 case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1218 case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1219 {
1220 uint32_t cbSize;
1221
1222 Log2(("SVM: %VGv mov cr%d, \n", pCtx->eip, exitCode - SVM_EXIT_WRITE_CR0));
1223 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1224 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1225
1226 switch (exitCode - SVM_EXIT_WRITE_CR0)
1227 {
1228 case 0:
1229 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1230 break;
1231 case 2:
1232 break;
1233 case 3:
1234 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
1235 break;
1236 case 4:
1237 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
1238 break;
1239 default:
1240 AssertFailed();
1241 }
1242 /* Check if a sync operation is pending. */
1243 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1244 && VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1245 {
1246 rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1247 AssertRC(rc);
1248
1249 /** @note Force a TLB flush. SVM requires us to do it manually. */
1250 fForceTLBFlush = true;
1251 }
1252 if (rc == VINF_SUCCESS)
1253 {
1254 /* EIP has been updated already. */
1255
1256 /* Only resume if successful. */
1257 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1258 goto ResumeExecution;
1259 }
1260 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1261 break;
1262 }
1263
1264 case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1265 case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1266 case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1267 case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1268 {
1269 uint32_t cbSize;
1270
1271 Log2(("SVM: %VGv mov x, cr%d\n", pCtx->eip, exitCode - SVM_EXIT_READ_CR0));
1272 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1273 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1274 if (rc == VINF_SUCCESS)
1275 {
1276 /* EIP has been updated already. */
1277
1278 /* Only resume if successful. */
1279 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1280 goto ResumeExecution;
1281 }
1282 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1283 break;
1284 }
1285
1286 case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1287 case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1288 case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1289 case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1290 {
1291 uint32_t cbSize;
1292
1293 Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_WRITE_DR0));
1294 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1295 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1296 if (rc == VINF_SUCCESS)
1297 {
1298 /* EIP has been updated already. */
1299
1300 /* Only resume if successful. */
1301 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1302 goto ResumeExecution;
1303 }
1304 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1305 break;
1306 }
1307
1308 case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1309 case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1310 case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1311 case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1312 {
1313 uint32_t cbSize;
1314
1315 Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_READ_DR0));
1316 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1317 rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1318 if (rc == VINF_SUCCESS)
1319 {
1320 /* EIP has been updated already. */
1321
1322 /* Only resume if successful. */
1323 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1324 goto ResumeExecution;
1325 }
1326 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
1327 break;
1328 }
1329
1330 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1331 case SVM_EXIT_IOIO: /* I/O instruction. */
1332 {
1333 SVM_IOIO_EXIT IoExitInfo;
1334 uint32_t uIOSize, uAndVal;
1335
1336 IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1337
1338 /** @todo could use a lookup table here */
1339 if (IoExitInfo.n.u1OP8)
1340 {
1341 uIOSize = 1;
1342 uAndVal = 0xff;
1343 }
1344 else
1345 if (IoExitInfo.n.u1OP16)
1346 {
1347 uIOSize = 2;
1348 uAndVal = 0xffff;
1349 }
1350 else
1351 if (IoExitInfo.n.u1OP32)
1352 {
1353 uIOSize = 4;
1354 uAndVal = 0xffffffff;
1355 }
1356 else
1357 {
1358 AssertFailed(); /* should be fatal. */
1359 rc = VINF_EM_RAW_EMULATE_INSTR;
1360 break;
1361 }
1362
1363 if (IoExitInfo.n.u1STR)
1364 {
1365 /* ins/outs */
1366 uint32_t prefix = 0;
1367 if (IoExitInfo.n.u1REP)
1368 prefix |= PREFIX_REP;
1369
1370 if (IoExitInfo.n.u1Type == 0)
1371 {
1372 Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1373 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1374 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1375 }
1376 else
1377 {
1378 Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1379 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1380 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1381 }
1382 }
1383 else
1384 {
1385 /* normal in/out */
1386 Assert(!IoExitInfo.n.u1REP);
1387
1388 if (IoExitInfo.n.u1Type == 0)
1389 {
1390 Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1391 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1392 rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1393 }
1394 else
1395 {
1396 uint32_t u32Val = 0;
1397
1398 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1399 rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1400 if (IOM_SUCCESS(rc))
1401 {
1402 /* Write back to the EAX register. */
1403 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
1404 Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1405 }
1406 }
1407 }
1408 /*
1409 * Handled the I/O return codes.
1410 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1411 */
1412 if (IOM_SUCCESS(rc))
1413 {
1414 /* Update EIP and continue execution. */
1415 pCtx->eip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1416 if (RT_LIKELY(rc == VINF_SUCCESS))
1417 {
1418 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1419 goto ResumeExecution;
1420 }
1421 Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize, rc));
1422 break;
1423 }
1424
1425#ifdef VBOX_STRICT
1426 if (rc == VINF_IOM_HC_IOPORT_READ)
1427 Assert(IoExitInfo.n.u1Type != 0);
1428 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1429 Assert(IoExitInfo.n.u1Type == 0);
1430 else
1431 AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1432#endif
1433 Log2(("Failed IO at %VGv %x size %d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
1434 break;
1435 }
1436
1437 case SVM_EXIT_HLT:
1438 /** Check if external interrupts are pending; if so, don't switch back. */
1439 if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
1440 {
1441 pCtx->eip++; /* skip hlt */
1442 goto ResumeExecution;
1443 }
1444
1445 rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1446 break;
1447
1448 case SVM_EXIT_RDPMC:
1449 case SVM_EXIT_RSM:
1450 case SVM_EXIT_INVLPGA:
1451 case SVM_EXIT_VMRUN:
1452 case SVM_EXIT_VMMCALL:
1453 case SVM_EXIT_VMLOAD:
1454 case SVM_EXIT_VMSAVE:
1455 case SVM_EXIT_STGI:
1456 case SVM_EXIT_CLGI:
1457 case SVM_EXIT_SKINIT:
1458 case SVM_EXIT_RDTSCP:
1459 {
1460 /* Unsupported instructions. */
1461 SVM_EVENT Event;
1462
1463 Event.au64[0] = 0;
1464 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1465 Event.n.u1Valid = 1;
1466 Event.n.u8Vector = X86_XCPT_UD;
1467
1468 Log(("Forced #UD trap at %VGv\n", pCtx->eip));
1469 SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1470
1471 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1472 goto ResumeExecution;
1473 }
1474
1475 /* Emulate RDMSR & WRMSR in ring 3. */
1476 case SVM_EXIT_MSR:
1477 rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1478 break;
1479
1480 case SVM_EXIT_NPF:
1481 AssertFailed(); /* unexpected */
1482 break;
1483
1484 case SVM_EXIT_SHUTDOWN:
1485 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1486 break;
1487
1488 case SVM_EXIT_PAUSE:
1489 case SVM_EXIT_IDTR_READ:
1490 case SVM_EXIT_GDTR_READ:
1491 case SVM_EXIT_LDTR_READ:
1492 case SVM_EXIT_TR_READ:
1493 case SVM_EXIT_IDTR_WRITE:
1494 case SVM_EXIT_GDTR_WRITE:
1495 case SVM_EXIT_LDTR_WRITE:
1496 case SVM_EXIT_TR_WRITE:
1497 case SVM_EXIT_CR0_SEL_WRITE:
1498 default:
1499 /* Unexpected exit codes. */
1500 rc = VERR_EM_INTERNAL_ERROR;
1501 AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1502 break;
1503 }
1504
1505end:
1506 if (fGuestStateSynced)
1507 {
1508 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1509 SVM_READ_SELREG(LDTR, ldtr);
1510 SVM_READ_SELREG(TR, tr);
1511
1512 pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1513 pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1514
1515 pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1516 pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1517
1518 /*
1519 * System MSRs
1520 */
1521 pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1522 pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1523 pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1524 }
1525
1526 /* Signal changes for the recompiler. */
1527 CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
1528
1529 /* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1530 if (exitCode == SVM_EXIT_INTR)
1531 {
1532 STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1533 /* On the next entry we'll only sync the host context. */
1534 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
1535 }
1536 else
1537 {
1538 /* On the next entry we'll sync everything. */
1539 /** @todo we can do better than this */
1540 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
1541 }
1542
1543 /* translate into a less severe return code */
1544 if (rc == VERR_EM_INTERPRETER)
1545 rc = VINF_EM_RAW_EMULATE_INSTR;
1546
1547 STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1548 return rc;
1549}
1550
1551/**
1552 * Enters the AMD-V session
1553 *
1554 * @returns VBox status code.
1555 * @param pVM The VM to operate on.
1556 */
1557HWACCMR0DECL(int) SVMR0Enter(PVM pVM)
1558{
1559 Assert(pVM->hwaccm.s.svm.fSupported);
1560
1561 /* Force a TLB flush on VM entry. */
1562 pVM->hwaccm.s.svm.fResumeVM = false;
1563
1564 /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1565 pVM->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_LDTR;
1566
1567 return VINF_SUCCESS;
1568}
1569
1570
1571/**
1572 * Leaves the AMD-V session
1573 *
1574 * @returns VBox status code.
1575 * @param pVM The VM to operate on.
1576 */
1577HWACCMR0DECL(int) SVMR0Leave(PVM pVM)
1578{
1579 Assert(pVM->hwaccm.s.svm.fSupported);
1580 return VINF_SUCCESS;
1581}
1582
1583
1584static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1585{
1586 OP_PARAMVAL param1;
1587 RTGCPTR addr;
1588
1589 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1590 if(VBOX_FAILURE(rc))
1591 return VERR_EM_INTERPRETER;
1592
1593 switch(param1.type)
1594 {
1595 case PARMTYPE_IMMEDIATE:
1596 case PARMTYPE_ADDRESS:
1597 if(!(param1.flags & PARAM_VAL32))
1598 return VERR_EM_INTERPRETER;
1599 addr = (RTGCPTR)param1.val.val32;
1600 break;
1601
1602 default:
1603 return VERR_EM_INTERPRETER;
1604 }
1605
1606 /** @todo is addr always a flat linear address or ds based
1607 * (in absence of segment override prefixes)????
1608 */
1609 rc = PGMInvalidatePage(pVM, addr);
1610 if (VBOX_SUCCESS(rc))
1611 {
1612 /* Manually invalidate the page for the VM's TLB. */
1613 SVMInvlpgA(addr, uASID);
1614 return VINF_SUCCESS;
1615 }
1616 /** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1617 return VERR_EM_INTERPRETER;
1618}
1619
1620/**
1621 * Interprets INVLPG
1622 *
1623 * @returns VBox status code.
1624 * @retval VINF_* Scheduling instructions.
1625 * @retval VERR_EM_INTERPRETER Something we can't cope with.
1626 * @retval VERR_* Fatal errors.
1627 *
1628 * @param pVM The VM handle.
1629 * @param pRegFrame The register frame.
1630 * @param ASID Tagged TLB id for the guest
1631 *
1632 * Updates the EIP if an instruction was executed successfully.
1633 */
1634static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1635{
1636 /*
1637 * Only allow 32-bit code.
1638 */
1639 if (SELMIsSelector32Bit(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid))
1640 {
1641 RTGCPTR pbCode;
1642 int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pbCode);
1643 if (VBOX_SUCCESS(rc))
1644 {
1645 uint32_t cbOp;
1646 DISCPUSTATE Cpu;
1647
1648 Cpu.mode = CPUMODE_32BIT;
1649 rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1650 Assert(VBOX_FAILURE(rc) || Cpu.pCurInstr->opcode == OP_INVLPG);
1651 if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1652 {
1653 Assert(cbOp == Cpu.opsize);
1654 rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1655 if (VBOX_SUCCESS(rc))
1656 {
1657 pRegFrame->eip += cbOp; /* Move on to the next instruction. */
1658 }
1659 return rc;
1660 }
1661 }
1662 }
1663 return VERR_EM_INTERPRETER;
1664}
1665
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette