HWSVMR0.cpp@ 47627

Last change on this file since 47627 was 47513, checked in by vboxsync, 11 years ago
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1	/* $Id: HWSVMR0.cpp 47513 2013-08-01 16:35:12Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HM
22	#include <VBox/vmm/hm.h>
23	#include <VBox/vmm/pgm.h>
24	#include <VBox/vmm/selm.h>
25	#include <VBox/vmm/iom.h>
26	#include <VBox/vmm/dbgf.h>
27	#include <VBox/vmm/dbgftrace.h>
28	#include <VBox/vmm/tm.h>
29	#include <VBox/vmm/pdmapi.h>
30	#include "HMInternal.h"
31	#include <VBox/vmm/vm.h>
32	#include <VBox/vmm/hm_svm.h>
33	#include <VBox/err.h>
34	#include <VBox/log.h>
35	#include <VBox/dis.h>
36	#include <VBox/disopcode.h>
37	#include <iprt/param.h>
38	#include <iprt/assert.h>
39	#include <iprt/asm.h>
40	#include <iprt/asm-amd64-x86.h>
41	#include <iprt/cpuset.h>
42	#include <iprt/mp.h>
43	#include <iprt/time.h>
44	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
45	# include <iprt/thread.h>
46	#endif
47	#include <iprt/x86.h>
48	#include "HMSVMR0.h"
49
50	#include "dtrace/VBoxVMM.h"
51
52
53	/*******************************************************************************
54	* Internal Functions *
55	*******************************************************************************/
56	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame);
57	static int hmR0SvmEmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
58	static void hmR0SvmSetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);
59
60	/*******************************************************************************
61	* Defined Constants And Macros *
62	*******************************************************************************/
63	/** Convert hidden selector attribute word between VMX and SVM formats. */
64	#define SVM_HIDSEGATTR_VMX2SVM(a) (a & 0xFF) \| ((a & 0xF000) >> 4)
65	#define SVM_HIDSEGATTR_SVM2VMX(a) (a & 0xFF) \| ((a & 0x0F00) << 4)
66
67	#define SVM_WRITE_SELREG(REG, reg) \
68	do \
69	{ \
70	Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \
71	Assert(pCtx->reg.ValidSel == pCtx->reg.Sel); \
72	pVmcb->guest.REG.u16Sel = pCtx->reg.Sel; \
73	pVmcb->guest.REG.u32Limit = pCtx->reg.u32Limit; \
74	pVmcb->guest.REG.u64Base = pCtx->reg.u64Base; \
75	pVmcb->guest.REG.u16Attr = SVM_HIDSEGATTR_VMX2SVM(pCtx->reg.Attr.u); \
76	} while (0)
77
78	#define SVM_READ_SELREG(REG, reg) \
79	do \
80	{ \
81	pCtx->reg.Sel = pVmcb->guest.REG.u16Sel; \
82	pCtx->reg.ValidSel = pVmcb->guest.REG.u16Sel; \
83	pCtx->reg.fFlags = CPUMSELREG_FLAGS_VALID; \
84	pCtx->reg.u32Limit = pVmcb->guest.REG.u32Limit; \
85	pCtx->reg.u64Base = pVmcb->guest.REG.u64Base; \
86	pCtx->reg.Attr.u = SVM_HIDSEGATTR_SVM2VMX(pVmcb->guest.REG.u16Attr); \
87	} while (0)
88
89	/*******************************************************************************
90	* Global Variables *
91	*******************************************************************************/
92	/* IO operation lookup arrays. */
93	static uint32_t const g_aIOSize[8] = {0, 1, 2, 0, 4, 0, 0, 0};
94	static uint32_t const g_aIOOpAnd[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
95
96
97	/**
98	* Sets up and activates AMD-V on the current CPU.
99	*
100	* @returns VBox status code.
101	* @param pCpu Pointer to the CPU info struct.
102	* @param pVM Pointer to the VM (can be NULL after a resume!).
103	* @param pvCpuPage Pointer to the global CPU page.
104	* @param HCPhysCpuPage Physical address of the global CPU page.
105	*/
106	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost)
107	{
108	AssertReturn(!fEnabledByHost, VERR_INVALID_PARAMETER);
109	AssertReturn(HCPhysCpuPage != 0 && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
110	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
111
112	/*
113	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per cpu/core.
114	*/
115	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
116	if (fEfer & MSR_K6_EFER_SVME)
117	{
118	/*
119	* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V.
120	*/
121	if ( pVM
122	&& pVM->hm.s.svm.fIgnoreInUseError)
123	{
124	pCpu->fIgnoreAMDVInUseError = true;
125	}
126
127	if (!pCpu->fIgnoreAMDVInUseError)
128	return VERR_SVM_IN_USE;
129	}
130
131	/* Turn on AMD-V in the EFER MSR. */
132	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
133
134	/* Write the physical page address where the CPU will store the host state while executing the VM. */
135	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
136
137	/*
138	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
139	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
140	* upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
141	* to flush the TLB with before using a new ASID.
142	*/
143	pCpu->fFlushAsidBeforeUse = true;
144
145	/*
146	* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
147	*/
148	++pCpu->cTlbFlushes;
149
150	return VINF_SUCCESS;
151	}
152
153
154	/**
155	* Deactivates AMD-V on the current CPU.
156	*
157	* @returns VBox status code.
158	* @param pCpu Pointer to the CPU info struct.
159	* @param pvCpuPage Pointer to the global CPU page.
160	* @param HCPhysCpuPage Physical address of the global CPU page.
161	*/
162	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
163	{
164	AssertReturn(HCPhysCpuPage != 0 && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
165	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
166	NOREF(pCpu);
167
168	/* Turn off AMD-V in the EFER MSR. */
169	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
170	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
171
172	/* Invalidate host state physical address. */
173	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
174
175	return VINF_SUCCESS;
176	}
177
178
179	/**
180	* Does global AMD-V initialization (called during module initialization).
181	*
182	* @returns VBox status code.
183	*/
184	VMMR0DECL(int) SVMR0GlobalInit(void)
185	{
186	return VINF_SUCCESS;
187	}
188
189
190	/**
191	* Does global VT-x termination (called during module termination).
192	*/
193	VMMR0DECL(void) SVMR0GlobalTerm(void)
194	{
195	}
196
197
198	/**
199	* Does Ring-0 per VM AMD-V init.
200	*
201	* @returns VBox status code.
202	* @param pVM Pointer to the VM.
203	*/
204	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
205	{
206	int rc;
207
208	pVM->hm.s.svm.hMemObjIOBitmap = NIL_RTR0MEMOBJ;
209
210	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
211	rc = RTR0MemObjAllocCont(&pVM->hm.s.svm.hMemObjIOBitmap, 3 << PAGE_SHIFT, false /* fExecutable */);
212	if (RT_FAILURE(rc))
213	return rc;
214
215	pVM->hm.s.svm.pvIOBitmap = RTR0MemObjAddress(pVM->hm.s.svm.hMemObjIOBitmap);
216	pVM->hm.s.svm.HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(pVM->hm.s.svm.hMemObjIOBitmap, 0);
217	/* Set all bits to intercept all IO accesses. */
218	ASMMemFill32(pVM->hm.s.svm.pvIOBitmap, 3 << PAGE_SHIFT, 0xffffffff);
219
220	/* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch. */
221	uint32_t u32Family;
222	uint32_t u32Model;
223	uint32_t u32Stepping;
224	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
225	{
226	Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
227	pVM->hm.s.svm.fAlwaysFlushTLB = true;
228	}
229
230	/* Allocate VMCBs for all guest CPUs. */
231	for (VMCPUID i = 0; i < pVM->cCpus; i++)
232	{
233	PVMCPU pVCpu = &pVM->aCpus[i];
234
235	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
236	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
237	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
238
239	/* Allocate one page for the host context */
240	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, 1 << PAGE_SHIFT, false /* fExecutable */);
241	if (RT_FAILURE(rc))
242	return rc;
243
244	pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
245	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0);
246	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
247	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
248
249	/* Allocate one page for the VM control block (VMCB). */
250	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, 1 << PAGE_SHIFT, false /* fExecutable */);
251	if (RT_FAILURE(rc))
252	return rc;
253
254	pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
255	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0);
256	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
257	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
258
259	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
260	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
261	if (RT_FAILURE(rc))
262	return rc;
263
264	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
265	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0);
266	/* Set all bits to intercept all MSR accesses. */
267	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, 2 << PAGE_SHIFT, 0xffffffff);
268	}
269
270	return VINF_SUCCESS;
271	}
272
273
274	/**
275	* Does Ring-0 per VM AMD-V termination.
276	*
277	* @returns VBox status code.
278	* @param pVM Pointer to the VM.
279	*/
280	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
281	{
282	for (VMCPUID i = 0; i < pVM->cCpus; i++)
283	{
284	PVMCPU pVCpu = &pVM->aCpus[i];
285
286	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
287	{
288	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
289	pVCpu->hm.s.svm.pvVmcbHost = 0;
290	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
291	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
292	}
293
294	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
295	{
296	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
297	pVCpu->hm.s.svm.pvVmcb = 0;
298	pVCpu->hm.s.svm.HCPhysVmcb = 0;
299	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
300	}
301	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
302	{
303	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
304	pVCpu->hm.s.svm.pvMsrBitmap = 0;
305	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
306	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
307	}
308	}
309	if (pVM->hm.s.svm.hMemObjIOBitmap != NIL_RTR0MEMOBJ)
310	{
311	RTR0MemObjFree(pVM->hm.s.svm.hMemObjIOBitmap, false);
312	pVM->hm.s.svm.pvIOBitmap = 0;
313	pVM->hm.s.svm.HCPhysIOBitmap = 0;
314	pVM->hm.s.svm.hMemObjIOBitmap = NIL_RTR0MEMOBJ;
315	}
316	return VINF_SUCCESS;
317	}
318
319
320	/**
321	* Sets up AMD-V for the specified VM.
322	*
323	* @returns VBox status code.
324	* @param pVM Pointer to the VM.
325	*/
326	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
327	{
328	int rc = VINF_SUCCESS;
329
330	AssertReturn(pVM, VERR_INVALID_PARAMETER);
331	Assert(pVM->hm.s.svm.fSupported);
332
333	for (VMCPUID i = 0; i < pVM->cCpus; i++)
334	{
335	PVMCPU pVCpu = &pVM->aCpus[i];
336	PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
337
338	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
339
340	/*
341	* Program the control fields. Most of them never have to be changed again.
342	* CR0/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's.
343	* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical.
344	*/
345	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
346
347	/* CR0/4 writes must be intercepted for obvious reasons. */
348	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
349
350	/* Intercept all DRx reads and writes by default. Changed later on. */
351	pVmcb->ctrl.u16InterceptRdDRx = 0xFFFF;
352	pVmcb->ctrl.u16InterceptWrDRx = 0xFFFF;
353
354	/* Intercept traps; only #NM is always intercepted. */
355	pVmcb->ctrl.u32InterceptException = RT_BIT(X86_XCPT_NM);
356	#ifdef VBOX_ALWAYS_TRAP_PF
357	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
358	#endif
359	#ifdef VBOX_STRICT
360	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_BP)
361	\| RT_BIT(X86_XCPT_DB)
362	\| RT_BIT(X86_XCPT_DE)
363	\| RT_BIT(X86_XCPT_UD)
364	\| RT_BIT(X86_XCPT_NP)
365	\| RT_BIT(X86_XCPT_SS)
366	\| RT_BIT(X86_XCPT_GP)
367	\| RT_BIT(X86_XCPT_MF)
368	;
369	#endif
370
371	/* Set up instruction and miscellaneous intercepts. */
372	pVmcb->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
373	\| SVM_CTRL1_INTERCEPT_VINTR
374	\| SVM_CTRL1_INTERCEPT_NMI
375	\| SVM_CTRL1_INTERCEPT_SMI
376	\| SVM_CTRL1_INTERCEPT_INIT
377	\| SVM_CTRL1_INTERCEPT_RDPMC
378	\| SVM_CTRL1_INTERCEPT_CPUID
379	\| SVM_CTRL1_INTERCEPT_RSM
380	\| SVM_CTRL1_INTERCEPT_HLT
381	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
382	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
383	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
384	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
385	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
386	;
387	pVmcb->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
388	\| SVM_CTRL2_INTERCEPT_VMMCALL
389	\| SVM_CTRL2_INTERCEPT_VMLOAD
390	\| SVM_CTRL2_INTERCEPT_VMSAVE
391	\| SVM_CTRL2_INTERCEPT_STGI
392	\| SVM_CTRL2_INTERCEPT_CLGI
393	\| SVM_CTRL2_INTERCEPT_SKINIT
394	\| SVM_CTRL2_INTERCEPT_WBINVD
395	\| SVM_CTRL2_INTERCEPT_MONITOR
396	\| SVM_CTRL2_INTERCEPT_MWAIT; /* don't execute mwait or else we'll idle inside the
397	guest (host thinks the cpu load is high) */
398
399	Log(("pVmcb->ctrl.u32InterceptException = %x\n", pVmcb->ctrl.u32InterceptException));
400	Log(("pVmcb->ctrl.u32InterceptCtrl1 = %x\n", pVmcb->ctrl.u32InterceptCtrl1));
401	Log(("pVmcb->ctrl.u32InterceptCtrl2 = %x\n", pVmcb->ctrl.u32InterceptCtrl2));
402
403	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
404	pVmcb->ctrl.IntCtrl.n.u1VIrqMasking = 1;
405
406	/* Ignore the priority in the TPR; just deliver it when we tell it to. */
407	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
408
409	/* Set IO and MSR bitmap addresses. */
410	pVmcb->ctrl.u64IOPMPhysAddr = pVM->hm.s.svm.HCPhysIOBitmap;
411	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
412
413	/* No LBR virtualization. */
414	pVmcb->ctrl.u64LBRVirt = 0;
415
416	/* The ASID must start at 1; the host uses 0. */
417	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
418
419	/*
420	* Setup the PAT MSR (nested paging only)
421	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
422	* so choose type 6 for all PAT slots.
423	*/
424	pVmcb->guest.u64GPAT = 0x0006060606060606ULL;
425
426	/* If nested paging is not in use, additional intercepts have to be set up. */
427	if (!pVM->hm.s.fNestedPaging)
428	{
429	/* CR3 reads/writes must be intercepted; our shadow values are different from guest's. */
430	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
431	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
432
433	/*
434	* We must also intercept:
435	* - INVLPG (must go through shadow paging)
436	* - task switches (may change CR3/EFLAGS/LDT)
437	*/
438	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_INVLPG
439	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH;
440
441	/* Page faults must be intercepted to implement shadow paging. */
442	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_PF);
443	}
444
445	/*
446	* The following MSRs are saved automatically by vmload/vmsave, so we allow the guest
447	* to modify them directly.
448	*/
449	hmR0SvmSetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
450	hmR0SvmSetMSRPermission(pVCpu, MSR_K8_CSTAR, true, true);
451	hmR0SvmSetMSRPermission(pVCpu, MSR_K6_STAR, true, true);
452	hmR0SvmSetMSRPermission(pVCpu, MSR_K8_SF_MASK, true, true);
453	hmR0SvmSetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true);
454	hmR0SvmSetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true);
455	hmR0SvmSetMSRPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, true, true);
456	hmR0SvmSetMSRPermission(pVCpu, MSR_IA32_SYSENTER_CS, true, true);
457	hmR0SvmSetMSRPermission(pVCpu, MSR_IA32_SYSENTER_ESP, true, true);
458	hmR0SvmSetMSRPermission(pVCpu, MSR_IA32_SYSENTER_EIP, true, true);
459	}
460
461	return rc;
462	}
463
464
465	/**
466	* Sets the permission bits for the specified MSR.
467	*
468	* @param pVCpu Pointer to the VMCPU.
469	* @param ulMSR MSR value.
470	* @param fRead Whether reading is allowed.
471	* @param fWrite Whether writing is allowed.
472	*/
473	static void hmR0SvmSetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)
474	{
475	unsigned ulBit;
476	uint8_t pvMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
477
478	if (ulMSR <= 0x00001FFF)
479	{
480	/* Pentium-compatible MSRs */
481	ulBit = ulMSR * 2;
482	}
483	else if ( ulMSR >= 0xC0000000
484	&& ulMSR <= 0xC0001FFF)
485	{
486	/* AMD Sixth Generation x86 Processor MSRs and SYSCALL */
487	ulBit = (ulMSR - 0xC0000000) * 2;
488	pvMsrBitmap += 0x800;
489	}
490	else if ( ulMSR >= 0xC0010000
491	&& ulMSR <= 0xC0011FFF)
492	{
493	/* AMD Seventh and Eighth Generation Processor MSRs */
494	ulBit = (ulMSR - 0xC0001000) * 2;
495	pvMsrBitmap += 0x1000;
496	}
497	else
498	{
499	AssertFailed();
500	return;
501	}
502	Assert(ulBit < 16 * 1024 - 1);
503	if (fRead)
504	ASMBitClear(pvMsrBitmap, ulBit);
505	else
506	ASMBitSet(pvMsrBitmap, ulBit);
507
508	if (fWrite)
509	ASMBitClear(pvMsrBitmap, ulBit + 1);
510	else
511	ASMBitSet(pvMsrBitmap, ulBit + 1);
512	}
513
514	/**
515	* Posts a pending event (trap or external interrupt). An injected event should only
516	* be written to the VMCB immediately before VMRUN, otherwise we might have stale events
517	* injected across VM resets and suchlike. See @bugref{6220}.
518	*
519	* @param pVCpu Pointer to the VMCPU.
520	* @param pCtx Pointer to the guest CPU context.
521	* @param pIntInfo Pointer to the SVM interrupt info.
522	*/
523	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, SVMEVENT *pEvent)
524	{
525	#ifdef VBOX_STRICT
526	Log(("SVM: Set pending event: intInfo=%016llx\n", pEvent->u));
527	#endif
528
529	/* If there's an event pending already, we're in trouble... */
530	Assert(!pVCpu->hm.s.Event.fPending);
531
532	/* Set pending event state. */
533	pVCpu->hm.s.Event.u64IntrInfo = pEvent->u;
534	pVCpu->hm.s.Event.fPending = true;
535	}
536
537	/**
538	* Injects an event (trap or external interrupt).
539	*
540	* @param pVCpu Pointer to the VMCPU.
541	* @param pVmcb Pointer to the VMCB.
542	* @param pCtx Pointer to the guest CPU context.
543	* @param pIntInfo Pointer to the SVM interrupt info.
544	*/
545	DECLINLINE(void) hmR0SvmInjectEvent(PVMCPU pVCpu, PSVMVMCB pVmcb, CPUMCTX pCtx, SVMEVENT pEvent)
546	{
547	#ifdef VBOX_WITH_STATISTICS
548	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
549	#endif
550
551	#ifdef VBOX_STRICT
552	if (pEvent->n.u8Vector == 0xE)
553	{
554	Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector,
555	(RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->u));
556	}
557	else if (pEvent->n.u8Vector < 0x20)
558	Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
559	else
560	{
561	Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
562	Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
563	Assert(pCtx->eflags.u32 & X86_EFL_IF);
564	}
565	#endif
566
567	/* Set event injection state. */
568	pVmcb->ctrl.EventInject.u = pEvent->u;
569	}
570
571
572	/**
573	* Checks for pending guest interrupts and injects them.
574	*
575	* @returns VBox status code.
576	* @param pVM Pointer to the VM.
577	* @param pVCpu Pointer to the VMCPU.
578	* @param pVmcb Pointer to the VMCB.
579	* @param pCtx Pointer to the guest CPU Context.
580	*/
581	static int hmR0SvmCheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, PSVMVMCB pVmcb, CPUMCTX *pCtx)
582	{
583	int rc;
584	NOREF(pVM);
585
586	/*
587	* Dispatch any pending interrupts (injected before, but a VM-exit occurred prematurely).
588	*/
589	if (pVCpu->hm.s.Event.fPending)
590	{
591	SVMEVENT Event;
592
593	Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hm.s.Event.u64IntrInfo, pVCpu->hm.s.Event.u32ErrCode,
594	(RTGCPTR)pCtx->rip));
595	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
596	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
597	hmR0SvmInjectEvent(pVCpu, pVmcb, pCtx, &Event);
598
599	pVCpu->hm.s.Event.fPending = false;
600	return VINF_SUCCESS;
601	}
602
603	/*
604	* If an active trap is already pending, we must forward it first!
605	*/
606	if (!TRPMHasTrap(pVCpu))
607	{
608	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI))
609	{
610	SVMEVENT Event;
611
612	Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
613	Event.n.u8Vector = X86_XCPT_NMI;
614	Event.n.u1Valid = 1;
615	Event.n.u32ErrorCode = 0;
616	Event.n.u3Type = SVM_EVENT_NMI;
617
618	hmR0SvmInjectEvent(pVCpu, pVmcb, pCtx, &Event);
619	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
620	return VINF_SUCCESS;
621	}
622
623	/** @todo SMI interrupts. */
624
625	/*
626	* When external interrupts are pending, we should exit the VM when IF is set.
627	*/
628	if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC\|VMCPU_FF_INTERRUPT_PIC)))
629	{
630	if ( !(pCtx->eflags.u32 & X86_EFL_IF)
631	\|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
632	{
633	if (!pVmcb->ctrl.IntCtrl.n.u1VIrqValid)
634	{
635	if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
636	LogFlow(("Enable irq window exit!\n"));
637	else
638	{
639	Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n",
640	(RTGCPTR)pCtx->rip));
641	}
642
643	/** @todo Use virtual interrupt method to inject a pending IRQ; dispatched as
644	* soon as guest.IF is set. */
645	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
646	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 1;
647	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
648	}
649	}
650	else
651	{
652	uint8_t u8Interrupt;
653
654	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
655	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
656	if (RT_SUCCESS(rc))
657	{
658	rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
659	AssertRC(rc);
660	}
661	else
662	{
663	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
664	Assert(!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC\|VMCPU_FF_INTERRUPT_PIC)));
665	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
666	/* Just continue */
667	}
668	}
669	}
670	}
671
672	#ifdef VBOX_STRICT
673	if (TRPMHasTrap(pVCpu))
674	{
675	uint8_t u8Vector;
676	rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, NULL, NULL, NULL);
677	AssertRC(rc);
678	}
679	#endif
680
681	if ( (pCtx->eflags.u32 & X86_EFL_IF)
682	&& (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
683	&& TRPMHasTrap(pVCpu)
684	)
685	{
686	uint8_t u8Vector;
687	TRPMEVENT enmType;
688	SVMEVENT Event;
689	RTGCUINT u32ErrorCode;
690
691	Event.u = 0;
692
693	/* If a new event is pending, then dispatch it now. */
694	rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, NULL, NULL);
695	AssertRC(rc);
696	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
697	Assert(enmType != TRPM_SOFTWARE_INT);
698
699	/* Clear the pending trap. */
700	rc = TRPMResetTrap(pVCpu);
701	AssertRC(rc);
702
703	Event.n.u8Vector = u8Vector;
704	Event.n.u1Valid = 1;
705	Event.n.u32ErrorCode = u32ErrorCode;
706
707	if (enmType == TRPM_TRAP)
708	{
709	switch (u8Vector)
710	{
711	case X86_XCPT_DF:
712	case X86_XCPT_TS:
713	case X86_XCPT_NP:
714	case X86_XCPT_SS:
715	case X86_XCPT_GP:
716	case X86_XCPT_PF:
717	case X86_XCPT_AC:
718	/* Valid error codes. */
719	Event.n.u1ErrorCodeValid = 1;
720	break;
721	default:
722	break;
723	}
724	if (u8Vector == X86_XCPT_NMI)
725	Event.n.u3Type = SVM_EVENT_NMI;
726	else
727	Event.n.u3Type = SVM_EVENT_EXCEPTION;
728
729	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
730	}
731	else
732	{
733	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
734	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
735	}
736
737	hmR0SvmInjectEvent(pVCpu, pVmcb, pCtx, &Event);
738	} /* if (interrupts can be dispatched) */
739
740	return VINF_SUCCESS;
741	}
742
743
744	/**
745	* Save the host state.
746	*
747	* @returns VBox status code.
748	* @param pVM Pointer to the VM.
749	* @param pVCpu Pointer to the VMCPU.
750	*/
751	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
752	{
753	NOREF(pVM);
754	NOREF(pVCpu);
755	/* Nothing to do here. */
756	return VINF_SUCCESS;
757	}
758
759
760	/**
761	* Loads the guest state.
762	*
763	* NOTE: Don't do anything here that can cause a jump back to ring-3!!!
764	*
765	* @returns VBox status code.
766	* @param pVM Pointer to the VM.
767	* @param pVCpu Pointer to the VMCPU.
768	* @param pCtx Pointer to the guest CPU context.
769	*/
770	VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
771	{
772	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
773
774	RTGCUINTPTR val;
775	PSVMVMCB pVmcb;
776
777	if (pVM == NULL)
778	return VERR_INVALID_PARAMETER;
779
780	/* Setup AMD SVM. */
781	Assert(pVM->hm.s.svm.fSupported);
782
783	pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
784	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
785
786	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
787	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_SEGMENT_REGS)
788	{
789	SVM_WRITE_SELREG(CS, cs);
790	SVM_WRITE_SELREG(SS, ss);
791	SVM_WRITE_SELREG(DS, ds);
792	SVM_WRITE_SELREG(ES, es);
793	SVM_WRITE_SELREG(FS, fs);
794	SVM_WRITE_SELREG(GS, gs);
795	}
796
797	/* Guest CPU context: LDTR. */
798	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_LDTR)
799	{
800	SVM_WRITE_SELREG(LDTR, ldtr);
801	}
802
803	/* Guest CPU context: TR. */
804	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_TR)
805	{
806	SVM_WRITE_SELREG(TR, tr);
807	}
808
809	/* Guest CPU context: GDTR. */
810	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_GDTR)
811	{
812	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
813	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
814	}
815
816	/* Guest CPU context: IDTR. */
817	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_IDTR)
818	{
819	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
820	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
821	}
822
823	/*
824	* Sysenter MSRs (unconditional)
825	*/
826	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
827	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
828	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
829
830	/* Control registers */
831	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR0)
832	{
833	val = pCtx->cr0;
834	if (!CPUMIsGuestFPUStateActive(pVCpu))
835	{
836	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
837	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
838	}
839	else
840	{
841	/** @todo check if we support the old style mess correctly. */
842	if (!(val & X86_CR0_NE))
843	{
844	Log(("Forcing X86_CR0_NE!!!\n"));
845
846	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
847	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_MF);
848	}
849	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
850	}
851	/* Always enable caching. */
852	val &= ~(X86_CR0_CD\|X86_CR0_NW);
853
854	/*
855	* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level.
856	* Note: In nested paging mode, the guest is allowed to run with paging disabled; the guest-physical to host-physical
857	* translation will remain active.
858	*/
859	if (!pVM->hm.s.fNestedPaging)
860	{
861	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
862	val \|= X86_CR0_WP; /* Must set this as we rely on protecting various pages and supervisor writes must be caught. */
863	}
864	pVmcb->guest.u64CR0 = val;
865	}
866	/* CR2 as well */
867	pVmcb->guest.u64CR2 = pCtx->cr2;
868
869	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR3)
870	{
871	/* Save our shadow CR3 register. */
872	if (pVM->hm.s.fNestedPaging)
873	{
874	PGMMODE enmShwPagingMode;
875
876	#if HC_ARCH_BITS == 32
877	if (CPUMIsGuestInLongModeEx(pCtx))
878	enmShwPagingMode = PGMMODE_AMD64_NX;
879	else
880	#endif
881	enmShwPagingMode = PGMGetHostMode(pVM);
882
883	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
884	Assert(pVmcb->ctrl.u64NestedPagingCR3);
885	pVmcb->guest.u64CR3 = pCtx->cr3;
886	}
887	else
888	{
889	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
890	Assert(pVmcb->guest.u64CR3 \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
891	}
892	}
893
894	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_CR4)
895	{
896	val = pCtx->cr4;
897	if (!pVM->hm.s.fNestedPaging)
898	{
899	switch (pVCpu->hm.s.enmShadowMode)
900	{
901	case PGMMODE_REAL:
902	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
903	AssertFailed();
904	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
905
906	case PGMMODE_32_BIT: /* 32-bit paging. */
907	val &= ~X86_CR4_PAE;
908	break;
909
910	case PGMMODE_PAE: /* PAE paging. */
911	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
912	/** Must use PAE paging as we could use physical memory > 4 GB */
913	val \|= X86_CR4_PAE;
914	break;
915
916	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
917	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
918	#ifdef VBOX_ENABLE_64_BITS_GUESTS
919	break;
920	#else
921	AssertFailed();
922	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
923	#endif
924
925	default: /* shut up gcc */
926	AssertFailed();
927	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
928	}
929	}
930	pVmcb->guest.u64CR4 = val;
931	}
932
933	/* Debug registers. */
934	if (pVCpu->hm.s.fContextUseFlags & HM_CHANGED_GUEST_DEBUG)
935	{
936	pCtx->dr[6] \|= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
937	pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
938
939	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
940	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
941	pCtx->dr[7] \|= 0x400; /* must be one */
942
943	pVmcb->guest.u64DR7 = pCtx->dr[7];
944	pVmcb->guest.u64DR6 = pCtx->dr[6];
945
946	#ifdef DEBUG
947	/* Sync the hypervisor debug state now if any breakpoint is armed. */
948	if ( CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK\|X86_DR7_GD)
949	&& !CPUMIsHyperDebugStateActive(pVCpu)
950	&& !DBGFIsStepping(pVCpu))
951	{
952	/* Save the host and load the hypervisor debug state. */
953	int rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
954	AssertRC(rc);
955
956	/* DRx intercepts remain enabled. */
957
958	/* Override dr6 & dr7 with the hypervisor values. */
959	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
960	pVmcb->guest.u64DR6 = CPUMGetHyperDR6(pVCpu);
961	}
962	else
963	#endif
964	/* Sync the debug state now if any breakpoint is armed. */
965	if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK\|X86_DR7_GD))
966	&& !CPUMIsGuestDebugStateActive(pVCpu)
967	&& !DBGFIsStepping(pVCpu))
968	{
969	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
970
971	/* Disable drx move intercepts. */
972	pVmcb->ctrl.u16InterceptRdDRx = 0;
973	pVmcb->ctrl.u16InterceptWrDRx = 0;
974
975	/* Save the host and load the guest debug state. */
976	int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
977	AssertRC(rc);
978	}
979	}
980
981	/* EIP, ESP and EFLAGS */
982	pVmcb->guest.u64RIP = pCtx->rip;
983	pVmcb->guest.u64RSP = pCtx->rsp;
984	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
985
986	/* Set CPL */
987	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
988
989	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
990	pVmcb->guest.u64RAX = pCtx->rax;
991
992	/* vmrun will fail without MSR_K6_EFER_SVME. */
993	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
994
995	/* 64 bits guest mode? */
996	if (CPUMIsGuestInLongModeEx(pCtx))
997	{
998	#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
999	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1000	#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1001	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1002	#else
1003	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1004	if (!pVM->hm.s.fAllow64BitGuests)
1005	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1006	# endif
1007	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1008	#endif
1009	/* Unconditionally update these as wrmsr might have changed them. (HM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
1010	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1011	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1012	}
1013	else
1014	{
1015	/* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
1016	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1017
1018	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1019	}
1020
1021	/* TSC offset. */
1022	if (TMCpuTickCanUseRealTSC(pVCpu, &pVmcb->ctrl.u64TSCOffset))
1023	{
1024	uint64_t u64CurTSC = ASMReadTSC();
1025	if (u64CurTSC + pVmcb->ctrl.u64TSCOffset > TMCpuTickGetLastSeen(pVCpu))
1026	{
1027	pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
1028	pVmcb->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
1029	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
1030	}
1031	else
1032	{
1033	/* Fall back to rdtsc emulation as we would otherwise pass decreasing tsc values to the guest. */
1034	LogFlow(("TSC %RX64 offset %RX64 time=%RX64 last=%RX64 (diff=%RX64, virt_tsc=%RX64)\n", u64CurTSC,
1035	pVmcb->ctrl.u64TSCOffset, u64CurTSC + pVmcb->ctrl.u64TSCOffset, TMCpuTickGetLastSeen(pVCpu),
1036	TMCpuTickGetLastSeen(pVCpu) - u64CurTSC - pVmcb->ctrl.u64TSCOffset, TMCpuTickGet(pVCpu)));
1037	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
1038	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
1039	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscInterceptOverFlow);
1040	}
1041	}
1042	else
1043	{
1044	pVmcb->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
1045	pVmcb->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
1046	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
1047	}
1048
1049	/* Sync the various MSRs for 64-bit mode. */
1050	pVmcb->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
1051	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR; /* 64-bit mode syscall rip */
1052	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
1053	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
1054	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* SWAPGS exchange value */
1055
1056	#ifdef DEBUG
1057	/* Intercept X86_XCPT_DB if stepping is enabled */
1058	if ( DBGFIsStepping(pVCpu)
1059	\|\| CPUMIsHyperDebugStateActive(pVCpu))
1060	pVmcb->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_DB);
1061	else
1062	pVmcb->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
1063	#endif
1064
1065	/* Done. */
1066	pVCpu->hm.s.fContextUseFlags &= ~HM_CHANGED_ALL_GUEST;
1067
1068	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
1069
1070	return VINF_SUCCESS;
1071	}
1072
1073
1074	/**
1075	* Setup TLB for ASID.
1076	*
1077	* @param pVM Pointer to the VM.
1078	* @param pVCpu Pointer to the VMCPU.
1079	*/
1080	static void hmR0SvmSetupTLB(PVM pVM, PVMCPU pVCpu)
1081	{
1082	PHMGLOBLCPUINFO pCpu;
1083
1084	AssertPtr(pVM);
1085	AssertPtr(pVCpu);
1086
1087	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1088	pCpu = HMR0GetCurrentCpu();
1089
1090	/*
1091	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
1092	* This can happen both for start & resume due to long jumps back to ring-3.
1093	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
1094	* so we cannot reuse the ASIDs without flushing.
1095	*/
1096	bool fNewAsid = false;
1097	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
1098	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
1099	{
1100	pVCpu->hm.s.fForceTLBFlush = true;
1101	fNewAsid = true;
1102	}
1103
1104	/*
1105	* Set TLB flush state as checked until we return from the world switch.
1106	*/
1107	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
1108
1109	/*
1110	* Check for TLB shootdown flushes.
1111	*/
1112	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1113	pVCpu->hm.s.fForceTLBFlush = true;
1114
1115	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1116	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
1117
1118	if (RT_UNLIKELY(pVM->hm.s.svm.fAlwaysFlushTLB))
1119	{
1120	/*
1121	* This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
1122	*/
1123	pCpu->uCurrentAsid = 1;
1124	pVCpu->hm.s.uCurrentAsid = 1;
1125	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1126	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1127	}
1128	else if (pVCpu->hm.s.fForceTLBFlush)
1129	{
1130	if (fNewAsid)
1131	{
1132	++pCpu->uCurrentAsid;
1133	bool fHitASIDLimit = false;
1134	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1135	{
1136	pCpu->uCurrentAsid = 1; /* start at 1; host uses 0 */
1137	pCpu->cTlbFlushes++;
1138	fHitASIDLimit = true;
1139
1140	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1141	{
1142	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1143	pCpu->fFlushAsidBeforeUse = true;
1144	}
1145	else
1146	{
1147	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1148	pCpu->fFlushAsidBeforeUse = false;
1149	}
1150	}
1151
1152	if ( !fHitASIDLimit
1153	&& pCpu->fFlushAsidBeforeUse)
1154	{
1155	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1156	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1157	else
1158	{
1159	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1160	pCpu->fFlushAsidBeforeUse = false;
1161	}
1162	}
1163
1164	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
1165	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1166	}
1167	else
1168	{
1169	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1170	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1171	else
1172	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1173	}
1174
1175	pVCpu->hm.s.fForceTLBFlush = false;
1176	}
1177	else
1178	{
1179	/** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
1180	* not be executed. See hmQueueInvlPage() where it is commented
1181	* out. Support individual entry flushing someday. */
1182	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1183	{
1184	/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1185	STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
1186	for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
1187	SVMR0InvlpgA(pVCpu->hm.s.TlbShootdown.aPages[i], pVmcb->ctrl.TLBCtrl.n.u32ASID);
1188	}
1189	}
1190
1191	pVCpu->hm.s.TlbShootdown.cPages = 0;
1192	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1193
1194	/* Update VMCB with the ASID. */
1195	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
1196
1197	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
1198	("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
1199	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
1200	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
1201	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
1202	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1203
1204	#ifdef VBOX_WITH_STATISTICS
1205	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1206	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1207	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1208	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1209	{
1210	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1211	}
1212	else
1213	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1214	#endif
1215	}
1216
1217
1218	/**
1219	* Runs guest code in an AMD-V VM.
1220	*
1221	* @returns VBox status code.
1222	* @param pVM Pointer to the VM.
1223	* @param pVCpu Pointer to the VMCPU.
1224	* @param pCtx Pointer to the guest CPU context.
1225	*/
1226	VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1227	{
1228	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
1229	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
1230	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
1231
1232	VBOXSTRICTRC rc = VINF_SUCCESS;
1233	int rc2;
1234	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
1235	PSVMVMCB pVmcb = NULL;
1236	bool fSyncTPR = false;
1237	unsigned cResume = 0;
1238	uint8_t u8LastTPR = 0; /* Initialized for potentially stupid compilers. */
1239	uint32_t u32HostExtFeatures = 0;
1240	PHMGLOBLCPUINFO pCpu = 0;
1241	RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
1242	#ifdef VBOX_STRICT
1243	RTCPUID idCpuCheck;
1244	#endif
1245	#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
1246	uint64_t u64LastTime = RTTimeMilliTS();
1247	#endif
1248
1249	pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1250	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1251
1252	/*
1253	* We can jump to this point to resume execution after determining that a VM-exit is innocent.
1254	*/
1255	ResumeExecution:
1256	if (!STAM_PROFILE_ADV_IS_RUNNING(&pVCpu->hm.s.StatEntry))
1257	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit2, &pVCpu->hm.s.StatEntry, x);
1258	Assert(!HMR0SuspendPending());
1259
1260	/*
1261	* Safety precaution; looping for too long here can have a very bad effect on the host.
1262	*/
1263	if (RT_UNLIKELY(++cResume > pVM->hm.s.cMaxResumeLoops))
1264	{
1265	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMaxResume);
1266	rc = VINF_EM_RAW_INTERRUPT;
1267	goto end;
1268	}
1269
1270	/*
1271	* Check for IRQ inhibition due to instruction fusing (sti, mov ss).
1272	*/
1273	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1274	{
1275	Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
1276	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
1277	{
1278	/*
1279	* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1280	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1281	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1282	* break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
1283	*/
1284	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1285	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
1286	pVmcb->ctrl.u64IntShadow = 0;
1287	}
1288	}
1289	else
1290	{
1291	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
1292	pVmcb->ctrl.u64IntShadow = 0;
1293	}
1294
1295	#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
1296	if (RT_UNLIKELY((cResume & 0xf) == 0))
1297	{
1298	uint64_t u64CurTime = RTTimeMilliTS();
1299
1300	if (RT_UNLIKELY(u64CurTime > u64LastTime))
1301	{
1302	u64LastTime = u64CurTime;
1303	TMTimerPollVoid(pVM, pVCpu);
1304	}
1305	}
1306	#endif
1307
1308	/*
1309	* Check for pending actions that force us to go back to ring-3.
1310	*/
1311	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING \| VM_FF_PDM_DMA)
1312	\|\| VMCPU_FF_IS_PENDING(pVCpu,
1313	VMCPU_FF_HM_TO_R3_MASK
1314	\| VMCPU_FF_PGM_SYNC_CR3
1315	\| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL
1316	\| VMCPU_FF_REQUEST))
1317	{
1318	/* Check if a sync operation is pending. */
1319	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1320	{
1321	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1322	AssertRC(VBOXSTRICTRC_VAL(rc));
1323	if (rc != VINF_SUCCESS)
1324	{
1325	Log(("Pending pool sync is forcing us back to ring 3; rc=%d\n", VBOXSTRICTRC_VAL(rc)));
1326	goto end;
1327	}
1328	}
1329
1330	#ifdef DEBUG
1331	/* Intercept X86_XCPT_DB if stepping is enabled */
1332	if (!DBGFIsStepping(pVCpu))
1333	#endif
1334	{
1335	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
1336	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
1337	{
1338	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
1339	rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
1340	goto end;
1341	}
1342	}
1343
1344	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1345	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
1346	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
1347	{
1348	rc = VINF_EM_PENDING_REQUEST;
1349	goto end;
1350	}
1351
1352	/* Check if a pgm pool flush is in progress. */
1353	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
1354	{
1355	rc = VINF_PGM_POOL_FLUSH_PENDING;
1356	goto end;
1357	}
1358
1359	/* Check if DMA work is pending (2nd+ run). */
1360	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA) && cResume > 1)
1361	{
1362	rc = VINF_EM_RAW_TO_R3;
1363	goto end;
1364	}
1365	}
1366
1367	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1368	/*
1369	* Exit to ring-3 preemption/work is pending.
1370	*
1371	* Interrupts are disabled before the call to make sure we don't miss any interrupt
1372	* that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
1373	* further down, but hmR0SvmCheckPendingInterrupt makes that impossible.)
1374	*
1375	* Note! Interrupts must be disabled done before we check for TLB flushes; TLB
1376	* shootdowns rely on this.
1377	*/
1378	uOldEFlags = ASMIntDisableFlags();
1379	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
1380	{
1381	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
1382	rc = VINF_EM_RAW_INTERRUPT;
1383	goto end;
1384	}
1385	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1386	#endif
1387
1388	/*
1389	* When external interrupts are pending, we should exit the VM when IF is set.
1390	* Note: After VM_FF_INHIBIT_INTERRUPTS check!!
1391	*/
1392	rc = hmR0SvmCheckPendingInterrupt(pVM, pVCpu, pVmcb, pCtx);
1393	if (RT_FAILURE(rc))
1394	goto end;
1395
1396	/*
1397	* TPR caching using CR8 is only available in 64-bit mode or with 32-bit guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is
1398	* supported.
1399	* Note: we can't do this in LoddGuestState as PDMApicGetTPR can jump back to ring 3 (lock)! (no longer true)
1400	*/
1401	/** @todo query and update the TPR only when it could have been changed (mmio access)
1402	*/
1403	if (pVM->hm.s.fHasIoApic)
1404	{
1405	/* TPR caching in CR8 */
1406	bool fPending;
1407	rc2 = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending, NULL /* pu8PendingIrq */);
1408	AssertRC(rc2);
1409
1410	if (pVM->hm.s.fTPRPatchingActive)
1411	{
1412	/* Our patch code uses LSTAR for TPR caching. */
1413	pCtx->msrLSTAR = u8LastTPR;
1414
1415	if (fPending)
1416	{
1417	/* A TPR change could activate a pending interrupt, so catch lstar writes. */
1418	hmR0SvmSetMSRPermission(pVCpu, MSR_K8_LSTAR, true, false);
1419	}
1420	else
1421	{
1422	/*
1423	* No interrupts are pending, so we don't need to be explicitely notified.
1424	* There are enough world switches for detecting pending interrupts.
1425	*/
1426	hmR0SvmSetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
1427	}
1428	}
1429	else
1430	{
1431	/* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1432	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8LastTPR >> 4);
1433
1434	if (fPending)
1435	{
1436	/* A TPR change could activate a pending interrupt, so catch cr8 writes. */
1437	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1438	}
1439	else
1440	{
1441	/*
1442	* No interrupts are pending, so we don't need to be explicitly notified.
1443	* There are enough world switches for detecting pending interrupts.
1444	*/
1445	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1446	}
1447	}
1448	fSyncTPR = !fPending;
1449	}
1450
1451	/* All done! Let's start VM execution. */
1452
1453	/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
1454	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
1455
1456	#ifdef LOG_ENABLED
1457	pCpu = HMR0GetCurrentCpu();
1458	if (pVCpu->hm.s.idLastCpu != pCpu->idCpu)
1459	LogFlow(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hm.s.idLastCpu, pCpu->idCpu));
1460	else if (pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
1461	LogFlow(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
1462	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
1463	LogFlow(("Manual TLB flush\n"));
1464	#endif
1465
1466	/*
1467	* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1468	* (until the actual world switch)
1469	*/
1470	#ifdef VBOX_STRICT
1471	idCpuCheck = RTMpCpuId();
1472	#endif
1473	VMMR0LogFlushDisable(pVCpu);
1474
1475	/*
1476	* Load the guest state; must be here as it sets up the shadow CR0 for lazy FPU syncing!
1477	*/
1478	rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
1479	if (RT_UNLIKELY(rc != VINF_SUCCESS))
1480	{
1481	VMMR0LogFlushEnable(pVCpu);
1482	goto end;
1483	}
1484
1485	#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1486	/*
1487	* Disable interrupts to make sure a poke will interrupt execution.
1488	* This must be done before we check for TLB flushes; TLB shootdowns rely on this.
1489	*/
1490	uOldEFlags = ASMIntDisableFlags();
1491	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1492	#endif
1493
1494	/* Setup TLB control and ASID in the VMCB. */
1495	hmR0SvmSetupTLB(pVM, pVCpu);
1496
1497	/* In case we execute a goto ResumeExecution later on. */
1498	pVCpu->hm.s.fResumeVM = true;
1499	pVCpu->hm.s.fForceTLBFlush = pVM->hm.s.svm.fAlwaysFlushTLB;
1500
1501	Assert(sizeof(pVCpu->hm.s.svm.HCPhysVmcb) == 8);
1502	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqMasking);
1503	Assert(pVmcb->ctrl.u64IOPMPhysAddr == pVM->hm.s.svm.HCPhysIOBitmap);
1504	Assert(pVmcb->ctrl.u64MSRPMPhysAddr == pVCpu->hm.s.svm.HCPhysMsrBitmap);
1505	Assert(pVmcb->ctrl.u64LBRVirt == 0);
1506
1507	#ifdef VBOX_STRICT
1508	Assert(idCpuCheck == RTMpCpuId());
1509	#endif
1510	TMNotifyStartOfExecution(pVCpu);
1511	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
1512
1513	/*
1514	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
1515	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
1516	*/
1517	u32HostExtFeatures = pVM->hm.s.cpuid.u32AMDFeatureEDX;
1518	if ( (u32HostExtFeatures & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
1519	&& !(pVmcb->ctrl.u32InterceptCtrl2 & SVM_CTRL2_INTERCEPT_RDTSCP))
1520	{
1521	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
1522	uint64_t u64GuestTscAux = 0;
1523	rc2 = CPUMQueryGuestMsr(pVCpu, MSR_K8_TSC_AUX, &u64GuestTscAux);
1524	AssertRC(rc2);
1525	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
1526	}
1527
1528	#ifdef VBOX_WITH_KERNEL_USING_XMM
1529	HMR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
1530	pVCpu->hm.s.svm.pfnVMRun);
1531	#else
1532	pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
1533	#endif
1534
1535	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false);
1536	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits);
1537	/* Possibly the last TSC value seen by the guest (too high) (only when we're in TSC offset mode). */
1538	if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
1539	{
1540	/* Restore host's TSC_AUX. */
1541	if (u32HostExtFeatures & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
1542	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
1543
1544	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() +
1545	pVmcb->ctrl.u64TSCOffset - 0x400 /* guestimate of world switch overhead in clock ticks */);
1546	}
1547
1548	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
1549	TMNotifyEndOfExecution(pVCpu);
1550	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
1551	ASMSetFlags(uOldEFlags);
1552	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1553	uOldEFlags = ~(RTCCUINTREG)0;
1554	#endif
1555
1556	/*
1557	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1558	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING-3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1559	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1560	*/
1561
1562	/* Reason for the VM exit */
1563	exitCode = pVmcb->ctrl.u64ExitCode;
1564
1565	if (RT_UNLIKELY(exitCode == (uint64_t)SVM_EXIT_INVALID)) /* Invalid guest state. */
1566	{
1567	HMDumpRegs(pVM, pVCpu, pCtx);
1568	#ifdef DEBUG
1569	Log(("ctrl.u16InterceptRdCRx %x\n", pVmcb->ctrl.u16InterceptRdCRx));
1570	Log(("ctrl.u16InterceptWrCRx %x\n", pVmcb->ctrl.u16InterceptWrCRx));
1571	Log(("ctrl.u16InterceptRdDRx %x\n", pVmcb->ctrl.u16InterceptRdDRx));
1572	Log(("ctrl.u16InterceptWrDRx %x\n", pVmcb->ctrl.u16InterceptWrDRx));
1573	Log(("ctrl.u32InterceptException %x\n", pVmcb->ctrl.u32InterceptException));
1574	Log(("ctrl.u32InterceptCtrl1 %x\n", pVmcb->ctrl.u32InterceptCtrl1));
1575	Log(("ctrl.u32InterceptCtrl2 %x\n", pVmcb->ctrl.u32InterceptCtrl2));
1576	Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
1577	Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
1578	Log(("ctrl.u64TSCOffset %RX64\n", pVmcb->ctrl.u64TSCOffset));
1579
1580	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
1581	Log(("ctrl.TLBCtrl.u8TLBFlush %x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
1582	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
1583
1584	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
1585	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqValid));
1586	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
1587	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVmcb->ctrl.IntCtrl.n.u4VIrqPriority));
1588	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
1589	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
1590	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqMasking));
1591	Log(("ctrl.IntCtrl.u6Reserved %x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
1592	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVmcb->ctrl.IntCtrl.n.u8VIrqVector));
1593	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
1594
1595	Log(("ctrl.u64IntShadow %RX64\n", pVmcb->ctrl.u64IntShadow));
1596	Log(("ctrl.u64ExitCode %RX64\n", pVmcb->ctrl.u64ExitCode));
1597	Log(("ctrl.u64ExitInfo1 %RX64\n", pVmcb->ctrl.u64ExitInfo1));
1598	Log(("ctrl.u64ExitInfo2 %RX64\n", pVmcb->ctrl.u64ExitInfo2));
1599	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
1600	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
1601	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1602	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
1603	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
1604	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
1605	Log(("ctrl.NestedPaging %RX64\n", pVmcb->ctrl.NestedPaging.u));
1606	Log(("ctrl.EventInject.u8Vector %x\n", pVmcb->ctrl.EventInject.n.u8Vector));
1607	Log(("ctrl.EventInject.u3Type %x\n", pVmcb->ctrl.EventInject.n.u3Type));
1608	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
1609	Log(("ctrl.EventInject.u19Reserved %x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
1610	Log(("ctrl.EventInject.u1Valid %x\n", pVmcb->ctrl.EventInject.n.u1Valid));
1611	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
1612
1613	Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
1614	Log(("ctrl.u64LBRVirt %RX64\n", pVmcb->ctrl.u64LBRVirt));
1615
1616	Log(("guest.CS.u16Sel %04X\n", pVmcb->guest.CS.u16Sel));
1617	Log(("guest.CS.u16Attr %04X\n", pVmcb->guest.CS.u16Attr));
1618	Log(("guest.CS.u32Limit %X\n", pVmcb->guest.CS.u32Limit));
1619	Log(("guest.CS.u64Base %RX64\n", pVmcb->guest.CS.u64Base));
1620	Log(("guest.DS.u16Sel %04X\n", pVmcb->guest.DS.u16Sel));
1621	Log(("guest.DS.u16Attr %04X\n", pVmcb->guest.DS.u16Attr));
1622	Log(("guest.DS.u32Limit %X\n", pVmcb->guest.DS.u32Limit));
1623	Log(("guest.DS.u64Base %RX64\n", pVmcb->guest.DS.u64Base));
1624	Log(("guest.ES.u16Sel %04X\n", pVmcb->guest.ES.u16Sel));
1625	Log(("guest.ES.u16Attr %04X\n", pVmcb->guest.ES.u16Attr));
1626	Log(("guest.ES.u32Limit %X\n", pVmcb->guest.ES.u32Limit));
1627	Log(("guest.ES.u64Base %RX64\n", pVmcb->guest.ES.u64Base));
1628	Log(("guest.FS.u16Sel %04X\n", pVmcb->guest.FS.u16Sel));
1629	Log(("guest.FS.u16Attr %04X\n", pVmcb->guest.FS.u16Attr));
1630	Log(("guest.FS.u32Limit %X\n", pVmcb->guest.FS.u32Limit));
1631	Log(("guest.FS.u64Base %RX64\n", pVmcb->guest.FS.u64Base));
1632	Log(("guest.GS.u16Sel %04X\n", pVmcb->guest.GS.u16Sel));
1633	Log(("guest.GS.u16Attr %04X\n", pVmcb->guest.GS.u16Attr));
1634	Log(("guest.GS.u32Limit %X\n", pVmcb->guest.GS.u32Limit));
1635	Log(("guest.GS.u64Base %RX64\n", pVmcb->guest.GS.u64Base));
1636
1637	Log(("guest.GDTR.u32Limit %X\n", pVmcb->guest.GDTR.u32Limit));
1638	Log(("guest.GDTR.u64Base %RX64\n", pVmcb->guest.GDTR.u64Base));
1639
1640	Log(("guest.LDTR.u16Sel %04X\n", pVmcb->guest.LDTR.u16Sel));
1641	Log(("guest.LDTR.u16Attr %04X\n", pVmcb->guest.LDTR.u16Attr));
1642	Log(("guest.LDTR.u32Limit %X\n", pVmcb->guest.LDTR.u32Limit));
1643	Log(("guest.LDTR.u64Base %RX64\n", pVmcb->guest.LDTR.u64Base));
1644
1645	Log(("guest.IDTR.u32Limit %X\n", pVmcb->guest.IDTR.u32Limit));
1646	Log(("guest.IDTR.u64Base %RX64\n", pVmcb->guest.IDTR.u64Base));
1647
1648	Log(("guest.TR.u16Sel %04X\n", pVmcb->guest.TR.u16Sel));
1649	Log(("guest.TR.u16Attr %04X\n", pVmcb->guest.TR.u16Attr));
1650	Log(("guest.TR.u32Limit %X\n", pVmcb->guest.TR.u32Limit));
1651	Log(("guest.TR.u64Base %RX64\n", pVmcb->guest.TR.u64Base));
1652
1653	Log(("guest.u8CPL %X\n", pVmcb->guest.u8CPL));
1654	Log(("guest.u64CR0 %RX64\n", pVmcb->guest.u64CR0));
1655	Log(("guest.u64CR2 %RX64\n", pVmcb->guest.u64CR2));
1656	Log(("guest.u64CR3 %RX64\n", pVmcb->guest.u64CR3));
1657	Log(("guest.u64CR4 %RX64\n", pVmcb->guest.u64CR4));
1658	Log(("guest.u64DR6 %RX64\n", pVmcb->guest.u64DR6));
1659	Log(("guest.u64DR7 %RX64\n", pVmcb->guest.u64DR7));
1660
1661	Log(("guest.u64RIP %RX64\n", pVmcb->guest.u64RIP));
1662	Log(("guest.u64RSP %RX64\n", pVmcb->guest.u64RSP));
1663	Log(("guest.u64RAX %RX64\n", pVmcb->guest.u64RAX));
1664	Log(("guest.u64RFlags %RX64\n", pVmcb->guest.u64RFlags));
1665
1666	Log(("guest.u64SysEnterCS %RX64\n", pVmcb->guest.u64SysEnterCS));
1667	Log(("guest.u64SysEnterEIP %RX64\n", pVmcb->guest.u64SysEnterEIP));
1668	Log(("guest.u64SysEnterESP %RX64\n", pVmcb->guest.u64SysEnterESP));
1669
1670	Log(("guest.u64EFER %RX64\n", pVmcb->guest.u64EFER));
1671	Log(("guest.u64STAR %RX64\n", pVmcb->guest.u64STAR));
1672	Log(("guest.u64LSTAR %RX64\n", pVmcb->guest.u64LSTAR));
1673	Log(("guest.u64CSTAR %RX64\n", pVmcb->guest.u64CSTAR));
1674	Log(("guest.u64SFMASK %RX64\n", pVmcb->guest.u64SFMASK));
1675	Log(("guest.u64KernelGSBase %RX64\n", pVmcb->guest.u64KernelGSBase));
1676	Log(("guest.u64GPAT %RX64\n", pVmcb->guest.u64GPAT));
1677	Log(("guest.u64DBGCTL %RX64\n", pVmcb->guest.u64DBGCTL));
1678	Log(("guest.u64BR_FROM %RX64\n", pVmcb->guest.u64BR_FROM));
1679	Log(("guest.u64BR_TO %RX64\n", pVmcb->guest.u64BR_TO));
1680	Log(("guest.u64LASTEXCPFROM %RX64\n", pVmcb->guest.u64LASTEXCPFROM));
1681	Log(("guest.u64LASTEXCPTO %RX64\n", pVmcb->guest.u64LASTEXCPTO));
1682	#endif
1683	rc = VERR_SVM_UNABLE_TO_START_VM;
1684	VMMR0LogFlushEnable(pVCpu);
1685	goto end;
1686	}
1687
1688	/* Let's first sync back EIP, ESP, and EFLAGS. */
1689	pCtx->rip = pVmcb->guest.u64RIP;
1690	pCtx->rsp = pVmcb->guest.u64RSP;
1691	pCtx->eflags.u32 = pVmcb->guest.u64RFlags;
1692	/* eax is saved/restore across the vmrun instruction */
1693	pCtx->rax = pVmcb->guest.u64RAX;
1694
1695	/*
1696	* Save all the MSRs that can be changed by the guest without causing a world switch.
1697	* FS & GS base are saved with SVM_READ_SELREG.
1698	*/
1699	pCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
1700	pCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
1701	pCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
1702	pCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
1703	pCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
1704	pCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
1705	pCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
1706	pCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
1707
1708	/* Can be updated behind our back in the nested paging case. */
1709	pCtx->cr2 = pVmcb->guest.u64CR2;
1710
1711	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1712	SVM_READ_SELREG(SS, ss);
1713	SVM_READ_SELREG(CS, cs);
1714	SVM_READ_SELREG(DS, ds);
1715	SVM_READ_SELREG(ES, es);
1716	SVM_READ_SELREG(FS, fs);
1717	SVM_READ_SELREG(GS, gs);
1718
1719	/*
1720	* Correct the hidden CS granularity flag. Haven't seen it being wrong in any other
1721	* register (yet).
1722	*/
1723	if ( !pCtx->cs.Attr.n.u1Granularity
1724	&& pCtx->cs.Attr.n.u1Present
1725	&& pCtx->cs.u32Limit > UINT32_C(0xfffff))
1726	{
1727	Assert((pCtx->cs.u32Limit & 0xfff) == 0xfff);
1728	pCtx->cs.Attr.n.u1Granularity = 1;
1729	}
1730	#define SVM_ASSERT_SEL_GRANULARITY(reg) \
1731	AssertMsg( !pCtx->reg.Attr.n.u1Present \
1732	\|\| ( pCtx->reg.Attr.n.u1Granularity \
1733	? (pCtx->reg.u32Limit & 0xfff) == 0xfff \
1734	: pCtx->reg.u32Limit <= 0xfffff), \
1735	("%#x %#x %#llx\n", pCtx->reg.u32Limit, pCtx->reg.Attr.u, pCtx->reg.u64Base))
1736	SVM_ASSERT_SEL_GRANULARITY(ss);
1737	SVM_ASSERT_SEL_GRANULARITY(cs);
1738	SVM_ASSERT_SEL_GRANULARITY(ds);
1739	SVM_ASSERT_SEL_GRANULARITY(es);
1740	SVM_ASSERT_SEL_GRANULARITY(fs);
1741	SVM_ASSERT_SEL_GRANULARITY(gs);
1742	#undef SVM_ASSERT_SEL_GRANULARITY
1743
1744	/*
1745	* Correct the hidden SS DPL field. It can be wrong on certain CPUs
1746	* sometimes (seen it on AMD Fusion CPUs with 64-bit guests). The CPU
1747	* always uses the CPL field in the VMCB instead of the DPL in the hidden
1748	* SS (chapter AMD spec. 15.5.1 Basic operation).
1749	*/
1750	Assert(!(pVmcb->guest.u8CPL & ~0x3));
1751	pCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
1752
1753	/*
1754	* Remaining guest CPU context: TR, IDTR, GDTR, LDTR;
1755	* must sync everything otherwise we can get out of sync when jumping back to ring-3.
1756	*/
1757	SVM_READ_SELREG(LDTR, ldtr);
1758	SVM_READ_SELREG(TR, tr);
1759
1760	pCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
1761	pCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
1762
1763	pCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
1764	pCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
1765
1766	/*
1767	* No reason to sync back the CRx and DRx registers as they cannot be changed by the guest
1768	* unless in the nested paging case where CR3 can be changed by the guest.
1769	*/
1770	if ( pVM->hm.s.fNestedPaging
1771	&& pCtx->cr3 != pVmcb->guest.u64CR3)
1772	{
1773	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
1774	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
1775	}
1776
1777	/* Note! NOW IT'S SAFE FOR LOGGING! */
1778	VMMR0LogFlushEnable(pVCpu);
1779
1780	/* Take care of instruction fusing (sti, mov ss) (see AMD spec. 15.20.5 Interrupt Shadows) */
1781	if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1782	{
1783	Log(("uInterruptState %x rip=%RGv\n", pVmcb->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
1784	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1785	}
1786	else
1787	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1788
1789	Log2(("exitCode = %x\n", exitCode));
1790
1791	/* Sync back DR6 as it could have been changed by hitting breakpoints. */
1792	pCtx->dr[6] = pVmcb->guest.u64DR6;
1793	/* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1794	pCtx->dr[7] = pVmcb->guest.u64DR7;
1795
1796	/* Check if an injected event was interrupted prematurely. */
1797	pVCpu->hm.s.Event.u64IntrInfo = pVmcb->ctrl.ExitIntInfo.u;
1798	if ( pVmcb->ctrl.ExitIntInfo.n.u1Valid
1799	/* we don't care about 'int xx' as the instruction will be restarted. */
1800	&& pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT)
1801	{
1802	Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hm.s.Event.u64IntrInfo, (RTGCPTR)pCtx->rip, exitCode));
1803
1804	#ifdef LOG_ENABLED
1805	SVMEVENT Event;
1806	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
1807
1808	if ( exitCode == SVM_EXIT_EXCEPTION_E
1809	&& Event.n.u8Vector == 0xE)
1810	{
1811	Log(("Double fault!\n"));
1812	}
1813	#endif
1814
1815	pVCpu->hm.s.Event.fPending = true;
1816	/* Error code present? (redundant) */
1817	if (pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1818	pVCpu->hm.s.Event.u32ErrCode = pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode;
1819	else
1820	pVCpu->hm.s.Event.u32ErrCode = 0;
1821	}
1822	#ifdef VBOX_WITH_STATISTICS
1823	if (exitCode == SVM_EXIT_NPF)
1824	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf);
1825	else
1826	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1827	#endif
1828
1829	/* Sync back the TPR if it was changed. */
1830	if (fSyncTPR)
1831	{
1832	if (pVM->hm.s.fTPRPatchingActive)
1833	{
1834	if ((pCtx->msrLSTAR & 0xff) != u8LastTPR)
1835	{
1836	/* Our patch code uses LSTAR for TPR caching. */
1837	rc2 = PDMApicSetTPR(pVCpu, pCtx->msrLSTAR & 0xff);
1838	AssertRC(rc2);
1839	}
1840	}
1841	else
1842	{
1843	if ((uint8_t)(u8LastTPR >> 4) != pVmcb->ctrl.IntCtrl.n.u8VTPR)
1844	{
1845	/* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1846	rc2 = PDMApicSetTPR(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
1847	AssertRC(rc2);
1848	}
1849	}
1850	}
1851
1852	#ifdef DBGFTRACE_ENABLED /** @todo DTrace */
1853	RTTraceBufAddMsgF(pVM->CTX_SUFF(hTraceBuf), "vmexit %08x at %04:%08RX64 %RX64 %RX64 %RX64",
1854	exitCode, pCtx->cs.Sel, pCtx->rip,
1855	pVmcb->ctrl.u64ExitInfo1, pVmcb->ctrl.u64ExitInfo2, pVmcb->ctrl.ExitIntInfo.u);
1856	#endif
1857	#if ARCH_BITS == 64 /* for the time being */
1858	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, exitCode, pVmcb->ctrl.u64ExitInfo1, pVmcb->ctrl.u64ExitInfo2,
1859	pVmcb->ctrl.ExitIntInfo.u, UINT64_MAX);
1860	#endif
1861	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
1862
1863	/* Deal with the reason of the VM-exit. */
1864	switch (exitCode)
1865	{
1866	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1867	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1868	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1869	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1870	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1871	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1872	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1873	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1874	{
1875	/* Pending trap. */
1876	SVMEVENT Event;
1877	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1878
1879	Log2(("Hardware/software interrupt %d\n", vector));
1880	switch (vector)
1881	{
1882	case X86_XCPT_DB:
1883	{
1884	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
1885
1886	/* Note that we don't support guest and host-initiated debugging at the same time. */
1887	Assert(DBGFIsStepping(pVCpu) \|\| CPUMIsHyperDebugStateActive(pVCpu));
1888
1889	rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1890	if (rc == VINF_EM_RAW_GUEST_TRAP)
1891	{
1892	Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
1893
1894	/* Reinject the exception. */
1895	Event.u = 0;
1896	Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1897	Event.n.u1Valid = 1;
1898	Event.n.u8Vector = X86_XCPT_DB;
1899
1900	hmR0SvmSetPendingEvent(pVCpu, &Event);
1901	goto ResumeExecution;
1902	}
1903	/* Return to ring 3 to deal with the debug exit code. */
1904	Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs.Sel, pCtx->rip, VBOXSTRICTRC_VAL(rc)));
1905	break;
1906	}
1907
1908	case X86_XCPT_NM:
1909	{
1910	Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
1911
1912	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1913	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1914	rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
1915	if (rc == VINF_SUCCESS)
1916	{
1917	Assert(CPUMIsGuestFPUStateActive(pVCpu));
1918	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
1919
1920	/* Continue execution. */
1921	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
1922
1923	goto ResumeExecution;
1924	}
1925
1926	Log(("Forward #NM fault to the guest\n"));
1927	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
1928
1929	Event.u = 0;
1930	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1931	Event.n.u1Valid = 1;
1932	Event.n.u8Vector = X86_XCPT_NM;
1933
1934	hmR0SvmSetPendingEvent(pVCpu, &Event);
1935	goto ResumeExecution;
1936	}
1937
1938	case X86_XCPT_PF: /* Page fault */
1939	{
1940	uint32_t errCode = pVmcb->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1941	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1942
1943	#ifdef VBOX_ALWAYS_TRAP_PF
1944	if (pVM->hm.s.fNestedPaging)
1945	{
1946	/*
1947	* A genuine pagefault. Forward the trap to the guest by injecting the exception and resuming execution.
1948	*/
1949	Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip,
1950	uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1951	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
1952
1953	/* Now we must update CR2. */
1954	pCtx->cr2 = uFaultAddress;
1955
1956	Event.u = 0;
1957	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1958	Event.n.u1Valid = 1;
1959	Event.n.u8Vector = X86_XCPT_PF;
1960	Event.n.u1ErrorCodeValid = 1;
1961	Event.n.u32ErrorCode = errCode;
1962
1963	hmR0SvmSetPendingEvent(pVCpu, &Event);
1964	goto ResumeExecution;
1965	}
1966	#endif
1967	Assert(!pVM->hm.s.fNestedPaging);
1968
1969	#ifdef VBOX_HM_WITH_GUEST_PATCHING
1970	/* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1971	if ( pVM->hm.s.fTRPPatchingAllowed
1972	&& (uFaultAddress & 0xfff) == 0x080
1973	&& !(errCode & X86_TRAP_PF_P) /* not present */
1974	&& CPUMGetGuestCPL(pVCpu) == 0
1975	&& !CPUMIsGuestInLongModeEx(pCtx)
1976	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
1977	{
1978	RTGCPHYS GCPhysApicBase, GCPhys;
1979	GCPhysApicBase = pCtx->msrApicBase;
1980	GCPhysApicBase &= PAGE_BASE_GC_MASK;
1981
1982	rc = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL, &GCPhys);
1983	if ( rc == VINF_SUCCESS
1984	&& GCPhys == GCPhysApicBase)
1985	{
1986	/* Only attempt to patch the instruction once. */
1987	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1988	if (!pPatch)
1989	{
1990	rc = VINF_EM_HM_PATCH_TPR_INSTR;
1991	break;
1992	}
1993	}
1994	}
1995	#endif
1996
1997	Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1998	/* Exit qualification contains the linear address of the page fault. */
1999	TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
2000	TRPMSetErrorCode(pVCpu, errCode);
2001	TRPMSetFaultAddress(pVCpu, uFaultAddress);
2002
2003	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
2004	rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
2005	Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc)));
2006	if (rc == VINF_SUCCESS)
2007	{
2008	/* We've successfully synced our shadow pages, so let's just continue execution. */
2009	Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
2010	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
2011
2012	TRPMResetTrap(pVCpu);
2013	goto ResumeExecution;
2014	}
2015	else if (rc == VINF_EM_RAW_GUEST_TRAP)
2016	{
2017	/*
2018	* A genuine pagefault. Forward the trap to the guest by injecting the exception and resuming execution.
2019	*/
2020	Log2(("Forward page fault to the guest\n"));
2021	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
2022	/* The error code might have been changed. */
2023	errCode = TRPMGetErrorCode(pVCpu);
2024
2025	TRPMResetTrap(pVCpu);
2026
2027	/* Now we must update CR2. */
2028	pCtx->cr2 = uFaultAddress;
2029
2030	Event.u = 0;
2031	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2032	Event.n.u1Valid = 1;
2033	Event.n.u8Vector = X86_XCPT_PF;
2034	Event.n.u1ErrorCodeValid = 1;
2035	Event.n.u32ErrorCode = errCode;
2036
2037	hmR0SvmSetPendingEvent(pVCpu, &Event);
2038	goto ResumeExecution;
2039	}
2040	#ifdef VBOX_STRICT
2041	if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
2042	LogFlow(("PGMTrap0eHandler failed with %d\n", VBOXSTRICTRC_VAL(rc)));
2043	#endif
2044	/* Need to go back to the recompiler to emulate the instruction. */
2045	TRPMResetTrap(pVCpu);
2046	break;
2047	}
2048
2049	case X86_XCPT_MF: /* Floating point exception. */
2050	{
2051	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
2052	if (!(pCtx->cr0 & X86_CR0_NE))
2053	{
2054	/* old style FPU error reporting needs some extra work. */
2055	/** @todo don't fall back to the recompiler, but do it manually. */
2056	rc = VINF_EM_RAW_EMULATE_INSTR;
2057	break;
2058	}
2059	Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
2060
2061	Event.u = 0;
2062	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2063	Event.n.u1Valid = 1;
2064	Event.n.u8Vector = X86_XCPT_MF;
2065
2066	hmR0SvmSetPendingEvent(pVCpu, &Event);
2067	goto ResumeExecution;
2068	}
2069
2070	#ifdef VBOX_STRICT
2071	case X86_XCPT_BP: /* Breakpoint. */
2072	case X86_XCPT_GP: /* General protection failure exception.*/
2073	case X86_XCPT_UD: /* Unknown opcode exception. */
2074	case X86_XCPT_DE: /* Divide error. */
2075	case X86_XCPT_SS: /* Stack segment exception. */
2076	case X86_XCPT_NP: /* Segment not present exception. */
2077	{
2078	Event.u = 0;
2079	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2080	Event.n.u1Valid = 1;
2081	Event.n.u8Vector = vector;
2082
2083	switch (vector)
2084	{
2085	case X86_XCPT_GP:
2086	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
2087	Event.n.u1ErrorCodeValid = 1;
2088	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
2089	break;
2090	case X86_XCPT_BP:
2091	/** Saves the wrong EIP on the stack (pointing to the int3 instead of the next instruction. */
2092	break;
2093	case X86_XCPT_DE:
2094	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
2095	break;
2096	case X86_XCPT_UD:
2097	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
2098	break;
2099	case X86_XCPT_SS:
2100	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
2101	Event.n.u1ErrorCodeValid = 1;
2102	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
2103	break;
2104	case X86_XCPT_NP:
2105	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
2106	Event.n.u1ErrorCodeValid = 1;
2107	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
2108	break;
2109	}
2110	Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip, pCtx->esi));
2111	hmR0SvmSetPendingEvent(pVCpu, &Event);
2112	goto ResumeExecution;
2113	}
2114	#endif
2115	default:
2116	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
2117	rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
2118	break;
2119
2120	} /* switch (vector) */
2121	break;
2122	}
2123
2124	case SVM_EXIT_NPF:
2125	{
2126	/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
2127	uint32_t errCode = pVmcb->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
2128	RTGCPHYS GCPhysFault = pVmcb->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
2129	PGMMODE enmShwPagingMode;
2130
2131	Assert(pVM->hm.s.fNestedPaging);
2132	LogFlow(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, GCPhysFault, errCode));
2133
2134	#ifdef VBOX_HM_WITH_GUEST_PATCHING
2135	/* Shortcut for APIC TPR reads and writes; 32 bits guests only */
2136	if ( pVM->hm.s.fTRPPatchingAllowed
2137	&& (GCPhysFault & PAGE_OFFSET_MASK) == 0x080
2138	&& ( !(errCode & X86_TRAP_PF_P) /* not present */
2139	\|\| (errCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD) /* mmio optimization */)
2140	&& CPUMGetGuestCPL(pVCpu) == 0
2141	&& !CPUMIsGuestInLongModeEx(pCtx)
2142	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
2143	{
2144	RTGCPHYS GCPhysApicBase = pCtx->msrApicBase;
2145	GCPhysApicBase &= PAGE_BASE_GC_MASK;
2146
2147	if (GCPhysFault == GCPhysApicBase + 0x80)
2148	{
2149	/* Only attempt to patch the instruction once. */
2150	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2151	if (!pPatch)
2152	{
2153	rc = VINF_EM_HM_PATCH_TPR_INSTR;
2154	break;
2155	}
2156	}
2157	}
2158	#endif
2159
2160	/* Handle the pagefault trap for the nested shadow table. */
2161	#if HC_ARCH_BITS == 32 /** @todo shadow this in a variable. */
2162	if (CPUMIsGuestInLongModeEx(pCtx))
2163	enmShwPagingMode = PGMMODE_AMD64_NX;
2164	else
2165	#endif
2166	enmShwPagingMode = PGMGetHostMode(pVM);
2167
2168	/* MMIO optimization */
2169	Assert((errCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
2170	if ((errCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2171	{
2172	rc = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmShwPagingMode, CPUMCTX2CORE(pCtx), GCPhysFault, errCode);
2173
2174	/*
2175	* If we succeed, resume execution.
2176	* Or, if fail in interpreting the instruction because we couldn't get the guest physical address
2177	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
2178	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
2179	* weird case. See @bugref{6043}.
2180	*/
2181	if ( rc == VINF_SUCCESS
2182	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
2183	\|\| rc == VERR_PAGE_NOT_PRESENT)
2184	{
2185	Log2(("PGMR0Trap0eHandlerNPMisconfig(,,,%RGp) at %RGv -> resume\n", GCPhysFault, (RTGCPTR)pCtx->rip));
2186	goto ResumeExecution;
2187	}
2188	Log2(("PGMR0Trap0eHandlerNPMisconfig(,,,%RGp) at %RGv -> resume\n", GCPhysFault, (RTGCPTR)pCtx->rip));
2189	break;
2190	}
2191
2192	/* Exit qualification contains the linear address of the page fault. */
2193	TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
2194	TRPMSetErrorCode(pVCpu, errCode);
2195	TRPMSetFaultAddress(pVCpu, GCPhysFault);
2196
2197	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), GCPhysFault);
2198	Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, VBOXSTRICTRC_VAL(rc)));
2199
2200	/*
2201	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
2202	*/
2203	if ( rc == VINF_SUCCESS
2204	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
2205	\|\| rc == VERR_PAGE_NOT_PRESENT)
2206	{
2207	/* We've successfully synced our shadow pages, so let's just continue execution. */
2208	Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, GCPhysFault, errCode));
2209	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
2210
2211	TRPMResetTrap(pVCpu);
2212	goto ResumeExecution;
2213	}
2214
2215	#ifdef VBOX_STRICT
2216	if (rc != VINF_EM_RAW_EMULATE_INSTR)
2217	LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", VBOXSTRICTRC_VAL(rc)));
2218	#endif
2219	/* Need to go back to the recompiler to emulate the instruction. */
2220	TRPMResetTrap(pVCpu);
2221	break;
2222	}
2223
2224	case SVM_EXIT_VINTR:
2225	/* A virtual interrupt is about to be delivered, which means IF=1. */
2226	Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
2227	pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 0;
2228	pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0;
2229	goto ResumeExecution;
2230
2231	case SVM_EXIT_INTR:
2232	case SVM_EXIT_FERR_FREEZE:
2233	case SVM_EXIT_NMI:
2234	case SVM_EXIT_SMI:
2235	case SVM_EXIT_INIT:
2236	if (exitCode == SVM_EXIT_INTR)
2237	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
2238	else if (exitCode == SVM_EXIT_NMI)
2239	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmi);
2240
2241	/* External interrupt; leave to allow it to be dispatched again. */
2242	rc = VINF_EM_RAW_INTERRUPT;
2243	break;
2244
2245	case SVM_EXIT_WBINVD:
2246	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
2247	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
2248	/* Skip instruction and continue directly. */
2249	pCtx->rip += 2; /* Note! hardcoded opcode size! */
2250	/* Continue execution.*/
2251	goto ResumeExecution;
2252
2253	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
2254	{
2255	Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
2256	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
2257	rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2258	if (rc == VINF_SUCCESS)
2259	{
2260	/* Update EIP and continue execution. */
2261	pCtx->rip += 2; /* Note! hardcoded opcode size! */
2262	goto ResumeExecution;
2263	}
2264	AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
2265	rc = VINF_EM_RAW_EMULATE_INSTR;
2266	break;
2267	}
2268
2269	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
2270	{
2271	Log2(("SVM: Rdtsc\n"));
2272	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
2273	rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2274	if (rc == VINF_SUCCESS)
2275	{
2276	/* Update EIP and continue execution. */
2277	pCtx->rip += 2; /* Note! hardcoded opcode size! */
2278	goto ResumeExecution;
2279	}
2280	rc = VINF_EM_RAW_EMULATE_INSTR;
2281	break;
2282	}
2283
2284	case SVM_EXIT_RDPMC: /* Guest software attempted to execute RDPMC. */
2285	{
2286	Log2(("SVM: Rdpmc %x\n", pCtx->ecx));
2287	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
2288	rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2289	if (rc == VINF_SUCCESS)
2290	{
2291	/* Update EIP and continue execution. */
2292	pCtx->rip += 2; /* Note! hardcoded opcode size! */
2293	goto ResumeExecution;
2294	}
2295	rc = VINF_EM_RAW_EMULATE_INSTR;
2296	break;
2297	}
2298
2299	case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
2300	{
2301	Log2(("SVM: Rdtscp\n"));
2302	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
2303	rc = EMInterpretRdtscp(pVM, pVCpu, pCtx);
2304	if (rc == VINF_SUCCESS)
2305	{
2306	/* Update EIP and continue execution. */
2307	pCtx->rip += 3; /* Note! hardcoded opcode size! */
2308	goto ResumeExecution;
2309	}
2310	AssertMsgFailed(("EMU: rdtscp failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
2311	rc = VINF_EM_RAW_EMULATE_INSTR;
2312	break;
2313	}
2314
2315	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVLPG. */
2316	{
2317	Log2(("SVM: invlpg\n"));
2318	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
2319
2320	Assert(!pVM->hm.s.fNestedPaging);
2321
2322	/* Truly a pita. Why can't SVM give the same information as VT-x? */
2323	rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2324	if (rc == VINF_SUCCESS)
2325	{
2326	goto ResumeExecution; /* eip already updated */
2327	}
2328	break;
2329	}
2330
2331	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
2332	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
2333	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
2334	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
2335	{
2336	Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
2337	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxWrite[exitCode - SVM_EXIT_WRITE_CR0]);
2338	rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0);
2339
2340	switch (exitCode - SVM_EXIT_WRITE_CR0)
2341	{
2342	case 0:
2343	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0;
2344	break;
2345	case 2:
2346	break;
2347	case 3:
2348	Assert(!pVM->hm.s.fNestedPaging);
2349	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR3;
2350	break;
2351	case 4:
2352	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR4;
2353	break;
2354	case 8:
2355	break;
2356	default:
2357	AssertFailed();
2358	}
2359	if (rc == VINF_SUCCESS)
2360	{
2361	/* EIP has been updated already. */
2362	/* Only resume if successful. */
2363	goto ResumeExecution;
2364	}
2365	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
2366	break;
2367	}
2368
2369	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
2370	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
2371	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
2372	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
2373	{
2374	Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
2375	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[exitCode - SVM_EXIT_READ_CR0]);
2376	rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0);
2377	if (rc == VINF_SUCCESS)
2378	{
2379	/* EIP has been updated already. */
2380	/* Only resume if successful. */
2381	goto ResumeExecution;
2382	}
2383	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
2384	break;
2385	}
2386
2387	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
2388	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
2389	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
2390	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
2391	{
2392	Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
2393	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
2394
2395	if ( !DBGFIsStepping(pVCpu)
2396	&& !CPUMIsHyperDebugStateActive(pVCpu))
2397	{
2398	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
2399
2400	/* Disable drx move intercepts. */
2401	pVmcb->ctrl.u16InterceptRdDRx = 0;
2402	pVmcb->ctrl.u16InterceptWrDRx = 0;
2403
2404	/* Save the host and load the guest debug state. */
2405	rc2 = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2406	AssertRC(rc2);
2407	goto ResumeExecution;
2408	}
2409
2410	rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0);
2411	if (rc == VINF_SUCCESS)
2412	{
2413	/* EIP has been updated already. */
2414	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
2415
2416	/* Only resume if successful. */
2417	goto ResumeExecution;
2418	}
2419	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
2420	break;
2421	}
2422
2423	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
2424	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
2425	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
2426	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
2427	{
2428	Log2(("SVM: %RGv mov x, dr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
2429	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
2430
2431	if (!DBGFIsStepping(pVCpu))
2432	{
2433	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
2434
2435	/* Disable DRx move intercepts. */
2436	pVmcb->ctrl.u16InterceptRdDRx = 0;
2437	pVmcb->ctrl.u16InterceptWrDRx = 0;
2438
2439	/* Save the host and load the guest debug state. */
2440	rc2 = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2441	AssertRC(rc2);
2442	goto ResumeExecution;
2443	}
2444
2445	rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0);
2446	if (rc == VINF_SUCCESS)
2447	{
2448	/* EIP has been updated already. */
2449	/* Only resume if successful. */
2450	goto ResumeExecution;
2451	}
2452	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
2453	break;
2454	}
2455
2456	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2457	case SVM_EXIT_IOIO: /* I/O instruction. */
2458	{
2459	SVMIOIOEXIT IoExitInfo;
2460
2461	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
2462	unsigned uIdx = (IoExitInfo.u >> 4) & 0x7;
2463	uint32_t uIOSize = g_aIOSize[uIdx];
2464	uint32_t uAndVal = g_aIOOpAnd[uIdx];
2465	if (RT_UNLIKELY(!uIOSize))
2466	{
2467	AssertFailed(); /* should be fatal. */
2468	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo r=ramshankar: would this really fall back to the recompiler and work? */
2469	break;
2470	}
2471
2472	if (IoExitInfo.n.u1STR)
2473	{
2474	/* ins/outs */
2475	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2476
2477	/* Disassemble manually to deal with segment prefixes. */
2478	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
2479	if (rc == VINF_SUCCESS)
2480	{
2481	if (IoExitInfo.n.u1Type == 0)
2482	{
2483	Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2484	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
2485	rc = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
2486	(DISCPUMODE)pDis->uAddrMode, uIOSize);
2487	}
2488	else
2489	{
2490	Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2491	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
2492	rc = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
2493	(DISCPUMODE)pDis->uAddrMode, uIOSize);
2494	}
2495	}
2496	else
2497	rc = VINF_EM_RAW_EMULATE_INSTR;
2498	}
2499	else
2500	{
2501	/* Normal in/out */
2502	Assert(!IoExitInfo.n.u1REP);
2503
2504	if (IoExitInfo.n.u1Type == 0)
2505	{
2506	Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal,
2507	uIOSize));
2508	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
2509	rc = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
2510	if (rc == VINF_IOM_R3_IOPORT_WRITE)
2511	{
2512	HMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port,
2513	uAndVal, uIOSize);
2514	}
2515	}
2516	else
2517	{
2518	uint32_t u32Val = 0;
2519
2520	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
2521	rc = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, uIOSize);
2522	if (IOM_SUCCESS(rc))
2523	{
2524	/* Write back to the EAX register. */
2525	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
2526	Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal,
2527	uIOSize));
2528	}
2529	else if (rc == VINF_IOM_R3_IOPORT_READ)
2530	{
2531	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port,
2532	uAndVal, uIOSize);
2533	}
2534	}
2535	}
2536
2537	/*
2538	* Handled the I/O return codes.
2539	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2540	*/
2541	if (IOM_SUCCESS(rc))
2542	{
2543	/* Update EIP and continue execution. */
2544	pCtx->rip = pVmcb->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
2545	if (RT_LIKELY(rc == VINF_SUCCESS))
2546	{
2547	/* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2548	if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2549	{
2550	/* IO operation lookup arrays. */
2551	static uint32_t const aIOSize[4] = { 1, 2, 0, 4 };
2552
2553	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
2554	for (unsigned i = 0; i < 4; i++)
2555	{
2556	unsigned uBPLen = aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2557
2558	if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
2559	&& (pCtx->dr[7] & (X86_DR7_L(i) \| X86_DR7_G(i)))
2560	&& (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2561	{
2562	SVMEVENT Event;
2563
2564	Assert(CPUMIsGuestDebugStateActive(pVCpu));
2565
2566	/* Clear all breakpoint status flags and set the one we just hit. */
2567	pCtx->dr[6] &= ~(X86_DR6_B0\|X86_DR6_B1\|X86_DR6_B2\|X86_DR6_B3);
2568	pCtx->dr[6] \|= (uint64_t)RT_BIT(i);
2569
2570	/*
2571	* Note: AMD64 Architecture Programmer's Manual 13.1:
2572	* Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared
2573	* by software after the contents have been read.
2574	*/
2575	pVmcb->guest.u64DR6 = pCtx->dr[6];
2576
2577	/* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2578	pCtx->dr[7] &= ~X86_DR7_GD;
2579
2580	/* Paranoia. */
2581	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2582	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
2583	pCtx->dr[7] \|= 0x400; /* must be one */
2584
2585	pVmcb->guest.u64DR7 = pCtx->dr[7];
2586
2587	/* Inject the exception. */
2588	Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
2589
2590	Event.u = 0;
2591	Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
2592	Event.n.u1Valid = 1;
2593	Event.n.u8Vector = X86_XCPT_DB;
2594
2595	hmR0SvmSetPendingEvent(pVCpu, &Event);
2596	goto ResumeExecution;
2597	}
2598	}
2599	}
2600	goto ResumeExecution;
2601	}
2602	Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize,
2603	VBOXSTRICTRC_VAL(rc)));
2604	break;
2605	}
2606
2607	#ifdef VBOX_STRICT
2608	if (rc == VINF_IOM_R3_IOPORT_READ)
2609	Assert(IoExitInfo.n.u1Type != 0);
2610	else if (rc == VINF_IOM_R3_IOPORT_WRITE)
2611	Assert(IoExitInfo.n.u1Type == 0);
2612	else
2613	{
2614	AssertMsg( RT_FAILURE(rc)
2615	\|\| rc == VINF_EM_RAW_EMULATE_INSTR
2616	\|\| rc == VINF_EM_RAW_GUEST_TRAP
2617	\|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rc)));
2618	}
2619	#endif
2620	Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2621	break;
2622	}
2623
2624	case SVM_EXIT_HLT:
2625	/* Check if external interrupts are pending; if so, don't switch back. */
2626	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
2627	pCtx->rip++; /* skip hlt */
2628	if (EMShouldContinueAfterHalt(pVCpu, pCtx))
2629	goto ResumeExecution;
2630
2631	rc = VINF_EM_HALT;
2632	break;
2633
2634	case SVM_EXIT_MWAIT:
2635	Log2(("SVM: mwait\n"));
2636	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
2637	rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2638	if ( rc == VINF_EM_HALT
2639	\|\| rc == VINF_SUCCESS)
2640	{
2641	/* Update EIP and continue execution. */
2642	pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2643
2644	/* Check if external interrupts are pending; if so, don't switch back. */
2645	if ( rc == VINF_SUCCESS
2646	\|\| ( rc == VINF_EM_HALT
2647	&& EMShouldContinueAfterHalt(pVCpu, pCtx))
2648	)
2649	goto ResumeExecution;
2650	}
2651	AssertMsg(rc == VERR_EM_INTERPRETER \|\| rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
2652	break;
2653
2654	case SVM_EXIT_MONITOR:
2655	{
2656	Log2(("SVM: monitor\n"));
2657
2658	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
2659	rc = EMInterpretMonitor(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2660	if (rc == VINF_SUCCESS)
2661	{
2662	/* Update EIP and continue execution. */
2663	pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2664	goto ResumeExecution;
2665	}
2666	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: monitor failed with %Rrc\n", VBOXSTRICTRC_VAL(rc)));
2667	break;
2668	}
2669
2670	case SVM_EXIT_VMMCALL:
2671	rc = hmR0SvmEmulateTprVMMCall(pVM, pVCpu, pCtx);
2672	if (rc == VINF_SUCCESS)
2673	{
2674	goto ResumeExecution; /* rip already updated. */
2675	}
2676	/* no break */
2677
2678	case SVM_EXIT_RSM:
2679	case SVM_EXIT_INVLPGA:
2680	case SVM_EXIT_VMRUN:
2681	case SVM_EXIT_VMLOAD:
2682	case SVM_EXIT_VMSAVE:
2683	case SVM_EXIT_STGI:
2684	case SVM_EXIT_CLGI:
2685	case SVM_EXIT_SKINIT:
2686	{
2687	/* Unsupported instructions. */
2688	SVMEVENT Event;
2689
2690	Event.u = 0;
2691	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2692	Event.n.u1Valid = 1;
2693	Event.n.u8Vector = X86_XCPT_UD;
2694
2695	Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
2696	hmR0SvmSetPendingEvent(pVCpu, &Event);
2697	goto ResumeExecution;
2698	}
2699
2700	/* Emulate in ring-3. */
2701	case SVM_EXIT_MSR:
2702	{
2703	/* When an interrupt is pending, we'll let MSR_K8_LSTAR writes fault in our TPR patch code. */
2704	if ( pVM->hm.s.fTPRPatchingActive
2705	&& pCtx->ecx == MSR_K8_LSTAR
2706	&& pVmcb->ctrl.u64ExitInfo1 == 1 /* wrmsr */)
2707	{
2708	if ((pCtx->eax & 0xff) != u8LastTPR)
2709	{
2710	Log(("SVM: Faulting MSR_K8_LSTAR write with new TPR value %x\n", pCtx->eax & 0xff));
2711
2712	/* Our patch code uses LSTAR for TPR caching. */
2713	rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
2714	AssertRC(rc2);
2715	}
2716
2717	/* Skip the instruction and continue. */
2718	pCtx->rip += 2; /* wrmsr = [0F 30] */
2719
2720	/* Only resume if successful. */
2721	goto ResumeExecution;
2722	}
2723
2724	/*
2725	* The Intel spec. claims there's an REX version of RDMSR that's slightly different,
2726	* so we play safe by completely disassembling the instruction.
2727	*/
2728	STAM_COUNTER_INC((pVmcb->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hm.s.StatExitRdmsr : &pVCpu->hm.s.StatExitWrmsr);
2729	Log(("SVM: %s\n", (pVmcb->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
2730	rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0);
2731	if (rc == VINF_SUCCESS)
2732	{
2733	/* EIP has been updated already. */
2734	/* Only resume if successful. */
2735	goto ResumeExecution;
2736	}
2737	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVmcb->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr",
2738	VBOXSTRICTRC_VAL(rc)));
2739	break;
2740	}
2741
2742	case SVM_EXIT_TASK_SWITCH: /* too complicated to emulate, so fall back to the recompiler */
2743	Log(("SVM_EXIT_TASK_SWITCH: exit2=%RX64\n", pVmcb->ctrl.u64ExitInfo2));
2744	if ( !(pVmcb->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET \| SVM_EXIT2_TASK_SWITCH_JMP))
2745	&& pVCpu->hm.s.Event.fPending)
2746	{
2747	SVMEVENT Event;
2748	Event.u = pVCpu->hm.s.Event.u64IntrInfo;
2749
2750	/* Caused by an injected interrupt. */
2751	pVCpu->hm.s.Event.fPending = false;
2752	switch (Event.n.u3Type)
2753	{
2754	case SVM_EVENT_EXTERNAL_IRQ:
2755	case SVM_EVENT_NMI:
2756	Log(("SVM_EXIT_TASK_SWITCH: reassert trap %d\n", Event.n.u8Vector));
2757	Assert(!Event.n.u1ErrorCodeValid);
2758	rc2 = TRPMAssertTrap(pVCpu, Event.n.u8Vector, TRPM_HARDWARE_INT);
2759	AssertRC(rc2);
2760	break;
2761
2762	default:
2763	/* Exceptions and software interrupts can just be restarted. */
2764	break;
2765	}
2766	}
2767	rc = VERR_EM_INTERPRETER;
2768	break;
2769
2770	case SVM_EXIT_PAUSE:
2771	case SVM_EXIT_MWAIT_ARMED:
2772	rc = VERR_EM_INTERPRETER;
2773	break;
2774
2775	case SVM_EXIT_SHUTDOWN:
2776	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2777	break;
2778
2779	case SVM_EXIT_IDTR_READ:
2780	case SVM_EXIT_GDTR_READ:
2781	case SVM_EXIT_LDTR_READ:
2782	case SVM_EXIT_TR_READ:
2783	case SVM_EXIT_IDTR_WRITE:
2784	case SVM_EXIT_GDTR_WRITE:
2785	case SVM_EXIT_LDTR_WRITE:
2786	case SVM_EXIT_TR_WRITE:
2787	case SVM_EXIT_CR0_SEL_WRITE:
2788	default:
2789	/* Unexpected exit codes. */
2790	rc = VERR_SVM_UNEXPECTED_EXIT;
2791	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2792	break;
2793	}
2794
2795	end:
2796
2797	/*
2798	* We are now going back to ring-3, so clear the forced action flag.
2799	*/
2800	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2801
2802	/*
2803	* Signal changes to the recompiler.
2804	*/
2805	CPUMSetChangedFlags(pVCpu,
2806	CPUM_CHANGED_SYSENTER_MSR
2807	\| CPUM_CHANGED_LDTR
2808	\| CPUM_CHANGED_GDTR
2809	\| CPUM_CHANGED_IDTR
2810	\| CPUM_CHANGED_TR
2811	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2812
2813	/*
2814	* If we executed vmrun and an external IRQ was pending, then we don't have to do a full sync the next time.
2815	*/
2816	if (exitCode == SVM_EXIT_INTR)
2817	{
2818	/* On the next entry we'll only sync the host context. */
2819	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT;
2820	}
2821	else
2822	{
2823	/* On the next entry we'll sync everything. */
2824	/** @todo we can do better than this */
2825	/* Not in the VINF_PGM_CHANGE_MODE though! */
2826	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
2827	}
2828
2829	/* Translate into a less severe return code */
2830	if (rc == VERR_EM_INTERPRETER)
2831	rc = VINF_EM_RAW_EMULATE_INSTR;
2832
2833	/* Just set the correct state here instead of trying to catch every goto above. */
2834	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2835
2836	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2837	/* Restore interrupts if we exitted after disabling them. */
2838	if (uOldEFlags != ~(RTCCUINTREG)0)
2839	ASMSetFlags(uOldEFlags);
2840	#endif
2841
2842	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
2843	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
2844	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
2845	return VBOXSTRICTRC_TODO(rc);
2846	}
2847
2848
2849	/**
2850	* Emulate simple mov tpr instruction.
2851	*
2852	* @returns VBox status code.
2853	* @param pVM Pointer to the VM.
2854	* @param pVCpu Pointer to the VMCPU.
2855	* @param pCtx Pointer to the guest CPU context.
2856	*/
2857	static int hmR0SvmEmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2858	{
2859	int rc;
2860
2861	LogFlow(("Emulated VMMCall TPR access replacement at %RGv\n", pCtx->rip));
2862
2863	for (;;)
2864	{
2865	bool fPending;
2866	uint8_t u8Tpr;
2867
2868	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2869	if (!pPatch)
2870	break;
2871
2872	switch (pPatch->enmType)
2873	{
2874	case HMTPRINSTR_READ:
2875	/* TPR caching in CR8 */
2876	rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
2877	AssertRC(rc);
2878
2879	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
2880	AssertRC(rc);
2881
2882	LogFlow(("Emulated read successfully\n"));
2883	pCtx->rip += pPatch->cbOp;
2884	break;
2885
2886	case HMTPRINSTR_WRITE_REG:
2887	case HMTPRINSTR_WRITE_IMM:
2888	/* Fetch the new TPR value */
2889	if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
2890	{
2891	uint32_t val;
2892
2893	rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &val);
2894	AssertRC(rc);
2895	u8Tpr = val;
2896	}
2897	else
2898	u8Tpr = (uint8_t)pPatch->uSrcOperand;
2899
2900	rc = PDMApicSetTPR(pVCpu, u8Tpr);
2901	AssertRC(rc);
2902	LogFlow(("Emulated write successfully\n"));
2903	pCtx->rip += pPatch->cbOp;
2904	break;
2905
2906	default:
2907	AssertMsgFailedReturn(("Unexpected type %d\n", pPatch->enmType), VERR_SVM_UNEXPECTED_PATCH_TYPE);
2908	}
2909	}
2910	return VINF_SUCCESS;
2911	}
2912
2913
2914	/**
2915	* Enters the AMD-V session.
2916	*
2917	* @returns VBox status code.
2918	* @param pVM Pointer to the VM.
2919	* @param pVCpu Pointer to the VMCPU.
2920	* @param pCpu Pointer to the CPU info struct.
2921	*/
2922	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu)
2923	{
2924	Assert(pVM->hm.s.svm.fSupported);
2925
2926	LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hm.s.idLastCpu, pVCpu->hm.s.uCurrentAsid));
2927	pVCpu->hm.s.fResumeVM = false;
2928
2929	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2930	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_LDTR; /** @todo r=ramshankar: I can't understand what effect this will have.
2931	Probably a left over? */
2932
2933	return VINF_SUCCESS;
2934	}
2935
2936
2937	/**
2938	* Leaves the AMD-V session.
2939	*
2940	* @returns VBox status code.
2941	* @param pVM Pointer to the VM.
2942	* @param pVCpu Pointer to the VMCPU.
2943	* @param pCtx Pointer to the guest CPU context.
2944	*/
2945	VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2946	{
2947	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2948
2949	Assert(pVM->hm.s.svm.fSupported);
2950
2951	#ifdef DEBUG
2952	if (CPUMIsHyperDebugStateActive(pVCpu))
2953	{
2954	CPUMR0LoadHostDebugState(pVM, pVCpu);
2955	}
2956	else
2957	#endif
2958	/* Save the guest debug state if necessary. */
2959	if (CPUMIsGuestDebugStateActive(pVCpu))
2960	{
2961	CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
2962
2963	/* Intercept all DRx reads and writes again. Changed later on. */
2964	pVmcb->ctrl.u16InterceptRdDRx = 0xFFFF;
2965	pVmcb->ctrl.u16InterceptWrDRx = 0xFFFF;
2966
2967	/* Resync the debug registers the next time. */
2968	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
2969	}
2970	else
2971	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xFFFF && pVmcb->ctrl.u16InterceptWrDRx == 0xFFFF);
2972
2973	return VINF_SUCCESS;
2974	}
2975
2976
2977	/**
2978	* Worker for Interprets INVLPG.
2979	*
2980	* @return VBox status code.
2981	* @param pVCpu Pointer to the VMCPU.
2982	* @param pCpu Pointer to the CPU info struct.
2983	* @param pRegFrame Pointer to the register frame.
2984	*/
2985	static int hmR0svmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame)
2986	{
2987	DISQPVPARAMVAL param1;
2988	RTGCPTR addr;
2989
2990	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->Param1, &param1, DISQPVWHICH_SRC);
2991	if (RT_FAILURE(rc))
2992	return VERR_EM_INTERPRETER;
2993
2994	switch (param1.type)
2995	{
2996	case DISQPV_TYPE_IMMEDIATE:
2997	case DISQPV_TYPE_ADDRESS:
2998	if (!(param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
2999	return VERR_EM_INTERPRETER;
3000	addr = param1.val.val64;
3001	break;
3002
3003	default:
3004	return VERR_EM_INTERPRETER;
3005	}
3006
3007	/** @todo is addr always a flat linear address or ds based
3008	* (in absence of segment override prefixes)????
3009	*/
3010	rc = PGMInvalidatePage(pVCpu, addr);
3011	if (RT_SUCCESS(rc))
3012	return VINF_SUCCESS;
3013
3014	AssertRC(rc);
3015	return rc;
3016	}
3017
3018
3019	/**
3020	* Interprets INVLPG.
3021	*
3022	* @returns VBox status code.
3023	* @retval VINF_* Scheduling instructions.
3024	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3025	* @retval VERR_* Fatal errors.
3026	*
3027	* @param pVM Pointer to the VM.
3028	* @param pRegFrame Pointer to the register frame.
3029	*
3030	* @remarks Updates the EIP if an instruction was executed successfully.
3031	*/
3032	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
3033	{
3034	/*
3035	* Only allow 32 & 64 bit code.
3036	*/
3037	if (CPUMGetGuestCodeBits(pVCpu) != 16)
3038	{
3039	PDISSTATE pDis = &pVCpu->hm.s.DisState;
3040	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
3041	if (RT_SUCCESS(rc) && pDis->pCurInstr->uOpcode == OP_INVLPG)
3042	{
3043	rc = hmR0svmInterpretInvlPgEx(pVCpu, pDis, pRegFrame);
3044	if (RT_SUCCESS(rc))
3045	pRegFrame->rip += pDis->cbInstr; /* Move on to the next instruction. */
3046	return rc;
3047	}
3048	}
3049	return VERR_EM_INTERPRETER;
3050	}
3051
3052
3053	/**
3054	* Invalidates a guest page by guest virtual address.
3055	*
3056	* @returns VBox status code.
3057	* @param pVM Pointer to the VM.
3058	* @param pVCpu Pointer to the VMCPU.
3059	* @param GCVirt Guest virtual address of the page to invalidate.
3060	*/
3061	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
3062	{
3063	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
3064
3065	/* Skip it if a TLB flush is already pending. */
3066	if (!fFlushPending)
3067	{
3068	PSVMVMCB pVmcb;
3069
3070	Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
3071	AssertReturn(pVM, VERR_INVALID_PARAMETER);
3072	Assert(pVM->hm.s.svm.fSupported);
3073
3074	pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3075	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
3076
3077	#if HC_ARCH_BITS == 32
3078	/* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
3079	if (CPUMIsGuestInLongMode(pVCpu))
3080	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
3081	else
3082	#endif
3083	{
3084	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
3085	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
3086	}
3087	}
3088	return VINF_SUCCESS;
3089	}
3090
3091
3092	#if 0 /* obsolete, but left here for clarification. */
3093	/**
3094	* Invalidates a guest page by physical address.
3095	*
3096	* @returns VBox status code.
3097	* @param pVM Pointer to the VM.
3098	* @param pVCpu Pointer to the VMCPU.
3099	* @param GCPhys Guest physical address of the page to invalidate.
3100	*/
3101	VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
3102	{
3103	Assert(pVM->hm.s.fNestedPaging);
3104	/* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
3105	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
3106	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgPhys);
3107	return VINF_SUCCESS;
3108	}
3109	#endif
3110
3111
3112	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3113	/**
3114	* Prepares for and executes VMRUN (64-bit guests from a 32-bit host).
3115	*
3116	* @returns VBox status code.
3117	* @param HCPhysVmcbHost Physical address of host VMCB.
3118	* @param HCPhysVmcb Physical address of the VMCB.
3119	* @param pCtx Pointer to the guest CPU context.
3120	* @param pVM Pointer to the VM.
3121	* @param pVCpu Pointer to the VMCPU.
3122	*/
3123	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
3124	{
3125	uint32_t aParam[4];
3126
3127	aParam[0] = (uint32_t)(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
3128	aParam[1] = (uint32_t)(HCPhysVmcbHost >> 32); /* Param 1: HCPhysVmcbHost - Hi. */
3129	aParam[2] = (uint32_t)(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
3130	aParam[3] = (uint32_t)(HCPhysVmcb >> 32); /* Param 2: HCPhysVmcb - Hi. */
3131
3132	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, 4, &aParam[0]);
3133	}
3134
3135
3136	/**
3137	* Executes the specified handler in 64-bit mode.
3138	*
3139	* @returns VBox status code.
3140	* @param pVM Pointer to the VM.
3141	* @param pVCpu Pointer to the VMCPU.
3142	* @param pCtx Pointer to the guest CPU context.
3143	* @param enmOp The operation to perform.
3144	* @param cbParam Number of parameters.
3145	* @param paParam Array of 32-bit parameters.
3146	*/
3147	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cbParam,
3148	uint32_t *paParam)
3149	{
3150	int rc;
3151	RTHCUINTREG uOldEFlags;
3152
3153	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
3154	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
3155
3156	/* Disable interrupts. */
3157	uOldEFlags = ASMIntDisableFlags();
3158
3159	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
3160	RTCPUID idHostCpu = RTMpCpuId();
3161	CPUMR0SetLApic(pVM, idHostCpu);
3162	#endif
3163
3164	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
3165	CPUMSetHyperEIP(pVCpu, enmOp);
3166	for (int i = (int)cbParam - 1; i >= 0; i--)
3167	CPUMPushHyper(pVCpu, paParam[i]);
3168
3169	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
3170	/* Call switcher. */
3171	rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
3172	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
3173
3174	ASMSetFlags(uOldEFlags);
3175	return rc;
3176	}
3177
3178	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
3179

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 47627

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