HWSVMR0.cpp@ 30590

Last change on this file since 30590 was 30590, checked in by vboxsync, 14 years ago
HWVMXR0.cpp,HWSVMR0.cpp: Realigned and simplified the profiling.
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1	/* $Id: HWSVMR0.cpp 30590 2010-07-02 18:21:50Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HWACCM
22	#include <VBox/hwaccm.h>
23	#include <VBox/pgm.h>
24	#include <VBox/selm.h>
25	#include <VBox/iom.h>
26	#include <VBox/dbgf.h>
27	#include <VBox/tm.h>
28	#include <VBox/pdmapi.h>
29	#include "HWACCMInternal.h"
30	#include <VBox/vm.h>
31	#include <VBox/x86.h>
32	#include <VBox/hwacc_svm.h>
33	#include <VBox/err.h>
34	#include <VBox/log.h>
35	#include <VBox/dis.h>
36	#include <VBox/disopcode.h>
37	#include <iprt/param.h>
38	#include <iprt/assert.h>
39	#include <iprt/asm.h>
40	#include <iprt/asm-amd64-x86.h>
41	#include <iprt/cpuset.h>
42	#include <iprt/mp.h>
43	#include <iprt/time.h>
44	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
45	# include <iprt/thread.h>
46	#endif
47	#include "HWSVMR0.h"
48
49	/*******************************************************************************
50	* Internal Functions *
51	*******************************************************************************/
52	static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID);
53	static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
54	static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);
55
56	/*******************************************************************************
57	* Global Variables *
58	*******************************************************************************/
59
60	/**
61	* Sets up and activates AMD-V on the current CPU
62	*
63	* @returns VBox status code.
64	* @param pCpu CPU info struct
65	* @param pVM The VM to operate on. (can be NULL after a resume!!)
66	* @param pvPageCpu Pointer to the global cpu page
67	* @param pPageCpuPhys Physical address of the global cpu page
68	*/
69	VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
70	{
71	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
72	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
73
74	/* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
75	uint64_t val = ASMRdMsr(MSR_K6_EFER);
76	if (val & MSR_K6_EFER_SVME)
77	{
78	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active, then we blindly use AMD-V. */
79	if ( pVM
80	&& pVM->hwaccm.s.svm.fIgnoreInUseError)
81	{
82	pCpu->fIgnoreAMDVInUseError = true;
83	}
84
85	if (!pCpu->fIgnoreAMDVInUseError)
86	return VERR_SVM_IN_USE;
87	}
88
89	/* Turn on AMD-V in the EFER MSR. */
90	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
91
92	/* Write the physical page address where the CPU will store the host state while executing the VM. */
93	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
94
95	return VINF_SUCCESS;
96	}
97
98	/**
99	* Deactivates AMD-V on the current CPU
100	*
101	* @returns VBox status code.
102	* @param pCpu CPU info struct
103	* @param pvPageCpu Pointer to the global cpu page
104	* @param pPageCpuPhys Physical address of the global cpu page
105	*/
106	VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
107	{
108	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
109	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
110
111	/* Turn off AMD-V in the EFER MSR. */
112	uint64_t val = ASMRdMsr(MSR_K6_EFER);
113	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
114
115	/* Invalidate host state physical address. */
116	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
117
118	return VINF_SUCCESS;
119	}
120
121	/**
122	* Does Ring-0 per VM AMD-V init.
123	*
124	* @returns VBox status code.
125	* @param pVM The VM to operate on.
126	*/
127	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
128	{
129	int rc;
130
131	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
132
133	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
134	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
135	if (RT_FAILURE(rc))
136	return rc;
137
138	pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
139	pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
140	/* Set all bits to intercept all IO accesses. */
141	ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
142
143	/* Erratum 170 which requires a forced TLB flush for each world switch:
144	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
145	*
146	* All BH-G1/2 and DH-G1/2 models include a fix:
147	* Athlon X2: 0x6b 1/2
148	* 0x68 1/2
149	* Athlon 64: 0x7f 1
150	* 0x6f 2
151	* Sempron: 0x7f 1/2
152	* 0x6f 2
153	* 0x6c 2
154	* 0x7c 2
155	* Turion 64: 0x68 2
156	*
157	*/
158	uint32_t u32Dummy;
159	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
160	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
161	u32BaseFamily= (u32Version >> 8) & 0xf;
162	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
163	u32Model = ((u32Version >> 4) & 0xf);
164	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
165	u32Stepping = u32Version & 0xf;
166	if ( u32Family == 0xf
167	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
168	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
169	{
170	Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
171	pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
172	}
173
174	/* Allocate VMCBs for all guest CPUs. */
175	for (VMCPUID i = 0; i < pVM->cCpus; i++)
176	{
177	PVMCPU pVCpu = &pVM->aCpus[i];
178
179	pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
180	pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
181	pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
182
183	/* Allocate one page for the host context */
184	rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
185	if (RT_FAILURE(rc))
186	return rc;
187
188	pVCpu->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCBHost);
189	pVCpu->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 0);
190	Assert(pVCpu->hwaccm.s.svm.pVMCBHostPhys < _4G);
191	ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCBHost);
192
193	/* Allocate one page for the VM control block (VMCB). */
194	rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
195	if (RT_FAILURE(rc))
196	return rc;
197
198	pVCpu->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCB);
199	pVCpu->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCB, 0);
200	Assert(pVCpu->hwaccm.s.svm.pVMCBPhys < _4G);
201	ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCB);
202
203	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
204	rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
205	if (RT_FAILURE(rc))
206	return rc;
207
208	pVCpu->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap);
209	pVCpu->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 0);
210	/* Set all bits to intercept all MSR accesses. */
211	ASMMemFill32(pVCpu->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
212	}
213
214	return VINF_SUCCESS;
215	}
216
217	/**
218	* Does Ring-0 per VM AMD-V termination.
219	*
220	* @returns VBox status code.
221	* @param pVM The VM to operate on.
222	*/
223	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
224	{
225	for (VMCPUID i = 0; i < pVM->cCpus; i++)
226	{
227	PVMCPU pVCpu = &pVM->aCpus[i];
228
229	if (pVCpu->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
230	{
231	RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, false);
232	pVCpu->hwaccm.s.svm.pVMCBHost = 0;
233	pVCpu->hwaccm.s.svm.pVMCBHostPhys = 0;
234	pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
235	}
236
237	if (pVCpu->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
238	{
239	RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCB, false);
240	pVCpu->hwaccm.s.svm.pVMCB = 0;
241	pVCpu->hwaccm.s.svm.pVMCBPhys = 0;
242	pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
243	}
244	if (pVCpu->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
245	{
246	RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, false);
247	pVCpu->hwaccm.s.svm.pMSRBitmap = 0;
248	pVCpu->hwaccm.s.svm.pMSRBitmapPhys = 0;
249	pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
250	}
251	}
252	if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
253	{
254	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
255	pVM->hwaccm.s.svm.pIOBitmap = 0;
256	pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
257	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
258	}
259	return VINF_SUCCESS;
260	}
261
262	/**
263	* Sets up AMD-V for the specified VM
264	*
265	* @returns VBox status code.
266	* @param pVM The VM to operate on.
267	*/
268	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
269	{
270	int rc = VINF_SUCCESS;
271
272	AssertReturn(pVM, VERR_INVALID_PARAMETER);
273
274	Assert(pVM->hwaccm.s.svm.fSupported);
275
276	for (VMCPUID i = 0; i < pVM->cCpus; i++)
277	{
278	PVMCPU pVCpu = &pVM->aCpus[i];
279	SVM_VMCB pVMCB = (SVM_VMCB )pVM->aCpus[i].hwaccm.s.svm.pVMCB;
280
281	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
282
283	/* Program the control fields. Most of them never have to be changed again. */
284	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
285	/* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
286	if (!pVM->hwaccm.s.fNestedPaging)
287	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
288	else
289	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
290
291	/*
292	* CR0/3/4 writes must be intercepted for obvious reasons.
293	*/
294	if (!pVM->hwaccm.s.fNestedPaging)
295	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
296	else
297	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
298
299	/* Intercept all DRx reads and writes by default. Changed later on. */
300	pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
301	pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
302
303	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
304	* All breakpoints are automatically cleared when the VM exits.
305	*/
306
307	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
308	#ifndef DEBUG
309	if (pVM->hwaccm.s.fNestedPaging)
310	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
311	#endif
312
313	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
314	\| SVM_CTRL1_INTERCEPT_VINTR
315	\| SVM_CTRL1_INTERCEPT_NMI
316	\| SVM_CTRL1_INTERCEPT_SMI
317	\| SVM_CTRL1_INTERCEPT_INIT
318	\| SVM_CTRL1_INTERCEPT_RDPMC
319	\| SVM_CTRL1_INTERCEPT_CPUID
320	\| SVM_CTRL1_INTERCEPT_RSM
321	\| SVM_CTRL1_INTERCEPT_HLT
322	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
323	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
324	\| SVM_CTRL1_INTERCEPT_INVLPG
325	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
326	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH
327	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
328	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
329	;
330	/* With nested paging we don't care about invlpg anymore. */
331	if (pVM->hwaccm.s.fNestedPaging)
332	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
333
334	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
335	\| SVM_CTRL2_INTERCEPT_VMMCALL
336	\| SVM_CTRL2_INTERCEPT_VMLOAD
337	\| SVM_CTRL2_INTERCEPT_VMSAVE
338	\| SVM_CTRL2_INTERCEPT_STGI
339	\| SVM_CTRL2_INTERCEPT_CLGI
340	\| SVM_CTRL2_INTERCEPT_SKINIT
341	\| SVM_CTRL2_INTERCEPT_WBINVD
342	\| SVM_CTRL2_INTERCEPT_MONITOR
343	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
344	;
345	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
346	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
347	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
348
349	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
350	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
351	/* Ignore the priority in the TPR; just deliver it when we tell it to. */
352	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
353
354	/* Set IO and MSR bitmap addresses. */
355	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
356	pVMCB->ctrl.u64MSRPMPhysAddr = pVCpu->hwaccm.s.svm.pMSRBitmapPhys;
357
358	/* No LBR virtualization. */
359	pVMCB->ctrl.u64LBRVirt = 0;
360
361	/** The ASID must start at 1; the host uses 0. */
362	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
363
364	/** Setup the PAT msr (nested paging only) */
365	/* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB, so choose type 6 for all PAT slots. */
366	pVMCB->guest.u64GPAT = 0x0006060606060606ULL;
367
368	/* The following MSRs are saved automatically by vmload/vmsave, so we allow the guest
369	* to modify them directly.
370	*/
371	svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
372	svmR0SetMSRPermission(pVCpu, MSR_K8_CSTAR, true, true);
373	svmR0SetMSRPermission(pVCpu, MSR_K6_STAR, true, true);
374	svmR0SetMSRPermission(pVCpu, MSR_K8_SF_MASK, true, true);
375	svmR0SetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true);
376	svmR0SetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true);
377	svmR0SetMSRPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, true, true);
378	svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_CS, true, true);
379	svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_ESP, true, true);
380	svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_EIP, true, true);
381	}
382
383	return rc;
384	}
385
386
387	/**
388	* Sets the permission bits for the specified MSR
389	*
390	* @param pVCpu The VMCPU to operate on.
391	* @param ulMSR MSR value
392	* @param fRead Reading allowed/disallowed
393	* @param fWrite Writing allowed/disallowed
394	*/
395	static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)
396	{
397	unsigned ulBit;
398	uint8_t pMSRBitmap = (uint8_t )pVCpu->hwaccm.s.svm.pMSRBitmap;
399
400	if (ulMSR <= 0x00001FFF)
401	{
402	/* Pentium-compatible MSRs */
403	ulBit = ulMSR * 2;
404	}
405	else
406	if ( ulMSR >= 0xC0000000
407	&& ulMSR <= 0xC0001FFF)
408	{
409	/* AMD Sixth Generation x86 Processor MSRs and SYSCALL */
410	ulBit = (ulMSR - 0xC0000000) * 2;
411	pMSRBitmap += 0x800;
412	}
413	else
414	if ( ulMSR >= 0xC0010000
415	&& ulMSR <= 0xC0011FFF)
416	{
417	/* AMD Seventh and Eighth Generation Processor MSRs */
418	ulBit = (ulMSR - 0xC0001000) * 2;
419	pMSRBitmap += 0x1000;
420	}
421	else
422	{
423	AssertFailed();
424	return;
425	}
426	Assert(ulBit < 16 * 1024 - 1);
427	if (fRead)
428	ASMBitClear(pMSRBitmap, ulBit);
429	else
430	ASMBitSet(pMSRBitmap, ulBit);
431
432	if (fWrite)
433	ASMBitClear(pMSRBitmap, ulBit + 1);
434	else
435	ASMBitSet(pMSRBitmap, ulBit + 1);
436	}
437
438	/**
439	* Injects an event (trap or external interrupt)
440	*
441	* @param pVCpu The VMCPU to operate on.
442	* @param pVMCB SVM control block
443	* @param pCtx CPU Context
444	* @param pIntInfo SVM interrupt info
445	*/
446	inline void SVMR0InjectEvent(PVMCPU pVCpu, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
447	{
448	#ifdef VBOX_WITH_STATISTICS
449	STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
450	#endif
451
452	#ifdef VBOX_STRICT
453	if (pEvent->n.u8Vector == 0xE)
454	Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
455	else
456	if (pEvent->n.u8Vector < 0x20)
457	Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
458	else
459	{
460	Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
461	Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
462	Assert(pCtx->eflags.u32 & X86_EFL_IF);
463	}
464	#endif
465
466	/* Set event injection state. */
467	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
468	}
469
470
471	/**
472	* Checks for pending guest interrupts and injects them
473	*
474	* @returns VBox status code.
475	* @param pVM The VM to operate on.
476	* @param pVCpu The VM CPU to operate on.
477	* @param pVMCB SVM control block
478	* @param pCtx CPU Context
479	*/
480	static int SVMR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB pVMCB, CPUMCTX pCtx)
481	{
482	int rc;
483
484	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
485	if (pVCpu->hwaccm.s.Event.fPending)
486	{
487	SVM_EVENT Event;
488
489	Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
490	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
491	Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
492	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
493
494	pVCpu->hwaccm.s.Event.fPending = false;
495	return VINF_SUCCESS;
496	}
497
498	/* If an active trap is already pending, then we must forward it first! */
499	if (!TRPMHasTrap(pVCpu))
500	{
501	if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI))
502	{
503	SVM_EVENT Event;
504
505	Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
506	Event.n.u8Vector = X86_XCPT_NMI;
507	Event.n.u1Valid = 1;
508	Event.n.u32ErrorCode = 0;
509	Event.n.u3Type = SVM_EVENT_NMI;
510
511	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
512	return VINF_SUCCESS;
513	}
514
515	/* @todo SMI interrupts. */
516
517	/* When external interrupts are pending, we should exit the VM when IF is set. */
518	if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC\|VMCPU_FF_INTERRUPT_PIC)))
519	{
520	if ( !(pCtx->eflags.u32 & X86_EFL_IF)
521	\|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
522	{
523	if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
524	{
525	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
526	LogFlow(("Enable irq window exit!\n"));
527	else
528	Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
529
530	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
531	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
532	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
533	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
534	}
535	}
536	else
537	{
538	uint8_t u8Interrupt;
539
540	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
541	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
542	if (RT_SUCCESS(rc))
543	{
544	rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
545	AssertRC(rc);
546	}
547	else
548	{
549	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
550	Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC\|VMCPU_FF_INTERRUPT_PIC)));
551	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
552	/* Just continue */
553	}
554	}
555	}
556	}
557
558	#ifdef VBOX_STRICT
559	if (TRPMHasTrap(pVCpu))
560	{
561	uint8_t u8Vector;
562	rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
563	AssertRC(rc);
564	}
565	#endif
566
567	if ( (pCtx->eflags.u32 & X86_EFL_IF)
568	&& (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
569	&& TRPMHasTrap(pVCpu)
570	)
571	{
572	uint8_t u8Vector;
573	TRPMEVENT enmType;
574	SVM_EVENT Event;
575	RTGCUINT u32ErrorCode;
576
577	Event.au64[0] = 0;
578
579	/* If a new event is pending, then dispatch it now. */
580	rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, 0);
581	AssertRC(rc);
582	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
583	Assert(enmType != TRPM_SOFTWARE_INT);
584
585	/* Clear the pending trap. */
586	rc = TRPMResetTrap(pVCpu);
587	AssertRC(rc);
588
589	Event.n.u8Vector = u8Vector;
590	Event.n.u1Valid = 1;
591	Event.n.u32ErrorCode = u32ErrorCode;
592
593	if (enmType == TRPM_TRAP)
594	{
595	switch (u8Vector) {
596	case 8:
597	case 10:
598	case 11:
599	case 12:
600	case 13:
601	case 14:
602	case 17:
603	/* Valid error codes. */
604	Event.n.u1ErrorCodeValid = 1;
605	break;
606	default:
607	break;
608	}
609	if (u8Vector == X86_XCPT_NMI)
610	Event.n.u3Type = SVM_EVENT_NMI;
611	else
612	Event.n.u3Type = SVM_EVENT_EXCEPTION;
613	}
614	else
615	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
616
617	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
618	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
619	} /* if (interrupts can be dispatched) */
620
621	return VINF_SUCCESS;
622	}
623
624	/**
625	* Save the host state
626	*
627	* @returns VBox status code.
628	* @param pVM The VM to operate on.
629	* @param pVCpu The VM CPU to operate on.
630	*/
631	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
632	{
633	NOREF(pVM);
634	NOREF(pVCpu);
635	/* Nothing to do here. */
636	return VINF_SUCCESS;
637	}
638
639	/**
640	* Loads the guest state
641	*
642	* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
643	*
644	* @returns VBox status code.
645	* @param pVM The VM to operate on.
646	* @param pVCpu The VM CPU to operate on.
647	* @param pCtx Guest context
648	*/
649	VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
650	{
651	RTGCUINTPTR val;
652	SVM_VMCB *pVMCB;
653
654	if (pVM == NULL)
655	return VERR_INVALID_PARAMETER;
656
657	/* Setup AMD SVM. */
658	Assert(pVM->hwaccm.s.svm.fSupported);
659
660	pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
661	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
662
663	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
664	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
665	{
666	SVM_WRITE_SELREG(CS, cs);
667	SVM_WRITE_SELREG(SS, ss);
668	SVM_WRITE_SELREG(DS, ds);
669	SVM_WRITE_SELREG(ES, es);
670	SVM_WRITE_SELREG(FS, fs);
671	SVM_WRITE_SELREG(GS, gs);
672	}
673
674	/* Guest CPU context: LDTR. */
675	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
676	{
677	SVM_WRITE_SELREG(LDTR, ldtr);
678	}
679
680	/* Guest CPU context: TR. */
681	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
682	{
683	SVM_WRITE_SELREG(TR, tr);
684	}
685
686	/* Guest CPU context: GDTR. */
687	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
688	{
689	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
690	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
691	}
692
693	/* Guest CPU context: IDTR. */
694	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
695	{
696	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
697	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
698	}
699
700	/*
701	* Sysenter MSRs (unconditional)
702	*/
703	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
704	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
705	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
706
707	/* Control registers */
708	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
709	{
710	val = pCtx->cr0;
711	if (!CPUMIsGuestFPUStateActive(pVCpu))
712	{
713	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
714	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
715	}
716	else
717	{
718	/** @todo check if we support the old style mess correctly. */
719	if (!(val & X86_CR0_NE))
720	{
721	Log(("Forcing X86_CR0_NE!!!\n"));
722
723	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
724	if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)
725	{
726	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_MF);
727	pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
728	}
729	}
730	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
731	}
732	/* Always enable caching. */
733	val &= ~(X86_CR0_CD\|X86_CR0_NW);
734
735	/* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
736	/* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
737	if (!pVM->hwaccm.s.fNestedPaging)
738	{
739	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
740	val \|= X86_CR0_WP; /* Must set this as we rely on protecting various pages and supervisor writes must be caught. */
741	}
742	pVMCB->guest.u64CR0 = val;
743	}
744	/* CR2 as well */
745	pVMCB->guest.u64CR2 = pCtx->cr2;
746
747	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
748	{
749	/* Save our shadow CR3 register. */
750	if (pVM->hwaccm.s.fNestedPaging)
751	{
752	PGMMODE enmShwPagingMode;
753
754	#if HC_ARCH_BITS == 32
755	if (CPUMIsGuestInLongModeEx(pCtx))
756	enmShwPagingMode = PGMMODE_AMD64_NX;
757	else
758	#endif
759	enmShwPagingMode = PGMGetHostMode(pVM);
760
761	pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
762	Assert(pVMCB->ctrl.u64NestedPagingCR3);
763	pVMCB->guest.u64CR3 = pCtx->cr3;
764	}
765	else
766	{
767	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
768	Assert(pVMCB->guest.u64CR3 \|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
769	}
770	}
771
772	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
773	{
774	val = pCtx->cr4;
775	if (!pVM->hwaccm.s.fNestedPaging)
776	{
777	switch(pVCpu->hwaccm.s.enmShadowMode)
778	{
779	case PGMMODE_REAL:
780	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
781	AssertFailed();
782	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
783
784	case PGMMODE_32_BIT: /* 32-bit paging. */
785	val &= ~X86_CR4_PAE;
786	break;
787
788	case PGMMODE_PAE: /* PAE paging. */
789	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
790	/** @todo use normal 32 bits paging */
791	val \|= X86_CR4_PAE;
792	break;
793
794	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
795	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
796	#ifdef VBOX_ENABLE_64_BITS_GUESTS
797	break;
798	#else
799	AssertFailed();
800	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
801	#endif
802
803	default: /* shut up gcc */
804	AssertFailed();
805	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
806	}
807	}
808	pVMCB->guest.u64CR4 = val;
809	}
810
811	/* Debug registers. */
812	if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
813	{
814	pCtx->dr[6] \|= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
815	pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
816
817	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
818	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
819	pCtx->dr[7] \|= 0x400; /* must be one */
820
821	pVMCB->guest.u64DR7 = pCtx->dr[7];
822	pVMCB->guest.u64DR6 = pCtx->dr[6];
823
824	#ifdef DEBUG
825	/* Sync the hypervisor debug state now if any breakpoint is armed. */
826	if ( CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK\|X86_DR7_GD)
827	&& !CPUMIsHyperDebugStateActive(pVCpu)
828	&& !DBGFIsStepping(pVCpu))
829	{
830	/* Save the host and load the hypervisor debug state. */
831	int rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
832	AssertRC(rc);
833
834	/* DRx intercepts remain enabled. */
835
836	/* Override dr6 & dr7 with the hypervisor values. */
837	pVMCB->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
838	pVMCB->guest.u64DR6 = CPUMGetHyperDR6(pVCpu);
839	}
840	else
841	#endif
842	/* Sync the debug state now if any breakpoint is armed. */
843	if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK\|X86_DR7_GD))
844	&& !CPUMIsGuestDebugStateActive(pVCpu)
845	&& !DBGFIsStepping(pVCpu))
846	{
847	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
848
849	/* Disable drx move intercepts. */
850	pVMCB->ctrl.u16InterceptRdDRx = 0;
851	pVMCB->ctrl.u16InterceptWrDRx = 0;
852
853	/* Save the host and load the guest debug state. */
854	int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
855	AssertRC(rc);
856	}
857	}
858
859	/* EIP, ESP and EFLAGS */
860	pVMCB->guest.u64RIP = pCtx->rip;
861	pVMCB->guest.u64RSP = pCtx->rsp;
862	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
863
864	/* Set CPL */
865	pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
866
867	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
868	pVMCB->guest.u64RAX = pCtx->rax;
869
870	/* vmrun will fail without MSR_K6_EFER_SVME. */
871	pVMCB->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
872
873	/* 64 bits guest mode? */
874	if (CPUMIsGuestInLongModeEx(pCtx))
875	{
876	#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
877	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
878	#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
879	pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
880	#else
881	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
882	if (!pVM->hwaccm.s.fAllow64BitGuests)
883	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
884	# endif
885	pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun64;
886	#endif
887	/* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
888	pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
889	pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
890	}
891	else
892	{
893	/* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
894	pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
895
896	pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun;
897	}
898
899	/* TSC offset. */
900	if (TMCpuTickCanUseRealTSC(pVCpu, &pVMCB->ctrl.u64TSCOffset))
901	{
902	uint64_t u64CurTSC = ASMReadTSC();
903	if (u64CurTSC + pVMCB->ctrl.u64TSCOffset >= TMCpuTickGetLastSeen(pVCpu))
904	{
905	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
906	pVMCB->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
907	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
908	}
909	else
910	{
911	/* Fall back to rdtsc emulation as we would otherwise pass decreasing tsc values to the guest. */
912	LogFlow(("TSC %RX64 offset %RX64 time=%RX64 last=%RX64 (diff=%RX64, virt_tsc=%RX64)\n", u64CurTSC, pVMCB->ctrl.u64TSCOffset, u64CurTSC + pVMCB->ctrl.u64TSCOffset, TMCpuTickGetLastSeen(pVCpu), TMCpuTickGetLastSeen(pVCpu) - u64CurTSC - pVMCB->ctrl.u64TSCOffset, TMCpuTickGet(pVCpu)));
913	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
914	pVMCB->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
915	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow);
916	}
917	}
918	else
919	{
920	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
921	pVMCB->ctrl.u32InterceptCtrl2 \|= SVM_CTRL2_INTERCEPT_RDTSCP;
922	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
923	}
924
925	/* Sync the various msrs for 64 bits mode. */
926	pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
927	pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
928	pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
929	pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
930	pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
931
932	#ifdef DEBUG
933	/* Intercept X86_XCPT_DB if stepping is enabled */
934	if ( DBGFIsStepping(pVCpu)
935	\|\| CPUMIsHyperDebugStateActive(pVCpu))
936	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_DB);
937	else
938	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
939	#endif
940
941	/* Done. */
942	pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
943
944	return VINF_SUCCESS;
945	}
946
947
948	/**
949	* Runs guest code in an AMD-V VM.
950	*
951	* @returns VBox status code.
952	* @param pVM The VM to operate on.
953	* @param pVCpu The VM CPU to operate on.
954	* @param pCtx Guest context
955	*/
956	VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
957	{
958	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
959	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hwaccm.s.StatExit1);
960	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hwaccm.s.StatExit2);
961
962	int rc = VINF_SUCCESS;
963	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
964	SVM_VMCB *pVMCB;
965	bool fSyncTPR = false;
966	unsigned cResume = 0;
967	uint8_t u8LastTPR;
968	PHWACCM_CPUINFO pCpu = 0;
969	RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
970	#ifdef VBOX_STRICT
971	RTCPUID idCpuCheck;
972	#endif
973	#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
974	uint64_t u64LastTime = RTTimeMilliTS();
975	#endif
976
977	pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
978	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
979
980	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
981	*/
982	ResumeExecution:
983	if (!STAM_PROFILE_ADV_IS_RUNNING(&pVCpu->hwaccm.s.StatEntry))
984	STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatExit2, &pVCpu->hwaccm.s.StatEntry, x);
985	Assert(!HWACCMR0SuspendPending());
986
987	/* Safety precaution; looping for too long here can have a very bad effect on the host */
988	if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
989	{
990	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
991	rc = VINF_EM_RAW_INTERRUPT;
992	goto end;
993	}
994
995	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
996	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
997	{
998	Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
999	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
1000	{
1001	/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
1002	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
1003	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1004	* break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
1005	*/
1006	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1007	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
1008	pVMCB->ctrl.u64IntShadow = 0;
1009	}
1010	}
1011	else
1012	{
1013	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
1014	pVMCB->ctrl.u64IntShadow = 0;
1015	}
1016
1017	#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
1018	if (RT_UNLIKELY(cResume & 0xf) == 0)
1019	{
1020	uint64_t u64CurTime = RTTimeMilliTS();
1021
1022	if (RT_UNLIKELY(u64CurTime > u64LastTime))
1023	{
1024	u64LastTime = u64CurTime;
1025	TMTimerPollVoid(pVM, pVCpu);
1026	}
1027	}
1028	#endif
1029
1030	/* Check for pending actions that force us to go back to ring 3. */
1031	if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK \| VM_FF_REQUEST \| VM_FF_PGM_POOL_FLUSH_PENDING)
1032	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK \| VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \| VMCPU_FF_REQUEST))
1033	{
1034	/* Check if a sync operation is pending. */
1035	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1036	{
1037	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1038	AssertRC(rc);
1039	if (rc != VINF_SUCCESS)
1040	{
1041	Log(("Pending pool sync is forcing us back to ring 3; rc=%d\n", rc));
1042	goto end;
1043	}
1044	}
1045
1046	#ifdef DEBUG
1047	/* Intercept X86_XCPT_DB if stepping is enabled */
1048	if (!DBGFIsStepping(pVCpu))
1049	#endif
1050	{
1051	if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
1052	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
1053	{
1054	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
1055	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
1056	rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
1057	goto end;
1058	}
1059	}
1060
1061	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1062	if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
1063	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1064	{
1065	rc = VINF_EM_PENDING_REQUEST;
1066	goto end;
1067	}
1068
1069	/* Check if a pgm pool flush is in progress. */
1070	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
1071	{
1072	rc = VINF_PGM_POOL_FLUSH_PENDING;
1073	goto end;
1074	}
1075	}
1076
1077	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1078	/*
1079	* Exit to ring-3 preemption/work is pending.
1080	*
1081	* Interrupts are disabled before the call to make sure we don't miss any interrupt
1082	* that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
1083	* further down, but SVMR0CheckPendingInterrupt makes that impossible.)
1084	*
1085	* Note! Interrupts must be disabled done before we check for TLB flushes; TLB
1086	* shootdowns rely on this.
1087	*/
1088	uOldEFlags = ASMIntDisableFlags();
1089	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
1090	{
1091	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
1092	rc = VINF_EM_RAW_INTERRUPT;
1093	goto end;
1094	}
1095	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1096	#endif
1097
1098	/* When external interrupts are pending, we should exit the VM when IF is set. */
1099	/* Note! After VM_FF_INHIBIT_INTERRUPTS check!!! */
1100	rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
1101	if (RT_FAILURE(rc))
1102	goto end;
1103
1104	/* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
1105	/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! (no longer true)
1106	* @todo query and update the TPR only when it could have been changed (mmio access)
1107	*/
1108	if (pVM->hwaccm.s.fHasIoApic)
1109	{
1110	bool fPending;
1111
1112	/* TPR caching in CR8 */
1113	int rc2 = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
1114	AssertRC(rc2);
1115
1116	if (pVM->hwaccm.s.fTPRPatchingActive)
1117	{
1118	/* Our patch code uses LSTAR for TPR caching. */
1119	pCtx->msrLSTAR = u8LastTPR;
1120
1121	if (fPending)
1122	{
1123	/* A TPR change could activate a pending interrupt, so catch lstar writes. */
1124	svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, false);
1125	}
1126	else
1127	/* No interrupts are pending, so we don't need to be explicitely notified.
1128	* There are enough world switches for detecting pending interrupts.
1129	*/
1130	svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
1131	}
1132	else
1133	{
1134	pVMCB->ctrl.IntCtrl.n.u8VTPR = (u8LastTPR >> 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1135
1136	if (fPending)
1137	{
1138	/* A TPR change could activate a pending interrupt, so catch cr8 writes. */
1139	pVMCB->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1140	}
1141	else
1142	/* No interrupts are pending, so we don't need to be explicitely notified.
1143	* There are enough world switches for detecting pending interrupts.
1144	*/
1145	pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1146	}
1147	fSyncTPR = !fPending;
1148	}
1149
1150	/* All done! Let's start VM execution. */
1151
1152	/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
1153	pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
1154
1155	#ifdef LOG_ENABLED
1156	pCpu = HWACCMR0GetCurrentCpu();
1157	if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1158	\|\| pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1159	{
1160	if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
1161	LogFlow(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
1162	else
1163	LogFlow(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1164	}
1165	if (pCpu->fFlushTLB)
1166	LogFlow(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
1167	#endif
1168
1169	/*
1170	* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1171	* (until the actual world switch)
1172	*/
1173	#ifdef VBOX_STRICT
1174	idCpuCheck = RTMpCpuId();
1175	#endif
1176	VMMR0LogFlushDisable(pVCpu);
1177
1178	/* Load the guest state; must be here as it sets up the shadow cr0 for lazy fpu syncing! */
1179	rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
1180	if (RT_UNLIKELY(rc != VINF_SUCCESS))
1181	{
1182	VMMR0LogFlushEnable(pVCpu);
1183	goto end;
1184	}
1185
1186	#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1187	/* Disable interrupts to make sure a poke will interrupt execution.
1188	* This must be done before we check for TLB flushes; TLB shootdowns rely on this.
1189	*/
1190	uOldEFlags = ASMIntDisableFlags();
1191	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1192	#endif
1193	STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatEntry, &pVCpu->hwaccm.s.StatInGC, x);
1194
1195	pCpu = HWACCMR0GetCurrentCpu();
1196	/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1197	/* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1198	if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1199	/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1200	\|\| pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1201	{
1202	/* Force a TLB flush on VM entry. */
1203	pVCpu->hwaccm.s.fForceTLBFlush = true;
1204	}
1205	else
1206	Assert(!pCpu->fFlushTLB \|\| pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1207
1208	pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1209
1210	/** Set TLB flush state as checked until we return from the world switch. */
1211	ASMAtomicWriteU8(&pVCpu->hwaccm.s.fCheckedTLBFlush, true);
1212
1213	/* Check for tlb shootdown flushes. */
1214	if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1215	pVCpu->hwaccm.s.fForceTLBFlush = true;
1216
1217	/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1218	if ( pVCpu->hwaccm.s.fForceTLBFlush
1219	&& !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
1220	{
1221	if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1222	\|\| pCpu->fFlushTLB)
1223	{
1224	pCpu->fFlushTLB = false;
1225	pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1226	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
1227	pCpu->cTLBFlushes++;
1228	}
1229	else
1230	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1231
1232	pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1233	pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1234	}
1235	else
1236	{
1237	Assert(!pCpu->fFlushTLB \|\| pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1238
1239	/* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
1240	if (!pCpu->uCurrentASID \|\| !pVCpu->hwaccm.s.uCurrentASID)
1241	pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1242
1243	Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB \|\| pVCpu->hwaccm.s.fForceTLBFlush);
1244	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
1245
1246	if ( !pVM->hwaccm.s.svm.fAlwaysFlushTLB
1247	&& VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1248	{
1249	/* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1250	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1251	for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1252	SVMR0InvlpgA(pVCpu->hwaccm.s.TlbShootdown.aPages[i], pVMCB->ctrl.TLBCtrl.n.u32ASID);
1253	}
1254	}
1255	pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1256	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1257
1258	AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1259	AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1260	AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1261	pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
1262
1263	#ifdef VBOX_WITH_STATISTICS
1264	if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
1265	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1266	else
1267	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1268	#endif
1269
1270	/* In case we execute a goto ResumeExecution later on. */
1271	pVCpu->hwaccm.s.fResumeVM = true;
1272	pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
1273
1274	Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
1275	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
1276	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
1277	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVCpu->hwaccm.s.svm.pMSRBitmapPhys);
1278	Assert(pVMCB->ctrl.u64LBRVirt == 0);
1279
1280	#ifdef VBOX_STRICT
1281	Assert(idCpuCheck == RTMpCpuId());
1282	#endif
1283	TMNotifyStartOfExecution(pVCpu);
1284	#ifdef VBOX_WITH_KERNEL_USING_XMM
1285	hwaccmR0SVMRunWrapXMM(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu, pVCpu->hwaccm.s.svm.pfnVMRun);
1286	#else
1287	pVCpu->hwaccm.s.svm.pfnVMRun(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);
1288	#endif
1289	ASMAtomicWriteU8(&pVCpu->hwaccm.s.fCheckedTLBFlush, false);
1290	ASMAtomicIncU32(&pVCpu->hwaccm.s.cWorldSwitchExit);
1291	/* Possibly the last TSC value seen by the guest (too high) (only when we're in tsc offset mode). */
1292	if (!(pVMCB->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
1293	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVMCB->ctrl.u64TSCOffset - 0x400 /* guestimate of world switch overhead in clock ticks */);
1294	TMNotifyEndOfExecution(pVCpu);
1295	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
1296	STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatInGC, &pVCpu->hwaccm.s.StatExit1, x);
1297	ASMSetFlags(uOldEFlags);
1298	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1299	uOldEFlags = ~(RTCCUINTREG)0;
1300	#endif
1301
1302	/*
1303	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1304	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1305	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1306	*/
1307
1308	/* Reason for the VM exit */
1309	exitCode = pVMCB->ctrl.u64ExitCode;
1310
1311	if (RT_UNLIKELY(exitCode == (uint64_t)SVM_EXIT_INVALID)) /* Invalid guest state. */
1312	{
1313	HWACCMDumpRegs(pVM, pVCpu, pCtx);
1314	#ifdef DEBUG
1315	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1316	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1317	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1318	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1319	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1320	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1321	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1322	Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1323	Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1324	Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
1325
1326	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1327	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1328	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1329	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1330
1331	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1332	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1333	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1334	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1335	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1336	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1337	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1338	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1339	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1340	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1341
1342	Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
1343	Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
1344	Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
1345	Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
1346	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1347	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1348	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1349	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1350	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1351	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1352	Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
1353	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1354	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1355	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1356	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1357	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1358	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1359
1360	Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1361	Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
1362
1363	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1364	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1365	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1366	Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
1367	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1368	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1369	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1370	Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
1371	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1372	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1373	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1374	Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
1375	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1376	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1377	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1378	Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
1379	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1380	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1381	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1382	Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
1383
1384	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1385	Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
1386
1387	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1388	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1389	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1390	Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
1391
1392	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1393	Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
1394
1395	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1396	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1397	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1398	Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
1399
1400	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1401	Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
1402	Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
1403	Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
1404	Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
1405	Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
1406	Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
1407
1408	Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
1409	Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
1410	Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
1411	Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
1412
1413	Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
1414	Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
1415	Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
1416
1417	Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
1418	Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
1419	Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
1420	Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
1421	Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
1422	Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
1423	Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
1424	Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
1425	Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
1426	Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
1427	Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
1428	Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
1429
1430	#endif
1431	rc = VERR_SVM_UNABLE_TO_START_VM;
1432	VMMR0LogFlushEnable(pVCpu);
1433	goto end;
1434	}
1435
1436	/* Let's first sync back eip, esp, and eflags. */
1437	pCtx->rip = pVMCB->guest.u64RIP;
1438	pCtx->rsp = pVMCB->guest.u64RSP;
1439	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1440	/* eax is saved/restore across the vmrun instruction */
1441	pCtx->rax = pVMCB->guest.u64RAX;
1442
1443	/* Save all the MSRs that can be changed by the guest without causing a world switch. (fs & gs base are saved with SVM_READ_SELREG) */
1444	pCtx->msrSTAR = pVMCB->guest.u64STAR; /* legacy syscall eip, cs & ss */
1445	pCtx->msrLSTAR = pVMCB->guest.u64LSTAR; /* 64 bits mode syscall rip */
1446	pCtx->msrCSTAR = pVMCB->guest.u64CSTAR; /* compatibility mode syscall rip */
1447	pCtx->msrSFMASK = pVMCB->guest.u64SFMASK; /* syscall flag mask */
1448	pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1449	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1450	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1451	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1452
1453	/* Can be updated behind our back in the nested paging case. */
1454	pCtx->cr2 = pVMCB->guest.u64CR2;
1455
1456	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1457	SVM_READ_SELREG(SS, ss);
1458	SVM_READ_SELREG(CS, cs);
1459	SVM_READ_SELREG(DS, ds);
1460	SVM_READ_SELREG(ES, es);
1461	SVM_READ_SELREG(FS, fs);
1462	SVM_READ_SELREG(GS, gs);
1463
1464	/* Correct the hidden CS granularity flag. Haven't seen it being wrong in
1465	any other register (yet). */
1466	if ( !pCtx->csHid.Attr.n.u1Granularity
1467	&& pCtx->csHid.Attr.n.u1Present
1468	&& pCtx->csHid.u32Limit > UINT32_C(0xfffff))
1469	{
1470	Assert((pCtx->csHid.u32Limit & 0xfff) == 0xfff);
1471	pCtx->csHid.Attr.n.u1Granularity = 1;
1472	}
1473	#define SVM_ASSERT_SEL_GRANULARITY(reg) \
1474	AssertMsg( !pCtx->reg##Hid.Attr.n.u1Present \
1475	\|\| ( pCtx->reg##Hid.Attr.n.u1Granularity \
1476	? (pCtx->reg##Hid.u32Limit & 0xfff) == 0xfff \
1477	: pCtx->reg##Hid.u32Limit <= 0xfffff), \
1478	("%#x %#x %#llx\n", pCtx->reg##Hid.u32Limit, pCtx->reg##Hid.Attr.u, pCtx->reg##Hid.u64Base))
1479	SVM_ASSERT_SEL_GRANULARITY(ss);
1480	SVM_ASSERT_SEL_GRANULARITY(cs);
1481	SVM_ASSERT_SEL_GRANULARITY(ds);
1482	SVM_ASSERT_SEL_GRANULARITY(es);
1483	SVM_ASSERT_SEL_GRANULARITY(fs);
1484	SVM_ASSERT_SEL_GRANULARITY(gs);
1485	#undef SVM_ASSERT_SEL_GRANULARITY
1486
1487	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1488	SVM_READ_SELREG(LDTR, ldtr);
1489	SVM_READ_SELREG(TR, tr);
1490
1491	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1492	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1493
1494	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1495	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1496
1497	/* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1498	/* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1499	if ( pVM->hwaccm.s.fNestedPaging
1500	&& pCtx->cr3 != pVMCB->guest.u64CR3)
1501	{
1502	CPUMSetGuestCR3(pVCpu, pVMCB->guest.u64CR3);
1503	PGMUpdateCR3(pVCpu, pVMCB->guest.u64CR3);
1504	}
1505
1506	/* Note! NOW IT'S SAFE FOR LOGGING! */
1507	VMMR0LogFlushEnable(pVCpu);
1508
1509	/* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1510	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1511	{
1512	Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
1513	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1514	}
1515	else
1516	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1517
1518	Log2(("exitCode = %x\n", exitCode));
1519
1520	/* Sync back DR6 as it could have been changed by hitting breakpoints. */
1521	pCtx->dr[6] = pVMCB->guest.u64DR6;
1522	/* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1523	pCtx->dr[7] = pVMCB->guest.u64DR7;
1524
1525	/* Check if an injected event was interrupted prematurely. */
1526	pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1527	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1528	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1529	{
1530	Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
1531
1532	#ifdef LOG_ENABLED
1533	SVM_EVENT Event;
1534	Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
1535
1536	if ( exitCode == SVM_EXIT_EXCEPTION_E
1537	&& Event.n.u8Vector == 0xE)
1538	{
1539	Log(("Double fault!\n"));
1540	}
1541	#endif
1542
1543	pVCpu->hwaccm.s.Event.fPending = true;
1544	/* Error code present? (redundant) */
1545	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1546	pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1547	else
1548	pVCpu->hwaccm.s.Event.errCode = 0;
1549	}
1550	#ifdef VBOX_WITH_STATISTICS
1551	if (exitCode == SVM_EXIT_NPF)
1552	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
1553	else
1554	STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1555	#endif
1556
1557	/* Sync back the TPR if it was changed. */
1558	if (fSyncTPR)
1559	{
1560	if (pVM->hwaccm.s.fTPRPatchingActive)
1561	{
1562	if ((pCtx->msrLSTAR & 0xff) != u8LastTPR)
1563	{
1564	/* Our patch code uses LSTAR for TPR caching. */
1565	rc = PDMApicSetTPR(pVCpu, pCtx->msrLSTAR & 0xff);
1566	AssertRC(rc);
1567	}
1568	}
1569	else
1570	{
1571	if ((u8LastTPR >> 4) != pVMCB->ctrl.IntCtrl.n.u8VTPR)
1572	{
1573	rc = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1574	AssertRC(rc);
1575	}
1576	}
1577	}
1578
1579	STAM_PROFILE_ADV_STOP_START(&pVCpu->hwaccm.s.StatExit1, &pVCpu->hwaccm.s.StatExit2, x);
1580
1581	/* Deal with the reason of the VM-exit. */
1582	switch (exitCode)
1583	{
1584	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1585	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1586	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1587	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1588	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1589	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1590	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1591	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1592	{
1593	/* Pending trap. */
1594	SVM_EVENT Event;
1595	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1596
1597	Log2(("Hardware/software interrupt %d\n", vector));
1598	switch (vector)
1599	{
1600	case X86_XCPT_DB:
1601	{
1602	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
1603
1604	/* Note that we don't support guest and host-initiated debugging at the same time. */
1605	Assert(DBGFIsStepping(pVCpu) \|\| CPUMIsHyperDebugStateActive(pVCpu));
1606
1607	rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1608	if (rc == VINF_EM_RAW_GUEST_TRAP)
1609	{
1610	Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
1611
1612	/* Reinject the exception. */
1613	Event.au64[0] = 0;
1614	Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1615	Event.n.u1Valid = 1;
1616	Event.n.u8Vector = X86_XCPT_DB;
1617
1618	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1619	goto ResumeExecution;
1620	}
1621	/* Return to ring 3 to deal with the debug exit code. */
1622	Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
1623	break;
1624	}
1625
1626	case X86_XCPT_NM:
1627	{
1628	Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
1629
1630	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1631	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1632	rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
1633	if (rc == VINF_SUCCESS)
1634	{
1635	Assert(CPUMIsGuestFPUStateActive(pVCpu));
1636	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
1637
1638	/* Continue execution. */
1639	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1640
1641	goto ResumeExecution;
1642	}
1643
1644	Log(("Forward #NM fault to the guest\n"));
1645	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
1646
1647	Event.au64[0] = 0;
1648	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1649	Event.n.u1Valid = 1;
1650	Event.n.u8Vector = X86_XCPT_NM;
1651
1652	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1653	goto ResumeExecution;
1654	}
1655
1656	case X86_XCPT_PF: /* Page fault */
1657	{
1658	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1659	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1660
1661	#ifdef DEBUG
1662	if (pVM->hwaccm.s.fNestedPaging)
1663	{ /* A genuine pagefault.
1664	* Forward the trap to the guest by injecting the exception and resuming execution.
1665	*/
1666	Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1667	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1668
1669	/* Now we must update CR2. */
1670	pCtx->cr2 = uFaultAddress;
1671
1672	Event.au64[0] = 0;
1673	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1674	Event.n.u1Valid = 1;
1675	Event.n.u8Vector = X86_XCPT_PF;
1676	Event.n.u1ErrorCodeValid = 1;
1677	Event.n.u32ErrorCode = errCode;
1678
1679	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1680	goto ResumeExecution;
1681	}
1682	#endif
1683	Assert(!pVM->hwaccm.s.fNestedPaging);
1684
1685	#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1686	/* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1687	if ( pVM->hwaccm.s.fTRPPatchingAllowed
1688	&& (uFaultAddress & 0xfff) == 0x080
1689	&& !(errCode & X86_TRAP_PF_P) /* not present */
1690	&& CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1691	&& !CPUMIsGuestInLongModeEx(pCtx)
1692	&& pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1693	{
1694	RTGCPHYS GCPhysApicBase, GCPhys;
1695	PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1696	GCPhysApicBase &= PAGE_BASE_GC_MASK;
1697
1698	rc = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL, &GCPhys);
1699	if ( rc == VINF_SUCCESS
1700	&& GCPhys == GCPhysApicBase)
1701	{
1702	/* Only attempt to patch the instruction once. */
1703	PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1704	if (!pPatch)
1705	{
1706	rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1707	break;
1708	}
1709	}
1710	}
1711	#endif
1712
1713	Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1714	/* Exit qualification contains the linear address of the page fault. */
1715	TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1716	TRPMSetErrorCode(pVCpu, errCode);
1717	TRPMSetFaultAddress(pVCpu, uFaultAddress);
1718
1719	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1720	rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1721	Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1722	if (rc == VINF_SUCCESS)
1723	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1724	Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1725	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1726
1727	TRPMResetTrap(pVCpu);
1728	goto ResumeExecution;
1729	}
1730	else
1731	if (rc == VINF_EM_RAW_GUEST_TRAP)
1732	{ /* A genuine pagefault.
1733	* Forward the trap to the guest by injecting the exception and resuming execution.
1734	*/
1735	Log2(("Forward page fault to the guest\n"));
1736	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1737	/* The error code might have been changed. */
1738	errCode = TRPMGetErrorCode(pVCpu);
1739
1740	TRPMResetTrap(pVCpu);
1741
1742	/* Now we must update CR2. */
1743	pCtx->cr2 = uFaultAddress;
1744
1745	Event.au64[0] = 0;
1746	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1747	Event.n.u1Valid = 1;
1748	Event.n.u8Vector = X86_XCPT_PF;
1749	Event.n.u1ErrorCodeValid = 1;
1750	Event.n.u32ErrorCode = errCode;
1751
1752	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1753	goto ResumeExecution;
1754	}
1755	#ifdef VBOX_STRICT
1756	if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
1757	LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1758	#endif
1759	/* Need to go back to the recompiler to emulate the instruction. */
1760	TRPMResetTrap(pVCpu);
1761	break;
1762	}
1763
1764	case X86_XCPT_MF: /* Floating point exception. */
1765	{
1766	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
1767	if (!(pCtx->cr0 & X86_CR0_NE))
1768	{
1769	/* old style FPU error reporting needs some extra work. */
1770	/** @todo don't fall back to the recompiler, but do it manually. */
1771	rc = VINF_EM_RAW_EMULATE_INSTR;
1772	break;
1773	}
1774	Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
1775
1776	Event.au64[0] = 0;
1777	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1778	Event.n.u1Valid = 1;
1779	Event.n.u8Vector = X86_XCPT_MF;
1780
1781	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1782	goto ResumeExecution;
1783	}
1784
1785	#ifdef VBOX_STRICT
1786	case X86_XCPT_BP: /* Breakpoint. */
1787	case X86_XCPT_GP: /* General protection failure exception.*/
1788	case X86_XCPT_UD: /* Unknown opcode exception. */
1789	case X86_XCPT_DE: /* Divide error. */
1790	case X86_XCPT_SS: /* Stack segment exception. */
1791	case X86_XCPT_NP: /* Segment not present exception. */
1792	{
1793	Event.au64[0] = 0;
1794	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1795	Event.n.u1Valid = 1;
1796	Event.n.u8Vector = vector;
1797
1798	switch(vector)
1799	{
1800	case X86_XCPT_GP:
1801	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
1802	Event.n.u1ErrorCodeValid = 1;
1803	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1804	break;
1805	case X86_XCPT_BP:
1806	break;
1807	case X86_XCPT_DE:
1808	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
1809	break;
1810	case X86_XCPT_UD:
1811	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
1812	break;
1813	case X86_XCPT_SS:
1814	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
1815	Event.n.u1ErrorCodeValid = 1;
1816	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1817	break;
1818	case X86_XCPT_NP:
1819	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
1820	Event.n.u1ErrorCodeValid = 1;
1821	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1822	break;
1823	}
1824	Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->esi));
1825	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1826	goto ResumeExecution;
1827	}
1828	#endif
1829	default:
1830	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1831	rc = VERR_EM_INTERNAL_ERROR;
1832	break;
1833
1834	} /* switch (vector) */
1835	break;
1836	}
1837
1838	case SVM_EXIT_NPF:
1839	{
1840	/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1841	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1842	RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1843	PGMMODE enmShwPagingMode;
1844
1845	Assert(pVM->hwaccm.s.fNestedPaging);
1846	LogFlow(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1847
1848	#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1849	/* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1850	if ( pVM->hwaccm.s.fTRPPatchingAllowed
1851	&& (uFaultAddress & 0xfff) == 0x080
1852	&& !(errCode & X86_TRAP_PF_P) /* not present */
1853	&& CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1854	&& !CPUMIsGuestInLongModeEx(pCtx)
1855	&& pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1856	{
1857	RTGCPHYS GCPhysApicBase;
1858	PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1859	GCPhysApicBase &= PAGE_BASE_GC_MASK;
1860
1861	if (uFaultAddress == GCPhysApicBase + 0x80)
1862	{
1863	/* Only attempt to patch the instruction once. */
1864	PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1865	if (!pPatch)
1866	{
1867	rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1868	break;
1869	}
1870	}
1871	}
1872	#endif
1873
1874	/* Exit qualification contains the linear address of the page fault. */
1875	TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1876	TRPMSetErrorCode(pVCpu, errCode);
1877	TRPMSetFaultAddress(pVCpu, uFaultAddress);
1878
1879	/* Handle the pagefault trap for the nested shadow table. */
1880	#if HC_ARCH_BITS == 32
1881	if (CPUMIsGuestInLongModeEx(pCtx))
1882	enmShwPagingMode = PGMMODE_AMD64_NX;
1883	else
1884	#endif
1885	enmShwPagingMode = PGMGetHostMode(pVM);
1886
1887	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1888	Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1889	if (rc == VINF_SUCCESS)
1890	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1891	Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1892	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1893
1894	TRPMResetTrap(pVCpu);
1895	goto ResumeExecution;
1896	}
1897
1898	#ifdef VBOX_STRICT
1899	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1900	LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1901	#endif
1902	/* Need to go back to the recompiler to emulate the instruction. */
1903	TRPMResetTrap(pVCpu);
1904	break;
1905	}
1906
1907	case SVM_EXIT_VINTR:
1908	/* A virtual interrupt is about to be delivered, which means IF=1. */
1909	Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1910	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1911	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1912	goto ResumeExecution;
1913
1914	case SVM_EXIT_FERR_FREEZE:
1915	case SVM_EXIT_INTR:
1916	case SVM_EXIT_NMI:
1917	case SVM_EXIT_SMI:
1918	case SVM_EXIT_INIT:
1919	/* External interrupt; leave to allow it to be dispatched again. */
1920	rc = VINF_EM_RAW_INTERRUPT;
1921	break;
1922
1923	case SVM_EXIT_WBINVD:
1924	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1925	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
1926	/* Skip instruction and continue directly. */
1927	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1928	/* Continue execution.*/
1929	goto ResumeExecution;
1930
1931	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1932	{
1933	Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
1934	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
1935	rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1936	if (rc == VINF_SUCCESS)
1937	{
1938	/* Update EIP and continue execution. */
1939	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1940	goto ResumeExecution;
1941	}
1942	AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
1943	rc = VINF_EM_RAW_EMULATE_INSTR;
1944	break;
1945	}
1946
1947	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1948	{
1949	Log2(("SVM: Rdtsc\n"));
1950	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1951	rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1952	if (rc == VINF_SUCCESS)
1953	{
1954	/* Update EIP and continue execution. */
1955	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1956	goto ResumeExecution;
1957	}
1958	rc = VINF_EM_RAW_EMULATE_INSTR;
1959	break;
1960	}
1961
1962	case SVM_EXIT_RDPMC: /* Guest software attempted to execute RDPMC. */
1963	{
1964	Log2(("SVM: Rdpmc %x\n", pCtx->ecx));
1965	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
1966	rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1967	if (rc == VINF_SUCCESS)
1968	{
1969	/* Update EIP and continue execution. */
1970	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1971	goto ResumeExecution;
1972	}
1973	rc = VINF_EM_RAW_EMULATE_INSTR;
1974	break;
1975	}
1976
1977	case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
1978	{
1979	Log2(("SVM: Rdtscp\n"));
1980	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1981	rc = EMInterpretRdtscp(pVM, pVCpu, pCtx);
1982	if (rc == VINF_SUCCESS)
1983	{
1984	/* Update EIP and continue execution. */
1985	pCtx->rip += 3; /* Note! hardcoded opcode size! */
1986	goto ResumeExecution;
1987	}
1988	AssertMsgFailed(("EMU: rdtscp failed with %Rrc\n", rc));
1989	rc = VINF_EM_RAW_EMULATE_INSTR;
1990	break;
1991	}
1992
1993	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1994	{
1995	Log2(("SVM: invlpg\n"));
1996	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
1997
1998	Assert(!pVM->hwaccm.s.fNestedPaging);
1999
2000	/* Truly a pita. Why can't SVM give the same information as VT-x? */
2001	rc = svmR0InterpretInvpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
2002	if (rc == VINF_SUCCESS)
2003	{
2004	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageInvlpg);
2005	goto ResumeExecution; /* eip already updated */
2006	}
2007	break;
2008	}
2009
2010	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
2011	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
2012	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
2013	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
2014	{
2015	uint32_t cbSize;
2016
2017	Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
2018	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[exitCode - SVM_EXIT_WRITE_CR0]);
2019	rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2020
2021	switch (exitCode - SVM_EXIT_WRITE_CR0)
2022	{
2023	case 0:
2024	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
2025	break;
2026	case 2:
2027	break;
2028	case 3:
2029	Assert(!pVM->hwaccm.s.fNestedPaging);
2030	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
2031	break;
2032	case 4:
2033	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
2034	break;
2035	case 8:
2036	break;
2037	default:
2038	AssertFailed();
2039	}
2040	if (rc == VINF_SUCCESS)
2041	{
2042	/* EIP has been updated already. */
2043
2044	/* Only resume if successful. */
2045	goto ResumeExecution;
2046	}
2047	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
2048	break;
2049	}
2050
2051	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
2052	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
2053	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
2054	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
2055	{
2056	uint32_t cbSize;
2057
2058	Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
2059	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[exitCode - SVM_EXIT_READ_CR0]);
2060	rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2061	if (rc == VINF_SUCCESS)
2062	{
2063	/* EIP has been updated already. */
2064
2065	/* Only resume if successful. */
2066	goto ResumeExecution;
2067	}
2068	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
2069	break;
2070	}
2071
2072	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
2073	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
2074	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
2075	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
2076	{
2077	uint32_t cbSize;
2078
2079	Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
2080	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
2081
2082	if ( !DBGFIsStepping(pVCpu)
2083	&& !CPUMIsHyperDebugStateActive(pVCpu))
2084	{
2085	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2086
2087	/* Disable drx move intercepts. */
2088	pVMCB->ctrl.u16InterceptRdDRx = 0;
2089	pVMCB->ctrl.u16InterceptWrDRx = 0;
2090
2091	/* Save the host and load the guest debug state. */
2092	rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2093	AssertRC(rc);
2094	goto ResumeExecution;
2095	}
2096
2097	rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2098	if (rc == VINF_SUCCESS)
2099	{
2100	/* EIP has been updated already. */
2101	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
2102
2103	/* Only resume if successful. */
2104	goto ResumeExecution;
2105	}
2106	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
2107	break;
2108	}
2109
2110	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
2111	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
2112	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
2113	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
2114	{
2115	uint32_t cbSize;
2116
2117	Log2(("SVM: %RGv mov x, dr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
2118	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2119
2120	if (!DBGFIsStepping(pVCpu))
2121	{
2122	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2123
2124	/* Disable drx move intercepts. */
2125	pVMCB->ctrl.u16InterceptRdDRx = 0;
2126	pVMCB->ctrl.u16InterceptWrDRx = 0;
2127
2128	/* Save the host and load the guest debug state. */
2129	rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2130	AssertRC(rc);
2131	goto ResumeExecution;
2132	}
2133
2134	rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2135	if (rc == VINF_SUCCESS)
2136	{
2137	/* EIP has been updated already. */
2138
2139	/* Only resume if successful. */
2140	goto ResumeExecution;
2141	}
2142	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
2143	break;
2144	}
2145
2146	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2147	case SVM_EXIT_IOIO: /* I/O instruction. */
2148	{
2149	SVM_IOIO_EXIT IoExitInfo;
2150	uint32_t uIOSize, uAndVal;
2151
2152	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
2153
2154	/** @todo could use a lookup table here */
2155	if (IoExitInfo.n.u1OP8)
2156	{
2157	uIOSize = 1;
2158	uAndVal = 0xff;
2159	}
2160	else
2161	if (IoExitInfo.n.u1OP16)
2162	{
2163	uIOSize = 2;
2164	uAndVal = 0xffff;
2165	}
2166	else
2167	if (IoExitInfo.n.u1OP32)
2168	{
2169	uIOSize = 4;
2170	uAndVal = 0xffffffff;
2171	}
2172	else
2173	{
2174	AssertFailed(); /* should be fatal. */
2175	rc = VINF_EM_RAW_EMULATE_INSTR;
2176	break;
2177	}
2178
2179	if (IoExitInfo.n.u1STR)
2180	{
2181	/* ins/outs */
2182	PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2183
2184	/* Disassemble manually to deal with segment prefixes. */
2185	rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
2186	if (rc == VINF_SUCCESS)
2187	{
2188	if (IoExitInfo.n.u1Type == 0)
2189	{
2190	Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2191	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
2192	rc = VBOXSTRICTRC_TODO(IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize));
2193	}
2194	else
2195	{
2196	Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2197	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
2198	rc = VBOXSTRICTRC_TODO(IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize));
2199	}
2200	}
2201	else
2202	rc = VINF_EM_RAW_EMULATE_INSTR;
2203	}
2204	else
2205	{
2206	/* normal in/out */
2207	Assert(!IoExitInfo.n.u1REP);
2208
2209	if (IoExitInfo.n.u1Type == 0)
2210	{
2211	Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2212	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
2213	rc = VBOXSTRICTRC_TODO(IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2214	if (rc == VINF_IOM_HC_IOPORT_WRITE)
2215	HWACCMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2216	}
2217	else
2218	{
2219	uint32_t u32Val = 0;
2220
2221	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
2222	rc = VBOXSTRICTRC_TODO(IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize));
2223	if (IOM_SUCCESS(rc))
2224	{
2225	/* Write back to the EAX register. */
2226	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
2227	Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
2228	}
2229	else
2230	if (rc == VINF_IOM_HC_IOPORT_READ)
2231	HWACCMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2232	}
2233	}
2234	/*
2235	* Handled the I/O return codes.
2236	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2237	*/
2238	if (IOM_SUCCESS(rc))
2239	{
2240	/* Update EIP and continue execution. */
2241	pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
2242	if (RT_LIKELY(rc == VINF_SUCCESS))
2243	{
2244	/* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2245	if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2246	{
2247	/* IO operation lookup arrays. */
2248	static uint32_t const aIOSize[4] = {1, 2, 0, 4};
2249
2250	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
2251	for (unsigned i=0;i<4;i++)
2252	{
2253	unsigned uBPLen = aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2254
2255	if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
2256	&& (pCtx->dr[7] & (X86_DR7_L(i) \| X86_DR7_G(i)))
2257	&& (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2258	{
2259	SVM_EVENT Event;
2260
2261	Assert(CPUMIsGuestDebugStateActive(pVCpu));
2262
2263	/* Clear all breakpoint status flags and set the one we just hit. */
2264	pCtx->dr[6] &= ~(X86_DR6_B0\|X86_DR6_B1\|X86_DR6_B2\|X86_DR6_B3);
2265	pCtx->dr[6] \|= (uint64_t)RT_BIT(i);
2266
2267	/* Note: AMD64 Architecture Programmer's Manual 13.1:
2268	* Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2269	* the contents have been read.
2270	*/
2271	pVMCB->guest.u64DR6 = pCtx->dr[6];
2272
2273	/* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2274	pCtx->dr[7] &= ~X86_DR7_GD;
2275
2276	/* Paranoia. */
2277	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2278	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
2279	pCtx->dr[7] \|= 0x400; /* must be one */
2280
2281	pVMCB->guest.u64DR7 = pCtx->dr[7];
2282
2283	/* Inject the exception. */
2284	Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
2285
2286	Event.au64[0] = 0;
2287	Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
2288	Event.n.u1Valid = 1;
2289	Event.n.u8Vector = X86_XCPT_DB;
2290
2291	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2292	goto ResumeExecution;
2293	}
2294	}
2295	}
2296	goto ResumeExecution;
2297	}
2298	Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
2299	break;
2300	}
2301
2302	#ifdef VBOX_STRICT
2303	if (rc == VINF_IOM_HC_IOPORT_READ)
2304	Assert(IoExitInfo.n.u1Type != 0);
2305	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2306	Assert(IoExitInfo.n.u1Type == 0);
2307	else
2308	AssertMsg(RT_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
2309	#endif
2310	Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2311	break;
2312	}
2313
2314	case SVM_EXIT_HLT:
2315	/** Check if external interrupts are pending; if so, don't switch back. */
2316	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2317	pCtx->rip++; /* skip hlt */
2318	if (EMShouldContinueAfterHalt(pVCpu, pCtx))
2319	goto ResumeExecution;
2320
2321	rc = VINF_EM_HALT;
2322	break;
2323
2324	case SVM_EXIT_MWAIT_UNCOND:
2325	Log2(("SVM: mwait\n"));
2326	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
2327	rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2328	if ( rc == VINF_EM_HALT
2329	\|\| rc == VINF_SUCCESS)
2330	{
2331	/* Update EIP and continue execution. */
2332	pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2333
2334	/** Check if external interrupts are pending; if so, don't switch back. */
2335	if ( rc == VINF_SUCCESS
2336	\|\| ( rc == VINF_EM_HALT
2337	&& EMShouldContinueAfterHalt(pVCpu, pCtx))
2338	)
2339	goto ResumeExecution;
2340	}
2341	AssertMsg(rc == VERR_EM_INTERPRETER \|\| rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
2342	break;
2343
2344	case SVM_EXIT_MONITOR:
2345	{
2346	Log2(("SVM: monitor\n"));
2347
2348	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMonitor);
2349	rc = EMInterpretMonitor(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2350	if (rc == VINF_SUCCESS)
2351	{
2352	/* Update EIP and continue execution. */
2353	pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2354	goto ResumeExecution;
2355	}
2356	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: monitor failed with %Rrc\n", rc));
2357	break;
2358	}
2359
2360
2361	case SVM_EXIT_VMMCALL:
2362	rc = svmR0EmulateTprVMMCall(pVM, pVCpu, pCtx);
2363	if (rc == VINF_SUCCESS)
2364	{
2365	goto ResumeExecution; /* rip already updated. */
2366	}
2367	/* no break */
2368
2369	case SVM_EXIT_RSM:
2370	case SVM_EXIT_INVLPGA:
2371	case SVM_EXIT_VMRUN:
2372	case SVM_EXIT_VMLOAD:
2373	case SVM_EXIT_VMSAVE:
2374	case SVM_EXIT_STGI:
2375	case SVM_EXIT_CLGI:
2376	case SVM_EXIT_SKINIT:
2377	{
2378	/* Unsupported instructions. */
2379	SVM_EVENT Event;
2380
2381	Event.au64[0] = 0;
2382	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2383	Event.n.u1Valid = 1;
2384	Event.n.u8Vector = X86_XCPT_UD;
2385
2386	Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
2387	SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2388	goto ResumeExecution;
2389	}
2390
2391	/* Emulate in ring 3. */
2392	case SVM_EXIT_MSR:
2393	{
2394	uint32_t cbSize;
2395
2396	/* When an interrupt is pending, we'll let MSR_K8_LSTAR writes fault in our TPR patch code. */
2397	if ( pVM->hwaccm.s.fTPRPatchingActive
2398	&& pCtx->ecx == MSR_K8_LSTAR
2399	&& pVMCB->ctrl.u64ExitInfo1 == 1 /* wrmsr */)
2400	{
2401	if ((pCtx->eax & 0xff) != u8LastTPR)
2402	{
2403	Log(("SVM: Faulting MSR_K8_LSTAR write with new TPR value %x\n", pCtx->eax & 0xff));
2404
2405	/* Our patch code uses LSTAR for TPR caching. */
2406	rc = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
2407	AssertRC(rc);
2408	}
2409
2410	/* Skip the instruction and continue. */
2411	pCtx->rip += 2; /* wrmsr = [0F 30] */
2412
2413	/* Only resume if successful. */
2414	goto ResumeExecution;
2415	}
2416
2417	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2418	STAM_COUNTER_INC((pVMCB->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
2419	Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
2420	rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2421	if (rc == VINF_SUCCESS)
2422	{
2423	/* EIP has been updated already. */
2424
2425	/* Only resume if successful. */
2426	goto ResumeExecution;
2427	}
2428	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
2429	break;
2430	}
2431
2432	case SVM_EXIT_TASK_SWITCH: /* too complicated to emulate, so fall back to the recompiler*/
2433	Log(("SVM_EXIT_TASK_SWITCH: exit2=%RX64\n", pVMCB->ctrl.u64ExitInfo2));
2434	if ( !(pVMCB->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET \| SVM_EXIT2_TASK_SWITCH_JMP))
2435	&& pVCpu->hwaccm.s.Event.fPending)
2436	{
2437	SVM_EVENT Event;
2438
2439	Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
2440
2441	/* Caused by an injected interrupt. */
2442	pVCpu->hwaccm.s.Event.fPending = false;
2443
2444	switch (Event.n.u3Type)
2445	{
2446	case SVM_EVENT_EXTERNAL_IRQ:
2447	case SVM_EVENT_NMI:
2448	Log(("SVM_EXIT_TASK_SWITCH: reassert trap %d\n", Event.n.u8Vector));
2449	Assert(!Event.n.u1ErrorCodeValid);
2450	rc = TRPMAssertTrap(pVCpu, Event.n.u8Vector, TRPM_HARDWARE_INT);
2451	AssertRC(rc);
2452	break;
2453
2454	default:
2455	/* Exceptions and software interrupts can just be restarted. */
2456	break;
2457	}
2458	}
2459	rc = VERR_EM_INTERPRETER;
2460	break;
2461
2462	case SVM_EXIT_PAUSE:
2463	case SVM_EXIT_MWAIT_ARMED:
2464	rc = VERR_EM_INTERPRETER;
2465	break;
2466
2467	case SVM_EXIT_SHUTDOWN:
2468	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2469	break;
2470
2471	case SVM_EXIT_IDTR_READ:
2472	case SVM_EXIT_GDTR_READ:
2473	case SVM_EXIT_LDTR_READ:
2474	case SVM_EXIT_TR_READ:
2475	case SVM_EXIT_IDTR_WRITE:
2476	case SVM_EXIT_GDTR_WRITE:
2477	case SVM_EXIT_LDTR_WRITE:
2478	case SVM_EXIT_TR_WRITE:
2479	case SVM_EXIT_CR0_SEL_WRITE:
2480	default:
2481	/* Unexpected exit codes. */
2482	rc = VERR_EM_INTERNAL_ERROR;
2483	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2484	break;
2485	}
2486
2487	end:
2488
2489	/* Signal changes for the recompiler. */
2490	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
2491
2492	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
2493	if (exitCode == SVM_EXIT_INTR)
2494	{
2495	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
2496	/* On the next entry we'll only sync the host context. */
2497	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
2498	}
2499	else
2500	{
2501	/* On the next entry we'll sync everything. */
2502	/** @todo we can do better than this */
2503	/* Not in the VINF_PGM_CHANGE_MODE though! */
2504	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
2505	}
2506
2507	/* translate into a less severe return code */
2508	if (rc == VERR_EM_INTERPRETER)
2509	rc = VINF_EM_RAW_EMULATE_INSTR;
2510
2511	/* Just set the correct state here instead of trying to catch every goto above. */
2512	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
2513
2514	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2515	/* Restore interrupts if we exitted after disabling them. */
2516	if (uOldEFlags != ~(RTCCUINTREG)0)
2517	ASMSetFlags(uOldEFlags);
2518	#endif
2519
2520	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit2, x);
2521	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2522	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
2523	return rc;
2524	}
2525
2526	/**
2527	* Emulate simple mov tpr instruction
2528	*
2529	* @returns VBox status code.
2530	* @param pVM The VM to operate on.
2531	* @param pVCpu The VM CPU to operate on.
2532	* @param pCtx CPU context
2533	*/
2534	static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2535	{
2536	int rc;
2537
2538	LogFlow(("Emulated VMMCall TPR access replacement at %RGv\n", pCtx->rip));
2539
2540	while (true)
2541	{
2542	bool fPending;
2543	uint8_t u8Tpr;
2544
2545	PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2546	if (!pPatch)
2547	break;
2548
2549	switch(pPatch->enmType)
2550	{
2551	case HWACCMTPRINSTR_READ:
2552	/* TPR caching in CR8 */
2553	rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending);
2554	AssertRC(rc);
2555
2556	rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
2557	AssertRC(rc);
2558
2559	LogFlow(("Emulated read successfully\n"));
2560	pCtx->rip += pPatch->cbOp;
2561	break;
2562
2563	case HWACCMTPRINSTR_WRITE_REG:
2564	case HWACCMTPRINSTR_WRITE_IMM:
2565	/* Fetch the new TPR value */
2566	if (pPatch->enmType == HWACCMTPRINSTR_WRITE_REG)
2567	{
2568	uint32_t val;
2569
2570	rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &val);
2571	AssertRC(rc);
2572	u8Tpr = val;
2573	}
2574	else
2575	u8Tpr = (uint8_t)pPatch->uSrcOperand;
2576
2577	rc = PDMApicSetTPR(pVCpu, u8Tpr);
2578	AssertRC(rc);
2579	LogFlow(("Emulated write successfully\n"));
2580	pCtx->rip += pPatch->cbOp;
2581	break;
2582	default:
2583	AssertMsgFailedReturn(("Unexpected type %d\n", pPatch->enmType), VERR_INTERNAL_ERROR);
2584	}
2585	}
2586	return VINF_SUCCESS;
2587	}
2588
2589
2590	/**
2591	* Enters the AMD-V session
2592	*
2593	* @returns VBox status code.
2594	* @param pVM The VM to operate on.
2595	* @param pVCpu The VM CPU to operate on.
2596	* @param pCpu CPU info struct
2597	*/
2598	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
2599	{
2600	Assert(pVM->hwaccm.s.svm.fSupported);
2601
2602	LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
2603	pVCpu->hwaccm.s.fResumeVM = false;
2604
2605	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2606	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
2607
2608	return VINF_SUCCESS;
2609	}
2610
2611
2612	/**
2613	* Leaves the AMD-V session
2614	*
2615	* @returns VBox status code.
2616	* @param pVM The VM to operate on.
2617	* @param pVCpu The VM CPU to operate on.
2618	* @param pCtx CPU context
2619	*/
2620	VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2621	{
2622	SVM_VMCB pVMCB = (SVM_VMCB )pVCpu->hwaccm.s.svm.pVMCB;
2623
2624	Assert(pVM->hwaccm.s.svm.fSupported);
2625
2626	#ifdef DEBUG
2627	if (CPUMIsHyperDebugStateActive(pVCpu))
2628	{
2629	CPUMR0LoadHostDebugState(pVM, pVCpu);
2630	}
2631	else
2632	#endif
2633	/* Save the guest debug state if necessary. */
2634	if (CPUMIsGuestDebugStateActive(pVCpu))
2635	{
2636	CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
2637
2638	/* Intercept all DRx reads and writes again. Changed later on. */
2639	pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
2640	pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
2641
2642	/* Resync the debug registers the next time. */
2643	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
2644	}
2645	else
2646	Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
2647
2648	return VINF_SUCCESS;
2649	}
2650
2651
2652	static int svmR0InterpretInvlPg(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2653	{
2654	OP_PARAMVAL param1;
2655	RTGCPTR addr;
2656
2657	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2658	if(RT_FAILURE(rc))
2659	return VERR_EM_INTERPRETER;
2660
2661	switch(param1.type)
2662	{
2663	case PARMTYPE_IMMEDIATE:
2664	case PARMTYPE_ADDRESS:
2665	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
2666	return VERR_EM_INTERPRETER;
2667	addr = param1.val.val64;
2668	break;
2669
2670	default:
2671	return VERR_EM_INTERPRETER;
2672	}
2673
2674	/** @todo is addr always a flat linear address or ds based
2675	* (in absence of segment override prefixes)????
2676	*/
2677	rc = PGMInvalidatePage(pVCpu, addr);
2678	if (RT_SUCCESS(rc))
2679	return VINF_SUCCESS;
2680
2681	AssertRC(rc);
2682	return rc;
2683	}
2684
2685	/**
2686	* Interprets INVLPG
2687	*
2688	* @returns VBox status code.
2689	* @retval VINF_* Scheduling instructions.
2690	* @retval VERR_EM_INTERPRETER Something we can't cope with.
2691	* @retval VERR_* Fatal errors.
2692	*
2693	* @param pVM The VM handle.
2694	* @param pRegFrame The register frame.
2695	* @param ASID Tagged TLB id for the guest
2696	*
2697	* Updates the EIP if an instruction was executed successfully.
2698	*/
2699	static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2700	{
2701	/*
2702	* Only allow 32 & 64 bits code.
2703	*/
2704	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2705	if (enmMode != CPUMODE_16BIT)
2706	{
2707	RTGCPTR pbCode;
2708	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
2709	&pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2710	if (RT_SUCCESS(rc))
2711	{
2712	uint32_t cbOp;
2713	PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2714
2715	pDis->mode = enmMode;
2716	rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, pDis, &cbOp);
2717	Assert(RT_FAILURE(rc) \|\| pDis->pCurInstr->opcode == OP_INVLPG);
2718	if (RT_SUCCESS(rc) && pDis->pCurInstr->opcode == OP_INVLPG)
2719	{
2720	Assert(cbOp == pDis->opsize);
2721	rc = svmR0InterpretInvlPg(pVCpu, pDis, pRegFrame, uASID);
2722	if (RT_SUCCESS(rc))
2723	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2724
2725	return rc;
2726	}
2727	}
2728	}
2729	return VERR_EM_INTERPRETER;
2730	}
2731
2732
2733	/**
2734	* Invalidates a guest page
2735	*
2736	* @returns VBox status code.
2737	* @param pVM The VM to operate on.
2738	* @param pVCpu The VM CPU to operate on.
2739	* @param GCVirt Page to invalidate
2740	*/
2741	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
2742	{
2743	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH);
2744
2745	/* Skip it if a TLB flush is already pending. */
2746	if (!fFlushPending)
2747	{
2748	SVM_VMCB *pVMCB;
2749
2750	Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
2751	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2752	Assert(pVM->hwaccm.s.svm.fSupported);
2753
2754	pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2755	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2756
2757	#if HC_ARCH_BITS == 32
2758	/* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
2759	if (CPUMIsGuestInLongMode(pVCpu))
2760	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2761	else
2762	#endif
2763	SVMR0InvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2764	}
2765	return VINF_SUCCESS;
2766	}
2767
2768
2769	#if 0 /* obsolete, but left here for clarification. */
2770	/**
2771	* Invalidates a guest page by physical address
2772	*
2773	* @returns VBox status code.
2774	* @param pVM The VM to operate on.
2775	* @param pVCpu The VM CPU to operate on.
2776	* @param GCPhys Page to invalidate
2777	*/
2778	VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
2779	{
2780	Assert(pVM->hwaccm.s.fNestedPaging);
2781	/* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
2782	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2783	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBInvlpga);
2784	return VINF_SUCCESS;
2785	}
2786	#endif
2787
2788	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2789	/**
2790	* Prepares for and executes VMRUN (64 bits guests from a 32 bits hosts).
2791	*
2792	* @returns VBox status code.
2793	* @param pVMCBHostPhys Physical address of host VMCB.
2794	* @param pVMCBPhys Physical address of the VMCB.
2795	* @param pCtx Guest context.
2796	* @param pVM The VM to operate on.
2797	* @param pVCpu The VMCPU to operate on.
2798	*/
2799	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
2800	{
2801	uint32_t aParam[4];
2802
2803	aParam[0] = (uint32_t)(pVMCBHostPhys); /* Param 1: pVMCBHostPhys - Lo. */
2804	aParam[1] = (uint32_t)(pVMCBHostPhys >> 32); /* Param 1: pVMCBHostPhys - Hi. */
2805	aParam[2] = (uint32_t)(pVMCBPhys); /* Param 2: pVMCBPhys - Lo. */
2806	aParam[3] = (uint32_t)(pVMCBPhys >> 32); /* Param 2: pVMCBPhys - Hi. */
2807
2808	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSVMGCVMRun64, 4, &aParam[0]);
2809	}
2810
2811	/**
2812	* Executes the specified handler in 64 mode
2813	*
2814	* @returns VBox status code.
2815	* @param pVM The VM to operate on.
2816	* @param pVCpu The VMCPU to operate on.
2817	* @param pCtx Guest context
2818	* @param pfnHandler RC handler
2819	* @param cbParam Number of parameters
2820	* @param paParam Array of 32 bits parameters
2821	*/
2822	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
2823	{
2824	int rc;
2825	RTHCUINTREG uOldEFlags;
2826
2827	Assert(pfnHandler);
2828
2829	/* Disable interrupts. */
2830	uOldEFlags = ASMIntDisableFlags();
2831
2832	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
2833	CPUMSetHyperEIP(pVCpu, pfnHandler);
2834	for (int i=(int)cbParam-1;i>=0;i--)
2835	CPUMPushHyper(pVCpu, paParam[i]);
2836
2837	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2838	/* Call switcher. */
2839	rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
2840	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2841
2842	ASMSetFlags(uOldEFlags);
2843	return rc;
2844	}
2845
2846	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 30590

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