VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 30263

Last change on this file since 30263 was 30263, checked in by vboxsync, 14 years ago

VMM,REM: Only invalidate hidden registers when using raw-mode. Fixes save restore during mode switching code like the windows boot menu. (#5057)
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1/* $Id: HWSVMR0.cpp 30263 2010-06-16 18:31:42Z vboxsync $ */
2/** @file
3 * HWACCM SVM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HWACCM
22#include <VBox/hwaccm.h>
23#include <VBox/pgm.h>
24#include <VBox/selm.h>
25#include <VBox/iom.h>
26#include <VBox/dbgf.h>
27#include <VBox/tm.h>
28#include <VBox/pdmapi.h>
29#include "HWACCMInternal.h"
30#include <VBox/vm.h>
31#include <VBox/x86.h>
32#include <VBox/hwacc_svm.h>
33#include <VBox/err.h>
34#include <VBox/log.h>
35#include <VBox/dis.h>
36#include <VBox/disopcode.h>
37#include <iprt/param.h>
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/asm-amd64-x86.h>
41#include <iprt/cpuset.h>
42#include <iprt/mp.h>
43#include <iprt/time.h>
44#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
45# include <iprt/thread.h>
46#endif
47#include "HWSVMR0.h"
48
49/*******************************************************************************
50* Internal Functions *
51*******************************************************************************/
52static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID);
53static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
54static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);
55
56/*******************************************************************************
57* Global Variables *
58*******************************************************************************/
59
60/**
61 * Sets up and activates AMD-V on the current CPU
62 *
63 * @returns VBox status code.
64 * @param pCpu CPU info struct
65 * @param pVM The VM to operate on. (can be NULL after a resume!!)
66 * @param pvPageCpu Pointer to the global cpu page
67 * @param pPageCpuPhys Physical address of the global cpu page
68 */
69VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
70{
71 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
72 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
73
74 /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
75 uint64_t val = ASMRdMsr(MSR_K6_EFER);
76 if (val & MSR_K6_EFER_SVME)
77 {
78 /* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active, then we blindly use AMD-V. */
79 if ( pVM
80 && pVM->hwaccm.s.svm.fIgnoreInUseError)
81 {
82 pCpu->fIgnoreAMDVInUseError = true;
83 }
84
85 if (!pCpu->fIgnoreAMDVInUseError)
86 return VERR_SVM_IN_USE;
87 }
88
89 /* Turn on AMD-V in the EFER MSR. */
90 ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);
91
92 /* Write the physical page address where the CPU will store the host state while executing the VM. */
93 ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
94
95 return VINF_SUCCESS;
96}
97
98/**
99 * Deactivates AMD-V on the current CPU
100 *
101 * @returns VBox status code.
102 * @param pCpu CPU info struct
103 * @param pvPageCpu Pointer to the global cpu page
104 * @param pPageCpuPhys Physical address of the global cpu page
105 */
106VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
107{
108 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
109 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
110
111 /* Turn off AMD-V in the EFER MSR. */
112 uint64_t val = ASMRdMsr(MSR_K6_EFER);
113 ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
114
115 /* Invalidate host state physical address. */
116 ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
117
118 return VINF_SUCCESS;
119}
120
121/**
122 * Does Ring-0 per VM AMD-V init.
123 *
124 * @returns VBox status code.
125 * @param pVM The VM to operate on.
126 */
127VMMR0DECL(int) SVMR0InitVM(PVM pVM)
128{
129 int rc;
130
131 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
132
133 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
134 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
135 if (RT_FAILURE(rc))
136 return rc;
137
138 pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
139 pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
140 /* Set all bits to intercept all IO accesses. */
141 ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
142
143 /* Erratum 170 which requires a forced TLB flush for each world switch:
144 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
145 *
146 * All BH-G1/2 and DH-G1/2 models include a fix:
147 * Athlon X2: 0x6b 1/2
148 * 0x68 1/2
149 * Athlon 64: 0x7f 1
150 * 0x6f 2
151 * Sempron: 0x7f 1/2
152 * 0x6f 2
153 * 0x6c 2
154 * 0x7c 2
155 * Turion 64: 0x68 2
156 *
157 */
158 uint32_t u32Dummy;
159 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
160 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
161 u32BaseFamily= (u32Version >> 8) & 0xf;
162 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
163 u32Model = ((u32Version >> 4) & 0xf);
164 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
165 u32Stepping = u32Version & 0xf;
166 if ( u32Family == 0xf
167 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
168 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
169 {
170 Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
171 pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
172 }
173
174 /* Allocate VMCBs for all guest CPUs. */
175 for (VMCPUID i = 0; i < pVM->cCpus; i++)
176 {
177 PVMCPU pVCpu = &pVM->aCpus[i];
178
179 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
180 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
181 pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
182
183 /* Allocate one page for the host context */
184 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
185 if (RT_FAILURE(rc))
186 return rc;
187
188 pVCpu->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCBHost);
189 pVCpu->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 0);
190 Assert(pVCpu->hwaccm.s.svm.pVMCBHostPhys < _4G);
191 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCBHost);
192
193 /* Allocate one page for the VM control block (VMCB). */
194 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
195 if (RT_FAILURE(rc))
196 return rc;
197
198 pVCpu->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCB);
199 pVCpu->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCB, 0);
200 Assert(pVCpu->hwaccm.s.svm.pVMCBPhys < _4G);
201 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCB);
202
203 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
204 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
205 if (RT_FAILURE(rc))
206 return rc;
207
208 pVCpu->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap);
209 pVCpu->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 0);
210 /* Set all bits to intercept all MSR accesses. */
211 ASMMemFill32(pVCpu->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
212 }
213
214 return VINF_SUCCESS;
215}
216
217/**
218 * Does Ring-0 per VM AMD-V termination.
219 *
220 * @returns VBox status code.
221 * @param pVM The VM to operate on.
222 */
223VMMR0DECL(int) SVMR0TermVM(PVM pVM)
224{
225 for (VMCPUID i = 0; i < pVM->cCpus; i++)
226 {
227 PVMCPU pVCpu = &pVM->aCpus[i];
228
229 if (pVCpu->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
230 {
231 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, false);
232 pVCpu->hwaccm.s.svm.pVMCBHost = 0;
233 pVCpu->hwaccm.s.svm.pVMCBHostPhys = 0;
234 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
235 }
236
237 if (pVCpu->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
238 {
239 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCB, false);
240 pVCpu->hwaccm.s.svm.pVMCB = 0;
241 pVCpu->hwaccm.s.svm.pVMCBPhys = 0;
242 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
243 }
244 if (pVCpu->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
245 {
246 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, false);
247 pVCpu->hwaccm.s.svm.pMSRBitmap = 0;
248 pVCpu->hwaccm.s.svm.pMSRBitmapPhys = 0;
249 pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
250 }
251 }
252 if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
253 {
254 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
255 pVM->hwaccm.s.svm.pIOBitmap = 0;
256 pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
257 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
258 }
259 return VINF_SUCCESS;
260}
261
262/**
263 * Sets up AMD-V for the specified VM
264 *
265 * @returns VBox status code.
266 * @param pVM The VM to operate on.
267 */
268VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
269{
270 int rc = VINF_SUCCESS;
271
272 AssertReturn(pVM, VERR_INVALID_PARAMETER);
273
274 Assert(pVM->hwaccm.s.svm.fSupported);
275
276 for (VMCPUID i = 0; i < pVM->cCpus; i++)
277 {
278 PVMCPU pVCpu = &pVM->aCpus[i];
279 SVM_VMCB *pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
280
281 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
282
283 /* Program the control fields. Most of them never have to be changed again. */
284 /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
285 /* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
286 if (!pVM->hwaccm.s.fNestedPaging)
287 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
288 else
289 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4);
290
291 /*
292 * CR0/3/4 writes must be intercepted for obvious reasons.
293 */
294 if (!pVM->hwaccm.s.fNestedPaging)
295 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
296 else
297 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4);
298
299 /* Intercept all DRx reads and writes by default. Changed later on. */
300 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
301 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
302
303 /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
304 * All breakpoints are automatically cleared when the VM exits.
305 */
306
307 pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
308#ifndef DEBUG
309 if (pVM->hwaccm.s.fNestedPaging)
310 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
311#endif
312
313 pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
314 | SVM_CTRL1_INTERCEPT_VINTR
315 | SVM_CTRL1_INTERCEPT_NMI
316 | SVM_CTRL1_INTERCEPT_SMI
317 | SVM_CTRL1_INTERCEPT_INIT
318 | SVM_CTRL1_INTERCEPT_RDPMC
319 | SVM_CTRL1_INTERCEPT_CPUID
320 | SVM_CTRL1_INTERCEPT_RSM
321 | SVM_CTRL1_INTERCEPT_HLT
322 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP
323 | SVM_CTRL1_INTERCEPT_MSR_SHADOW
324 | SVM_CTRL1_INTERCEPT_INVLPG
325 | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
326 | SVM_CTRL1_INTERCEPT_TASK_SWITCH
327 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
328 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
329 ;
330 /* With nested paging we don't care about invlpg anymore. */
331 if (pVM->hwaccm.s.fNestedPaging)
332 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
333
334 pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
335 | SVM_CTRL2_INTERCEPT_VMMCALL
336 | SVM_CTRL2_INTERCEPT_VMLOAD
337 | SVM_CTRL2_INTERCEPT_VMSAVE
338 | SVM_CTRL2_INTERCEPT_STGI
339 | SVM_CTRL2_INTERCEPT_CLGI
340 | SVM_CTRL2_INTERCEPT_SKINIT
341 | SVM_CTRL2_INTERCEPT_WBINVD
342 | SVM_CTRL2_INTERCEPT_MONITOR
343 | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
344 ;
345 Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
346 Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
347 Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
348
349 /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
350 pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
351 /* Ignore the priority in the TPR; just deliver it when we tell it to. */
352 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
353
354 /* Set IO and MSR bitmap addresses. */
355 pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
356 pVMCB->ctrl.u64MSRPMPhysAddr = pVCpu->hwaccm.s.svm.pMSRBitmapPhys;
357
358 /* No LBR virtualization. */
359 pVMCB->ctrl.u64LBRVirt = 0;
360
361 /** The ASID must start at 1; the host uses 0. */
362 pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
363
364 /** Setup the PAT msr (nested paging only) */
365 /* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB, so choose type 6 for all PAT slots. */
366 pVMCB->guest.u64GPAT = 0x0006060606060606ULL;
367
368 /* The following MSRs are saved automatically by vmload/vmsave, so we allow the guest
369 * to modify them directly.
370 */
371 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
372 svmR0SetMSRPermission(pVCpu, MSR_K8_CSTAR, true, true);
373 svmR0SetMSRPermission(pVCpu, MSR_K6_STAR, true, true);
374 svmR0SetMSRPermission(pVCpu, MSR_K8_SF_MASK, true, true);
375 svmR0SetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true);
376 svmR0SetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true);
377 svmR0SetMSRPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, true, true);
378 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_CS, true, true);
379 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_ESP, true, true);
380 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_EIP, true, true);
381 }
382
383 return rc;
384}
385
386
387/**
388 * Sets the permission bits for the specified MSR
389 *
390 * @param pVCpu The VMCPU to operate on.
391 * @param ulMSR MSR value
392 * @param fRead Reading allowed/disallowed
393 * @param fWrite Writing allowed/disallowed
394 */
395static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)
396{
397 unsigned ulBit;
398 uint8_t *pMSRBitmap = (uint8_t *)pVCpu->hwaccm.s.svm.pMSRBitmap;
399
400 if (ulMSR <= 0x00001FFF)
401 {
402 /* Pentium-compatible MSRs */
403 ulBit = ulMSR * 2;
404 }
405 else
406 if ( ulMSR >= 0xC0000000
407 && ulMSR <= 0xC0001FFF)
408 {
409 /* AMD Sixth Generation x86 Processor MSRs and SYSCALL */
410 ulBit = (ulMSR - 0xC0000000) * 2;
411 pMSRBitmap += 0x800;
412 }
413 else
414 if ( ulMSR >= 0xC0010000
415 && ulMSR <= 0xC0011FFF)
416 {
417 /* AMD Seventh and Eighth Generation Processor MSRs */
418 ulBit = (ulMSR - 0xC0001000) * 2;
419 pMSRBitmap += 0x1000;
420 }
421 else
422 {
423 AssertFailed();
424 return;
425 }
426 Assert(ulBit < 16 * 1024 - 1);
427 if (fRead)
428 ASMBitClear(pMSRBitmap, ulBit);
429 else
430 ASMBitSet(pMSRBitmap, ulBit);
431
432 if (fWrite)
433 ASMBitClear(pMSRBitmap, ulBit + 1);
434 else
435 ASMBitSet(pMSRBitmap, ulBit + 1);
436}
437
438/**
439 * Injects an event (trap or external interrupt)
440 *
441 * @param pVCpu The VMCPU to operate on.
442 * @param pVMCB SVM control block
443 * @param pCtx CPU Context
444 * @param pIntInfo SVM interrupt info
445 */
446inline void SVMR0InjectEvent(PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)
447{
448#ifdef VBOX_WITH_STATISTICS
449 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
450#endif
451
452#ifdef VBOX_STRICT
453 if (pEvent->n.u8Vector == 0xE)
454 Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
455 else
456 if (pEvent->n.u8Vector < 0x20)
457 Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
458 else
459 {
460 Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
461 Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
462 Assert(pCtx->eflags.u32 & X86_EFL_IF);
463 }
464#endif
465
466 /* Set event injection state. */
467 pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
468}
469
470
471/**
472 * Checks for pending guest interrupts and injects them
473 *
474 * @returns VBox status code.
475 * @param pVM The VM to operate on.
476 * @param pVCpu The VM CPU to operate on.
477 * @param pVMCB SVM control block
478 * @param pCtx CPU Context
479 */
480static int SVMR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
481{
482 int rc;
483
484 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
485 if (pVCpu->hwaccm.s.Event.fPending)
486 {
487 SVM_EVENT Event;
488
489 Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
490 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
491 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
492 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
493
494 pVCpu->hwaccm.s.Event.fPending = false;
495 return VINF_SUCCESS;
496 }
497
498 /* If an active trap is already pending, then we must forward it first! */
499 if (!TRPMHasTrap(pVCpu))
500 {
501 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI))
502 {
503 SVM_EVENT Event;
504
505 Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
506 Event.n.u8Vector = X86_XCPT_NMI;
507 Event.n.u1Valid = 1;
508 Event.n.u32ErrorCode = 0;
509 Event.n.u3Type = SVM_EVENT_NMI;
510
511 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
512 return VINF_SUCCESS;
513 }
514
515 /* @todo SMI interrupts. */
516
517 /* When external interrupts are pending, we should exit the VM when IF is set. */
518 if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
519 {
520 if ( !(pCtx->eflags.u32 & X86_EFL_IF)
521 || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
522 {
523 if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
524 {
525 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
526 LogFlow(("Enable irq window exit!\n"));
527 else
528 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
529
530 /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
531 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
532 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
533 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
534 }
535 }
536 else
537 {
538 uint8_t u8Interrupt;
539
540 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
541 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
542 if (RT_SUCCESS(rc))
543 {
544 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
545 AssertRC(rc);
546 }
547 else
548 {
549 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
550 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
551 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
552 /* Just continue */
553 }
554 }
555 }
556 }
557
558#ifdef VBOX_STRICT
559 if (TRPMHasTrap(pVCpu))
560 {
561 uint8_t u8Vector;
562 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
563 AssertRC(rc);
564 }
565#endif
566
567 if ( (pCtx->eflags.u32 & X86_EFL_IF)
568 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
569 && TRPMHasTrap(pVCpu)
570 )
571 {
572 uint8_t u8Vector;
573 TRPMEVENT enmType;
574 SVM_EVENT Event;
575 RTGCUINT u32ErrorCode;
576
577 Event.au64[0] = 0;
578
579 /* If a new event is pending, then dispatch it now. */
580 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, 0);
581 AssertRC(rc);
582 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
583 Assert(enmType != TRPM_SOFTWARE_INT);
584
585 /* Clear the pending trap. */
586 rc = TRPMResetTrap(pVCpu);
587 AssertRC(rc);
588
589 Event.n.u8Vector = u8Vector;
590 Event.n.u1Valid = 1;
591 Event.n.u32ErrorCode = u32ErrorCode;
592
593 if (enmType == TRPM_TRAP)
594 {
595 switch (u8Vector) {
596 case 8:
597 case 10:
598 case 11:
599 case 12:
600 case 13:
601 case 14:
602 case 17:
603 /* Valid error codes. */
604 Event.n.u1ErrorCodeValid = 1;
605 break;
606 default:
607 break;
608 }
609 if (u8Vector == X86_XCPT_NMI)
610 Event.n.u3Type = SVM_EVENT_NMI;
611 else
612 Event.n.u3Type = SVM_EVENT_EXCEPTION;
613 }
614 else
615 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
616
617 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
618 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
619 } /* if (interrupts can be dispatched) */
620
621 return VINF_SUCCESS;
622}
623
624/**
625 * Save the host state
626 *
627 * @returns VBox status code.
628 * @param pVM The VM to operate on.
629 * @param pVCpu The VM CPU to operate on.
630 */
631VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
632{
633 NOREF(pVM);
634 NOREF(pVCpu);
635 /* Nothing to do here. */
636 return VINF_SUCCESS;
637}
638
639/**
640 * Loads the guest state
641 *
642 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
643 *
644 * @returns VBox status code.
645 * @param pVM The VM to operate on.
646 * @param pVCpu The VM CPU to operate on.
647 * @param pCtx Guest context
648 */
649VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
650{
651 RTGCUINTPTR val;
652 SVM_VMCB *pVMCB;
653
654 if (pVM == NULL)
655 return VERR_INVALID_PARAMETER;
656
657 /* Setup AMD SVM. */
658 Assert(pVM->hwaccm.s.svm.fSupported);
659
660 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
661 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
662
663 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
664 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
665 {
666 SVM_WRITE_SELREG(CS, cs);
667 SVM_WRITE_SELREG(SS, ss);
668 SVM_WRITE_SELREG(DS, ds);
669 SVM_WRITE_SELREG(ES, es);
670 SVM_WRITE_SELREG(FS, fs);
671 SVM_WRITE_SELREG(GS, gs);
672 }
673
674 /* Guest CPU context: LDTR. */
675 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
676 {
677 SVM_WRITE_SELREG(LDTR, ldtr);
678 }
679
680 /* Guest CPU context: TR. */
681 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
682 {
683 SVM_WRITE_SELREG(TR, tr);
684 }
685
686 /* Guest CPU context: GDTR. */
687 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
688 {
689 pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
690 pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
691 }
692
693 /* Guest CPU context: IDTR. */
694 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
695 {
696 pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
697 pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
698 }
699
700 /*
701 * Sysenter MSRs (unconditional)
702 */
703 pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
704 pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
705 pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
706
707 /* Control registers */
708 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
709 {
710 val = pCtx->cr0;
711 if (!CPUMIsGuestFPUStateActive(pVCpu))
712 {
713 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
714 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
715 }
716 else
717 {
718 /** @todo check if we support the old style mess correctly. */
719 if (!(val & X86_CR0_NE))
720 {
721 Log(("Forcing X86_CR0_NE!!!\n"));
722
723 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
724 if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)
725 {
726 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_MF);
727 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
728 }
729 }
730 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
731 }
732 /* Always enable caching. */
733 val &= ~(X86_CR0_CD|X86_CR0_NW);
734
735 /* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
736 /* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
737 if (!pVM->hwaccm.s.fNestedPaging)
738 {
739 val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
740 val |= X86_CR0_WP; /* Must set this as we rely on protecting various pages and supervisor writes must be caught. */
741 }
742 pVMCB->guest.u64CR0 = val;
743 }
744 /* CR2 as well */
745 pVMCB->guest.u64CR2 = pCtx->cr2;
746
747 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
748 {
749 /* Save our shadow CR3 register. */
750 if (pVM->hwaccm.s.fNestedPaging)
751 {
752 PGMMODE enmShwPagingMode;
753
754#if HC_ARCH_BITS == 32
755 if (CPUMIsGuestInLongModeEx(pCtx))
756 enmShwPagingMode = PGMMODE_AMD64_NX;
757 else
758#endif
759 enmShwPagingMode = PGMGetHostMode(pVM);
760
761 pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
762 Assert(pVMCB->ctrl.u64NestedPagingCR3);
763 pVMCB->guest.u64CR3 = pCtx->cr3;
764 }
765 else
766 {
767 pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
768 Assert(pVMCB->guest.u64CR3 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
769 }
770 }
771
772 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
773 {
774 val = pCtx->cr4;
775 if (!pVM->hwaccm.s.fNestedPaging)
776 {
777 switch(pVCpu->hwaccm.s.enmShadowMode)
778 {
779 case PGMMODE_REAL:
780 case PGMMODE_PROTECTED: /* Protected mode, no paging. */
781 AssertFailed();
782 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
783
784 case PGMMODE_32_BIT: /* 32-bit paging. */
785 val &= ~X86_CR4_PAE;
786 break;
787
788 case PGMMODE_PAE: /* PAE paging. */
789 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
790 /** @todo use normal 32 bits paging */
791 val |= X86_CR4_PAE;
792 break;
793
794 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
795 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
796#ifdef VBOX_ENABLE_64_BITS_GUESTS
797 break;
798#else
799 AssertFailed();
800 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
801#endif
802
803 default: /* shut up gcc */
804 AssertFailed();
805 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
806 }
807 }
808 pVMCB->guest.u64CR4 = val;
809 }
810
811 /* Debug registers. */
812 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
813 {
814 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
815 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
816
817 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
818 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
819 pCtx->dr[7] |= 0x400; /* must be one */
820
821 pVMCB->guest.u64DR7 = pCtx->dr[7];
822 pVMCB->guest.u64DR6 = pCtx->dr[6];
823
824#ifdef DEBUG
825 /* Sync the hypervisor debug state now if any breakpoint is armed. */
826 if ( CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK|X86_DR7_GD)
827 && !CPUMIsHyperDebugStateActive(pVCpu)
828 && !DBGFIsStepping(pVCpu))
829 {
830 /* Save the host and load the hypervisor debug state. */
831 int rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
832 AssertRC(rc);
833
834 /* DRx intercepts remain enabled. */
835
836 /* Override dr6 & dr7 with the hypervisor values. */
837 pVMCB->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
838 pVMCB->guest.u64DR6 = CPUMGetHyperDR6(pVCpu);
839 }
840 else
841#endif
842 /* Sync the debug state now if any breakpoint is armed. */
843 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
844 && !CPUMIsGuestDebugStateActive(pVCpu)
845 && !DBGFIsStepping(pVCpu))
846 {
847 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
848
849 /* Disable drx move intercepts. */
850 pVMCB->ctrl.u16InterceptRdDRx = 0;
851 pVMCB->ctrl.u16InterceptWrDRx = 0;
852
853 /* Save the host and load the guest debug state. */
854 int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
855 AssertRC(rc);
856 }
857 }
858
859 /* EIP, ESP and EFLAGS */
860 pVMCB->guest.u64RIP = pCtx->rip;
861 pVMCB->guest.u64RSP = pCtx->rsp;
862 pVMCB->guest.u64RFlags = pCtx->eflags.u32;
863
864 /* Set CPL */
865 pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
866
867 /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
868 pVMCB->guest.u64RAX = pCtx->rax;
869
870 /* vmrun will fail without MSR_K6_EFER_SVME. */
871 pVMCB->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
872
873 /* 64 bits guest mode? */
874 if (CPUMIsGuestInLongModeEx(pCtx))
875 {
876#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
877 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
878#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
879 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
880#else
881# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
882 if (!pVM->hwaccm.s.fAllow64BitGuests)
883 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
884# endif
885 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun64;
886#endif
887 /* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
888 pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
889 pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
890 }
891 else
892 {
893 /* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
894 pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
895
896 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun;
897 }
898
899 /* TSC offset. */
900 if (TMCpuTickCanUseRealTSC(pVCpu, &pVMCB->ctrl.u64TSCOffset))
901 {
902 uint64_t u64CurTSC = ASMReadTSC();
903 if (u64CurTSC + pVMCB->ctrl.u64TSCOffset >= TMCpuTickGetLastSeen(pVCpu))
904 {
905 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
906 pVMCB->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
907 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
908 }
909 else
910 {
911 /* Fall back to rdtsc emulation as we would otherwise pass decreasing tsc values to the guest. */
912 LogFlow(("TSC %RX64 offset %RX64 time=%RX64 last=%RX64 (diff=%RX64, virt_tsc=%RX64)\n", u64CurTSC, pVMCB->ctrl.u64TSCOffset, u64CurTSC + pVMCB->ctrl.u64TSCOffset, TMCpuTickGetLastSeen(pVCpu), TMCpuTickGetLastSeen(pVCpu) - u64CurTSC - pVMCB->ctrl.u64TSCOffset, TMCpuTickGet(pVCpu)));
913 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
914 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
915 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow);
916 }
917 }
918 else
919 {
920 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
921 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
922 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
923 }
924
925 /* Sync the various msrs for 64 bits mode. */
926 pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
927 pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
928 pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
929 pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
930 pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
931
932#ifdef DEBUG
933 /* Intercept X86_XCPT_DB if stepping is enabled */
934 if ( DBGFIsStepping(pVCpu)
935 || CPUMIsHyperDebugStateActive(pVCpu))
936 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_DB);
937 else
938 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
939#endif
940
941 /* Done. */
942 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
943
944 return VINF_SUCCESS;
945}
946
947
948/**
949 * Runs guest code in an AMD-V VM.
950 *
951 * @returns VBox status code.
952 * @param pVM The VM to operate on.
953 * @param pVCpu The VM CPU to operate on.
954 * @param pCtx Guest context
955 */
956VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
957{
958 int rc = VINF_SUCCESS;
959 uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
960 SVM_VMCB *pVMCB;
961 bool fSyncTPR = false;
962 unsigned cResume = 0;
963 uint8_t u8LastTPR;
964 PHWACCM_CPUINFO pCpu = 0;
965 RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
966#ifdef VBOX_STRICT
967 RTCPUID idCpuCheck;
968#endif
969#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
970 uint64_t u64LastTime = RTTimeMilliTS();
971#endif
972
973 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
974
975 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
976 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
977
978 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
979 */
980ResumeExecution:
981 Assert(!HWACCMR0SuspendPending());
982
983 /* Safety precaution; looping for too long here can have a very bad effect on the host */
984 if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
985 {
986 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
987 rc = VINF_EM_RAW_INTERRUPT;
988 goto end;
989 }
990
991 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
992 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
993 {
994 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
995 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
996 {
997 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
998 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
999 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
1000 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
1001 */
1002 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1003 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
1004 pVMCB->ctrl.u64IntShadow = 0;
1005 }
1006 }
1007 else
1008 {
1009 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
1010 pVMCB->ctrl.u64IntShadow = 0;
1011 }
1012
1013#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
1014 if (RT_UNLIKELY(cResume & 0xf) == 0)
1015 {
1016 uint64_t u64CurTime = RTTimeMilliTS();
1017
1018 if (RT_UNLIKELY(u64CurTime > u64LastTime))
1019 {
1020 u64LastTime = u64CurTime;
1021 TMTimerPollVoid(pVM, pVCpu);
1022 }
1023 }
1024#endif
1025
1026 /* Check for pending actions that force us to go back to ring 3. */
1027 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK | VM_FF_REQUEST | VM_FF_PGM_POOL_FLUSH_PENDING)
1028 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_REQUEST))
1029 {
1030 /* Check if a sync operation is pending. */
1031 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1032 {
1033 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1034 AssertRC(rc);
1035 if (rc != VINF_SUCCESS)
1036 {
1037 Log(("Pending pool sync is forcing us back to ring 3; rc=%d\n", rc));
1038 goto end;
1039 }
1040 }
1041
1042#ifdef DEBUG
1043 /* Intercept X86_XCPT_DB if stepping is enabled */
1044 if (!DBGFIsStepping(pVCpu))
1045#endif
1046 {
1047 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
1048 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
1049 {
1050 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
1051 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
1052 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1053 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
1054 goto end;
1055 }
1056 }
1057
1058 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1059 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
1060 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1061 {
1062 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1063 rc = VINF_EM_PENDING_REQUEST;
1064 goto end;
1065 }
1066
1067 /* Check if a pgm pool flush is in progress. */
1068 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
1069 {
1070 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1071 rc = VINF_PGM_POOL_FLUSH_PENDING;
1072 goto end;
1073 }
1074 }
1075
1076#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1077 /*
1078 * Exit to ring-3 preemption/work is pending.
1079 *
1080 * Interrupts are disabled before the call to make sure we don't miss any interrupt
1081 * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
1082 * further down, but SVMR0CheckPendingInterrupt makes that impossible.)
1083 *
1084 * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
1085 * shootdowns rely on this.
1086 */
1087 uOldEFlags = ASMIntDisableFlags();
1088 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
1089 {
1090 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
1091 rc = VINF_EM_RAW_INTERRUPT;
1092 goto end;
1093 }
1094 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1095#endif
1096
1097 /* When external interrupts are pending, we should exit the VM when IF is set. */
1098 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
1099 rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
1100 if (RT_FAILURE(rc))
1101 {
1102 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1103 goto end;
1104 }
1105
1106 /* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
1107 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! (no longer true)
1108 * @todo query and update the TPR only when it could have been changed (mmio access)
1109 */
1110 if (pVM->hwaccm.s.fHasIoApic)
1111 {
1112 bool fPending;
1113
1114 /* TPR caching in CR8 */
1115 int rc2 = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
1116 AssertRC(rc2);
1117
1118 if (pVM->hwaccm.s.fTPRPatchingActive)
1119 {
1120 /* Our patch code uses LSTAR for TPR caching. */
1121 pCtx->msrLSTAR = u8LastTPR;
1122
1123 if (fPending)
1124 {
1125 /* A TPR change could activate a pending interrupt, so catch lstar writes. */
1126 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, false);
1127 }
1128 else
1129 /* No interrupts are pending, so we don't need to be explicitely notified.
1130 * There are enough world switches for detecting pending interrupts.
1131 */
1132 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
1133 }
1134 else
1135 {
1136 pVMCB->ctrl.IntCtrl.n.u8VTPR = (u8LastTPR >> 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1137
1138 if (fPending)
1139 {
1140 /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
1141 pVMCB->ctrl.u16InterceptWrCRx |= RT_BIT(8);
1142 }
1143 else
1144 /* No interrupts are pending, so we don't need to be explicitely notified.
1145 * There are enough world switches for detecting pending interrupts.
1146 */
1147 pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1148 }
1149 fSyncTPR = !fPending;
1150 }
1151
1152 /* All done! Let's start VM execution. */
1153 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, x);
1154
1155 /* Enable nested paging if necessary (disabled each time after #VMEXIT). */
1156 pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
1157
1158#ifdef LOG_ENABLED
1159 pCpu = HWACCMR0GetCurrentCpu();
1160 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1161 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1162 {
1163 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
1164 LogFlow(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
1165 else
1166 LogFlow(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1167 }
1168 if (pCpu->fFlushTLB)
1169 LogFlow(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
1170#endif
1171
1172 /*
1173 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1174 * (until the actual world switch)
1175 */
1176#ifdef VBOX_STRICT
1177 idCpuCheck = RTMpCpuId();
1178#endif
1179 VMMR0LogFlushDisable(pVCpu);
1180
1181 /* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */
1182 rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
1183 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1184 {
1185 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1186 VMMR0LogFlushEnable(pVCpu);
1187 goto end;
1188 }
1189
1190#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1191 /* Disable interrupts to make sure a poke will interrupt execution.
1192 * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
1193 */
1194 uOldEFlags = ASMIntDisableFlags();
1195 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1196#endif
1197
1198 pCpu = HWACCMR0GetCurrentCpu();
1199 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1200 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1201 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1202 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1203 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1204 {
1205 /* Force a TLB flush on VM entry. */
1206 pVCpu->hwaccm.s.fForceTLBFlush = true;
1207 }
1208 else
1209 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1210
1211 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1212
1213 /** Set TLB flush state as checked until we return from the world switch. */
1214 ASMAtomicWriteU8(&pVCpu->hwaccm.s.fCheckedTLBFlush, true);
1215
1216 /* Check for tlb shootdown flushes. */
1217 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1218 pVCpu->hwaccm.s.fForceTLBFlush = true;
1219
1220 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1221 if ( pVCpu->hwaccm.s.fForceTLBFlush
1222 && !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
1223 {
1224 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1225 || pCpu->fFlushTLB)
1226 {
1227 pCpu->fFlushTLB = false;
1228 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1229 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
1230 pCpu->cTLBFlushes++;
1231 }
1232 else
1233 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1234
1235 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1236 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1237 }
1238 else
1239 {
1240 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1241
1242 /* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
1243 if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)
1244 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1245
1246 Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB || pVCpu->hwaccm.s.fForceTLBFlush);
1247 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
1248
1249 if ( !pVM->hwaccm.s.svm.fAlwaysFlushTLB
1250 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1251 {
1252 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1253 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1254 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1255 SVMR0InvlpgA(pVCpu->hwaccm.s.TlbShootdown.aPages[i], pVMCB->ctrl.TLBCtrl.n.u32ASID);
1256 }
1257 }
1258 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1259 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1260
1261 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1262 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1263 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1264 pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
1265
1266#ifdef VBOX_WITH_STATISTICS
1267 if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
1268 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1269 else
1270 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1271#endif
1272
1273 /* In case we execute a goto ResumeExecution later on. */
1274 pVCpu->hwaccm.s.fResumeVM = true;
1275 pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
1276
1277 Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
1278 Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
1279 Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
1280 Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVCpu->hwaccm.s.svm.pMSRBitmapPhys);
1281 Assert(pVMCB->ctrl.u64LBRVirt == 0);
1282
1283#ifdef VBOX_STRICT
1284 Assert(idCpuCheck == RTMpCpuId());
1285#endif
1286 TMNotifyStartOfExecution(pVCpu);
1287#ifdef VBOX_WITH_KERNEL_USING_XMM
1288 hwaccmR0SVMRunWrapXMM(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu, pVCpu->hwaccm.s.svm.pfnVMRun);
1289#else
1290 pVCpu->hwaccm.s.svm.pfnVMRun(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);
1291#endif
1292 ASMAtomicWriteU8(&pVCpu->hwaccm.s.fCheckedTLBFlush, false);
1293 ASMAtomicIncU32(&pVCpu->hwaccm.s.cWorldSwitchExit);
1294 /* Possibly the last TSC value seen by the guest (too high) (only when we're in tsc offset mode). */
1295 if (!(pVMCB->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
1296 TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVMCB->ctrl.u64TSCOffset - 0x400 /* guestimate of world switch overhead in clock ticks */);
1297 TMNotifyEndOfExecution(pVCpu);
1298 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
1299 ASMSetFlags(uOldEFlags);
1300#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1301 uOldEFlags = ~(RTCCUINTREG)0;
1302#endif
1303 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, x);
1304
1305 /*
1306 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1307 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1308 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1309 */
1310
1311 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, x);
1312
1313 /* Reason for the VM exit */
1314 exitCode = pVMCB->ctrl.u64ExitCode;
1315
1316 if (RT_UNLIKELY(exitCode == (uint64_t)SVM_EXIT_INVALID)) /* Invalid guest state. */
1317 {
1318 HWACCMDumpRegs(pVM, pVCpu, pCtx);
1319#ifdef DEBUG
1320 Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1321 Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1322 Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1323 Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1324 Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1325 Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1326 Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1327 Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1328 Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1329 Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
1330
1331 Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1332 Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1333 Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1334 Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1335
1336 Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1337 Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1338 Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1339 Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1340 Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1341 Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1342 Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1343 Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1344 Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1345 Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1346
1347 Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
1348 Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
1349 Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
1350 Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
1351 Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1352 Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1353 Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1354 Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1355 Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1356 Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1357 Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
1358 Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1359 Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1360 Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1361 Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1362 Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1363 Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1364
1365 Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1366 Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
1367
1368 Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1369 Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1370 Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1371 Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
1372 Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1373 Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1374 Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1375 Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
1376 Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1377 Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1378 Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1379 Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
1380 Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1381 Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1382 Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1383 Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
1384 Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1385 Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1386 Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1387 Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
1388
1389 Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1390 Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
1391
1392 Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1393 Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1394 Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1395 Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
1396
1397 Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1398 Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
1399
1400 Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1401 Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1402 Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1403 Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
1404
1405 Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1406 Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
1407 Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
1408 Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
1409 Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
1410 Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
1411 Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
1412
1413 Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
1414 Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
1415 Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
1416 Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
1417
1418 Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
1419 Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
1420 Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
1421
1422 Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
1423 Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
1424 Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
1425 Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
1426 Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
1427 Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
1428 Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
1429 Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
1430 Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
1431 Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
1432 Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
1433 Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
1434
1435#endif
1436 rc = VERR_SVM_UNABLE_TO_START_VM;
1437 VMMR0LogFlushEnable(pVCpu);
1438 goto end;
1439 }
1440
1441 /* Let's first sync back eip, esp, and eflags. */
1442 pCtx->rip = pVMCB->guest.u64RIP;
1443 pCtx->rsp = pVMCB->guest.u64RSP;
1444 pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1445 /* eax is saved/restore across the vmrun instruction */
1446 pCtx->rax = pVMCB->guest.u64RAX;
1447
1448 /* Save all the MSRs that can be changed by the guest without causing a world switch. (fs & gs base are saved with SVM_READ_SELREG) */
1449 pCtx->msrSTAR = pVMCB->guest.u64STAR; /* legacy syscall eip, cs & ss */
1450 pCtx->msrLSTAR = pVMCB->guest.u64LSTAR; /* 64 bits mode syscall rip */
1451 pCtx->msrCSTAR = pVMCB->guest.u64CSTAR; /* compatibility mode syscall rip */
1452 pCtx->msrSFMASK = pVMCB->guest.u64SFMASK; /* syscall flag mask */
1453 pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1454 pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1455 pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1456 pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1457
1458 /* Can be updated behind our back in the nested paging case. */
1459 pCtx->cr2 = pVMCB->guest.u64CR2;
1460
1461 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1462 SVM_READ_SELREG(SS, ss);
1463 SVM_READ_SELREG(CS, cs);
1464 SVM_READ_SELREG(DS, ds);
1465 SVM_READ_SELREG(ES, es);
1466 SVM_READ_SELREG(FS, fs);
1467 SVM_READ_SELREG(GS, gs);
1468
1469 /* Correct the hidden CS granularity flag. Haven't seen it being wrong in
1470 any other register (yet). */
1471 if ( !pCtx->csHid.Attr.n.u1Granularity
1472 && pCtx->csHid.Attr.n.u1Present
1473 && pCtx->csHid.u32Limit > UINT32_C(0xfffff))
1474 {
1475 Assert((pCtx->csHid.u32Limit & 0xfff) == 0xfff);
1476 pCtx->csHid.Attr.n.u1Granularity = 1;
1477 }
1478#define SVM_ASSERT_SEL_GRANULARITY(reg) \
1479 AssertMsg( !pCtx->reg##Hid.Attr.n.u1Present \
1480 || ( pCtx->reg##Hid.Attr.n.u1Granularity \
1481 ? (pCtx->reg##Hid.u32Limit & 0xfff) == 0xfff \
1482 : pCtx->reg##Hid.u32Limit <= 0xfffff), \
1483 ("%#x %#x %#llx\n", pCtx->reg##Hid.u32Limit, pCtx->reg##Hid.Attr.u, pCtx->reg##Hid.u64Base))
1484 SVM_ASSERT_SEL_GRANULARITY(ss);
1485 SVM_ASSERT_SEL_GRANULARITY(cs);
1486 SVM_ASSERT_SEL_GRANULARITY(ds);
1487 SVM_ASSERT_SEL_GRANULARITY(es);
1488 SVM_ASSERT_SEL_GRANULARITY(fs);
1489 SVM_ASSERT_SEL_GRANULARITY(gs);
1490#undef SVM_ASSERT_SEL_GRANULARITY
1491
1492 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1493 SVM_READ_SELREG(LDTR, ldtr);
1494 SVM_READ_SELREG(TR, tr);
1495
1496 pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1497 pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1498
1499 pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1500 pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1501
1502 /* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1503 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1504 if ( pVM->hwaccm.s.fNestedPaging
1505 && pCtx->cr3 != pVMCB->guest.u64CR3)
1506 {
1507 CPUMSetGuestCR3(pVCpu, pVMCB->guest.u64CR3);
1508 PGMUpdateCR3(pVCpu, pVMCB->guest.u64CR3);
1509 }
1510
1511 /* Note! NOW IT'S SAFE FOR LOGGING! */
1512 VMMR0LogFlushEnable(pVCpu);
1513
1514 /* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1515 if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1516 {
1517 Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
1518 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1519 }
1520 else
1521 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1522
1523 Log2(("exitCode = %x\n", exitCode));
1524
1525 /* Sync back DR6 as it could have been changed by hitting breakpoints. */
1526 pCtx->dr[6] = pVMCB->guest.u64DR6;
1527 /* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1528 pCtx->dr[7] = pVMCB->guest.u64DR7;
1529
1530 /* Check if an injected event was interrupted prematurely. */
1531 pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1532 if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1533 && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1534 {
1535 Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
1536
1537#ifdef LOG_ENABLED
1538 SVM_EVENT Event;
1539 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
1540
1541 if ( exitCode == SVM_EXIT_EXCEPTION_E
1542 && Event.n.u8Vector == 0xE)
1543 {
1544 Log(("Double fault!\n"));
1545 }
1546#endif
1547
1548 pVCpu->hwaccm.s.Event.fPending = true;
1549 /* Error code present? (redundant) */
1550 if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1551 pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1552 else
1553 pVCpu->hwaccm.s.Event.errCode = 0;
1554 }
1555#ifdef VBOX_WITH_STATISTICS
1556 if (exitCode == SVM_EXIT_NPF)
1557 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
1558 else
1559 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1560#endif
1561
1562 /* Sync back the TPR if it was changed. */
1563 if (fSyncTPR)
1564 {
1565 if (pVM->hwaccm.s.fTPRPatchingActive)
1566 {
1567 if ((pCtx->msrLSTAR & 0xff) != u8LastTPR)
1568 {
1569 /* Our patch code uses LSTAR for TPR caching. */
1570 rc = PDMApicSetTPR(pVCpu, pCtx->msrLSTAR & 0xff);
1571 AssertRC(rc);
1572 }
1573 }
1574 else
1575 {
1576 if ((u8LastTPR >> 4) != pVMCB->ctrl.IntCtrl.n.u8VTPR)
1577 {
1578 rc = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1579 AssertRC(rc);
1580 }
1581 }
1582 }
1583
1584 /* Deal with the reason of the VM-exit. */
1585 switch (exitCode)
1586 {
1587 case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1588 case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1589 case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1590 case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1591 case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1592 case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1593 case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1594 case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1595 {
1596 /* Pending trap. */
1597 SVM_EVENT Event;
1598 uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1599
1600 Log2(("Hardware/software interrupt %d\n", vector));
1601 switch (vector)
1602 {
1603 case X86_XCPT_DB:
1604 {
1605 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
1606
1607 /* Note that we don't support guest and host-initiated debugging at the same time. */
1608 Assert(DBGFIsStepping(pVCpu) || CPUMIsHyperDebugStateActive(pVCpu));
1609
1610 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1611 if (rc == VINF_EM_RAW_GUEST_TRAP)
1612 {
1613 Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
1614
1615 /* Reinject the exception. */
1616 Event.au64[0] = 0;
1617 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1618 Event.n.u1Valid = 1;
1619 Event.n.u8Vector = X86_XCPT_DB;
1620
1621 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1622
1623 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1624 goto ResumeExecution;
1625 }
1626 /* Return to ring 3 to deal with the debug exit code. */
1627 Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
1628 break;
1629 }
1630
1631 case X86_XCPT_NM:
1632 {
1633 Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
1634
1635 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1636 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1637 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
1638 if (rc == VINF_SUCCESS)
1639 {
1640 Assert(CPUMIsGuestFPUStateActive(pVCpu));
1641 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
1642
1643 /* Continue execution. */
1644 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1645 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1646
1647 goto ResumeExecution;
1648 }
1649
1650 Log(("Forward #NM fault to the guest\n"));
1651 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
1652
1653 Event.au64[0] = 0;
1654 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1655 Event.n.u1Valid = 1;
1656 Event.n.u8Vector = X86_XCPT_NM;
1657
1658 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1659 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1660 goto ResumeExecution;
1661 }
1662
1663 case X86_XCPT_PF: /* Page fault */
1664 {
1665 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1666 RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1667
1668#ifdef DEBUG
1669 if (pVM->hwaccm.s.fNestedPaging)
1670 { /* A genuine pagefault.
1671 * Forward the trap to the guest by injecting the exception and resuming execution.
1672 */
1673 Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1674 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1675
1676 /* Now we must update CR2. */
1677 pCtx->cr2 = uFaultAddress;
1678
1679 Event.au64[0] = 0;
1680 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1681 Event.n.u1Valid = 1;
1682 Event.n.u8Vector = X86_XCPT_PF;
1683 Event.n.u1ErrorCodeValid = 1;
1684 Event.n.u32ErrorCode = errCode;
1685
1686 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1687
1688 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1689 goto ResumeExecution;
1690 }
1691#endif
1692 Assert(!pVM->hwaccm.s.fNestedPaging);
1693
1694#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1695 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1696 if ( pVM->hwaccm.s.fTRPPatchingAllowed
1697 && (uFaultAddress & 0xfff) == 0x080
1698 && !(errCode & X86_TRAP_PF_P) /* not present */
1699 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1700 && !CPUMIsGuestInLongModeEx(pCtx)
1701 && pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1702 {
1703 RTGCPHYS GCPhysApicBase, GCPhys;
1704 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1705 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1706
1707 rc = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL, &GCPhys);
1708 if ( rc == VINF_SUCCESS
1709 && GCPhys == GCPhysApicBase)
1710 {
1711 /* Only attempt to patch the instruction once. */
1712 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1713 if (!pPatch)
1714 {
1715 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1716 break;
1717 }
1718 }
1719 }
1720#endif
1721
1722 Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1723 /* Exit qualification contains the linear address of the page fault. */
1724 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1725 TRPMSetErrorCode(pVCpu, errCode);
1726 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1727
1728 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1729 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1730 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1731 if (rc == VINF_SUCCESS)
1732 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1733 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1734 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1735
1736 TRPMResetTrap(pVCpu);
1737 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1738 goto ResumeExecution;
1739 }
1740 else
1741 if (rc == VINF_EM_RAW_GUEST_TRAP)
1742 { /* A genuine pagefault.
1743 * Forward the trap to the guest by injecting the exception and resuming execution.
1744 */
1745 Log2(("Forward page fault to the guest\n"));
1746 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1747 /* The error code might have been changed. */
1748 errCode = TRPMGetErrorCode(pVCpu);
1749
1750 TRPMResetTrap(pVCpu);
1751
1752 /* Now we must update CR2. */
1753 pCtx->cr2 = uFaultAddress;
1754
1755 Event.au64[0] = 0;
1756 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1757 Event.n.u1Valid = 1;
1758 Event.n.u8Vector = X86_XCPT_PF;
1759 Event.n.u1ErrorCodeValid = 1;
1760 Event.n.u32ErrorCode = errCode;
1761
1762 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1763
1764 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1765 goto ResumeExecution;
1766 }
1767#ifdef VBOX_STRICT
1768 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
1769 LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1770#endif
1771 /* Need to go back to the recompiler to emulate the instruction. */
1772 TRPMResetTrap(pVCpu);
1773 break;
1774 }
1775
1776 case X86_XCPT_MF: /* Floating point exception. */
1777 {
1778 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
1779 if (!(pCtx->cr0 & X86_CR0_NE))
1780 {
1781 /* old style FPU error reporting needs some extra work. */
1782 /** @todo don't fall back to the recompiler, but do it manually. */
1783 rc = VINF_EM_RAW_EMULATE_INSTR;
1784 break;
1785 }
1786 Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
1787
1788 Event.au64[0] = 0;
1789 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1790 Event.n.u1Valid = 1;
1791 Event.n.u8Vector = X86_XCPT_MF;
1792
1793 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1794
1795 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1796 goto ResumeExecution;
1797 }
1798
1799#ifdef VBOX_STRICT
1800 case X86_XCPT_BP: /* Breakpoint. */
1801 case X86_XCPT_GP: /* General protection failure exception.*/
1802 case X86_XCPT_UD: /* Unknown opcode exception. */
1803 case X86_XCPT_DE: /* Divide error. */
1804 case X86_XCPT_SS: /* Stack segment exception. */
1805 case X86_XCPT_NP: /* Segment not present exception. */
1806 {
1807 Event.au64[0] = 0;
1808 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1809 Event.n.u1Valid = 1;
1810 Event.n.u8Vector = vector;
1811
1812 switch(vector)
1813 {
1814 case X86_XCPT_GP:
1815 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
1816 Event.n.u1ErrorCodeValid = 1;
1817 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1818 break;
1819 case X86_XCPT_BP:
1820 break;
1821 case X86_XCPT_DE:
1822 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
1823 break;
1824 case X86_XCPT_UD:
1825 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
1826 break;
1827 case X86_XCPT_SS:
1828 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
1829 Event.n.u1ErrorCodeValid = 1;
1830 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1831 break;
1832 case X86_XCPT_NP:
1833 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
1834 Event.n.u1ErrorCodeValid = 1;
1835 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1836 break;
1837 }
1838 Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->esi));
1839 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1840
1841 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1842 goto ResumeExecution;
1843 }
1844#endif
1845 default:
1846 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1847 rc = VERR_EM_INTERNAL_ERROR;
1848 break;
1849
1850 } /* switch (vector) */
1851 break;
1852 }
1853
1854 case SVM_EXIT_NPF:
1855 {
1856 /* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1857 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1858 RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1859 PGMMODE enmShwPagingMode;
1860
1861 Assert(pVM->hwaccm.s.fNestedPaging);
1862 LogFlow(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1863
1864#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1865 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1866 if ( pVM->hwaccm.s.fTRPPatchingAllowed
1867 && (uFaultAddress & 0xfff) == 0x080
1868 && !(errCode & X86_TRAP_PF_P) /* not present */
1869 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1870 && !CPUMIsGuestInLongModeEx(pCtx)
1871 && pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1872 {
1873 RTGCPHYS GCPhysApicBase;
1874 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1875 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1876
1877 if (uFaultAddress == GCPhysApicBase + 0x80)
1878 {
1879 /* Only attempt to patch the instruction once. */
1880 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1881 if (!pPatch)
1882 {
1883 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1884 break;
1885 }
1886 }
1887 }
1888#endif
1889
1890 /* Exit qualification contains the linear address of the page fault. */
1891 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1892 TRPMSetErrorCode(pVCpu, errCode);
1893 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1894
1895 /* Handle the pagefault trap for the nested shadow table. */
1896#if HC_ARCH_BITS == 32
1897 if (CPUMIsGuestInLongModeEx(pCtx))
1898 enmShwPagingMode = PGMMODE_AMD64_NX;
1899 else
1900#endif
1901 enmShwPagingMode = PGMGetHostMode(pVM);
1902
1903 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1904 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1905 if (rc == VINF_SUCCESS)
1906 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1907 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1908 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1909
1910 TRPMResetTrap(pVCpu);
1911
1912 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1913 goto ResumeExecution;
1914 }
1915
1916#ifdef VBOX_STRICT
1917 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1918 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1919#endif
1920 /* Need to go back to the recompiler to emulate the instruction. */
1921 TRPMResetTrap(pVCpu);
1922 break;
1923 }
1924
1925 case SVM_EXIT_VINTR:
1926 /* A virtual interrupt is about to be delivered, which means IF=1. */
1927 Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1928 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1929 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1930 goto ResumeExecution;
1931
1932 case SVM_EXIT_FERR_FREEZE:
1933 case SVM_EXIT_INTR:
1934 case SVM_EXIT_NMI:
1935 case SVM_EXIT_SMI:
1936 case SVM_EXIT_INIT:
1937 /* External interrupt; leave to allow it to be dispatched again. */
1938 rc = VINF_EM_RAW_INTERRUPT;
1939 break;
1940
1941 case SVM_EXIT_WBINVD:
1942 case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1943 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
1944 /* Skip instruction and continue directly. */
1945 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1946 /* Continue execution.*/
1947 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1948 goto ResumeExecution;
1949
1950 case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1951 {
1952 Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
1953 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
1954 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1955 if (rc == VINF_SUCCESS)
1956 {
1957 /* Update EIP and continue execution. */
1958 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1959 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1960 goto ResumeExecution;
1961 }
1962 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
1963 rc = VINF_EM_RAW_EMULATE_INSTR;
1964 break;
1965 }
1966
1967 case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1968 {
1969 Log2(("SVM: Rdtsc\n"));
1970 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1971 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1972 if (rc == VINF_SUCCESS)
1973 {
1974 /* Update EIP and continue execution. */
1975 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1976 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1977 goto ResumeExecution;
1978 }
1979 rc = VINF_EM_RAW_EMULATE_INSTR;
1980 break;
1981 }
1982
1983 case SVM_EXIT_RDPMC: /* Guest software attempted to execute RDPMC. */
1984 {
1985 Log2(("SVM: Rdpmc %x\n", pCtx->ecx));
1986 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
1987 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1988 if (rc == VINF_SUCCESS)
1989 {
1990 /* Update EIP and continue execution. */
1991 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1992 goto ResumeExecution;
1993 }
1994 rc = VINF_EM_RAW_EMULATE_INSTR;
1995 break;
1996 }
1997
1998 case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
1999 {
2000 Log2(("SVM: Rdtscp\n"));
2001 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
2002 rc = EMInterpretRdtscp(pVM, pVCpu, pCtx);
2003 if (rc == VINF_SUCCESS)
2004 {
2005 /* Update EIP and continue execution. */
2006 pCtx->rip += 3; /* Note! hardcoded opcode size! */
2007 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2008 goto ResumeExecution;
2009 }
2010 AssertMsgFailed(("EMU: rdtscp failed with %Rrc\n", rc));
2011 rc = VINF_EM_RAW_EMULATE_INSTR;
2012 break;
2013 }
2014
2015 case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
2016 {
2017 Log2(("SVM: invlpg\n"));
2018 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
2019
2020 Assert(!pVM->hwaccm.s.fNestedPaging);
2021
2022 /* Truly a pita. Why can't SVM give the same information as VT-x? */
2023 rc = svmR0InterpretInvpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
2024 if (rc == VINF_SUCCESS)
2025 {
2026 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageInvlpg);
2027 goto ResumeExecution; /* eip already updated */
2028 }
2029 break;
2030 }
2031
2032 case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
2033 case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
2034 case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
2035 case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
2036 {
2037 uint32_t cbSize;
2038
2039 Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
2040 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[exitCode - SVM_EXIT_WRITE_CR0]);
2041 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2042
2043 switch (exitCode - SVM_EXIT_WRITE_CR0)
2044 {
2045 case 0:
2046 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2047 break;
2048 case 2:
2049 break;
2050 case 3:
2051 Assert(!pVM->hwaccm.s.fNestedPaging);
2052 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
2053 break;
2054 case 4:
2055 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
2056 break;
2057 case 8:
2058 break;
2059 default:
2060 AssertFailed();
2061 }
2062 if (rc == VINF_SUCCESS)
2063 {
2064 /* EIP has been updated already. */
2065
2066 /* Only resume if successful. */
2067 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2068 goto ResumeExecution;
2069 }
2070 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2071 break;
2072 }
2073
2074 case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
2075 case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
2076 case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
2077 case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
2078 {
2079 uint32_t cbSize;
2080
2081 Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
2082 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[exitCode - SVM_EXIT_READ_CR0]);
2083 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2084 if (rc == VINF_SUCCESS)
2085 {
2086 /* EIP has been updated already. */
2087
2088 /* Only resume if successful. */
2089 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2090 goto ResumeExecution;
2091 }
2092 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2093 break;
2094 }
2095
2096 case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
2097 case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
2098 case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
2099 case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
2100 {
2101 uint32_t cbSize;
2102
2103 Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
2104 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
2105
2106 if ( !DBGFIsStepping(pVCpu)
2107 && !CPUMIsHyperDebugStateActive(pVCpu))
2108 {
2109 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2110
2111 /* Disable drx move intercepts. */
2112 pVMCB->ctrl.u16InterceptRdDRx = 0;
2113 pVMCB->ctrl.u16InterceptWrDRx = 0;
2114
2115 /* Save the host and load the guest debug state. */
2116 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2117 AssertRC(rc);
2118
2119 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2120 goto ResumeExecution;
2121 }
2122
2123 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2124 if (rc == VINF_SUCCESS)
2125 {
2126 /* EIP has been updated already. */
2127 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2128
2129 /* Only resume if successful. */
2130 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2131 goto ResumeExecution;
2132 }
2133 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2134 break;
2135 }
2136
2137 case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
2138 case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
2139 case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
2140 case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
2141 {
2142 uint32_t cbSize;
2143
2144 Log2(("SVM: %RGv mov x, dr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
2145 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2146
2147 if (!DBGFIsStepping(pVCpu))
2148 {
2149 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2150
2151 /* Disable drx move intercepts. */
2152 pVMCB->ctrl.u16InterceptRdDRx = 0;
2153 pVMCB->ctrl.u16InterceptWrDRx = 0;
2154
2155 /* Save the host and load the guest debug state. */
2156 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2157 AssertRC(rc);
2158
2159 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2160 goto ResumeExecution;
2161 }
2162
2163 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2164 if (rc == VINF_SUCCESS)
2165 {
2166 /* EIP has been updated already. */
2167
2168 /* Only resume if successful. */
2169 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2170 goto ResumeExecution;
2171 }
2172 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2173 break;
2174 }
2175
2176 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2177 case SVM_EXIT_IOIO: /* I/O instruction. */
2178 {
2179 SVM_IOIO_EXIT IoExitInfo;
2180 uint32_t uIOSize, uAndVal;
2181
2182 IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
2183
2184 /** @todo could use a lookup table here */
2185 if (IoExitInfo.n.u1OP8)
2186 {
2187 uIOSize = 1;
2188 uAndVal = 0xff;
2189 }
2190 else
2191 if (IoExitInfo.n.u1OP16)
2192 {
2193 uIOSize = 2;
2194 uAndVal = 0xffff;
2195 }
2196 else
2197 if (IoExitInfo.n.u1OP32)
2198 {
2199 uIOSize = 4;
2200 uAndVal = 0xffffffff;
2201 }
2202 else
2203 {
2204 AssertFailed(); /* should be fatal. */
2205 rc = VINF_EM_RAW_EMULATE_INSTR;
2206 break;
2207 }
2208
2209 if (IoExitInfo.n.u1STR)
2210 {
2211 /* ins/outs */
2212 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2213
2214 /* Disassemble manually to deal with segment prefixes. */
2215 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
2216 if (rc == VINF_SUCCESS)
2217 {
2218 if (IoExitInfo.n.u1Type == 0)
2219 {
2220 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2221 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
2222 rc = VBOXSTRICTRC_TODO(IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize));
2223 }
2224 else
2225 {
2226 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2227 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
2228 rc = VBOXSTRICTRC_TODO(IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize));
2229 }
2230 }
2231 else
2232 rc = VINF_EM_RAW_EMULATE_INSTR;
2233 }
2234 else
2235 {
2236 /* normal in/out */
2237 Assert(!IoExitInfo.n.u1REP);
2238
2239 if (IoExitInfo.n.u1Type == 0)
2240 {
2241 Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2242 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
2243 rc = VBOXSTRICTRC_TODO(IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2244 if (rc == VINF_IOM_HC_IOPORT_WRITE)
2245 HWACCMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2246 }
2247 else
2248 {
2249 uint32_t u32Val = 0;
2250
2251 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
2252 rc = VBOXSTRICTRC_TODO(IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize));
2253 if (IOM_SUCCESS(rc))
2254 {
2255 /* Write back to the EAX register. */
2256 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2257 Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
2258 }
2259 else
2260 if (rc == VINF_IOM_HC_IOPORT_READ)
2261 HWACCMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2262 }
2263 }
2264 /*
2265 * Handled the I/O return codes.
2266 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2267 */
2268 if (IOM_SUCCESS(rc))
2269 {
2270 /* Update EIP and continue execution. */
2271 pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
2272 if (RT_LIKELY(rc == VINF_SUCCESS))
2273 {
2274 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2275 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2276 {
2277 /* IO operation lookup arrays. */
2278 static uint32_t const aIOSize[4] = {1, 2, 0, 4};
2279
2280 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
2281 for (unsigned i=0;i<4;i++)
2282 {
2283 unsigned uBPLen = aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2284
2285 if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
2286 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
2287 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2288 {
2289 SVM_EVENT Event;
2290
2291 Assert(CPUMIsGuestDebugStateActive(pVCpu));
2292
2293 /* Clear all breakpoint status flags and set the one we just hit. */
2294 pCtx->dr[6] &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
2295 pCtx->dr[6] |= (uint64_t)RT_BIT(i);
2296
2297 /* Note: AMD64 Architecture Programmer's Manual 13.1:
2298 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2299 * the contents have been read.
2300 */
2301 pVMCB->guest.u64DR6 = pCtx->dr[6];
2302
2303 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2304 pCtx->dr[7] &= ~X86_DR7_GD;
2305
2306 /* Paranoia. */
2307 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2308 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2309 pCtx->dr[7] |= 0x400; /* must be one */
2310
2311 pVMCB->guest.u64DR7 = pCtx->dr[7];
2312
2313 /* Inject the exception. */
2314 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
2315
2316 Event.au64[0] = 0;
2317 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
2318 Event.n.u1Valid = 1;
2319 Event.n.u8Vector = X86_XCPT_DB;
2320
2321 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2322
2323 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2324 goto ResumeExecution;
2325 }
2326 }
2327 }
2328
2329 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2330 goto ResumeExecution;
2331 }
2332 Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
2333 break;
2334 }
2335
2336#ifdef VBOX_STRICT
2337 if (rc == VINF_IOM_HC_IOPORT_READ)
2338 Assert(IoExitInfo.n.u1Type != 0);
2339 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2340 Assert(IoExitInfo.n.u1Type == 0);
2341 else
2342 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
2343#endif
2344 Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2345 break;
2346 }
2347
2348 case SVM_EXIT_HLT:
2349 /** Check if external interrupts are pending; if so, don't switch back. */
2350 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2351 pCtx->rip++; /* skip hlt */
2352 if (EMShouldContinueAfterHalt(pVCpu, pCtx))
2353 goto ResumeExecution;
2354
2355 rc = VINF_EM_HALT;
2356 break;
2357
2358 case SVM_EXIT_MWAIT_UNCOND:
2359 Log2(("SVM: mwait\n"));
2360 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
2361 rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2362 if ( rc == VINF_EM_HALT
2363 || rc == VINF_SUCCESS)
2364 {
2365 /* Update EIP and continue execution. */
2366 pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2367
2368 /** Check if external interrupts are pending; if so, don't switch back. */
2369 if ( rc == VINF_SUCCESS
2370 || ( rc == VINF_EM_HALT
2371 && EMShouldContinueAfterHalt(pVCpu, pCtx))
2372 )
2373 goto ResumeExecution;
2374 }
2375 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
2376 break;
2377
2378 case SVM_EXIT_MONITOR:
2379 {
2380 Log2(("SVM: monitor\n"));
2381
2382 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMonitor);
2383 rc = EMInterpretMonitor(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2384 if (rc == VINF_SUCCESS)
2385 {
2386 /* Update EIP and continue execution. */
2387 pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2388 goto ResumeExecution;
2389 }
2390 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: monitor failed with %Rrc\n", rc));
2391 break;
2392 }
2393
2394
2395 case SVM_EXIT_VMMCALL:
2396 rc = svmR0EmulateTprVMMCall(pVM, pVCpu, pCtx);
2397 if (rc == VINF_SUCCESS)
2398 {
2399 goto ResumeExecution; /* rip already updated. */
2400 }
2401 /* no break */
2402
2403 case SVM_EXIT_RSM:
2404 case SVM_EXIT_INVLPGA:
2405 case SVM_EXIT_VMRUN:
2406 case SVM_EXIT_VMLOAD:
2407 case SVM_EXIT_VMSAVE:
2408 case SVM_EXIT_STGI:
2409 case SVM_EXIT_CLGI:
2410 case SVM_EXIT_SKINIT:
2411 {
2412 /* Unsupported instructions. */
2413 SVM_EVENT Event;
2414
2415 Event.au64[0] = 0;
2416 Event.n.u3Type = SVM_EVENT_EXCEPTION;
2417 Event.n.u1Valid = 1;
2418 Event.n.u8Vector = X86_XCPT_UD;
2419
2420 Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
2421 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2422
2423 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2424 goto ResumeExecution;
2425 }
2426
2427 /* Emulate in ring 3. */
2428 case SVM_EXIT_MSR:
2429 {
2430 uint32_t cbSize;
2431
2432 /* When an interrupt is pending, we'll let MSR_K8_LSTAR writes fault in our TPR patch code. */
2433 if ( pVM->hwaccm.s.fTPRPatchingActive
2434 && pCtx->ecx == MSR_K8_LSTAR
2435 && pVMCB->ctrl.u64ExitInfo1 == 1 /* wrmsr */)
2436 {
2437 if ((pCtx->eax & 0xff) != u8LastTPR)
2438 {
2439 Log(("SVM: Faulting MSR_K8_LSTAR write with new TPR value %x\n", pCtx->eax & 0xff));
2440
2441 /* Our patch code uses LSTAR for TPR caching. */
2442 rc = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
2443 AssertRC(rc);
2444 }
2445
2446 /* Skip the instruction and continue. */
2447 pCtx->rip += 2; /* wrmsr = [0F 30] */
2448
2449 /* Only resume if successful. */
2450 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2451 goto ResumeExecution;
2452 }
2453
2454 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2455 STAM_COUNTER_INC((pVMCB->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
2456 Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
2457 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2458 if (rc == VINF_SUCCESS)
2459 {
2460 /* EIP has been updated already. */
2461
2462 /* Only resume if successful. */
2463 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2464 goto ResumeExecution;
2465 }
2466 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
2467 break;
2468 }
2469
2470 case SVM_EXIT_TASK_SWITCH: /* too complicated to emulate, so fall back to the recompiler*/
2471 Log(("SVM_EXIT_TASK_SWITCH: exit2=%RX64\n", pVMCB->ctrl.u64ExitInfo2));
2472 if ( !(pVMCB->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET | SVM_EXIT2_TASK_SWITCH_JMP))
2473 && pVCpu->hwaccm.s.Event.fPending)
2474 {
2475 SVM_EVENT Event;
2476
2477 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
2478
2479 /* Caused by an injected interrupt. */
2480 pVCpu->hwaccm.s.Event.fPending = false;
2481
2482 switch (Event.n.u3Type)
2483 {
2484 case SVM_EVENT_EXTERNAL_IRQ:
2485 case SVM_EVENT_NMI:
2486 Log(("SVM_EXIT_TASK_SWITCH: reassert trap %d\n", Event.n.u8Vector));
2487 Assert(!Event.n.u1ErrorCodeValid);
2488 rc = TRPMAssertTrap(pVCpu, Event.n.u8Vector, TRPM_HARDWARE_INT);
2489 AssertRC(rc);
2490 break;
2491
2492 default:
2493 /* Exceptions and software interrupts can just be restarted. */
2494 break;
2495 }
2496 }
2497 rc = VERR_EM_INTERPRETER;
2498 break;
2499
2500 case SVM_EXIT_PAUSE:
2501 case SVM_EXIT_MWAIT_ARMED:
2502 rc = VERR_EM_INTERPRETER;
2503 break;
2504
2505 case SVM_EXIT_SHUTDOWN:
2506 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2507 break;
2508
2509 case SVM_EXIT_IDTR_READ:
2510 case SVM_EXIT_GDTR_READ:
2511 case SVM_EXIT_LDTR_READ:
2512 case SVM_EXIT_TR_READ:
2513 case SVM_EXIT_IDTR_WRITE:
2514 case SVM_EXIT_GDTR_WRITE:
2515 case SVM_EXIT_LDTR_WRITE:
2516 case SVM_EXIT_TR_WRITE:
2517 case SVM_EXIT_CR0_SEL_WRITE:
2518 default:
2519 /* Unexpected exit codes. */
2520 rc = VERR_EM_INTERNAL_ERROR;
2521 AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2522 break;
2523 }
2524
2525end:
2526
2527 /* Signal changes for the recompiler. */
2528 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2529
2530 /* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
2531 if (exitCode == SVM_EXIT_INTR)
2532 {
2533 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
2534 /* On the next entry we'll only sync the host context. */
2535 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2536 }
2537 else
2538 {
2539 /* On the next entry we'll sync everything. */
2540 /** @todo we can do better than this */
2541 /* Not in the VINF_PGM_CHANGE_MODE though! */
2542 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2543 }
2544
2545 /* translate into a less severe return code */
2546 if (rc == VERR_EM_INTERPRETER)
2547 rc = VINF_EM_RAW_EMULATE_INSTR;
2548
2549 /* Just set the correct state here instead of trying to catch every goto above. */
2550 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
2551
2552#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2553 /* Restore interrupts if we exitted after disabling them. */
2554 if (uOldEFlags != ~(RTCCUINTREG)0)
2555 ASMSetFlags(uOldEFlags);
2556#endif
2557
2558 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2559 return rc;
2560}
2561
2562/**
2563 * Emulate simple mov tpr instruction
2564 *
2565 * @returns VBox status code.
2566 * @param pVM The VM to operate on.
2567 * @param pVCpu The VM CPU to operate on.
2568 * @param pCtx CPU context
2569 */
2570static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2571{
2572 int rc;
2573
2574 LogFlow(("Emulated VMMCall TPR access replacement at %RGv\n", pCtx->rip));
2575
2576 while (true)
2577 {
2578 bool fPending;
2579 uint8_t u8Tpr;
2580
2581 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2582 if (!pPatch)
2583 break;
2584
2585 switch(pPatch->enmType)
2586 {
2587 case HWACCMTPRINSTR_READ:
2588 /* TPR caching in CR8 */
2589 rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending);
2590 AssertRC(rc);
2591
2592 rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
2593 AssertRC(rc);
2594
2595 LogFlow(("Emulated read successfully\n"));
2596 pCtx->rip += pPatch->cbOp;
2597 break;
2598
2599 case HWACCMTPRINSTR_WRITE_REG:
2600 case HWACCMTPRINSTR_WRITE_IMM:
2601 /* Fetch the new TPR value */
2602 if (pPatch->enmType == HWACCMTPRINSTR_WRITE_REG)
2603 {
2604 uint32_t val;
2605
2606 rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &val);
2607 AssertRC(rc);
2608 u8Tpr = val;
2609 }
2610 else
2611 u8Tpr = (uint8_t)pPatch->uSrcOperand;
2612
2613 rc = PDMApicSetTPR(pVCpu, u8Tpr);
2614 AssertRC(rc);
2615 LogFlow(("Emulated write successfully\n"));
2616 pCtx->rip += pPatch->cbOp;
2617 break;
2618 default:
2619 AssertMsgFailedReturn(("Unexpected type %d\n", pPatch->enmType), VERR_INTERNAL_ERROR);
2620 }
2621 }
2622 return VINF_SUCCESS;
2623}
2624
2625
2626/**
2627 * Enters the AMD-V session
2628 *
2629 * @returns VBox status code.
2630 * @param pVM The VM to operate on.
2631 * @param pVCpu The VM CPU to operate on.
2632 * @param pCpu CPU info struct
2633 */
2634VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
2635{
2636 Assert(pVM->hwaccm.s.svm.fSupported);
2637
2638 LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
2639 pVCpu->hwaccm.s.fResumeVM = false;
2640
2641 /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2642 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_LDTR;
2643
2644 return VINF_SUCCESS;
2645}
2646
2647
2648/**
2649 * Leaves the AMD-V session
2650 *
2651 * @returns VBox status code.
2652 * @param pVM The VM to operate on.
2653 * @param pVCpu The VM CPU to operate on.
2654 * @param pCtx CPU context
2655 */
2656VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2657{
2658 SVM_VMCB *pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2659
2660 Assert(pVM->hwaccm.s.svm.fSupported);
2661
2662#ifdef DEBUG
2663 if (CPUMIsHyperDebugStateActive(pVCpu))
2664 {
2665 CPUMR0LoadHostDebugState(pVM, pVCpu);
2666 }
2667 else
2668#endif
2669 /* Save the guest debug state if necessary. */
2670 if (CPUMIsGuestDebugStateActive(pVCpu))
2671 {
2672 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
2673
2674 /* Intercept all DRx reads and writes again. Changed later on. */
2675 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
2676 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
2677
2678 /* Resync the debug registers the next time. */
2679 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2680 }
2681 else
2682 Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
2683
2684 return VINF_SUCCESS;
2685}
2686
2687
2688static int svmR0InterpretInvlPg(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2689{
2690 OP_PARAMVAL param1;
2691 RTGCPTR addr;
2692
2693 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2694 if(RT_FAILURE(rc))
2695 return VERR_EM_INTERPRETER;
2696
2697 switch(param1.type)
2698 {
2699 case PARMTYPE_IMMEDIATE:
2700 case PARMTYPE_ADDRESS:
2701 if(!(param1.flags & (PARAM_VAL32|PARAM_VAL64)))
2702 return VERR_EM_INTERPRETER;
2703 addr = param1.val.val64;
2704 break;
2705
2706 default:
2707 return VERR_EM_INTERPRETER;
2708 }
2709
2710 /** @todo is addr always a flat linear address or ds based
2711 * (in absence of segment override prefixes)????
2712 */
2713 rc = PGMInvalidatePage(pVCpu, addr);
2714 if (RT_SUCCESS(rc))
2715 return VINF_SUCCESS;
2716
2717 AssertRC(rc);
2718 return rc;
2719}
2720
2721/**
2722 * Interprets INVLPG
2723 *
2724 * @returns VBox status code.
2725 * @retval VINF_* Scheduling instructions.
2726 * @retval VERR_EM_INTERPRETER Something we can't cope with.
2727 * @retval VERR_* Fatal errors.
2728 *
2729 * @param pVM The VM handle.
2730 * @param pRegFrame The register frame.
2731 * @param ASID Tagged TLB id for the guest
2732 *
2733 * Updates the EIP if an instruction was executed successfully.
2734 */
2735static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2736{
2737 /*
2738 * Only allow 32 & 64 bits code.
2739 */
2740 DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2741 if (enmMode != CPUMODE_16BIT)
2742 {
2743 RTGCPTR pbCode;
2744 int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
2745 &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2746 if (RT_SUCCESS(rc))
2747 {
2748 uint32_t cbOp;
2749 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2750
2751 pDis->mode = enmMode;
2752 rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, pDis, &cbOp);
2753 Assert(RT_FAILURE(rc) || pDis->pCurInstr->opcode == OP_INVLPG);
2754 if (RT_SUCCESS(rc) && pDis->pCurInstr->opcode == OP_INVLPG)
2755 {
2756 Assert(cbOp == pDis->opsize);
2757 rc = svmR0InterpretInvlPg(pVCpu, pDis, pRegFrame, uASID);
2758 if (RT_SUCCESS(rc))
2759 pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2760
2761 return rc;
2762 }
2763 }
2764 }
2765 return VERR_EM_INTERPRETER;
2766}
2767
2768
2769/**
2770 * Invalidates a guest page
2771 *
2772 * @returns VBox status code.
2773 * @param pVM The VM to operate on.
2774 * @param pVCpu The VM CPU to operate on.
2775 * @param GCVirt Page to invalidate
2776 */
2777VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
2778{
2779 bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB | VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH);
2780
2781 /* Skip it if a TLB flush is already pending. */
2782 if (!fFlushPending)
2783 {
2784 SVM_VMCB *pVMCB;
2785
2786 Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
2787 AssertReturn(pVM, VERR_INVALID_PARAMETER);
2788 Assert(pVM->hwaccm.s.svm.fSupported);
2789
2790 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2791 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2792
2793#if HC_ARCH_BITS == 32
2794 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
2795 if (CPUMIsGuestInLongMode(pVCpu))
2796 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2797 else
2798#endif
2799 SVMR0InvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2800 }
2801 return VINF_SUCCESS;
2802}
2803
2804
2805#if 0 /* obsolete, but left here for clarification. */
2806/**
2807 * Invalidates a guest page by physical address
2808 *
2809 * @returns VBox status code.
2810 * @param pVM The VM to operate on.
2811 * @param pVCpu The VM CPU to operate on.
2812 * @param GCPhys Page to invalidate
2813 */
2814VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
2815{
2816 Assert(pVM->hwaccm.s.fNestedPaging);
2817 /* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
2818 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2819 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBInvlpga);
2820 return VINF_SUCCESS;
2821}
2822#endif
2823
2824#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2825/**
2826 * Prepares for and executes VMRUN (64 bits guests from a 32 bits hosts).
2827 *
2828 * @returns VBox status code.
2829 * @param pVMCBHostPhys Physical address of host VMCB.
2830 * @param pVMCBPhys Physical address of the VMCB.
2831 * @param pCtx Guest context.
2832 * @param pVM The VM to operate on.
2833 * @param pVCpu The VMCPU to operate on.
2834 */
2835DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
2836{
2837 uint32_t aParam[4];
2838
2839 aParam[0] = (uint32_t)(pVMCBHostPhys); /* Param 1: pVMCBHostPhys - Lo. */
2840 aParam[1] = (uint32_t)(pVMCBHostPhys >> 32); /* Param 1: pVMCBHostPhys - Hi. */
2841 aParam[2] = (uint32_t)(pVMCBPhys); /* Param 2: pVMCBPhys - Lo. */
2842 aParam[3] = (uint32_t)(pVMCBPhys >> 32); /* Param 2: pVMCBPhys - Hi. */
2843
2844 return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSVMGCVMRun64, 4, &aParam[0]);
2845}
2846
2847/**
2848 * Executes the specified handler in 64 mode
2849 *
2850 * @returns VBox status code.
2851 * @param pVM The VM to operate on.
2852 * @param pVCpu The VMCPU to operate on.
2853 * @param pCtx Guest context
2854 * @param pfnHandler RC handler
2855 * @param cbParam Number of parameters
2856 * @param paParam Array of 32 bits parameters
2857 */
2858VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
2859{
2860 int rc;
2861 RTHCUINTREG uOldEFlags;
2862
2863 Assert(pfnHandler);
2864
2865 /* Disable interrupts. */
2866 uOldEFlags = ASMIntDisableFlags();
2867
2868 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
2869 CPUMSetHyperEIP(pVCpu, pfnHandler);
2870 for (int i=(int)cbParam-1;i>=0;i--)
2871 CPUMPushHyper(pVCpu, paParam[i]);
2872
2873 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2874 /* Call switcher. */
2875 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
2876 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2877
2878 ASMSetFlags(uOldEFlags);
2879 return rc;
2880}
2881
2882#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
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