VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 25062

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1/* $Id: HWSVMR0.cpp 24994 2009-11-26 12:09:48Z vboxsync $ */
2/** @file
3 * HWACCM SVM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/hwacc_svm.h>
32#include <VBox/pgm.h>
33#include <VBox/pdm.h>
34#include <VBox/err.h>
35#include <VBox/log.h>
36#include <VBox/selm.h>
37#include <VBox/iom.h>
38#include <VBox/dis.h>
39#include <VBox/dbgf.h>
40#include <VBox/disopcode.h>
41#include <iprt/param.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/cpuset.h>
45#include <iprt/mp.h>
46#include <iprt/time.h>
47#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
48# include <iprt/thread.h>
49#endif
50#include "HWSVMR0.h"
51
52/*******************************************************************************
53* Internal Functions *
54*******************************************************************************/
55static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID);
56static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
57static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);
58
59/*******************************************************************************
60* Global Variables *
61*******************************************************************************/
62
63/**
64 * Sets up and activates AMD-V on the current CPU
65 *
66 * @returns VBox status code.
67 * @param pCpu CPU info struct
68 * @param pVM The VM to operate on. (can be NULL after a resume!!)
69 * @param pvPageCpu Pointer to the global cpu page
70 * @param pPageCpuPhys Physical address of the global cpu page
71 */
72VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
73{
74 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
75 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
76
77 /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
78 uint64_t val = ASMRdMsr(MSR_K6_EFER);
79 if (val & MSR_K6_EFER_SVME)
80 return VERR_SVM_IN_USE;
81
82 /* Turn on AMD-V in the EFER MSR. */
83 ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);
84
85 /* Write the physical page address where the CPU will store the host state while executing the VM. */
86 ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
87
88 return VINF_SUCCESS;
89}
90
91/**
92 * Deactivates AMD-V on the current CPU
93 *
94 * @returns VBox status code.
95 * @param pCpu CPU info struct
96 * @param pvPageCpu Pointer to the global cpu page
97 * @param pPageCpuPhys Physical address of the global cpu page
98 */
99VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
100{
101 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
102 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
103
104 /* Turn off AMD-V in the EFER MSR. */
105 uint64_t val = ASMRdMsr(MSR_K6_EFER);
106 ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
107
108 /* Invalidate host state physical address. */
109 ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
110
111 return VINF_SUCCESS;
112}
113
114/**
115 * Does Ring-0 per VM AMD-V init.
116 *
117 * @returns VBox status code.
118 * @param pVM The VM to operate on.
119 */
120VMMR0DECL(int) SVMR0InitVM(PVM pVM)
121{
122 int rc;
123
124 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
125
126 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
127 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
128 if (RT_FAILURE(rc))
129 return rc;
130
131 pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
132 pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
133 /* Set all bits to intercept all IO accesses. */
134 ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
135
136 /* Erratum 170 which requires a forced TLB flush for each world switch:
137 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
138 *
139 * All BH-G1/2 and DH-G1/2 models include a fix:
140 * Athlon X2: 0x6b 1/2
141 * 0x68 1/2
142 * Athlon 64: 0x7f 1
143 * 0x6f 2
144 * Sempron: 0x7f 1/2
145 * 0x6f 2
146 * 0x6c 2
147 * 0x7c 2
148 * Turion 64: 0x68 2
149 *
150 */
151 uint32_t u32Dummy;
152 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
153 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
154 u32BaseFamily= (u32Version >> 8) & 0xf;
155 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
156 u32Model = ((u32Version >> 4) & 0xf);
157 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
158 u32Stepping = u32Version & 0xf;
159 if ( u32Family == 0xf
160 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
161 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
162 {
163 Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
164 pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
165 }
166
167 /* Allocate VMCBs for all guest CPUs. */
168 for (VMCPUID i = 0; i < pVM->cCpus; i++)
169 {
170 PVMCPU pVCpu = &pVM->aCpus[i];
171
172 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
173 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
174 pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
175
176 /* Allocate one page for the host context */
177 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
178 if (RT_FAILURE(rc))
179 return rc;
180
181 pVCpu->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCBHost);
182 pVCpu->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 0);
183 Assert(pVCpu->hwaccm.s.svm.pVMCBHostPhys < _4G);
184 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCBHost);
185
186 /* Allocate one page for the VM control block (VMCB). */
187 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
188 if (RT_FAILURE(rc))
189 return rc;
190
191 pVCpu->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCB);
192 pVCpu->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCB, 0);
193 Assert(pVCpu->hwaccm.s.svm.pVMCBPhys < _4G);
194 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCB);
195
196 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
197 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
198 if (RT_FAILURE(rc))
199 return rc;
200
201 pVCpu->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap);
202 pVCpu->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 0);
203 /* Set all bits to intercept all MSR accesses. */
204 ASMMemFill32(pVCpu->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
205 }
206
207 return VINF_SUCCESS;
208}
209
210/**
211 * Does Ring-0 per VM AMD-V termination.
212 *
213 * @returns VBox status code.
214 * @param pVM The VM to operate on.
215 */
216VMMR0DECL(int) SVMR0TermVM(PVM pVM)
217{
218 for (VMCPUID i = 0; i < pVM->cCpus; i++)
219 {
220 PVMCPU pVCpu = &pVM->aCpus[i];
221
222 if (pVCpu->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
223 {
224 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, false);
225 pVCpu->hwaccm.s.svm.pVMCBHost = 0;
226 pVCpu->hwaccm.s.svm.pVMCBHostPhys = 0;
227 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
228 }
229
230 if (pVCpu->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
231 {
232 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCB, false);
233 pVCpu->hwaccm.s.svm.pVMCB = 0;
234 pVCpu->hwaccm.s.svm.pVMCBPhys = 0;
235 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
236 }
237 if (pVCpu->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
238 {
239 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, false);
240 pVCpu->hwaccm.s.svm.pMSRBitmap = 0;
241 pVCpu->hwaccm.s.svm.pMSRBitmapPhys = 0;
242 pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
243 }
244 }
245 if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
246 {
247 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
248 pVM->hwaccm.s.svm.pIOBitmap = 0;
249 pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
250 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
251 }
252 return VINF_SUCCESS;
253}
254
255/**
256 * Sets up AMD-V for the specified VM
257 *
258 * @returns VBox status code.
259 * @param pVM The VM to operate on.
260 */
261VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
262{
263 int rc = VINF_SUCCESS;
264
265 AssertReturn(pVM, VERR_INVALID_PARAMETER);
266
267 Assert(pVM->hwaccm.s.svm.fSupported);
268
269 for (VMCPUID i = 0; i < pVM->cCpus; i++)
270 {
271 PVMCPU pVCpu = &pVM->aCpus[i];
272 SVM_VMCB *pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
273
274 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
275
276 /* Program the control fields. Most of them never have to be changed again. */
277 /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
278 /* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
279 if (!pVM->hwaccm.s.fNestedPaging)
280 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
281 else
282 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4);
283
284 /*
285 * CR0/3/4 writes must be intercepted for obvious reasons.
286 */
287 if (!pVM->hwaccm.s.fNestedPaging)
288 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
289 else
290 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4) | RT_BIT(8);
291
292 /* Intercept all DRx reads and writes by default. Changed later on. */
293 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
294 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
295
296 /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
297 * All breakpoints are automatically cleared when the VM exits.
298 */
299
300 pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
301#ifndef DEBUG
302 if (pVM->hwaccm.s.fNestedPaging)
303 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
304#endif
305
306 pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
307 | SVM_CTRL1_INTERCEPT_VINTR
308 | SVM_CTRL1_INTERCEPT_NMI
309 | SVM_CTRL1_INTERCEPT_SMI
310 | SVM_CTRL1_INTERCEPT_INIT
311 | SVM_CTRL1_INTERCEPT_RDPMC
312 | SVM_CTRL1_INTERCEPT_CPUID
313 | SVM_CTRL1_INTERCEPT_RSM
314 | SVM_CTRL1_INTERCEPT_HLT
315 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP
316 | SVM_CTRL1_INTERCEPT_MSR_SHADOW
317 | SVM_CTRL1_INTERCEPT_INVLPG
318 | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
319 | SVM_CTRL1_INTERCEPT_TASK_SWITCH
320 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
321 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
322 ;
323 /* With nested paging we don't care about invlpg anymore. */
324 if (pVM->hwaccm.s.fNestedPaging)
325 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
326
327 pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
328 | SVM_CTRL2_INTERCEPT_VMMCALL
329 | SVM_CTRL2_INTERCEPT_VMLOAD
330 | SVM_CTRL2_INTERCEPT_VMSAVE
331 | SVM_CTRL2_INTERCEPT_STGI
332 | SVM_CTRL2_INTERCEPT_CLGI
333 | SVM_CTRL2_INTERCEPT_SKINIT
334 | SVM_CTRL2_INTERCEPT_WBINVD
335 | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
336 ;
337 Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
338 Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
339 Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
340
341 /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
342 pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
343 /* Ignore the priority in the TPR; just deliver it when we tell it to. */
344 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
345
346 /* Set IO and MSR bitmap addresses. */
347 pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
348 pVMCB->ctrl.u64MSRPMPhysAddr = pVCpu->hwaccm.s.svm.pMSRBitmapPhys;
349
350 /* No LBR virtualization. */
351 pVMCB->ctrl.u64LBRVirt = 0;
352
353 /** The ASID must start at 1; the host uses 0. */
354 pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
355
356 /** Setup the PAT msr (nested paging only) */
357 pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
358
359 /* The following MSRs are saved automatically by vmload/vmsave, so we allow the guest
360 * to modify them directly.
361 */
362 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
363 svmR0SetMSRPermission(pVCpu, MSR_K8_CSTAR, true, true);
364 svmR0SetMSRPermission(pVCpu, MSR_K6_STAR, true, true);
365 svmR0SetMSRPermission(pVCpu, MSR_K8_SF_MASK, true, true);
366 svmR0SetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true);
367 svmR0SetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true);
368 svmR0SetMSRPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, true, true);
369 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_CS, true, true);
370 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_ESP, true, true);
371 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_EIP, true, true);
372 }
373
374 return rc;
375}
376
377
378/**
379 * Sets the permission bits for the specified MSR
380 *
381 * @param pVCpu The VMCPU to operate on.
382 * @param ulMSR MSR value
383 * @param fRead Reading allowed/disallowed
384 * @param fWrite Writing allowed/disallowed
385 */
386static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)
387{
388 unsigned ulBit;
389 uint8_t *pMSRBitmap = (uint8_t *)pVCpu->hwaccm.s.svm.pMSRBitmap;
390
391 if (ulMSR <= 0x00001FFF)
392 {
393 /* Pentium-compatible MSRs */
394 ulBit = ulMSR * 2;
395 }
396 else
397 if ( ulMSR >= 0xC0000000
398 && ulMSR <= 0xC0001FFF)
399 {
400 /* AMD Sixth Generation x86 Processor MSRs and SYSCALL */
401 ulBit = (ulMSR - 0xC0000000) * 2;
402 pMSRBitmap += 0x800;
403 }
404 else
405 if ( ulMSR >= 0xC0010000
406 && ulMSR <= 0xC0011FFF)
407 {
408 /* AMD Seventh and Eighth Generation Processor MSRs */
409 ulBit = (ulMSR - 0xC0001000) * 2;
410 pMSRBitmap += 0x1000;
411 }
412 else
413 {
414 AssertFailed();
415 return;
416 }
417 Assert(ulBit < 16 * 1024 - 1);
418 if (fRead)
419 ASMBitClear(pMSRBitmap, ulBit);
420 else
421 ASMBitSet(pMSRBitmap, ulBit);
422
423 if (fWrite)
424 ASMBitClear(pMSRBitmap, ulBit + 1);
425 else
426 ASMBitSet(pMSRBitmap, ulBit + 1);
427}
428
429/**
430 * Injects an event (trap or external interrupt)
431 *
432 * @param pVCpu The VMCPU to operate on.
433 * @param pVMCB SVM control block
434 * @param pCtx CPU Context
435 * @param pIntInfo SVM interrupt info
436 */
437inline void SVMR0InjectEvent(PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)
438{
439#ifdef VBOX_WITH_STATISTICS
440 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
441#endif
442
443#ifdef VBOX_STRICT
444 if (pEvent->n.u8Vector == 0xE)
445 Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
446 else
447 if (pEvent->n.u8Vector < 0x20)
448 Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
449 else
450 {
451 Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
452 Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
453 Assert(pCtx->eflags.u32 & X86_EFL_IF);
454 }
455#endif
456
457 /* Set event injection state. */
458 pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
459}
460
461
462/**
463 * Checks for pending guest interrupts and injects them
464 *
465 * @returns VBox status code.
466 * @param pVM The VM to operate on.
467 * @param pVCpu The VM CPU to operate on.
468 * @param pVMCB SVM control block
469 * @param pCtx CPU Context
470 */
471static int SVMR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
472{
473 int rc;
474
475 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
476 if (pVCpu->hwaccm.s.Event.fPending)
477 {
478 SVM_EVENT Event;
479
480 Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
481 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
482 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
483 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
484
485 pVCpu->hwaccm.s.Event.fPending = false;
486 return VINF_SUCCESS;
487 }
488
489 /* If an active trap is already pending, then we must forward it first! */
490 if (!TRPMHasTrap(pVCpu))
491 {
492 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI))
493 {
494 SVM_EVENT Event;
495
496 Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
497 Event.n.u8Vector = X86_XCPT_NMI;
498 Event.n.u1Valid = 1;
499 Event.n.u32ErrorCode = 0;
500 Event.n.u3Type = SVM_EVENT_NMI;
501
502 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
503 return VINF_SUCCESS;
504 }
505
506 /* @todo SMI interrupts. */
507
508 /* When external interrupts are pending, we should exit the VM when IF is set. */
509 if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
510 {
511 if ( !(pCtx->eflags.u32 & X86_EFL_IF)
512 || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
513 {
514 if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
515 {
516 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
517 LogFlow(("Enable irq window exit!\n"));
518 else
519 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
520
521 /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
522 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
523 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
524 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
525 }
526 }
527 else
528 {
529 uint8_t u8Interrupt;
530
531 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
532 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
533 if (RT_SUCCESS(rc))
534 {
535 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
536 AssertRC(rc);
537 }
538 else
539 {
540 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
541 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
542 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
543 /* Just continue */
544 }
545 }
546 }
547 }
548
549#ifdef VBOX_STRICT
550 if (TRPMHasTrap(pVCpu))
551 {
552 uint8_t u8Vector;
553 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
554 AssertRC(rc);
555 }
556#endif
557
558 if ( (pCtx->eflags.u32 & X86_EFL_IF)
559 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
560 && TRPMHasTrap(pVCpu)
561 )
562 {
563 uint8_t u8Vector;
564 int rc;
565 TRPMEVENT enmType;
566 SVM_EVENT Event;
567 RTGCUINT u32ErrorCode;
568
569 Event.au64[0] = 0;
570
571 /* If a new event is pending, then dispatch it now. */
572 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, 0);
573 AssertRC(rc);
574 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
575 Assert(enmType != TRPM_SOFTWARE_INT);
576
577 /* Clear the pending trap. */
578 rc = TRPMResetTrap(pVCpu);
579 AssertRC(rc);
580
581 Event.n.u8Vector = u8Vector;
582 Event.n.u1Valid = 1;
583 Event.n.u32ErrorCode = u32ErrorCode;
584
585 if (enmType == TRPM_TRAP)
586 {
587 switch (u8Vector) {
588 case 8:
589 case 10:
590 case 11:
591 case 12:
592 case 13:
593 case 14:
594 case 17:
595 /* Valid error codes. */
596 Event.n.u1ErrorCodeValid = 1;
597 break;
598 default:
599 break;
600 }
601 if (u8Vector == X86_XCPT_NMI)
602 Event.n.u3Type = SVM_EVENT_NMI;
603 else
604 Event.n.u3Type = SVM_EVENT_EXCEPTION;
605 }
606 else
607 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
608
609 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
610 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
611 } /* if (interrupts can be dispatched) */
612
613 return VINF_SUCCESS;
614}
615
616/**
617 * Save the host state
618 *
619 * @returns VBox status code.
620 * @param pVM The VM to operate on.
621 * @param pVCpu The VM CPU to operate on.
622 */
623VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
624{
625 NOREF(pVM);
626 NOREF(pVCpu);
627 /* Nothing to do here. */
628 return VINF_SUCCESS;
629}
630
631/**
632 * Loads the guest state
633 *
634 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
635 *
636 * @returns VBox status code.
637 * @param pVM The VM to operate on.
638 * @param pVCpu The VM CPU to operate on.
639 * @param pCtx Guest context
640 */
641VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
642{
643 RTGCUINTPTR val;
644 SVM_VMCB *pVMCB;
645
646 if (pVM == NULL)
647 return VERR_INVALID_PARAMETER;
648
649 /* Setup AMD SVM. */
650 Assert(pVM->hwaccm.s.svm.fSupported);
651
652 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
653 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
654
655 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
656 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
657 {
658 SVM_WRITE_SELREG(CS, cs);
659 SVM_WRITE_SELREG(SS, ss);
660 SVM_WRITE_SELREG(DS, ds);
661 SVM_WRITE_SELREG(ES, es);
662 SVM_WRITE_SELREG(FS, fs);
663 SVM_WRITE_SELREG(GS, gs);
664 }
665
666 /* Guest CPU context: LDTR. */
667 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
668 {
669 SVM_WRITE_SELREG(LDTR, ldtr);
670 }
671
672 /* Guest CPU context: TR. */
673 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
674 {
675 SVM_WRITE_SELREG(TR, tr);
676 }
677
678 /* Guest CPU context: GDTR. */
679 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
680 {
681 pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
682 pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
683 }
684
685 /* Guest CPU context: IDTR. */
686 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
687 {
688 pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
689 pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
690 }
691
692 /*
693 * Sysenter MSRs (unconditional)
694 */
695 pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
696 pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
697 pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
698
699 /* Control registers */
700 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
701 {
702 val = pCtx->cr0;
703 if (!CPUMIsGuestFPUStateActive(pVCpu))
704 {
705 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
706 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
707 }
708 else
709 {
710 /** @todo check if we support the old style mess correctly. */
711 if (!(val & X86_CR0_NE))
712 {
713 Log(("Forcing X86_CR0_NE!!!\n"));
714
715 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
716 if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)
717 {
718 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_MF);
719 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
720 }
721 }
722 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
723 }
724 /* Always enable caching. */
725 val &= ~(X86_CR0_CD|X86_CR0_NW);
726
727 /* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
728 /* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
729 if (!pVM->hwaccm.s.fNestedPaging)
730 {
731 val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
732 val |= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
733 }
734 pVMCB->guest.u64CR0 = val;
735 }
736 /* CR2 as well */
737 pVMCB->guest.u64CR2 = pCtx->cr2;
738
739 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
740 {
741 /* Save our shadow CR3 register. */
742 if (pVM->hwaccm.s.fNestedPaging)
743 {
744 PGMMODE enmShwPagingMode;
745
746#if HC_ARCH_BITS == 32
747 if (CPUMIsGuestInLongModeEx(pCtx))
748 enmShwPagingMode = PGMMODE_AMD64_NX;
749 else
750#endif
751 enmShwPagingMode = PGMGetHostMode(pVM);
752
753 pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
754 Assert(pVMCB->ctrl.u64NestedPagingCR3);
755 pVMCB->guest.u64CR3 = pCtx->cr3;
756 }
757 else
758 {
759 pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
760 Assert(pVMCB->guest.u64CR3 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
761 }
762 }
763
764 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
765 {
766 val = pCtx->cr4;
767 if (!pVM->hwaccm.s.fNestedPaging)
768 {
769 switch(pVCpu->hwaccm.s.enmShadowMode)
770 {
771 case PGMMODE_REAL:
772 case PGMMODE_PROTECTED: /* Protected mode, no paging. */
773 AssertFailed();
774 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
775
776 case PGMMODE_32_BIT: /* 32-bit paging. */
777 val &= ~X86_CR4_PAE;
778 break;
779
780 case PGMMODE_PAE: /* PAE paging. */
781 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
782 /** @todo use normal 32 bits paging */
783 val |= X86_CR4_PAE;
784 break;
785
786 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
787 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
788#ifdef VBOX_ENABLE_64_BITS_GUESTS
789 break;
790#else
791 AssertFailed();
792 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
793#endif
794
795 default: /* shut up gcc */
796 AssertFailed();
797 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
798 }
799 }
800 pVMCB->guest.u64CR4 = val;
801 }
802
803 /* Debug registers. */
804 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
805 {
806 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
807 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
808
809 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
810 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
811 pCtx->dr[7] |= 0x400; /* must be one */
812
813 pVMCB->guest.u64DR7 = pCtx->dr[7];
814 pVMCB->guest.u64DR6 = pCtx->dr[6];
815
816#ifdef DEBUG
817 /* Sync the hypervisor debug state now if any breakpoint is armed. */
818 if ( CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK|X86_DR7_GD)
819 && !CPUMIsHyperDebugStateActive(pVCpu)
820 && !DBGFIsStepping(pVCpu))
821 {
822 /* Save the host and load the hypervisor debug state. */
823 int rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
824 AssertRC(rc);
825
826 /* DRx intercepts remain enabled. */
827
828 /* Override dr6 & dr7 with the hypervisor values. */
829 pVMCB->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
830 pVMCB->guest.u64DR6 = CPUMGetHyperDR6(pVCpu);
831 }
832 else
833#endif
834 /* Sync the debug state now if any breakpoint is armed. */
835 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
836 && !CPUMIsGuestDebugStateActive(pVCpu)
837 && !DBGFIsStepping(pVCpu))
838 {
839 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
840
841 /* Disable drx move intercepts. */
842 pVMCB->ctrl.u16InterceptRdDRx = 0;
843 pVMCB->ctrl.u16InterceptWrDRx = 0;
844
845 /* Save the host and load the guest debug state. */
846 int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
847 AssertRC(rc);
848 }
849 }
850
851 /* EIP, ESP and EFLAGS */
852 pVMCB->guest.u64RIP = pCtx->rip;
853 pVMCB->guest.u64RSP = pCtx->rsp;
854 pVMCB->guest.u64RFlags = pCtx->eflags.u32;
855
856 /* Set CPL */
857 pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
858
859 /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
860 pVMCB->guest.u64RAX = pCtx->rax;
861
862 /* vmrun will fail without MSR_K6_EFER_SVME. */
863 pVMCB->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
864
865 /* 64 bits guest mode? */
866 if (CPUMIsGuestInLongModeEx(pCtx))
867 {
868#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
869 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
870#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
871 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
872#else
873# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
874 if (!pVM->hwaccm.s.fAllow64BitGuests)
875 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
876# endif
877 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun64;
878#endif
879 /* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
880 pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
881 pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
882 }
883 else
884 {
885 /* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
886 pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
887
888 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun;
889 }
890
891 /* TSC offset. */
892 if (TMCpuTickCanUseRealTSC(pVCpu, &pVMCB->ctrl.u64TSCOffset))
893 {
894 uint64_t u64CurTSC = ASMReadTSC();
895 if (u64CurTSC + pVMCB->ctrl.u64TSCOffset >= TMCpuTickGetLastSeen(pVCpu))
896 {
897 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
898 pVMCB->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
899 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
900 }
901 else
902 {
903 /* Fall back to rdtsc emulation as we would otherwise pass decreasing tsc values to the guest. */
904 LogFlow(("TSC %RX64 offset %RX64 time=%RX64 last=%RX64 (diff=%RX64, virt_tsc=%RX64)\n", u64CurTSC, pVMCB->ctrl.u64TSCOffset, u64CurTSC + pVMCB->ctrl.u64TSCOffset, TMCpuTickGetLastSeen(pVCpu), TMCpuTickGetLastSeen(pVCpu) - u64CurTSC - pVMCB->ctrl.u64TSCOffset, TMCpuTickGet(pVCpu)));
905 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
906 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
907 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow);
908 }
909 }
910 else
911 {
912 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
913 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
914 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
915 }
916
917 /* Sync the various msrs for 64 bits mode. */
918 pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
919 pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
920 pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
921 pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
922 pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
923
924#ifdef DEBUG
925 /* Intercept X86_XCPT_DB if stepping is enabled */
926 if ( DBGFIsStepping(pVCpu)
927 || CPUMIsHyperDebugStateActive(pVCpu))
928 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_DB);
929 else
930 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
931#endif
932
933 /* Done. */
934 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
935
936 return VINF_SUCCESS;
937}
938
939
940/**
941 * Runs guest code in an AMD-V VM.
942 *
943 * @returns VBox status code.
944 * @param pVM The VM to operate on.
945 * @param pVCpu The VM CPU to operate on.
946 * @param pCtx Guest context
947 */
948VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
949{
950 int rc = VINF_SUCCESS;
951 uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
952 SVM_VMCB *pVMCB;
953 bool fSyncTPR = false;
954 unsigned cResume = 0;
955 uint8_t u8LastTPR;
956 PHWACCM_CPUINFO pCpu = 0;
957 RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
958#ifdef VBOX_STRICT
959 RTCPUID idCpuCheck;
960#endif
961#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
962 uint64_t u64LastTime = RTTimeMilliTS();
963#endif
964
965 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
966
967 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
968 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
969
970 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
971 */
972ResumeExecution:
973 Assert(!HWACCMR0SuspendPending());
974
975 /* Safety precaution; looping for too long here can have a very bad effect on the host */
976 if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
977 {
978 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
979 rc = VINF_EM_RAW_INTERRUPT;
980 goto end;
981 }
982
983 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
984 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
985 {
986 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
987 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
988 {
989 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
990 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
991 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
992 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
993 */
994 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
995 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
996 pVMCB->ctrl.u64IntShadow = 0;
997 }
998 }
999 else
1000 {
1001 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
1002 pVMCB->ctrl.u64IntShadow = 0;
1003 }
1004
1005#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
1006 if (RT_UNLIKELY(cResume & 0xf) == 0)
1007 {
1008 uint64_t u64CurTime = RTTimeMilliTS();
1009
1010 if (RT_UNLIKELY(u64CurTime > u64LastTime))
1011 {
1012 u64LastTime = u64CurTime;
1013 TMTimerPollVoid(pVM, pVCpu);
1014 }
1015 }
1016#endif
1017
1018 /* Check for pending actions that force us to go back to ring 3. */
1019#ifdef DEBUG
1020 /* Intercept X86_XCPT_DB if stepping is enabled */
1021 if (!DBGFIsStepping(pVCpu))
1022#endif
1023 {
1024 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
1025 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
1026 {
1027 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
1028 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
1029 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1030 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
1031 goto end;
1032 }
1033 }
1034
1035 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1036 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
1037 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1038 {
1039 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1040 rc = VINF_EM_PENDING_REQUEST;
1041 goto end;
1042 }
1043
1044#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1045 /*
1046 * Exit to ring-3 preemption/work is pending.
1047 *
1048 * Interrupts are disabled before the call to make sure we don't miss any interrupt
1049 * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
1050 * further down, but SVMR0CheckPendingInterrupt makes that impossible.)
1051 *
1052 * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
1053 * shootdowns rely on this.
1054 */
1055 uOldEFlags = ASMIntDisableFlags();
1056 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
1057 {
1058 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
1059 rc = VINF_EM_RAW_INTERRUPT;
1060 goto end;
1061 }
1062 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1063#endif
1064
1065 /* When external interrupts are pending, we should exit the VM when IF is set. */
1066 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
1067 rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
1068 if (RT_FAILURE(rc))
1069 {
1070 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1071 goto end;
1072 }
1073
1074 /* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
1075 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! (no longer true)
1076 * @todo query and update the TPR only when it could have been changed (mmio access)
1077 */
1078 if (pVM->hwaccm.s.fHasIoApic)
1079 {
1080 bool fPending;
1081
1082 /* TPR caching in CR8 */
1083 int rc = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
1084 AssertRC(rc);
1085
1086 if (pVM->hwaccm.s.fTPRPatchingActive)
1087 {
1088 /* Our patch code uses LSTAR for TPR caching. */
1089 pCtx->msrLSTAR = u8LastTPR;
1090
1091 if (fPending)
1092 {
1093 /* A TPR change could activate a pending interrupt, so catch lstar writes. */
1094 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, false);
1095 }
1096 else
1097 /* No interrupts are pending, so we don't need to be explicitely notified.
1098 * There are enough world switches for detecting pending interrupts.
1099 */
1100 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
1101 }
1102 else
1103 {
1104 pVMCB->ctrl.IntCtrl.n.u8VTPR = (u8LastTPR >> 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1105
1106 if (fPending)
1107 {
1108 /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
1109 pVMCB->ctrl.u16InterceptWrCRx |= RT_BIT(8);
1110 }
1111 else
1112 /* No interrupts are pending, so we don't need to be explicitely notified.
1113 * There are enough world switches for detecting pending interrupts.
1114 */
1115 pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1116 }
1117 fSyncTPR = !fPending;
1118 }
1119
1120 /* All done! Let's start VM execution. */
1121 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, x);
1122
1123 /* Enable nested paging if necessary (disabled each time after #VMEXIT). */
1124 pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
1125
1126#ifdef LOG_ENABLED
1127 pCpu = HWACCMR0GetCurrentCpu();
1128 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1129 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1130 {
1131 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
1132 LogFlow(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
1133 else
1134 LogFlow(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1135 }
1136 if (pCpu->fFlushTLB)
1137 LogFlow(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
1138#endif
1139
1140 /*
1141 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1142 * (until the actual world switch)
1143 */
1144#ifdef VBOX_STRICT
1145 idCpuCheck = RTMpCpuId();
1146#endif
1147 VMMR0LogFlushDisable(pVCpu);
1148
1149 /* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */
1150 rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
1151 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1152 {
1153 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1154 VMMR0LogFlushEnable(pVCpu);
1155 goto end;
1156 }
1157
1158#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1159 /* Disable interrupts to make sure a poke will interrupt execution.
1160 * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
1161 */
1162 uOldEFlags = ASMIntDisableFlags();
1163 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1164#endif
1165
1166 pCpu = HWACCMR0GetCurrentCpu();
1167 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1168 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1169 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1170 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1171 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1172 {
1173 /* Force a TLB flush on VM entry. */
1174 pVCpu->hwaccm.s.fForceTLBFlush = true;
1175 }
1176 else
1177 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1178
1179 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1180
1181 /** Set TLB flush state as checked until we return from the world switch. */
1182 ASMAtomicWriteU8(&pVCpu->hwaccm.s.fCheckedTLBFlush, true);
1183
1184 /* Check for tlb shootdown flushes. */
1185 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1186 pVCpu->hwaccm.s.fForceTLBFlush = true;
1187
1188 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1189 if ( pVCpu->hwaccm.s.fForceTLBFlush
1190 && !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
1191 {
1192 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1193 || pCpu->fFlushTLB)
1194 {
1195 pCpu->fFlushTLB = false;
1196 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1197 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
1198 pCpu->cTLBFlushes++;
1199 }
1200 else
1201 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1202
1203 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1204 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1205 }
1206 else
1207 {
1208 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1209
1210 /* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
1211 if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)
1212 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1213
1214 Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB || pVCpu->hwaccm.s.fForceTLBFlush);
1215 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
1216
1217 if ( !pVM->hwaccm.s.svm.fAlwaysFlushTLB
1218 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1219 {
1220 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1221 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1222 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1223 SVMR0InvlpgA(pVCpu->hwaccm.s.TlbShootdown.aPages[i], pVMCB->ctrl.TLBCtrl.n.u32ASID);
1224 }
1225 }
1226 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1227 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1228
1229 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1230 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1231 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1232 pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
1233
1234#ifdef VBOX_WITH_STATISTICS
1235 if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
1236 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1237 else
1238 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1239#endif
1240
1241 /* In case we execute a goto ResumeExecution later on. */
1242 pVCpu->hwaccm.s.fResumeVM = true;
1243 pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
1244
1245 Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
1246 Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
1247 Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
1248 Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVCpu->hwaccm.s.svm.pMSRBitmapPhys);
1249 Assert(pVMCB->ctrl.u64LBRVirt == 0);
1250
1251#ifdef VBOX_STRICT
1252 Assert(idCpuCheck == RTMpCpuId());
1253#endif
1254 TMNotifyStartOfExecution(pVCpu);
1255#ifdef VBOX_WITH_KERNEL_USING_XMM
1256 hwaccmR0SVMRunWrapXMM(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu, pVCpu->hwaccm.s.svm.pfnVMRun);
1257#else
1258 pVCpu->hwaccm.s.svm.pfnVMRun(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);
1259#endif
1260 ASMAtomicWriteU8(&pVCpu->hwaccm.s.fCheckedTLBFlush, false);
1261 ASMAtomicIncU32(&pVCpu->hwaccm.s.cWorldSwitchExit);
1262 /* Possibly the last TSC value seen by the guest (too high) (only when we're in tsc offset mode). */
1263 if (!(pVMCB->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
1264 TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVMCB->ctrl.u64TSCOffset - 0x400 /* guestimate of world switch overhead in clock ticks */);
1265 TMNotifyEndOfExecution(pVCpu);
1266 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
1267 ASMSetFlags(uOldEFlags);
1268#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1269 uOldEFlags = ~(RTCCUINTREG)0;
1270#endif
1271 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, x);
1272
1273 /*
1274 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1275 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1276 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1277 */
1278
1279 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, x);
1280
1281 /* Reason for the VM exit */
1282 exitCode = pVMCB->ctrl.u64ExitCode;
1283
1284 if (RT_UNLIKELY(exitCode == (uint64_t)SVM_EXIT_INVALID)) /* Invalid guest state. */
1285 {
1286 HWACCMDumpRegs(pVM, pVCpu, pCtx);
1287#ifdef DEBUG
1288 Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1289 Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1290 Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1291 Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1292 Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1293 Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1294 Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1295 Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1296 Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1297 Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
1298
1299 Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1300 Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1301 Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1302 Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1303
1304 Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1305 Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1306 Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1307 Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1308 Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1309 Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1310 Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1311 Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1312 Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1313 Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1314
1315 Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
1316 Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
1317 Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
1318 Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
1319 Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1320 Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1321 Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1322 Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1323 Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1324 Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1325 Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
1326 Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1327 Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1328 Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1329 Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1330 Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1331 Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1332
1333 Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1334 Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
1335
1336 Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1337 Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1338 Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1339 Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
1340 Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1341 Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1342 Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1343 Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
1344 Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1345 Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1346 Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1347 Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
1348 Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1349 Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1350 Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1351 Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
1352 Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1353 Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1354 Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1355 Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
1356
1357 Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1358 Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
1359
1360 Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1361 Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1362 Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1363 Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
1364
1365 Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1366 Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
1367
1368 Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1369 Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1370 Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1371 Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
1372
1373 Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1374 Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
1375 Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
1376 Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
1377 Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
1378 Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
1379 Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
1380
1381 Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
1382 Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
1383 Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
1384 Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
1385
1386 Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
1387 Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
1388 Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
1389
1390 Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
1391 Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
1392 Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
1393 Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
1394 Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
1395 Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
1396 Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
1397 Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
1398 Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
1399 Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
1400 Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
1401 Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
1402
1403#endif
1404 rc = VERR_SVM_UNABLE_TO_START_VM;
1405 VMMR0LogFlushEnable(pVCpu);
1406 goto end;
1407 }
1408
1409 /* Let's first sync back eip, esp, and eflags. */
1410 pCtx->rip = pVMCB->guest.u64RIP;
1411 pCtx->rsp = pVMCB->guest.u64RSP;
1412 pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1413 /* eax is saved/restore across the vmrun instruction */
1414 pCtx->rax = pVMCB->guest.u64RAX;
1415
1416 /* Save all the MSRs that can be changed by the guest without causing a world switch. (fs & gs base are saved with SVM_READ_SELREG) */
1417 pCtx->msrSTAR = pVMCB->guest.u64STAR; /* legacy syscall eip, cs & ss */
1418 pCtx->msrLSTAR = pVMCB->guest.u64LSTAR; /* 64 bits mode syscall rip */
1419 pCtx->msrCSTAR = pVMCB->guest.u64CSTAR; /* compatibility mode syscall rip */
1420 pCtx->msrSFMASK = pVMCB->guest.u64SFMASK; /* syscall flag mask */
1421 pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1422 pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1423 pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1424 pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1425
1426 /* Can be updated behind our back in the nested paging case. */
1427 pCtx->cr2 = pVMCB->guest.u64CR2;
1428
1429 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1430 SVM_READ_SELREG(SS, ss);
1431 SVM_READ_SELREG(CS, cs);
1432 SVM_READ_SELREG(DS, ds);
1433 SVM_READ_SELREG(ES, es);
1434 SVM_READ_SELREG(FS, fs);
1435 SVM_READ_SELREG(GS, gs);
1436
1437 /* Correct the hidden CS granularity flag. Haven't seen it being wrong in
1438 any other register (yet). */
1439 if ( !pCtx->csHid.Attr.n.u1Granularity
1440 && pCtx->csHid.Attr.n.u1Present
1441 && pCtx->csHid.u32Limit > UINT32_C(0xfffff))
1442 {
1443 Assert((pCtx->csHid.u32Limit & 0xfff) == 0xfff);
1444 pCtx->csHid.Attr.n.u1Granularity = 1;
1445 }
1446#define SVM_ASSERT_SEL_GRANULARITY(reg) \
1447 AssertMsg( !pCtx->reg##Hid.Attr.n.u1Present \
1448 || ( pCtx->reg##Hid.Attr.n.u1Granularity \
1449 ? (pCtx->reg##Hid.u32Limit & 0xfff) == 0xfff \
1450 : pCtx->reg##Hid.u32Limit <= 0xfffff), \
1451 ("%#x %#x %#llx\n", pCtx->reg##Hid.u32Limit, pCtx->reg##Hid.Attr.u, pCtx->reg##Hid.u64Base))
1452 SVM_ASSERT_SEL_GRANULARITY(ss);
1453 SVM_ASSERT_SEL_GRANULARITY(cs);
1454 SVM_ASSERT_SEL_GRANULARITY(ds);
1455 SVM_ASSERT_SEL_GRANULARITY(es);
1456 SVM_ASSERT_SEL_GRANULARITY(fs);
1457 SVM_ASSERT_SEL_GRANULARITY(gs);
1458#undef SVM_ASSERT_SEL_GRANULARITY
1459
1460 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1461 SVM_READ_SELREG(LDTR, ldtr);
1462 SVM_READ_SELREG(TR, tr);
1463
1464 pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1465 pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1466
1467 pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1468 pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1469
1470 /* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1471 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1472 if ( pVM->hwaccm.s.fNestedPaging
1473 && pCtx->cr3 != pVMCB->guest.u64CR3)
1474 {
1475 CPUMSetGuestCR3(pVCpu, pVMCB->guest.u64CR3);
1476 PGMUpdateCR3(pVCpu, pVMCB->guest.u64CR3);
1477 }
1478
1479 /* Note! NOW IT'S SAFE FOR LOGGING! */
1480 VMMR0LogFlushEnable(pVCpu);
1481
1482 /* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1483 if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1484 {
1485 Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
1486 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1487 }
1488 else
1489 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1490
1491 Log2(("exitCode = %x\n", exitCode));
1492
1493 /* Sync back DR6 as it could have been changed by hitting breakpoints. */
1494 pCtx->dr[6] = pVMCB->guest.u64DR6;
1495 /* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1496 pCtx->dr[7] = pVMCB->guest.u64DR7;
1497
1498 /* Check if an injected event was interrupted prematurely. */
1499 pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1500 if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1501 && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1502 {
1503 Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
1504
1505#ifdef LOG_ENABLED
1506 SVM_EVENT Event;
1507 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
1508
1509 if ( exitCode == SVM_EXIT_EXCEPTION_E
1510 && Event.n.u8Vector == 0xE)
1511 {
1512 Log(("Double fault!\n"));
1513 }
1514#endif
1515
1516 pVCpu->hwaccm.s.Event.fPending = true;
1517 /* Error code present? (redundant) */
1518 if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1519 pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1520 else
1521 pVCpu->hwaccm.s.Event.errCode = 0;
1522 }
1523#ifdef VBOX_WITH_STATISTICS
1524 if (exitCode == SVM_EXIT_NPF)
1525 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
1526 else
1527 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1528#endif
1529
1530 /* Sync back the TPR if it was changed. */
1531 if (fSyncTPR)
1532 {
1533 if (pVM->hwaccm.s.fTPRPatchingActive)
1534 {
1535 if ((pCtx->msrLSTAR & 0xff) != u8LastTPR)
1536 {
1537 /* Our patch code uses LSTAR for TPR caching. */
1538 rc = PDMApicSetTPR(pVCpu, pCtx->msrLSTAR & 0xff);
1539 AssertRC(rc);
1540 }
1541 }
1542 else
1543 {
1544 if ((u8LastTPR >> 4) != pVMCB->ctrl.IntCtrl.n.u8VTPR)
1545 {
1546 rc = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1547 AssertRC(rc);
1548 }
1549 }
1550 }
1551
1552 /* Deal with the reason of the VM-exit. */
1553 switch (exitCode)
1554 {
1555 case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1556 case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1557 case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1558 case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1559 case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1560 case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1561 case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1562 case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1563 {
1564 /* Pending trap. */
1565 SVM_EVENT Event;
1566 uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1567
1568 Log2(("Hardware/software interrupt %d\n", vector));
1569 switch (vector)
1570 {
1571 case X86_XCPT_DB:
1572 {
1573 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
1574
1575 /* Note that we don't support guest and host-initiated debugging at the same time. */
1576 Assert(DBGFIsStepping(pVCpu) || CPUMIsHyperDebugStateActive(pVCpu));
1577
1578 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1579 if (rc == VINF_EM_RAW_GUEST_TRAP)
1580 {
1581 Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
1582
1583 /* Reinject the exception. */
1584 Event.au64[0] = 0;
1585 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1586 Event.n.u1Valid = 1;
1587 Event.n.u8Vector = X86_XCPT_DB;
1588
1589 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1590
1591 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1592 goto ResumeExecution;
1593 }
1594 /* Return to ring 3 to deal with the debug exit code. */
1595 Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
1596 break;
1597 }
1598
1599 case X86_XCPT_NM:
1600 {
1601 Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
1602
1603 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1604 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1605 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
1606 if (rc == VINF_SUCCESS)
1607 {
1608 Assert(CPUMIsGuestFPUStateActive(pVCpu));
1609 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
1610
1611 /* Continue execution. */
1612 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1613 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1614
1615 goto ResumeExecution;
1616 }
1617
1618 Log(("Forward #NM fault to the guest\n"));
1619 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
1620
1621 Event.au64[0] = 0;
1622 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1623 Event.n.u1Valid = 1;
1624 Event.n.u8Vector = X86_XCPT_NM;
1625
1626 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1627 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1628 goto ResumeExecution;
1629 }
1630
1631 case X86_XCPT_PF: /* Page fault */
1632 {
1633 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1634 RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1635
1636#ifdef DEBUG
1637 if (pVM->hwaccm.s.fNestedPaging)
1638 { /* A genuine pagefault.
1639 * Forward the trap to the guest by injecting the exception and resuming execution.
1640 */
1641 Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1642 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1643
1644 /* Now we must update CR2. */
1645 pCtx->cr2 = uFaultAddress;
1646
1647 Event.au64[0] = 0;
1648 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1649 Event.n.u1Valid = 1;
1650 Event.n.u8Vector = X86_XCPT_PF;
1651 Event.n.u1ErrorCodeValid = 1;
1652 Event.n.u32ErrorCode = errCode;
1653
1654 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1655
1656 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1657 goto ResumeExecution;
1658 }
1659#endif
1660 Assert(!pVM->hwaccm.s.fNestedPaging);
1661
1662#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1663 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1664 if ( pVM->hwaccm.s.fTRPPatchingAllowed
1665 && (uFaultAddress & 0xfff) == 0x080
1666 && !(errCode & X86_TRAP_PF_P) /* not present */
1667 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1668 && !CPUMIsGuestInLongModeEx(pCtx)
1669 && pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1670 {
1671 RTGCPHYS GCPhysApicBase, GCPhys;
1672 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1673 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1674
1675 rc = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL, &GCPhys);
1676 if ( rc == VINF_SUCCESS
1677 && GCPhys == GCPhysApicBase)
1678 {
1679 /* Only attempt to patch the instruction once. */
1680 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1681 if (!pPatch)
1682 {
1683 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1684 break;
1685 }
1686 }
1687 }
1688#endif
1689
1690 Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1691 /* Exit qualification contains the linear address of the page fault. */
1692 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1693 TRPMSetErrorCode(pVCpu, errCode);
1694 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1695
1696 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1697 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1698 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1699 if (rc == VINF_SUCCESS)
1700 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1701 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1702 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1703
1704 TRPMResetTrap(pVCpu);
1705
1706 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1707 goto ResumeExecution;
1708 }
1709 else
1710 if (rc == VINF_EM_RAW_GUEST_TRAP)
1711 { /* A genuine pagefault.
1712 * Forward the trap to the guest by injecting the exception and resuming execution.
1713 */
1714 Log2(("Forward page fault to the guest\n"));
1715 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1716 /* The error code might have been changed. */
1717 errCode = TRPMGetErrorCode(pVCpu);
1718
1719 TRPMResetTrap(pVCpu);
1720
1721 /* Now we must update CR2. */
1722 pCtx->cr2 = uFaultAddress;
1723
1724 Event.au64[0] = 0;
1725 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1726 Event.n.u1Valid = 1;
1727 Event.n.u8Vector = X86_XCPT_PF;
1728 Event.n.u1ErrorCodeValid = 1;
1729 Event.n.u32ErrorCode = errCode;
1730
1731 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1732
1733 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1734 goto ResumeExecution;
1735 }
1736#ifdef VBOX_STRICT
1737 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
1738 LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1739#endif
1740 /* Need to go back to the recompiler to emulate the instruction. */
1741 TRPMResetTrap(pVCpu);
1742 break;
1743 }
1744
1745 case X86_XCPT_MF: /* Floating point exception. */
1746 {
1747 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
1748 if (!(pCtx->cr0 & X86_CR0_NE))
1749 {
1750 /* old style FPU error reporting needs some extra work. */
1751 /** @todo don't fall back to the recompiler, but do it manually. */
1752 rc = VINF_EM_RAW_EMULATE_INSTR;
1753 break;
1754 }
1755 Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
1756
1757 Event.au64[0] = 0;
1758 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1759 Event.n.u1Valid = 1;
1760 Event.n.u8Vector = X86_XCPT_MF;
1761
1762 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1763
1764 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1765 goto ResumeExecution;
1766 }
1767
1768#ifdef VBOX_STRICT
1769 case X86_XCPT_GP: /* General protection failure exception.*/
1770 case X86_XCPT_UD: /* Unknown opcode exception. */
1771 case X86_XCPT_DE: /* Divide error. */
1772 case X86_XCPT_SS: /* Stack segment exception. */
1773 case X86_XCPT_NP: /* Segment not present exception. */
1774 {
1775 Event.au64[0] = 0;
1776 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1777 Event.n.u1Valid = 1;
1778 Event.n.u8Vector = vector;
1779
1780 switch(vector)
1781 {
1782 case X86_XCPT_GP:
1783 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
1784 Event.n.u1ErrorCodeValid = 1;
1785 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1786 break;
1787 case X86_XCPT_DE:
1788 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
1789 break;
1790 case X86_XCPT_UD:
1791 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
1792 break;
1793 case X86_XCPT_SS:
1794 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
1795 Event.n.u1ErrorCodeValid = 1;
1796 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1797 break;
1798 case X86_XCPT_NP:
1799 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
1800 Event.n.u1ErrorCodeValid = 1;
1801 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1802 break;
1803 }
1804 Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->esi));
1805 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1806
1807 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1808 goto ResumeExecution;
1809 }
1810#endif
1811 default:
1812 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1813 rc = VERR_EM_INTERNAL_ERROR;
1814 break;
1815
1816 } /* switch (vector) */
1817 break;
1818 }
1819
1820 case SVM_EXIT_NPF:
1821 {
1822 /* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1823 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1824 RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1825 PGMMODE enmShwPagingMode;
1826
1827 Assert(pVM->hwaccm.s.fNestedPaging);
1828 LogFlow(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1829
1830#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1831 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1832 if ( pVM->hwaccm.s.fTRPPatchingAllowed
1833 && (uFaultAddress & 0xfff) == 0x080
1834 && !(errCode & X86_TRAP_PF_P) /* not present */
1835 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1836 && !CPUMIsGuestInLongModeEx(pCtx)
1837 && pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches))
1838 {
1839 RTGCPHYS GCPhysApicBase;
1840 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1841 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1842
1843 if (uFaultAddress == GCPhysApicBase + 0x80)
1844 {
1845 /* Only attempt to patch the instruction once. */
1846 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1847 if (!pPatch)
1848 {
1849 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1850 break;
1851 }
1852 }
1853 }
1854#endif
1855
1856 /* Exit qualification contains the linear address of the page fault. */
1857 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1858 TRPMSetErrorCode(pVCpu, errCode);
1859 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1860
1861 /* Handle the pagefault trap for the nested shadow table. */
1862#if HC_ARCH_BITS == 32
1863 if (CPUMIsGuestInLongModeEx(pCtx))
1864 enmShwPagingMode = PGMMODE_AMD64_NX;
1865 else
1866#endif
1867 enmShwPagingMode = PGMGetHostMode(pVM);
1868
1869 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1870 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1871 if (rc == VINF_SUCCESS)
1872 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1873 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1874 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1875
1876 TRPMResetTrap(pVCpu);
1877
1878 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1879 goto ResumeExecution;
1880 }
1881
1882#ifdef VBOX_STRICT
1883 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1884 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1885#endif
1886 /* Need to go back to the recompiler to emulate the instruction. */
1887 TRPMResetTrap(pVCpu);
1888 break;
1889 }
1890
1891 case SVM_EXIT_VINTR:
1892 /* A virtual interrupt is about to be delivered, which means IF=1. */
1893 Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1894 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1895 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1896 goto ResumeExecution;
1897
1898 case SVM_EXIT_FERR_FREEZE:
1899 case SVM_EXIT_INTR:
1900 case SVM_EXIT_NMI:
1901 case SVM_EXIT_SMI:
1902 case SVM_EXIT_INIT:
1903 /* External interrupt; leave to allow it to be dispatched again. */
1904 rc = VINF_EM_RAW_INTERRUPT;
1905 break;
1906
1907 case SVM_EXIT_WBINVD:
1908 case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1909 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
1910 /* Skip instruction and continue directly. */
1911 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1912 /* Continue execution.*/
1913 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1914 goto ResumeExecution;
1915
1916 case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1917 {
1918 Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
1919 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
1920 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1921 if (rc == VINF_SUCCESS)
1922 {
1923 /* Update EIP and continue execution. */
1924 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1925 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1926 goto ResumeExecution;
1927 }
1928 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
1929 rc = VINF_EM_RAW_EMULATE_INSTR;
1930 break;
1931 }
1932
1933 case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1934 {
1935 Log2(("SVM: Rdtsc\n"));
1936 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1937 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1938 if (rc == VINF_SUCCESS)
1939 {
1940 /* Update EIP and continue execution. */
1941 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1942 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1943 goto ResumeExecution;
1944 }
1945 rc = VINF_EM_RAW_EMULATE_INSTR;
1946 break;
1947 }
1948
1949 case SVM_EXIT_RDPMC: /* Guest software attempted to execute RDPMC. */
1950 {
1951 Log2(("SVM: Rdpmc %x\n", pCtx->ecx));
1952 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
1953 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1954 if (rc == VINF_SUCCESS)
1955 {
1956 /* Update EIP and continue execution. */
1957 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1958 goto ResumeExecution;
1959 }
1960 rc = VINF_EM_RAW_EMULATE_INSTR;
1961 break;
1962 }
1963
1964 case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
1965 {
1966 Log2(("SVM: Rdtscp\n"));
1967 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1968 rc = EMInterpretRdtscp(pVM, pVCpu, pCtx);
1969 if (rc == VINF_SUCCESS)
1970 {
1971 /* Update EIP and continue execution. */
1972 pCtx->rip += 3; /* Note! hardcoded opcode size! */
1973 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1974 goto ResumeExecution;
1975 }
1976 AssertMsgFailed(("EMU: rdtscp failed with %Rrc\n", rc));
1977 rc = VINF_EM_RAW_EMULATE_INSTR;
1978 break;
1979 }
1980
1981 case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1982 {
1983 Log2(("SVM: invlpg\n"));
1984 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
1985
1986 Assert(!pVM->hwaccm.s.fNestedPaging);
1987
1988 /* Truly a pita. Why can't SVM give the same information as VT-x? */
1989 rc = svmR0InterpretInvpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1990 if (rc == VINF_SUCCESS)
1991 {
1992 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageInvlpg);
1993 goto ResumeExecution; /* eip already updated */
1994 }
1995 break;
1996 }
1997
1998 case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1999 case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
2000 case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
2001 case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
2002 {
2003 uint32_t cbSize;
2004
2005 Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
2006 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[exitCode - SVM_EXIT_WRITE_CR0]);
2007 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2008
2009 switch (exitCode - SVM_EXIT_WRITE_CR0)
2010 {
2011 case 0:
2012 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
2013 break;
2014 case 2:
2015 break;
2016 case 3:
2017 Assert(!pVM->hwaccm.s.fNestedPaging);
2018 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
2019 break;
2020 case 4:
2021 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
2022 break;
2023 case 8:
2024 break;
2025 default:
2026 AssertFailed();
2027 }
2028 /* Check if a sync operation is pending. */
2029 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
2030 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2031 {
2032 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2033 AssertRC(rc);
2034
2035 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBCRxChange);
2036
2037 /* Must be set by PGMSyncCR3 */
2038 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || PGMGetGuestMode(pVCpu) <= PGMMODE_PROTECTED || pVCpu->hwaccm.s.fForceTLBFlush,
2039 ("rc=%Rrc mode=%d fForceTLBFlush=%RTbool\n", rc, PGMGetGuestMode(pVCpu), pVCpu->hwaccm.s.fForceTLBFlush));
2040 }
2041 if (rc == VINF_SUCCESS)
2042 {
2043 /* EIP has been updated already. */
2044
2045 /* Only resume if successful. */
2046 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2047 goto ResumeExecution;
2048 }
2049 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2050 break;
2051 }
2052
2053 case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
2054 case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
2055 case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
2056 case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
2057 {
2058 uint32_t cbSize;
2059
2060 Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
2061 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[exitCode - SVM_EXIT_READ_CR0]);
2062 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2063 if (rc == VINF_SUCCESS)
2064 {
2065 /* EIP has been updated already. */
2066
2067 /* Only resume if successful. */
2068 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2069 goto ResumeExecution;
2070 }
2071 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2072 break;
2073 }
2074
2075 case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
2076 case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
2077 case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
2078 case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
2079 {
2080 uint32_t cbSize;
2081
2082 Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
2083 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
2084
2085 if ( !DBGFIsStepping(pVCpu)
2086 && !CPUMIsHyperDebugStateActive(pVCpu))
2087 {
2088 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2089
2090 /* Disable drx move intercepts. */
2091 pVMCB->ctrl.u16InterceptRdDRx = 0;
2092 pVMCB->ctrl.u16InterceptWrDRx = 0;
2093
2094 /* Save the host and load the guest debug state. */
2095 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2096 AssertRC(rc);
2097
2098 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2099 goto ResumeExecution;
2100 }
2101
2102 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2103 if (rc == VINF_SUCCESS)
2104 {
2105 /* EIP has been updated already. */
2106 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2107
2108 /* Only resume if successful. */
2109 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2110 goto ResumeExecution;
2111 }
2112 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2113 break;
2114 }
2115
2116 case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
2117 case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
2118 case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
2119 case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
2120 {
2121 uint32_t cbSize;
2122
2123 Log2(("SVM: %RGv mov x, dr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
2124 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2125
2126 if (!DBGFIsStepping(pVCpu))
2127 {
2128 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2129
2130 /* Disable drx move intercepts. */
2131 pVMCB->ctrl.u16InterceptRdDRx = 0;
2132 pVMCB->ctrl.u16InterceptWrDRx = 0;
2133
2134 /* Save the host and load the guest debug state. */
2135 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2136 AssertRC(rc);
2137
2138 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2139 goto ResumeExecution;
2140 }
2141
2142 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2143 if (rc == VINF_SUCCESS)
2144 {
2145 /* EIP has been updated already. */
2146
2147 /* Only resume if successful. */
2148 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2149 goto ResumeExecution;
2150 }
2151 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2152 break;
2153 }
2154
2155 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2156 case SVM_EXIT_IOIO: /* I/O instruction. */
2157 {
2158 SVM_IOIO_EXIT IoExitInfo;
2159 uint32_t uIOSize, uAndVal;
2160
2161 IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
2162
2163 /** @todo could use a lookup table here */
2164 if (IoExitInfo.n.u1OP8)
2165 {
2166 uIOSize = 1;
2167 uAndVal = 0xff;
2168 }
2169 else
2170 if (IoExitInfo.n.u1OP16)
2171 {
2172 uIOSize = 2;
2173 uAndVal = 0xffff;
2174 }
2175 else
2176 if (IoExitInfo.n.u1OP32)
2177 {
2178 uIOSize = 4;
2179 uAndVal = 0xffffffff;
2180 }
2181 else
2182 {
2183 AssertFailed(); /* should be fatal. */
2184 rc = VINF_EM_RAW_EMULATE_INSTR;
2185 break;
2186 }
2187
2188 if (IoExitInfo.n.u1STR)
2189 {
2190 /* ins/outs */
2191 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2192
2193 /* Disassemble manually to deal with segment prefixes. */
2194 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
2195 if (rc == VINF_SUCCESS)
2196 {
2197 if (IoExitInfo.n.u1Type == 0)
2198 {
2199 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2200 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
2201 rc = VBOXSTRICTRC_TODO(IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize));
2202 }
2203 else
2204 {
2205 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2206 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
2207 rc = VBOXSTRICTRC_TODO(IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize));
2208 }
2209 }
2210 else
2211 rc = VINF_EM_RAW_EMULATE_INSTR;
2212 }
2213 else
2214 {
2215 /* normal in/out */
2216 Assert(!IoExitInfo.n.u1REP);
2217
2218 if (IoExitInfo.n.u1Type == 0)
2219 {
2220 Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2221 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
2222 rc = VBOXSTRICTRC_TODO(IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2223 if (rc == VINF_IOM_HC_IOPORT_WRITE)
2224 HWACCMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2225 }
2226 else
2227 {
2228 uint32_t u32Val = 0;
2229
2230 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
2231 rc = VBOXSTRICTRC_TODO(IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize));
2232 if (IOM_SUCCESS(rc))
2233 {
2234 /* Write back to the EAX register. */
2235 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2236 Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
2237 }
2238 else
2239 if (rc == VINF_IOM_HC_IOPORT_READ)
2240 HWACCMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2241 }
2242 }
2243 /*
2244 * Handled the I/O return codes.
2245 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2246 */
2247 if (IOM_SUCCESS(rc))
2248 {
2249 /* Update EIP and continue execution. */
2250 pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
2251 if (RT_LIKELY(rc == VINF_SUCCESS))
2252 {
2253 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2254 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2255 {
2256 /* IO operation lookup arrays. */
2257 static uint32_t const aIOSize[4] = {1, 2, 0, 4};
2258
2259 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
2260 for (unsigned i=0;i<4;i++)
2261 {
2262 unsigned uBPLen = aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2263
2264 if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
2265 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
2266 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2267 {
2268 SVM_EVENT Event;
2269
2270 Assert(CPUMIsGuestDebugStateActive(pVCpu));
2271
2272 /* Clear all breakpoint status flags and set the one we just hit. */
2273 pCtx->dr[6] &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
2274 pCtx->dr[6] |= (uint64_t)RT_BIT(i);
2275
2276 /* Note: AMD64 Architecture Programmer's Manual 13.1:
2277 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2278 * the contents have been read.
2279 */
2280 pVMCB->guest.u64DR6 = pCtx->dr[6];
2281
2282 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2283 pCtx->dr[7] &= ~X86_DR7_GD;
2284
2285 /* Paranoia. */
2286 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2287 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2288 pCtx->dr[7] |= 0x400; /* must be one */
2289
2290 pVMCB->guest.u64DR7 = pCtx->dr[7];
2291
2292 /* Inject the exception. */
2293 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
2294
2295 Event.au64[0] = 0;
2296 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
2297 Event.n.u1Valid = 1;
2298 Event.n.u8Vector = X86_XCPT_DB;
2299
2300 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2301
2302 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2303 goto ResumeExecution;
2304 }
2305 }
2306 }
2307
2308 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2309 goto ResumeExecution;
2310 }
2311 Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
2312 break;
2313 }
2314
2315#ifdef VBOX_STRICT
2316 if (rc == VINF_IOM_HC_IOPORT_READ)
2317 Assert(IoExitInfo.n.u1Type != 0);
2318 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2319 Assert(IoExitInfo.n.u1Type == 0);
2320 else
2321 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
2322#endif
2323 Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2324 break;
2325 }
2326
2327 case SVM_EXIT_HLT:
2328 /** Check if external interrupts are pending; if so, don't switch back. */
2329 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2330 pCtx->rip++; /* skip hlt */
2331 if ( pCtx->eflags.Bits.u1IF
2332 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
2333 goto ResumeExecution;
2334
2335 rc = VINF_EM_HALT;
2336 break;
2337
2338 case SVM_EXIT_MWAIT_UNCOND:
2339 Log2(("SVM: mwait\n"));
2340 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
2341 rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2342 if ( rc == VINF_EM_HALT
2343 || rc == VINF_SUCCESS)
2344 {
2345 /* Update EIP and continue execution. */
2346 pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2347
2348 /** Check if external interrupts are pending; if so, don't switch back. */
2349 if ( rc == VINF_SUCCESS
2350 || ( rc == VINF_EM_HALT
2351 && pCtx->eflags.Bits.u1IF
2352 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
2353 )
2354 goto ResumeExecution;
2355 }
2356 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
2357 break;
2358
2359 case SVM_EXIT_VMMCALL:
2360 rc = svmR0EmulateTprVMMCall(pVM, pVCpu, pCtx);
2361 if (rc == VINF_SUCCESS)
2362 {
2363 goto ResumeExecution; /* rip already updated. */
2364 }
2365 /* no break */
2366
2367 case SVM_EXIT_RSM:
2368 case SVM_EXIT_INVLPGA:
2369 case SVM_EXIT_VMRUN:
2370 case SVM_EXIT_VMLOAD:
2371 case SVM_EXIT_VMSAVE:
2372 case SVM_EXIT_STGI:
2373 case SVM_EXIT_CLGI:
2374 case SVM_EXIT_SKINIT:
2375 {
2376 /* Unsupported instructions. */
2377 SVM_EVENT Event;
2378
2379 Event.au64[0] = 0;
2380 Event.n.u3Type = SVM_EVENT_EXCEPTION;
2381 Event.n.u1Valid = 1;
2382 Event.n.u8Vector = X86_XCPT_UD;
2383
2384 Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
2385 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2386
2387 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2388 goto ResumeExecution;
2389 }
2390
2391 /* Emulate in ring 3. */
2392 case SVM_EXIT_MSR:
2393 {
2394 uint32_t cbSize;
2395
2396 /* When an interrupt is pending, we'll let MSR_K8_LSTAR writes fault in our TPR patch code. */
2397 if ( pVM->hwaccm.s.fTPRPatchingActive
2398 && pCtx->ecx == MSR_K8_LSTAR
2399 && pVMCB->ctrl.u64ExitInfo1 == 1 /* wrmsr */)
2400 {
2401 if ((pCtx->eax & 0xff) != u8LastTPR)
2402 {
2403 Log(("SVM: Faulting MSR_K8_LSTAR write with new TPR value %x\n", pCtx->eax & 0xff));
2404
2405 /* Our patch code uses LSTAR for TPR caching. */
2406 rc = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
2407 AssertRC(rc);
2408 }
2409
2410 /* Skip the instruction and continue. */
2411 pCtx->rip += 2; /* wrmsr = [0F 30] */
2412
2413 /* Only resume if successful. */
2414 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2415 goto ResumeExecution;
2416 }
2417
2418 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2419 STAM_COUNTER_INC((pVMCB->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
2420 Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
2421 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2422 if (rc == VINF_SUCCESS)
2423 {
2424 /* EIP has been updated already. */
2425
2426 /* Only resume if successful. */
2427 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2428 goto ResumeExecution;
2429 }
2430 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
2431 break;
2432 }
2433
2434 case SVM_EXIT_TASK_SWITCH: /* too complicated to emulate, so fall back to the recompiler*/
2435 Log(("SVM_EXIT_TASK_SWITCH: exit2=%RX64\n", pVMCB->ctrl.u64ExitInfo2));
2436 if ( !(pVMCB->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET | SVM_EXIT2_TASK_SWITCH_JMP))
2437 && pVCpu->hwaccm.s.Event.fPending)
2438 {
2439 SVM_EVENT Event;
2440
2441 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
2442
2443 /* Caused by an injected interrupt. */
2444 pVCpu->hwaccm.s.Event.fPending = false;
2445
2446 switch (Event.n.u3Type)
2447 {
2448 case SVM_EVENT_EXTERNAL_IRQ:
2449 case SVM_EVENT_NMI:
2450 Log(("SVM_EXIT_TASK_SWITCH: reassert trap %d\n", Event.n.u8Vector));
2451 Assert(!Event.n.u1ErrorCodeValid);
2452 rc = TRPMAssertTrap(pVCpu, Event.n.u8Vector, TRPM_HARDWARE_INT);
2453 AssertRC(rc);
2454 break;
2455
2456 default:
2457 /* Exceptions and software interrupts can just be restarted. */
2458 break;
2459 }
2460 }
2461 rc = VERR_EM_INTERPRETER;
2462 break;
2463
2464 case SVM_EXIT_MONITOR:
2465 case SVM_EXIT_PAUSE:
2466 case SVM_EXIT_MWAIT_ARMED:
2467 rc = VERR_EM_INTERPRETER;
2468 break;
2469
2470 case SVM_EXIT_SHUTDOWN:
2471 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2472 break;
2473
2474 case SVM_EXIT_IDTR_READ:
2475 case SVM_EXIT_GDTR_READ:
2476 case SVM_EXIT_LDTR_READ:
2477 case SVM_EXIT_TR_READ:
2478 case SVM_EXIT_IDTR_WRITE:
2479 case SVM_EXIT_GDTR_WRITE:
2480 case SVM_EXIT_LDTR_WRITE:
2481 case SVM_EXIT_TR_WRITE:
2482 case SVM_EXIT_CR0_SEL_WRITE:
2483 default:
2484 /* Unexpected exit codes. */
2485 rc = VERR_EM_INTERNAL_ERROR;
2486 AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2487 break;
2488 }
2489
2490end:
2491
2492 /* Signal changes for the recompiler. */
2493 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2494
2495 /* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
2496 if (exitCode == SVM_EXIT_INTR)
2497 {
2498 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
2499 /* On the next entry we'll only sync the host context. */
2500 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2501 }
2502 else
2503 {
2504 /* On the next entry we'll sync everything. */
2505 /** @todo we can do better than this */
2506 /* Not in the VINF_PGM_CHANGE_MODE though! */
2507 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2508 }
2509
2510 /* translate into a less severe return code */
2511 if (rc == VERR_EM_INTERPRETER)
2512 rc = VINF_EM_RAW_EMULATE_INSTR;
2513
2514 /* Just set the correct state here instead of trying to catch every goto above. */
2515 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
2516
2517#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2518 /* Restore interrupts if we exitted after disabling them. */
2519 if (uOldEFlags != ~(RTCCUINTREG)0)
2520 ASMSetFlags(uOldEFlags);
2521#endif
2522
2523 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2524 return rc;
2525}
2526
2527/**
2528 * Emulate simple mov tpr instruction
2529 *
2530 * @returns VBox status code.
2531 * @param pVM The VM to operate on.
2532 * @param pVCpu The VM CPU to operate on.
2533 * @param pCtx CPU context
2534 */
2535static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2536{
2537 int rc;
2538
2539 LogFlow(("Emulated VMMCall TPR access replacement at %RGv\n", pCtx->rip));
2540
2541 while (true)
2542 {
2543 bool fPending;
2544 uint8_t u8Tpr;
2545
2546 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2547 if (!pPatch)
2548 break;
2549
2550 switch(pPatch->enmType)
2551 {
2552 case HWACCMTPRINSTR_READ:
2553 /* TPR caching in CR8 */
2554 rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending);
2555 AssertRC(rc);
2556
2557 rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
2558 AssertRC(rc);
2559
2560 LogFlow(("Emulated read successfully\n"));
2561 pCtx->rip += pPatch->cbOp;
2562 break;
2563
2564 case HWACCMTPRINSTR_WRITE_REG:
2565 case HWACCMTPRINSTR_WRITE_IMM:
2566 /* Fetch the new TPR value */
2567 if (pPatch->enmType == HWACCMTPRINSTR_WRITE_REG)
2568 {
2569 uint32_t val;
2570
2571 rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &val);
2572 AssertRC(rc);
2573 u8Tpr = val;
2574 }
2575 else
2576 u8Tpr = (uint8_t)pPatch->uSrcOperand;
2577
2578 rc = PDMApicSetTPR(pVCpu, u8Tpr);
2579 AssertRC(rc);
2580 LogFlow(("Emulated write successfully\n"));
2581 pCtx->rip += pPatch->cbOp;
2582 break;
2583 default:
2584 AssertMsgFailedReturn(("Unexpected type %d\n", pPatch->enmType), VERR_INTERNAL_ERROR);
2585 }
2586 }
2587 return VINF_SUCCESS;
2588}
2589
2590
2591/**
2592 * Enters the AMD-V session
2593 *
2594 * @returns VBox status code.
2595 * @param pVM The VM to operate on.
2596 * @param pVCpu The VM CPU to operate on.
2597 * @param pCpu CPU info struct
2598 */
2599VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
2600{
2601 Assert(pVM->hwaccm.s.svm.fSupported);
2602
2603 LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
2604 pVCpu->hwaccm.s.fResumeVM = false;
2605
2606 /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2607 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_LDTR;
2608
2609 return VINF_SUCCESS;
2610}
2611
2612
2613/**
2614 * Leaves the AMD-V session
2615 *
2616 * @returns VBox status code.
2617 * @param pVM The VM to operate on.
2618 * @param pVCpu The VM CPU to operate on.
2619 * @param pCtx CPU context
2620 */
2621VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2622{
2623 SVM_VMCB *pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2624
2625 Assert(pVM->hwaccm.s.svm.fSupported);
2626
2627#ifdef DEBUG
2628 if (CPUMIsHyperDebugStateActive(pVCpu))
2629 {
2630 CPUMR0LoadHostDebugState(pVM, pVCpu);
2631 }
2632 else
2633#endif
2634 /* Save the guest debug state if necessary. */
2635 if (CPUMIsGuestDebugStateActive(pVCpu))
2636 {
2637 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
2638
2639 /* Intercept all DRx reads and writes again. Changed later on. */
2640 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
2641 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
2642
2643 /* Resync the debug registers the next time. */
2644 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2645 }
2646 else
2647 Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
2648
2649 return VINF_SUCCESS;
2650}
2651
2652
2653static int svmR0InterpretInvlPg(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2654{
2655 OP_PARAMVAL param1;
2656 RTGCPTR addr;
2657
2658 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2659 if(RT_FAILURE(rc))
2660 return VERR_EM_INTERPRETER;
2661
2662 switch(param1.type)
2663 {
2664 case PARMTYPE_IMMEDIATE:
2665 case PARMTYPE_ADDRESS:
2666 if(!(param1.flags & (PARAM_VAL32|PARAM_VAL64)))
2667 return VERR_EM_INTERPRETER;
2668 addr = param1.val.val64;
2669 break;
2670
2671 default:
2672 return VERR_EM_INTERPRETER;
2673 }
2674
2675 /** @todo is addr always a flat linear address or ds based
2676 * (in absence of segment override prefixes)????
2677 */
2678 rc = PGMInvalidatePage(pVCpu, addr);
2679 if (RT_SUCCESS(rc))
2680 {
2681 /* Manually invalidate the page for the VM's TLB. */
2682 Log(("SVMR0InvlpgA %RGv ASID=%d\n", addr, uASID));
2683 SVMR0InvlpgA(addr, uASID);
2684 return VINF_SUCCESS;
2685 }
2686 AssertRC(rc);
2687 return rc;
2688}
2689
2690/**
2691 * Interprets INVLPG
2692 *
2693 * @returns VBox status code.
2694 * @retval VINF_* Scheduling instructions.
2695 * @retval VERR_EM_INTERPRETER Something we can't cope with.
2696 * @retval VERR_* Fatal errors.
2697 *
2698 * @param pVM The VM handle.
2699 * @param pRegFrame The register frame.
2700 * @param ASID Tagged TLB id for the guest
2701 *
2702 * Updates the EIP if an instruction was executed successfully.
2703 */
2704static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2705{
2706 /*
2707 * Only allow 32 & 64 bits code.
2708 */
2709 DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2710 if (enmMode != CPUMODE_16BIT)
2711 {
2712 RTGCPTR pbCode;
2713 int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2714 if (RT_SUCCESS(rc))
2715 {
2716 uint32_t cbOp;
2717 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2718
2719 pDis->mode = enmMode;
2720 rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, pDis, &cbOp);
2721 Assert(RT_FAILURE(rc) || pDis->pCurInstr->opcode == OP_INVLPG);
2722 if (RT_SUCCESS(rc) && pDis->pCurInstr->opcode == OP_INVLPG)
2723 {
2724 Assert(cbOp == pDis->opsize);
2725 rc = svmR0InterpretInvlPg(pVCpu, pDis, pRegFrame, uASID);
2726 if (RT_SUCCESS(rc))
2727 {
2728 pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2729 }
2730 return rc;
2731 }
2732 }
2733 }
2734 return VERR_EM_INTERPRETER;
2735}
2736
2737
2738/**
2739 * Invalidates a guest page
2740 *
2741 * @returns VBox status code.
2742 * @param pVM The VM to operate on.
2743 * @param pVCpu The VM CPU to operate on.
2744 * @param GCVirt Page to invalidate
2745 */
2746VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
2747{
2748 bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB | VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH);
2749
2750 /* Skip it if a TLB flush is already pending. */
2751 if (!fFlushPending)
2752 {
2753 SVM_VMCB *pVMCB;
2754
2755 Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
2756 AssertReturn(pVM, VERR_INVALID_PARAMETER);
2757 Assert(pVM->hwaccm.s.svm.fSupported);
2758
2759 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2760 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2761
2762#if HC_ARCH_BITS == 32
2763 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
2764 if (CPUMIsGuestInLongMode(pVCpu))
2765 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2766 else
2767#endif
2768 SVMR0InvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2769 }
2770 return VINF_SUCCESS;
2771}
2772
2773
2774#if 0 /* obsolete, but left here for clarification. */
2775/**
2776 * Invalidates a guest page by physical address
2777 *
2778 * @returns VBox status code.
2779 * @param pVM The VM to operate on.
2780 * @param pVCpu The VM CPU to operate on.
2781 * @param GCPhys Page to invalidate
2782 */
2783VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
2784{
2785 Assert(pVM->hwaccm.s.fNestedPaging);
2786 /* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
2787 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2788 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBInvlpga);
2789 return VINF_SUCCESS;
2790}
2791#endif
2792
2793#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2794/**
2795 * Prepares for and executes VMRUN (64 bits guests from a 32 bits hosts).
2796 *
2797 * @returns VBox status code.
2798 * @param pVMCBHostPhys Physical address of host VMCB.
2799 * @param pVMCBPhys Physical address of the VMCB.
2800 * @param pCtx Guest context.
2801 * @param pVM The VM to operate on.
2802 * @param pVCpu The VMCPU to operate on.
2803 */
2804DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
2805{
2806 uint32_t aParam[4];
2807
2808 aParam[0] = (uint32_t)(pVMCBHostPhys); /* Param 1: pVMCBHostPhys - Lo. */
2809 aParam[1] = (uint32_t)(pVMCBHostPhys >> 32); /* Param 1: pVMCBHostPhys - Hi. */
2810 aParam[2] = (uint32_t)(pVMCBPhys); /* Param 2: pVMCBPhys - Lo. */
2811 aParam[3] = (uint32_t)(pVMCBPhys >> 32); /* Param 2: pVMCBPhys - Hi. */
2812
2813 return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSVMGCVMRun64, 4, &aParam[0]);
2814}
2815
2816/**
2817 * Executes the specified handler in 64 mode
2818 *
2819 * @returns VBox status code.
2820 * @param pVM The VM to operate on.
2821 * @param pVCpu The VMCPU to operate on.
2822 * @param pCtx Guest context
2823 * @param pfnHandler RC handler
2824 * @param cbParam Number of parameters
2825 * @param paParam Array of 32 bits parameters
2826 */
2827VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
2828{
2829 int rc;
2830 RTHCUINTREG uOldEFlags;
2831
2832 /* @todo This code is not guest SMP safe (hyper stack and switchers) */
2833 AssertReturn(pVM->cCpus == 1, VERR_TOO_MANY_CPUS);
2834 Assert(pfnHandler);
2835
2836 /* Disable interrupts. */
2837 uOldEFlags = ASMIntDisableFlags();
2838
2839 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVM));
2840 CPUMSetHyperEIP(pVCpu, pfnHandler);
2841 for (int i=(int)cbParam-1;i>=0;i--)
2842 CPUMPushHyper(pVCpu, paParam[i]);
2843
2844 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2845 /* Call switcher. */
2846 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
2847 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2848
2849 ASMSetFlags(uOldEFlags);
2850 return rc;
2851}
2852
2853#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
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