VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 23080

Last change on this file since 23080 was 23058, checked in by vboxsync, 15 years ago

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1/* $Id: HWSVMR0.cpp 23058 2009-09-16 09:43:34Z vboxsync $ */
2/** @file
3 * HWACCM SVM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_HWACCM
27#include <VBox/hwaccm.h>
28#include "HWACCMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/hwacc_svm.h>
32#include <VBox/pgm.h>
33#include <VBox/pdm.h>
34#include <VBox/err.h>
35#include <VBox/log.h>
36#include <VBox/selm.h>
37#include <VBox/iom.h>
38#include <VBox/dis.h>
39#include <VBox/dbgf.h>
40#include <VBox/disopcode.h>
41#include <iprt/param.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/cpuset.h>
45#include <iprt/mp.h>
46#include <iprt/time.h>
47#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
48# include <iprt/thread.h>
49#endif
50#include "HWSVMR0.h"
51
52/*******************************************************************************
53* Internal Functions *
54*******************************************************************************/
55static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID);
56static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
57static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite);
58
59/*******************************************************************************
60* Global Variables *
61*******************************************************************************/
62/* IO operation lookup arrays. */
63static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
64
65/**
66 * Sets up and activates AMD-V on the current CPU
67 *
68 * @returns VBox status code.
69 * @param pCpu CPU info struct
70 * @param pVM The VM to operate on. (can be NULL after a resume!!)
71 * @param pvPageCpu Pointer to the global cpu page
72 * @param pPageCpuPhys Physical address of the global cpu page
73 */
74VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
75{
76 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
77 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
78
79 /* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
80
81#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
82 SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
83#endif
84
85 /* Turn on AMD-V in the EFER MSR. */
86 uint64_t val = ASMRdMsr(MSR_K6_EFER);
87 if (!(val & MSR_K6_EFER_SVME))
88 ASMWrMsr(MSR_K6_EFER, val | MSR_K6_EFER_SVME);
89
90 /* Write the physical page address where the CPU will store the host state while executing the VM. */
91 ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
92
93 return VINF_SUCCESS;
94}
95
96/**
97 * Deactivates AMD-V on the current CPU
98 *
99 * @returns VBox status code.
100 * @param pCpu CPU info struct
101 * @param pvPageCpu Pointer to the global cpu page
102 * @param pPageCpuPhys Physical address of the global cpu page
103 */
104VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
105{
106 AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
107 AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
108
109#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
110 SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
111#endif
112
113 /* Turn off AMD-V in the EFER MSR. */
114 uint64_t val = ASMRdMsr(MSR_K6_EFER);
115 ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
116
117 /* Invalidate host state physical address. */
118 ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
119
120 return VINF_SUCCESS;
121}
122
123/**
124 * Does Ring-0 per VM AMD-V init.
125 *
126 * @returns VBox status code.
127 * @param pVM The VM to operate on.
128 */
129VMMR0DECL(int) SVMR0InitVM(PVM pVM)
130{
131 int rc;
132
133 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
134
135 /* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
136 rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
137 if (RT_FAILURE(rc))
138 return rc;
139
140 pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
141 pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
142 /* Set all bits to intercept all IO accesses. */
143 ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
144
145 /* Erratum 170 which requires a forced TLB flush for each world switch:
146 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
147 *
148 * All BH-G1/2 and DH-G1/2 models include a fix:
149 * Athlon X2: 0x6b 1/2
150 * 0x68 1/2
151 * Athlon 64: 0x7f 1
152 * 0x6f 2
153 * Sempron: 0x7f 1/2
154 * 0x6f 2
155 * 0x6c 2
156 * 0x7c 2
157 * Turion 64: 0x68 2
158 *
159 */
160 uint32_t u32Dummy;
161 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
162 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
163 u32BaseFamily= (u32Version >> 8) & 0xf;
164 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
165 u32Model = ((u32Version >> 4) & 0xf);
166 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
167 u32Stepping = u32Version & 0xf;
168 if ( u32Family == 0xf
169 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
170 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
171 {
172 Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
173 pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
174 }
175
176 /* Allocate VMCBs for all guest CPUs. */
177 for (VMCPUID i = 0; i < pVM->cCpus; i++)
178 {
179 PVMCPU pVCpu = &pVM->aCpus[i];
180
181 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
182 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
183 pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
184
185 /* Allocate one page for the host context */
186 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
187 if (RT_FAILURE(rc))
188 return rc;
189
190 pVCpu->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCBHost);
191 pVCpu->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, 0);
192 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCBHost);
193
194 /* Allocate one page for the VM control block (VMCB). */
195 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
196 if (RT_FAILURE(rc))
197 return rc;
198
199 pVCpu->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjVMCB);
200 pVCpu->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjVMCB, 0);
201 ASMMemZeroPage(pVCpu->hwaccm.s.svm.pVMCB);
202
203 /* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
204 rc = RTR0MemObjAllocCont(&pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
205 if (RT_FAILURE(rc))
206 return rc;
207
208 pVCpu->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap);
209 pVCpu->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, 0);
210 /* Set all bits to intercept all MSR accesses. */
211 ASMMemFill32(pVCpu->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
212 }
213
214 return VINF_SUCCESS;
215}
216
217/**
218 * Does Ring-0 per VM AMD-V termination.
219 *
220 * @returns VBox status code.
221 * @param pVM The VM to operate on.
222 */
223VMMR0DECL(int) SVMR0TermVM(PVM pVM)
224{
225 for (VMCPUID i = 0; i < pVM->cCpus; i++)
226 {
227 PVMCPU pVCpu = &pVM->aCpus[i];
228
229 if (pVCpu->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
230 {
231 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCBHost, false);
232 pVCpu->hwaccm.s.svm.pVMCBHost = 0;
233 pVCpu->hwaccm.s.svm.pVMCBHostPhys = 0;
234 pVCpu->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
235 }
236
237 if (pVCpu->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
238 {
239 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjVMCB, false);
240 pVCpu->hwaccm.s.svm.pVMCB = 0;
241 pVCpu->hwaccm.s.svm.pVMCBPhys = 0;
242 pVCpu->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
243 }
244 if (pVCpu->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
245 {
246 RTR0MemObjFree(pVCpu->hwaccm.s.svm.pMemObjMSRBitmap, false);
247 pVCpu->hwaccm.s.svm.pMSRBitmap = 0;
248 pVCpu->hwaccm.s.svm.pMSRBitmapPhys = 0;
249 pVCpu->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
250 }
251 }
252 if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
253 {
254 RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
255 pVM->hwaccm.s.svm.pIOBitmap = 0;
256 pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
257 pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
258 }
259 return VINF_SUCCESS;
260}
261
262/**
263 * Sets up AMD-V for the specified VM
264 *
265 * @returns VBox status code.
266 * @param pVM The VM to operate on.
267 */
268VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
269{
270 int rc = VINF_SUCCESS;
271
272 AssertReturn(pVM, VERR_INVALID_PARAMETER);
273
274 Assert(pVM->hwaccm.s.svm.fSupported);
275
276 for (VMCPUID i = 0; i < pVM->cCpus; i++)
277 {
278 PVMCPU pVCpu = &pVM->aCpus[i];
279 SVM_VMCB *pVMCB = (SVM_VMCB *)pVM->aCpus[i].hwaccm.s.svm.pVMCB;
280
281 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
282
283 /* Program the control fields. Most of them never have to be changed again. */
284 /* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
285 /* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
286 if (!pVM->hwaccm.s.fNestedPaging)
287 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
288 else
289 pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4);
290
291 /*
292 * CR0/3/4 writes must be intercepted for obvious reasons.
293 */
294 if (!pVM->hwaccm.s.fNestedPaging)
295 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(3) | RT_BIT(4);
296 else
297 pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4) | RT_BIT(8);
298
299 /* Intercept all DRx reads and writes by default. Changed later on. */
300 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
301 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
302
303 /* Currently we don't care about DRx reads or writes. DRx registers are trashed.
304 * All breakpoints are automatically cleared when the VM exits.
305 */
306
307 pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
308#ifndef DEBUG
309 if (pVM->hwaccm.s.fNestedPaging)
310 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
311#endif
312
313 pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
314 | SVM_CTRL1_INTERCEPT_VINTR
315 | SVM_CTRL1_INTERCEPT_NMI
316 | SVM_CTRL1_INTERCEPT_SMI
317 | SVM_CTRL1_INTERCEPT_INIT
318 | SVM_CTRL1_INTERCEPT_RDPMC
319 | SVM_CTRL1_INTERCEPT_CPUID
320 | SVM_CTRL1_INTERCEPT_RSM
321 | SVM_CTRL1_INTERCEPT_HLT
322 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP
323 | SVM_CTRL1_INTERCEPT_MSR_SHADOW
324 | SVM_CTRL1_INTERCEPT_INVLPG
325 | SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
326 | SVM_CTRL1_INTERCEPT_TASK_SWITCH
327 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
328 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
329 ;
330 /* With nested paging we don't care about invlpg anymore. */
331 if (pVM->hwaccm.s.fNestedPaging)
332 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
333
334 pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
335 | SVM_CTRL2_INTERCEPT_VMMCALL
336 | SVM_CTRL2_INTERCEPT_VMLOAD
337 | SVM_CTRL2_INTERCEPT_VMSAVE
338 | SVM_CTRL2_INTERCEPT_STGI
339 | SVM_CTRL2_INTERCEPT_CLGI
340 | SVM_CTRL2_INTERCEPT_SKINIT
341 | SVM_CTRL2_INTERCEPT_WBINVD
342 | SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
343 ;
344 Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
345 Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
346 Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
347
348 /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
349 pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
350 /* Ignore the priority in the TPR; just deliver it when we tell it to. */
351 pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
352
353 /* Set IO and MSR bitmap addresses. */
354 pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
355 pVMCB->ctrl.u64MSRPMPhysAddr = pVCpu->hwaccm.s.svm.pMSRBitmapPhys;
356
357 /* No LBR virtualization. */
358 pVMCB->ctrl.u64LBRVirt = 0;
359
360 /** The ASID must start at 1; the host uses 0. */
361 pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
362
363 /** Setup the PAT msr (nested paging only) */
364 pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
365
366 /* The following MSRs are saved automatically by vmload/vmsave, so we allow the guest
367 * to modify them directly.
368 */
369 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
370 svmR0SetMSRPermission(pVCpu, MSR_K8_CSTAR, true, true);
371 svmR0SetMSRPermission(pVCpu, MSR_K6_STAR, true, true);
372 svmR0SetMSRPermission(pVCpu, MSR_K8_SF_MASK, true, true);
373 svmR0SetMSRPermission(pVCpu, MSR_K8_FS_BASE, true, true);
374 svmR0SetMSRPermission(pVCpu, MSR_K8_GS_BASE, true, true);
375 svmR0SetMSRPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, true, true);
376 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_CS, true, true);
377 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_ESP, true, true);
378 svmR0SetMSRPermission(pVCpu, MSR_IA32_SYSENTER_EIP, true, true);
379 }
380
381 return rc;
382}
383
384
385/**
386 * Sets the permission bits for the specified MSR
387 *
388 * @param pVCpu The VMCPU to operate on.
389 * @param ulMSR MSR value
390 * @param fRead Reading allowed/disallowed
391 * @param fWrite Writing allowed/disallowed
392 */
393static void svmR0SetMSRPermission(PVMCPU pVCpu, unsigned ulMSR, bool fRead, bool fWrite)
394{
395 unsigned ulBit;
396 uint8_t *pMSRBitmap = (uint8_t *)pVCpu->hwaccm.s.svm.pMSRBitmap;
397
398 if (ulMSR <= 0x00001FFF)
399 {
400 /* Pentium-compatible MSRs */
401 ulBit = ulMSR * 2;
402 }
403 else
404 if ( ulMSR >= 0xC0000000
405 && ulMSR <= 0xC0001FFF)
406 {
407 /* AMD Sixth Generation x86 Processor MSRs and SYSCALL */
408 ulBit = (ulMSR - 0xC0000000) * 2;
409 pMSRBitmap += 0x800;
410 }
411 else
412 if ( ulMSR >= 0xC0010000
413 && ulMSR <= 0xC0011FFF)
414 {
415 /* AMD Seventh and Eighth Generation Processor MSRs */
416 ulBit = (ulMSR - 0xC0001000) * 2;
417 pMSRBitmap += 0x1000;
418 }
419 else
420 {
421 AssertFailed();
422 return;
423 }
424 Assert(ulBit < 16 * 1024 - 1);
425 if (fRead)
426 ASMBitClear(pMSRBitmap, ulBit);
427 else
428 ASMBitSet(pMSRBitmap, ulBit);
429
430 if (fWrite)
431 ASMBitClear(pMSRBitmap, ulBit + 1);
432 else
433 ASMBitSet(pMSRBitmap, ulBit + 1);
434}
435
436/**
437 * Injects an event (trap or external interrupt)
438 *
439 * @param pVCpu The VMCPU to operate on.
440 * @param pVMCB SVM control block
441 * @param pCtx CPU Context
442 * @param pIntInfo SVM interrupt info
443 */
444inline void SVMR0InjectEvent(PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx, SVM_EVENT* pEvent)
445{
446#ifdef VBOX_WITH_STATISTICS
447 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
448#endif
449
450#ifdef VBOX_STRICT
451 if (pEvent->n.u8Vector == 0xE)
452 Log(("SVM: Inject int %d at %RGv error code=%02x CR2=%RGv intInfo=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode, (RTGCPTR)pCtx->cr2, pEvent->au64[0]));
453 else
454 if (pEvent->n.u8Vector < 0x20)
455 Log(("SVM: Inject int %d at %RGv error code=%08x\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip, pEvent->n.u32ErrorCode));
456 else
457 {
458 Log(("INJ-EI: %x at %RGv\n", pEvent->n.u8Vector, (RTGCPTR)pCtx->rip));
459 Assert(!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
460 Assert(pCtx->eflags.u32 & X86_EFL_IF);
461 }
462#endif
463
464 /* Set event injection state. */
465 pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
466}
467
468
469/**
470 * Checks for pending guest interrupts and injects them
471 *
472 * @returns VBox status code.
473 * @param pVM The VM to operate on.
474 * @param pVCpu The VM CPU to operate on.
475 * @param pVMCB SVM control block
476 * @param pCtx CPU Context
477 */
478static int SVMR0CheckPendingInterrupt(PVM pVM, PVMCPU pVCpu, SVM_VMCB *pVMCB, CPUMCTX *pCtx)
479{
480 int rc;
481
482 /* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
483 if (pVCpu->hwaccm.s.Event.fPending)
484 {
485 SVM_EVENT Event;
486
487 Log(("Reinjecting event %08x %08x at %RGv\n", pVCpu->hwaccm.s.Event.intInfo, pVCpu->hwaccm.s.Event.errCode, (RTGCPTR)pCtx->rip));
488 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntReinject);
489 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
490 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
491
492 pVCpu->hwaccm.s.Event.fPending = false;
493 return VINF_SUCCESS;
494 }
495
496 /* If an active trap is already pending, then we must forward it first! */
497 if (!TRPMHasTrap(pVCpu))
498 {
499 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI))
500 {
501 SVM_EVENT Event;
502
503 Log(("CPU%d: injecting #NMI\n", pVCpu->idCpu));
504 Event.n.u8Vector = X86_XCPT_NMI;
505 Event.n.u1Valid = 1;
506 Event.n.u32ErrorCode = 0;
507 Event.n.u3Type = SVM_EVENT_NMI;
508
509 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
510 return VINF_SUCCESS;
511 }
512
513 /* @todo SMI interrupts. */
514
515 /* When external interrupts are pending, we should exit the VM when IF is set. */
516 if (VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
517 {
518 if ( !(pCtx->eflags.u32 & X86_EFL_IF)
519 || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
520 {
521 if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
522 {
523 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
524 LogFlow(("Enable irq window exit!\n"));
525 else
526 Log(("Pending interrupt blocked at %RGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", (RTGCPTR)pCtx->rip));
527
528 /** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
529 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
530 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
531 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
532 }
533 }
534 else
535 {
536 uint8_t u8Interrupt;
537
538 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
539 Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
540 if (RT_SUCCESS(rc))
541 {
542 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
543 AssertRC(rc);
544 }
545 else
546 {
547 /* Can only happen in rare cases where a pending interrupt is cleared behind our back */
548 Assert(!VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)));
549 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchGuestIrq);
550 /* Just continue */
551 }
552 }
553 }
554 }
555
556#ifdef VBOX_STRICT
557 if (TRPMHasTrap(pVCpu))
558 {
559 uint8_t u8Vector;
560 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, 0, 0, 0);
561 AssertRC(rc);
562 }
563#endif
564
565 if ( (pCtx->eflags.u32 & X86_EFL_IF)
566 && (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
567 && TRPMHasTrap(pVCpu)
568 )
569 {
570 uint8_t u8Vector;
571 int rc;
572 TRPMEVENT enmType;
573 SVM_EVENT Event;
574 RTGCUINT u32ErrorCode;
575
576 Event.au64[0] = 0;
577
578 /* If a new event is pending, then dispatch it now. */
579 rc = TRPMQueryTrapAll(pVCpu, &u8Vector, &enmType, &u32ErrorCode, 0);
580 AssertRC(rc);
581 Assert(pCtx->eflags.Bits.u1IF == 1 || enmType == TRPM_TRAP);
582 Assert(enmType != TRPM_SOFTWARE_INT);
583
584 /* Clear the pending trap. */
585 rc = TRPMResetTrap(pVCpu);
586 AssertRC(rc);
587
588 Event.n.u8Vector = u8Vector;
589 Event.n.u1Valid = 1;
590 Event.n.u32ErrorCode = u32ErrorCode;
591
592 if (enmType == TRPM_TRAP)
593 {
594 switch (u8Vector) {
595 case 8:
596 case 10:
597 case 11:
598 case 12:
599 case 13:
600 case 14:
601 case 17:
602 /* Valid error codes. */
603 Event.n.u1ErrorCodeValid = 1;
604 break;
605 default:
606 break;
607 }
608 if (u8Vector == X86_XCPT_NMI)
609 Event.n.u3Type = SVM_EVENT_NMI;
610 else
611 Event.n.u3Type = SVM_EVENT_EXCEPTION;
612 }
613 else
614 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
615
616 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatIntInject);
617 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
618 } /* if (interrupts can be dispatched) */
619
620 return VINF_SUCCESS;
621}
622
623/**
624 * Save the host state
625 *
626 * @returns VBox status code.
627 * @param pVM The VM to operate on.
628 * @param pVCpu The VM CPU to operate on.
629 */
630VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
631{
632 NOREF(pVM);
633 NOREF(pVCpu);
634 /* Nothing to do here. */
635 return VINF_SUCCESS;
636}
637
638/**
639 * Loads the guest state
640 *
641 * NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
642 *
643 * @returns VBox status code.
644 * @param pVM The VM to operate on.
645 * @param pVCpu The VM CPU to operate on.
646 * @param pCtx Guest context
647 */
648VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
649{
650 RTGCUINTPTR val;
651 SVM_VMCB *pVMCB;
652
653 if (pVM == NULL)
654 return VERR_INVALID_PARAMETER;
655
656 /* Setup AMD SVM. */
657 Assert(pVM->hwaccm.s.svm.fSupported);
658
659 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
660 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
661
662 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
663 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
664 {
665 SVM_WRITE_SELREG(CS, cs);
666 SVM_WRITE_SELREG(SS, ss);
667 SVM_WRITE_SELREG(DS, ds);
668 SVM_WRITE_SELREG(ES, es);
669 SVM_WRITE_SELREG(FS, fs);
670 SVM_WRITE_SELREG(GS, gs);
671 }
672
673 /* Guest CPU context: LDTR. */
674 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
675 {
676 SVM_WRITE_SELREG(LDTR, ldtr);
677 }
678
679 /* Guest CPU context: TR. */
680 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
681 {
682 SVM_WRITE_SELREG(TR, tr);
683 }
684
685 /* Guest CPU context: GDTR. */
686 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
687 {
688 pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
689 pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
690 }
691
692 /* Guest CPU context: IDTR. */
693 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
694 {
695 pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
696 pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
697 }
698
699 /*
700 * Sysenter MSRs (unconditional)
701 */
702 pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
703 pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
704 pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
705
706 /* Control registers */
707 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
708 {
709 val = pCtx->cr0;
710 if (!CPUMIsGuestFPUStateActive(pVCpu))
711 {
712 /* Always use #NM exceptions to load the FPU/XMM state on demand. */
713 val |= X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
714 }
715 else
716 {
717 /** @todo check if we support the old style mess correctly. */
718 if (!(val & X86_CR0_NE))
719 {
720 Log(("Forcing X86_CR0_NE!!!\n"));
721
722 /* Also catch floating point exceptions as we need to report them to the guest in a different way. */
723 if (!pVCpu->hwaccm.s.fFPUOldStyleOverride)
724 {
725 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_MF);
726 pVCpu->hwaccm.s.fFPUOldStyleOverride = true;
727 }
728 }
729 val |= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
730 }
731 /* Always enable caching. */
732 val &= ~(X86_CR0_CD|X86_CR0_NW);
733
734 /* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
735 /* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
736 if (!pVM->hwaccm.s.fNestedPaging)
737 {
738 val |= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
739 val |= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
740 }
741 pVMCB->guest.u64CR0 = val;
742 }
743 /* CR2 as well */
744 pVMCB->guest.u64CR2 = pCtx->cr2;
745
746 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
747 {
748 /* Save our shadow CR3 register. */
749 if (pVM->hwaccm.s.fNestedPaging)
750 {
751 PGMMODE enmShwPagingMode;
752
753#if HC_ARCH_BITS == 32
754 if (CPUMIsGuestInLongModeEx(pCtx))
755 enmShwPagingMode = PGMMODE_AMD64_NX;
756 else
757#endif
758 enmShwPagingMode = PGMGetHostMode(pVM);
759
760 pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
761 Assert(pVMCB->ctrl.u64NestedPagingCR3);
762 pVMCB->guest.u64CR3 = pCtx->cr3;
763 }
764 else
765 {
766 pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
767 Assert(pVMCB->guest.u64CR3 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
768 }
769 }
770
771 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
772 {
773 val = pCtx->cr4;
774 if (!pVM->hwaccm.s.fNestedPaging)
775 {
776 switch(pVCpu->hwaccm.s.enmShadowMode)
777 {
778 case PGMMODE_REAL:
779 case PGMMODE_PROTECTED: /* Protected mode, no paging. */
780 AssertFailed();
781 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
782
783 case PGMMODE_32_BIT: /* 32-bit paging. */
784 val &= ~X86_CR4_PAE;
785 break;
786
787 case PGMMODE_PAE: /* PAE paging. */
788 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
789 /** @todo use normal 32 bits paging */
790 val |= X86_CR4_PAE;
791 break;
792
793 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
794 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
795#ifdef VBOX_ENABLE_64_BITS_GUESTS
796 break;
797#else
798 AssertFailed();
799 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
800#endif
801
802 default: /* shut up gcc */
803 AssertFailed();
804 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
805 }
806 }
807 pVMCB->guest.u64CR4 = val;
808 }
809
810 /* Debug registers. */
811 if (pVCpu->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
812 {
813 pCtx->dr[6] |= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
814 pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
815
816 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
817 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
818 pCtx->dr[7] |= 0x400; /* must be one */
819
820 pVMCB->guest.u64DR7 = pCtx->dr[7];
821 pVMCB->guest.u64DR6 = pCtx->dr[6];
822
823#ifdef DEBUG
824 /* Sync the hypervisor debug state now if any breakpoint is armed. */
825 if ( CPUMGetHyperDR7(pVCpu) & (X86_DR7_ENABLED_MASK|X86_DR7_GD)
826 && !CPUMIsHyperDebugStateActive(pVCpu)
827 && !DBGFIsStepping(pVCpu))
828 {
829 /* Save the host and load the hypervisor debug state. */
830 int rc = CPUMR0LoadHyperDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
831 AssertRC(rc);
832
833 /* DRx intercepts remain enabled. */
834
835 /* Override dr6 & dr7 with the hypervisor values. */
836 pVMCB->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
837 pVMCB->guest.u64DR6 = CPUMGetHyperDR6(pVCpu);
838 }
839 else
840#endif
841 /* Sync the debug state now if any breakpoint is armed. */
842 if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK|X86_DR7_GD))
843 && !CPUMIsGuestDebugStateActive(pVCpu)
844 && !DBGFIsStepping(pVCpu))
845 {
846 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxArmed);
847
848 /* Disable drx move intercepts. */
849 pVMCB->ctrl.u16InterceptRdDRx = 0;
850 pVMCB->ctrl.u16InterceptWrDRx = 0;
851
852 /* Save the host and load the guest debug state. */
853 int rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
854 AssertRC(rc);
855 }
856 }
857
858 /* EIP, ESP and EFLAGS */
859 pVMCB->guest.u64RIP = pCtx->rip;
860 pVMCB->guest.u64RSP = pCtx->rsp;
861 pVMCB->guest.u64RFlags = pCtx->eflags.u32;
862
863 /* Set CPL */
864 pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
865
866 /* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
867 pVMCB->guest.u64RAX = pCtx->rax;
868
869 /* vmrun will fail without MSR_K6_EFER_SVME. */
870 pVMCB->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
871
872 /* 64 bits guest mode? */
873 if (CPUMIsGuestInLongModeEx(pCtx))
874 {
875#if !defined(VBOX_ENABLE_64_BITS_GUESTS)
876 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
877#elif HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
878 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
879#else
880# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
881 if (!pVM->hwaccm.s.fAllow64BitGuests)
882 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
883# endif
884 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun64;
885#endif
886 /* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
887 pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
888 pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
889 }
890 else
891 {
892 /* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
893 pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
894
895 pVCpu->hwaccm.s.svm.pfnVMRun = SVMR0VMRun;
896 }
897
898 /* TSC offset. */
899 if (TMCpuTickCanUseRealTSC(pVCpu, &pVMCB->ctrl.u64TSCOffset))
900 {
901 uint64_t u64CurTSC = ASMReadTSC();
902 if (u64CurTSC + pVMCB->ctrl.u64TSCOffset >= TMCpuTickGetLastSeen(pVCpu))
903 {
904 pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
905 pVMCB->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
906 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCOffset);
907 }
908 else
909 {
910 /* Fall back to rdtsc emulation as we would otherwise pass decreasing tsc values to the guest. */
911 LogFlow(("TSC %RX64 offset %RX64 time=%RX64 last=%RX64 (diff=%RX64, virt_tsc=%RX64)\n", u64CurTSC, pVMCB->ctrl.u64TSCOffset, u64CurTSC + pVMCB->ctrl.u64TSCOffset, TMCpuTickGetLastSeen(pVCpu), TMCpuTickGetLastSeen(pVCpu) - u64CurTSC - pVMCB->ctrl.u64TSCOffset, TMCpuTickGet(pVCpu)));
912 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
913 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
914 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow);
915 }
916 }
917 else
918 {
919 pVMCB->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
920 pVMCB->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
921 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTSCIntercept);
922 }
923
924 /* Sync the various msrs for 64 bits mode. */
925 pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
926 pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
927 pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
928 pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
929 pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
930
931#ifdef DEBUG
932 /* Intercept X86_XCPT_DB if stepping is enabled */
933 if ( DBGFIsStepping(pVCpu)
934 || CPUMIsHyperDebugStateActive(pVCpu))
935 pVMCB->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_DB);
936 else
937 pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
938#endif
939
940 /* Done. */
941 pVCpu->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
942
943 return VINF_SUCCESS;
944}
945
946
947/**
948 * Runs guest code in an AMD-V VM.
949 *
950 * @returns VBox status code.
951 * @param pVM The VM to operate on.
952 * @param pVCpu The VM CPU to operate on.
953 * @param pCtx Guest context
954 */
955VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
956{
957 int rc = VINF_SUCCESS;
958 uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
959 SVM_VMCB *pVMCB;
960 bool fSyncTPR = false;
961 unsigned cResume = 0;
962 uint8_t u8LastTPR;
963 PHWACCM_CPUINFO pCpu = 0;
964 RTCCUINTREG uOldEFlags = ~(RTCCUINTREG)0;
965#ifdef VBOX_STRICT
966 RTCPUID idCpuCheck;
967#endif
968#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
969 uint64_t u64LastTime = RTTimeMilliTS();
970#endif
971
972 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatEntry, x);
973
974 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
975 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
976
977 /* We can jump to this point to resume execution after determining that a VM-exit is innocent.
978 */
979ResumeExecution:
980 Assert(!HWACCMR0SuspendPending());
981
982 /* Safety precaution; looping for too long here can have a very bad effect on the host */
983 if (RT_UNLIKELY(++cResume > pVM->hwaccm.s.cMaxResumeLoops))
984 {
985 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMaxResume);
986 rc = VINF_EM_RAW_INTERRUPT;
987 goto end;
988 }
989
990 /* Check for irq inhibition due to instruction fusing (sti, mov ss). */
991 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
992 {
993 Log(("VM_FF_INHIBIT_INTERRUPTS at %RGv successor %RGv\n", (RTGCPTR)pCtx->rip, EMGetInhibitInterruptsPC(pVCpu)));
994 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
995 {
996 /* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
997 * Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
998 * force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
999 * break the guest. Sounds very unlikely, but such timing sensitive problems are not as rare as you might think.
1000 */
1001 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1002 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
1003 pVMCB->ctrl.u64IntShadow = 0;
1004 }
1005 }
1006 else
1007 {
1008 /* Irq inhibition is no longer active; clear the corresponding SVM state. */
1009 pVMCB->ctrl.u64IntShadow = 0;
1010 }
1011
1012#ifdef VBOX_HIGH_RES_TIMERS_HACK_IN_RING0
1013 if (RT_UNLIKELY(cResume & 0xf) == 0)
1014 {
1015 uint64_t u64CurTime = RTTimeMilliTS();
1016
1017 if (RT_UNLIKELY(u64CurTime > u64LastTime))
1018 {
1019 u64LastTime = u64CurTime;
1020 TMTimerPollVoid(pVM, pVCpu);
1021 }
1022 }
1023#endif
1024
1025 /* Check for pending actions that force us to go back to ring 3. */
1026#ifdef DEBUG
1027 /* Intercept X86_XCPT_DB if stepping is enabled */
1028 if (!DBGFIsStepping(pVCpu))
1029#endif
1030 {
1031 if ( VM_FF_ISPENDING(pVM, VM_FF_HWACCM_TO_R3_MASK)
1032 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HWACCM_TO_R3_MASK))
1033 {
1034 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
1035 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatSwitchToR3);
1036 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1037 rc = RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
1038 goto end;
1039 }
1040 }
1041
1042 /* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
1043 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
1044 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1045 {
1046 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1047 rc = VINF_EM_PENDING_REQUEST;
1048 goto end;
1049 }
1050
1051#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1052 /*
1053 * Exit to ring-3 preemption/work is pending.
1054 *
1055 * Interrupts are disabled before the call to make sure we don't miss any interrupt
1056 * that would flag preemption (IPI, timer tick, ++). (Would've been nice to do this
1057 * further down, but SVMR0CheckPendingInterrupt makes that impossible.)
1058 *
1059 * Note! Interrupts must be disabled done *before* we check for TLB flushes; TLB
1060 * shootdowns rely on this.
1061 */
1062 uOldEFlags = ASMIntDisableFlags();
1063 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
1064 {
1065 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitPreemptPending);
1066 rc = VINF_EM_RAW_INTERRUPT;
1067 goto end;
1068 }
1069 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1070#endif
1071
1072 /* When external interrupts are pending, we should exit the VM when IF is set. */
1073 /* Note! *After* VM_FF_INHIBIT_INTERRUPTS check!!! */
1074 rc = SVMR0CheckPendingInterrupt(pVM, pVCpu, pVMCB, pCtx);
1075 if (RT_FAILURE(rc))
1076 {
1077 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1078 goto end;
1079 }
1080
1081 /* TPR caching using CR8 is only available in 64 bits mode or with 32 bits guests when X86_CPUID_AMD_FEATURE_ECX_CR8L is supported. */
1082 /* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! (no longer true)
1083 * @todo query and update the TPR only when it could have been changed (mmio access)
1084 */
1085 if (pVM->hwaccm.s.fHasIoApic)
1086 {
1087 bool fPending;
1088
1089 /* TPR caching in CR8 */
1090 int rc = PDMApicGetTPR(pVCpu, &u8LastTPR, &fPending);
1091 AssertRC(rc);
1092
1093 if (pVM->hwaccm.s.svm.fTPRPatchingActive)
1094 {
1095 /* Our patch code uses LSTAR for TPR caching. */
1096 pCtx->msrLSTAR = u8LastTPR;
1097
1098 if (fPending)
1099 {
1100 /* A TPR change could activate a pending interrupt, so catch lstar writes. */
1101 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, false);
1102 }
1103 else
1104 /* No interrupts are pending, so we don't need to be explicitely notified.
1105 * There are enough world switches for detecting pending interrupts.
1106 */
1107 svmR0SetMSRPermission(pVCpu, MSR_K8_LSTAR, true, true);
1108 }
1109 else
1110 {
1111 pVMCB->ctrl.IntCtrl.n.u8VTPR = (u8LastTPR >> 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1112
1113 if (fPending)
1114 {
1115 /* A TPR change could activate a pending interrupt, so catch cr8 writes. */
1116 pVMCB->ctrl.u16InterceptWrCRx |= RT_BIT(8);
1117 }
1118 else
1119 /* No interrupts are pending, so we don't need to be explicitely notified.
1120 * There are enough world switches for detecting pending interrupts.
1121 */
1122 pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1123 }
1124 fSyncTPR = !fPending;
1125 }
1126
1127 /* All done! Let's start VM execution. */
1128 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatInGC, x);
1129
1130 /* Enable nested paging if necessary (disabled each time after #VMEXIT). */
1131 pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
1132
1133#ifdef LOG_ENABLED
1134 pCpu = HWACCMR0GetCurrentCpu();
1135 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1136 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1137 {
1138 if (pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu)
1139 Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVCpu->hwaccm.s.idLastCpu, pCpu->idCpu));
1140 else
1141 Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1142 }
1143 if (pCpu->fFlushTLB)
1144 Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
1145#endif
1146
1147 /*
1148 * NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
1149 * (until the actual world switch)
1150 */
1151#ifdef VBOX_STRICT
1152 idCpuCheck = RTMpCpuId();
1153#endif
1154 VMMR0LogFlushDisable(pVCpu);
1155
1156 /* Load the guest state; *must* be here as it sets up the shadow cr0 for lazy fpu syncing! */
1157 rc = SVMR0LoadGuestState(pVM, pVCpu, pCtx);
1158 if (RT_UNLIKELY(rc != VINF_SUCCESS))
1159 {
1160 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatEntry, x);
1161 VMMR0LogFlushEnable(pVCpu);
1162 goto end;
1163 }
1164
1165#ifndef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1166 /* Disable interrupts to make sure a poke will interrupt execution.
1167 * This must be done *before* we check for TLB flushes; TLB shootdowns rely on this.
1168 */
1169 uOldEFlags = ASMIntDisableFlags();
1170 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
1171#endif
1172
1173 pCpu = HWACCMR0GetCurrentCpu();
1174 /* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
1175 /* Note that this can happen both for start and resume due to long jumps back to ring 3. */
1176 if ( pVCpu->hwaccm.s.idLastCpu != pCpu->idCpu
1177 /* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
1178 || pVCpu->hwaccm.s.cTLBFlushes != pCpu->cTLBFlushes)
1179 {
1180 /* Force a TLB flush on VM entry. */
1181 pVCpu->hwaccm.s.fForceTLBFlush = true;
1182 }
1183 else
1184 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1185
1186 pVCpu->hwaccm.s.idLastCpu = pCpu->idCpu;
1187
1188 /* Check for tlb shootdown flushes. */
1189 if (VMCPU_FF_TESTANDCLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1190 pVCpu->hwaccm.s.fForceTLBFlush = true;
1191
1192 /* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
1193 if ( pVCpu->hwaccm.s.fForceTLBFlush
1194 && !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
1195 {
1196 if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.uMaxASID
1197 || pCpu->fFlushTLB)
1198 {
1199 pCpu->fFlushTLB = false;
1200 pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
1201 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
1202 pCpu->cTLBFlushes++;
1203 }
1204 else
1205 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushASID);
1206
1207 pVCpu->hwaccm.s.cTLBFlushes = pCpu->cTLBFlushes;
1208 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID;
1209 }
1210 else
1211 {
1212 Assert(!pCpu->fFlushTLB || pVM->hwaccm.s.svm.fAlwaysFlushTLB);
1213
1214 /* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
1215 if (!pCpu->uCurrentASID || !pVCpu->hwaccm.s.uCurrentASID)
1216 pVCpu->hwaccm.s.uCurrentASID = pCpu->uCurrentASID = 1;
1217
1218 Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB || pVCpu->hwaccm.s.fForceTLBFlush);
1219 pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVCpu->hwaccm.s.fForceTLBFlush;
1220
1221 if ( !pVM->hwaccm.s.svm.fAlwaysFlushTLB
1222 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
1223 {
1224 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
1225 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatTlbShootdown);
1226 for (unsigned i=0;i<pVCpu->hwaccm.s.TlbShootdown.cPages;i++)
1227 SVMR0InvlpgA(pVCpu->hwaccm.s.TlbShootdown.aPages[i], pVMCB->ctrl.TLBCtrl.n.u32ASID);
1228 }
1229 }
1230 pVCpu->hwaccm.s.TlbShootdown.cPages = 0;
1231 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
1232
1233 AssertMsg(pVCpu->hwaccm.s.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hwaccm.s.cTLBFlushes, pCpu->cTLBFlushes));
1234 AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
1235 AssertMsg(pVCpu->hwaccm.s.uCurrentASID >= 1 && pVCpu->hwaccm.s.uCurrentASID < pVM->hwaccm.s.uMaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVCpu->hwaccm.s.uCurrentASID));
1236 pVMCB->ctrl.TLBCtrl.n.u32ASID = pVCpu->hwaccm.s.uCurrentASID;
1237
1238#ifdef VBOX_WITH_STATISTICS
1239 if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
1240 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch);
1241 else
1242 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch);
1243#endif
1244
1245 /* In case we execute a goto ResumeExecution later on. */
1246 pVCpu->hwaccm.s.fResumeVM = true;
1247 pVCpu->hwaccm.s.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
1248
1249 Assert(sizeof(pVCpu->hwaccm.s.svm.pVMCBPhys) == 8);
1250 Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
1251 Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
1252 Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVCpu->hwaccm.s.svm.pMSRBitmapPhys);
1253 Assert(pVMCB->ctrl.u64LBRVirt == 0);
1254
1255#ifdef VBOX_STRICT
1256 Assert(idCpuCheck == RTMpCpuId());
1257#endif
1258 TMNotifyStartOfExecution(pVCpu);
1259#ifdef VBOX_WITH_KERNEL_USING_XMM
1260 hwaccmR0SVMRunWrapXMM(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu, pVCpu->hwaccm.s.svm.pfnVMRun);
1261#else
1262 pVCpu->hwaccm.s.svm.pfnVMRun(pVCpu->hwaccm.s.svm.pVMCBHostPhys, pVCpu->hwaccm.s.svm.pVMCBPhys, pCtx, pVM, pVCpu);
1263#endif
1264 /* Possibly the last TSC value seen by the guest (too high) (only when we're in tsc offset mode). */
1265 if (!(pVMCB->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
1266 TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVMCB->ctrl.u64TSCOffset - 0x400 /* guestimate of world switch overhead in clock ticks */);
1267 TMNotifyEndOfExecution(pVCpu);
1268 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
1269 ASMSetFlags(uOldEFlags);
1270#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1271 uOldEFlags = ~(RTCCUINTREG)0;
1272#endif
1273 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatInGC, x);
1274
1275 /*
1276 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1277 * IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 *BEFORE* WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1278 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1279 */
1280
1281 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatExit1, x);
1282
1283 /* Reason for the VM exit */
1284 exitCode = pVMCB->ctrl.u64ExitCode;
1285
1286 if (RT_UNLIKELY(exitCode == (uint64_t)SVM_EXIT_INVALID)) /* Invalid guest state. */
1287 {
1288 HWACCMDumpRegs(pVM, pVCpu, pCtx);
1289#ifdef DEBUG
1290 Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1291 Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1292 Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1293 Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1294 Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1295 Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1296 Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1297 Log(("ctrl.u64IOPMPhysAddr %RX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1298 Log(("ctrl.u64MSRPMPhysAddr %RX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1299 Log(("ctrl.u64TSCOffset %RX64\n", pVMCB->ctrl.u64TSCOffset));
1300
1301 Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1302 Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1303 Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1304 Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1305
1306 Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1307 Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1308 Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1309 Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1310 Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1311 Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1312 Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1313 Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1314 Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1315 Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1316
1317 Log(("ctrl.u64IntShadow %RX64\n", pVMCB->ctrl.u64IntShadow));
1318 Log(("ctrl.u64ExitCode %RX64\n", pVMCB->ctrl.u64ExitCode));
1319 Log(("ctrl.u64ExitInfo1 %RX64\n", pVMCB->ctrl.u64ExitInfo1));
1320 Log(("ctrl.u64ExitInfo2 %RX64\n", pVMCB->ctrl.u64ExitInfo2));
1321 Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1322 Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1323 Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1324 Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1325 Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1326 Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1327 Log(("ctrl.NestedPaging %RX64\n", pVMCB->ctrl.NestedPaging.au64));
1328 Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1329 Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1330 Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1331 Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1332 Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1333 Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1334
1335 Log(("ctrl.u64NestedPagingCR3 %RX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1336 Log(("ctrl.u64LBRVirt %RX64\n", pVMCB->ctrl.u64LBRVirt));
1337
1338 Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1339 Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1340 Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1341 Log(("guest.CS.u64Base %RX64\n", pVMCB->guest.CS.u64Base));
1342 Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1343 Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1344 Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1345 Log(("guest.DS.u64Base %RX64\n", pVMCB->guest.DS.u64Base));
1346 Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1347 Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1348 Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1349 Log(("guest.ES.u64Base %RX64\n", pVMCB->guest.ES.u64Base));
1350 Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1351 Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1352 Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1353 Log(("guest.FS.u64Base %RX64\n", pVMCB->guest.FS.u64Base));
1354 Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1355 Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1356 Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1357 Log(("guest.GS.u64Base %RX64\n", pVMCB->guest.GS.u64Base));
1358
1359 Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1360 Log(("guest.GDTR.u64Base %RX64\n", pVMCB->guest.GDTR.u64Base));
1361
1362 Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1363 Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1364 Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1365 Log(("guest.LDTR.u64Base %RX64\n", pVMCB->guest.LDTR.u64Base));
1366
1367 Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1368 Log(("guest.IDTR.u64Base %RX64\n", pVMCB->guest.IDTR.u64Base));
1369
1370 Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1371 Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1372 Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1373 Log(("guest.TR.u64Base %RX64\n", pVMCB->guest.TR.u64Base));
1374
1375 Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1376 Log(("guest.u64CR0 %RX64\n", pVMCB->guest.u64CR0));
1377 Log(("guest.u64CR2 %RX64\n", pVMCB->guest.u64CR2));
1378 Log(("guest.u64CR3 %RX64\n", pVMCB->guest.u64CR3));
1379 Log(("guest.u64CR4 %RX64\n", pVMCB->guest.u64CR4));
1380 Log(("guest.u64DR6 %RX64\n", pVMCB->guest.u64DR6));
1381 Log(("guest.u64DR7 %RX64\n", pVMCB->guest.u64DR7));
1382
1383 Log(("guest.u64RIP %RX64\n", pVMCB->guest.u64RIP));
1384 Log(("guest.u64RSP %RX64\n", pVMCB->guest.u64RSP));
1385 Log(("guest.u64RAX %RX64\n", pVMCB->guest.u64RAX));
1386 Log(("guest.u64RFlags %RX64\n", pVMCB->guest.u64RFlags));
1387
1388 Log(("guest.u64SysEnterCS %RX64\n", pVMCB->guest.u64SysEnterCS));
1389 Log(("guest.u64SysEnterEIP %RX64\n", pVMCB->guest.u64SysEnterEIP));
1390 Log(("guest.u64SysEnterESP %RX64\n", pVMCB->guest.u64SysEnterESP));
1391
1392 Log(("guest.u64EFER %RX64\n", pVMCB->guest.u64EFER));
1393 Log(("guest.u64STAR %RX64\n", pVMCB->guest.u64STAR));
1394 Log(("guest.u64LSTAR %RX64\n", pVMCB->guest.u64LSTAR));
1395 Log(("guest.u64CSTAR %RX64\n", pVMCB->guest.u64CSTAR));
1396 Log(("guest.u64SFMASK %RX64\n", pVMCB->guest.u64SFMASK));
1397 Log(("guest.u64KernelGSBase %RX64\n", pVMCB->guest.u64KernelGSBase));
1398 Log(("guest.u64GPAT %RX64\n", pVMCB->guest.u64GPAT));
1399 Log(("guest.u64DBGCTL %RX64\n", pVMCB->guest.u64DBGCTL));
1400 Log(("guest.u64BR_FROM %RX64\n", pVMCB->guest.u64BR_FROM));
1401 Log(("guest.u64BR_TO %RX64\n", pVMCB->guest.u64BR_TO));
1402 Log(("guest.u64LASTEXCPFROM %RX64\n", pVMCB->guest.u64LASTEXCPFROM));
1403 Log(("guest.u64LASTEXCPTO %RX64\n", pVMCB->guest.u64LASTEXCPTO));
1404
1405#endif
1406 rc = VERR_SVM_UNABLE_TO_START_VM;
1407 VMMR0LogFlushEnable(pVCpu);
1408 goto end;
1409 }
1410
1411 /* Let's first sync back eip, esp, and eflags. */
1412 pCtx->rip = pVMCB->guest.u64RIP;
1413 pCtx->rsp = pVMCB->guest.u64RSP;
1414 pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1415 /* eax is saved/restore across the vmrun instruction */
1416 pCtx->rax = pVMCB->guest.u64RAX;
1417
1418 /* Save all the MSRs that can be changed by the guest without causing a world switch. (fs & gs base are saved with SVM_READ_SELREG) */
1419 pCtx->msrSTAR = pVMCB->guest.u64STAR; /* legacy syscall eip, cs & ss */
1420 pCtx->msrLSTAR = pVMCB->guest.u64LSTAR; /* 64 bits mode syscall rip */
1421 pCtx->msrCSTAR = pVMCB->guest.u64CSTAR; /* compatibility mode syscall rip */
1422 pCtx->msrSFMASK = pVMCB->guest.u64SFMASK; /* syscall flag mask */
1423 pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1424 pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1425 pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1426 pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1427
1428 /* Can be updated behind our back in the nested paging case. */
1429 pCtx->cr2 = pVMCB->guest.u64CR2;
1430
1431 /* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1432 SVM_READ_SELREG(SS, ss);
1433 SVM_READ_SELREG(CS, cs);
1434 SVM_READ_SELREG(DS, ds);
1435 SVM_READ_SELREG(ES, es);
1436 SVM_READ_SELREG(FS, fs);
1437 SVM_READ_SELREG(GS, gs);
1438
1439 /* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1440 SVM_READ_SELREG(LDTR, ldtr);
1441 SVM_READ_SELREG(TR, tr);
1442
1443 pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1444 pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1445
1446 pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1447 pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1448
1449 /* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1450 /* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1451 if ( pVM->hwaccm.s.fNestedPaging
1452 && pCtx->cr3 != pVMCB->guest.u64CR3)
1453 {
1454 CPUMSetGuestCR3(pVCpu, pVMCB->guest.u64CR3);
1455 PGMUpdateCR3(pVCpu, pVMCB->guest.u64CR3);
1456 }
1457
1458 /* Note! NOW IT'S SAFE FOR LOGGING! */
1459 VMMR0LogFlushEnable(pVCpu);
1460
1461 /* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1462 if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1463 {
1464 Log(("uInterruptState %x rip=%RGv\n", pVMCB->ctrl.u64IntShadow, (RTGCPTR)pCtx->rip));
1465 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
1466 }
1467 else
1468 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1469
1470 Log2(("exitCode = %x\n", exitCode));
1471
1472 /* Sync back DR6 as it could have been changed by hitting breakpoints. */
1473 pCtx->dr[6] = pVMCB->guest.u64DR6;
1474 /* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1475 pCtx->dr[7] = pVMCB->guest.u64DR7;
1476
1477 /* Check if an injected event was interrupted prematurely. */
1478 pVCpu->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1479 if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1480 && pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1481 {
1482 Log(("Pending inject %RX64 at %RGv exit=%08x\n", pVCpu->hwaccm.s.Event.intInfo, (RTGCPTR)pCtx->rip, exitCode));
1483
1484#ifdef LOG_ENABLED
1485 SVM_EVENT Event;
1486 Event.au64[0] = pVCpu->hwaccm.s.Event.intInfo;
1487
1488 if ( exitCode == SVM_EXIT_EXCEPTION_E
1489 && Event.n.u8Vector == 0xE)
1490 {
1491 Log(("Double fault!\n"));
1492 }
1493#endif
1494
1495 pVCpu->hwaccm.s.Event.fPending = true;
1496 /* Error code present? (redundant) */
1497 if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1498 pVCpu->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1499 else
1500 pVCpu->hwaccm.s.Event.errCode = 0;
1501 }
1502#ifdef VBOX_WITH_STATISTICS
1503 if (exitCode == SVM_EXIT_NPF)
1504 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitReasonNPF);
1505 else
1506 STAM_COUNTER_INC(&pVCpu->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1507#endif
1508
1509 /* Sync back the TPR if it was changed. */
1510 if (fSyncTPR)
1511 {
1512 if (pVM->hwaccm.s.svm.fTPRPatchingActive)
1513 {
1514 if ((pCtx->msrLSTAR & 0xff) != u8LastTPR)
1515 {
1516 /* Our patch code uses LSTAR for TPR caching. */
1517 rc = PDMApicSetTPR(pVCpu, pCtx->msrLSTAR & 0xff);
1518 AssertRC(rc);
1519 }
1520 }
1521 else
1522 {
1523 if ((u8LastTPR >> 4) != pVMCB->ctrl.IntCtrl.n.u8VTPR)
1524 {
1525 rc = PDMApicSetTPR(pVCpu, pVMCB->ctrl.IntCtrl.n.u8VTPR << 4); /* cr8 bits 3-0 correspond to bits 7-4 of the task priority mmio register. */
1526 AssertRC(rc);
1527 }
1528 }
1529 }
1530
1531 /* Deal with the reason of the VM-exit. */
1532 switch (exitCode)
1533 {
1534 case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1535 case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1536 case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1537 case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1538 case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1539 case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1540 case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1541 case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1542 {
1543 /* Pending trap. */
1544 SVM_EVENT Event;
1545 uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1546
1547 Log2(("Hardware/software interrupt %d\n", vector));
1548 switch (vector)
1549 {
1550 case X86_XCPT_DB:
1551 {
1552 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDB);
1553
1554 /* Note that we don't support guest and host-initiated debugging at the same time. */
1555 Assert(DBGFIsStepping(pVCpu) || CPUMIsHyperDebugStateActive(pVCpu));
1556
1557 rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1558 if (rc == VINF_EM_RAW_GUEST_TRAP)
1559 {
1560 Log(("Trap %x (debug) at %016RX64\n", vector, pCtx->rip));
1561
1562 /* Reinject the exception. */
1563 Event.au64[0] = 0;
1564 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1565 Event.n.u1Valid = 1;
1566 Event.n.u8Vector = X86_XCPT_DB;
1567
1568 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1569
1570 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1571 goto ResumeExecution;
1572 }
1573 /* Return to ring 3 to deal with the debug exit code. */
1574 Log(("Debugger hardware BP at %04x:%RGv (rc=%Rrc)\n", pCtx->cs, pCtx->rip, rc));
1575 break;
1576 }
1577
1578 case X86_XCPT_NM:
1579 {
1580 Log(("#NM fault at %RGv\n", (RTGCPTR)pCtx->rip));
1581
1582 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1583 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1584 rc = CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
1585 if (rc == VINF_SUCCESS)
1586 {
1587 Assert(CPUMIsGuestFPUStateActive(pVCpu));
1588 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowNM);
1589
1590 /* Continue execution. */
1591 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1592 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1593
1594 goto ResumeExecution;
1595 }
1596
1597 Log(("Forward #NM fault to the guest\n"));
1598 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNM);
1599
1600 Event.au64[0] = 0;
1601 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1602 Event.n.u1Valid = 1;
1603 Event.n.u8Vector = X86_XCPT_NM;
1604
1605 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1606 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1607 goto ResumeExecution;
1608 }
1609
1610 case X86_XCPT_PF: /* Page fault */
1611 {
1612 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1613 RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1614
1615#ifdef DEBUG
1616 if (pVM->hwaccm.s.fNestedPaging)
1617 { /* A genuine pagefault.
1618 * Forward the trap to the guest by injecting the exception and resuming execution.
1619 */
1620 Log(("Guest page fault at %04X:%RGv cr2=%RGv error code %x rsp=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1621 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1622
1623 /* Now we must update CR2. */
1624 pCtx->cr2 = uFaultAddress;
1625
1626 Event.au64[0] = 0;
1627 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1628 Event.n.u1Valid = 1;
1629 Event.n.u8Vector = X86_XCPT_PF;
1630 Event.n.u1ErrorCodeValid = 1;
1631 Event.n.u32ErrorCode = errCode;
1632
1633 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1634
1635 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1636 goto ResumeExecution;
1637 }
1638#endif
1639 Assert(!pVM->hwaccm.s.fNestedPaging);
1640
1641#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1642 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1643 if ( pVM->hwaccm.s.fTRPPatchingAllowed
1644 && (uFaultAddress & 0xfff) == 0x080
1645 && !(errCode & X86_TRAP_PF_P) /* not present */
1646 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1647 && !CPUMIsGuestInLongModeEx(pCtx)
1648 && pVM->hwaccm.s.svm.cPatches < RT_ELEMENTS(pVM->hwaccm.s.svm.aPatches))
1649 {
1650 RTGCPHYS GCPhysApicBase, GCPhys;
1651 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1652 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1653
1654 rc = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL, &GCPhys);
1655 if ( rc == VINF_SUCCESS
1656 && GCPhys == GCPhysApicBase)
1657 {
1658 /* Only attempt to patch the instruction once. */
1659 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.svm.PatchTree, (AVLOU32KEY)pCtx->eip);
1660 if (!pPatch)
1661 {
1662 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1663 break;
1664 }
1665 }
1666 }
1667#endif
1668
1669 Log2(("Page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1670 /* Exit qualification contains the linear address of the page fault. */
1671 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1672 TRPMSetErrorCode(pVCpu, errCode);
1673 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1674
1675 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1676 rc = PGMTrap0eHandler(pVCpu, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1677 Log2(("PGMTrap0eHandler %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1678 if (rc == VINF_SUCCESS)
1679 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1680 Log2(("Shadow page fault at %RGv cr2=%RGv error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1681 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1682
1683 TRPMResetTrap(pVCpu);
1684
1685 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1686 goto ResumeExecution;
1687 }
1688 else
1689 if (rc == VINF_EM_RAW_GUEST_TRAP)
1690 { /* A genuine pagefault.
1691 * Forward the trap to the guest by injecting the exception and resuming execution.
1692 */
1693 Log2(("Forward page fault to the guest\n"));
1694 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestPF);
1695 /* The error code might have been changed. */
1696 errCode = TRPMGetErrorCode(pVCpu);
1697
1698 TRPMResetTrap(pVCpu);
1699
1700 /* Now we must update CR2. */
1701 pCtx->cr2 = uFaultAddress;
1702
1703 Event.au64[0] = 0;
1704 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1705 Event.n.u1Valid = 1;
1706 Event.n.u8Vector = X86_XCPT_PF;
1707 Event.n.u1ErrorCodeValid = 1;
1708 Event.n.u32ErrorCode = errCode;
1709
1710 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1711
1712 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1713 goto ResumeExecution;
1714 }
1715#ifdef VBOX_STRICT
1716 if (rc != VINF_EM_RAW_EMULATE_INSTR && rc != VINF_EM_RAW_EMULATE_IO_BLOCK)
1717 LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1718#endif
1719 /* Need to go back to the recompiler to emulate the instruction. */
1720 TRPMResetTrap(pVCpu);
1721 break;
1722 }
1723
1724 case X86_XCPT_MF: /* Floating point exception. */
1725 {
1726 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestMF);
1727 if (!(pCtx->cr0 & X86_CR0_NE))
1728 {
1729 /* old style FPU error reporting needs some extra work. */
1730 /** @todo don't fall back to the recompiler, but do it manually. */
1731 rc = VINF_EM_RAW_EMULATE_INSTR;
1732 break;
1733 }
1734 Log(("Trap %x at %RGv\n", vector, (RTGCPTR)pCtx->rip));
1735
1736 Event.au64[0] = 0;
1737 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1738 Event.n.u1Valid = 1;
1739 Event.n.u8Vector = X86_XCPT_MF;
1740
1741 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1742
1743 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1744 goto ResumeExecution;
1745 }
1746
1747#ifdef VBOX_STRICT
1748 case X86_XCPT_GP: /* General protection failure exception.*/
1749 case X86_XCPT_UD: /* Unknown opcode exception. */
1750 case X86_XCPT_DE: /* Divide error. */
1751 case X86_XCPT_SS: /* Stack segment exception. */
1752 case X86_XCPT_NP: /* Segment not present exception. */
1753 {
1754 Event.au64[0] = 0;
1755 Event.n.u3Type = SVM_EVENT_EXCEPTION;
1756 Event.n.u1Valid = 1;
1757 Event.n.u8Vector = vector;
1758
1759 switch(vector)
1760 {
1761 case X86_XCPT_GP:
1762 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestGP);
1763 Event.n.u1ErrorCodeValid = 1;
1764 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1765 break;
1766 case X86_XCPT_DE:
1767 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestDE);
1768 break;
1769 case X86_XCPT_UD:
1770 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestUD);
1771 break;
1772 case X86_XCPT_SS:
1773 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestSS);
1774 Event.n.u1ErrorCodeValid = 1;
1775 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1776 break;
1777 case X86_XCPT_NP:
1778 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitGuestNP);
1779 Event.n.u1ErrorCodeValid = 1;
1780 Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1781 break;
1782 }
1783 Log(("Trap %x at %04x:%RGv esi=%x\n", vector, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->esi));
1784 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
1785
1786 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1787 goto ResumeExecution;
1788 }
1789#endif
1790 default:
1791 AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1792 rc = VERR_EM_INTERNAL_ERROR;
1793 break;
1794
1795 } /* switch (vector) */
1796 break;
1797 }
1798
1799 case SVM_EXIT_NPF:
1800 {
1801 /* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1802 uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1803 RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1804 PGMMODE enmShwPagingMode;
1805
1806 Assert(pVM->hwaccm.s.fNestedPaging);
1807 LogFlow(("Nested page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1808
1809#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
1810 /* Shortcut for APIC TPR reads and writes; 32 bits guests only */
1811 if ( pVM->hwaccm.s.fTRPPatchingAllowed
1812 && (uFaultAddress & 0xfff) == 0x080
1813 && !(errCode & X86_TRAP_PF_P) /* not present */
1814 && CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx)) == 0
1815 && !CPUMIsGuestInLongModeEx(pCtx)
1816 && pVM->hwaccm.s.svm.cPatches < RT_ELEMENTS(pVM->hwaccm.s.svm.aPatches))
1817 {
1818 RTGCPHYS GCPhysApicBase;
1819 PDMApicGetBase(pVM, &GCPhysApicBase); /* @todo cache this */
1820 GCPhysApicBase &= PAGE_BASE_GC_MASK;
1821
1822 if (uFaultAddress == GCPhysApicBase + 0x80)
1823 {
1824 /* Only attempt to patch the instruction once. */
1825 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.svm.PatchTree, (AVLOU32KEY)pCtx->eip);
1826 if (!pPatch)
1827 {
1828 rc = VINF_EM_HWACCM_PATCH_TPR_INSTR;
1829 break;
1830 }
1831 }
1832 }
1833#endif
1834
1835 /* Exit qualification contains the linear address of the page fault. */
1836 TRPMAssertTrap(pVCpu, X86_XCPT_PF, TRPM_TRAP);
1837 TRPMSetErrorCode(pVCpu, errCode);
1838 TRPMSetFaultAddress(pVCpu, uFaultAddress);
1839
1840 /* Handle the pagefault trap for the nested shadow table. */
1841#if HC_ARCH_BITS == 32
1842 if (CPUMIsGuestInLongModeEx(pCtx))
1843 enmShwPagingMode = PGMMODE_AMD64_NX;
1844 else
1845#endif
1846 enmShwPagingMode = PGMGetHostMode(pVM);
1847
1848 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmShwPagingMode, errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1849 Log2(("PGMR0Trap0eHandlerNestedPaging %RGv returned %Rrc\n", (RTGCPTR)pCtx->rip, rc));
1850 if (rc == VINF_SUCCESS)
1851 { /* We've successfully synced our shadow pages, so let's just continue execution. */
1852 Log2(("Shadow page fault at %RGv cr2=%RGp error code %x\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode));
1853 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitShadowPF);
1854
1855 TRPMResetTrap(pVCpu);
1856
1857 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1858 goto ResumeExecution;
1859 }
1860
1861#ifdef VBOX_STRICT
1862 if (rc != VINF_EM_RAW_EMULATE_INSTR)
1863 LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1864#endif
1865 /* Need to go back to the recompiler to emulate the instruction. */
1866 TRPMResetTrap(pVCpu);
1867 break;
1868 }
1869
1870 case SVM_EXIT_VINTR:
1871 /* A virtual interrupt is about to be delivered, which means IF=1. */
1872 Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1873 pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1874 pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1875 goto ResumeExecution;
1876
1877 case SVM_EXIT_FERR_FREEZE:
1878 case SVM_EXIT_INTR:
1879 case SVM_EXIT_NMI:
1880 case SVM_EXIT_SMI:
1881 case SVM_EXIT_INIT:
1882 /* External interrupt; leave to allow it to be dispatched again. */
1883 rc = VINF_EM_RAW_INTERRUPT;
1884 break;
1885
1886 case SVM_EXIT_WBINVD:
1887 case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1888 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvd);
1889 /* Skip instruction and continue directly. */
1890 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1891 /* Continue execution.*/
1892 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1893 goto ResumeExecution;
1894
1895 case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1896 {
1897 Log2(("SVM: Cpuid at %RGv for %x\n", (RTGCPTR)pCtx->rip, pCtx->eax));
1898 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCpuid);
1899 rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1900 if (rc == VINF_SUCCESS)
1901 {
1902 /* Update EIP and continue execution. */
1903 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1904 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1905 goto ResumeExecution;
1906 }
1907 AssertMsgFailed(("EMU: cpuid failed with %Rrc\n", rc));
1908 rc = VINF_EM_RAW_EMULATE_INSTR;
1909 break;
1910 }
1911
1912 case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1913 {
1914 Log2(("SVM: Rdtsc\n"));
1915 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1916 rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1917 if (rc == VINF_SUCCESS)
1918 {
1919 /* Update EIP and continue execution. */
1920 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1921 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1922 goto ResumeExecution;
1923 }
1924 rc = VINF_EM_RAW_EMULATE_INSTR;
1925 break;
1926 }
1927
1928 case SVM_EXIT_RDPMC: /* Guest software attempted to execute RDPMC. */
1929 {
1930 Log2(("SVM: Rdpmc %x\n", pCtx->ecx));
1931 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdpmc);
1932 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
1933 if (rc == VINF_SUCCESS)
1934 {
1935 /* Update EIP and continue execution. */
1936 pCtx->rip += 2; /* Note! hardcoded opcode size! */
1937 goto ResumeExecution;
1938 }
1939 rc = VINF_EM_RAW_EMULATE_INSTR;
1940 break;
1941 }
1942
1943 case SVM_EXIT_RDTSCP: /* Guest software attempted to execute RDTSCP. */
1944 {
1945 Log2(("SVM: Rdtscp\n"));
1946 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitRdtsc);
1947 rc = EMInterpretRdtscp(pVM, pVCpu, pCtx);
1948 if (rc == VINF_SUCCESS)
1949 {
1950 /* Update EIP and continue execution. */
1951 pCtx->rip += 3; /* Note! hardcoded opcode size! */
1952 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
1953 goto ResumeExecution;
1954 }
1955 AssertMsgFailed(("EMU: rdtscp failed with %Rrc\n", rc));
1956 rc = VINF_EM_RAW_EMULATE_INSTR;
1957 break;
1958 }
1959
1960 case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1961 {
1962 Log2(("SVM: invlpg\n"));
1963 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitInvpg);
1964
1965 Assert(!pVM->hwaccm.s.fNestedPaging);
1966
1967 /* Truly a pita. Why can't SVM give the same information as VT-x? */
1968 rc = svmR0InterpretInvpg(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1969 if (rc == VINF_SUCCESS)
1970 {
1971 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushPageInvlpg);
1972 goto ResumeExecution; /* eip already updated */
1973 }
1974 break;
1975 }
1976
1977 case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1978 case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1979 case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1980 case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1981 {
1982 uint32_t cbSize;
1983
1984 Log2(("SVM: %RGv mov cr%d, \n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
1985 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxWrite[exitCode - SVM_EXIT_WRITE_CR0]);
1986 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
1987
1988 switch (exitCode - SVM_EXIT_WRITE_CR0)
1989 {
1990 case 0:
1991 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR0;
1992 break;
1993 case 2:
1994 break;
1995 case 3:
1996 Assert(!pVM->hwaccm.s.fNestedPaging);
1997 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR3;
1998 break;
1999 case 4:
2000 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_CR4;
2001 break;
2002 case 8:
2003 break;
2004 default:
2005 AssertFailed();
2006 }
2007 /* Check if a sync operation is pending. */
2008 if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
2009 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2010 {
2011 rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2012 AssertRC(rc);
2013
2014 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBCRxChange);
2015
2016 /* Must be set by PGMSyncCR3 */
2017 AssertMsg(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3 || PGMGetGuestMode(pVCpu) <= PGMMODE_PROTECTED || pVCpu->hwaccm.s.fForceTLBFlush,
2018 ("rc=%Rrc mode=%d fForceTLBFlush=%RTbool\n", rc, PGMGetGuestMode(pVCpu), pVCpu->hwaccm.s.fForceTLBFlush));
2019 }
2020 if (rc == VINF_SUCCESS)
2021 {
2022 /* EIP has been updated already. */
2023
2024 /* Only resume if successful. */
2025 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2026 goto ResumeExecution;
2027 }
2028 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2029 break;
2030 }
2031
2032 case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
2033 case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
2034 case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
2035 case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
2036 {
2037 uint32_t cbSize;
2038
2039 Log2(("SVM: %RGv mov x, cr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
2040 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitCRxRead[exitCode - SVM_EXIT_READ_CR0]);
2041 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2042 if (rc == VINF_SUCCESS)
2043 {
2044 /* EIP has been updated already. */
2045
2046 /* Only resume if successful. */
2047 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2048 goto ResumeExecution;
2049 }
2050 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2051 break;
2052 }
2053
2054 case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
2055 case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
2056 case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
2057 case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
2058 {
2059 uint32_t cbSize;
2060
2061 Log2(("SVM: %RGv mov dr%d, x\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
2062 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxWrite);
2063
2064 if ( !DBGFIsStepping(pVCpu)
2065 && !CPUMIsHyperDebugStateActive(pVCpu))
2066 {
2067 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2068
2069 /* Disable drx move intercepts. */
2070 pVMCB->ctrl.u16InterceptRdDRx = 0;
2071 pVMCB->ctrl.u16InterceptWrDRx = 0;
2072
2073 /* Save the host and load the guest debug state. */
2074 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2075 AssertRC(rc);
2076
2077 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2078 goto ResumeExecution;
2079 }
2080
2081 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2082 if (rc == VINF_SUCCESS)
2083 {
2084 /* EIP has been updated already. */
2085 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2086
2087 /* Only resume if successful. */
2088 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2089 goto ResumeExecution;
2090 }
2091 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2092 break;
2093 }
2094
2095 case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
2096 case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
2097 case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
2098 case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
2099 {
2100 uint32_t cbSize;
2101
2102 Log2(("SVM: %RGv mov x, dr%d\n", (RTGCPTR)pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
2103 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitDRxRead);
2104
2105 if (!DBGFIsStepping(pVCpu))
2106 {
2107 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxContextSwitch);
2108
2109 /* Disable drx move intercepts. */
2110 pVMCB->ctrl.u16InterceptRdDRx = 0;
2111 pVMCB->ctrl.u16InterceptWrDRx = 0;
2112
2113 /* Save the host and load the guest debug state. */
2114 rc = CPUMR0LoadGuestDebugState(pVM, pVCpu, pCtx, false /* exclude DR6 */);
2115 AssertRC(rc);
2116
2117 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2118 goto ResumeExecution;
2119 }
2120
2121 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2122 if (rc == VINF_SUCCESS)
2123 {
2124 /* EIP has been updated already. */
2125
2126 /* Only resume if successful. */
2127 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2128 goto ResumeExecution;
2129 }
2130 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
2131 break;
2132 }
2133
2134 /* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
2135 case SVM_EXIT_IOIO: /* I/O instruction. */
2136 {
2137 SVM_IOIO_EXIT IoExitInfo;
2138 uint32_t uIOSize, uAndVal;
2139
2140 IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
2141
2142 /** @todo could use a lookup table here */
2143 if (IoExitInfo.n.u1OP8)
2144 {
2145 uIOSize = 1;
2146 uAndVal = 0xff;
2147 }
2148 else
2149 if (IoExitInfo.n.u1OP16)
2150 {
2151 uIOSize = 2;
2152 uAndVal = 0xffff;
2153 }
2154 else
2155 if (IoExitInfo.n.u1OP32)
2156 {
2157 uIOSize = 4;
2158 uAndVal = 0xffffffff;
2159 }
2160 else
2161 {
2162 AssertFailed(); /* should be fatal. */
2163 rc = VINF_EM_RAW_EMULATE_INSTR;
2164 break;
2165 }
2166
2167 if (IoExitInfo.n.u1STR)
2168 {
2169 /* ins/outs */
2170 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2171
2172 /* Disassemble manually to deal with segment prefixes. */
2173 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, NULL);
2174 if (rc == VINF_SUCCESS)
2175 {
2176 if (IoExitInfo.n.u1Type == 0)
2177 {
2178 Log2(("IOMInterpretOUTSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2179 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringWrite);
2180 rc = VBOXSTRICTRC_TODO(IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize));
2181 }
2182 else
2183 {
2184 Log2(("IOMInterpretINSEx %RGv %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2185 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOStringRead);
2186 rc = VBOXSTRICTRC_TODO(IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->prefix, uIOSize));
2187 }
2188 }
2189 else
2190 rc = VINF_EM_RAW_EMULATE_INSTR;
2191 }
2192 else
2193 {
2194 /* normal in/out */
2195 Assert(!IoExitInfo.n.u1REP);
2196
2197 if (IoExitInfo.n.u1Type == 0)
2198 {
2199 Log2(("IOMIOPortWrite %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2200 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIOWrite);
2201 rc = VBOXSTRICTRC_TODO(IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
2202 if (rc == VINF_IOM_HC_IOPORT_WRITE)
2203 HWACCMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2204 }
2205 else
2206 {
2207 uint32_t u32Val = 0;
2208
2209 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitIORead);
2210 rc = VBOXSTRICTRC_TODO(IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize));
2211 if (IOM_SUCCESS(rc))
2212 {
2213 /* Write back to the EAX register. */
2214 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2215 Log2(("IOMIOPortRead %RGv %x %x size=%d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
2216 }
2217 else
2218 if (rc == VINF_IOM_HC_IOPORT_READ)
2219 HWACCMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVMCB->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, uIOSize);
2220 }
2221 }
2222 /*
2223 * Handled the I/O return codes.
2224 * (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
2225 */
2226 if (IOM_SUCCESS(rc))
2227 {
2228 /* Update EIP and continue execution. */
2229 pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
2230 if (RT_LIKELY(rc == VINF_SUCCESS))
2231 {
2232 /* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
2233 if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
2234 {
2235 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDRxIOCheck);
2236 for (unsigned i=0;i<4;i++)
2237 {
2238 unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
2239
2240 if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
2241 && (pCtx->dr[7] & (X86_DR7_L(i) | X86_DR7_G(i)))
2242 && (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
2243 {
2244 SVM_EVENT Event;
2245
2246 Assert(CPUMIsGuestDebugStateActive(pVCpu));
2247
2248 /* Clear all breakpoint status flags and set the one we just hit. */
2249 pCtx->dr[6] &= ~(X86_DR6_B0|X86_DR6_B1|X86_DR6_B2|X86_DR6_B3);
2250 pCtx->dr[6] |= (uint64_t)RT_BIT(i);
2251
2252 /* Note: AMD64 Architecture Programmer's Manual 13.1:
2253 * Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
2254 * the contents have been read.
2255 */
2256 pVMCB->guest.u64DR6 = pCtx->dr[6];
2257
2258 /* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
2259 pCtx->dr[7] &= ~X86_DR7_GD;
2260
2261 /* Paranoia. */
2262 pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
2263 pCtx->dr[7] &= ~(RT_BIT(11) | RT_BIT(12) | RT_BIT(14) | RT_BIT(15)); /* must be zero */
2264 pCtx->dr[7] |= 0x400; /* must be one */
2265
2266 pVMCB->guest.u64DR7 = pCtx->dr[7];
2267
2268 /* Inject the exception. */
2269 Log(("Inject IO debug trap at %RGv\n", (RTGCPTR)pCtx->rip));
2270
2271 Event.au64[0] = 0;
2272 Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
2273 Event.n.u1Valid = 1;
2274 Event.n.u8Vector = X86_XCPT_DB;
2275
2276 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2277
2278 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2279 goto ResumeExecution;
2280 }
2281 }
2282 }
2283
2284 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2285 goto ResumeExecution;
2286 }
2287 Log2(("EM status from IO at %RGv %x size %d: %Rrc\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
2288 break;
2289 }
2290
2291#ifdef VBOX_STRICT
2292 if (rc == VINF_IOM_HC_IOPORT_READ)
2293 Assert(IoExitInfo.n.u1Type != 0);
2294 else if (rc == VINF_IOM_HC_IOPORT_WRITE)
2295 Assert(IoExitInfo.n.u1Type == 0);
2296 else
2297 AssertMsg(RT_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", rc));
2298#endif
2299 Log2(("Failed IO at %RGv %x size %d\n", (RTGCPTR)pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
2300 break;
2301 }
2302
2303 case SVM_EXIT_HLT:
2304 /** Check if external interrupts are pending; if so, don't switch back. */
2305 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitHlt);
2306 pCtx->rip++; /* skip hlt */
2307 if ( pCtx->eflags.Bits.u1IF
2308 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
2309 goto ResumeExecution;
2310
2311 rc = VINF_EM_HALT;
2312 break;
2313
2314 case SVM_EXIT_MWAIT_UNCOND:
2315 Log2(("SVM: mwait\n"));
2316 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatExitMwait);
2317 rc = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
2318 if ( rc == VINF_EM_HALT
2319 || rc == VINF_SUCCESS)
2320 {
2321 /* Update EIP and continue execution. */
2322 pCtx->rip += 3; /* Note: hardcoded opcode size assumption! */
2323
2324 /** Check if external interrupts are pending; if so, don't switch back. */
2325 if ( rc == VINF_SUCCESS
2326 || ( rc == VINF_EM_HALT
2327 && pCtx->eflags.Bits.u1IF
2328 && VMCPU_FF_ISPENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC|VMCPU_FF_INTERRUPT_PIC)))
2329 )
2330 goto ResumeExecution;
2331 }
2332 AssertMsg(rc == VERR_EM_INTERPRETER || rc == VINF_EM_HALT, ("EMU: mwait failed with %Rrc\n", rc));
2333 break;
2334
2335 case SVM_EXIT_VMMCALL:
2336 rc = svmR0EmulateTprVMMCall(pVM, pVCpu, pCtx);
2337 if (rc == VINF_SUCCESS)
2338 {
2339 goto ResumeExecution; /* rip already updated. */
2340 }
2341 /* no break */
2342
2343 case SVM_EXIT_RSM:
2344 case SVM_EXIT_INVLPGA:
2345 case SVM_EXIT_VMRUN:
2346 case SVM_EXIT_VMLOAD:
2347 case SVM_EXIT_VMSAVE:
2348 case SVM_EXIT_STGI:
2349 case SVM_EXIT_CLGI:
2350 case SVM_EXIT_SKINIT:
2351 {
2352 /* Unsupported instructions. */
2353 SVM_EVENT Event;
2354
2355 Event.au64[0] = 0;
2356 Event.n.u3Type = SVM_EVENT_EXCEPTION;
2357 Event.n.u1Valid = 1;
2358 Event.n.u8Vector = X86_XCPT_UD;
2359
2360 Log(("Forced #UD trap at %RGv\n", (RTGCPTR)pCtx->rip));
2361 SVMR0InjectEvent(pVCpu, pVMCB, pCtx, &Event);
2362
2363 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2364 goto ResumeExecution;
2365 }
2366
2367 /* Emulate in ring 3. */
2368 case SVM_EXIT_MSR:
2369 {
2370 uint32_t cbSize;
2371
2372 /* When an interrupt is pending, we'll let MSR_K8_LSTAR writes fault in our TPR patch code. */
2373 if ( pVM->hwaccm.s.svm.fTPRPatchingActive
2374 && pCtx->ecx == MSR_K8_LSTAR
2375 && pVMCB->ctrl.u64ExitInfo1 == 1 /* wrmsr */)
2376 {
2377 if ((pCtx->eax & 0xff) != u8LastTPR)
2378 {
2379 Log(("SVM: Faulting MSR_K8_LSTAR write with new TPR value %x\n", pCtx->eax & 0xff));
2380
2381 /* Our patch code uses LSTAR for TPR caching. */
2382 rc = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
2383 AssertRC(rc);
2384 }
2385
2386 /* Skip the instruction and continue. */
2387 pCtx->rip += 2; /* wrmsr = [0F 30] */
2388
2389 /* Only resume if successful. */
2390 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2391 goto ResumeExecution;
2392 }
2393
2394 /* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
2395 STAM_COUNTER_INC((pVMCB->ctrl.u64ExitInfo1 == 0) ? &pVCpu->hwaccm.s.StatExitRdmsr : &pVCpu->hwaccm.s.StatExitWrmsr);
2396 Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
2397 rc = EMInterpretInstruction(pVM, pVCpu, CPUMCTX2CORE(pCtx), 0, &cbSize);
2398 if (rc == VINF_SUCCESS)
2399 {
2400 /* EIP has been updated already. */
2401
2402 /* Only resume if successful. */
2403 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2404 goto ResumeExecution;
2405 }
2406 AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Rrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
2407 break;
2408 }
2409
2410 case SVM_EXIT_MONITOR:
2411 case SVM_EXIT_PAUSE:
2412 case SVM_EXIT_MWAIT_ARMED:
2413 case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
2414 rc = VERR_EM_INTERPRETER;
2415 break;
2416
2417 case SVM_EXIT_SHUTDOWN:
2418 rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2419 break;
2420
2421 case SVM_EXIT_IDTR_READ:
2422 case SVM_EXIT_GDTR_READ:
2423 case SVM_EXIT_LDTR_READ:
2424 case SVM_EXIT_TR_READ:
2425 case SVM_EXIT_IDTR_WRITE:
2426 case SVM_EXIT_GDTR_WRITE:
2427 case SVM_EXIT_LDTR_WRITE:
2428 case SVM_EXIT_TR_WRITE:
2429 case SVM_EXIT_CR0_SEL_WRITE:
2430 default:
2431 /* Unexpected exit codes. */
2432 rc = VERR_EM_INTERNAL_ERROR;
2433 AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2434 break;
2435 }
2436
2437end:
2438
2439 /* Signal changes for the recompiler. */
2440 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR | CPUM_CHANGED_LDTR | CPUM_CHANGED_GDTR | CPUM_CHANGED_IDTR | CPUM_CHANGED_TR | CPUM_CHANGED_HIDDEN_SEL_REGS);
2441
2442 /* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
2443 if (exitCode == SVM_EXIT_INTR)
2444 {
2445 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatPendingHostIrq);
2446 /* On the next entry we'll only sync the host context. */
2447 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_HOST_CONTEXT;
2448 }
2449 else
2450 {
2451 /* On the next entry we'll sync everything. */
2452 /** @todo we can do better than this */
2453 /* Not in the VINF_PGM_CHANGE_MODE though! */
2454 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL;
2455 }
2456
2457 /* translate into a less severe return code */
2458 if (rc == VERR_EM_INTERPRETER)
2459 rc = VINF_EM_RAW_EMULATE_INSTR;
2460
2461 /* Just set the correct state here instead of trying to catch every goto above. */
2462 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC);
2463
2464#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
2465 /* Restore interrupts if we exitted after disabling them. */
2466 if (uOldEFlags != ~(RTCCUINTREG)0)
2467 ASMSetFlags(uOldEFlags);
2468#endif
2469
2470 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatExit1, x);
2471 return rc;
2472}
2473
2474/**
2475 * Emulate simple mov tpr instruction
2476 *
2477 * @returns VBox status code.
2478 * @param pVM The VM to operate on.
2479 * @param pVCpu The VM CPU to operate on.
2480 * @param pCtx CPU context
2481 */
2482static int svmR0EmulateTprVMMCall(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2483{
2484 int rc;
2485
2486 LogFlow(("Emulated VMMCall TPR access replacement at %RGv\n", pCtx->rip));
2487
2488 while (true)
2489 {
2490 bool fPending;
2491 uint8_t u8Tpr;
2492
2493 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.svm.PatchTree, (AVLOU32KEY)pCtx->eip);
2494 if (!pPatch)
2495 break;
2496
2497 switch(pPatch->enmType)
2498 {
2499 case HWACCMTPRINSTR_READ:
2500 /* TPR caching in CR8 */
2501 rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending);
2502 AssertRC(rc);
2503
2504 rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
2505 AssertRC(rc);
2506
2507 LogFlow(("Emulated read successfully\n"));
2508 pCtx->rip += pPatch->cbOp;
2509 break;
2510
2511 case HWACCMTPRINSTR_WRITE_REG:
2512 case HWACCMTPRINSTR_WRITE_IMM:
2513 /* Fetch the new TPR value */
2514 if (pPatch->enmType == HWACCMTPRINSTR_WRITE_REG)
2515 {
2516 uint32_t val;
2517
2518 rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &val);
2519 AssertRC(rc);
2520 u8Tpr = val;
2521 }
2522 else
2523 u8Tpr = (uint8_t)pPatch->uSrcOperand;
2524
2525 rc = PDMApicSetTPR(pVCpu, u8Tpr);
2526 AssertRC(rc);
2527 LogFlow(("Emulated write successfully\n"));
2528 pCtx->rip += pPatch->cbOp;
2529 break;
2530 default:
2531 AssertMsgFailedReturn(("Unexpected type %d\n", pPatch->enmType), VERR_INTERNAL_ERROR);
2532 }
2533 }
2534 return VINF_SUCCESS;
2535}
2536
2537
2538/**
2539 * Enters the AMD-V session
2540 *
2541 * @returns VBox status code.
2542 * @param pVM The VM to operate on.
2543 * @param pVCpu The VM CPU to operate on.
2544 * @param pCpu CPU info struct
2545 */
2546VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
2547{
2548 Assert(pVM->hwaccm.s.svm.fSupported);
2549
2550 LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVCpu->hwaccm.s.idLastCpu, pVCpu->hwaccm.s.uCurrentASID));
2551 pVCpu->hwaccm.s.fResumeVM = false;
2552
2553 /* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2554 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_LDTR;
2555
2556 return VINF_SUCCESS;
2557}
2558
2559
2560/**
2561 * Leaves the AMD-V session
2562 *
2563 * @returns VBox status code.
2564 * @param pVM The VM to operate on.
2565 * @param pVCpu The VM CPU to operate on.
2566 * @param pCtx CPU context
2567 */
2568VMMR0DECL(int) SVMR0Leave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2569{
2570 SVM_VMCB *pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2571
2572 Assert(pVM->hwaccm.s.svm.fSupported);
2573
2574#ifdef DEBUG
2575 if (CPUMIsHyperDebugStateActive(pVCpu))
2576 {
2577 CPUMR0LoadHostDebugState(pVM, pVCpu);
2578 }
2579 else
2580#endif
2581 /* Save the guest debug state if necessary. */
2582 if (CPUMIsGuestDebugStateActive(pVCpu))
2583 {
2584 CPUMR0SaveGuestDebugState(pVM, pVCpu, pCtx, false /* skip DR6 */);
2585
2586 /* Intercept all DRx reads and writes again. Changed later on. */
2587 pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
2588 pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
2589
2590 /* Resync the debug registers the next time. */
2591 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_GUEST_DEBUG;
2592 }
2593 else
2594 Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
2595
2596 return VINF_SUCCESS;
2597}
2598
2599
2600static int svmR0InterpretInvlPg(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2601{
2602 OP_PARAMVAL param1;
2603 RTGCPTR addr;
2604
2605 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2606 if(RT_FAILURE(rc))
2607 return VERR_EM_INTERPRETER;
2608
2609 switch(param1.type)
2610 {
2611 case PARMTYPE_IMMEDIATE:
2612 case PARMTYPE_ADDRESS:
2613 if(!(param1.flags & (PARAM_VAL32|PARAM_VAL64)))
2614 return VERR_EM_INTERPRETER;
2615 addr = param1.val.val64;
2616 break;
2617
2618 default:
2619 return VERR_EM_INTERPRETER;
2620 }
2621
2622 /** @todo is addr always a flat linear address or ds based
2623 * (in absence of segment override prefixes)????
2624 */
2625 rc = PGMInvalidatePage(pVCpu, addr);
2626 if (RT_SUCCESS(rc))
2627 {
2628 /* Manually invalidate the page for the VM's TLB. */
2629 Log(("SVMR0InvlpgA %RGv ASID=%d\n", addr, uASID));
2630 SVMR0InvlpgA(addr, uASID);
2631 return VINF_SUCCESS;
2632 }
2633 AssertRC(rc);
2634 return rc;
2635}
2636
2637/**
2638 * Interprets INVLPG
2639 *
2640 * @returns VBox status code.
2641 * @retval VINF_* Scheduling instructions.
2642 * @retval VERR_EM_INTERPRETER Something we can't cope with.
2643 * @retval VERR_* Fatal errors.
2644 *
2645 * @param pVM The VM handle.
2646 * @param pRegFrame The register frame.
2647 * @param ASID Tagged TLB id for the guest
2648 *
2649 * Updates the EIP if an instruction was executed successfully.
2650 */
2651static int svmR0InterpretInvpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2652{
2653 /*
2654 * Only allow 32 & 64 bits code.
2655 */
2656 DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2657 if (enmMode != CPUMODE_16BIT)
2658 {
2659 RTGCPTR pbCode;
2660 int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2661 if (RT_SUCCESS(rc))
2662 {
2663 uint32_t cbOp;
2664 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
2665
2666 pDis->mode = enmMode;
2667 rc = EMInterpretDisasOneEx(pVM, pVCpu, pbCode, pRegFrame, pDis, &cbOp);
2668 Assert(RT_FAILURE(rc) || pDis->pCurInstr->opcode == OP_INVLPG);
2669 if (RT_SUCCESS(rc) && pDis->pCurInstr->opcode == OP_INVLPG)
2670 {
2671 Assert(cbOp == pDis->opsize);
2672 rc = svmR0InterpretInvlPg(pVCpu, pDis, pRegFrame, uASID);
2673 if (RT_SUCCESS(rc))
2674 {
2675 pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2676 }
2677 return rc;
2678 }
2679 }
2680 }
2681 return VERR_EM_INTERPRETER;
2682}
2683
2684
2685/**
2686 * Invalidates a guest page
2687 *
2688 * @returns VBox status code.
2689 * @param pVM The VM to operate on.
2690 * @param pVCpu The VM CPU to operate on.
2691 * @param GCVirt Page to invalidate
2692 */
2693VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
2694{
2695 bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB | VMCPU_FF_ISSET(pVCpu, VMCPU_FF_TLB_FLUSH);
2696
2697 /* Skip it if a TLB flush is already pending. */
2698 if (!fFlushPending)
2699 {
2700 SVM_VMCB *pVMCB;
2701
2702 Log2(("SVMR0InvalidatePage %RGv\n", GCVirt));
2703 AssertReturn(pVM, VERR_INVALID_PARAMETER);
2704 Assert(pVM->hwaccm.s.svm.fSupported);
2705
2706 pVMCB = (SVM_VMCB *)pVCpu->hwaccm.s.svm.pVMCB;
2707 AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2708
2709#if HC_ARCH_BITS == 32
2710 /* If we get a flush in 64 bits guest mode, then force a full TLB flush. Invlpga takes only 32 bits addresses. */
2711 if (CPUMIsGuestInLongMode(pVCpu))
2712 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2713 else
2714#endif
2715 SVMR0InvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2716 }
2717 return VINF_SUCCESS;
2718}
2719
2720
2721#if 0 /* obsolete, but left here for clarification. */
2722/**
2723 * Invalidates a guest page by physical address
2724 *
2725 * @returns VBox status code.
2726 * @param pVM The VM to operate on.
2727 * @param pVCpu The VM CPU to operate on.
2728 * @param GCPhys Page to invalidate
2729 */
2730VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
2731{
2732 Assert(pVM->hwaccm.s.fNestedPaging);
2733 /* invlpga only invalidates TLB entries for guest virtual addresses; we have no choice but to force a TLB flush here. */
2734 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2735 STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFlushTLBInvlpga);
2736 return VINF_SUCCESS;
2737}
2738#endif
2739
2740#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2741/**
2742 * Prepares for and executes VMRUN (64 bits guests from a 32 bits hosts).
2743 *
2744 * @returns VBox status code.
2745 * @param pVMCBHostPhys Physical address of host VMCB.
2746 * @param pVMCBPhys Physical address of the VMCB.
2747 * @param pCtx Guest context.
2748 * @param pVM The VM to operate on.
2749 * @param pVCpu The VMCPU to operate on.
2750 */
2751DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
2752{
2753 uint32_t aParam[4];
2754
2755 aParam[0] = (uint32_t)(pVMCBHostPhys); /* Param 1: pVMCBHostPhys - Lo. */
2756 aParam[1] = (uint32_t)(pVMCBHostPhys >> 32); /* Param 1: pVMCBHostPhys - Hi. */
2757 aParam[2] = (uint32_t)(pVMCBPhys); /* Param 2: pVMCBPhys - Lo. */
2758 aParam[3] = (uint32_t)(pVMCBPhys >> 32); /* Param 2: pVMCBPhys - Hi. */
2759
2760 return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSVMGCVMRun64, 4, &aParam[0]);
2761}
2762
2763/**
2764 * Executes the specified handler in 64 mode
2765 *
2766 * @returns VBox status code.
2767 * @param pVM The VM to operate on.
2768 * @param pVCpu The VMCPU to operate on.
2769 * @param pCtx Guest context
2770 * @param pfnHandler RC handler
2771 * @param cbParam Number of parameters
2772 * @param paParam Array of 32 bits parameters
2773 */
2774VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTRCPTR pfnHandler, uint32_t cbParam, uint32_t *paParam)
2775{
2776 int rc;
2777 RTHCUINTREG uOldEFlags;
2778
2779 /* @todo This code is not guest SMP safe (hyper stack and switchers) */
2780 AssertReturn(pVM->cCpus == 1, VERR_TOO_MANY_CPUS);
2781 Assert(pfnHandler);
2782
2783 /* Disable interrupts. */
2784 uOldEFlags = ASMIntDisableFlags();
2785
2786 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVM));
2787 CPUMSetHyperEIP(pVCpu, pfnHandler);
2788 for (int i=(int)cbParam-1;i>=0;i--)
2789 CPUMPushHyper(pVCpu, paParam[i]);
2790
2791 STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2792 /* Call switcher. */
2793 rc = pVM->hwaccm.s.pfnHost32ToGuest64R0(pVM);
2794 STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
2795
2796 ASMSetFlags(uOldEFlags);
2797 return rc;
2798}
2799
2800#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
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