HWSVMR0.cpp@ 1211

Last change on this file since 1211 was 1211, checked in by vboxsync, 18 years ago
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1	/* $Id: HWSVMR0.cpp 1211 2007-03-05 12:42:11Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/disopcode.h>
40	#include <iprt/param.h>
41	#include <iprt/assert.h>
42	#include <iprt/asm.h>
43	#include "HWSVMR0.h"
44
45	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
46
47	/**
48	* Sets up and activates SVM
49	*
50	* @returns VBox status code.
51	* @param pVM The VM to operate on.
52	*/
53	HWACCMR0DECL(int) SVMR0Setup(PVM pVM)
54	{
55	int rc = VINF_SUCCESS;
56	SVM_VMCB *pVMCB;
57
58	if (pVM == NULL)
59	return VERR_INVALID_PARAMETER;
60
61	/* Setup AMD SVM. */
62	Assert(pVM->hwaccm.s.svm.fSupported);
63
64	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
65	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
66
67	/* Program the control fields. Most of them never have to be changed again. */
68	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
69	/** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
70	pVMCB->ctrl.u16InterceptRdCRx = BIT(0) \| BIT(3) \| BIT(4) \| BIT(8);
71
72	/*
73	* CR0/3/4 writes must be intercepted for obvious reasons.
74	*/
75	pVMCB->ctrl.u16InterceptWrCRx = BIT(0) \| BIT(3) \| BIT(4) \| BIT(8);
76
77	/* Intercept all DRx reads and writes. */
78	pVMCB->ctrl.u16InterceptRdDRx = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \| BIT(6) \| BIT(7);
79	pVMCB->ctrl.u16InterceptWrDRx = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \| BIT(6) \| BIT(7);
80
81	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
82	* All breakpoints are automatically cleared when the VM exits.
83	*/
84
85	/** @todo nested paging */
86	/* Intercept #NM only; #PF is not relevant due to nested paging (we get a seperate exit code (SVM_EXIT_NPF) for
87	* pagefaults that need our attention).
88	*/
89	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
90
91	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
92	\| SVM_CTRL1_INTERCEPT_VINTR
93	\| SVM_CTRL1_INTERCEPT_NMI
94	\| SVM_CTRL1_INTERCEPT_SMI
95	\| SVM_CTRL1_INTERCEPT_INIT
96	\| SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
97	\| SVM_CTRL1_INTERCEPT_RDPMC
98	\| SVM_CTRL1_INTERCEPT_CPUID
99	\| SVM_CTRL1_INTERCEPT_RSM
100	\| SVM_CTRL1_INTERCEPT_HLT
101	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
102	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
103	\| SVM_CTRL1_INTERCEPT_INVLPG
104	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
105	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
106	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
107	;
108	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
109	\| SVM_CTRL2_INTERCEPT_VMMCALL
110	\| SVM_CTRL2_INTERCEPT_VMLOAD
111	\| SVM_CTRL2_INTERCEPT_VMSAVE
112	\| SVM_CTRL2_INTERCEPT_STGI
113	\| SVM_CTRL2_INTERCEPT_CLGI
114	\| SVM_CTRL2_INTERCEPT_SKINIT
115	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
116	;
117	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
118	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
119	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
120
121	/* Virtualize masking of INTR interrupts. */
122	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
123
124	/* Set IO and MSR bitmap addresses. */
125	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
126	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
127
128	/* Enable nested paging. */
129	/** @todo how to detect support for this?? */
130	pVMCB->ctrl.u64NestedPaging = 0; /** @todo SVM_NESTED_PAGING_ENABLE; */
131
132	/* No LBR virtualization. */
133	pVMCB->ctrl.u64LBRVirt = 0;
134
135	return rc;
136	}
137
138
139	/**
140	* Injects an event (trap or external interrupt)
141	*
142	* @param pVM The VM to operate on.
143	* @param pVMCB SVM control block
144	* @param pCtx CPU Context
145	* @param pIntInfo SVM interrupt info
146	*/
147	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
148	{
149	#ifdef VBOX_STRICT
150	if (pEvent->n.u8Vector == 0xE)
151	Log(("SVMR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
152	else
153	if (pEvent->n.u8Vector < 0x20)
154	Log(("SVMR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode));
155	else
156	{
157	Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->eip));
158	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
159	Assert(pCtx->eflags.u32 & X86_EFL_IF);
160	}
161	#endif
162
163	/* Set event injection state. */
164	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
165	}
166
167
168	/**
169	* Checks for pending guest interrupts and injects them
170	*
171	* @returns VBox status code.
172	* @param pVM The VM to operate on.
173	* @param pVMCB SVM control block
174	* @param pCtx CPU Context
175	*/
176	static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx)
177	{
178	int rc;
179
180	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
181	if (pVM->hwaccm.s.Event.fPending)
182	{
183	SVM_EVENT Event;
184
185	Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
186	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
187	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
188	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
189
190	pVM->hwaccm.s.Event.fPending = false;
191	return VINF_SUCCESS;
192	}
193
194	/* When external interrupts are pending, we should exit the VM when IF is set. */
195	if ( !TRPMHasTrap(pVM)
196	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
197	{
198	if (!(pCtx->eflags.u32 & X86_EFL_IF))
199	{
200	Log2(("Enable irq window exit!\n"));
201	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
202	//// pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
203	//// AssertRC(rc);
204	}
205	else
206	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
207	{
208	uint8_t u8Interrupt;
209
210	rc = PDMGetInterrupt(pVM, &u8Interrupt);
211	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
212	if (VBOX_SUCCESS(rc))
213	{
214	rc = TRPMAssertTrap(pVM, u8Interrupt, false);
215	AssertRC(rc);
216	}
217	else
218	{
219	/* can't happen... */
220	AssertFailed();
221	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
222	return VINF_EM_RAW_INTERRUPT_PENDING;
223	}
224	}
225	else
226	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
227	}
228
229	#ifdef VBOX_STRICT
230	if (TRPMHasTrap(pVM))
231	{
232	uint8_t u8Vector;
233	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
234	AssertRC(rc);
235	Assert(u8Vector >= 0x20);
236	}
237	#endif
238
239	if ( pCtx->eflags.u32 & X86_EFL_IF
240	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
241	&& TRPMHasTrap(pVM)
242	)
243	{
244	uint8_t u8Vector;
245	int rc;
246	bool fSoftwareInt;
247	SVM_EVENT Event;
248	uint32_t u32ErrorCode;
249
250	Event.au64[0] = 0;
251
252	/* If a new event is pending, then dispatch it now. */
253	rc = TRPMQueryTrapAll(pVM, &u8Vector, &fSoftwareInt, &u32ErrorCode, 0);
254	AssertRC(rc);
255	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| u8Vector < 0x20);
256	Assert(fSoftwareInt == false);
257
258	/* Clear the pending trap. */
259	rc = TRPMResetTrap(pVM);
260	AssertRC(rc);
261
262	Event.n.u8Vector = u8Vector;
263	Event.n.u1Valid = 1;
264	Event.n.u32ErrorCode = u32ErrorCode;
265
266	switch (u8Vector) {
267	case 8:
268	case 10:
269	case 11:
270	case 12:
271	case 13:
272	case 14:
273	case 17:
274	/* Valid error codes. */
275	Event.n.u1ErrorCodeValid = 1;
276	break;
277	default:
278	break;
279	}
280
281	if (u8Vector == X86_XCPT_NMI)
282	Event.n.u3Type = SVM_EVENT_NMI;
283	else
284	if (u8Vector < 0x20)
285	Event.n.u3Type = SVM_EVENT_EXCEPTION;
286	else
287	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
288
289	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
290	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
291	} /* if (interrupts can be dispatched) */
292
293	return VINF_SUCCESS;
294	}
295
296
297	/**
298	* Loads the guest state
299	*
300	* @returns VBox status code.
301	* @param pVM The VM to operate on.
302	* @param pCtx Guest context
303	*/
304	HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
305	{
306	int rc = VINF_SUCCESS;
307	RTGCUINTPTR val;
308	SVM_VMCB *pVMCB;
309
310	if (pVM == NULL)
311	return VERR_INVALID_PARAMETER;
312
313	/* Setup AMD SVM. */
314	Assert(pVM->hwaccm.s.svm.fSupported);
315
316	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
317	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
318
319	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
320	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
321	{
322	SVM_WRITE_SELREG(CS, cs);
323	Assert(pVMCB->guest.CS.u16Sel \|\| !pVMCB->guest.CS.u16Attr);
324
325	SVM_WRITE_SELREG(SS, ss);
326	Assert(pVMCB->guest.SS.u16Sel \|\| !pVMCB->guest.SS.u16Attr);
327
328	SVM_WRITE_SELREG(DS, ds);
329	Assert(pVMCB->guest.DS.u16Sel \|\| !pVMCB->guest.DS.u16Attr);
330
331	SVM_WRITE_SELREG(ES, es);
332	Assert(pVMCB->guest.ES.u16Sel \|\| !pVMCB->guest.ES.u16Attr);
333
334	SVM_WRITE_SELREG(FS, fs);
335	Assert(pVMCB->guest.FS.u16Sel \|\| !pVMCB->guest.FS.u16Attr);
336
337	SVM_WRITE_SELREG(GS, gs);
338	Assert(pVMCB->guest.GS.u16Sel \|\| !pVMCB->guest.GS.u16Attr);
339	}
340
341	/* Guest CPU context: LDTR. */
342	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
343	{
344	SVM_WRITE_SELREG(LDTR, ldtr);
345	}
346
347	/* Guest CPU context: TR. */
348	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
349	{
350	SVM_WRITE_SELREG(TR, tr);
351	}
352
353	/* Guest CPU context: GDTR. */
354	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
355	{
356	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
357	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
358	}
359
360	/* Guest CPU context: IDTR. */
361	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
362	{
363	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
364	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
365	}
366
367	/*
368	* Sysenter MSRs
369	*/
370	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
371	{
372	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
373	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
374	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
375	}
376
377	/* Control registers */
378	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
379	{
380	val = pCtx->cr0;
381	if (CPUMIsGuestFPUStateActive(pVM) == false)
382	{
383	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
384	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
385	}
386	else
387	{
388	Assert(pVM->hwaccm.s.svm.fResumeVM == true);
389	/** @todo check if we support the old style mess correctly. */
390	if (!(val & X86_CR0_NE))
391	{
392	Log(("Forcing X86_CR0_NE!!!\n"));
393
394	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
395	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
396	{
397	pVMCB->ctrl.u32InterceptException \|= BIT(16);
398	pVM->hwaccm.s.fFPUOldStyleOverride = true;
399	}
400	}
401	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
402	}
403	/* Illegal when cache is turned on. */
404	val &= ~X86_CR0_NW;
405
406	pVMCB->guest.u64CR0 = val;
407	}
408	/* CR2 as well */
409	pVMCB->guest.u64CR2 = pCtx->cr2;
410
411	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
412	{
413	/* Save our shadow CR3 register. */
414	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
415	}
416
417	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
418	{
419	val = pCtx->cr4;
420	switch(pVM->hwaccm.s.enmShadowMode)
421	{
422	case PGMMODE_REAL:
423	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
424	AssertFailed();
425	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
426
427	case PGMMODE_32_BIT: /* 32-bit paging. */
428	break;
429
430	case PGMMODE_PAE: /* PAE paging. */
431	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
432	/** @todo use normal 32 bits paging */
433	val \|= X86_CR4_PAE;
434	break;
435
436	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
437	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
438	AssertFailed();
439	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
440
441	default: /* shut up gcc */
442	AssertFailed();
443	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
444	}
445	pVMCB->guest.u64CR4 = val;
446	}
447
448	/* Debug registers. */
449	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
450	{
451	/** @todo DR0-6 */
452	val = pCtx->dr7;
453	val &= ~(BIT(11) \| BIT(12) \| BIT(14) \| BIT(15)); /* must be zero */
454	val \|= 0x400; /* must be one */
455	#ifdef VBOX_STRICT
456	val = 0x400;
457	#endif
458	pVMCB->guest.u64DR7 = val;
459
460	pVMCB->guest.u64DR6 = pCtx->dr6;
461	}
462
463	/* EIP, ESP and EFLAGS */
464	pVMCB->guest.u64RIP = pCtx->eip;
465	pVMCB->guest.u64RSP = pCtx->esp;
466	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
467
468	/* Set CPL */
469	if (!(pCtx->cr0 & X86_CR0_PE))
470	pVMCB->guest.u8CPL = 0;
471	else
472	if (pCtx->eflags.Bits.u1VM)
473	pVMCB->guest.u8CPL = 3;
474	else
475	pVMCB->guest.u8CPL = (pCtx->ss & X86_SEL_RPL);
476
477	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
478	pVMCB->guest.u64RAX = pCtx->eax;
479
480	/* vmrun will fail otherwise. */
481	pVMCB->guest.u64EFER = MSR_K6_EFER_SVME;
482
483	/** @note We can do more complex things with tagged TLBs. */
484	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
485
486	/** @todo TSC offset. */
487	/** @todo 64 bits stuff (?):
488	* - STAR
489	* - LSTAR
490	* - CSTAR
491	* - SFMASK
492	* - KernelGSBase
493	*/
494
495	/* Done. */
496	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
497
498	return rc;
499	}
500
501
502	/**
503	* Runs guest code in an SVM VM.
504	*
505	* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
506	*
507	* @returns VBox status code.
508	* @param pVM The VM to operate on.
509	* @param pCtx Guest context
510	*/
511	HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
512	{
513	int rc = VINF_SUCCESS;
514	uint64_t exitCode;
515	SVM_VMCB *pVMCB;
516	bool fForceTLBFlush = false;
517	int cResume = 0;
518
519	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
520
521	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
522	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
523
524	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
525	*/
526	ResumeExecution:
527	cResume++;
528
529	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
530	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
531	{
532	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
533	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
534	{
535	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
536	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
537	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
538	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
539	*/
540	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
541	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
542	pVMCB->ctrl.u64IntShadow = 0;
543	}
544	}
545	else
546	{
547	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
548	pVMCB->ctrl.u64IntShadow = 0;
549	}
550
551	/* Check for pending actions that force us to go back to ring 3. */
552	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
553	{
554	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
555	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
556	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
557	rc = VINF_EM_RAW_TO_R3;
558	goto end;
559	}
560	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
561	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
562	{
563	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
564	rc = VINF_EM_PENDING_REQUEST;
565	goto end;
566	}
567
568	/* When external interrupts are pending, we should exit the VM when IF is set. */
569	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
570	rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
571	if (VBOX_FAILURE(rc))
572	{
573	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
574	goto end;
575	}
576
577	/** @todo check timers?? */
578
579	/* Load the guest state */
580	rc = SVMR0LoadGuestState(pVM, pCtx);
581	if (rc != VINF_SUCCESS)
582	{
583	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
584	goto end;
585	}
586
587	/* All done! Let's start VM execution. */
588	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
589	if ( pVM->hwaccm.s.svm.fResumeVM == false
590	\|\| fForceTLBFlush)
591	{
592	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1;
593	}
594	else
595	{
596	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 0;
597	}
598	/* In case we execute a goto ResumeExecution later on. */
599	pVM->hwaccm.s.svm.fResumeVM = true;
600	fForceTLBFlush = false;
601
602	Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
603	Assert(pVMCB->ctrl.u32InterceptCtrl1 == ( SVM_CTRL1_INTERCEPT_INTR
604	\| SVM_CTRL1_INTERCEPT_VINTR
605	\| SVM_CTRL1_INTERCEPT_NMI
606	\| SVM_CTRL1_INTERCEPT_SMI
607	\| SVM_CTRL1_INTERCEPT_INIT
608	\| SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
609	\| SVM_CTRL1_INTERCEPT_RDPMC
610	\| SVM_CTRL1_INTERCEPT_CPUID
611	\| SVM_CTRL1_INTERCEPT_RSM
612	\| SVM_CTRL1_INTERCEPT_HLT
613	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
614	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
615	\| SVM_CTRL1_INTERCEPT_INVLPG
616	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
617	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
618	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE /* Legacy FPU FERR handling. */
619	));
620	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
621	\| SVM_CTRL2_INTERCEPT_VMMCALL
622	\| SVM_CTRL2_INTERCEPT_VMLOAD
623	\| SVM_CTRL2_INTERCEPT_VMSAVE
624	\| SVM_CTRL2_INTERCEPT_STGI
625	\| SVM_CTRL2_INTERCEPT_CLGI
626	\| SVM_CTRL2_INTERCEPT_SKINIT
627	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
628	));
629	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
630	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
631	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
632	Assert(pVMCB->ctrl.u64NestedPaging == 0);
633	Assert(pVMCB->ctrl.u64LBRVirt == 0);
634
635	SVMVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
636	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
637
638	/**
639	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
640	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
641	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
642	*/
643
644	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
645
646	/* Reason for the VM exit */
647	exitCode = pVMCB->ctrl.u64ExitCode;
648
649	if (exitCode == SVM_EXIT_INVALID) /* Invalid guest state. */
650	{
651	HWACCMDumpRegs(pCtx);
652	#ifdef DEBUG
653	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
654	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
655	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
656	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
657	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
658	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
659	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
660	Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
661	Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
662	Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
663
664	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
665	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
666	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
667	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
668
669	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
670	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
671	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
672	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
673	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
674	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
675	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
676	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
677	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
678	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
679
680	Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
681	Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
682	Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
683	Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
684	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
685	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
686	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
687	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
688	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
689	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
690	Log(("ctrl.u64NestedPaging %VX64\n", pVMCB->ctrl.u64NestedPaging));
691	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
692	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
693	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
694	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
695	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
696	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
697
698	Log(("ctrl.u64HostCR3 %VX64\n", pVMCB->ctrl.u64HostCR3));
699	Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
700
701	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
702	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
703	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
704	Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
705	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
706	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
707	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
708	Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
709	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
710	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
711	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
712	Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
713	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
714	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
715	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
716	Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
717	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
718	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
719	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
720	Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
721
722	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
723	Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
724
725	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
726	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
727	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
728	Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
729
730	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
731	Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
732
733	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
734	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
735	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
736	Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
737
738	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
739	Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
740	Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
741	Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
742	Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
743	Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
744	Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
745
746	Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
747	Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
748	Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
749	Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
750
751	Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
752	Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
753	Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
754
755	Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
756	Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
757	Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
758	Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
759	Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
760	Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
761	Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
762	Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
763	Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
764	Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
765	Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
766	Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
767
768	#endif
769	rc = VERR_SVM_UNABLE_TO_START_VM;
770	goto end;
771	}
772
773	/* Let's first sync back eip, esp, and eflags. */
774	pCtx->eip = pVMCB->guest.u64RIP;
775	pCtx->esp = pVMCB->guest.u64RSP;
776	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
777	/* eax is saved/restore across the vmrun instruction */
778	pCtx->eax = pVMCB->guest.u64RAX;
779
780	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
781	SVM_READ_SELREG(SS, ss);
782	SVM_READ_SELREG(CS, cs);
783	SVM_READ_SELREG(DS, ds);
784	SVM_READ_SELREG(ES, es);
785	SVM_READ_SELREG(FS, fs);
786	SVM_READ_SELREG(GS, gs);
787
788	/** @note no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
789
790	/** @note NOW IT'S SAFE FOR LOGGING! */
791
792	/* Take care of instruction fusing (sti, mov ss) */
793	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
794	{
795	Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->eip));
796	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
797	}
798	else
799	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
800
801	Log2(("exitCode = %x\n", exitCode));
802
803	/* Check if an injected event was interrupted prematurely. */
804	pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
805	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
806	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
807	{
808	Log(("Pending inject %VX64 at %08x exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitCode));
809	pVM->hwaccm.s.Event.fPending = true;
810	/* Error code present? (redundant) */
811	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
812	{
813	pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
814	}
815	else
816	pVM->hwaccm.s.Event.errCode = 0;
817	}
818	/** @note Safety precaution; frequent loops have been observed even though external interrupts were pending. */
819	if (cResume > 32 /* low limit, but anything higher risks a hanging host due to interrupts left pending for too long */)
820	{
821	exitCode = SVM_EXIT_INTR;
822	}
823
824	/* Deal with the reason of the VM-exit. */
825	switch (exitCode)
826	{
827	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
828	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
829	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
830	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
831	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
832	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
833	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
834	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
835	{
836	/* Pending trap. */
837	SVM_EVENT Event;
838	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
839
840	Log2(("Hardware/software interrupt %d\n", vector));
841	switch (vector)
842	{
843	case X86_XCPT_NM:
844	{
845	uint32_t oldCR0;
846
847	Log(("#NM fault at %VGv\n", pCtx->eip));
848
849	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
850	oldCR0 = ASMGetCR0();
851	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
852	rc = CPUMHandleLazyFPU(pVM);
853	if (rc == VINF_SUCCESS)
854	{
855	Assert(CPUMIsGuestFPUStateActive(pVM));
856
857	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
858	ASMSetCR0(oldCR0);
859
860	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
861
862	/* Continue execution. */
863	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
864	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
865
866	goto ResumeExecution;
867	}
868
869	Log(("Forward #NM fault to the guest\n"));
870	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
871
872	Event.au64[0] = 0;
873	Event.n.u3Type = SVM_EVENT_EXCEPTION;
874	Event.n.u1Valid = 1;
875	Event.n.u8Vector = X86_XCPT_NM;
876
877	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
878	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
879	goto ResumeExecution;
880	}
881
882	case X86_XCPT_PF: /* Page fault */
883	{
884	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
885	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
886
887	Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
888	/* Exit qualification contains the linear address of the page fault. */
889	TRPMAssertTrap(pVM, X86_XCPT_PF, false);
890	TRPMSetErrorCode(pVM, errCode);
891	TRPMSetFaultAddress(pVM, uFaultAddress);
892
893	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
894	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
895	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
896	if (rc == VINF_SUCCESS)
897	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
898	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
899	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
900
901	TRPMResetTrap(pVM);
902
903	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
904	goto ResumeExecution;
905	}
906	else
907	if (rc == VINF_EM_RAW_GUEST_TRAP)
908	{ /* A genuine pagefault.
909	* Forward the trap to the guest by injecting the exception and resuming execution.
910	*/
911	Log2(("Forward page fault to the guest\n"));
912	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
913	/* The error code might have been changed. */
914	errCode = TRPMGetErrorCode(pVM);
915
916	TRPMResetTrap(pVM);
917
918	/* Now we must update CR2. */
919	pCtx->cr2 = uFaultAddress;
920
921	Event.au64[0] = 0;
922	Event.n.u3Type = SVM_EVENT_EXCEPTION;
923	Event.n.u1Valid = 1;
924	Event.n.u8Vector = X86_XCPT_PF;
925	Event.n.u1ErrorCodeValid = 1;
926	Event.n.u32ErrorCode = errCode;
927
928	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
929
930	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
931	goto ResumeExecution;
932	}
933	#ifdef VBOX_STRICT
934	if (rc != VINF_EM_RAW_EMULATE_INSTR)
935	Log(("PGMTrap0eHandler failed with %d\n", rc));
936	#endif
937	/* Need to go back to the recompiler to emulate the instruction. */
938	TRPMResetTrap(pVM);
939	break;
940	}
941
942	case X86_XCPT_MF: /* Floating point exception. */
943	{
944	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
945	if (!(pCtx->cr0 & X86_CR0_NE))
946	{
947	/* old style FPU error reporting needs some extra work. */
948	/** @todo don't fall back to the recompiler, but do it manually. */
949	rc = VINF_EM_RAW_EMULATE_INSTR;
950	break;
951	}
952	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
953
954	Event.au64[0] = 0;
955	Event.n.u3Type = SVM_EVENT_EXCEPTION;
956	Event.n.u1Valid = 1;
957	Event.n.u8Vector = X86_XCPT_MF;
958
959	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
960
961	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
962	goto ResumeExecution;
963	}
964
965	case X86_XCPT_GP: /* General protection failure exception.*/
966	{
967	if (pCtx->eflags.Bits.u1VM == 1)
968	{
969	Log(("#GP in V86 mode -> fall back\n"));
970	/** @note workaround for #GP loop; looks like an SVM bug */
971	rc = VINF_EM_RAW_EMULATE_INSTR;
972	break;
973	}
974	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
975
976	Event.au64[0] = 0;
977	Event.n.u3Type = SVM_EVENT_EXCEPTION;
978	Event.n.u1Valid = 1;
979	Event.n.u8Vector = X86_XCPT_GP;
980	Event.n.u1ErrorCodeValid= 1;
981	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
982	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
983	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
984
985	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
986	goto ResumeExecution;
987	}
988
989	#ifdef VBOX_STRICT
990	case X86_XCPT_UD: /* Unknown opcode exception. */
991	case X86_XCPT_DE: /* Debug exception. */
992	case X86_XCPT_SS: /* Stack segment exception. */
993	case X86_XCPT_NP: /* Segment not present exception. */
994	{
995	Event.au64[0] = 0;
996	Event.n.u3Type = SVM_EVENT_EXCEPTION;
997	Event.n.u1Valid = 1;
998	Event.n.u8Vector = vector;
999
1000	switch(vector)
1001	{
1002	case X86_XCPT_DE:
1003	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1004	break;
1005	case X86_XCPT_UD:
1006	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1007	break;
1008	case X86_XCPT_SS:
1009	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1010	Event.n.u1ErrorCodeValid = 1;
1011	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1012	break;
1013	case X86_XCPT_NP:
1014	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1015	Event.n.u1ErrorCodeValid = 1;
1016	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1017	break;
1018	}
1019
1020	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1021	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1022
1023	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1024	goto ResumeExecution;
1025	}
1026	#endif
1027	default:
1028	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1029	rc = VERR_EM_INTERNAL_ERROR;
1030	break;
1031
1032	} /* switch (vector) */
1033	break;
1034	}
1035
1036	case SVM_EXIT_FERR_FREEZE:
1037	case SVM_EXIT_INTR:
1038	case SVM_EXIT_NMI:
1039	case SVM_EXIT_SMI:
1040	case SVM_EXIT_INIT:
1041	case SVM_EXIT_VINTR:
1042	/* External interrupt; leave to allow it to be dispatched again. */
1043	rc = VINF_EM_RAW_INTERRUPT;
1044	break;
1045
1046	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1047	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1048	/* Skip instruction and continue directly. */
1049	pCtx->eip += 2; /** @note hardcoded opcode size! */
1050	/* Continue execution.*/
1051	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1052	goto ResumeExecution;
1053
1054	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1055	{
1056	Log2(("SVM: Cpuid %x\n", pCtx->eax));
1057	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1058	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1059	if (rc == VINF_SUCCESS)
1060	{
1061	/* Update EIP and continue execution. */
1062	pCtx->eip += 2; /** @note hardcoded opcode size! */
1063	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1064	goto ResumeExecution;
1065	}
1066	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1067	rc = VINF_EM_RAW_EMULATE_INSTR;
1068	break;
1069	}
1070
1071	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1072	{
1073	Log2(("VMX: invlpg\n"));
1074	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1075
1076	/* Truly a pita. Why can't SVM give the same information as VMX? */
1077	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1078	break;
1079	}
1080
1081	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1082	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1083	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1084	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1085	{
1086	uint32_t cbSize;
1087
1088	Log2(("VMX: %VGv mov cr%d, \n", pCtx->eip, exitCode - SVM_EXIT_WRITE_CR0));
1089	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1090	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1091
1092	switch (exitCode - SVM_EXIT_WRITE_CR0)
1093	{
1094	case 0:
1095	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1096	break;
1097	case 2:
1098	break;
1099	case 3:
1100	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1101	break;
1102	case 4:
1103	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1104	break;
1105	default:
1106	AssertFailed();
1107	}
1108	/* Check if a sync operation is pending. */
1109	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1110	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1111	{
1112	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1113	AssertRC(rc);
1114
1115	/** @note Force a TLB flush. SVM requires us to do it manually. */
1116	fForceTLBFlush = true;
1117	}
1118	if (rc == VINF_SUCCESS)
1119	{
1120	/* EIP has been updated already. */
1121
1122	/* Only resume if successful. */
1123	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1124	goto ResumeExecution;
1125	}
1126	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1127	if (rc == VERR_EM_INTERPRETER)
1128	rc = VINF_EM_RAW_EMULATE_INSTR;
1129	break;
1130	}
1131
1132	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1133	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1134	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1135	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1136	{
1137	uint32_t cbSize;
1138
1139	Log2(("VMX: %VGv mov x, cr%d\n", pCtx->eip, exitCode - SVM_EXIT_READ_CR0));
1140	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1141	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1142	if (rc == VINF_SUCCESS)
1143	{
1144	/* EIP has been updated already. */
1145
1146	/* Only resume if successful. */
1147	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1148	goto ResumeExecution;
1149	}
1150	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1151	if (rc == VERR_EM_INTERPRETER)
1152	rc = VINF_EM_RAW_EMULATE_INSTR;
1153	break;
1154	}
1155
1156	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1157	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1158	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1159	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1160	{
1161	uint32_t cbSize;
1162
1163	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_WRITE_DR0));
1164	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1165	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1166	if (rc == VINF_SUCCESS)
1167	{
1168	/* EIP has been updated already. */
1169
1170	/* Only resume if successful. */
1171	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1172	goto ResumeExecution;
1173	}
1174	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1175	if (rc == VERR_EM_INTERPRETER)
1176	rc = VINF_EM_RAW_EMULATE_INSTR;
1177	break;
1178	}
1179
1180	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1181	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1182	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1183	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1184	{
1185	uint32_t cbSize;
1186
1187	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_READ_DR0));
1188	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1189	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1190	if (rc == VINF_SUCCESS)
1191	{
1192	/* EIP has been updated already. */
1193
1194	/* Only resume if successful. */
1195	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1196	goto ResumeExecution;
1197	}
1198	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1199	if (rc == VERR_EM_INTERPRETER)
1200	rc = VINF_EM_RAW_EMULATE_INSTR;
1201	break;
1202	}
1203
1204	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1205	case SVM_EXIT_IOIO: /* I/O instruction. */
1206	{
1207	SVM_IOIO_EXIT IoExitInfo;
1208	uint32_t uIOSize, uAndVal;
1209
1210	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1211
1212	/** @todo could use a lookup table here */
1213	if (IoExitInfo.n.u1OP8)
1214	{
1215	uIOSize = 1;
1216	uAndVal = 0xff;
1217	}
1218	else
1219	if (IoExitInfo.n.u1OP16)
1220	{
1221	uIOSize = 2;
1222	uAndVal = 0xffff;
1223	}
1224	else
1225	if (IoExitInfo.n.u1OP32)
1226	{
1227	uIOSize = 4;
1228	uAndVal = 0xffffffff;
1229	}
1230	else
1231	{
1232	AssertFailed(); /* should be fatal. */
1233	rc = VINF_EM_RAW_EMULATE_INSTR;
1234	break;
1235	}
1236
1237	/* First simple in and out instructions. */
1238	/** @todo str & rep */
1239	if ( !IoExitInfo.n.u1REP
1240	&& !IoExitInfo.n.u1STR
1241	)
1242	{
1243	if (IoExitInfo.n.u1Type == 0)
1244	{
1245	Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1246	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1247	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1248	}
1249	else
1250	{
1251	uint32_t u32Val = 0;
1252
1253	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1254	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1255	if (rc == VINF_SUCCESS)
1256	{
1257	/* Write back to the EAX register. */
1258	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1259	Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1260	}
1261	}
1262	if (rc == VINF_SUCCESS)
1263	{
1264	/* Update EIP and continue execution. */
1265	pCtx->eip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1266	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1267	goto ResumeExecution;
1268	}
1269	Assert(rc == VINF_IOM_HC_IOPORT_READ \|\| rc == VINF_IOM_HC_IOPORT_WRITE);
1270	rc = (IoExitInfo.n.u1Type == 0) ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1271	}
1272	else
1273	rc = VINF_IOM_HC_IOPORT_READWRITE;
1274
1275	break;
1276	}
1277
1278	case SVM_EXIT_HLT:
1279	/** Check if external interrupts are pending; if so, don't switch back. */
1280	if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1281	{
1282	pCtx->eip++; /* skip hlt */
1283	goto ResumeExecution;
1284	}
1285
1286	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1287	break;
1288
1289	case SVM_EXIT_RDPMC:
1290	case SVM_EXIT_RSM:
1291	case SVM_EXIT_INVLPGA:
1292	case SVM_EXIT_VMRUN:
1293	case SVM_EXIT_VMMCALL:
1294	case SVM_EXIT_VMLOAD:
1295	case SVM_EXIT_VMSAVE:
1296	case SVM_EXIT_STGI:
1297	case SVM_EXIT_CLGI:
1298	case SVM_EXIT_SKINIT:
1299	case SVM_EXIT_RDTSCP:
1300	{
1301	/* Unsupported instructions. */
1302	SVM_EVENT Event;
1303
1304	Event.au64[0] = 0;
1305	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1306	Event.n.u1Valid = 1;
1307	Event.n.u8Vector = X86_XCPT_UD;
1308
1309	Log(("Forced #UD trap at %VGv\n", pCtx->eip));
1310	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1311
1312	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1313	goto ResumeExecution;
1314	}
1315
1316	/* Emulate RDMSR & WRMSR in ring 3. */
1317	case SVM_EXIT_MSR:
1318	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1319	break;
1320
1321	case SVM_EXIT_NPF:
1322	AssertFailed(); /* unexpected */
1323	break;
1324
1325	case SVM_EXIT_SHUTDOWN:
1326	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1327	break;
1328
1329	case SVM_EXIT_PAUSE:
1330	case SVM_EXIT_IDTR_READ:
1331	case SVM_EXIT_GDTR_READ:
1332	case SVM_EXIT_LDTR_READ:
1333	case SVM_EXIT_TR_READ:
1334	case SVM_EXIT_IDTR_WRITE:
1335	case SVM_EXIT_GDTR_WRITE:
1336	case SVM_EXIT_LDTR_WRITE:
1337	case SVM_EXIT_TR_WRITE:
1338	case SVM_EXIT_CR0_SEL_WRITE:
1339	default:
1340	/* Unexpected exit codes. */
1341	rc = VERR_EM_INTERNAL_ERROR;
1342	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1343	break;
1344	}
1345
1346	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1347	SVM_READ_SELREG(LDTR, ldtr);
1348	SVM_READ_SELREG(TR, tr);
1349
1350	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1351	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1352
1353	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1354	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1355
1356	/*
1357	* System MSRs
1358	*/
1359	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1360	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1361	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1362
1363	/* Signal changes for the recompiler. */
1364	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1365
1366	end:
1367
1368	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1369	if (exitCode == SVM_EXIT_INTR)
1370	{
1371	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1372	/* On the next entry we'll only sync the host context. */
1373	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1374	}
1375	else
1376	{
1377	/* On the next entry we'll sync everything. */
1378	/** @todo we can do better than this */
1379	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1380	}
1381
1382	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1383	return rc;
1384	}
1385
1386	/**
1387	* Enable SVM
1388	*
1389	* @returns VBox status code.
1390	* @param pVM The VM to operate on.
1391	*/
1392	HWACCMR0DECL(int) SVMR0Enable(PVM pVM)
1393	{
1394	uint64_t val;
1395
1396	Assert(pVM->hwaccm.s.svm.fSupported);
1397
1398	/* We must turn on SVM and setup the host state physical address, as those MSRs are per-cpu/core. */
1399
1400	/* Turn on SVM in the EFER MSR. */
1401	val = ASMRdMsr(MSR_K6_EFER);
1402	if (!(val & MSR_K6_EFER_SVME))
1403	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
1404
1405	/* Write the physical page address where the CPU will store the host state while executing the VM. */
1406	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pVM->hwaccm.s.svm.pHStatePhys);
1407
1408	/* Force a TLB flush on VM entry. */
1409	pVM->hwaccm.s.svm.fResumeVM = false;
1410
1411	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1412	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
1413
1414	return VINF_SUCCESS;
1415	}
1416
1417
1418	/**
1419	* Disable SVM
1420	*
1421	* @returns VBox status code.
1422	* @param pVM The VM to operate on.
1423	*/
1424	HWACCMR0DECL(int) SVMR0Disable(PVM pVM)
1425	{
1426	/** @todo hopefully this is not very expensive. */
1427
1428	/* Turn off SVM in the EFER MSR. */
1429	uint64_t val = ASMRdMsr(MSR_K6_EFER);
1430	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
1431
1432	/* Invalidate host state physical address. */
1433	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
1434
1435	Assert(pVM->hwaccm.s.svm.fSupported);
1436	return VINF_SUCCESS;
1437	}
1438
1439
1440	static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1441	{
1442	OP_PARAMVAL param1;
1443	RTGCPTR addr;
1444
1445	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1446	if(VBOX_FAILURE(rc))
1447	return VERR_EM_INTERPRETER;
1448
1449	switch(param1.type)
1450	{
1451	case PARMTYPE_IMMEDIATE:
1452	case PARMTYPE_ADDRESS:
1453	if(!(param1.flags & PARAM_VAL32))
1454	return VERR_EM_INTERPRETER;
1455	addr = (RTGCPTR)param1.val.val32;
1456	break;
1457
1458	default:
1459	return VERR_EM_INTERPRETER;
1460	}
1461
1462	/** @todo is addr always a flat linear address or ds based
1463	* (in absence of segment override prefixes)????
1464	*/
1465	rc = PGMInvalidatePage(pVM, addr);
1466	if (VBOX_SUCCESS(rc))
1467	{
1468	/* Manually invalidate the page for the VM's TLB. */
1469	SVMInvlpgA(addr, uASID);
1470	return VINF_SUCCESS;
1471	}
1472	/** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1473	return VERR_EM_INTERPRETER;
1474	}
1475
1476	/**
1477	* Interprets INVLPG
1478	*
1479	* @returns VBox status code.
1480	* @retval VINF_* Scheduling instructions.
1481	* @retval VERR_EM_INTERPRETER Something we can't cope with.
1482	* @retval VERR_* Fatal errors.
1483	*
1484	* @param pVM The VM handle.
1485	* @param pRegFrame The register frame.
1486	* @param ASID Tagged TLB id for the guest
1487	*
1488	* Updates the EIP if an instruction was executed successfully.
1489	*/
1490	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1491	{
1492	/*
1493	* Only allow 32-bit code.
1494	*/
1495	if (SELMIsSelector32Bit(pVM, pRegFrame->cs, &pRegFrame->csHid))
1496	{
1497	RTGCPTR pbCode;
1498	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pbCode);
1499	if (VBOX_SUCCESS(rc))
1500	{
1501	uint32_t cbOp;
1502	DISCPUSTATE Cpu;
1503
1504	Cpu.mode = CPUMODE_32BIT;
1505	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1506	Assert(VBOX_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
1507	if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1508	{
1509	Assert(cbOp == Cpu.opsize);
1510	rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1511	if (VBOX_SUCCESS(rc))
1512	{
1513	pRegFrame->eip += cbOp; /* Move on to the next instruction. */
1514	}
1515	return rc;
1516	}
1517	}
1518	}
1519	return VERR_EM_INTERPRETER;
1520	}
1521

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 1211

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