HWSVMR0.cpp@ 11280

Last change on this file since 11280 was 10886, checked in by vboxsync, 16 years ago
Fixes for syncing back sysenter MSRs.
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File size: 83.8 KB

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1	/* $Id: HWSVMR0.cpp 10886 2008-07-25 11:30:55Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/disopcode.h>
41	#include <iprt/param.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/cpuset.h>
45	#include <iprt/mp.h>
46	#include "HWSVMR0.h"
47
48	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
49
50	/**
51	* Sets up and activates AMD-V on the current CPU
52	*
53	* @returns VBox status code.
54	* @param pCpu CPU info struct
55	* @param pVM The VM to operate on.
56	* @param pvPageCpu Pointer to the global cpu page
57	* @param pPageCpuPhys Physical address of the global cpu page
58	*/
59	HWACCMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
60	{
61	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
62	AssertReturn(pVM, VERR_INVALID_PARAMETER);
63	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
64
65	/* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
66
67	#ifdef LOG_ENABLED
68	SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
69	#endif
70
71	/* Turn on AMD-V in the EFER MSR. */
72	uint64_t val = ASMRdMsr(MSR_K6_EFER);
73	if (!(val & MSR_K6_EFER_SVME))
74	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
75
76	/* Write the physical page address where the CPU will store the host state while executing the VM. */
77	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
78
79	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
80	pCpu->cTLBFlushes = 0;
81	return VINF_SUCCESS;
82	}
83
84	/**
85	* Deactivates AMD-V on the current CPU
86	*
87	* @returns VBox status code.
88	* @param pCpu CPU info struct
89	* @param pvPageCpu Pointer to the global cpu page
90	* @param pPageCpuPhys Physical address of the global cpu page
91	*/
92	HWACCMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
93	{
94	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
95	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
96
97	#ifdef LOG_ENABLED
98	SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
99	#endif
100
101	/* Turn off AMD-V in the EFER MSR. */
102	uint64_t val = ASMRdMsr(MSR_K6_EFER);
103	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
104
105	/* Invalidate host state physical address. */
106	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
107	pCpu->uCurrentASID = 0;
108
109	return VINF_SUCCESS;
110	}
111
112	/**
113	* Does Ring-0 per VM AMD-V init.
114	*
115	* @returns VBox status code.
116	* @param pVM The VM to operate on.
117	*/
118	HWACCMR0DECL(int) SVMR0InitVM(PVM pVM)
119	{
120	int rc;
121
122	pVM->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
123	pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
124	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
125	pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
126
127
128	/* Allocate one page for the VM control block (VMCB). */
129	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
130	if (RT_FAILURE(rc))
131	return rc;
132
133	pVM->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCB);
134	pVM->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCB, 0);
135	ASMMemZeroPage(pVM->hwaccm.s.svm.pVMCB);
136
137	/* Allocate one page for the host context */
138	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
139	if (RT_FAILURE(rc))
140	return rc;
141
142	pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
143	pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
144	ASMMemZeroPage(pVM->hwaccm.s.svm.pVMCBHost);
145
146	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
147	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
148	if (RT_FAILURE(rc))
149	return rc;
150
151	pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
152	pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
153	/* Set all bits to intercept all IO accesses. */
154	ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
155
156	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
157	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
158	if (RT_FAILURE(rc))
159	return rc;
160
161	pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
162	pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
163	/* Set all bits to intercept all MSR accesses. */
164	ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
165
166	/* Erratum 170 which requires a forced TLB flush for each world switch:
167	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
168	*
169	* All BH-G1/2 and DH-G1/2 models include a fix:
170	* Athlon X2: 0x6b 1/2
171	* 0x68 1/2
172	* Athlon 64: 0x7f 1
173	* 0x6f 2
174	* Sempron: 0x7f 1/2
175	* 0x6f 2
176	* 0x6c 2
177	* 0x7c 2
178	* Turion 64: 0x68 2
179	*
180	*/
181	uint32_t u32Dummy;
182	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
183	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
184	u32BaseFamily= (u32Version >> 8) & 0xf;
185	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
186	u32Model = ((u32Version >> 4) & 0xf);
187	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
188	u32Stepping = u32Version & 0xf;
189	if ( u32Family == 0xf
190	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
191	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
192	{
193	Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
194	pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
195	}
196
197	/* Invalidate the last cpu we were running on. */
198	pVM->hwaccm.s.svm.idLastCpu = NIL_RTCPUID;
199	return VINF_SUCCESS;
200	}
201
202	/**
203	* Does Ring-0 per VM AMD-V termination.
204	*
205	* @returns VBox status code.
206	* @param pVM The VM to operate on.
207	*/
208	HWACCMR0DECL(int) SVMR0TermVM(PVM pVM)
209	{
210	if (pVM->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
211	{
212	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCB, false);
213	pVM->hwaccm.s.svm.pVMCB = 0;
214	pVM->hwaccm.s.svm.pVMCBPhys = 0;
215	pVM->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
216	}
217	if (pVM->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
218	{
219	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
220	pVM->hwaccm.s.svm.pVMCBHost = 0;
221	pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
222	pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
223	}
224	if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
225	{
226	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
227	pVM->hwaccm.s.svm.pIOBitmap = 0;
228	pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
229	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
230	}
231	if (pVM->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
232	{
233	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
234	pVM->hwaccm.s.svm.pMSRBitmap = 0;
235	pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
236	pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
237	}
238	return VINF_SUCCESS;
239	}
240
241	/**
242	* Sets up AMD-V for the specified VM
243	*
244	* @returns VBox status code.
245	* @param pVM The VM to operate on.
246	*/
247	HWACCMR0DECL(int) SVMR0SetupVM(PVM pVM)
248	{
249	int rc = VINF_SUCCESS;
250	SVM_VMCB *pVMCB;
251
252	AssertReturn(pVM, VERR_INVALID_PARAMETER);
253
254	Assert(pVM->hwaccm.s.svm.fSupported);
255
256	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
257	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
258
259	/* Program the control fields. Most of them never have to be changed again. */
260	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
261	/** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
262	if (!pVM->hwaccm.s.fNestedPaging)
263	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
264	else
265	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
266
267	/*
268	* CR0/3/4 writes must be intercepted for obvious reasons.
269	*/
270	if (!pVM->hwaccm.s.fNestedPaging)
271	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
272	else
273	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4) \| RT_BIT(8);
274
275	/* Intercept all DRx reads and writes. */
276	pVMCB->ctrl.u16InterceptRdDRx = RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7);
277	pVMCB->ctrl.u16InterceptWrDRx = RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6) \| RT_BIT(7);
278
279	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
280	* All breakpoints are automatically cleared when the VM exits.
281	*/
282
283	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
284	#ifndef DEBUG
285	if (pVM->hwaccm.s.fNestedPaging)
286	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(14); /* no longer need to intercept #PF. */
287	#endif
288
289	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
290	\| SVM_CTRL1_INTERCEPT_VINTR
291	\| SVM_CTRL1_INTERCEPT_NMI
292	\| SVM_CTRL1_INTERCEPT_SMI
293	\| SVM_CTRL1_INTERCEPT_INIT
294	\| SVM_CTRL1_INTERCEPT_RDPMC
295	\| SVM_CTRL1_INTERCEPT_CPUID
296	\| SVM_CTRL1_INTERCEPT_RSM
297	\| SVM_CTRL1_INTERCEPT_HLT
298	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
299	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
300	\| SVM_CTRL1_INTERCEPT_INVLPG
301	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
302	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH
303	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
304	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
305	;
306	/* With nested paging we don't care about invlpg anymore. */
307	if (pVM->hwaccm.s.fNestedPaging)
308	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
309
310	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
311	\| SVM_CTRL2_INTERCEPT_VMMCALL
312	\| SVM_CTRL2_INTERCEPT_VMLOAD
313	\| SVM_CTRL2_INTERCEPT_VMSAVE
314	\| SVM_CTRL2_INTERCEPT_STGI
315	\| SVM_CTRL2_INTERCEPT_CLGI
316	\| SVM_CTRL2_INTERCEPT_SKINIT
317	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
318	\| SVM_CTRL2_INTERCEPT_WBINVD
319	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
320	;
321	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
322	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
323	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
324
325	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
326	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
327	/* Ignore the priority in the TPR; just deliver it when we tell it to. */
328	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
329
330	/* Set IO and MSR bitmap addresses. */
331	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
332	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
333
334	/* No LBR virtualization. */
335	pVMCB->ctrl.u64LBRVirt = 0;
336
337	/** The ASID must start at 1; the host uses 0. */
338	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
339
340	/** Setup the PAT msr (nested paging only) */
341	pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
342	return rc;
343	}
344
345
346	/**
347	* Injects an event (trap or external interrupt)
348	*
349	* @param pVM The VM to operate on.
350	* @param pVMCB SVM control block
351	* @param pCtx CPU Context
352	* @param pIntInfo SVM interrupt info
353	*/
354	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
355	{
356	#ifdef VBOX_STRICT
357	if (pEvent->n.u8Vector == 0xE)
358	Log(("SVM: Inject int %d at %VGv error code=%02x CR2=%VGv intInfo=%08x\n", pEvent->n.u8Vector, pCtx->rip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
359	else
360	if (pEvent->n.u8Vector < 0x20)
361	Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->rip, pEvent->n.u32ErrorCode));
362	else
363	{
364	Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->rip));
365	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
366	Assert(pCtx->eflags.u32 & X86_EFL_IF);
367	}
368	#endif
369
370	/* Set event injection state. */
371	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
372	}
373
374
375	/**
376	* Checks for pending guest interrupts and injects them
377	*
378	* @returns VBox status code.
379	* @param pVM The VM to operate on.
380	* @param pVMCB SVM control block
381	* @param pCtx CPU Context
382	*/
383	static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx)
384	{
385	int rc;
386
387	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
388	if (pVM->hwaccm.s.Event.fPending)
389	{
390	SVM_EVENT Event;
391
392	Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip));
393	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
394	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
395	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
396
397	pVM->hwaccm.s.Event.fPending = false;
398	return VINF_SUCCESS;
399	}
400
401	/* When external interrupts are pending, we should exit the VM when IF is set. */
402	if ( !TRPMHasTrap(pVM)
403	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
404	{
405	if ( !(pCtx->eflags.u32 & X86_EFL_IF)
406	\|\| VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
407	{
408	if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
409	{
410	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
411	LogFlow(("Enable irq window exit!\n"));
412	else
413	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", pCtx->rip));
414
415	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
416	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
417	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
418	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
419	}
420	}
421	else
422	{
423	uint8_t u8Interrupt;
424
425	rc = PDMGetInterrupt(pVM, &u8Interrupt);
426	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
427	if (VBOX_SUCCESS(rc))
428	{
429	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
430	AssertRC(rc);
431	}
432	else
433	{
434	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
435	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
436	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
437	/* Just continue */
438	}
439	}
440	}
441
442	#ifdef VBOX_STRICT
443	if (TRPMHasTrap(pVM))
444	{
445	uint8_t u8Vector;
446	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
447	AssertRC(rc);
448	}
449	#endif
450
451	if ( pCtx->eflags.u32 & X86_EFL_IF
452	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
453	&& TRPMHasTrap(pVM)
454	)
455	{
456	uint8_t u8Vector;
457	int rc;
458	TRPMEVENT enmType;
459	SVM_EVENT Event;
460	RTGCUINT u32ErrorCode;
461
462	Event.au64[0] = 0;
463
464	/* If a new event is pending, then dispatch it now. */
465	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
466	AssertRC(rc);
467	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
468	Assert(enmType != TRPM_SOFTWARE_INT);
469
470	/* Clear the pending trap. */
471	rc = TRPMResetTrap(pVM);
472	AssertRC(rc);
473
474	Event.n.u8Vector = u8Vector;
475	Event.n.u1Valid = 1;
476	Event.n.u32ErrorCode = u32ErrorCode;
477
478	if (enmType == TRPM_TRAP)
479	{
480	switch (u8Vector) {
481	case 8:
482	case 10:
483	case 11:
484	case 12:
485	case 13:
486	case 14:
487	case 17:
488	/* Valid error codes. */
489	Event.n.u1ErrorCodeValid = 1;
490	break;
491	default:
492	break;
493	}
494	if (u8Vector == X86_XCPT_NMI)
495	Event.n.u3Type = SVM_EVENT_NMI;
496	else
497	Event.n.u3Type = SVM_EVENT_EXCEPTION;
498	}
499	else
500	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
501
502	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
503	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
504	} /* if (interrupts can be dispatched) */
505
506	return VINF_SUCCESS;
507	}
508
509	/**
510	* Save the host state
511	*
512	* @returns VBox status code.
513	* @param pVM The VM to operate on.
514	*/
515	HWACCMR0DECL(int) SVMR0SaveHostState(PVM pVM)
516	{
517	/* Nothing to do here. */
518	return VINF_SUCCESS;
519	}
520
521	/**
522	* Loads the guest state
523	*
524	* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
525	*
526	* @returns VBox status code.
527	* @param pVM The VM to operate on.
528	* @param pCtx Guest context
529	*/
530	HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
531	{
532	RTGCUINTPTR val;
533	SVM_VMCB *pVMCB;
534
535	if (pVM == NULL)
536	return VERR_INVALID_PARAMETER;
537
538	/* Setup AMD SVM. */
539	Assert(pVM->hwaccm.s.svm.fSupported);
540
541	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
542	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
543
544	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
545	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
546	{
547	SVM_WRITE_SELREG(CS, cs);
548	SVM_WRITE_SELREG(SS, ss);
549	SVM_WRITE_SELREG(DS, ds);
550	SVM_WRITE_SELREG(ES, es);
551	SVM_WRITE_SELREG(FS, fs);
552	SVM_WRITE_SELREG(GS, gs);
553	}
554
555	/* Guest CPU context: LDTR. */
556	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
557	{
558	SVM_WRITE_SELREG(LDTR, ldtr);
559	}
560
561	/* Guest CPU context: TR. */
562	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
563	{
564	SVM_WRITE_SELREG(TR, tr);
565	}
566
567	/* Guest CPU context: GDTR. */
568	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
569	{
570	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
571	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
572	}
573
574	/* Guest CPU context: IDTR. */
575	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
576	{
577	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
578	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
579	}
580
581	/*
582	* Sysenter MSRs (unconditional)
583	*/
584	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
585	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
586	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
587
588	/* Control registers */
589	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
590	{
591	val = pCtx->cr0;
592	if (!CPUMIsGuestFPUStateActive(pVM))
593	{
594	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
595	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
596	}
597	else
598	{
599	/** @todo check if we support the old style mess correctly. */
600	if (!(val & X86_CR0_NE))
601	{
602	Log(("Forcing X86_CR0_NE!!!\n"));
603
604	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
605	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
606	{
607	pVMCB->ctrl.u32InterceptException \|= RT_BIT(16);
608	pVM->hwaccm.s.fFPUOldStyleOverride = true;
609	}
610	}
611	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
612	}
613	/* Always enable caching. */
614	val &= ~(X86_CR0_CD\|X86_CR0_NW);
615
616	/* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
617	/* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
618	if (!pVM->hwaccm.s.fNestedPaging)
619	{
620	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
621	val \|= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
622	}
623	pVMCB->guest.u64CR0 = val;
624	}
625	/* CR2 as well */
626	pVMCB->guest.u64CR2 = pCtx->cr2;
627
628	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
629	{
630	/* Save our shadow CR3 register. */
631	if (pVM->hwaccm.s.fNestedPaging)
632	{
633	pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
634	Assert(pVMCB->ctrl.u64NestedPagingCR3);
635	pVMCB->guest.u64CR3 = pCtx->cr3;
636	}
637	else
638	{
639	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
640	Assert(pVMCB->guest.u64CR3);
641	}
642	}
643
644	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
645	{
646	val = pCtx->cr4;
647	if (!pVM->hwaccm.s.fNestedPaging)
648	{
649	switch(pVM->hwaccm.s.enmShadowMode)
650	{
651	case PGMMODE_REAL:
652	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
653	AssertFailed();
654	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
655
656	case PGMMODE_32_BIT: /* 32-bit paging. */
657	break;
658
659	case PGMMODE_PAE: /* PAE paging. */
660	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
661	/** @todo use normal 32 bits paging */
662	val \|= X86_CR4_PAE;
663	break;
664
665	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
666	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
667	#ifdef VBOX_ENABLE_64_BITS_GUESTS
668	break;
669	#else
670	AssertFailed();
671	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
672	#endif
673
674	default: /* shut up gcc */
675	AssertFailed();
676	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
677	}
678	}
679	pVMCB->guest.u64CR4 = val;
680	}
681
682	/* Debug registers. */
683	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
684	{
685	/** @todo DR0-6 */
686	val = pCtx->dr7;
687	val &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
688	val \|= 0x400; /* must be one */
689	#ifdef VBOX_STRICT
690	val = 0x400;
691	#endif
692	pVMCB->guest.u64DR7 = val;
693
694	pVMCB->guest.u64DR6 = pCtx->dr6;
695	}
696
697	/* EIP, ESP and EFLAGS */
698	pVMCB->guest.u64RIP = pCtx->rip;
699	pVMCB->guest.u64RSP = pCtx->rsp;
700	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
701
702	/* Set CPL */
703	pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
704
705	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
706	pVMCB->guest.u64RAX = pCtx->rax;
707
708	/* vmrun will fail without MSR_K6_EFER_SVME. */
709	pVMCB->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
710
711	/* 64 bits guest mode? */
712	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
713	{
714	#if !defined(VBOX_WITH_64_BITS_GUESTS) \|\| HC_ARCH_BITS != 64
715	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
716	#else
717	pVM->hwaccm.s.svm.pfnVMRun = SVMVMRun64;
718	#endif
719	/* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
720	pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
721	pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
722	}
723	else
724	{
725	/* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
726	pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
727
728	pVM->hwaccm.s.svm.pfnVMRun = SVMVMRun;
729	}
730
731	/** TSC offset. */
732	if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
733	{
734	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
735	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
736	}
737	else
738	{
739	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
740	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
741	}
742
743	/* Sync the various msrs for 64 bits mode. */
744	pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
745	pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
746	pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
747	pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
748	pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
749
750	#ifdef DEBUG
751	/* Intercept X86_XCPT_DB if stepping is enabled */
752	if (DBGFIsStepping(pVM))
753	pVMCB->ctrl.u32InterceptException \|= RT_BIT(1);
754	else
755	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(1);
756	#endif
757
758	/* Done. */
759	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
760
761	return VINF_SUCCESS;
762	}
763
764
765	/**
766	* Runs guest code in an SVM VM.
767	*
768	* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
769	*
770	* @returns VBox status code.
771	* @param pVM The VM to operate on.
772	* @param pCtx Guest context
773	*/
774	HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
775	{
776	int rc = VINF_SUCCESS;
777	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
778	SVM_VMCB *pVMCB;
779	bool fGuestStateSynced = false;
780	bool fSyncTPR = false;
781	unsigned cResume = 0;
782	uint8_t u8LastVTPR;
783	PHWACCM_CPUINFO pCpu = 0;
784	#ifdef VBOX_STRICT
785	RTCPUID idCpuCheck;
786	#endif
787
788	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
789
790	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
791	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
792
793	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
794	*/
795	ResumeExecution:
796	/* Safety precaution; looping for too long here can have a very bad effect on the host */
797	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
798	{
799	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
800	rc = VINF_EM_RAW_INTERRUPT;
801	goto end;
802	}
803
804	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
805	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
806	{
807	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
808	if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
809	{
810	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
811	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
812	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
813	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
814	*/
815	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
816	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
817	pVMCB->ctrl.u64IntShadow = 0;
818	}
819	}
820	else
821	{
822	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
823	pVMCB->ctrl.u64IntShadow = 0;
824	}
825
826	/* Check for pending actions that force us to go back to ring 3. */
827	#ifdef DEBUG
828	/* Intercept X86_XCPT_DB if stepping is enabled */
829	if (!DBGFIsStepping(pVM))
830	#endif
831	{
832	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
833	{
834	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
835	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
836	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
837	rc = VINF_EM_RAW_TO_R3;
838	goto end;
839	}
840	}
841
842	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
843	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
844	{
845	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
846	rc = VINF_EM_PENDING_REQUEST;
847	goto end;
848	}
849
850	/* When external interrupts are pending, we should exit the VM when IF is set. */
851	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
852	rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
853	if (VBOX_FAILURE(rc))
854	{
855	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
856	goto end;
857	}
858
859	/* TPR caching using CR8 is only available in 64 bits mode */
860	/* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
861	/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! */
862	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
863	{
864	bool fPending;
865
866	/* TPR caching in CR8 */
867	int rc = PDMApicGetTPR(pVM, &u8LastVTPR, &fPending);
868	AssertRC(rc);
869	pVMCB->ctrl.IntCtrl.n.u8VTPR = u8LastVTPR;
870
871	if (fPending)
872	{
873	/* A TPR change could activate a pending interrupt, so catch cr8 writes. */
874	pVMCB->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
875	}
876	else
877	/* No interrupts are pending, so we don't need to be explicitely notified.
878	* There are enough world switches for detecting pending interrupts.
879	*/
880	pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
881
882	fSyncTPR = !fPending;
883	}
884
885	/* All done! Let's start VM execution. */
886	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
887
888	/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
889	pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
890
891	#ifdef LOG_ENABLED
892	pCpu = HWACCMR0GetCurrentCpu();
893	if ( pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu
894	\|\| pVM->hwaccm.s.svm.cTLBFlushes != pCpu->cTLBFlushes)
895	{
896	if (pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu)
897	Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVM->hwaccm.s.svm.idLastCpu, pCpu->idCpu));
898	else
899	Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVM->hwaccm.s.svm.cTLBFlushes, pCpu->cTLBFlushes));
900	}
901	if (pCpu->fFlushTLB)
902	Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
903	#endif
904
905	/*
906	* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
907	* (until the actual world switch)
908	*/
909
910	#ifdef VBOX_STRICT
911	idCpuCheck = RTMpCpuId();
912	#endif
913
914	/* Load the guest state; must be here as it sets up the shadow cr0 for lazy fpu syncing! */
915	rc = SVMR0LoadGuestState(pVM, pCtx);
916	if (rc != VINF_SUCCESS)
917	{
918	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
919	goto end;
920	}
921	fGuestStateSynced = true;
922
923	pCpu = HWACCMR0GetCurrentCpu();
924	/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
925	/* Note that this can happen both for start and resume due to long jumps back to ring 3. */
926	if ( pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu
927	/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
928	\|\| pVM->hwaccm.s.svm.cTLBFlushes != pCpu->cTLBFlushes)
929	{
930	/* Force a TLB flush on VM entry. */
931	pVM->hwaccm.s.svm.fForceTLBFlush = true;
932	}
933	else
934	Assert(!pCpu->fFlushTLB);
935
936	pVM->hwaccm.s.svm.idLastCpu = pCpu->idCpu;
937
938	/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
939	if ( pVM->hwaccm.s.svm.fForceTLBFlush
940	&& !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
941	{
942	if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.svm.u32MaxASID
943	\|\| pCpu->fFlushTLB)
944	{
945	pCpu->fFlushTLB = false;
946	pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
947	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
948	pCpu->cTLBFlushes++;
949	}
950	else
951	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushASID);
952
953	pVM->hwaccm.s.svm.cTLBFlushes = pCpu->cTLBFlushes;
954	}
955	else
956	{
957	Assert(!pCpu->fFlushTLB \|\| pVM->hwaccm.s.svm.fAlwaysFlushTLB);
958
959	/* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
960	if (!pCpu->uCurrentASID)
961	pCpu->uCurrentASID = 1;
962
963	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVM->hwaccm.s.svm.fForceTLBFlush;
964	}
965	AssertMsg(pVM->hwaccm.s.svm.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVM->hwaccm.s.svm.cTLBFlushes, pCpu->cTLBFlushes));
966	AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.svm.u32MaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
967	pVMCB->ctrl.TLBCtrl.n.u32ASID = pCpu->uCurrentASID;
968
969	#ifdef VBOX_WITH_STATISTICS
970	if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
971	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
972	else
973	STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
974	#endif
975
976	/* In case we execute a goto ResumeExecution later on. */
977	pVM->hwaccm.s.svm.fResumeVM = true;
978	pVM->hwaccm.s.svm.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
979
980	Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
981	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
982	\| SVM_CTRL2_INTERCEPT_VMMCALL
983	\| SVM_CTRL2_INTERCEPT_VMLOAD
984	\| SVM_CTRL2_INTERCEPT_VMSAVE
985	\| SVM_CTRL2_INTERCEPT_STGI
986	\| SVM_CTRL2_INTERCEPT_CLGI
987	\| SVM_CTRL2_INTERCEPT_SKINIT
988	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
989	\| SVM_CTRL2_INTERCEPT_WBINVD
990	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
991	));
992	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
993	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
994	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
995	Assert(pVMCB->ctrl.u64LBRVirt == 0);
996
997	#ifdef VBOX_STRICT
998	Assert(idCpuCheck == RTMpCpuId());
999	#endif
1000	pVM->hwaccm.s.svm.pfnVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
1001	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1002
1003	/**
1004	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1005	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1006	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1007	*/
1008
1009	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1010
1011	/* Reason for the VM exit */
1012	exitCode = pVMCB->ctrl.u64ExitCode;
1013
1014	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
1015	{
1016	HWACCMDumpRegs(pVM, pCtx);
1017	#ifdef DEBUG
1018	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1019	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1020	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1021	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1022	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1023	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1024	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1025	Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1026	Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1027	Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
1028
1029	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1030	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1031	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1032	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1033
1034	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1035	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1036	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1037	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1038	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1039	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1040	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1041	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1042	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1043	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1044
1045	Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
1046	Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
1047	Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
1048	Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
1049	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1050	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1051	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1052	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1053	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1054	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1055	Log(("ctrl.NestedPaging %VX64\n", pVMCB->ctrl.NestedPaging.au64));
1056	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1057	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1058	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1059	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1060	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1061	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1062
1063	Log(("ctrl.u64NestedPagingCR3 %VX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1064	Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
1065
1066	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1067	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1068	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1069	Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
1070	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1071	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1072	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1073	Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
1074	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1075	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1076	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1077	Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
1078	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1079	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1080	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1081	Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
1082	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1083	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1084	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1085	Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
1086
1087	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1088	Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
1089
1090	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1091	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1092	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1093	Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
1094
1095	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1096	Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
1097
1098	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1099	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1100	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1101	Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
1102
1103	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1104	Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
1105	Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
1106	Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
1107	Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
1108	Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
1109	Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
1110
1111	Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
1112	Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
1113	Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
1114	Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
1115
1116	Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
1117	Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
1118	Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
1119
1120	Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
1121	Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
1122	Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
1123	Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
1124	Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
1125	Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
1126	Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
1127	Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
1128	Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
1129	Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
1130	Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
1131	Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
1132
1133	#endif
1134	rc = VERR_SVM_UNABLE_TO_START_VM;
1135	goto end;
1136	}
1137
1138	/* Let's first sync back eip, esp, and eflags. */
1139	pCtx->rip = pVMCB->guest.u64RIP;
1140	pCtx->rsp = pVMCB->guest.u64RSP;
1141	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1142	/* eax is saved/restore across the vmrun instruction */
1143	pCtx->rax = pVMCB->guest.u64RAX;
1144
1145	pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1146
1147	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1148	SVM_READ_SELREG(SS, ss);
1149	SVM_READ_SELREG(CS, cs);
1150	SVM_READ_SELREG(DS, ds);
1151	SVM_READ_SELREG(ES, es);
1152	SVM_READ_SELREG(FS, fs);
1153	SVM_READ_SELREG(GS, gs);
1154
1155	/*
1156	* System MSRs
1157	*/
1158	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1159	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1160	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1161
1162	/* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1163	/* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1164	if ( pVM->hwaccm.s.fNestedPaging
1165	&& pCtx->cr3 != pVMCB->guest.u64CR3)
1166	{
1167	CPUMSetGuestCR3(pVM, pVMCB->guest.u64CR3);
1168	PGMUpdateCR3(pVM, pVMCB->guest.u64CR3);
1169	}
1170
1171	/** @note NOW IT'S SAFE FOR LOGGING! */
1172
1173	/* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1174	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1175	{
1176	Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->rip));
1177	EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1178	}
1179	else
1180	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1181
1182	Log2(("exitCode = %x\n", exitCode));
1183
1184	/* Sync back the debug registers. */
1185	/** @todo Implement debug registers correctly. */
1186	pCtx->dr6 = pVMCB->guest.u64DR6;
1187	pCtx->dr7 = pVMCB->guest.u64DR7;
1188
1189	/* Check if an injected event was interrupted prematurely. */
1190	pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1191	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1192	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1193	{
1194	Log(("Pending inject %VX64 at %VGv exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitCode));
1195
1196	#ifdef LOG_ENABLED
1197	SVM_EVENT Event;
1198	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
1199
1200	if ( exitCode == SVM_EXIT_EXCEPTION_E
1201	&& Event.n.u8Vector == 0xE)
1202	{
1203	Log(("Double fault!\n"));
1204	}
1205	#endif
1206
1207	pVM->hwaccm.s.Event.fPending = true;
1208	/* Error code present? (redundant) */
1209	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1210	{
1211	pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1212	}
1213	else
1214	pVM->hwaccm.s.Event.errCode = 0;
1215	}
1216	#ifdef VBOX_WITH_STATISTICS
1217	if (exitCode == SVM_EXIT_NPF)
1218	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitReasonNPF);
1219	else
1220	STAM_COUNTER_INC(&pVM->hwaccm.s.pStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1221	#endif
1222
1223	if (fSyncTPR)
1224	{
1225	rc = PDMApicSetTPR(pVM, pVMCB->ctrl.IntCtrl.n.u8VTPR);
1226	AssertRC(rc);
1227	}
1228
1229	/* Deal with the reason of the VM-exit. */
1230	switch (exitCode)
1231	{
1232	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1233	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1234	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1235	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1236	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1237	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1238	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1239	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1240	{
1241	/* Pending trap. */
1242	SVM_EVENT Event;
1243	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1244
1245	Log2(("Hardware/software interrupt %d\n", vector));
1246	switch (vector)
1247	{
1248	#ifdef DEBUG
1249	case X86_XCPT_DB:
1250	rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pVMCB->guest.u64DR6);
1251	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
1252	break;
1253	#endif
1254
1255	case X86_XCPT_NM:
1256	{
1257	Log(("#NM fault at %VGv\n", pCtx->rip));
1258
1259	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1260	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1261	rc = CPUMR0LoadGuestFPU(pVM, pCtx);
1262	if (rc == VINF_SUCCESS)
1263	{
1264	Assert(CPUMIsGuestFPUStateActive(pVM));
1265	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1266
1267	/* Continue execution. */
1268	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1269	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1270
1271	goto ResumeExecution;
1272	}
1273
1274	Log(("Forward #NM fault to the guest\n"));
1275	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1276
1277	Event.au64[0] = 0;
1278	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1279	Event.n.u1Valid = 1;
1280	Event.n.u8Vector = X86_XCPT_NM;
1281
1282	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1283	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1284	goto ResumeExecution;
1285	}
1286
1287	case X86_XCPT_PF: /* Page fault */
1288	{
1289	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1290	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1291
1292	#ifdef DEBUG
1293	if (pVM->hwaccm.s.fNestedPaging)
1294	{ /* A genuine pagefault.
1295	* Forward the trap to the guest by injecting the exception and resuming execution.
1296	*/
1297	Log(("Guest page fault at %VGv cr2=%VGv error code %x rsp=%VGv\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1298	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1299
1300	/* Now we must update CR2. */
1301	pCtx->cr2 = uFaultAddress;
1302
1303	Event.au64[0] = 0;
1304	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1305	Event.n.u1Valid = 1;
1306	Event.n.u8Vector = X86_XCPT_PF;
1307	Event.n.u1ErrorCodeValid = 1;
1308	Event.n.u32ErrorCode = errCode;
1309
1310	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1311
1312	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1313	goto ResumeExecution;
1314	}
1315	#endif
1316	Assert(!pVM->hwaccm.s.fNestedPaging);
1317
1318	Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
1319	/* Exit qualification contains the linear address of the page fault. */
1320	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1321	TRPMSetErrorCode(pVM, errCode);
1322	TRPMSetFaultAddress(pVM, uFaultAddress);
1323
1324	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1325	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1326	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1327	if (rc == VINF_SUCCESS)
1328	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1329	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
1330	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1331
1332	TRPMResetTrap(pVM);
1333
1334	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1335	goto ResumeExecution;
1336	}
1337	else
1338	if (rc == VINF_EM_RAW_GUEST_TRAP)
1339	{ /* A genuine pagefault.
1340	* Forward the trap to the guest by injecting the exception and resuming execution.
1341	*/
1342	Log2(("Forward page fault to the guest\n"));
1343	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1344	/* The error code might have been changed. */
1345	errCode = TRPMGetErrorCode(pVM);
1346
1347	TRPMResetTrap(pVM);
1348
1349	/* Now we must update CR2. */
1350	pCtx->cr2 = uFaultAddress;
1351
1352	Event.au64[0] = 0;
1353	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1354	Event.n.u1Valid = 1;
1355	Event.n.u8Vector = X86_XCPT_PF;
1356	Event.n.u1ErrorCodeValid = 1;
1357	Event.n.u32ErrorCode = errCode;
1358
1359	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1360
1361	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1362	goto ResumeExecution;
1363	}
1364	#ifdef VBOX_STRICT
1365	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1366	LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1367	#endif
1368	/* Need to go back to the recompiler to emulate the instruction. */
1369	TRPMResetTrap(pVM);
1370	break;
1371	}
1372
1373	case X86_XCPT_MF: /* Floating point exception. */
1374	{
1375	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1376	if (!(pCtx->cr0 & X86_CR0_NE))
1377	{
1378	/* old style FPU error reporting needs some extra work. */
1379	/** @todo don't fall back to the recompiler, but do it manually. */
1380	rc = VINF_EM_RAW_EMULATE_INSTR;
1381	break;
1382	}
1383	Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1384
1385	Event.au64[0] = 0;
1386	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1387	Event.n.u1Valid = 1;
1388	Event.n.u8Vector = X86_XCPT_MF;
1389
1390	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1391
1392	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1393	goto ResumeExecution;
1394	}
1395
1396	#ifdef VBOX_STRICT
1397	case X86_XCPT_GP: /* General protection failure exception.*/
1398	case X86_XCPT_UD: /* Unknown opcode exception. */
1399	case X86_XCPT_DE: /* Debug exception. */
1400	case X86_XCPT_SS: /* Stack segment exception. */
1401	case X86_XCPT_NP: /* Segment not present exception. */
1402	{
1403	Event.au64[0] = 0;
1404	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1405	Event.n.u1Valid = 1;
1406	Event.n.u8Vector = vector;
1407
1408	switch(vector)
1409	{
1410	case X86_XCPT_GP:
1411	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1412	Event.n.u1ErrorCodeValid = 1;
1413	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1414	break;
1415	case X86_XCPT_DE:
1416	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1417	break;
1418	case X86_XCPT_UD:
1419	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1420	break;
1421	case X86_XCPT_SS:
1422	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1423	Event.n.u1ErrorCodeValid = 1;
1424	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1425	break;
1426	case X86_XCPT_NP:
1427	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1428	Event.n.u1ErrorCodeValid = 1;
1429	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1430	break;
1431	}
1432	Log(("Trap %x at %VGv esi=%x\n", vector, pCtx->rip, pCtx->esi));
1433	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1434
1435	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1436	goto ResumeExecution;
1437	}
1438	#endif
1439	default:
1440	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1441	rc = VERR_EM_INTERNAL_ERROR;
1442	break;
1443
1444	} /* switch (vector) */
1445	break;
1446	}
1447
1448	case SVM_EXIT_NPF:
1449	{
1450	/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1451	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1452	RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1453
1454	Assert(pVM->hwaccm.s.fNestedPaging);
1455	Log(("Nested page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, uFaultAddress, errCode));
1456	/* Exit qualification contains the linear address of the page fault. */
1457	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1458	TRPMSetErrorCode(pVM, errCode);
1459	TRPMSetFaultAddress(pVM, uFaultAddress);
1460
1461	/* Handle the pagefault trap for the nested shadow table. */
1462	rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMGetHostMode(pVM), errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1463	Log2(("PGMR0Trap0eHandlerNestedPaging %VGv returned %Vrc\n", pCtx->rip, rc));
1464	if (rc == VINF_SUCCESS)
1465	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1466	Log2(("Shadow page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, uFaultAddress, errCode));
1467	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1468
1469	TRPMResetTrap(pVM);
1470
1471	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1472	goto ResumeExecution;
1473	}
1474
1475	#ifdef VBOX_STRICT
1476	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1477	LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1478	#endif
1479	/* Need to go back to the recompiler to emulate the instruction. */
1480	TRPMResetTrap(pVM);
1481	break;
1482	}
1483
1484	case SVM_EXIT_VINTR:
1485	/* A virtual interrupt is about to be delivered, which means IF=1. */
1486	Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1487	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1488	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1489	goto ResumeExecution;
1490
1491	case SVM_EXIT_FERR_FREEZE:
1492	case SVM_EXIT_INTR:
1493	case SVM_EXIT_NMI:
1494	case SVM_EXIT_SMI:
1495	case SVM_EXIT_INIT:
1496	/* External interrupt; leave to allow it to be dispatched again. */
1497	rc = VINF_EM_RAW_INTERRUPT;
1498	break;
1499
1500	case SVM_EXIT_WBINVD:
1501	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1502	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1503	/* Skip instruction and continue directly. */
1504	pCtx->rip += 2; /** @note hardcoded opcode size! */
1505	/* Continue execution.*/
1506	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1507	goto ResumeExecution;
1508
1509	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1510	{
1511	Log2(("SVM: Cpuid at %VGv for %x\n", pCtx->rip, pCtx->eax));
1512	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1513	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1514	if (rc == VINF_SUCCESS)
1515	{
1516	/* Update EIP and continue execution. */
1517	pCtx->rip += 2; /** @note hardcoded opcode size! */
1518	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1519	goto ResumeExecution;
1520	}
1521	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1522	rc = VINF_EM_RAW_EMULATE_INSTR;
1523	break;
1524	}
1525
1526	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1527	{
1528	Log2(("SVM: Rdtsc\n"));
1529	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1530	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1531	if (rc == VINF_SUCCESS)
1532	{
1533	/* Update EIP and continue execution. */
1534	pCtx->rip += 2; /** @note hardcoded opcode size! */
1535	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1536	goto ResumeExecution;
1537	}
1538	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1539	rc = VINF_EM_RAW_EMULATE_INSTR;
1540	break;
1541	}
1542
1543	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1544	{
1545	Log2(("SVM: invlpg\n"));
1546	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1547
1548	Assert(!pVM->hwaccm.s.fNestedPaging);
1549
1550	/* Truly a pita. Why can't SVM give the same information as VT-x? */
1551	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1552	if (rc == VINF_SUCCESS)
1553	{
1554	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageInvlpg);
1555	goto ResumeExecution; /* eip already updated */
1556	}
1557	break;
1558	}
1559
1560	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1561	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1562	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1563	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1564	{
1565	uint32_t cbSize;
1566
1567	Log2(("SVM: %VGv mov cr%d, \n", pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
1568	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1569	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1570
1571	switch (exitCode - SVM_EXIT_WRITE_CR0)
1572	{
1573	case 0:
1574	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1575	break;
1576	case 2:
1577	break;
1578	case 3:
1579	Assert(!pVM->hwaccm.s.fNestedPaging);
1580	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1581	break;
1582	case 4:
1583	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1584	break;
1585	case 8:
1586	break;
1587	default:
1588	AssertFailed();
1589	}
1590	/* Check if a sync operation is pending. */
1591	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1592	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1593	{
1594	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1595	AssertRC(rc);
1596
1597	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBCRxChange);
1598
1599	/* Must be set by PGMSyncCR3 */
1600	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PROTECTED \|\| pVM->hwaccm.s.svm.fForceTLBFlush);
1601	}
1602	if (rc == VINF_SUCCESS)
1603	{
1604	/* EIP has been updated already. */
1605
1606	/* Only resume if successful. */
1607	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1608	goto ResumeExecution;
1609	}
1610	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1611	break;
1612	}
1613
1614	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1615	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1616	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1617	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1618	{
1619	uint32_t cbSize;
1620
1621	Log2(("SVM: %VGv mov x, cr%d\n", pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
1622	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1623	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1624	if (rc == VINF_SUCCESS)
1625	{
1626	/* EIP has been updated already. */
1627
1628	/* Only resume if successful. */
1629	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1630	goto ResumeExecution;
1631	}
1632	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1633	break;
1634	}
1635
1636	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1637	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1638	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1639	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1640	{
1641	uint32_t cbSize;
1642
1643	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
1644	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1645	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1646	if (rc == VINF_SUCCESS)
1647	{
1648	/* EIP has been updated already. */
1649
1650	/* Only resume if successful. */
1651	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1652	goto ResumeExecution;
1653	}
1654	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1655	break;
1656	}
1657
1658	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1659	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1660	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1661	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1662	{
1663	uint32_t cbSize;
1664
1665	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
1666	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1667	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1668	if (rc == VINF_SUCCESS)
1669	{
1670	/* EIP has been updated already. */
1671
1672	/* Only resume if successful. */
1673	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1674	goto ResumeExecution;
1675	}
1676	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1677	break;
1678	}
1679
1680	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1681	case SVM_EXIT_IOIO: /* I/O instruction. */
1682	{
1683	SVM_IOIO_EXIT IoExitInfo;
1684	uint32_t uIOSize, uAndVal;
1685
1686	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1687
1688	/** @todo could use a lookup table here */
1689	if (IoExitInfo.n.u1OP8)
1690	{
1691	uIOSize = 1;
1692	uAndVal = 0xff;
1693	}
1694	else
1695	if (IoExitInfo.n.u1OP16)
1696	{
1697	uIOSize = 2;
1698	uAndVal = 0xffff;
1699	}
1700	else
1701	if (IoExitInfo.n.u1OP32)
1702	{
1703	uIOSize = 4;
1704	uAndVal = 0xffffffff;
1705	}
1706	else
1707	{
1708	AssertFailed(); /* should be fatal. */
1709	rc = VINF_EM_RAW_EMULATE_INSTR;
1710	break;
1711	}
1712
1713	if (IoExitInfo.n.u1STR)
1714	{
1715	/* ins/outs */
1716	uint32_t prefix = 0;
1717	if (IoExitInfo.n.u1REP)
1718	prefix \|= PREFIX_REP;
1719
1720	if (IoExitInfo.n.u1Type == 0)
1721	{
1722	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1723	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1724	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1725	}
1726	else
1727	{
1728	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1729	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1730	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1731	}
1732	}
1733	else
1734	{
1735	/* normal in/out */
1736	Assert(!IoExitInfo.n.u1REP);
1737
1738	if (IoExitInfo.n.u1Type == 0)
1739	{
1740	Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1741	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1742	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1743	}
1744	else
1745	{
1746	uint32_t u32Val = 0;
1747
1748	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1749	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1750	if (IOM_SUCCESS(rc))
1751	{
1752	/* Write back to the EAX register. */
1753	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1754	Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1755	}
1756	}
1757	}
1758	/*
1759	* Handled the I/O return codes.
1760	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1761	*/
1762	if (IOM_SUCCESS(rc))
1763	{
1764	/* Update EIP and continue execution. */
1765	pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1766	if (RT_LIKELY(rc == VINF_SUCCESS))
1767	{
1768	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1769	goto ResumeExecution;
1770	}
1771	Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
1772	break;
1773	}
1774
1775	#ifdef VBOX_STRICT
1776	if (rc == VINF_IOM_HC_IOPORT_READ)
1777	Assert(IoExitInfo.n.u1Type != 0);
1778	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1779	Assert(IoExitInfo.n.u1Type == 0);
1780	else
1781	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1782	#endif
1783	Log2(("Failed IO at %VGv %x size %d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1784	break;
1785	}
1786
1787	case SVM_EXIT_HLT:
1788	/** Check if external interrupts are pending; if so, don't switch back. */
1789	pCtx->rip++; /* skip hlt */
1790	if ( pCtx->eflags.Bits.u1IF
1791	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1792	goto ResumeExecution;
1793
1794	rc = VINF_EM_HALT;
1795	break;
1796
1797	case SVM_EXIT_RSM:
1798	case SVM_EXIT_INVLPGA:
1799	case SVM_EXIT_VMRUN:
1800	case SVM_EXIT_VMMCALL:
1801	case SVM_EXIT_VMLOAD:
1802	case SVM_EXIT_VMSAVE:
1803	case SVM_EXIT_STGI:
1804	case SVM_EXIT_CLGI:
1805	case SVM_EXIT_SKINIT:
1806	case SVM_EXIT_RDTSCP:
1807	{
1808	/* Unsupported instructions. */
1809	SVM_EVENT Event;
1810
1811	Event.au64[0] = 0;
1812	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1813	Event.n.u1Valid = 1;
1814	Event.n.u8Vector = X86_XCPT_UD;
1815
1816	Log(("Forced #UD trap at %VGv\n", pCtx->rip));
1817	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1818
1819	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1820	goto ResumeExecution;
1821	}
1822
1823	/* Emulate in ring 3. */
1824	case SVM_EXIT_MSR:
1825	{
1826	uint32_t cbSize;
1827
1828	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1829	Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
1830	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1831	if (rc == VINF_SUCCESS)
1832	{
1833	/* EIP has been updated already. */
1834
1835	/* Only resume if successful. */
1836	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1837	goto ResumeExecution;
1838	}
1839	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
1840	break;
1841	}
1842
1843	case SVM_EXIT_MONITOR:
1844	case SVM_EXIT_RDPMC:
1845	case SVM_EXIT_PAUSE:
1846	case SVM_EXIT_MWAIT_UNCOND:
1847	case SVM_EXIT_MWAIT_ARMED:
1848	case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
1849	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1850	break;
1851
1852	case SVM_EXIT_SHUTDOWN:
1853	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1854	break;
1855
1856	case SVM_EXIT_IDTR_READ:
1857	case SVM_EXIT_GDTR_READ:
1858	case SVM_EXIT_LDTR_READ:
1859	case SVM_EXIT_TR_READ:
1860	case SVM_EXIT_IDTR_WRITE:
1861	case SVM_EXIT_GDTR_WRITE:
1862	case SVM_EXIT_LDTR_WRITE:
1863	case SVM_EXIT_TR_WRITE:
1864	case SVM_EXIT_CR0_SEL_WRITE:
1865	default:
1866	/* Unexpected exit codes. */
1867	rc = VERR_EM_INTERNAL_ERROR;
1868	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1869	break;
1870	}
1871
1872	end:
1873	if (fGuestStateSynced)
1874	{
1875	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1876	SVM_READ_SELREG(LDTR, ldtr);
1877	SVM_READ_SELREG(TR, tr);
1878
1879	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1880	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1881
1882	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1883	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1884	}
1885
1886	/* Signal changes for the recompiler. */
1887	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1888
1889	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1890	if (exitCode == SVM_EXIT_INTR)
1891	{
1892	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1893	/* On the next entry we'll only sync the host context. */
1894	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1895	}
1896	else
1897	{
1898	/* On the next entry we'll sync everything. */
1899	/** @todo we can do better than this */
1900	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1901	}
1902
1903	/* translate into a less severe return code */
1904	if (rc == VERR_EM_INTERPRETER)
1905	rc = VINF_EM_RAW_EMULATE_INSTR;
1906
1907	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1908	return rc;
1909	}
1910
1911	/**
1912	* Enters the AMD-V session
1913	*
1914	* @returns VBox status code.
1915	* @param pVM The VM to operate on.
1916	* @param pCpu CPU info struct
1917	*/
1918	HWACCMR0DECL(int) SVMR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
1919	{
1920	Assert(pVM->hwaccm.s.svm.fSupported);
1921
1922	LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVM->hwaccm.s.svm.idLastCpu, pCpu->uCurrentASID));
1923	pVM->hwaccm.s.svm.fResumeVM = false;
1924
1925	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1926	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
1927
1928	return VINF_SUCCESS;
1929	}
1930
1931
1932	/**
1933	* Leaves the AMD-V session
1934	*
1935	* @returns VBox status code.
1936	* @param pVM The VM to operate on.
1937	*/
1938	HWACCMR0DECL(int) SVMR0Leave(PVM pVM)
1939	{
1940	Assert(pVM->hwaccm.s.svm.fSupported);
1941	return VINF_SUCCESS;
1942	}
1943
1944
1945	static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1946	{
1947	OP_PARAMVAL param1;
1948	RTGCPTR addr;
1949
1950	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1951	if(VBOX_FAILURE(rc))
1952	return VERR_EM_INTERPRETER;
1953
1954	switch(param1.type)
1955	{
1956	case PARMTYPE_IMMEDIATE:
1957	case PARMTYPE_ADDRESS:
1958	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
1959	return VERR_EM_INTERPRETER;
1960	addr = param1.val.val64;
1961	break;
1962
1963	default:
1964	return VERR_EM_INTERPRETER;
1965	}
1966
1967	/** @todo is addr always a flat linear address or ds based
1968	* (in absence of segment override prefixes)????
1969	*/
1970	rc = PGMInvalidatePage(pVM, addr);
1971	if (VBOX_SUCCESS(rc))
1972	{
1973	/* Manually invalidate the page for the VM's TLB. */
1974	Log(("SVMInvlpgA %VGv ASID=%d\n", addr, uASID));
1975	SVMInvlpgA(addr, uASID);
1976	return VINF_SUCCESS;
1977	}
1978	Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
1979	return rc;
1980	}
1981
1982	/**
1983	* Interprets INVLPG
1984	*
1985	* @returns VBox status code.
1986	* @retval VINF_* Scheduling instructions.
1987	* @retval VERR_EM_INTERPRETER Something we can't cope with.
1988	* @retval VERR_* Fatal errors.
1989	*
1990	* @param pVM The VM handle.
1991	* @param pRegFrame The register frame.
1992	* @param ASID Tagged TLB id for the guest
1993	*
1994	* Updates the EIP if an instruction was executed successfully.
1995	*/
1996	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1997	{
1998	/*
1999	* Only allow 32 & 64 bits code.
2000	*/
2001	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2002	if (enmMode != CPUMODE_16BIT)
2003	{
2004	RTGCPTR pbCode;
2005	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2006	if (VBOX_SUCCESS(rc))
2007	{
2008	uint32_t cbOp;
2009	DISCPUSTATE Cpu;
2010
2011	Cpu.mode = enmMode;
2012	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
2013	Assert(VBOX_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
2014	if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
2015	{
2016	Assert(cbOp == Cpu.opsize);
2017	rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
2018	if (VBOX_SUCCESS(rc))
2019	{
2020	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2021	}
2022	return rc;
2023	}
2024	}
2025	}
2026	return VERR_EM_INTERPRETER;
2027	}
2028
2029
2030	/**
2031	* Invalidates a guest page
2032	*
2033	* @returns VBox status code.
2034	* @param pVM The VM to operate on.
2035	* @param GCVirt Page to invalidate
2036	*/
2037	HWACCMR0DECL(int) SVMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
2038	{
2039	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVM->hwaccm.s.svm.fForceTLBFlush;
2040
2041	/* Skip it if a TLB flush is already pending. */
2042	if (!fFlushPending)
2043	{
2044	SVM_VMCB *pVMCB;
2045
2046	Log2(("SVMR0InvalidatePage %VGv\n", GCVirt));
2047	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2048	Assert(pVM->hwaccm.s.svm.fSupported);
2049
2050	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
2051	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2052
2053	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageManual);
2054	SVMInvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2055	}
2056	return VINF_SUCCESS;
2057	}
2058
2059
2060	/**
2061	* Invalidates a guest page by physical address
2062	*
2063	* NOTE: Assumes the current instruction references this physical page though a virtual address!!
2064	*
2065	* @returns VBox status code.
2066	* @param pVM The VM to operate on.
2067	* @param GCPhys Page to invalidate
2068	*/
2069	HWACCMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys)
2070	{
2071	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVM->hwaccm.s.svm.fForceTLBFlush;
2072
2073	Assert(pVM->hwaccm.s.fNestedPaging);
2074
2075	/* Skip it if a TLB flush is already pending. */
2076	if (!fFlushPending)
2077	{
2078	CPUMCTX *pCtx;
2079	int rc;
2080	SVM_VMCB *pVMCB;
2081
2082	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
2083	AssertRCReturn(rc, rc);
2084
2085	Log2(("SVMR0InvalidatePhysPage %VGp\n", GCPhys));
2086	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2087	Assert(pVM->hwaccm.s.svm.fSupported);
2088
2089	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
2090	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2091
2092	/*
2093	* Only allow 32 & 64 bits code.
2094	*/
2095	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid);
2096	if (enmMode != CPUMODE_16BIT)
2097	{
2098	RTGCPTR pbCode;
2099	int rc = SELMValidateAndConvertCSAddr(pVM, pCtx->eflags, pCtx->ss, pCtx->cs, &pCtx->csHid, (RTGCPTR)pCtx->rip, &pbCode);
2100	if (VBOX_SUCCESS(rc))
2101	{
2102	uint32_t cbOp;
2103	DISCPUSTATE Cpu;
2104	OP_PARAMVAL param1;
2105	RTGCPTR addr;
2106
2107	Cpu.mode = enmMode;
2108	rc = EMInterpretDisasOneEx(pVM, pbCode, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
2109	AssertRCReturn(rc, rc);
2110	Assert(cbOp == Cpu.opsize);
2111
2112	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param1, &param1, PARAM_SOURCE);
2113	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2114
2115	switch(param1.type)
2116	{
2117	case PARMTYPE_IMMEDIATE:
2118	case PARMTYPE_ADDRESS:
2119	AssertReturn((param1.flags & (PARAM_VAL32\|PARAM_VAL64)), VERR_EM_INTERPRETER);
2120
2121	addr = param1.val.val64;
2122	break;
2123
2124	default:
2125	AssertFailed();
2126	return VERR_EM_INTERPRETER;
2127	}
2128
2129	/* Manually invalidate the page for the VM's TLB. */
2130	Log(("SVMR0InvalidatePhysPage Phys=%VGp Virt=%VGv ASID=%d\n", GCPhys, addr, pVMCB->ctrl.TLBCtrl.n.u32ASID));
2131	SVMInvlpgA(addr, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2132	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPhysPageManual);
2133
2134	return VINF_SUCCESS;
2135	}
2136	}
2137	AssertFailed();
2138	return VERR_EM_INTERPRETER;
2139	}
2140	return VINF_SUCCESS;
2141	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 11280

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