HWSVMR0.cpp@ 1

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1	/** @file
2	*
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/disopcode.h>
40	#include <iprt/param.h>
41	#include <iprt/assert.h>
42	#include <iprt/asm.h>
43	#include "HWSVMR0.h"
44
45	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
46
47	/**
48	* Sets up and activates SVM
49	*
50	* @returns VBox status code.
51	* @param pVM The VM to operate on.
52	*/
53	HWACCMR0DECL(int) SVMR0Setup(PVM pVM)
54	{
55	int rc = VINF_SUCCESS;
56	SVM_VMCB *pVMCB;
57
58	if (pVM == NULL)
59	return VERR_INVALID_PARAMETER;
60
61	/* Setup AMD SVM. */
62	Assert(pVM->hwaccm.s.svm.fSupported);
63
64	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
65	Assert(pVMCB);
66	if (pVMCB == 0)
67	return VERR_EM_INTERNAL_ERROR;
68
69	/* Program the control fields. Most of them never have to be changed again. */
70	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
71	/** @note CR0 & CR4 can be safely read when guest and shadow copies are identical. */
72	pVMCB->ctrl.u16InterceptRdCRx = BIT(0) \| BIT(3) \| BIT(4) \| BIT(8);
73
74	/*
75	* CR0/3/4 writes must be intercepted for obvious reasons.
76	*/
77	pVMCB->ctrl.u16InterceptWrCRx = BIT(0) \| BIT(3) \| BIT(4) \| BIT(8);
78
79	/* Intercept all DRx reads and writes. */
80	pVMCB->ctrl.u16InterceptRdDRx = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \| BIT(6) \| BIT(7);
81	pVMCB->ctrl.u16InterceptWrDRx = BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(5) \| BIT(6) \| BIT(7);
82
83	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
84	* All breakpoints are automatically cleared when the VM exits.
85	*/
86
87	/** @todo nested paging */
88	/* Intercept #NM only; #PF is not relevant due to nested paging (we get a seperate exit code (SVM_EXIT_NPF) for
89	* pagefaults that need our attention).
90	*/
91	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
92
93	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
94	\| SVM_CTRL1_INTERCEPT_VINTR
95	\| SVM_CTRL1_INTERCEPT_NMI
96	\| SVM_CTRL1_INTERCEPT_SMI
97	\| SVM_CTRL1_INTERCEPT_INIT
98	\| SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
99	\| SVM_CTRL1_INTERCEPT_RDPMC
100	\| SVM_CTRL1_INTERCEPT_CPUID
101	\| SVM_CTRL1_INTERCEPT_RSM
102	\| SVM_CTRL1_INTERCEPT_HLT
103	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
104	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
105	\| SVM_CTRL1_INTERCEPT_INVLPG
106	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
107	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
108	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
109	;
110	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
111	\| SVM_CTRL2_INTERCEPT_VMMCALL
112	\| SVM_CTRL2_INTERCEPT_VMLOAD
113	\| SVM_CTRL2_INTERCEPT_VMSAVE
114	\| SVM_CTRL2_INTERCEPT_STGI
115	\| SVM_CTRL2_INTERCEPT_CLGI
116	\| SVM_CTRL2_INTERCEPT_SKINIT
117	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
118	;
119	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
120	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
121	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
122
123	/* Virtualize masking of INTR interrupts. */
124	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
125
126	/* Set IO and MSR bitmap addresses. */
127	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
128	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
129
130	/* Enable nested paging. */
131	/** @todo how to detect support for this?? */
132	pVMCB->ctrl.u64NestedPaging = 0; /** @todo SVM_NESTED_PAGING_ENABLE; */
133
134	/* No LBR virtualization. */
135	pVMCB->ctrl.u64LBRVirt = 0;
136
137	return rc;
138	}
139
140
141	/**
142	* Injects an event (trap or external interrupt)
143	*
144	* @param pVM The VM to operate on.
145	* @param pVMCB SVM control block
146	* @param pCtx CPU Context
147	* @param pIntInfo SVM interrupt info
148	*/
149	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
150	{
151	#ifdef VBOX_STRICT
152	if (pEvent->n.u8Vector == 0xE)
153	Log(("SVMR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
154	else
155	if (pEvent->n.u8Vector < 0x20)
156	Log(("SVMR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode));
157	else
158	{
159	Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->eip));
160	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
161	Assert(pCtx->eflags.u32 & X86_EFL_IF);
162	}
163	#endif
164
165	/* Set event injection state. */
166	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
167	}
168
169
170	/**
171	* Checks for pending guest interrupts and injects them
172	*
173	* @returns VBox status code.
174	* @param pVM The VM to operate on.
175	* @param pVMCB SVM control block
176	* @param pCtx CPU Context
177	*/
178	static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx)
179	{
180	int rc;
181
182	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
183	if (pVM->hwaccm.s.Event.fPending)
184	{
185	SVM_EVENT Event;
186
187	Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
188	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
189	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
190	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
191
192	pVM->hwaccm.s.Event.fPending = false;
193	return VINF_SUCCESS;
194	}
195
196	/* When external interrupts are pending, we should exit the VM when IF is set. */
197	if ( !TRPMHasTrap(pVM)
198	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
199	{
200	if (!(pCtx->eflags.u32 & X86_EFL_IF))
201	{
202	Log2(("Enable irq window exit!\n"));
203	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
204	//// pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
205	//// AssertRC(rc);
206	}
207	else
208	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
209	{
210	uint8_t u8Interrupt;
211
212	rc = PDMGetInterrupt(pVM, &u8Interrupt);
213	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
214	if (VBOX_SUCCESS(rc))
215	{
216	rc = TRPMAssertTrap(pVM, u8Interrupt, false);
217	AssertRC(rc);
218	}
219	else
220	{
221	/* can't happen... */
222	AssertFailed();
223	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
224	return VINF_EM_RAW_INTERRUPT_PENDING;
225	}
226	}
227	else
228	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
229	}
230
231	#ifdef VBOX_STRICT
232	if (TRPMHasTrap(pVM))
233	{
234	uint8_t u8Vector;
235	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
236	AssertRC(rc);
237	Assert(u8Vector >= 0x20);
238	}
239	#endif
240
241	if ( pCtx->eflags.u32 & X86_EFL_IF
242	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
243	&& TRPMHasTrap(pVM)
244	)
245	{
246	uint8_t u8Vector;
247	int rc;
248	bool fSoftwareInt;
249	SVM_EVENT Event;
250	uint32_t u32ErrorCode;
251
252	Event.au64[0] = 0;
253
254	/* If a new event is pending, then dispatch it now. */
255	rc = TRPMQueryTrapAll(pVM, &u8Vector, &fSoftwareInt, &u32ErrorCode, 0);
256	AssertRC(rc);
257	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| u8Vector < 0x20);
258	Assert(fSoftwareInt == false);
259
260	/* Clear the pending trap. */
261	rc = TRPMResetTrap(pVM);
262	AssertRC(rc);
263
264	Event.n.u8Vector = u8Vector;
265	Event.n.u1Valid = 1;
266	Event.n.u32ErrorCode = u32ErrorCode;
267
268	switch (u8Vector) {
269	case 8:
270	case 10:
271	case 11:
272	case 12:
273	case 13:
274	case 14:
275	case 17:
276	/* Valid error codes. */
277	Event.n.u1ErrorCodeValid = 1;
278	break;
279	default:
280	break;
281	}
282
283	if (u8Vector == X86_XCPT_NMI)
284	Event.n.u3Type = SVM_EVENT_NMI;
285	else
286	if (u8Vector < 0x20)
287	Event.n.u3Type = SVM_EVENT_EXCEPTION;
288	else
289	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
290
291	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
292	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
293	} /* if (interrupts can be dispatched) */
294
295	return VINF_SUCCESS;
296	}
297
298
299	/**
300	* Loads the guest state
301	*
302	* @returns VBox status code.
303	* @param pVM The VM to operate on.
304	* @param pCtx Guest context
305	*/
306	HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
307	{
308	int rc = VINF_SUCCESS;
309	RTGCUINTPTR val;
310	SVM_VMCB *pVMCB;
311
312	if (pVM == NULL)
313	return VERR_INVALID_PARAMETER;
314
315	/* Setup AMD SVM. */
316	Assert(pVM->hwaccm.s.svm.fSupported);
317
318	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
319	Assert(pVMCB);
320	if (pVMCB == 0)
321	return VERR_EM_INTERNAL_ERROR;
322
323	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
324	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
325	{
326	SVM_WRITE_SELREG(CS, cs);
327	Assert(pVMCB->guest.CS.u16Sel \|\| !pVMCB->guest.CS.u16Attr);
328
329	SVM_WRITE_SELREG(SS, ss);
330	Assert(pVMCB->guest.SS.u16Sel \|\| !pVMCB->guest.SS.u16Attr);
331
332	SVM_WRITE_SELREG(DS, ds);
333	Assert(pVMCB->guest.DS.u16Sel \|\| !pVMCB->guest.DS.u16Attr);
334
335	SVM_WRITE_SELREG(ES, es);
336	Assert(pVMCB->guest.ES.u16Sel \|\| !pVMCB->guest.ES.u16Attr);
337
338	SVM_WRITE_SELREG(FS, fs);
339	Assert(pVMCB->guest.FS.u16Sel \|\| !pVMCB->guest.FS.u16Attr);
340
341	SVM_WRITE_SELREG(GS, gs);
342	Assert(pVMCB->guest.GS.u16Sel \|\| !pVMCB->guest.GS.u16Attr);
343	}
344
345	/* Guest CPU context: LDTR. */
346	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
347	{
348	SVM_WRITE_SELREG(LDTR, ldtr);
349	}
350
351	/* Guest CPU context: TR. */
352	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
353	{
354	SVM_WRITE_SELREG(TR, tr);
355	}
356
357	/* Guest CPU context: GDTR. */
358	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
359	{
360	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
361	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
362	}
363
364	/* Guest CPU context: IDTR. */
365	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
366	{
367	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
368	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
369	}
370
371	/*
372	* Sysenter MSRs
373	*/
374	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SYSENTER_MSR)
375	{
376	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
377	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
378	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
379	}
380
381	/* Control registers */
382	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
383	{
384	val = pCtx->cr0;
385	if (CPUMIsGuestFPUStateActive(pVM) == false)
386	{
387	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
388	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
389	}
390	else
391	{
392	Assert(pVM->hwaccm.s.svm.fResumeVM == true);
393	/** @todo check if we support the old style mess correctly. */
394	if (!(val & X86_CR0_NE))
395	{
396	Log(("Forcing X86_CR0_NE!!!\n"));
397
398	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
399	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
400	{
401	pVMCB->ctrl.u32InterceptException \|= BIT(16);
402	pVM->hwaccm.s.fFPUOldStyleOverride = true;
403	}
404	}
405	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
406	}
407	/* Illegal when cache is turned on. */
408	val &= ~X86_CR0_NW;
409
410	pVMCB->guest.u64CR0 = val;
411	}
412	/* CR2 as well */
413	pVMCB->guest.u64CR2 = pCtx->cr2;
414
415	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
416	{
417	/* Save our shadow CR3 register. */
418	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
419	}
420
421	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
422	{
423	val = pCtx->cr4;
424	switch(pVM->hwaccm.s.enmShadowMode)
425	{
426	case PGMMODE_REAL:
427	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
428	AssertFailed();
429	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
430
431	case PGMMODE_32_BIT: /* 32-bit paging. */
432	break;
433
434	case PGMMODE_PAE: /* PAE paging. */
435	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
436	/** @todo use normal 32 bits paging */
437	val \|= X86_CR4_PAE;
438	break;
439
440	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
441	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
442	AssertFailed();
443	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
444
445	default: /* shut up gcc */
446	AssertFailed();
447	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
448	}
449	pVMCB->guest.u64CR4 = val;
450	}
451
452	/* Debug registers. */
453	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
454	{
455	/** @todo DR0-6 */
456	val = pCtx->dr7;
457	val &= ~(BIT(11) \| BIT(12) \| BIT(14) \| BIT(15)); /* must be zero */
458	val \|= 0x400; /* must be one */
459	#ifdef VBOX_STRICT
460	val = 0x400;
461	#endif
462	pVMCB->guest.u64DR7 = val;
463
464	pVMCB->guest.u64DR6 = pCtx->dr6;
465	}
466
467	/* EIP, ESP and EFLAGS */
468	pVMCB->guest.u64RIP = pCtx->eip;
469	pVMCB->guest.u64RSP = pCtx->esp;
470	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
471
472	/* Set CPL */
473	if (!(pCtx->cr0 & X86_CR0_PE))
474	pVMCB->guest.u8CPL = 0;
475	else
476	if (pCtx->eflags.Bits.u1VM)
477	pVMCB->guest.u8CPL = 3;
478	else
479	pVMCB->guest.u8CPL = (pCtx->ss & X86_SEL_RPL);
480
481	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
482	pVMCB->guest.u64RAX = pCtx->eax;
483
484	/* vmrun will fail otherwise. */
485	pVMCB->guest.u64EFER = MSR_K6_EFER_SVME;
486
487	/** @note We can do more complex things with tagged TLBs. */
488	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
489
490	/** @todo TSC offset. */
491	/** @todo 64 bits stuff (?):
492	* - STAR
493	* - LSTAR
494	* - CSTAR
495	* - SFMASK
496	* - KernelGSBase
497	*/
498
499	/* Done. */
500	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
501
502	return rc;
503	}
504
505
506	/**
507	* Runs guest code in an SVM VM.
508	*
509	* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
510	*
511	* @returns VBox status code.
512	* @param pVM The VM to operate on.
513	* @param pCtx Guest context
514	*/
515	HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
516	{
517	int rc = VINF_SUCCESS;
518	uint64_t exitCode;
519	SVM_VMCB *pVMCB;
520	bool fForceTLBFlush = false;
521	int cResume = 0;
522
523	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
524
525	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
526	Assert(pVMCB);
527	if (pVMCB == 0)
528	return VERR_EM_INTERNAL_ERROR;
529
530	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
531	*/
532	ResumeExecution:
533	cResume++;
534
535	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
536	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
537	{
538	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
539	if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
540	{
541	/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
542	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
543	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
544	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
545	*/
546	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
547	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
548	pVMCB->ctrl.u64IntShadow = 0;
549	}
550	}
551	else
552	{
553	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
554	pVMCB->ctrl.u64IntShadow = 0;
555	}
556
557	/* Check for pending actions that force us to go back to ring 3. */
558	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
559	{
560	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
561	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
562	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
563	rc = VINF_EM_RAW_TO_R3;
564	goto end;
565	}
566	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
567	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
568	{
569	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
570	rc = VINF_EM_PENDING_REQUEST;
571	goto end;
572	}
573
574	/* When external interrupts are pending, we should exit the VM when IF is set. */
575	/** @note after VM_FF_INHIBIT_INTERRUPTS check!!! */
576	rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
577	if (VBOX_FAILURE(rc))
578	{
579	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
580	goto end;
581	}
582
583	/** @todo check timers?? */
584
585	/* Load the guest state */
586	rc = SVMR0LoadGuestState(pVM, pCtx);
587	if (rc != VINF_SUCCESS)
588	{
589	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
590	goto end;
591	}
592
593	/* All done! Let's start VM execution. */
594	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
595	if ( pVM->hwaccm.s.svm.fResumeVM == false
596	\|\| fForceTLBFlush)
597	{
598	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1;
599	}
600	else
601	{
602	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 0;
603	}
604	/* In case we execute a goto ResumeExecution later on. */
605	pVM->hwaccm.s.svm.fResumeVM = true;
606	fForceTLBFlush = false;
607
608	Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
609	Assert(pVMCB->ctrl.u32InterceptCtrl1 == ( SVM_CTRL1_INTERCEPT_INTR
610	\| SVM_CTRL1_INTERCEPT_VINTR
611	\| SVM_CTRL1_INTERCEPT_NMI
612	\| SVM_CTRL1_INTERCEPT_SMI
613	\| SVM_CTRL1_INTERCEPT_INIT
614	\| SVM_CTRL1_INTERCEPT_CR0 /** @todo redundant? */
615	\| SVM_CTRL1_INTERCEPT_RDPMC
616	\| SVM_CTRL1_INTERCEPT_CPUID
617	\| SVM_CTRL1_INTERCEPT_RSM
618	\| SVM_CTRL1_INTERCEPT_HLT
619	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
620	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
621	\| SVM_CTRL1_INTERCEPT_INVLPG
622	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
623	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
624	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE /* Legacy FPU FERR handling. */
625	));
626	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
627	\| SVM_CTRL2_INTERCEPT_VMMCALL
628	\| SVM_CTRL2_INTERCEPT_VMLOAD
629	\| SVM_CTRL2_INTERCEPT_VMSAVE
630	\| SVM_CTRL2_INTERCEPT_STGI
631	\| SVM_CTRL2_INTERCEPT_CLGI
632	\| SVM_CTRL2_INTERCEPT_SKINIT
633	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
634	));
635	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
636	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
637	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
638	Assert(pVMCB->ctrl.u64NestedPaging == 0);
639	Assert(pVMCB->ctrl.u64LBRVirt == 0);
640
641	SVMVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
642	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
643
644	/**
645	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
646	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
647	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
648	*/
649
650	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
651
652	/* Reason for the VM exit */
653	exitCode = pVMCB->ctrl.u64ExitCode;
654
655	if (exitCode == SVM_EXIT_INVALID) /* Invalid guest state. */
656	{
657	HWACCMDumpRegs(pCtx);
658	#ifdef DEBUG
659	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
660	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
661	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
662	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
663	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
664	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
665	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
666	Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
667	Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
668	Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
669
670	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
671	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
672	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
673	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
674
675	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
676	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
677	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
678	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
679	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
680	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
681	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
682	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
683	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
684	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
685
686	Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
687	Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
688	Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
689	Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
690	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
691	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
692	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
693	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
694	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
695	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
696	Log(("ctrl.u64NestedPaging %VX64\n", pVMCB->ctrl.u64NestedPaging));
697	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
698	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
699	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
700	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
701	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
702	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
703
704	Log(("ctrl.u64HostCR3 %VX64\n", pVMCB->ctrl.u64HostCR3));
705	Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
706
707	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
708	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
709	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
710	Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
711	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
712	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
713	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
714	Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
715	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
716	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
717	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
718	Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
719	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
720	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
721	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
722	Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
723	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
724	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
725	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
726	Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
727
728	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
729	Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
730
731	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
732	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
733	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
734	Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
735
736	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
737	Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
738
739	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
740	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
741	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
742	Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
743
744	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
745	Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
746	Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
747	Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
748	Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
749	Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
750	Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
751
752	Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
753	Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
754	Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
755	Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
756
757	Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
758	Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
759	Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
760
761	Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
762	Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
763	Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
764	Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
765	Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
766	Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
767	Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
768	Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
769	Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
770	Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
771	Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
772	Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
773
774	#endif
775	rc = VERR_SVM_UNABLE_TO_START_VM;
776	goto end;
777	}
778
779	/* Let's first sync back eip, esp, and eflags. */
780	pCtx->eip = pVMCB->guest.u64RIP;
781	pCtx->esp = pVMCB->guest.u64RSP;
782	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
783	/* eax is saved/restore across the vmrun instruction */
784	pCtx->eax = pVMCB->guest.u64RAX;
785
786	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
787	SVM_READ_SELREG(SS, ss);
788	SVM_READ_SELREG(CS, cs);
789	SVM_READ_SELREG(DS, ds);
790	SVM_READ_SELREG(ES, es);
791	SVM_READ_SELREG(FS, fs);
792	SVM_READ_SELREG(GS, gs);
793
794	/** @note no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
795
796	/** @note NOW IT'S SAFE FOR LOGGING! */
797
798	/* Take care of instruction fusing (sti, mov ss) */
799	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
800	{
801	Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->eip));
802	EMSetInhibitInterruptsPC(pVM, pCtx->eip);
803	}
804	else
805	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
806
807	Log2(("exitCode = %x\n", exitCode));
808
809	/* Check if an injected event was interrupted prematurely. */
810	pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
811	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
812	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
813	{
814	Log(("Pending inject %VX64 at %08x exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitCode));
815	pVM->hwaccm.s.Event.fPending = true;
816	/* Error code present? (redundant) */
817	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
818	{
819	pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
820	}
821	else
822	pVM->hwaccm.s.Event.errCode = 0;
823	}
824	/** @note Safety precaution; frequent loops have been observed even though external interrupts were pending. */
825	if (cResume > 32 /* low limit, but anything higher risks a hanging host due to interrupts left pending for too long */)
826	{
827	exitCode = SVM_EXIT_INTR;
828	}
829
830	/* Deal with the reason of the VM-exit. */
831	switch (exitCode)
832	{
833	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
834	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
835	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
836	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
837	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
838	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
839	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
840	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
841	{
842	/* Pending trap. */
843	SVM_EVENT Event;
844	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
845
846	Log2(("Hardware/software interrupt %d\n", vector));
847	switch (vector)
848	{
849	case X86_XCPT_NM:
850	{
851	uint32_t oldCR0;
852
853	Log(("#NM fault at %VGv\n", pCtx->eip));
854
855	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
856	oldCR0 = ASMGetCR0();
857	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
858	rc = CPUMHandleLazyFPU(pVM);
859	if (rc == VINF_SUCCESS)
860	{
861	Assert(CPUMIsGuestFPUStateActive(pVM));
862
863	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
864	ASMSetCR0(oldCR0);
865
866	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
867
868	/* Continue execution. */
869	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
870	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
871
872	goto ResumeExecution;
873	}
874
875	Log(("Forward #NM fault to the guest\n"));
876	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
877
878	Event.au64[0] = 0;
879	Event.n.u3Type = SVM_EVENT_EXCEPTION;
880	Event.n.u1Valid = 1;
881	Event.n.u8Vector = X86_XCPT_NM;
882
883	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
884	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
885	goto ResumeExecution;
886	}
887
888	case X86_XCPT_PF: /* Page fault */
889	{
890	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
891	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
892
893	Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
894	/* Exit qualification contains the linear address of the page fault. */
895	TRPMAssertTrap(pVM, X86_XCPT_PF, false);
896	TRPMSetErrorCode(pVM, errCode);
897	TRPMSetFaultAddress(pVM, uFaultAddress);
898
899	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
900	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
901	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
902	if (rc == VINF_SUCCESS)
903	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
904	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
905	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
906
907	TRPMResetTrap(pVM);
908
909	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
910	goto ResumeExecution;
911	}
912	else
913	if (rc == VINF_EM_RAW_GUEST_TRAP)
914	{ /* A genuine pagefault.
915	* Forward the trap to the guest by injecting the exception and resuming execution.
916	*/
917	Log2(("Forward page fault to the guest\n"));
918	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
919	/* The error code might have been changed. */
920	errCode = TRPMGetErrorCode(pVM);
921
922	TRPMResetTrap(pVM);
923
924	/* Now we must update CR2. */
925	pCtx->cr2 = uFaultAddress;
926
927	Event.au64[0] = 0;
928	Event.n.u3Type = SVM_EVENT_EXCEPTION;
929	Event.n.u1Valid = 1;
930	Event.n.u8Vector = X86_XCPT_PF;
931	Event.n.u1ErrorCodeValid = 1;
932	Event.n.u32ErrorCode = errCode;
933
934	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
935
936	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
937	goto ResumeExecution;
938	}
939	#ifdef VBOX_STRICT
940	if (rc != VINF_EM_RAW_EMULATE_INSTR)
941	Log(("PGMTrap0eHandler failed with %d\n", rc));
942	#endif
943	/* Need to go back to the recompiler to emulate the instruction. */
944	TRPMResetTrap(pVM);
945	break;
946	}
947
948	case X86_XCPT_MF: /* Floating point exception. */
949	{
950	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
951	if (!(pCtx->cr0 & X86_CR0_NE))
952	{
953	/* old style FPU error reporting needs some extra work. */
954	/** @todo don't fall back to the recompiler, but do it manually. */
955	rc = VINF_EM_RAW_EMULATE_INSTR;
956	break;
957	}
958	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
959
960	Event.au64[0] = 0;
961	Event.n.u3Type = SVM_EVENT_EXCEPTION;
962	Event.n.u1Valid = 1;
963	Event.n.u8Vector = X86_XCPT_MF;
964
965	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
966
967	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
968	goto ResumeExecution;
969	}
970
971	case X86_XCPT_GP: /* General protection failure exception.*/
972	{
973	if (pCtx->eflags.Bits.u1VM == 1)
974	{
975	Log(("#GP in V86 mode -> fall back\n"));
976	/** @note workaround for #GP loop; looks like an SVM bug */
977	rc = VINF_EM_RAW_EMULATE_INSTR;
978	break;
979	}
980	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
981
982	Event.au64[0] = 0;
983	Event.n.u3Type = SVM_EVENT_EXCEPTION;
984	Event.n.u1Valid = 1;
985	Event.n.u8Vector = X86_XCPT_GP;
986	Event.n.u1ErrorCodeValid= 1;
987	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
988	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
989	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
990
991	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
992	goto ResumeExecution;
993	}
994
995	#ifdef VBOX_STRICT
996	case X86_XCPT_UD: /* Unknown opcode exception. */
997	case X86_XCPT_DE: /* Debug exception. */
998	case X86_XCPT_SS: /* Stack segment exception. */
999	case X86_XCPT_NP: /* Segment not present exception. */
1000	{
1001	Event.au64[0] = 0;
1002	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1003	Event.n.u1Valid = 1;
1004	Event.n.u8Vector = vector;
1005
1006	switch(vector)
1007	{
1008	case X86_XCPT_DE:
1009	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1010	break;
1011	case X86_XCPT_UD:
1012	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1013	break;
1014	case X86_XCPT_SS:
1015	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1016	Event.n.u1ErrorCodeValid = 1;
1017	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1018	break;
1019	case X86_XCPT_NP:
1020	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1021	Event.n.u1ErrorCodeValid = 1;
1022	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1023	break;
1024	}
1025
1026	Log(("Trap %x at %VGv\n", vector, pCtx->eip));
1027	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1028
1029	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1030	goto ResumeExecution;
1031	}
1032	#endif
1033	default:
1034	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1035	rc = VERR_EM_INTERNAL_ERROR;
1036	break;
1037
1038	} /* switch (vector) */
1039	break;
1040	}
1041
1042	case SVM_EXIT_FERR_FREEZE:
1043	case SVM_EXIT_INTR:
1044	case SVM_EXIT_NMI:
1045	case SVM_EXIT_SMI:
1046	case SVM_EXIT_INIT:
1047	case SVM_EXIT_VINTR:
1048	/* External interrupt; leave to allow it to be dispatched again. */
1049	rc = VINF_EM_RAW_INTERRUPT;
1050	break;
1051
1052	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1053	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1054	/* Skip instruction and continue directly. */
1055	pCtx->eip += 2; /** @note hardcoded opcode size! */
1056	/* Continue execution.*/
1057	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1058	goto ResumeExecution;
1059
1060	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1061	{
1062	Log2(("SVM: Cpuid %x\n", pCtx->eax));
1063	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1064	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1065	if (rc == VINF_SUCCESS)
1066	{
1067	/* Update EIP and continue execution. */
1068	pCtx->eip += 2; /** @note hardcoded opcode size! */
1069	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1070	goto ResumeExecution;
1071	}
1072	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1073	rc = VINF_EM_RAW_EMULATE_INSTR;
1074	break;
1075	}
1076
1077	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1078	{
1079	Log2(("VMX: invlpg\n"));
1080	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1081
1082	/* Truly a pita. Why can't SVM give the same information as VMX? */
1083	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1084	break;
1085	}
1086
1087	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1088	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1089	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1090	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1091	{
1092	uint32_t cbSize;
1093
1094	Log2(("VMX: %VGv mov cr%d, \n", pCtx->eip, exitCode - SVM_EXIT_WRITE_CR0));
1095	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1096	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1097
1098	switch (exitCode - SVM_EXIT_WRITE_CR0)
1099	{
1100	case 0:
1101	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1102	break;
1103	case 2:
1104	break;
1105	case 3:
1106	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1107	break;
1108	case 4:
1109	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1110	break;
1111	default:
1112	AssertFailed();
1113	}
1114	/* Check if a sync operation is pending. */
1115	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1116	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1117	{
1118	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1119	AssertRC(rc);
1120
1121	/** @note Force a TLB flush. SVM requires us to do it manually. */
1122	fForceTLBFlush = true;
1123	}
1124	if (rc == VINF_SUCCESS)
1125	{
1126	/* EIP has been updated already. */
1127
1128	/* Only resume if successful. */
1129	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1130	goto ResumeExecution;
1131	}
1132	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1133	if (rc == VERR_EM_INTERPRETER)
1134	rc = VINF_EM_RAW_EMULATE_INSTR;
1135	break;
1136	}
1137
1138	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1139	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1140	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1141	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1142	{
1143	uint32_t cbSize;
1144
1145	Log2(("VMX: %VGv mov x, cr%d\n", pCtx->eip, exitCode - SVM_EXIT_READ_CR0));
1146	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1147	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1148	if (rc == VINF_SUCCESS)
1149	{
1150	/* EIP has been updated already. */
1151
1152	/* Only resume if successful. */
1153	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1154	goto ResumeExecution;
1155	}
1156	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1157	if (rc == VERR_EM_INTERPRETER)
1158	rc = VINF_EM_RAW_EMULATE_INSTR;
1159	break;
1160	}
1161
1162	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1163	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1164	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1165	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1166	{
1167	uint32_t cbSize;
1168
1169	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_WRITE_DR0));
1170	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1171	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1172	if (rc == VINF_SUCCESS)
1173	{
1174	/* EIP has been updated already. */
1175
1176	/* Only resume if successful. */
1177	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1178	goto ResumeExecution;
1179	}
1180	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1181	if (rc == VERR_EM_INTERPRETER)
1182	rc = VINF_EM_RAW_EMULATE_INSTR;
1183	break;
1184	}
1185
1186	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1187	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1188	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1189	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1190	{
1191	uint32_t cbSize;
1192
1193	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_READ_DR0));
1194	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1195	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1196	if (rc == VINF_SUCCESS)
1197	{
1198	/* EIP has been updated already. */
1199
1200	/* Only resume if successful. */
1201	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1202	goto ResumeExecution;
1203	}
1204	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1205	if (rc == VERR_EM_INTERPRETER)
1206	rc = VINF_EM_RAW_EMULATE_INSTR;
1207	break;
1208	}
1209
1210	/** @note We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1211	case SVM_EXIT_IOIO: /* I/O instruction. */
1212	{
1213	SVM_IOIO_EXIT IoExitInfo;
1214	uint32_t uIOSize, uAndVal;
1215
1216	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1217
1218	/** @todo could use a lookup table here */
1219	if (IoExitInfo.n.u1OP8)
1220	{
1221	uIOSize = 1;
1222	uAndVal = 0xff;
1223	}
1224	else
1225	if (IoExitInfo.n.u1OP16)
1226	{
1227	uIOSize = 2;
1228	uAndVal = 0xffff;
1229	}
1230	else
1231	if (IoExitInfo.n.u1OP32)
1232	{
1233	uIOSize = 4;
1234	uAndVal = 0xffffffff;
1235	}
1236	else
1237	{
1238	AssertFailed(); /* should be fatal. */
1239	rc = VINF_EM_RAW_EMULATE_INSTR;
1240	break;
1241	}
1242
1243	/* First simple in and out instructions. */
1244	/** @todo str & rep */
1245	if ( !IoExitInfo.n.u1REP
1246	&& !IoExitInfo.n.u1STR
1247	)
1248	{
1249	if (IoExitInfo.n.u1Type == 0)
1250	{
1251	Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1252	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1253	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1254	}
1255	else
1256	{
1257	uint32_t u32Val = 0;
1258
1259	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1260	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1261	if (rc == VINF_SUCCESS)
1262	{
1263	/* Write back to the EAX register. */
1264	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1265	Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1266	}
1267	}
1268	if (rc == VINF_SUCCESS)
1269	{
1270	/* Update EIP and continue execution. */
1271	pCtx->eip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1272	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1273	goto ResumeExecution;
1274	}
1275	Assert(rc == VINF_IOM_HC_IOPORT_READ \|\| rc == VINF_IOM_HC_IOPORT_WRITE);
1276	rc = (IoExitInfo.n.u1Type == 0) ? VINF_IOM_HC_IOPORT_WRITE : VINF_IOM_HC_IOPORT_READ;
1277	}
1278	else
1279	rc = VINF_IOM_HC_IOPORT_READWRITE;
1280
1281	break;
1282	}
1283
1284	case SVM_EXIT_HLT:
1285	/** Check if external interrupts are pending; if so, don't switch back. */
1286	if (VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1287	{
1288	pCtx->eip++; /* skip hlt */
1289	goto ResumeExecution;
1290	}
1291
1292	rc = VINF_EM_RAW_EMULATE_INSTR_HLT;
1293	break;
1294
1295	case SVM_EXIT_RDPMC:
1296	case SVM_EXIT_RSM:
1297	case SVM_EXIT_INVLPGA:
1298	case SVM_EXIT_VMRUN:
1299	case SVM_EXIT_VMMCALL:
1300	case SVM_EXIT_VMLOAD:
1301	case SVM_EXIT_VMSAVE:
1302	case SVM_EXIT_STGI:
1303	case SVM_EXIT_CLGI:
1304	case SVM_EXIT_SKINIT:
1305	case SVM_EXIT_RDTSCP:
1306	{
1307	/* Unsupported instructions. */
1308	SVM_EVENT Event;
1309
1310	Event.au64[0] = 0;
1311	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1312	Event.n.u1Valid = 1;
1313	Event.n.u8Vector = X86_XCPT_UD;
1314
1315	Log(("Forced #UD trap at %VGv\n", pCtx->eip));
1316	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1317
1318	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1319	goto ResumeExecution;
1320	}
1321
1322	/* Emulate RDMSR & WRMSR in ring 3. */
1323	case SVM_EXIT_MSR:
1324	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
1325	break;
1326
1327	case SVM_EXIT_NPF:
1328	AssertFailed(); /* unexpected */
1329	break;
1330
1331	case SVM_EXIT_SHUTDOWN:
1332	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
1333	break;
1334
1335	case SVM_EXIT_PAUSE:
1336	case SVM_EXIT_IDTR_READ:
1337	case SVM_EXIT_GDTR_READ:
1338	case SVM_EXIT_LDTR_READ:
1339	case SVM_EXIT_TR_READ:
1340	case SVM_EXIT_IDTR_WRITE:
1341	case SVM_EXIT_GDTR_WRITE:
1342	case SVM_EXIT_LDTR_WRITE:
1343	case SVM_EXIT_TR_WRITE:
1344	case SVM_EXIT_CR0_SEL_WRITE:
1345	default:
1346	/* Unexpected exit codes. */
1347	rc = VERR_EM_INTERNAL_ERROR;
1348	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
1349	break;
1350	}
1351
1352	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR. */
1353	SVM_READ_SELREG(LDTR, ldtr);
1354	SVM_READ_SELREG(TR, tr);
1355
1356	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1357	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1358
1359	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1360	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1361
1362	/*
1363	* System MSRs
1364	*/
1365	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1366	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1367	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1368
1369	/* Signal changes for the recompiler. */
1370	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
1371
1372	end:
1373
1374	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
1375	if (exitCode == SVM_EXIT_INTR)
1376	{
1377	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
1378	/* On the next entry we'll only sync the host context. */
1379	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
1380	}
1381	else
1382	{
1383	/* On the next entry we'll sync everything. */
1384	/** @todo we can do better than this */
1385	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
1386	}
1387
1388	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1389	return rc;
1390	}
1391
1392	/**
1393	* Enable SVM
1394	*
1395	* @returns VBox status code.
1396	* @param pVM The VM to operate on.
1397	*/
1398	HWACCMR0DECL(int) SVMR0Enable(PVM pVM)
1399	{
1400	uint64_t val;
1401
1402	Assert(pVM->hwaccm.s.svm.fSupported);
1403
1404	/* We must turn on SVM and setup the host state physical address, as those MSRs are per-cpu/core. */
1405
1406	/* Turn on SVM in the EFER MSR. */
1407	val = ASMRdMsr(MSR_K6_EFER);
1408	if (!(val & MSR_K6_EFER_SVME))
1409	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
1410
1411	/* Write the physical page address where the CPU will store the host state while executing the VM. */
1412	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pVM->hwaccm.s.svm.pHStatePhys);
1413
1414	/* Force a TLB flush on VM entry. */
1415	pVM->hwaccm.s.svm.fResumeVM = false;
1416
1417	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
1418	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
1419
1420	return VINF_SUCCESS;
1421	}
1422
1423
1424	/**
1425	* Disable SVM
1426	*
1427	* @returns VBox status code.
1428	* @param pVM The VM to operate on.
1429	*/
1430	HWACCMR0DECL(int) SVMR0Disable(PVM pVM)
1431	{
1432	/** @todo hopefully this is not very expensive. */
1433
1434	/* Turn off SVM in the EFER MSR. */
1435	uint64_t val = ASMRdMsr(MSR_K6_EFER);
1436	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
1437
1438	/* Invalidate host state physical address. */
1439	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
1440
1441	Assert(pVM->hwaccm.s.svm.fSupported);
1442	return VINF_SUCCESS;
1443	}
1444
1445
1446	static int svmInterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1447	{
1448	OP_PARAMVAL param1;
1449	RTGCPTR addr;
1450
1451	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
1452	if(VBOX_FAILURE(rc))
1453	return VERR_EM_INTERPRETER;
1454
1455	switch(param1.type)
1456	{
1457	case PARMTYPE_IMMEDIATE:
1458	case PARMTYPE_ADDRESS:
1459	if(!(param1.flags & PARAM_VAL32))
1460	return VERR_EM_INTERPRETER;
1461	addr = (RTGCPTR)param1.val.val32;
1462	break;
1463
1464	default:
1465	return VERR_EM_INTERPRETER;
1466	}
1467
1468	/** @todo is addr always a flat linear address or ds based
1469	* (in absence of segment override prefixes)????
1470	*/
1471	rc = PGMInvalidatePage(pVM, addr);
1472	if (VBOX_SUCCESS(rc))
1473	{
1474	/* Manually invalidate the page for the VM's TLB. */
1475	SVMInvlpgA(addr, uASID);
1476	return VINF_SUCCESS;
1477	}
1478	/** @todo r=bird: we shouldn't ignore returns codes like this... I'm 99% sure the error is fatal. */
1479	return VERR_EM_INTERPRETER;
1480	}
1481
1482	/**
1483	* Interprets INVLPG
1484	*
1485	* @returns VBox status code.
1486	* @retval VINF_* Scheduling instructions.
1487	* @retval VERR_EM_INTERPRETER Something we can't cope with.
1488	* @retval VERR_* Fatal errors.
1489	*
1490	* @param pVM The VM handle.
1491	* @param pRegFrame The register frame.
1492	* @param ASID Tagged TLB id for the guest
1493	*
1494	* Updates the EIP if an instruction was executed successfully.
1495	*/
1496	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
1497	{
1498	/*
1499	* Only allow 32-bit code.
1500	*/
1501	if (SELMIsSelector32Bit(pVM, pRegFrame->cs, &pRegFrame->csHid))
1502	{
1503	RTGCPTR pbCode;
1504	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pbCode);
1505	if (VBOX_SUCCESS(rc))
1506	{
1507	uint32_t cbOp;
1508	DISCPUSTATE Cpu;
1509
1510	Cpu.mode = CPUMODE_32BIT;
1511	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
1512	Assert(VBOX_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
1513	if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
1514	{
1515	Assert(cbOp == Cpu.opsize);
1516	rc = svmInterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
1517	if (VBOX_SUCCESS(rc))
1518	{
1519	pRegFrame->eip += cbOp; /* Move on to the next instruction. */
1520	}
1521	return rc;
1522	}
1523	}
1524	}
1525	return VERR_EM_INTERPRETER;
1526	}
1527

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 1

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