HWSVMR0.cpp@ 12983

Last change on this file since 12983 was 12795, checked in by vboxsync, 16 years ago
HWACCM: fixed unsigned/signed compare warning (x86.h), use const and g_.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 91.1 KB

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1	/* $Id: HWSVMR0.cpp 12795 2008-09-29 13:07:00Z vboxsync $ */
2	/** @file
3	* HWACCM SVM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_svm.h>
32	#include <VBox/pgm.h>
33	#include <VBox/pdm.h>
34	#include <VBox/err.h>
35	#include <VBox/log.h>
36	#include <VBox/selm.h>
37	#include <VBox/iom.h>
38	#include <VBox/dis.h>
39	#include <VBox/dbgf.h>
40	#include <VBox/disopcode.h>
41	#include <iprt/param.h>
42	#include <iprt/assert.h>
43	#include <iprt/asm.h>
44	#include <iprt/cpuset.h>
45	#include <iprt/mp.h>
46	#include "HWSVMR0.h"
47
48	/*******************************************************************************
49	* Internal Functions *
50	*******************************************************************************/
51	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID);
52
53	/*******************************************************************************
54	* Global Variables *
55	*******************************************************************************/
56	/* IO operation lookup arrays. */
57	static uint32_t const g_aIOSize[4] = {1, 2, 0, 4};
58
59	/**
60	* Sets up and activates AMD-V on the current CPU
61	*
62	* @returns VBox status code.
63	* @param pCpu CPU info struct
64	* @param pVM The VM to operate on.
65	* @param pvPageCpu Pointer to the global cpu page
66	* @param pPageCpuPhys Physical address of the global cpu page
67	*/
68	HWACCMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
69	{
70	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
71	AssertReturn(pVM, VERR_INVALID_PARAMETER);
72	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
73
74	/* We must turn on AMD-V and setup the host state physical address, as those MSRs are per-cpu/core. */
75
76	#ifdef LOG_ENABLED
77	SUPR0Printf("SVMR0EnableCpu cpu %d page (%x) %x\n", pCpu->idCpu, pvPageCpu, (uint32_t)pPageCpuPhys);
78	#endif
79
80	/* Turn on AMD-V in the EFER MSR. */
81	uint64_t val = ASMRdMsr(MSR_K6_EFER);
82	if (!(val & MSR_K6_EFER_SVME))
83	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
84
85	/* Write the physical page address where the CPU will store the host state while executing the VM. */
86	ASMWrMsr(MSR_K8_VM_HSAVE_PA, pPageCpuPhys);
87
88	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
89	pCpu->cTLBFlushes = 0;
90	return VINF_SUCCESS;
91	}
92
93	/**
94	* Deactivates AMD-V on the current CPU
95	*
96	* @returns VBox status code.
97	* @param pCpu CPU info struct
98	* @param pvPageCpu Pointer to the global cpu page
99	* @param pPageCpuPhys Physical address of the global cpu page
100	*/
101	HWACCMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
102	{
103	AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
104	AssertReturn(pvPageCpu, VERR_INVALID_PARAMETER);
105
106	#ifdef LOG_ENABLED
107	SUPR0Printf("SVMR0DisableCpu cpu %d\n", pCpu->idCpu);
108	#endif
109
110	/* Turn off AMD-V in the EFER MSR. */
111	uint64_t val = ASMRdMsr(MSR_K6_EFER);
112	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
113
114	/* Invalidate host state physical address. */
115	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
116	pCpu->uCurrentASID = 0;
117
118	return VINF_SUCCESS;
119	}
120
121	/**
122	* Does Ring-0 per VM AMD-V init.
123	*
124	* @returns VBox status code.
125	* @param pVM The VM to operate on.
126	*/
127	HWACCMR0DECL(int) SVMR0InitVM(PVM pVM)
128	{
129	int rc;
130
131	pVM->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
132	pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
133	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
134	pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
135
136
137	/* Allocate one page for the VM control block (VMCB). */
138	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCB, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
139	if (RT_FAILURE(rc))
140	return rc;
141
142	pVM->hwaccm.s.svm.pVMCB = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCB);
143	pVM->hwaccm.s.svm.pVMCBPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCB, 0);
144	ASMMemZeroPage(pVM->hwaccm.s.svm.pVMCB);
145
146	/* Allocate one page for the host context */
147	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjVMCBHost, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
148	if (RT_FAILURE(rc))
149	return rc;
150
151	pVM->hwaccm.s.svm.pVMCBHost = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjVMCBHost);
152	pVM->hwaccm.s.svm.pVMCBHostPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjVMCBHost, 0);
153	ASMMemZeroPage(pVM->hwaccm.s.svm.pVMCBHost);
154
155	/* Allocate 12 KB for the IO bitmap (doesn't seem to be a way to convince SVM not to use it) */
156	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjIOBitmap, 3 << PAGE_SHIFT, true /* executable R0 mapping */);
157	if (RT_FAILURE(rc))
158	return rc;
159
160	pVM->hwaccm.s.svm.pIOBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjIOBitmap);
161	pVM->hwaccm.s.svm.pIOBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjIOBitmap, 0);
162	/* Set all bits to intercept all IO accesses. */
163	ASMMemFill32(pVM->hwaccm.s.svm.pIOBitmap, PAGE_SIZE*3, 0xffffffff);
164
165	/* Allocate 8 KB for the MSR bitmap (doesn't seem to be a way to convince SVM not to use it) */
166	rc = RTR0MemObjAllocCont(&pVM->hwaccm.s.svm.pMemObjMSRBitmap, 2 << PAGE_SHIFT, true /* executable R0 mapping */);
167	if (RT_FAILURE(rc))
168	return rc;
169
170	pVM->hwaccm.s.svm.pMSRBitmap = RTR0MemObjAddress(pVM->hwaccm.s.svm.pMemObjMSRBitmap);
171	pVM->hwaccm.s.svm.pMSRBitmapPhys = RTR0MemObjGetPagePhysAddr(pVM->hwaccm.s.svm.pMemObjMSRBitmap, 0);
172	/* Set all bits to intercept all MSR accesses. */
173	ASMMemFill32(pVM->hwaccm.s.svm.pMSRBitmap, PAGE_SIZE*2, 0xffffffff);
174
175	/* Erratum 170 which requires a forced TLB flush for each world switch:
176	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
177	*
178	* All BH-G1/2 and DH-G1/2 models include a fix:
179	* Athlon X2: 0x6b 1/2
180	* 0x68 1/2
181	* Athlon 64: 0x7f 1
182	* 0x6f 2
183	* Sempron: 0x7f 1/2
184	* 0x6f 2
185	* 0x6c 2
186	* 0x7c 2
187	* Turion 64: 0x68 2
188	*
189	*/
190	uint32_t u32Dummy;
191	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
192	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
193	u32BaseFamily= (u32Version >> 8) & 0xf;
194	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
195	u32Model = ((u32Version >> 4) & 0xf);
196	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
197	u32Stepping = u32Version & 0xf;
198	if ( u32Family == 0xf
199	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
200	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
201	{
202	Log(("SVMR0InitVM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
203	pVM->hwaccm.s.svm.fAlwaysFlushTLB = true;
204	}
205
206	/* Invalidate the last cpu we were running on. */
207	pVM->hwaccm.s.svm.idLastCpu = NIL_RTCPUID;
208
209	/* we'll aways increment this the first time (host uses ASID 0) */
210	pVM->hwaccm.s.svm.uCurrentASID = 0;
211	return VINF_SUCCESS;
212	}
213
214	/**
215	* Does Ring-0 per VM AMD-V termination.
216	*
217	* @returns VBox status code.
218	* @param pVM The VM to operate on.
219	*/
220	HWACCMR0DECL(int) SVMR0TermVM(PVM pVM)
221	{
222	if (pVM->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
223	{
224	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCB, false);
225	pVM->hwaccm.s.svm.pVMCB = 0;
226	pVM->hwaccm.s.svm.pVMCBPhys = 0;
227	pVM->hwaccm.s.svm.pMemObjVMCB = NIL_RTR0MEMOBJ;
228	}
229	if (pVM->hwaccm.s.svm.pMemObjVMCBHost != NIL_RTR0MEMOBJ)
230	{
231	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjVMCBHost, false);
232	pVM->hwaccm.s.svm.pVMCBHost = 0;
233	pVM->hwaccm.s.svm.pVMCBHostPhys = 0;
234	pVM->hwaccm.s.svm.pMemObjVMCBHost = NIL_RTR0MEMOBJ;
235	}
236	if (pVM->hwaccm.s.svm.pMemObjIOBitmap != NIL_RTR0MEMOBJ)
237	{
238	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjIOBitmap, false);
239	pVM->hwaccm.s.svm.pIOBitmap = 0;
240	pVM->hwaccm.s.svm.pIOBitmapPhys = 0;
241	pVM->hwaccm.s.svm.pMemObjIOBitmap = NIL_RTR0MEMOBJ;
242	}
243	if (pVM->hwaccm.s.svm.pMemObjMSRBitmap != NIL_RTR0MEMOBJ)
244	{
245	RTR0MemObjFree(pVM->hwaccm.s.svm.pMemObjMSRBitmap, false);
246	pVM->hwaccm.s.svm.pMSRBitmap = 0;
247	pVM->hwaccm.s.svm.pMSRBitmapPhys = 0;
248	pVM->hwaccm.s.svm.pMemObjMSRBitmap = NIL_RTR0MEMOBJ;
249	}
250	return VINF_SUCCESS;
251	}
252
253	/**
254	* Sets up AMD-V for the specified VM
255	*
256	* @returns VBox status code.
257	* @param pVM The VM to operate on.
258	*/
259	HWACCMR0DECL(int) SVMR0SetupVM(PVM pVM)
260	{
261	int rc = VINF_SUCCESS;
262	SVM_VMCB *pVMCB;
263
264	AssertReturn(pVM, VERR_INVALID_PARAMETER);
265
266	Assert(pVM->hwaccm.s.svm.fSupported);
267
268	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
269	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
270
271	/* Program the control fields. Most of them never have to be changed again. */
272	/* CR0/3/4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
273	/* Note: CR0 & CR4 can be safely read when guest and shadow copies are identical. */
274	if (!pVM->hwaccm.s.fNestedPaging)
275	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
276	else
277	pVMCB->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
278
279	/*
280	* CR0/3/4 writes must be intercepted for obvious reasons.
281	*/
282	if (!pVM->hwaccm.s.fNestedPaging)
283	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(3) \| RT_BIT(4);
284	else
285	pVMCB->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4) \| RT_BIT(8);
286
287	/* Intercept all DRx reads and writes by default. Changed later on. */
288	pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
289	pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
290
291	/* Currently we don't care about DRx reads or writes. DRx registers are trashed.
292	* All breakpoints are automatically cleared when the VM exits.
293	*/
294
295	pVMCB->ctrl.u32InterceptException = HWACCM_SVM_TRAP_MASK;
296	#ifndef DEBUG
297	if (pVM->hwaccm.s.fNestedPaging)
298	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_PF); /* no longer need to intercept #PF. */
299	#endif
300
301	pVMCB->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR
302	\| SVM_CTRL1_INTERCEPT_VINTR
303	\| SVM_CTRL1_INTERCEPT_NMI
304	\| SVM_CTRL1_INTERCEPT_SMI
305	\| SVM_CTRL1_INTERCEPT_INIT
306	\| SVM_CTRL1_INTERCEPT_RDPMC
307	\| SVM_CTRL1_INTERCEPT_CPUID
308	\| SVM_CTRL1_INTERCEPT_RSM
309	\| SVM_CTRL1_INTERCEPT_HLT
310	\| SVM_CTRL1_INTERCEPT_INOUT_BITMAP
311	\| SVM_CTRL1_INTERCEPT_MSR_SHADOW
312	\| SVM_CTRL1_INTERCEPT_INVLPG
313	\| SVM_CTRL1_INTERCEPT_INVLPGA /* AMD only */
314	\| SVM_CTRL1_INTERCEPT_TASK_SWITCH
315	\| SVM_CTRL1_INTERCEPT_SHUTDOWN /* fatal */
316	\| SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Legacy FPU FERR handling. */
317	;
318	/* With nested paging we don't care about invlpg anymore. */
319	if (pVM->hwaccm.s.fNestedPaging)
320	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_INVLPG;
321
322	pVMCB->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* required */
323	\| SVM_CTRL2_INTERCEPT_VMMCALL
324	\| SVM_CTRL2_INTERCEPT_VMLOAD
325	\| SVM_CTRL2_INTERCEPT_VMSAVE
326	\| SVM_CTRL2_INTERCEPT_STGI
327	\| SVM_CTRL2_INTERCEPT_CLGI
328	\| SVM_CTRL2_INTERCEPT_SKINIT
329	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
330	\| SVM_CTRL2_INTERCEPT_WBINVD
331	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND; /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
332	;
333	Log(("pVMCB->ctrl.u32InterceptException = %x\n", pVMCB->ctrl.u32InterceptException));
334	Log(("pVMCB->ctrl.u32InterceptCtrl1 = %x\n", pVMCB->ctrl.u32InterceptCtrl1));
335	Log(("pVMCB->ctrl.u32InterceptCtrl2 = %x\n", pVMCB->ctrl.u32InterceptCtrl2));
336
337	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
338	pVMCB->ctrl.IntCtrl.n.u1VIrqMasking = 1;
339	/* Ignore the priority in the TPR; just deliver it when we tell it to. */
340	pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
341
342	/* Set IO and MSR bitmap addresses. */
343	pVMCB->ctrl.u64IOPMPhysAddr = pVM->hwaccm.s.svm.pIOBitmapPhys;
344	pVMCB->ctrl.u64MSRPMPhysAddr = pVM->hwaccm.s.svm.pMSRBitmapPhys;
345
346	/* No LBR virtualization. */
347	pVMCB->ctrl.u64LBRVirt = 0;
348
349	/** The ASID must start at 1; the host uses 0. */
350	pVMCB->ctrl.TLBCtrl.n.u32ASID = 1;
351
352	/** Setup the PAT msr (nested paging only) */
353	pVMCB->guest.u64GPAT = 0x0007040600070406ULL;
354	return rc;
355	}
356
357
358	/**
359	* Injects an event (trap or external interrupt)
360	*
361	* @param pVM The VM to operate on.
362	* @param pVMCB SVM control block
363	* @param pCtx CPU Context
364	* @param pIntInfo SVM interrupt info
365	*/
366	inline void SVMR0InjectEvent(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx, SVM_EVENT* pEvent)
367	{
368	#ifdef VBOX_STRICT
369	if (pEvent->n.u8Vector == 0xE)
370	Log(("SVM: Inject int %d at %VGv error code=%02x CR2=%VGv intInfo=%08x\n", pEvent->n.u8Vector, pCtx->rip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
371	else
372	if (pEvent->n.u8Vector < 0x20)
373	Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->rip, pEvent->n.u32ErrorCode));
374	else
375	{
376	Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->rip));
377	Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
378	Assert(pCtx->eflags.u32 & X86_EFL_IF);
379	}
380	#endif
381
382	/* Set event injection state. */
383	pVMCB->ctrl.EventInject.au64[0] = pEvent->au64[0];
384	}
385
386
387	/**
388	* Checks for pending guest interrupts and injects them
389	*
390	* @returns VBox status code.
391	* @param pVM The VM to operate on.
392	* @param pVMCB SVM control block
393	* @param pCtx CPU Context
394	*/
395	static int SVMR0CheckPendingInterrupt(PVM pVM, SVM_VMCB pVMCB, CPUMCTX pCtx)
396	{
397	int rc;
398
399	/* Dispatch any pending interrupts. (injected before, but a VM exit occurred prematurely) */
400	if (pVM->hwaccm.s.Event.fPending)
401	{
402	SVM_EVENT Event;
403
404	Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip));
405	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
406	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
407	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
408
409	pVM->hwaccm.s.Event.fPending = false;
410	return VINF_SUCCESS;
411	}
412
413	/* When external interrupts are pending, we should exit the VM when IF is set. */
414	if ( !TRPMHasTrap(pVM)
415	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
416	{
417	if ( !(pCtx->eflags.u32 & X86_EFL_IF)
418	\|\| VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
419	{
420	if (!pVMCB->ctrl.IntCtrl.n.u1VIrqValid)
421	{
422	if (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
423	LogFlow(("Enable irq window exit!\n"));
424	else
425	Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS -> irq window exit\n", pCtx->rip));
426
427	/** @todo use virtual interrupt method to inject a pending irq; dispatched as soon as guest.IF is set. */
428	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_VINTR;
429	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 1;
430	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0; /* don't care */
431	}
432	}
433	else
434	{
435	uint8_t u8Interrupt;
436
437	rc = PDMGetInterrupt(pVM, &u8Interrupt);
438	Log(("Dispatch interrupt: u8Interrupt=%x (%d) rc=%Vrc\n", u8Interrupt, u8Interrupt, rc));
439	if (VBOX_SUCCESS(rc))
440	{
441	rc = TRPMAssertTrap(pVM, u8Interrupt, TRPM_HARDWARE_INT);
442	AssertRC(rc);
443	}
444	else
445	{
446	/* Can only happen in rare cases where a pending interrupt is cleared behind our back */
447	Assert(!VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)));
448	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchGuestIrq);
449	/* Just continue */
450	}
451	}
452	}
453
454	#ifdef VBOX_STRICT
455	if (TRPMHasTrap(pVM))
456	{
457	uint8_t u8Vector;
458	rc = TRPMQueryTrapAll(pVM, &u8Vector, 0, 0, 0);
459	AssertRC(rc);
460	}
461	#endif
462
463	if ( pCtx->eflags.u32 & X86_EFL_IF
464	&& (!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
465	&& TRPMHasTrap(pVM)
466	)
467	{
468	uint8_t u8Vector;
469	int rc;
470	TRPMEVENT enmType;
471	SVM_EVENT Event;
472	RTGCUINT u32ErrorCode;
473
474	Event.au64[0] = 0;
475
476	/* If a new event is pending, then dispatch it now. */
477	rc = TRPMQueryTrapAll(pVM, &u8Vector, &enmType, &u32ErrorCode, 0);
478	AssertRC(rc);
479	Assert(pCtx->eflags.Bits.u1IF == 1 \|\| enmType == TRPM_TRAP);
480	Assert(enmType != TRPM_SOFTWARE_INT);
481
482	/* Clear the pending trap. */
483	rc = TRPMResetTrap(pVM);
484	AssertRC(rc);
485
486	Event.n.u8Vector = u8Vector;
487	Event.n.u1Valid = 1;
488	Event.n.u32ErrorCode = u32ErrorCode;
489
490	if (enmType == TRPM_TRAP)
491	{
492	switch (u8Vector) {
493	case 8:
494	case 10:
495	case 11:
496	case 12:
497	case 13:
498	case 14:
499	case 17:
500	/* Valid error codes. */
501	Event.n.u1ErrorCodeValid = 1;
502	break;
503	default:
504	break;
505	}
506	if (u8Vector == X86_XCPT_NMI)
507	Event.n.u3Type = SVM_EVENT_NMI;
508	else
509	Event.n.u3Type = SVM_EVENT_EXCEPTION;
510	}
511	else
512	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
513
514	STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntInject);
515	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
516	} /* if (interrupts can be dispatched) */
517
518	return VINF_SUCCESS;
519	}
520
521	/**
522	* Save the host state
523	*
524	* @returns VBox status code.
525	* @param pVM The VM to operate on.
526	*/
527	HWACCMR0DECL(int) SVMR0SaveHostState(PVM pVM)
528	{
529	/* Nothing to do here. */
530	return VINF_SUCCESS;
531	}
532
533	/**
534	* Loads the guest state
535	*
536	* NOTE: Don't do anything here that can cause a jump back to ring 3!!!!!
537	*
538	* @returns VBox status code.
539	* @param pVM The VM to operate on.
540	* @param pCtx Guest context
541	*/
542	HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
543	{
544	RTGCUINTPTR val;
545	SVM_VMCB *pVMCB;
546
547	if (pVM == NULL)
548	return VERR_INVALID_PARAMETER;
549
550	/* Setup AMD SVM. */
551	Assert(pVM->hwaccm.s.svm.fSupported);
552
553	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
554	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
555
556	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
557	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_SEGMENT_REGS)
558	{
559	SVM_WRITE_SELREG(CS, cs);
560	SVM_WRITE_SELREG(SS, ss);
561	SVM_WRITE_SELREG(DS, ds);
562	SVM_WRITE_SELREG(ES, es);
563	SVM_WRITE_SELREG(FS, fs);
564	SVM_WRITE_SELREG(GS, gs);
565	}
566
567	/* Guest CPU context: LDTR. */
568	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_LDTR)
569	{
570	SVM_WRITE_SELREG(LDTR, ldtr);
571	}
572
573	/* Guest CPU context: TR. */
574	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_TR)
575	{
576	SVM_WRITE_SELREG(TR, tr);
577	}
578
579	/* Guest CPU context: GDTR. */
580	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_GDTR)
581	{
582	pVMCB->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
583	pVMCB->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
584	}
585
586	/* Guest CPU context: IDTR. */
587	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_IDTR)
588	{
589	pVMCB->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
590	pVMCB->guest.IDTR.u64Base = pCtx->idtr.pIdt;
591	}
592
593	/*
594	* Sysenter MSRs (unconditional)
595	*/
596	pVMCB->guest.u64SysEnterCS = pCtx->SysEnter.cs;
597	pVMCB->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
598	pVMCB->guest.u64SysEnterESP = pCtx->SysEnter.esp;
599
600	/* Control registers */
601	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR0)
602	{
603	val = pCtx->cr0;
604	if (!CPUMIsGuestFPUStateActive(pVM))
605	{
606	/* Always use #NM exceptions to load the FPU/XMM state on demand. */
607	val \|= X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP;
608	}
609	else
610	{
611	/** @todo check if we support the old style mess correctly. */
612	if (!(val & X86_CR0_NE))
613	{
614	Log(("Forcing X86_CR0_NE!!!\n"));
615
616	/* Also catch floating point exceptions as we need to report them to the guest in a different way. */
617	if (!pVM->hwaccm.s.fFPUOldStyleOverride)
618	{
619	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_MF);
620	pVM->hwaccm.s.fFPUOldStyleOverride = true;
621	}
622	}
623	val \|= X86_CR0_NE; /* always turn on the native mechanism to report FPU errors (old style uses interrupts) */
624	}
625	/* Always enable caching. */
626	val &= ~(X86_CR0_CD\|X86_CR0_NW);
627
628	/* Note: WP is not relevant in nested paging mode as we catch accesses on the (guest) physical level. */
629	/* Note: In nested paging mode the guest is allowed to run with paging disabled; the guest physical to host physical translation will remain active. */
630	if (!pVM->hwaccm.s.fNestedPaging)
631	{
632	val \|= X86_CR0_PG; /* Paging is always enabled; even when the guest is running in real mode or PE without paging. */
633	val \|= X86_CR0_WP; /* Must set this as we rely on protect various pages and supervisor writes must be caught. */
634	}
635	pVMCB->guest.u64CR0 = val;
636	}
637	/* CR2 as well */
638	pVMCB->guest.u64CR2 = pCtx->cr2;
639
640	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR3)
641	{
642	/* Save our shadow CR3 register. */
643	if (pVM->hwaccm.s.fNestedPaging)
644	{
645	pVMCB->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVM, PGMGetHostMode(pVM));
646	Assert(pVMCB->ctrl.u64NestedPagingCR3);
647	pVMCB->guest.u64CR3 = pCtx->cr3;
648	}
649	else
650	{
651	pVMCB->guest.u64CR3 = PGMGetHyperCR3(pVM);
652	Assert(pVMCB->guest.u64CR3);
653	}
654	}
655
656	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_CR4)
657	{
658	val = pCtx->cr4;
659	if (!pVM->hwaccm.s.fNestedPaging)
660	{
661	switch(pVM->hwaccm.s.enmShadowMode)
662	{
663	case PGMMODE_REAL:
664	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
665	AssertFailed();
666	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
667
668	case PGMMODE_32_BIT: /* 32-bit paging. */
669	break;
670
671	case PGMMODE_PAE: /* PAE paging. */
672	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
673	/** @todo use normal 32 bits paging */
674	val \|= X86_CR4_PAE;
675	break;
676
677	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
678	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
679	#ifdef VBOX_ENABLE_64_BITS_GUESTS
680	break;
681	#else
682	AssertFailed();
683	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
684	#endif
685
686	default: /* shut up gcc */
687	AssertFailed();
688	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
689	}
690	}
691	pVMCB->guest.u64CR4 = val;
692	}
693
694	/* Debug registers. */
695	if (pVM->hwaccm.s.fContextUseFlags & HWACCM_CHANGED_GUEST_DEBUG)
696	{
697	pCtx->dr[6] \|= X86_DR6_INIT_VAL; /* set all reserved bits to 1. */
698	pCtx->dr[6] &= ~RT_BIT(12); /* must be zero. */
699
700	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
701	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
702	pCtx->dr[7] \|= 0x400; /* must be one */
703
704	pVMCB->guest.u64DR7 = pCtx->dr[7];
705	pVMCB->guest.u64DR6 = pCtx->dr[6];
706
707	/* Sync the debug state now if any breakpoint is armed. */
708	if ( (pCtx->dr[7] & (X86_DR7_ENABLED_MASK\|X86_DR7_GD))
709	&& !CPUMIsGuestDebugStateActive(pVM)
710	&& !DBGFIsStepping(pVM))
711	{
712	STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxArmed);
713
714	/* Disable drx move intercepts. */
715	pVMCB->ctrl.u16InterceptRdDRx = 0;
716	pVMCB->ctrl.u16InterceptWrDRx = 0;
717
718	/* Save the host and load the guest debug state. */
719	int rc = CPUMR0LoadGuestDebugState(pVM, pCtx, false /* exclude DR6 */);
720	AssertRC(rc);
721	}
722	}
723
724	/* EIP, ESP and EFLAGS */
725	pVMCB->guest.u64RIP = pCtx->rip;
726	pVMCB->guest.u64RSP = pCtx->rsp;
727	pVMCB->guest.u64RFlags = pCtx->eflags.u32;
728
729	/* Set CPL */
730	pVMCB->guest.u8CPL = pCtx->csHid.Attr.n.u2Dpl;
731
732	/* RAX/EAX too, as VMRUN uses RAX as an implicit parameter. */
733	pVMCB->guest.u64RAX = pCtx->rax;
734
735	/* vmrun will fail without MSR_K6_EFER_SVME. */
736	pVMCB->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
737
738	/* 64 bits guest mode? */
739	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
740	{
741	#if !defined(VBOX_WITH_64_BITS_GUESTS) \|\| HC_ARCH_BITS != 64
742	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
743	#else
744	pVM->hwaccm.s.svm.pfnVMRun = SVMVMRun64;
745	#endif
746	/* Unconditionally update these as wrmsr might have changed them. (HWACCM_CHANGED_GUEST_SEGMENT_REGS will not be set) */
747	pVMCB->guest.FS.u64Base = pCtx->fsHid.u64Base;
748	pVMCB->guest.GS.u64Base = pCtx->gsHid.u64Base;
749	}
750	else
751	{
752	/* Filter out the MSR_K6_LME bit or else AMD-V expects amd64 shadow paging. */
753	pVMCB->guest.u64EFER &= ~MSR_K6_EFER_LME;
754
755	pVM->hwaccm.s.svm.pfnVMRun = SVMVMRun;
756	}
757
758	/* TSC offset. */
759	if (TMCpuTickCanUseRealTSC(pVM, &pVMCB->ctrl.u64TSCOffset))
760	{
761	pVMCB->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
762	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCOffset);
763	}
764	else
765	{
766	pVMCB->ctrl.u32InterceptCtrl1 \|= SVM_CTRL1_INTERCEPT_RDTSC;
767	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTSCIntercept);
768	}
769
770	/* Sync the various msrs for 64 bits mode. */
771	pVMCB->guest.u64STAR = pCtx->msrSTAR; /* legacy syscall eip, cs & ss */
772	pVMCB->guest.u64LSTAR = pCtx->msrLSTAR; /* 64 bits mode syscall rip */
773	pVMCB->guest.u64CSTAR = pCtx->msrCSTAR; /* compatibility mode syscall rip */
774	pVMCB->guest.u64SFMASK = pCtx->msrSFMASK; /* syscall flag mask */
775	pVMCB->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE; /* swapgs exchange value */
776
777	#ifdef DEBUG
778	/* Intercept X86_XCPT_DB if stepping is enabled */
779	if (DBGFIsStepping(pVM))
780	pVMCB->ctrl.u32InterceptException \|= RT_BIT(X86_XCPT_DB);
781	else
782	pVMCB->ctrl.u32InterceptException &= ~RT_BIT(X86_XCPT_DB);
783	#endif
784
785	/* Done. */
786	pVM->hwaccm.s.fContextUseFlags &= ~HWACCM_CHANGED_ALL_GUEST;
787
788	return VINF_SUCCESS;
789	}
790
791
792	/**
793	* Runs guest code in an SVM VM.
794	*
795	* @todo This can be much more efficient, when we only sync that which has actually changed. (this is the first attempt only)
796	*
797	* @returns VBox status code.
798	* @param pVM The VM to operate on.
799	* @param pCtx Guest context
800	*/
801	HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
802	{
803	int rc = VINF_SUCCESS;
804	uint64_t exitCode = (uint64_t)SVM_EXIT_INVALID;
805	SVM_VMCB *pVMCB;
806	bool fSyncTPR = false;
807	unsigned cResume = 0;
808	uint8_t u8LastVTPR;
809	PHWACCM_CPUINFO pCpu = 0;
810	#ifdef VBOX_STRICT
811	RTCPUID idCpuCheck;
812	#endif
813
814	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatEntry, x);
815
816	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
817	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
818
819	/* We can jump to this point to resume execution after determining that a VM-exit is innocent.
820	*/
821	ResumeExecution:
822	/* Safety precaution; looping for too long here can have a very bad effect on the host */
823	if (++cResume > HWACCM_MAX_RESUME_LOOPS)
824	{
825	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitMaxResume);
826	rc = VINF_EM_RAW_INTERRUPT;
827	goto end;
828	}
829
830	/* Check for irq inhibition due to instruction fusing (sti, mov ss). */
831	if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
832	{
833	Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
834	if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
835	{
836	/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
837	* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
838	* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
839	* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
840	*/
841	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
842	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
843	pVMCB->ctrl.u64IntShadow = 0;
844	}
845	}
846	else
847	{
848	/* Irq inhibition is no longer active; clear the corresponding SVM state. */
849	pVMCB->ctrl.u64IntShadow = 0;
850	}
851
852	/* Check for pending actions that force us to go back to ring 3. */
853	#ifdef DEBUG
854	/* Intercept X86_XCPT_DB if stepping is enabled */
855	if (!DBGFIsStepping(pVM))
856	#endif
857	{
858	if (VM_FF_ISPENDING(pVM, VM_FF_TO_R3 \| VM_FF_TIMER))
859	{
860	VM_FF_CLEAR(pVM, VM_FF_TO_R3);
861	STAM_COUNTER_INC(&pVM->hwaccm.s.StatSwitchToR3);
862	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
863	rc = VINF_EM_RAW_TO_R3;
864	goto end;
865	}
866	}
867
868	/* Pending request packets might contain actions that need immediate attention, such as pending hardware interrupts. */
869	if (VM_FF_ISPENDING(pVM, VM_FF_REQUEST))
870	{
871	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
872	rc = VINF_EM_PENDING_REQUEST;
873	goto end;
874	}
875
876	/* When external interrupts are pending, we should exit the VM when IF is set. */
877	/* Note! After VM_FF_INHIBIT_INTERRUPTS check!!! */
878	rc = SVMR0CheckPendingInterrupt(pVM, pVMCB, pCtx);
879	if (VBOX_FAILURE(rc))
880	{
881	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
882	goto end;
883	}
884
885	/* TPR caching using CR8 is only available in 64 bits mode */
886	/* Note the 32 bits exception for AMD (X86_CPUID_AMD_FEATURE_ECX_CR8L), but that appears missing in Intel CPUs */
887	/* Note: we can't do this in LoadGuestState as PDMApicGetTPR can jump back to ring 3 (lock)!!!!!!!! */
888	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
889	{
890	bool fPending;
891
892	/* TPR caching in CR8 */
893	int rc = PDMApicGetTPR(pVM, &u8LastVTPR, &fPending);
894	AssertRC(rc);
895	pVMCB->ctrl.IntCtrl.n.u8VTPR = u8LastVTPR;
896
897	if (fPending)
898	{
899	/* A TPR change could activate a pending interrupt, so catch cr8 writes. */
900	pVMCB->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
901	}
902	else
903	/* No interrupts are pending, so we don't need to be explicitely notified.
904	* There are enough world switches for detecting pending interrupts.
905	*/
906	pVMCB->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
907
908	fSyncTPR = !fPending;
909	}
910
911	/* All done! Let's start VM execution. */
912	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatInGC, x);
913
914	/* Enable nested paging if necessary (disabled each time after #VMEXIT). */
915	pVMCB->ctrl.NestedPaging.n.u1NestedPaging = pVM->hwaccm.s.fNestedPaging;
916
917	#ifdef LOG_ENABLED
918	pCpu = HWACCMR0GetCurrentCpu();
919	if ( pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu
920	\|\| pVM->hwaccm.s.svm.cTLBFlushes != pCpu->cTLBFlushes)
921	{
922	if (pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu)
923	Log(("Force TLB flush due to rescheduling to a different cpu (%d vs %d)\n", pVM->hwaccm.s.svm.idLastCpu, pCpu->idCpu));
924	else
925	Log(("Force TLB flush due to changed TLB flush count (%x vs %x)\n", pVM->hwaccm.s.svm.cTLBFlushes, pCpu->cTLBFlushes));
926	}
927	if (pCpu->fFlushTLB)
928	Log(("Force TLB flush: first time cpu %d is used -> flush\n", pCpu->idCpu));
929	#endif
930
931	/*
932	* NOTE: DO NOT DO ANYTHING AFTER THIS POINT THAT MIGHT JUMP BACK TO RING 3!
933	* (until the actual world switch)
934	*/
935
936	#ifdef VBOX_STRICT
937	idCpuCheck = RTMpCpuId();
938	#endif
939
940	/* Load the guest state; must be here as it sets up the shadow cr0 for lazy fpu syncing! */
941	rc = SVMR0LoadGuestState(pVM, pCtx);
942	if (rc != VINF_SUCCESS)
943	{
944	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatEntry, x);
945	goto end;
946	}
947
948	pCpu = HWACCMR0GetCurrentCpu();
949	/* Force a TLB flush for the first world switch if the current cpu differs from the one we ran on last. */
950	/* Note that this can happen both for start and resume due to long jumps back to ring 3. */
951	if ( pVM->hwaccm.s.svm.idLastCpu != pCpu->idCpu
952	/* if the tlb flush count has changed, another VM has flushed the TLB of this cpu, so we can't use our current ASID anymore. */
953	\|\| pVM->hwaccm.s.svm.cTLBFlushes != pCpu->cTLBFlushes)
954	{
955	/* Force a TLB flush on VM entry. */
956	pVM->hwaccm.s.svm.fForceTLBFlush = true;
957	}
958	else
959	Assert(!pCpu->fFlushTLB \|\| pVM->hwaccm.s.svm.fAlwaysFlushTLB);
960
961	pVM->hwaccm.s.svm.idLastCpu = pCpu->idCpu;
962
963	/* Make sure we flush the TLB when required. Switch ASID to achieve the same thing, but without actually flushing the whole TLB (which is expensive). */
964	if ( pVM->hwaccm.s.svm.fForceTLBFlush
965	&& !pVM->hwaccm.s.svm.fAlwaysFlushTLB)
966	{
967	if ( ++pCpu->uCurrentASID >= pVM->hwaccm.s.svm.u32MaxASID
968	\|\| pCpu->fFlushTLB)
969	{
970	pCpu->fFlushTLB = false;
971	pCpu->uCurrentASID = 1; /* start at 1; host uses 0 */
972	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = 1; /* wrap around; flush TLB */
973	pCpu->cTLBFlushes++;
974	}
975	else
976	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushASID);
977
978	pVM->hwaccm.s.svm.cTLBFlushes = pCpu->cTLBFlushes;
979	pVM->hwaccm.s.svm.uCurrentASID = pCpu->uCurrentASID;
980	}
981	else
982	{
983	Assert(!pCpu->fFlushTLB \|\| pVM->hwaccm.s.svm.fAlwaysFlushTLB);
984
985	/* We never increase uCurrentASID in the fAlwaysFlushTLB (erratum 170) case. */
986	if (!pCpu->uCurrentASID \|\| !pVM->hwaccm.s.svm.uCurrentASID)
987	pVM->hwaccm.s.svm.uCurrentASID = pCpu->uCurrentASID = 1;
988
989	Assert(!pVM->hwaccm.s.svm.fAlwaysFlushTLB \|\| pVM->hwaccm.s.svm.fForceTLBFlush);
990	pVMCB->ctrl.TLBCtrl.n.u1TLBFlush = pVM->hwaccm.s.svm.fForceTLBFlush;
991	}
992	AssertMsg(pVM->hwaccm.s.svm.cTLBFlushes == pCpu->cTLBFlushes, ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVM->hwaccm.s.svm.cTLBFlushes, pCpu->cTLBFlushes));
993	AssertMsg(pCpu->uCurrentASID >= 1 && pCpu->uCurrentASID < pVM->hwaccm.s.svm.u32MaxASID, ("cpu%d uCurrentASID = %x\n", pCpu->idCpu, pCpu->uCurrentASID));
994	AssertMsg(pVM->hwaccm.s.svm.uCurrentASID >= 1 && pVM->hwaccm.s.svm.uCurrentASID < pVM->hwaccm.s.svm.u32MaxASID, ("cpu%d VM uCurrentASID = %x\n", pCpu->idCpu, pVM->hwaccm.s.svm.uCurrentASID));
995	pVMCB->ctrl.TLBCtrl.n.u32ASID = pVM->hwaccm.s.svm.uCurrentASID;
996
997	#ifdef VBOX_WITH_STATISTICS
998	if (pVMCB->ctrl.TLBCtrl.n.u1TLBFlush)
999	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBWorldSwitch);
1000	else
1001	STAM_COUNTER_INC(&pVM->hwaccm.s.StatNoFlushTLBWorldSwitch);
1002	#endif
1003
1004	/* In case we execute a goto ResumeExecution later on. */
1005	pVM->hwaccm.s.svm.fResumeVM = true;
1006	pVM->hwaccm.s.svm.fForceTLBFlush = pVM->hwaccm.s.svm.fAlwaysFlushTLB;
1007
1008	Assert(sizeof(pVM->hwaccm.s.svm.pVMCBPhys) == 8);
1009	Assert(pVMCB->ctrl.u32InterceptCtrl2 == ( SVM_CTRL2_INTERCEPT_VMRUN /* required */
1010	\| SVM_CTRL2_INTERCEPT_VMMCALL
1011	\| SVM_CTRL2_INTERCEPT_VMLOAD
1012	\| SVM_CTRL2_INTERCEPT_VMSAVE
1013	\| SVM_CTRL2_INTERCEPT_STGI
1014	\| SVM_CTRL2_INTERCEPT_CLGI
1015	\| SVM_CTRL2_INTERCEPT_SKINIT
1016	\| SVM_CTRL2_INTERCEPT_RDTSCP /* AMD only; we don't support this one */
1017	\| SVM_CTRL2_INTERCEPT_WBINVD
1018	\| SVM_CTRL2_INTERCEPT_MWAIT_UNCOND /* don't execute mwait or else we'll idle inside the guest (host thinks the cpu load is high) */
1019	));
1020	Assert(pVMCB->ctrl.IntCtrl.n.u1VIrqMasking);
1021	Assert(pVMCB->ctrl.u64IOPMPhysAddr == pVM->hwaccm.s.svm.pIOBitmapPhys);
1022	Assert(pVMCB->ctrl.u64MSRPMPhysAddr == pVM->hwaccm.s.svm.pMSRBitmapPhys);
1023	Assert(pVMCB->ctrl.u64LBRVirt == 0);
1024
1025	#ifdef VBOX_STRICT
1026	Assert(idCpuCheck == RTMpCpuId());
1027	#endif
1028	TMNotifyStartOfExecution(pVM);
1029	pVM->hwaccm.s.svm.pfnVMRun(pVM->hwaccm.s.svm.pVMCBHostPhys, pVM->hwaccm.s.svm.pVMCBPhys, pCtx);
1030	TMNotifyEndOfExecution(pVM);
1031	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatInGC, x);
1032
1033	/*
1034	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1035	* IMPORTANT: WE CAN'T DO ANY LOGGING OR OPERATIONS THAT CAN DO A LONGJMP BACK TO RING 3 BEFORE WE'VE SYNCED BACK (MOST OF) THE GUEST STATE
1036	* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
1037	*/
1038
1039	STAM_PROFILE_ADV_START(&pVM->hwaccm.s.StatExit, x);
1040
1041	/* Reason for the VM exit */
1042	exitCode = pVMCB->ctrl.u64ExitCode;
1043
1044	if (exitCode == (uint64_t)SVM_EXIT_INVALID) /* Invalid guest state. */
1045	{
1046	HWACCMDumpRegs(pVM, pCtx);
1047	#ifdef DEBUG
1048	Log(("ctrl.u16InterceptRdCRx %x\n", pVMCB->ctrl.u16InterceptRdCRx));
1049	Log(("ctrl.u16InterceptWrCRx %x\n", pVMCB->ctrl.u16InterceptWrCRx));
1050	Log(("ctrl.u16InterceptRdDRx %x\n", pVMCB->ctrl.u16InterceptRdDRx));
1051	Log(("ctrl.u16InterceptWrDRx %x\n", pVMCB->ctrl.u16InterceptWrDRx));
1052	Log(("ctrl.u32InterceptException %x\n", pVMCB->ctrl.u32InterceptException));
1053	Log(("ctrl.u32InterceptCtrl1 %x\n", pVMCB->ctrl.u32InterceptCtrl1));
1054	Log(("ctrl.u32InterceptCtrl2 %x\n", pVMCB->ctrl.u32InterceptCtrl2));
1055	Log(("ctrl.u64IOPMPhysAddr %VX64\n", pVMCB->ctrl.u64IOPMPhysAddr));
1056	Log(("ctrl.u64MSRPMPhysAddr %VX64\n", pVMCB->ctrl.u64MSRPMPhysAddr));
1057	Log(("ctrl.u64TSCOffset %VX64\n", pVMCB->ctrl.u64TSCOffset));
1058
1059	Log(("ctrl.TLBCtrl.u32ASID %x\n", pVMCB->ctrl.TLBCtrl.n.u32ASID));
1060	Log(("ctrl.TLBCtrl.u1TLBFlush %x\n", pVMCB->ctrl.TLBCtrl.n.u1TLBFlush));
1061	Log(("ctrl.TLBCtrl.u7Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u7Reserved));
1062	Log(("ctrl.TLBCtrl.u24Reserved %x\n", pVMCB->ctrl.TLBCtrl.n.u24Reserved));
1063
1064	Log(("ctrl.IntCtrl.u8VTPR %x\n", pVMCB->ctrl.IntCtrl.n.u8VTPR));
1065	Log(("ctrl.IntCtrl.u1VIrqValid %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqValid));
1066	Log(("ctrl.IntCtrl.u7Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved));
1067	Log(("ctrl.IntCtrl.u4VIrqPriority %x\n", pVMCB->ctrl.IntCtrl.n.u4VIrqPriority));
1068	Log(("ctrl.IntCtrl.u1IgnoreTPR %x\n", pVMCB->ctrl.IntCtrl.n.u1IgnoreTPR));
1069	Log(("ctrl.IntCtrl.u3Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u3Reserved));
1070	Log(("ctrl.IntCtrl.u1VIrqMasking %x\n", pVMCB->ctrl.IntCtrl.n.u1VIrqMasking));
1071	Log(("ctrl.IntCtrl.u7Reserved2 %x\n", pVMCB->ctrl.IntCtrl.n.u7Reserved2));
1072	Log(("ctrl.IntCtrl.u8VIrqVector %x\n", pVMCB->ctrl.IntCtrl.n.u8VIrqVector));
1073	Log(("ctrl.IntCtrl.u24Reserved %x\n", pVMCB->ctrl.IntCtrl.n.u24Reserved));
1074
1075	Log(("ctrl.u64IntShadow %VX64\n", pVMCB->ctrl.u64IntShadow));
1076	Log(("ctrl.u64ExitCode %VX64\n", pVMCB->ctrl.u64ExitCode));
1077	Log(("ctrl.u64ExitInfo1 %VX64\n", pVMCB->ctrl.u64ExitInfo1));
1078	Log(("ctrl.u64ExitInfo2 %VX64\n", pVMCB->ctrl.u64ExitInfo2));
1079	Log(("ctrl.ExitIntInfo.u8Vector %x\n", pVMCB->ctrl.ExitIntInfo.n.u8Vector));
1080	Log(("ctrl.ExitIntInfo.u3Type %x\n", pVMCB->ctrl.ExitIntInfo.n.u3Type));
1081	Log(("ctrl.ExitIntInfo.u1ErrorCodeValid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
1082	Log(("ctrl.ExitIntInfo.u19Reserved %x\n", pVMCB->ctrl.ExitIntInfo.n.u19Reserved));
1083	Log(("ctrl.ExitIntInfo.u1Valid %x\n", pVMCB->ctrl.ExitIntInfo.n.u1Valid));
1084	Log(("ctrl.ExitIntInfo.u32ErrorCode %x\n", pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode));
1085	Log(("ctrl.NestedPaging %VX64\n", pVMCB->ctrl.NestedPaging.au64));
1086	Log(("ctrl.EventInject.u8Vector %x\n", pVMCB->ctrl.EventInject.n.u8Vector));
1087	Log(("ctrl.EventInject.u3Type %x\n", pVMCB->ctrl.EventInject.n.u3Type));
1088	Log(("ctrl.EventInject.u1ErrorCodeValid %x\n", pVMCB->ctrl.EventInject.n.u1ErrorCodeValid));
1089	Log(("ctrl.EventInject.u19Reserved %x\n", pVMCB->ctrl.EventInject.n.u19Reserved));
1090	Log(("ctrl.EventInject.u1Valid %x\n", pVMCB->ctrl.EventInject.n.u1Valid));
1091	Log(("ctrl.EventInject.u32ErrorCode %x\n", pVMCB->ctrl.EventInject.n.u32ErrorCode));
1092
1093	Log(("ctrl.u64NestedPagingCR3 %VX64\n", pVMCB->ctrl.u64NestedPagingCR3));
1094	Log(("ctrl.u64LBRVirt %VX64\n", pVMCB->ctrl.u64LBRVirt));
1095
1096	Log(("guest.CS.u16Sel %04X\n", pVMCB->guest.CS.u16Sel));
1097	Log(("guest.CS.u16Attr %04X\n", pVMCB->guest.CS.u16Attr));
1098	Log(("guest.CS.u32Limit %X\n", pVMCB->guest.CS.u32Limit));
1099	Log(("guest.CS.u64Base %VX64\n", pVMCB->guest.CS.u64Base));
1100	Log(("guest.DS.u16Sel %04X\n", pVMCB->guest.DS.u16Sel));
1101	Log(("guest.DS.u16Attr %04X\n", pVMCB->guest.DS.u16Attr));
1102	Log(("guest.DS.u32Limit %X\n", pVMCB->guest.DS.u32Limit));
1103	Log(("guest.DS.u64Base %VX64\n", pVMCB->guest.DS.u64Base));
1104	Log(("guest.ES.u16Sel %04X\n", pVMCB->guest.ES.u16Sel));
1105	Log(("guest.ES.u16Attr %04X\n", pVMCB->guest.ES.u16Attr));
1106	Log(("guest.ES.u32Limit %X\n", pVMCB->guest.ES.u32Limit));
1107	Log(("guest.ES.u64Base %VX64\n", pVMCB->guest.ES.u64Base));
1108	Log(("guest.FS.u16Sel %04X\n", pVMCB->guest.FS.u16Sel));
1109	Log(("guest.FS.u16Attr %04X\n", pVMCB->guest.FS.u16Attr));
1110	Log(("guest.FS.u32Limit %X\n", pVMCB->guest.FS.u32Limit));
1111	Log(("guest.FS.u64Base %VX64\n", pVMCB->guest.FS.u64Base));
1112	Log(("guest.GS.u16Sel %04X\n", pVMCB->guest.GS.u16Sel));
1113	Log(("guest.GS.u16Attr %04X\n", pVMCB->guest.GS.u16Attr));
1114	Log(("guest.GS.u32Limit %X\n", pVMCB->guest.GS.u32Limit));
1115	Log(("guest.GS.u64Base %VX64\n", pVMCB->guest.GS.u64Base));
1116
1117	Log(("guest.GDTR.u32Limit %X\n", pVMCB->guest.GDTR.u32Limit));
1118	Log(("guest.GDTR.u64Base %VX64\n", pVMCB->guest.GDTR.u64Base));
1119
1120	Log(("guest.LDTR.u16Sel %04X\n", pVMCB->guest.LDTR.u16Sel));
1121	Log(("guest.LDTR.u16Attr %04X\n", pVMCB->guest.LDTR.u16Attr));
1122	Log(("guest.LDTR.u32Limit %X\n", pVMCB->guest.LDTR.u32Limit));
1123	Log(("guest.LDTR.u64Base %VX64\n", pVMCB->guest.LDTR.u64Base));
1124
1125	Log(("guest.IDTR.u32Limit %X\n", pVMCB->guest.IDTR.u32Limit));
1126	Log(("guest.IDTR.u64Base %VX64\n", pVMCB->guest.IDTR.u64Base));
1127
1128	Log(("guest.TR.u16Sel %04X\n", pVMCB->guest.TR.u16Sel));
1129	Log(("guest.TR.u16Attr %04X\n", pVMCB->guest.TR.u16Attr));
1130	Log(("guest.TR.u32Limit %X\n", pVMCB->guest.TR.u32Limit));
1131	Log(("guest.TR.u64Base %VX64\n", pVMCB->guest.TR.u64Base));
1132
1133	Log(("guest.u8CPL %X\n", pVMCB->guest.u8CPL));
1134	Log(("guest.u64CR0 %VX64\n", pVMCB->guest.u64CR0));
1135	Log(("guest.u64CR2 %VX64\n", pVMCB->guest.u64CR2));
1136	Log(("guest.u64CR3 %VX64\n", pVMCB->guest.u64CR3));
1137	Log(("guest.u64CR4 %VX64\n", pVMCB->guest.u64CR4));
1138	Log(("guest.u64DR6 %VX64\n", pVMCB->guest.u64DR6));
1139	Log(("guest.u64DR7 %VX64\n", pVMCB->guest.u64DR7));
1140
1141	Log(("guest.u64RIP %VX64\n", pVMCB->guest.u64RIP));
1142	Log(("guest.u64RSP %VX64\n", pVMCB->guest.u64RSP));
1143	Log(("guest.u64RAX %VX64\n", pVMCB->guest.u64RAX));
1144	Log(("guest.u64RFlags %VX64\n", pVMCB->guest.u64RFlags));
1145
1146	Log(("guest.u64SysEnterCS %VX64\n", pVMCB->guest.u64SysEnterCS));
1147	Log(("guest.u64SysEnterEIP %VX64\n", pVMCB->guest.u64SysEnterEIP));
1148	Log(("guest.u64SysEnterESP %VX64\n", pVMCB->guest.u64SysEnterESP));
1149
1150	Log(("guest.u64EFER %VX64\n", pVMCB->guest.u64EFER));
1151	Log(("guest.u64STAR %VX64\n", pVMCB->guest.u64STAR));
1152	Log(("guest.u64LSTAR %VX64\n", pVMCB->guest.u64LSTAR));
1153	Log(("guest.u64CSTAR %VX64\n", pVMCB->guest.u64CSTAR));
1154	Log(("guest.u64SFMASK %VX64\n", pVMCB->guest.u64SFMASK));
1155	Log(("guest.u64KernelGSBase %VX64\n", pVMCB->guest.u64KernelGSBase));
1156	Log(("guest.u64GPAT %VX64\n", pVMCB->guest.u64GPAT));
1157	Log(("guest.u64DBGCTL %VX64\n", pVMCB->guest.u64DBGCTL));
1158	Log(("guest.u64BR_FROM %VX64\n", pVMCB->guest.u64BR_FROM));
1159	Log(("guest.u64BR_TO %VX64\n", pVMCB->guest.u64BR_TO));
1160	Log(("guest.u64LASTEXCPFROM %VX64\n", pVMCB->guest.u64LASTEXCPFROM));
1161	Log(("guest.u64LASTEXCPTO %VX64\n", pVMCB->guest.u64LASTEXCPTO));
1162
1163	#endif
1164	rc = VERR_SVM_UNABLE_TO_START_VM;
1165	goto end;
1166	}
1167
1168	/* Let's first sync back eip, esp, and eflags. */
1169	pCtx->rip = pVMCB->guest.u64RIP;
1170	pCtx->rsp = pVMCB->guest.u64RSP;
1171	pCtx->eflags.u32 = pVMCB->guest.u64RFlags;
1172	/* eax is saved/restore across the vmrun instruction */
1173	pCtx->rax = pVMCB->guest.u64RAX;
1174
1175	pCtx->msrKERNELGSBASE = pVMCB->guest.u64KernelGSBase; /* swapgs exchange value */
1176
1177	/* Can be updated behind our back in the nested paging case. */
1178	pCtx->cr2 = pVMCB->guest.u64CR2;
1179
1180	/* Guest CPU context: ES, CS, SS, DS, FS, GS. */
1181	SVM_READ_SELREG(SS, ss);
1182	SVM_READ_SELREG(CS, cs);
1183	SVM_READ_SELREG(DS, ds);
1184	SVM_READ_SELREG(ES, es);
1185	SVM_READ_SELREG(FS, fs);
1186	SVM_READ_SELREG(GS, gs);
1187
1188	/*
1189	* System MSRs
1190	*/
1191	pCtx->SysEnter.cs = pVMCB->guest.u64SysEnterCS;
1192	pCtx->SysEnter.eip = pVMCB->guest.u64SysEnterEIP;
1193	pCtx->SysEnter.esp = pVMCB->guest.u64SysEnterESP;
1194
1195	/* Remaining guest CPU context: TR, IDTR, GDTR, LDTR; must sync everything otherwise we can get out of sync when jumping to ring 3. */
1196	SVM_READ_SELREG(LDTR, ldtr);
1197	SVM_READ_SELREG(TR, tr);
1198
1199	pCtx->gdtr.cbGdt = pVMCB->guest.GDTR.u32Limit;
1200	pCtx->gdtr.pGdt = pVMCB->guest.GDTR.u64Base;
1201
1202	pCtx->idtr.cbIdt = pVMCB->guest.IDTR.u32Limit;
1203	pCtx->idtr.pIdt = pVMCB->guest.IDTR.u64Base;
1204
1205	/* Note: no reason to sync back the CRx and DRx registers. They can't be changed by the guest. */
1206	/* Note: only in the nested paging case can CR3 & CR4 be changed by the guest. */
1207	if ( pVM->hwaccm.s.fNestedPaging
1208	&& pCtx->cr3 != pVMCB->guest.u64CR3)
1209	{
1210	CPUMSetGuestCR3(pVM, pVMCB->guest.u64CR3);
1211	PGMUpdateCR3(pVM, pVMCB->guest.u64CR3);
1212	}
1213
1214	/* Note! NOW IT'S SAFE FOR LOGGING! */
1215
1216	/* Take care of instruction fusing (sti, mov ss) (see 15.20.5 Interrupt Shadows) */
1217	if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1218	{
1219	Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->rip));
1220	EMSetInhibitInterruptsPC(pVM, pCtx->rip);
1221	}
1222	else
1223	VM_FF_CLEAR(pVM, VM_FF_INHIBIT_INTERRUPTS);
1224
1225	Log2(("exitCode = %x\n", exitCode));
1226
1227	/* Sync back DR6 as it could have been changed by hitting breakpoints. */
1228	pCtx->dr[6] = pVMCB->guest.u64DR6;
1229	/* DR7.GD can be cleared by debug exceptions, so sync it back as well. */
1230	pCtx->dr[7] = pVMCB->guest.u64DR7;
1231
1232	/* Check if an injected event was interrupted prematurely. */
1233	pVM->hwaccm.s.Event.intInfo = pVMCB->ctrl.ExitIntInfo.au64[0];
1234	if ( pVMCB->ctrl.ExitIntInfo.n.u1Valid
1235	&& pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
1236	{
1237	Log(("Pending inject %VX64 at %VGv exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitCode));
1238
1239	#ifdef LOG_ENABLED
1240	SVM_EVENT Event;
1241	Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
1242
1243	if ( exitCode == SVM_EXIT_EXCEPTION_E
1244	&& Event.n.u8Vector == 0xE)
1245	{
1246	Log(("Double fault!\n"));
1247	}
1248	#endif
1249
1250	pVM->hwaccm.s.Event.fPending = true;
1251	/* Error code present? (redundant) */
1252	if (pVMCB->ctrl.ExitIntInfo.n.u1ErrorCodeValid)
1253	{
1254	pVM->hwaccm.s.Event.errCode = pVMCB->ctrl.ExitIntInfo.n.u32ErrorCode;
1255	}
1256	else
1257	pVM->hwaccm.s.Event.errCode = 0;
1258	}
1259	#ifdef VBOX_WITH_STATISTICS
1260	if (exitCode == SVM_EXIT_NPF)
1261	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitReasonNPF);
1262	else
1263	STAM_COUNTER_INC(&pVM->hwaccm.s.paStatExitReasonR0[exitCode & MASK_EXITREASON_STAT]);
1264	#endif
1265
1266	if (fSyncTPR)
1267	{
1268	rc = PDMApicSetTPR(pVM, pVMCB->ctrl.IntCtrl.n.u8VTPR);
1269	AssertRC(rc);
1270	}
1271
1272	/* Deal with the reason of the VM-exit. */
1273	switch (exitCode)
1274	{
1275	case SVM_EXIT_EXCEPTION_0: case SVM_EXIT_EXCEPTION_1: case SVM_EXIT_EXCEPTION_2: case SVM_EXIT_EXCEPTION_3:
1276	case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5: case SVM_EXIT_EXCEPTION_6: case SVM_EXIT_EXCEPTION_7:
1277	case SVM_EXIT_EXCEPTION_8: case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_A: case SVM_EXIT_EXCEPTION_B:
1278	case SVM_EXIT_EXCEPTION_C: case SVM_EXIT_EXCEPTION_D: case SVM_EXIT_EXCEPTION_E: case SVM_EXIT_EXCEPTION_F:
1279	case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11: case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13:
1280	case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: case SVM_EXIT_EXCEPTION_17:
1281	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B:
1282	case SVM_EXIT_EXCEPTION_1C: case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
1283	{
1284	/* Pending trap. */
1285	SVM_EVENT Event;
1286	uint32_t vector = exitCode - SVM_EXIT_EXCEPTION_0;
1287
1288	Log2(("Hardware/software interrupt %d\n", vector));
1289	switch (vector)
1290	{
1291	case X86_XCPT_DB:
1292	{
1293	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDB);
1294
1295	/* Note that we don't support guest and host-initiated debugging at the same time. */
1296	Assert(DBGFIsStepping(pVM));
1297
1298	rc = DBGFR0Trap01Handler(pVM, CPUMCTX2CORE(pCtx), pCtx->dr[6]);
1299	if (rc == VINF_EM_RAW_GUEST_TRAP)
1300	{
1301	Log(("Trap %x (debug) at %VGv\n", vector, pCtx->rip));
1302
1303	/* Reinject the exception. */
1304	Event.au64[0] = 0;
1305	Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1306	Event.n.u1Valid = 1;
1307	Event.n.u8Vector = X86_XCPT_DB;
1308
1309	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1310
1311	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1312	goto ResumeExecution;
1313	}
1314	/* Return to ring 3 to deal with the debug exit code. */
1315	break;
1316	}
1317
1318	case X86_XCPT_NM:
1319	{
1320	Log(("#NM fault at %VGv\n", pCtx->rip));
1321
1322	/** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
1323	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
1324	rc = CPUMR0LoadGuestFPU(pVM, pCtx);
1325	if (rc == VINF_SUCCESS)
1326	{
1327	Assert(CPUMIsGuestFPUStateActive(pVM));
1328	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowNM);
1329
1330	/* Continue execution. */
1331	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1332	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1333
1334	goto ResumeExecution;
1335	}
1336
1337	Log(("Forward #NM fault to the guest\n"));
1338	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNM);
1339
1340	Event.au64[0] = 0;
1341	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1342	Event.n.u1Valid = 1;
1343	Event.n.u8Vector = X86_XCPT_NM;
1344
1345	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1346	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1347	goto ResumeExecution;
1348	}
1349
1350	case X86_XCPT_PF: /* Page fault */
1351	{
1352	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1353	RTGCUINTPTR uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1354
1355	#ifdef DEBUG
1356	if (pVM->hwaccm.s.fNestedPaging)
1357	{ /* A genuine pagefault.
1358	* Forward the trap to the guest by injecting the exception and resuming execution.
1359	*/
1360	Log(("Guest page fault at %VGv cr2=%VGv error code %x rsp=%VGv\n", (RTGCPTR)pCtx->rip, uFaultAddress, errCode, (RTGCPTR)pCtx->rsp));
1361	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1362
1363	/* Now we must update CR2. */
1364	pCtx->cr2 = uFaultAddress;
1365
1366	Event.au64[0] = 0;
1367	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1368	Event.n.u1Valid = 1;
1369	Event.n.u8Vector = X86_XCPT_PF;
1370	Event.n.u1ErrorCodeValid = 1;
1371	Event.n.u32ErrorCode = errCode;
1372
1373	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1374
1375	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1376	goto ResumeExecution;
1377	}
1378	#endif
1379	Assert(!pVM->hwaccm.s.fNestedPaging);
1380
1381	Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
1382	/* Exit qualification contains the linear address of the page fault. */
1383	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1384	TRPMSetErrorCode(pVM, errCode);
1385	TRPMSetFaultAddress(pVM, uFaultAddress);
1386
1387	/* Forward it to our trap handler first, in case our shadow pages are out of sync. */
1388	rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
1389	Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
1390	if (rc == VINF_SUCCESS)
1391	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1392	Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
1393	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1394
1395	TRPMResetTrap(pVM);
1396
1397	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1398	goto ResumeExecution;
1399	}
1400	else
1401	if (rc == VINF_EM_RAW_GUEST_TRAP)
1402	{ /* A genuine pagefault.
1403	* Forward the trap to the guest by injecting the exception and resuming execution.
1404	*/
1405	Log2(("Forward page fault to the guest\n"));
1406	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
1407	/* The error code might have been changed. */
1408	errCode = TRPMGetErrorCode(pVM);
1409
1410	TRPMResetTrap(pVM);
1411
1412	/* Now we must update CR2. */
1413	pCtx->cr2 = uFaultAddress;
1414
1415	Event.au64[0] = 0;
1416	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1417	Event.n.u1Valid = 1;
1418	Event.n.u8Vector = X86_XCPT_PF;
1419	Event.n.u1ErrorCodeValid = 1;
1420	Event.n.u32ErrorCode = errCode;
1421
1422	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1423
1424	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1425	goto ResumeExecution;
1426	}
1427	#ifdef VBOX_STRICT
1428	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1429	LogFlow(("PGMTrap0eHandler failed with %d\n", rc));
1430	#endif
1431	/* Need to go back to the recompiler to emulate the instruction. */
1432	TRPMResetTrap(pVM);
1433	break;
1434	}
1435
1436	case X86_XCPT_MF: /* Floating point exception. */
1437	{
1438	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestMF);
1439	if (!(pCtx->cr0 & X86_CR0_NE))
1440	{
1441	/* old style FPU error reporting needs some extra work. */
1442	/** @todo don't fall back to the recompiler, but do it manually. */
1443	rc = VINF_EM_RAW_EMULATE_INSTR;
1444	break;
1445	}
1446	Log(("Trap %x at %VGv\n", vector, pCtx->rip));
1447
1448	Event.au64[0] = 0;
1449	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1450	Event.n.u1Valid = 1;
1451	Event.n.u8Vector = X86_XCPT_MF;
1452
1453	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1454
1455	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1456	goto ResumeExecution;
1457	}
1458
1459	#ifdef VBOX_STRICT
1460	case X86_XCPT_GP: /* General protection failure exception.*/
1461	case X86_XCPT_UD: /* Unknown opcode exception. */
1462	case X86_XCPT_DE: /* Divide error. */
1463	case X86_XCPT_SS: /* Stack segment exception. */
1464	case X86_XCPT_NP: /* Segment not present exception. */
1465	{
1466	Event.au64[0] = 0;
1467	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1468	Event.n.u1Valid = 1;
1469	Event.n.u8Vector = vector;
1470
1471	switch(vector)
1472	{
1473	case X86_XCPT_GP:
1474	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestGP);
1475	Event.n.u1ErrorCodeValid = 1;
1476	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1477	break;
1478	case X86_XCPT_DE:
1479	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestDE);
1480	break;
1481	case X86_XCPT_UD:
1482	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestUD);
1483	break;
1484	case X86_XCPT_SS:
1485	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestSS);
1486	Event.n.u1ErrorCodeValid = 1;
1487	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1488	break;
1489	case X86_XCPT_NP:
1490	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestNP);
1491	Event.n.u1ErrorCodeValid = 1;
1492	Event.n.u32ErrorCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1493	break;
1494	}
1495	Log(("Trap %x at %VGv esi=%x\n", vector, pCtx->rip, pCtx->esi));
1496	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1497
1498	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1499	goto ResumeExecution;
1500	}
1501	#endif
1502	default:
1503	AssertMsgFailed(("Unexpected vm-exit caused by exception %x\n", vector));
1504	rc = VERR_EM_INTERNAL_ERROR;
1505	break;
1506
1507	} /* switch (vector) */
1508	break;
1509	}
1510
1511	case SVM_EXIT_NPF:
1512	{
1513	/* EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault. */
1514	uint32_t errCode = pVMCB->ctrl.u64ExitInfo1; /* EXITINFO1 = error code */
1515	RTGCPHYS uFaultAddress = pVMCB->ctrl.u64ExitInfo2; /* EXITINFO2 = fault address */
1516
1517	Assert(pVM->hwaccm.s.fNestedPaging);
1518	Log(("Nested page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, uFaultAddress, errCode));
1519	/* Exit qualification contains the linear address of the page fault. */
1520	TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
1521	TRPMSetErrorCode(pVM, errCode);
1522	TRPMSetFaultAddress(pVM, uFaultAddress);
1523
1524	/* Handle the pagefault trap for the nested shadow table. */
1525	rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMGetHostMode(pVM), errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
1526	Log2(("PGMR0Trap0eHandlerNestedPaging %VGv returned %Vrc\n", pCtx->rip, rc));
1527	if (rc == VINF_SUCCESS)
1528	{ /* We've successfully synced our shadow pages, so let's just continue execution. */
1529	Log2(("Shadow page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, uFaultAddress, errCode));
1530	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
1531
1532	TRPMResetTrap(pVM);
1533
1534	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1535	goto ResumeExecution;
1536	}
1537
1538	#ifdef VBOX_STRICT
1539	if (rc != VINF_EM_RAW_EMULATE_INSTR)
1540	LogFlow(("PGMTrap0eHandlerNestedPaging failed with %d\n", rc));
1541	#endif
1542	/* Need to go back to the recompiler to emulate the instruction. */
1543	TRPMResetTrap(pVM);
1544	break;
1545	}
1546
1547	case SVM_EXIT_VINTR:
1548	/* A virtual interrupt is about to be delivered, which means IF=1. */
1549	Log(("SVM_EXIT_VINTR IF=%d\n", pCtx->eflags.Bits.u1IF));
1550	pVMCB->ctrl.IntCtrl.n.u1VIrqValid = 0;
1551	pVMCB->ctrl.IntCtrl.n.u8VIrqVector = 0;
1552	goto ResumeExecution;
1553
1554	case SVM_EXIT_FERR_FREEZE:
1555	case SVM_EXIT_INTR:
1556	case SVM_EXIT_NMI:
1557	case SVM_EXIT_SMI:
1558	case SVM_EXIT_INIT:
1559	/* External interrupt; leave to allow it to be dispatched again. */
1560	rc = VINF_EM_RAW_INTERRUPT;
1561	break;
1562
1563	case SVM_EXIT_WBINVD:
1564	case SVM_EXIT_INVD: /* Guest software attempted to execute INVD. */
1565	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
1566	/* Skip instruction and continue directly. */
1567	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1568	/* Continue execution.*/
1569	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1570	goto ResumeExecution;
1571
1572	case SVM_EXIT_CPUID: /* Guest software attempted to execute CPUID. */
1573	{
1574	Log2(("SVM: Cpuid at %VGv for %x\n", pCtx->rip, pCtx->eax));
1575	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCpuid);
1576	rc = EMInterpretCpuId(pVM, CPUMCTX2CORE(pCtx));
1577	if (rc == VINF_SUCCESS)
1578	{
1579	/* Update EIP and continue execution. */
1580	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1581	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1582	goto ResumeExecution;
1583	}
1584	AssertMsgFailed(("EMU: cpuid failed with %Vrc\n", rc));
1585	rc = VINF_EM_RAW_EMULATE_INSTR;
1586	break;
1587	}
1588
1589	case SVM_EXIT_RDTSC: /* Guest software attempted to execute RDTSC. */
1590	{
1591	Log2(("SVM: Rdtsc\n"));
1592	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitRdtsc);
1593	rc = EMInterpretRdtsc(pVM, CPUMCTX2CORE(pCtx));
1594	if (rc == VINF_SUCCESS)
1595	{
1596	/* Update EIP and continue execution. */
1597	pCtx->rip += 2; /* Note! hardcoded opcode size! */
1598	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1599	goto ResumeExecution;
1600	}
1601	AssertMsgFailed(("EMU: rdtsc failed with %Vrc\n", rc));
1602	rc = VINF_EM_RAW_EMULATE_INSTR;
1603	break;
1604	}
1605
1606	case SVM_EXIT_INVLPG: /* Guest software attempted to execute INVPG. */
1607	{
1608	Log2(("SVM: invlpg\n"));
1609	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvpg);
1610
1611	Assert(!pVM->hwaccm.s.fNestedPaging);
1612
1613	/* Truly a pita. Why can't SVM give the same information as VT-x? */
1614	rc = SVMR0InterpretInvpg(pVM, CPUMCTX2CORE(pCtx), pVMCB->ctrl.TLBCtrl.n.u32ASID);
1615	if (rc == VINF_SUCCESS)
1616	{
1617	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageInvlpg);
1618	goto ResumeExecution; /* eip already updated */
1619	}
1620	break;
1621	}
1622
1623	case SVM_EXIT_WRITE_CR0: case SVM_EXIT_WRITE_CR1: case SVM_EXIT_WRITE_CR2: case SVM_EXIT_WRITE_CR3:
1624	case SVM_EXIT_WRITE_CR4: case SVM_EXIT_WRITE_CR5: case SVM_EXIT_WRITE_CR6: case SVM_EXIT_WRITE_CR7:
1625	case SVM_EXIT_WRITE_CR8: case SVM_EXIT_WRITE_CR9: case SVM_EXIT_WRITE_CR10: case SVM_EXIT_WRITE_CR11:
1626	case SVM_EXIT_WRITE_CR12: case SVM_EXIT_WRITE_CR13: case SVM_EXIT_WRITE_CR14: case SVM_EXIT_WRITE_CR15:
1627	{
1628	uint32_t cbSize;
1629
1630	Log2(("SVM: %VGv mov cr%d, \n", pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
1631	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
1632	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1633
1634	switch (exitCode - SVM_EXIT_WRITE_CR0)
1635	{
1636	case 0:
1637	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1638	break;
1639	case 2:
1640	break;
1641	case 3:
1642	Assert(!pVM->hwaccm.s.fNestedPaging);
1643	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR3;
1644	break;
1645	case 4:
1646	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR4;
1647	break;
1648	case 8:
1649	break;
1650	default:
1651	AssertFailed();
1652	}
1653	/* Check if a sync operation is pending. */
1654	if ( rc == VINF_SUCCESS /* don't bother if we are going to ring 3 anyway */
1655	&& VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL))
1656	{
1657	rc = PGMSyncCR3(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM), VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
1658	AssertRC(rc);
1659
1660	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushTLBCRxChange);
1661
1662	/* Must be set by PGMSyncCR3 */
1663	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PROTECTED \|\| pVM->hwaccm.s.svm.fForceTLBFlush);
1664	}
1665	if (rc == VINF_SUCCESS)
1666	{
1667	/* EIP has been updated already. */
1668
1669	/* Only resume if successful. */
1670	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1671	goto ResumeExecution;
1672	}
1673	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1674	break;
1675	}
1676
1677	case SVM_EXIT_READ_CR0: case SVM_EXIT_READ_CR1: case SVM_EXIT_READ_CR2: case SVM_EXIT_READ_CR3:
1678	case SVM_EXIT_READ_CR4: case SVM_EXIT_READ_CR5: case SVM_EXIT_READ_CR6: case SVM_EXIT_READ_CR7:
1679	case SVM_EXIT_READ_CR8: case SVM_EXIT_READ_CR9: case SVM_EXIT_READ_CR10: case SVM_EXIT_READ_CR11:
1680	case SVM_EXIT_READ_CR12: case SVM_EXIT_READ_CR13: case SVM_EXIT_READ_CR14: case SVM_EXIT_READ_CR15:
1681	{
1682	uint32_t cbSize;
1683
1684	Log2(("SVM: %VGv mov x, cr%d\n", pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
1685	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
1686	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1687	if (rc == VINF_SUCCESS)
1688	{
1689	/* EIP has been updated already. */
1690
1691	/* Only resume if successful. */
1692	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1693	goto ResumeExecution;
1694	}
1695	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1696	break;
1697	}
1698
1699	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
1700	case SVM_EXIT_WRITE_DR4: case SVM_EXIT_WRITE_DR5: case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7:
1701	case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9: case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11:
1702	case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13: case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
1703	{
1704	uint32_t cbSize;
1705
1706	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
1707	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1708
1709	if (!DBGFIsStepping(pVM))
1710	{
1711	STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxContextSwitch);
1712
1713	/* Disable drx move intercepts. */
1714	pVMCB->ctrl.u16InterceptRdDRx = 0;
1715	pVMCB->ctrl.u16InterceptWrDRx = 0;
1716
1717	/* Save the host and load the guest debug state. */
1718	rc = CPUMR0LoadGuestDebugState(pVM, pCtx, false /* exclude DR6 */);
1719	AssertRC(rc);
1720
1721	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1722	goto ResumeExecution;
1723	}
1724
1725	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1726	if (rc == VINF_SUCCESS)
1727	{
1728	/* EIP has been updated already. */
1729	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
1730
1731	/* Only resume if successful. */
1732	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1733	goto ResumeExecution;
1734	}
1735	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1736	break;
1737	}
1738
1739	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
1740	case SVM_EXIT_READ_DR4: case SVM_EXIT_READ_DR5: case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7:
1741	case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9: case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11:
1742	case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13: case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
1743	{
1744	uint32_t cbSize;
1745
1746	Log2(("SVM: %VGv mov dr%d, x\n", pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
1747	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
1748
1749	if (!DBGFIsStepping(pVM))
1750	{
1751	STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxContextSwitch);
1752
1753	/* Disable drx move intercepts. */
1754	pVMCB->ctrl.u16InterceptRdDRx = 0;
1755	pVMCB->ctrl.u16InterceptWrDRx = 0;
1756
1757	/* Save the host and load the guest debug state. */
1758	rc = CPUMR0LoadGuestDebugState(pVM, pCtx, false /* exclude DR6 */);
1759	AssertRC(rc);
1760
1761	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1762	goto ResumeExecution;
1763	}
1764
1765	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1766	if (rc == VINF_SUCCESS)
1767	{
1768	/* EIP has been updated already. */
1769
1770	/* Only resume if successful. */
1771	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1772	goto ResumeExecution;
1773	}
1774	Assert(rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3);
1775	break;
1776	}
1777
1778	/* Note: We'll get a #GP if the IO instruction isn't allowed (IOPL or TSS bitmap); no need to double check. */
1779	case SVM_EXIT_IOIO: /* I/O instruction. */
1780	{
1781	SVM_IOIO_EXIT IoExitInfo;
1782	uint32_t uIOSize, uAndVal;
1783
1784	IoExitInfo.au32[0] = pVMCB->ctrl.u64ExitInfo1;
1785
1786	/** @todo could use a lookup table here */
1787	if (IoExitInfo.n.u1OP8)
1788	{
1789	uIOSize = 1;
1790	uAndVal = 0xff;
1791	}
1792	else
1793	if (IoExitInfo.n.u1OP16)
1794	{
1795	uIOSize = 2;
1796	uAndVal = 0xffff;
1797	}
1798	else
1799	if (IoExitInfo.n.u1OP32)
1800	{
1801	uIOSize = 4;
1802	uAndVal = 0xffffffff;
1803	}
1804	else
1805	{
1806	AssertFailed(); /* should be fatal. */
1807	rc = VINF_EM_RAW_EMULATE_INSTR;
1808	break;
1809	}
1810
1811	if (IoExitInfo.n.u1STR)
1812	{
1813	/* ins/outs */
1814	uint32_t prefix = 0;
1815	if (IoExitInfo.n.u1REP)
1816	prefix \|= PREFIX_REP;
1817
1818	if (IoExitInfo.n.u1Type == 0)
1819	{
1820	Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1821	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
1822	rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1823	}
1824	else
1825	{
1826	Log2(("IOMInterpretINSEx %VGv %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1827	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
1828	rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
1829	}
1830	}
1831	else
1832	{
1833	/* normal in/out */
1834	Assert(!IoExitInfo.n.u1REP);
1835
1836	if (IoExitInfo.n.u1Type == 0)
1837	{
1838	Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
1839	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
1840	rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
1841	}
1842	else
1843	{
1844	uint32_t u32Val = 0;
1845
1846	STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIORead);
1847	rc = IOMIOPortRead(pVM, IoExitInfo.n.u16Port, &u32Val, uIOSize);
1848	if (IOM_SUCCESS(rc))
1849	{
1850	/* Write back to the EAX register. */
1851	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
1852	Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
1853	}
1854	}
1855	}
1856	/*
1857	* Handled the I/O return codes.
1858	* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
1859	*/
1860	if (IOM_SUCCESS(rc))
1861	{
1862	/* Update EIP and continue execution. */
1863	pCtx->rip = pVMCB->ctrl.u64ExitInfo2; /* RIP/EIP of the next instruction is saved in EXITINFO2. */
1864	if (RT_LIKELY(rc == VINF_SUCCESS))
1865	{
1866	/* If any IO breakpoints are armed, then we should check if a debug trap needs to be generated. */
1867	if (pCtx->dr[7] & X86_DR7_ENABLED_MASK)
1868	{
1869	STAM_COUNTER_INC(&pVM->hwaccm.s.StatDRxIOCheck);
1870	for (unsigned i=0;i<4;i++)
1871	{
1872	unsigned uBPLen = g_aIOSize[X86_DR7_GET_LEN(pCtx->dr[7], i)];
1873
1874	if ( (IoExitInfo.n.u16Port >= pCtx->dr[i] && IoExitInfo.n.u16Port < pCtx->dr[i] + uBPLen)
1875	&& (pCtx->dr[7] & (X86_DR7_L(i) \| X86_DR7_G(i)))
1876	&& (pCtx->dr[7] & X86_DR7_RW(i, X86_DR7_RW_IO)) == X86_DR7_RW(i, X86_DR7_RW_IO))
1877	{
1878	SVM_EVENT Event;
1879
1880	Assert(CPUMIsGuestDebugStateActive(pVM));
1881
1882	/* Clear all breakpoint status flags and set the one we just hit. */
1883	pCtx->dr[6] &= ~(X86_DR6_B0\|X86_DR6_B1\|X86_DR6_B2\|X86_DR6_B3);
1884	pCtx->dr[6] \|= RT_BIT(i);
1885
1886	/* Note: AMD64 Architecture Programmer's Manual 13.1:
1887	* Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software after
1888	* the contents have been read.
1889	*/
1890	pVMCB->guest.u64DR6 = pCtx->dr[6];
1891
1892	/* X86_DR7_GD will be cleared if drx accesses should be trapped inside the guest. */
1893	pCtx->dr[7] &= ~X86_DR7_GD;
1894
1895	/* Paranoia. */
1896	pCtx->dr[7] &= 0xffffffff; /* upper 32 bits reserved */
1897	pCtx->dr[7] &= ~(RT_BIT(11) \| RT_BIT(12) \| RT_BIT(14) \| RT_BIT(15)); /* must be zero */
1898	pCtx->dr[7] \|= 0x400; /* must be one */
1899
1900	pVMCB->guest.u64DR7 = pCtx->dr[7];
1901
1902	/* Inject the exception. */
1903	Log(("Inject IO debug trap at %VGv\n", pCtx->rip));
1904
1905	Event.au64[0] = 0;
1906	Event.n.u3Type = SVM_EVENT_EXCEPTION; /* trap or fault */
1907	Event.n.u1Valid = 1;
1908	Event.n.u8Vector = X86_XCPT_DB;
1909
1910	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1911
1912	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1913	goto ResumeExecution;
1914	}
1915	}
1916	}
1917
1918	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1919	goto ResumeExecution;
1920	}
1921	Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
1922	break;
1923	}
1924
1925	#ifdef VBOX_STRICT
1926	if (rc == VINF_IOM_HC_IOPORT_READ)
1927	Assert(IoExitInfo.n.u1Type != 0);
1928	else if (rc == VINF_IOM_HC_IOPORT_WRITE)
1929	Assert(IoExitInfo.n.u1Type == 0);
1930	else
1931	AssertMsg(VBOX_FAILURE(rc) \|\| rc == VINF_EM_RAW_EMULATE_INSTR \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
1932	#endif
1933	Log2(("Failed IO at %VGv %x size %d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
1934	break;
1935	}
1936
1937	case SVM_EXIT_HLT:
1938	/** Check if external interrupts are pending; if so, don't switch back. */
1939	pCtx->rip++; /* skip hlt */
1940	if ( pCtx->eflags.Bits.u1IF
1941	&& VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC\|VM_FF_INTERRUPT_PIC)))
1942	goto ResumeExecution;
1943
1944	rc = VINF_EM_HALT;
1945	break;
1946
1947	case SVM_EXIT_RSM:
1948	case SVM_EXIT_INVLPGA:
1949	case SVM_EXIT_VMRUN:
1950	case SVM_EXIT_VMMCALL:
1951	case SVM_EXIT_VMLOAD:
1952	case SVM_EXIT_VMSAVE:
1953	case SVM_EXIT_STGI:
1954	case SVM_EXIT_CLGI:
1955	case SVM_EXIT_SKINIT:
1956	case SVM_EXIT_RDTSCP:
1957	{
1958	/* Unsupported instructions. */
1959	SVM_EVENT Event;
1960
1961	Event.au64[0] = 0;
1962	Event.n.u3Type = SVM_EVENT_EXCEPTION;
1963	Event.n.u1Valid = 1;
1964	Event.n.u8Vector = X86_XCPT_UD;
1965
1966	Log(("Forced #UD trap at %VGv\n", pCtx->rip));
1967	SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
1968
1969	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1970	goto ResumeExecution;
1971	}
1972
1973	/* Emulate in ring 3. */
1974	case SVM_EXIT_MSR:
1975	{
1976	uint32_t cbSize;
1977
1978	/* Note: the intel manual claims there's a REX version of RDMSR that's slightly different, so we play safe by completely disassembling the instruction. */
1979	Log(("SVM: %s\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr"));
1980	rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
1981	if (rc == VINF_SUCCESS)
1982	{
1983	/* EIP has been updated already. */
1984
1985	/* Only resume if successful. */
1986	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
1987	goto ResumeExecution;
1988	}
1989	AssertMsg(rc == VERR_EM_INTERPRETER, ("EMU: %s failed with %Vrc\n", (pVMCB->ctrl.u64ExitInfo1 == 0) ? "rdmsr" : "wrmsr", rc));
1990	break;
1991	}
1992
1993	case SVM_EXIT_MONITOR:
1994	case SVM_EXIT_RDPMC:
1995	case SVM_EXIT_PAUSE:
1996	case SVM_EXIT_MWAIT_UNCOND:
1997	case SVM_EXIT_MWAIT_ARMED:
1998	case SVM_EXIT_TASK_SWITCH: /* can change CR3; emulate */
1999	rc = VINF_EM_RAW_EXCEPTION_PRIVILEGED;
2000	break;
2001
2002	case SVM_EXIT_SHUTDOWN:
2003	rc = VINF_EM_RESET; /* Triple fault equals a reset. */
2004	break;
2005
2006	case SVM_EXIT_IDTR_READ:
2007	case SVM_EXIT_GDTR_READ:
2008	case SVM_EXIT_LDTR_READ:
2009	case SVM_EXIT_TR_READ:
2010	case SVM_EXIT_IDTR_WRITE:
2011	case SVM_EXIT_GDTR_WRITE:
2012	case SVM_EXIT_LDTR_WRITE:
2013	case SVM_EXIT_TR_WRITE:
2014	case SVM_EXIT_CR0_SEL_WRITE:
2015	default:
2016	/* Unexpected exit codes. */
2017	rc = VERR_EM_INTERNAL_ERROR;
2018	AssertMsgFailed(("Unexpected exit code %x\n", exitCode)); /* Can't happen. */
2019	break;
2020	}
2021
2022	end:
2023
2024	/* Signal changes for the recompiler. */
2025	CPUMSetChangedFlags(pVM, CPUM_CHANGED_SYSENTER_MSR \| CPUM_CHANGED_LDTR \| CPUM_CHANGED_GDTR \| CPUM_CHANGED_IDTR \| CPUM_CHANGED_TR \| CPUM_CHANGED_HIDDEN_SEL_REGS);
2026
2027	/* If we executed vmrun and an external irq was pending, then we don't have to do a full sync the next time. */
2028	if (exitCode == SVM_EXIT_INTR)
2029	{
2030	STAM_COUNTER_INC(&pVM->hwaccm.s.StatPendingHostIrq);
2031	/* On the next entry we'll only sync the host context. */
2032	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_HOST_CONTEXT;
2033	}
2034	else
2035	{
2036	/* On the next entry we'll sync everything. */
2037	/** @todo we can do better than this */
2038	/* Not in the VINF_PGM_CHANGE_MODE though! */
2039	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL;
2040	}
2041
2042	/* translate into a less severe return code */
2043	if (rc == VERR_EM_INTERPRETER)
2044	rc = VINF_EM_RAW_EMULATE_INSTR;
2045
2046	STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
2047	return rc;
2048	}
2049
2050	/**
2051	* Enters the AMD-V session
2052	*
2053	* @returns VBox status code.
2054	* @param pVM The VM to operate on.
2055	* @param pCpu CPU info struct
2056	*/
2057	HWACCMR0DECL(int) SVMR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
2058	{
2059	Assert(pVM->hwaccm.s.svm.fSupported);
2060
2061	LogFlow(("SVMR0Enter cpu%d last=%d asid=%d\n", pCpu->idCpu, pVM->hwaccm.s.svm.idLastCpu, pVM->hwaccm.s.svm.uCurrentASID));
2062	pVM->hwaccm.s.svm.fResumeVM = false;
2063
2064	/* Force to reload LDTR, so we'll execute VMLoad to load additional guest state. */
2065	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_LDTR;
2066
2067	return VINF_SUCCESS;
2068	}
2069
2070
2071	/**
2072	* Leaves the AMD-V session
2073	*
2074	* @returns VBox status code.
2075	* @param pVM The VM to operate on.
2076	* @param pCtx CPU context
2077	*/
2078	HWACCMR0DECL(int) SVMR0Leave(PVM pVM, PCPUMCTX pCtx)
2079	{
2080	SVM_VMCB pVMCB = (SVM_VMCB )pVM->hwaccm.s.svm.pVMCB;
2081
2082	Assert(pVM->hwaccm.s.svm.fSupported);
2083
2084	/* Save the guest debug state if necessary. */
2085	if (CPUMIsGuestDebugStateActive(pVM))
2086	{
2087	CPUMR0SaveGuestDebugState(pVM, pCtx, false /* skip DR6 */);
2088
2089	/* Intercept all DRx reads and writes again. Changed later on. */
2090	pVMCB->ctrl.u16InterceptRdDRx = 0xFFFF;
2091	pVMCB->ctrl.u16InterceptWrDRx = 0xFFFF;
2092
2093	/* Resync the debug registers the next time. */
2094	pVM->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_DEBUG;
2095	}
2096	else
2097	Assert(pVMCB->ctrl.u16InterceptRdDRx == 0xFFFF && pVMCB->ctrl.u16InterceptWrDRx == 0xFFFF);
2098
2099	return VINF_SUCCESS;
2100	}
2101
2102
2103	static int svmR0InterpretInvlPg(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2104	{
2105	OP_PARAMVAL param1;
2106	RTGCPTR addr;
2107
2108	int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->param1, &param1, PARAM_SOURCE);
2109	if(VBOX_FAILURE(rc))
2110	return VERR_EM_INTERPRETER;
2111
2112	switch(param1.type)
2113	{
2114	case PARMTYPE_IMMEDIATE:
2115	case PARMTYPE_ADDRESS:
2116	if(!(param1.flags & (PARAM_VAL32\|PARAM_VAL64)))
2117	return VERR_EM_INTERPRETER;
2118	addr = param1.val.val64;
2119	break;
2120
2121	default:
2122	return VERR_EM_INTERPRETER;
2123	}
2124
2125	/** @todo is addr always a flat linear address or ds based
2126	* (in absence of segment override prefixes)????
2127	*/
2128	rc = PGMInvalidatePage(pVM, addr);
2129	if (VBOX_SUCCESS(rc))
2130	{
2131	/* Manually invalidate the page for the VM's TLB. */
2132	Log(("SVMInvlpgA %VGv ASID=%d\n", addr, uASID));
2133	SVMInvlpgA(addr, uASID);
2134	return VINF_SUCCESS;
2135	}
2136	Assert(rc == VERR_REM_FLUSHED_PAGES_OVERFLOW);
2137	return rc;
2138	}
2139
2140	/**
2141	* Interprets INVLPG
2142	*
2143	* @returns VBox status code.
2144	* @retval VINF_* Scheduling instructions.
2145	* @retval VERR_EM_INTERPRETER Something we can't cope with.
2146	* @retval VERR_* Fatal errors.
2147	*
2148	* @param pVM The VM handle.
2149	* @param pRegFrame The register frame.
2150	* @param ASID Tagged TLB id for the guest
2151	*
2152	* Updates the EIP if an instruction was executed successfully.
2153	*/
2154	static int SVMR0InterpretInvpg(PVM pVM, PCPUMCTXCORE pRegFrame, uint32_t uASID)
2155	{
2156	/*
2157	* Only allow 32 & 64 bits code.
2158	*/
2159	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid);
2160	if (enmMode != CPUMODE_16BIT)
2161	{
2162	RTGCPTR pbCode;
2163	int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
2164	if (VBOX_SUCCESS(rc))
2165	{
2166	uint32_t cbOp;
2167	DISCPUSTATE Cpu;
2168
2169	Cpu.mode = enmMode;
2170	rc = EMInterpretDisasOneEx(pVM, pbCode, pRegFrame, &Cpu, &cbOp);
2171	Assert(VBOX_FAILURE(rc) \|\| Cpu.pCurInstr->opcode == OP_INVLPG);
2172	if (VBOX_SUCCESS(rc) && Cpu.pCurInstr->opcode == OP_INVLPG)
2173	{
2174	Assert(cbOp == Cpu.opsize);
2175	rc = svmR0InterpretInvlPg(pVM, &Cpu, pRegFrame, uASID);
2176	if (VBOX_SUCCESS(rc))
2177	{
2178	pRegFrame->rip += cbOp; /* Move on to the next instruction. */
2179	}
2180	return rc;
2181	}
2182	}
2183	}
2184	return VERR_EM_INTERPRETER;
2185	}
2186
2187
2188	/**
2189	* Invalidates a guest page
2190	*
2191	* @returns VBox status code.
2192	* @param pVM The VM to operate on.
2193	* @param GCVirt Page to invalidate
2194	*/
2195	HWACCMR0DECL(int) SVMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
2196	{
2197	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVM->hwaccm.s.svm.fForceTLBFlush;
2198
2199	/* Skip it if a TLB flush is already pending. */
2200	if (!fFlushPending)
2201	{
2202	SVM_VMCB *pVMCB;
2203
2204	Log2(("SVMR0InvalidatePage %VGv\n", GCVirt));
2205	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2206	Assert(pVM->hwaccm.s.svm.fSupported);
2207
2208	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
2209	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2210
2211	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPageManual);
2212	SVMInvlpgA(GCVirt, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2213	}
2214	return VINF_SUCCESS;
2215	}
2216
2217
2218	/**
2219	* Invalidates a guest page by physical address
2220	*
2221	* NOTE: Assumes the current instruction references this physical page though a virtual address!!
2222	*
2223	* @returns VBox status code.
2224	* @param pVM The VM to operate on.
2225	* @param GCPhys Page to invalidate
2226	*/
2227	HWACCMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys)
2228	{
2229	bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB \| pVM->hwaccm.s.svm.fForceTLBFlush;
2230
2231	Assert(pVM->hwaccm.s.fNestedPaging);
2232
2233	/* Skip it if a TLB flush is already pending. */
2234	if (!fFlushPending)
2235	{
2236	CPUMCTX *pCtx;
2237	int rc;
2238	SVM_VMCB *pVMCB;
2239
2240	rc = CPUMQueryGuestCtxPtr(pVM, &pCtx);
2241	AssertRCReturn(rc, rc);
2242
2243	Log2(("SVMR0InvalidatePhysPage %VGp\n", GCPhys));
2244	AssertReturn(pVM, VERR_INVALID_PARAMETER);
2245	Assert(pVM->hwaccm.s.svm.fSupported);
2246
2247	pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
2248	AssertMsgReturn(pVMCB, ("Invalid pVMCB\n"), VERR_EM_INTERNAL_ERROR);
2249
2250	/*
2251	* Only allow 32 & 64 bits code.
2252	*/
2253	DISCPUMODE enmMode = SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid);
2254	if (enmMode != CPUMODE_16BIT)
2255	{
2256	RTGCPTR pbCode;
2257	int rc = SELMValidateAndConvertCSAddr(pVM, pCtx->eflags, pCtx->ss, pCtx->cs, &pCtx->csHid, (RTGCPTR)pCtx->rip, &pbCode);
2258	if (VBOX_SUCCESS(rc))
2259	{
2260	uint32_t cbOp;
2261	DISCPUSTATE Cpu;
2262	OP_PARAMVAL param1;
2263	RTGCPTR addr;
2264
2265	Cpu.mode = enmMode;
2266	rc = EMInterpretDisasOneEx(pVM, pbCode, CPUMCTX2CORE(pCtx), &Cpu, &cbOp);
2267	AssertRCReturn(rc, rc);
2268	Assert(cbOp == Cpu.opsize);
2269
2270	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), &Cpu, &Cpu.param1, &param1, PARAM_SOURCE);
2271	AssertRCReturn(rc, VERR_EM_INTERPRETER);
2272
2273	switch(param1.type)
2274	{
2275	case PARMTYPE_IMMEDIATE:
2276	case PARMTYPE_ADDRESS:
2277	AssertReturn((param1.flags & (PARAM_VAL32\|PARAM_VAL64)), VERR_EM_INTERPRETER);
2278
2279	addr = param1.val.val64;
2280	break;
2281
2282	default:
2283	AssertFailed();
2284	return VERR_EM_INTERPRETER;
2285	}
2286
2287	/* Manually invalidate the page for the VM's TLB. */
2288	Log(("SVMR0InvalidatePhysPage Phys=%VGp Virt=%VGv ASID=%d\n", GCPhys, addr, pVMCB->ctrl.TLBCtrl.n.u32ASID));
2289	SVMInvlpgA(addr, pVMCB->ctrl.TLBCtrl.n.u32ASID);
2290	STAM_COUNTER_INC(&pVM->hwaccm.s.StatFlushPhysPageManual);
2291
2292	return VINF_SUCCESS;
2293	}
2294	}
2295	AssertFailed();
2296	return VERR_EM_INTERPRETER;
2297	}
2298	return VINF_SUCCESS;
2299	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp@ 12983

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