HWACCMR0.cpp@ 38845

Last change on this file since 38845 was 38684, checked in by vboxsync, 13 years ago
HM: some file headers
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1	/* $Id: HWACCMR0.cpp 38684 2011-09-08 08:36:48Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HWACCM
23	#include <VBox/vmm/hwaccm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HWACCMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hwacc_vmx.h>
28	#include <VBox/vmm/hwacc_svm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HWVMXR0.h"
44	#include "HWSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBLCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
93	DECLR0CALLBACKMEMBER(int, pfnEnableCpu,(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
94	DECLR0CALLBACKMEMBER(int, pfnDisableCpu,(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
95	DECLR0CALLBACKMEMBER(int, pfnInitVM,(PVM pVM));
96	DECLR0CALLBACKMEMBER(int, pfnTermVM,(PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnSetupVM,(PVM pVM));
98	/** @} */
99
100	/** Maximum ASID allowed. */
101	uint32_t uMaxASID;
102
103	/** VT-x data. */
104	struct
105	{
106	/** Set to by us to indicate VMX is supported by the CPU. */
107	bool fSupported;
108	/** Whether we're using SUPR0EnableVTx or not. */
109	bool fUsingSUPR0EnableVTx;
110	/** Whether we're using the preemption timer or not. */
111	bool fUsePreemptTimer;
112	/** The shift mask employed by the VMX-Preemption timer. */
113	uint8_t cPreemptTimerShift;
114
115	/** Host CR4 value (set by ring-0 VMX init) */
116	uint64_t hostCR4;
117
118	/** Host EFER value (set by ring-0 VMX init) */
119	uint64_t hostEFER;
120
121	/** VMX MSR values */
122	struct
123	{
124	uint64_t feature_ctrl;
125	uint64_t vmx_basic_info;
126	VMX_CAPABILITY vmx_pin_ctls;
127	VMX_CAPABILITY vmx_proc_ctls;
128	VMX_CAPABILITY vmx_proc_ctls2;
129	VMX_CAPABILITY vmx_exit;
130	VMX_CAPABILITY vmx_entry;
131	uint64_t vmx_misc;
132	uint64_t vmx_cr0_fixed0;
133	uint64_t vmx_cr0_fixed1;
134	uint64_t vmx_cr4_fixed0;
135	uint64_t vmx_cr4_fixed1;
136	uint64_t vmx_vmcs_enum;
137	uint64_t vmx_eptcaps;
138	} msr;
139	/* Last instruction error */
140	uint32_t ulLastInstrError;
141	} vmx;
142
143	/** AMD-V information. */
144	struct
145	{
146	/* HWCR msr (for diagnostics) */
147	uint64_t msrHWCR;
148
149	/** SVM revision. */
150	uint32_t u32Rev;
151
152	/** SVM feature bits from cpuid 0x8000000a */
153	uint32_t u32Features;
154
155	/** Set by us to indicate SVM is supported by the CPU. */
156	bool fSupported;
157	} svm;
158	/** Saved error from detection */
159	int32_t lLastError;
160
161	struct
162	{
163	uint32_t u32AMDFeatureECX;
164	uint32_t u32AMDFeatureEDX;
165	} cpuid;
166
167	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
168	* enabled and disabled each time it's used to execute guest code. */
169	bool fGlobalInit;
170	/** Indicates whether the host is suspending or not. We'll refuse a few
171	* actions when the host is being suspended to speed up the suspending and
172	* avoid trouble. */
173	volatile bool fSuspended;
174
175	/** Whether we've already initialized all CPUs.
176	* @remarks We could check the EnableAllCpusOnce state, but this is
177	* simpler and hopefully easier to understand. */
178	bool fEnabled;
179	/** Serialize initialization in HWACCMR0EnableAllCpus. */
180	RTONCE EnableAllCpusOnce;
181	} g_HvmR0;
182
183
184
185	/**
186	* Initializes a first return code structure.
187	*
188	* @param pFirstRc The structure to init.
189	*/
190	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
191	{
192	pFirstRc->rc = VINF_SUCCESS;
193	pFirstRc->idCpu = NIL_RTCPUID;
194	}
195
196
197	/**
198	* Try se the status code (success ignored).
199	*
200	* @param pFirstRc The first return code structure.
201	* @param rc The status code.
202	*/
203	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
204	{
205	if ( RT_FAILURE(rc)
206	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
207	pFirstRc->idCpu = RTMpCpuId();
208	}
209
210
211	/**
212	* Get the status code of a first return code structure.
213	*
214	* @returns The status code; VINF_SUCCESS or error status, no informational or
215	* warning errors.
216	* @param pFirstRc The first return code structure.
217	*/
218	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
219	{
220	return pFirstRc->rc;
221	}
222
223
224	/**
225	* Get the CPU ID on which the failure status code was reported.
226	*
227	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
228	* @param pFirstRc The first return code structure.
229	*/
230	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
231	{
232	return pFirstRc->idCpu;
233	}
234
235
236	/** @name Dummy callback handlers.
237	* @{ */
238
239	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu)
240	{
241	return VINF_SUCCESS;
242	}
243
244	static DECLCALLBACK(int) hmR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
245	{
246	return VINF_SUCCESS;
247	}
248
249	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
250	{
251	return VINF_SUCCESS;
252	}
253
254	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
255	{
256	return VINF_SUCCESS;
257	}
258
259	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
260	{
261	return VINF_SUCCESS;
262	}
263
264	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
265	{
266	return VINF_SUCCESS;
267	}
268
269	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
270	{
271	return VINF_SUCCESS;
272	}
273
274	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
275	{
276	return VINF_SUCCESS;
277	}
278
279	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
280	{
281	return VINF_SUCCESS;
282	}
283
284	static DECLCALLBACK(int) hmR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
285	{
286	return VINF_SUCCESS;
287	}
288
289	/** @} */
290
291
292	/**
293	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
294	* Down at the Rate Specified" erratum.
295	*
296	* Errata names and related steppings:
297	* - BA86 - D0.
298	* - AAX65 - C2.
299	* - AAU65 - C2, K0.
300	* - AAO95 - B1.
301	* - AAT59 - C2.
302	* - AAK139 - D0.
303	* - AAM126 - C0, C1, D0.
304	* - AAN92 - B1.
305	* - AAJ124 - C0, D0.
306	*
307	* - AAP86 - B1.
308	*
309	* Steppings: B1, C0, C1, C2, D0, K0.
310	*
311	* @returns true if subject to it, false if not.
312	*/
313	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
314	{
315	uint32_t u = ASMCpuId_EAX(1);
316	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
317	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
318	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
319	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
320	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
321	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
322	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
323	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
324	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
325	\|\| u == UINT32_C(0x000106A0) /?321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification /
326	\|\| u == UINT32_C(0x000106A1) /?321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification /
327	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
328	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
329	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
330	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
331	)
332	return true;
333	return false;
334	}
335
336
337	/**
338	* Intel specific initialization code.
339	*
340	* @returns VBox status code (will only fail if out of memory).
341	*/
342	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
343	{
344	/*
345	* Check that all the required VT-x features are present.
346	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
347	*/
348	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
349	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
350	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
351	)
352	{
353	/** @todo move this into a separate function. */
354	g_HvmR0.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
355
356	/*
357	* First try use native kernel API for controlling VT-x.
358	* (This is only supported by some Mac OS X kernels atm.)
359	*/
360	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
361	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
362	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
363	{
364	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
365	if (RT_SUCCESS(rc))
366	{
367	g_HvmR0.vmx.fSupported = true;
368	rc = SUPR0EnableVTx(false /* fEnable */);
369	AssertRC(rc);
370	}
371	}
372	else
373	{
374	/* We need to check if VT-x has been properly initialized on all
375	CPUs. Some BIOSes do a lousy job. */
376	HMR0FIRSTRC FirstRc;
377	hmR0FirstRcInit(&FirstRc);
378	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
379	if (RT_SUCCESS(g_HvmR0.lLastError))
380	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
381	}
382	if (RT_SUCCESS(g_HvmR0.lLastError))
383	{
384	/* Reread in case we've changed it. */
385	g_HvmR0.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
386
387	if ( (g_HvmR0.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
388	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
389	{
390	/*
391	* Read all relevant MSR.
392	*/
393	g_HvmR0.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
394	g_HvmR0.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
395	g_HvmR0.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
396	g_HvmR0.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
397	g_HvmR0.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
398	g_HvmR0.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
399	g_HvmR0.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
400	g_HvmR0.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
401	g_HvmR0.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
402	g_HvmR0.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
403	g_HvmR0.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
404	g_HvmR0.vmx.hostCR4 = ASMGetCR4();
405	g_HvmR0.vmx.hostEFER = ASMRdMsr(MSR_K6_EFER);
406	/* VPID 16 bits ASID. */
407	g_HvmR0.uMaxASID = 0x10000; /* exclusive */
408
409	if (g_HvmR0.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
410	{
411	g_HvmR0.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
412	if ( g_HvmR0.vmx.msr.vmx_proc_ctls2.n.allowed1
413	& (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
414	g_HvmR0.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
415	}
416
417	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
418	{
419	/*
420	* Enter root mode
421	*/
422	RTR0MEMOBJ hScatchMemObj;
423	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, true /* executable R0 mapping */);
424	if (RT_FAILURE(rc))
425	return rc;
426
427	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
428	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
429	ASMMemZeroPage(pvScatchPage);
430
431	/* Set revision dword at the beginning of the structure. */
432	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.msr.vmx_basic_info);
433
434	/* Make sure we don't get rescheduled to another cpu during this probe. */
435	RTCCUINTREG fFlags = ASMIntDisableFlags();
436
437	/*
438	* Check CR4.VMXE
439	*/
440	g_HvmR0.vmx.hostCR4 = ASMGetCR4();
441	if (!(g_HvmR0.vmx.hostCR4 & X86_CR4_VMXE))
442	{
443	/* In theory this bit could be cleared behind our back. Which would cause
444	#UD faults when we try to execute the VMX instructions... */
445	ASMSetCR4(g_HvmR0.vmx.hostCR4 \| X86_CR4_VMXE);
446	}
447
448	/* Enter VMX Root Mode */
449	rc = VMXEnable(HCPhysScratchPage);
450	if (RT_SUCCESS(rc))
451	{
452	g_HvmR0.vmx.fSupported = true;
453	VMXDisable();
454
455	/*
456	* Check for the VMX-Preemption Timer and adjust for the * "VMX-Preemption
457	* Timer Does Not Count Down at the Rate Specified" erratum.
458	*/
459	if ( g_HvmR0.vmx.msr.vmx_pin_ctls.n.allowed1
460	& VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
461	{
462	g_HvmR0.vmx.fUsePreemptTimer = true;
463	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.msr.vmx_misc);
464	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
465	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
466	}
467	}
468	else
469	{
470	/*
471	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
472	* it will crash the host when we enter raw mode, because:
473	*
474	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
475	* this bit), and
476	* (b) turning off paging causes a #GP (unavoidable when switching
477	* from long to 32 bits mode or 32 bits to PAE).
478	*
479	* They should fix their code, but until they do we simply refuse to run.
480	*/
481	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
482	}
483
484	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
485	if it wasn't so before (some software could incorrectly
486	think it's in VMX mode). */
487	ASMSetCR4(g_HvmR0.vmx.hostCR4);
488	ASMSetFlags(fFlags);
489
490	RTR0MemObjFree(hScatchMemObj, false);
491	}
492	}
493	else
494	{
495	AssertFailed(); /* can't hit this case anymore */
496	g_HvmR0.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
497	}
498
499	/*
500	* Install the VT-x methods.
501	*/
502	if (g_HvmR0.vmx.fSupported)
503	{
504	g_HvmR0.pfnEnterSession = VMXR0Enter;
505	g_HvmR0.pfnLeaveSession = VMXR0Leave;
506	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
507	g_HvmR0.pfnLoadGuestState = VMXR0LoadGuestState;
508	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
509	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
510	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
511	g_HvmR0.pfnInitVM = VMXR0InitVM;
512	g_HvmR0.pfnTermVM = VMXR0TermVM;
513	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
514	}
515	}
516	#ifdef LOG_ENABLED
517	else
518	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
519	#endif
520	}
521	else
522	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
523	return VINF_SUCCESS;
524	}
525
526
527	/**
528	* AMD specific initialization code.
529	*/
530	static void hmR0InitAmd(uint32_t u32FeaturesEDX)
531	{
532	/*
533	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
534	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
535	*/
536	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
537	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
538	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
539	)
540	{
541	g_HvmR0.pfnEnterSession = SVMR0Enter;
542	g_HvmR0.pfnLeaveSession = SVMR0Leave;
543	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
544	g_HvmR0.pfnLoadGuestState = SVMR0LoadGuestState;
545	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
546	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
547	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
548	g_HvmR0.pfnInitVM = SVMR0InitVM;
549	g_HvmR0.pfnTermVM = SVMR0TermVM;
550	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
551
552	/* Query AMD features. */
553	uint32_t u32Dummy;
554	ASMCpuId(0x8000000A, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxASID,
555	&u32Dummy, &g_HvmR0.svm.u32Features);
556
557	/*
558	* We need to check if AMD-V has been properly initialized on all CPUs.
559	* Some BIOSes might do a poor job.
560	*/
561	HMR0FIRSTRC FirstRc;
562	hmR0FirstRcInit(&FirstRc);
563	int rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
564	AssertRC(rc);
565	if (RT_SUCCESS(rc))
566	rc = hmR0FirstRcGetStatus(&FirstRc);
567	#ifndef DEBUG_bird
568	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
569	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
570	#endif
571	if (RT_SUCCESS(rc))
572	{
573	/* Read the HWCR msr for diagnostics. */
574	g_HvmR0.svm.msrHWCR = ASMRdMsr(MSR_K8_HWCR);
575	g_HvmR0.svm.fSupported = true;
576	}
577	else
578	g_HvmR0.lLastError = rc;
579	}
580	else
581	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
582	}
583
584
585	/**
586	* Does global Ring-0 HM initialization (at module init).
587	*
588	* @returns VBox status code.
589	*/
590	VMMR0DECL(int) HWACCMR0Init(void)
591	{
592	/*
593	* Initialize the globals.
594	*/
595	g_HvmR0.fEnabled = false;
596	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
597	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
598	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
599	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
600
601	/* Fill in all callbacks with placeholders. */
602	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
603	g_HvmR0.pfnLeaveSession = hmR0DummyLeave;
604	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
605	g_HvmR0.pfnLoadGuestState = hmR0DummyLoadGuestState;
606	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
607	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
608	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
609	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
610	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
611	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
612
613	/* Default is global VT-x/AMD-V init */
614	g_HvmR0.fGlobalInit = true;
615
616	/*
617	* Make sure aCpuInfo is big enough for all the CPUs on this system.
618	*/
619	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
620	{
621	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
622	return VERR_TOO_MANY_CPUS;
623	}
624
625	/*
626	* Check for VT-x and AMD-V capabilities
627	*/
628	int rc;
629	if (ASMHasCpuId())
630	{
631	uint32_t u32FeaturesECX, u32FeaturesEDX;
632	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
633	uint32_t u32Dummy;
634
635	/* Standard features. */
636	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
637	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
638
639	/* Query AMD features. */
640	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
641	&g_HvmR0.cpuid.u32AMDFeatureECX,
642	&g_HvmR0.cpuid.u32AMDFeatureEDX);
643
644	/* Go to CPU specific initialization code. */
645	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
646	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
647	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX)
648	{
649	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
650	if (RT_FAILURE(rc))
651	return rc;
652	}
653	else if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
654	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
655	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX)
656	hmR0InitAmd(u32FeaturesEDX);
657	else
658	g_HvmR0.lLastError = VERR_HWACCM_UNKNOWN_CPU;
659	}
660	else
661	g_HvmR0.lLastError = VERR_HWACCM_NO_CPUID;
662
663	/*
664	* Register notification callbacks that we can use to disable/enable CPUs
665	* when brought offline/online or suspending/resuming.
666	*/
667	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
668	{
669	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
670	AssertRC(rc);
671
672	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
673	AssertRC(rc);
674	}
675
676	/* We return success here because module init shall not fail if HM
677	fails to initialize. */
678	return VINF_SUCCESS;
679	}
680
681
682	/**
683	* Does global Ring-0 HM termination (at module termination).
684	*
685	* @returns VBox status code.
686	*/
687	VMMR0DECL(int) HWACCMR0Term(void)
688	{
689	int rc;
690	if ( g_HvmR0.vmx.fSupported
691	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
692	{
693	/*
694	* Simple if the host OS manages VT-x.
695	*/
696	Assert(g_HvmR0.fGlobalInit);
697	rc = SUPR0EnableVTx(false /* fEnable */);
698
699	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
700	{
701	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
702	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
703	}
704	}
705	else
706	{
707	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
708	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
709	{
710	/* Doesn't really matter if this fails. */
711	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
712	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
713	}
714	else
715	rc = VINF_SUCCESS;
716
717	/*
718	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
719	*/
720	if (g_HvmR0.fGlobalInit)
721	{
722	HMR0FIRSTRC FirstRc;
723	hmR0FirstRcInit(&FirstRc);
724	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL, &FirstRc);
725	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
726	if (RT_SUCCESS(rc))
727	{
728	rc = hmR0FirstRcGetStatus(&FirstRc);
729	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
730	}
731	}
732
733	/*
734	* Free the per-cpu pages used for VT-x and AMD-V.
735	*/
736	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
737	{
738	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
739	{
740	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
741	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
742	}
743	}
744	}
745	return rc;
746	}
747
748
749	/**
750	* Worker function used by hmR0PowerCallback and HWACCMR0Init to initalize
751	* VT-x on a CPU.
752	*
753	* @param idCpu The identifier for the CPU the function is called on.
754	* @param pvUser1 Pointer to the first RC structure.
755	* @param pvUser2 Ignored.
756	*/
757	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
758	{
759	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
760	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
761	NOREF(pvUser2);
762
763	/*
764	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
765	* Once the lock bit is set, this MSR can no longer be modified.
766	*/
767	uint64_t fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
768	if ( !(fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
769	\|\| ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
770	== MSR_IA32_FEATURE_CONTROL_VMXON ) /* Some BIOSes forget to set the locked bit. */
771	)
772	{
773	/* MSR is not yet locked; we can change it ourselves here */
774	ASMWrMsr(MSR_IA32_FEATURE_CONTROL,
775	g_HvmR0.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
776	fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
777	}
778
779	int rc;
780	if ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
781	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
782	rc = VINF_SUCCESS;
783	else
784	rc = VERR_VMX_MSR_LOCKED_OR_DISABLED;
785
786	hmR0FirstRcSetStatus(pFirstRc, rc);
787	}
788
789
790	/**
791	* Worker function used by hmR0PowerCallback and HWACCMR0Init to initalize
792	* VT-x / AMD-V on a CPU.
793	*
794	* @param idCpu The identifier for the CPU the function is called on.
795	* @param pvUser1 Pointer to the first RC structure.
796	* @param pvUser2 Ignored.
797	*/
798	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
799	{
800	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
801	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
802	NOREF(pvUser2);
803
804	/* Check if SVM is disabled. */
805	int rc;
806	uint64_t fVmCr = ASMRdMsr(MSR_K8_VM_CR);
807	if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
808	{
809	/* Turn on SVM in the EFER MSR. */
810	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
811	if (fEfer & MSR_K6_EFER_SVME)
812	rc = VERR_SVM_IN_USE;
813	else
814	{
815	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
816
817	/* Paranoia. */
818	fEfer = ASMRdMsr(MSR_K6_EFER);
819	if (fEfer & MSR_K6_EFER_SVME)
820	{
821	/* Restore previous value. */
822	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
823	rc = VINF_SUCCESS;
824	}
825	else
826	rc = VERR_SVM_ILLEGAL_EFER_MSR;
827	}
828	}
829	else
830	rc = VERR_SVM_DISABLED;
831
832	hmR0FirstRcSetStatus(pFirstRc, rc);
833	}
834
835
836
837	/**
838	* Disable VT-x or AMD-V on the current CPU
839	*
840	* @returns VBox status code.
841	* @param pVM VM handle (can be 0!)
842	* @param idCpu The identifier for the CPU the function is called on.
843	*/
844	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
845	{
846	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
847
848	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
849	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
850	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
851	Assert(!pCpu->fConfigured);
852	Assert(!g_HvmR0.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
853
854	pCpu->idCpu = idCpu;
855
856	/* Make sure we start with a clean TLB. */
857	pCpu->fFlushTLB = true;
858
859	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
860	pCpu->cTLBFlushes = 0;
861
862	/* Should never happen */
863	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
864	{
865	AssertLogRelMsgFailed(("hmR0EnableCpu failed idCpu=%u.\n", idCpu));
866	return VERR_INTERNAL_ERROR;
867	}
868
869	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
870	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
871
872	int rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage);
873	AssertRC(rc);
874	if (RT_SUCCESS(rc))
875	pCpu->fConfigured = true;
876
877	return rc;
878	}
879
880
881	/**
882	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
883	* is to be called on the target cpus.
884	*
885	* @param idCpu The identifier for the CPU the function is called on.
886	* @param pvUser1 The 1st user argument.
887	* @param pvUser2 The 2nd user argument.
888	*/
889	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
890	{
891	PVM pVM = (PVM)pvUser1; /* can be NULL! */
892	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
893	AssertReturnVoid(g_HvmR0.fGlobalInit);
894	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
895	}
896
897
898	/**
899	* RTOnce callback employed by HWACCMR0EnableAllCpus.
900	*
901	* @returns VBox status code
902	* @param pvUser The VM handle.
903	* @param pvUserIgnore NULL, ignored.
904	*/
905	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void pvUser, void pvUserIgnore)
906	{
907	PVM pVM = (PVM)pvUser;
908	NOREF(pvUserIgnore);
909
910	/*
911	* Indicate that we've initialized.
912	*
913	* Note! There is a potential race between this function and the suspend
914	* notification. Kind of unlikely though, so ignored for now.
915	*/
916	AssertReturn(!g_HvmR0.fEnabled, VERR_INTERNAL_ERROR_3);
917	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
918
919	/*
920	* The global init variable is set by the first VM.
921	*/
922	g_HvmR0.fGlobalInit = pVM->hwaccm.s.fGlobalInit;
923
924	int rc;
925	if ( g_HvmR0.vmx.fSupported
926	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
927	{
928	/*
929	* Global VT-x initialization API (only darwin for now).
930	*/
931	rc = SUPR0EnableVTx(true /* fEnable */);
932	if (RT_SUCCESS(rc))
933	{
934	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
935	{
936	g_HvmR0.aCpuInfo[iCpu].fConfigured = true;
937	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
938	}
939
940	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
941	g_HvmR0.fGlobalInit = pVM->hwaccm.s.fGlobalInit = true;
942	}
943	else
944	AssertMsgFailed(("HWACCMR0EnableAllCpus/SUPR0EnableVTx: rc=%Rrc\n", rc));
945	}
946	else
947	{
948	/*
949	* We're doing the job ourselves.
950	*/
951	/* Allocate one page per cpu for the global vt-x and amd-v pages */
952	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
953	{
954	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
955
956	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
957	{
958	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
959	AssertLogRelRCReturn(rc, rc);
960
961	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
962	ASMMemZeroPage(pvR0);
963	}
964	g_HvmR0.aCpuInfo[i].fConfigured = false;
965	}
966
967	if (g_HvmR0.fGlobalInit)
968	{
969	/* First time, so initialize each cpu/core. */
970	HMR0FIRSTRC FirstRc;
971	hmR0FirstRcInit(&FirstRc);
972	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
973	if (RT_SUCCESS(rc))
974	rc = hmR0FirstRcGetStatus(&FirstRc);
975	AssertMsgRC(rc, ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
976	}
977	else
978	rc = VINF_SUCCESS;
979	}
980
981	return rc;
982	}
983
984
985	/**
986	* Sets up HWACCM on all cpus.
987	*
988	* @returns VBox status code.
989	* @param pVM The VM handle.
990	*/
991	VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM)
992	{
993	/* Make sure we don't touch hwaccm after we've disabled hwaccm in
994	preparation of a suspend. */
995	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
996	return VERR_HWACCM_SUSPEND_PENDING;
997
998	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM, NULL);
999	}
1000
1001
1002	/**
1003	* Disable VT-x or AMD-V on the current CPU
1004	*
1005	* @returns VBox status code.
1006	* @param idCpu The identifier for the CPU the function is called on.
1007	*/
1008	static int hmR0DisableCpu(RTCPUID idCpu)
1009	{
1010	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1011
1012	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1013	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
1014	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1015	Assert(!g_HvmR0.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
1016	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1017
1018	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1019	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1020
1021	int rc;
1022	if (pCpu->fConfigured)
1023	{
1024	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1025	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1026	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1027	AssertRC(rc);
1028	pCpu->fConfigured = false;
1029	}
1030	else
1031	rc = VINF_SUCCESS; /* nothing to do */
1032
1033	pCpu->uCurrentASID = 0;
1034	return rc;
1035	}
1036
1037
1038	/**
1039	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
1040	* is to be called on the target cpus.
1041	*
1042	* @param idCpu The identifier for the CPU the function is called on.
1043	* @param pvUser1 The 1st user argument.
1044	* @param pvUser2 The 2nd user argument.
1045	*/
1046	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1047	{
1048	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
1049	AssertReturnVoid(g_HvmR0.fGlobalInit);
1050	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1051	}
1052
1053
1054	/**
1055	* Callback function invoked when a cpu goes online or offline.
1056	*
1057	* @param enmEvent The Mp event.
1058	* @param idCpu The identifier for the CPU the function is called on.
1059	* @param pvData Opaque data (PVM pointer).
1060	*/
1061	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1062	{
1063	/*
1064	* We only care about uninitializing a CPU that is going offline. When a
1065	* CPU comes online, the initialization is done lazily in HWACCMR0Enter().
1066	*/
1067	AssertRelease(idCpu == RTMpCpuId());
1068	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1069	switch (enmEvent)
1070	{
1071	case RTMPEVENT_OFFLINE:
1072	{
1073	int rc = hmR0DisableCpu(idCpu);
1074	AssertRC(rc);
1075	break;
1076	}
1077
1078	default:
1079	break;
1080	}
1081	}
1082
1083
1084	/**
1085	* Called whenever a system power state change occurs.
1086	*
1087	* @param enmEvent Power event
1088	* @param pvUser User argument
1089	*/
1090	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1091	{
1092	NOREF(pvUser);
1093	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1094
1095	#ifdef LOG_ENABLED
1096	if (enmEvent == RTPOWEREVENT_SUSPEND)
1097	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1098	else
1099	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1100	#endif
1101
1102	if (enmEvent == RTPOWEREVENT_SUSPEND)
1103	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1104
1105	if (g_HvmR0.fEnabled)
1106	{
1107	int rc;
1108	HMR0FIRSTRC FirstRc;
1109	hmR0FirstRcInit(&FirstRc);
1110
1111	if (enmEvent == RTPOWEREVENT_SUSPEND)
1112	{
1113	if (g_HvmR0.fGlobalInit)
1114	{
1115	/* Turn off VT-x or AMD-V on all CPUs. */
1116	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL, &FirstRc);
1117	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1118	}
1119	/* else nothing to do here for the local init case */
1120	}
1121	else
1122	{
1123	/* Reinit the CPUs from scratch as the suspend state might have
1124	messed with the MSRs. (lousy BIOSes as usual) */
1125	if (g_HvmR0.vmx.fSupported)
1126	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1127	else
1128	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1129	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1130	if (RT_SUCCESS(rc))
1131	rc = hmR0FirstRcGetStatus(&FirstRc);
1132	#ifdef LOG_ENABLED
1133	if (RT_FAILURE(rc))
1134	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1135	#endif
1136	if (g_HvmR0.fGlobalInit)
1137	{
1138	/* Turn VT-x or AMD-V back on on all CPUs. */
1139	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL, &FirstRc /* output ignored */);
1140	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1141	}
1142	/* else nothing to do here for the local init case */
1143	}
1144	}
1145
1146	if (enmEvent == RTPOWEREVENT_RESUME)
1147	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1148	}
1149
1150
1151	/**
1152	* Does Ring-0 per VM HM initialization.
1153	*
1154	* This will copy HM global into the VM structure and call the CPU specific
1155	* init routine which will allocate resources for each virtual CPU and such.
1156	*
1157	* @returns VBox status code.
1158	* @param pVM The VM to operate on.
1159	*/
1160	VMMR0DECL(int) HWACCMR0InitVM(PVM pVM)
1161	{
1162	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1163
1164	#ifdef LOG_ENABLED
1165	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
1166	#endif
1167
1168	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
1169	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1170	return VERR_HWACCM_SUSPEND_PENDING;
1171
1172	/*
1173	* Copy globals to the VM structure.
1174	*/
1175	pVM->hwaccm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1176	pVM->hwaccm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1177
1178	pVM->hwaccm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer;
1179	pVM->hwaccm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1180	pVM->hwaccm.s.vmx.msr.feature_ctrl = g_HvmR0.vmx.msr.feature_ctrl;
1181	pVM->hwaccm.s.vmx.hostCR4 = g_HvmR0.vmx.hostCR4;
1182	pVM->hwaccm.s.vmx.hostEFER = g_HvmR0.vmx.hostEFER;
1183	pVM->hwaccm.s.vmx.msr.vmx_basic_info = g_HvmR0.vmx.msr.vmx_basic_info;
1184	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = g_HvmR0.vmx.msr.vmx_pin_ctls;
1185	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = g_HvmR0.vmx.msr.vmx_proc_ctls;
1186	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = g_HvmR0.vmx.msr.vmx_proc_ctls2;
1187	pVM->hwaccm.s.vmx.msr.vmx_exit = g_HvmR0.vmx.msr.vmx_exit;
1188	pVM->hwaccm.s.vmx.msr.vmx_entry = g_HvmR0.vmx.msr.vmx_entry;
1189	pVM->hwaccm.s.vmx.msr.vmx_misc = g_HvmR0.vmx.msr.vmx_misc;
1190	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = g_HvmR0.vmx.msr.vmx_cr0_fixed0;
1191	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = g_HvmR0.vmx.msr.vmx_cr0_fixed1;
1192	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = g_HvmR0.vmx.msr.vmx_cr4_fixed0;
1193	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = g_HvmR0.vmx.msr.vmx_cr4_fixed1;
1194	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = g_HvmR0.vmx.msr.vmx_vmcs_enum;
1195	pVM->hwaccm.s.vmx.msr.vmx_eptcaps = g_HvmR0.vmx.msr.vmx_eptcaps;
1196	pVM->hwaccm.s.svm.msrHWCR = g_HvmR0.svm.msrHWCR;
1197	pVM->hwaccm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1198	pVM->hwaccm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1199	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1200	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1201	pVM->hwaccm.s.lLastError = g_HvmR0.lLastError;
1202
1203	pVM->hwaccm.s.uMaxASID = g_HvmR0.uMaxASID;
1204
1205
1206	if (!pVM->hwaccm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1207	{
1208	pVM->hwaccm.s.cMaxResumeLoops = 1024;
1209	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1210	if (RTThreadPreemptIsPendingTrusty())
1211	pVM->hwaccm.s.cMaxResumeLoops = 8192;
1212	#endif
1213	}
1214
1215	/*
1216	* Initialize some per CPU fields.
1217	*/
1218	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1219	{
1220	PVMCPU pVCpu = &pVM->aCpus[i];
1221
1222	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1223
1224	/* Invalidate the last cpu we were running on. */
1225	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
1226
1227	/* we'll aways increment this the first time (host uses ASID 0) */
1228	pVCpu->hwaccm.s.uCurrentASID = 0;
1229	}
1230
1231	/*
1232	* Call the hardware specific initialization method.
1233	*
1234	* Note! The fInUse handling here isn't correct as we can we can be
1235	* rescheduled to a different cpu, but the fInUse case is mostly for
1236	* debugging... Disabling preemption isn't an option when allocating
1237	* memory, so we'll let it slip for now.
1238	*/
1239	RTCCUINTREG fFlags = ASMIntDisableFlags();
1240	PHMGLOBLCPUINFO pCpu = HWACCMR0GetCurrentCpu();
1241	ASMAtomicWriteBool(&pCpu->fInUse, true);
1242	ASMSetFlags(fFlags);
1243
1244	int rc = g_HvmR0.pfnInitVM(pVM);
1245
1246	ASMAtomicWriteBool(&pCpu->fInUse, false);
1247	return rc;
1248	}
1249
1250
1251	/**
1252	* Does Ring-0 per VM HM termination.
1253	*
1254	* @returns VBox status code.
1255	* @param pVM The VM to operate on.
1256	*/
1257	VMMR0DECL(int) HWACCMR0TermVM(PVM pVM)
1258	{
1259	Log(("HWACCMR0TermVM: %p\n", pVM));
1260	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1261
1262	/* Make sure we don't touch hm after we've disabled hwaccm in preparation
1263	of a suspend. */
1264	/** @todo r=bird: This cannot be right, the termination functions are
1265	* just freeing memory and resetting pVM/pVCpu members...
1266	* ==> memory leak. */
1267	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1268
1269	/*
1270	* Call the hardware specific method.
1271	*
1272	* Note! Not correct as we can be rescheduled to a different cpu, but the
1273	* fInUse case is mostly for debugging.
1274	*/
1275	RTCCUINTREG fFlags = ASMIntDisableFlags();
1276	PHMGLOBLCPUINFO pCpu = HWACCMR0GetCurrentCpu();
1277	ASMAtomicWriteBool(&pCpu->fInUse, true);
1278	ASMSetFlags(fFlags);
1279
1280	int rc = g_HvmR0.pfnTermVM(pVM);
1281
1282	ASMAtomicWriteBool(&pCpu->fInUse, false);
1283	return rc;
1284	}
1285
1286
1287	/**
1288	* Sets up a VT-x or AMD-V session.
1289	*
1290	* This is mostly about setting up the hardware VM state.
1291	*
1292	* @returns VBox status code.
1293	* @param pVM The VM to operate on.
1294	*/
1295	VMMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
1296	{
1297	Log(("HWACCMR0SetupVM: %p\n", pVM));
1298	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1299
1300	/* Make sure we don't touch hwaccm after we've disabled hwaccm in
1301	preparation of a suspend. */
1302	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1303
1304
1305	/*
1306	* Call the hardware specific setup VM method. This requires the CPU to be
1307	* enabled for AMD-V/VT-x and preemption to be prevented.
1308	*/
1309	RTCCUINTREG fFlags = ASMIntDisableFlags();
1310	RTCPUID idCpu = RTMpCpuId();
1311	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1312	ASMAtomicWriteBool(&pCpu->fInUse, true);
1313
1314	/* On first entry we'll sync everything. */
1315	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1316	pVM->aCpus[i].hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1317
1318	/* Enable VT-x or AMD-V if local init is required. */
1319	int rc;
1320	if (!g_HvmR0.fGlobalInit)
1321	{
1322	rc = hmR0EnableCpu(pVM, idCpu);
1323	AssertReturnStmt(RT_SUCCESS_NP(rc), ASMSetFlags(fFlags), rc);
1324	}
1325
1326	/* Setup VT-x or AMD-V. */
1327	rc = g_HvmR0.pfnSetupVM(pVM);
1328
1329	/* Disable VT-x or AMD-V if local init was done before. */
1330	if (!g_HvmR0.fGlobalInit)
1331	{
1332	int rc2 = hmR0DisableCpu(idCpu);
1333	AssertRC(rc2);
1334	}
1335
1336	ASMAtomicWriteBool(&pCpu->fInUse, false);
1337	ASMSetFlags(fFlags);
1338
1339	return rc;
1340	}
1341
1342
1343	/**
1344	* Enters the VT-x or AMD-V session
1345	*
1346	* @returns VBox status code.
1347	* @param pVM The VM to operate on.
1348	* @param pVCpu VMCPU handle.
1349	*
1350	* @remarks This is called with preemption disabled.
1351	*/
1352	VMMR0DECL(int) HWACCMR0Enter(PVM pVM, PVMCPU pVCpu)
1353	{
1354	RTCPUID idCpu = RTMpCpuId();
1355	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1356
1357	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1358	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1359	ASMAtomicWriteBool(&pCpu->fInUse, true);
1360
1361	AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVCpu->hwaccm.s.idEnteredCpu));
1362	pVCpu->hwaccm.s.idEnteredCpu = idCpu;
1363
1364	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1365
1366	/* Always load the guest's FPU/XMM state on-demand. */
1367	CPUMDeactivateGuestFPUState(pVCpu);
1368
1369	/* Always load the guest's debug state on-demand. */
1370	CPUMDeactivateGuestDebugState(pVCpu);
1371
1372	/* Always reload the host context and the guest's CR0 register. (!!!!) */
1373	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
1374
1375	/* Setup the register and mask according to the current execution mode. */
1376	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1377	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
1378	else
1379	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
1380
1381	/* Enable VT-x or AMD-V if local init is required, or enable if it's a
1382	freshly onlined CPU. */
1383	int rc;
1384	if ( !pCpu->fConfigured
1385	\|\| !g_HvmR0.fGlobalInit)
1386	{
1387	rc = hmR0EnableCpu(pVM, idCpu);
1388	AssertRCReturn(rc, rc);
1389	}
1390
1391	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1392	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1393	#endif
1394
1395	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1396	AssertRC(rc);
1397	/* We must save the host context here (VT-x) as we might be rescheduled on
1398	a different cpu after a long jump back to ring 3. */
1399	rc \|= g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1400	AssertRC(rc);
1401	rc \|= g_HvmR0.pfnLoadGuestState(pVM, pVCpu, pCtx);
1402	AssertRC(rc);
1403
1404	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1405	if (fStartedSet)
1406	PGMRZDynMapReleaseAutoSet(pVCpu);
1407	#endif
1408
1409	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1410	and ring-3 calls. */
1411	if (RT_FAILURE(rc))
1412	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1413	return rc;
1414	}
1415
1416
1417	/**
1418	* Leaves the VT-x or AMD-V session
1419	*
1420	* @returns VBox status code.
1421	* @param pVM The VM to operate on.
1422	* @param pVCpu VMCPU handle.
1423	*
1424	* @remarks Called with preemption disabled just like HWACCMR0Enter, our
1425	* counterpart.
1426	*/
1427	VMMR0DECL(int) HWACCMR0Leave(PVM pVM, PVMCPU pVCpu)
1428	{
1429	int rc;
1430	RTCPUID idCpu = RTMpCpuId();
1431	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1432	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1433
1434	/** @todo r=bird: This can't be entirely right? */
1435	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1436
1437	/*
1438	* Save the guest FPU and XMM state if necessary.
1439	*
1440	* Note! It's rather tricky with longjmps done by e.g. Log statements or
1441	* the page fault handler. We must restore the host FPU here to make
1442	* absolutely sure we don't leave the guest FPU state active or trash
1443	* somebody else's FPU state.
1444	*/
1445	if (CPUMIsGuestFPUStateActive(pVCpu))
1446	{
1447	Log2(("CPUMR0SaveGuestFPU\n"));
1448	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1449
1450	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1451	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1452	}
1453
1454	rc = g_HvmR0.pfnLeaveSession(pVM, pVCpu, pCtx);
1455
1456	/* We don't pass on invlpg information to the recompiler for nested paging
1457	guests, so we must make sure the recompiler flushes its TLB the next
1458	time it executes code. */
1459	if ( pVM->hwaccm.s.fNestedPaging
1460	&& CPUMIsGuestInPagedProtectedModeEx(pCtx))
1461	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1462
1463	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1464	and ring-3 calls. */
1465	#ifdef RT_STRICT
1466	if (RT_UNLIKELY( pVCpu->hwaccm.s.idEnteredCpu != idCpu
1467	&& RT_FAILURE(rc)))
1468	{
1469	AssertMsgFailed(("Owner is %d, I'm %d", (int)pVCpu->hwaccm.s.idEnteredCpu, (int)idCpu));
1470	rc = VERR_INTERNAL_ERROR;
1471	}
1472	#endif
1473	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1474
1475	/*
1476	* Disable VT-x or AMD-V if local init was done before.
1477	*/
1478	if (!g_HvmR0.fGlobalInit)
1479	{
1480	rc = hmR0DisableCpu(idCpu);
1481	AssertRC(rc);
1482
1483	/* Reset these to force a TLB flush for the next entry. (-> EXPENSIVE) */
1484	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
1485	pVCpu->hwaccm.s.uCurrentASID = 0;
1486	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1487	}
1488
1489	ASMAtomicWriteBool(&pCpu->fInUse, false);
1490	return rc;
1491	}
1492
1493
1494	/**
1495	* Runs guest code in a hardware accelerated VM.
1496	*
1497	* @returns VBox status code.
1498	* @param pVM The VM to operate on.
1499	* @param pVCpu VMCPUD id.
1500	*
1501	* @remarks Called with preemption disabled and after first having called
1502	* HWACCMR0Enter.
1503	*/
1504	VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1505	{
1506	#ifdef VBOX_STRICT
1507	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1508	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1509	Assert(pCpu->fConfigured);
1510	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1511	Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
1512	#endif
1513
1514	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1515	PGMRZDynMapStartAutoSet(pVCpu);
1516	#endif
1517
1518	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1519
1520	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1521	PGMRZDynMapReleaseAutoSet(pVCpu);
1522	#endif
1523	return rc;
1524	}
1525
1526	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1527
1528	/**
1529	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1530	*
1531	* @returns VBox status code.
1532	* @param pVM VM handle.
1533	* @param pVCpu VMCPU handle.
1534	* @param pCtx CPU context
1535	*/
1536	VMMR0DECL(int) HWACCMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1537	{
1538	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatFpu64SwitchBack);
1539	if (pVM->hwaccm.s.vmx.fSupported)
1540	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1541	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1542	}
1543
1544
1545	/**
1546	* Save guest debug state (64 bits guest mode & 32 bits host only)
1547	*
1548	* @returns VBox status code.
1549	* @param pVM VM handle.
1550	* @param pVCpu VMCPU handle.
1551	* @param pCtx CPU context
1552	*/
1553	VMMR0DECL(int) HWACCMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1554	{
1555	STAM_COUNTER_INC(&pVCpu->hwaccm.s.StatDebug64SwitchBack);
1556	if (pVM->hwaccm.s.vmx.fSupported)
1557	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1558	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1559	}
1560
1561
1562	/**
1563	* Test the 32->64 bits switcher
1564	*
1565	* @returns VBox status code.
1566	* @param pVM VM handle.
1567	*/
1568	VMMR0DECL(int) HWACCMR0TestSwitcher3264(PVM pVM)
1569	{
1570	PVMCPU pVCpu = &pVM->aCpus[0];
1571	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1572	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1573	int rc;
1574
1575	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1576	if (pVM->hwaccm.s.vmx.fSupported)
1577	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1578	else
1579	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1580	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1581
1582	return rc;
1583	}
1584
1585	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1586
1587	/**
1588	* Returns suspend status of the host
1589	*
1590	* @returns Suspend pending or not
1591	*/
1592	VMMR0DECL(bool) HWACCMR0SuspendPending(void)
1593	{
1594	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1595	}
1596
1597
1598	/**
1599	* Returns the cpu structure for the current cpu.
1600	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1601	*
1602	* @returns cpu structure pointer
1603	*/
1604	VMMR0DECL(PHMGLOBLCPUINFO) HWACCMR0GetCurrentCpu(void)
1605	{
1606	RTCPUID idCpu = RTMpCpuId();
1607	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1608	return &g_HvmR0.aCpuInfo[idCpu];
1609	}
1610
1611
1612	/**
1613	* Returns the cpu structure for the current cpu.
1614	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1615	*
1616	* @returns cpu structure pointer
1617	* @param idCpu id of the VCPU
1618	*/
1619	VMMR0DECL(PHMGLOBLCPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu)
1620	{
1621	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1622	return &g_HvmR0.aCpuInfo[idCpu];
1623	}
1624
1625
1626	/**
1627	* Save a pending IO read.
1628	*
1629	* @param pVCpu The VMCPU to operate on.
1630	* @param GCPtrRip Address of IO instruction
1631	* @param GCPtrRipNext Address of the next instruction
1632	* @param uPort Port address
1633	* @param uAndVal And mask for saving the result in eax
1634	* @param cbSize Read size
1635	*/
1636	VMMR0DECL(void) HWACCMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1637	{
1638	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_READ;
1639	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1640	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1641	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1642	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1643	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1644	return;
1645	}
1646
1647
1648	/**
1649	* Save a pending IO write.
1650	*
1651	* @param pVCpu The VMCPU to operate on.
1652	* @param GCPtrRIP Address of IO instruction
1653	* @param uPort Port address
1654	* @param uAndVal And mask for fetching the result from eax
1655	* @param cbSize Read size
1656	*/
1657	VMMR0DECL(void) HWACCMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1658	{
1659	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_WRITE;
1660	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1661	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1662	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1663	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1664	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1665	return;
1666	}
1667
1668
1669	/**
1670	* Raw-mode switcher hook - disable VT-x if it's active and the current
1671	* switcher turns off paging.
1672	*
1673	* @returns VBox status code.
1674	* @param pVM VM handle.
1675	* @param pfVTxDisabled VT-x was disabled or not (out).
1676	*/
1677	VMMR0DECL(int) HWACCMR0EnterSwitcher(PVM pVM, bool *pfVTxDisabled)
1678	{
1679	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1680
1681	*pfVTxDisabled = false;
1682
1683	if ( !g_HvmR0.fEnabled
1684	\|\| !g_HvmR0.vmx.fSupported /* no such issues with AMD-V */
1685	\|\| !g_HvmR0.fGlobalInit /* Local init implies the CPU is currently not in VMX root mode. */)
1686	return VINF_SUCCESS; /* nothing to do */
1687
1688	switch (VMMGetSwitcher(pVM))
1689	{
1690	case VMMSWITCHER_32_TO_32:
1691	case VMMSWITCHER_PAE_TO_PAE:
1692	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1693
1694	case VMMSWITCHER_32_TO_PAE:
1695	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1696	case VMMSWITCHER_AMD64_TO_32:
1697	case VMMSWITCHER_AMD64_TO_PAE:
1698	break; /* unsafe switchers */
1699
1700	default:
1701	AssertFailed();
1702	return VERR_INTERNAL_ERROR;
1703	}
1704
1705	PHMGLOBLCPUINFO pCpu = HWACCMR0GetCurrentCpu();
1706	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_INTERNAL_ERROR);
1707
1708	*pfVTxDisabled = true;
1709	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1710	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1711	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1712	}
1713
1714
1715	/**
1716	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1717	* switcher turned off paging.
1718	*
1719	* @returns VBox status code.
1720	* @param pVM VM handle.
1721	* @param fVTxDisabled VT-x was disabled or not.
1722	*/
1723	VMMR0DECL(int) HWACCMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1724	{
1725	Assert(!(ASMGetFlags() & X86_EFL_IF));
1726
1727	if (!fVTxDisabled)
1728	return VINF_SUCCESS; /* nothing to do */
1729
1730	Assert(g_HvmR0.fEnabled);
1731	Assert(g_HvmR0.vmx.fSupported);
1732	Assert(g_HvmR0.fGlobalInit);
1733
1734	PHMGLOBLCPUINFO pCpu = HWACCMR0GetCurrentCpu();
1735	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_INTERNAL_ERROR);
1736
1737	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1738	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1739	return VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage);
1740	}
1741
1742	#ifdef VBOX_STRICT
1743
1744	/**
1745	* Dumps a descriptor.
1746	*
1747	* @param pDesc Descriptor to dump.
1748	* @param Sel Selector number.
1749	* @param pszMsg Message to prepend the log entry with.
1750	*/
1751	VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1752	{
1753	/*
1754	* Make variable description string.
1755	*/
1756	static struct
1757	{
1758	unsigned cch;
1759	const char *psz;
1760	} const s_aTypes[32] =
1761	{
1762	# define STRENTRY(str) { sizeof(str) - 1, str }
1763
1764	/* system */
1765	# if HC_ARCH_BITS == 64
1766	STRENTRY("Reserved0 "), /* 0x00 */
1767	STRENTRY("Reserved1 "), /* 0x01 */
1768	STRENTRY("LDT "), /* 0x02 */
1769	STRENTRY("Reserved3 "), /* 0x03 */
1770	STRENTRY("Reserved4 "), /* 0x04 */
1771	STRENTRY("Reserved5 "), /* 0x05 */
1772	STRENTRY("Reserved6 "), /* 0x06 */
1773	STRENTRY("Reserved7 "), /* 0x07 */
1774	STRENTRY("Reserved8 "), /* 0x08 */
1775	STRENTRY("TSS64Avail "), /* 0x09 */
1776	STRENTRY("ReservedA "), /* 0x0a */
1777	STRENTRY("TSS64Busy "), /* 0x0b */
1778	STRENTRY("Call64 "), /* 0x0c */
1779	STRENTRY("ReservedD "), /* 0x0d */
1780	STRENTRY("Int64 "), /* 0x0e */
1781	STRENTRY("Trap64 "), /* 0x0f */
1782	# else
1783	STRENTRY("Reserved0 "), /* 0x00 */
1784	STRENTRY("TSS16Avail "), /* 0x01 */
1785	STRENTRY("LDT "), /* 0x02 */
1786	STRENTRY("TSS16Busy "), /* 0x03 */
1787	STRENTRY("Call16 "), /* 0x04 */
1788	STRENTRY("Task "), /* 0x05 */
1789	STRENTRY("Int16 "), /* 0x06 */
1790	STRENTRY("Trap16 "), /* 0x07 */
1791	STRENTRY("Reserved8 "), /* 0x08 */
1792	STRENTRY("TSS32Avail "), /* 0x09 */
1793	STRENTRY("ReservedA "), /* 0x0a */
1794	STRENTRY("TSS32Busy "), /* 0x0b */
1795	STRENTRY("Call32 "), /* 0x0c */
1796	STRENTRY("ReservedD "), /* 0x0d */
1797	STRENTRY("Int32 "), /* 0x0e */
1798	STRENTRY("Trap32 "), /* 0x0f */
1799	# endif
1800	/* non system */
1801	STRENTRY("DataRO "), /* 0x10 */
1802	STRENTRY("DataRO Accessed "), /* 0x11 */
1803	STRENTRY("DataRW "), /* 0x12 */
1804	STRENTRY("DataRW Accessed "), /* 0x13 */
1805	STRENTRY("DataDownRO "), /* 0x14 */
1806	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1807	STRENTRY("DataDownRW "), /* 0x16 */
1808	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1809	STRENTRY("CodeEO "), /* 0x18 */
1810	STRENTRY("CodeEO Accessed "), /* 0x19 */
1811	STRENTRY("CodeER "), /* 0x1a */
1812	STRENTRY("CodeER Accessed "), /* 0x1b */
1813	STRENTRY("CodeConfEO "), /* 0x1c */
1814	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1815	STRENTRY("CodeConfER "), /* 0x1e */
1816	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1817	# undef SYSENTRY
1818	};
1819	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1820	char szMsg[128];
1821	char *psz = &szMsg[0];
1822	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1823	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1824	psz += s_aTypes[i].cch;
1825
1826	if (pDesc->Gen.u1Present)
1827	ADD_STR(psz, "Present ");
1828	else
1829	ADD_STR(psz, "Not-Present ");
1830	# if HC_ARCH_BITS == 64
1831	if (pDesc->Gen.u1Long)
1832	ADD_STR(psz, "64-bit ");
1833	else
1834	ADD_STR(psz, "Comp ");
1835	# else
1836	if (pDesc->Gen.u1Granularity)
1837	ADD_STR(psz, "Page ");
1838	if (pDesc->Gen.u1DefBig)
1839	ADD_STR(psz, "32-bit ");
1840	else
1841	ADD_STR(psz, "16-bit ");
1842	# endif
1843	# undef ADD_STR
1844	*psz = '\0';
1845
1846	/*
1847	* Limit and Base and format the output.
1848	*/
1849	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
1850	if (pDesc->Gen.u1Granularity)
1851	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
1852
1853	# if HC_ARCH_BITS == 64
1854	uint64_t u32Base = X86DESC64_BASE(*pDesc);
1855
1856	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1857	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1858	# else
1859	uint32_t u32Base = X86DESC_BASE(*pDesc);
1860
1861	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1862	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1863	# endif
1864	}
1865
1866
1867	/**
1868	* Formats a full register dump.
1869	*
1870	* @param pVM The VM to operate on.
1871	* @param pVCpu The VMCPU to operate on.
1872	* @param pCtx The context to format.
1873	*/
1874	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1875	{
1876	/*
1877	* Format the flags.
1878	*/
1879	static struct
1880	{
1881	const char pszSet; const char pszClear; uint32_t fFlag;
1882	} aFlags[] =
1883	{
1884	{ "vip",NULL, X86_EFL_VIP },
1885	{ "vif",NULL, X86_EFL_VIF },
1886	{ "ac", NULL, X86_EFL_AC },
1887	{ "vm", NULL, X86_EFL_VM },
1888	{ "rf", NULL, X86_EFL_RF },
1889	{ "nt", NULL, X86_EFL_NT },
1890	{ "ov", "nv", X86_EFL_OF },
1891	{ "dn", "up", X86_EFL_DF },
1892	{ "ei", "di", X86_EFL_IF },
1893	{ "tf", NULL, X86_EFL_TF },
1894	{ "nt", "pl", X86_EFL_SF },
1895	{ "nz", "zr", X86_EFL_ZF },
1896	{ "ac", "na", X86_EFL_AF },
1897	{ "po", "pe", X86_EFL_PF },
1898	{ "cy", "nc", X86_EFL_CF },
1899	};
1900	char szEFlags[80];
1901	char *psz = szEFlags;
1902	uint32_t efl = pCtx->eflags.u32;
1903	for (unsigned i = 0; i < RT_ELEMENTS(aFlags); i++)
1904	{
1905	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
1906	if (pszAdd)
1907	{
1908	strcpy(psz, pszAdd);
1909	psz += strlen(pszAdd);
1910	*psz++ = ' ';
1911	}
1912	}
1913	psz[-1] = '\0';
1914
1915
1916	/*
1917	* Format the registers.
1918	*/
1919	if (CPUMIsGuestIn64BitCode(pVCpu, CPUMCTX2CORE(pCtx)))
1920	{
1921	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1922	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1923	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1924	"r14=%016RX64 r15=%016RX64\n"
1925	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1926	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1927	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1928	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1929	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1930	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1931	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1932	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1933	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1934	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1935	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1936	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1937	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1938	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1939	,
1940	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1941	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1942	pCtx->r14, pCtx->r15,
1943	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1944	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1945	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1946	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1947	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1948	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1949	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1950	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1951	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1952	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1953	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1954	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1955	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1956	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1957	}
1958	else
1959	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1960	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1961	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1962	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1963	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1964	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1965	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1966	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1967	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1968	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1969	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1970	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1971	,
1972	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1973	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1974	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0], pCtx->dr[1],
1975	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2], pCtx->dr[3],
1976	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4], pCtx->dr[5],
1977	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6], pCtx->dr[7],
1978	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1979	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1980	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1981	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1982	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1983	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1984
1985	Log(("FPU:\n"
1986	"FCW=%04x FSW=%04x FTW=%02x\n"
1987	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1988	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1989	,
1990	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1991	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
1992	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1993	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1994
1995
1996	Log(("MSR:\n"
1997	"EFER =%016RX64\n"
1998	"PAT =%016RX64\n"
1999	"STAR =%016RX64\n"
2000	"CSTAR =%016RX64\n"
2001	"LSTAR =%016RX64\n"
2002	"SFMASK =%016RX64\n"
2003	"KERNELGSBASE =%016RX64\n",
2004	pCtx->msrEFER,
2005	pCtx->msrPAT,
2006	pCtx->msrSTAR,
2007	pCtx->msrCSTAR,
2008	pCtx->msrLSTAR,
2009	pCtx->msrSFMASK,
2010	pCtx->msrKERNELGSBASE));
2011
2012	}
2013
2014	#endif /* VBOX_STRICT */
2015

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 38845

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