HWACCMR0.cpp@ 25193

Last change on this file since 25193 was 25193, checked in by vboxsync, 15 years ago
Wrong use of fGlobalInit
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1	/* $Id: HWACCMR0.cpp 25193 2009-12-04 14:34:07Z vboxsync $ */
2	/** @file
3	* HWACCM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_HWACCM
27	#include <VBox/hwaccm.h>
28	#include "HWACCMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/hwacc_vmx.h>
32	#include <VBox/hwacc_svm.h>
33	#include <VBox/pgm.h>
34	#include <VBox/pdm.h>
35	#include <VBox/err.h>
36	#include <VBox/log.h>
37	#include <VBox/selm.h>
38	#include <VBox/iom.h>
39	#include <iprt/assert.h>
40	#include <iprt/asm.h>
41	#include <iprt/cpuset.h>
42	#include <iprt/memobj.h>
43	#include <iprt/param.h>
44	#include <iprt/power.h>
45	#include <iprt/string.h>
46	#include <iprt/thread.h>
47	#include "HWVMXR0.h"
48	#include "HWSVMR0.h"
49
50	/*******************************************************************************
51	* Internal Functions *
52	*******************************************************************************/
53	static DECLCALLBACK(void) hwaccmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hwaccmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2);
56	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu);
57	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
58
59	/*******************************************************************************
60	* Global Variables *
61	*******************************************************************************/
62
63	static struct
64	{
65	HWACCM_CPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
66
67	/** Ring 0 handlers for VT-x and AMD-V. */
68	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu));
69	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
70	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
71	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
72	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
73	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
74	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys));
75	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
76	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
77	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
78
79	/** Maximum ASID allowed. */
80	uint32_t uMaxASID;
81
82	struct
83	{
84	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
85	bool fSupported;
86	/** Whether we're using SUPR0EnableVTx or not. */
87	bool fUsingSUPR0EnableVTx;
88
89	/** Host CR4 value (set by ring-0 VMX init) */
90	uint64_t hostCR4;
91
92	/** VMX MSR values */
93	struct
94	{
95	uint64_t feature_ctrl;
96	uint64_t vmx_basic_info;
97	VMX_CAPABILITY vmx_pin_ctls;
98	VMX_CAPABILITY vmx_proc_ctls;
99	VMX_CAPABILITY vmx_proc_ctls2;
100	VMX_CAPABILITY vmx_exit;
101	VMX_CAPABILITY vmx_entry;
102	uint64_t vmx_misc;
103	uint64_t vmx_cr0_fixed0;
104	uint64_t vmx_cr0_fixed1;
105	uint64_t vmx_cr4_fixed0;
106	uint64_t vmx_cr4_fixed1;
107	uint64_t vmx_vmcs_enum;
108	uint64_t vmx_eptcaps;
109	} msr;
110	/* Last instruction error */
111	uint32_t ulLastInstrError;
112	} vmx;
113	struct
114	{
115	/* HWCR msr (for diagnostics) */
116	uint64_t msrHWCR;
117
118	/** SVM revision. */
119	uint32_t u32Rev;
120
121	/** SVM feature bits from cpuid 0x8000000a */
122	uint32_t u32Features;
123
124	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
125	bool fSupported;
126	} svm;
127	/** Saved error from detection */
128	int32_t lLastError;
129
130	struct
131	{
132	uint32_t u32AMDFeatureECX;
133	uint32_t u32AMDFeatureEDX;
134	} cpuid;
135
136	HWACCMSTATE enmHwAccmState;
137
138	bool fGlobalInit;
139	volatile bool fSuspended;
140	} HWACCMR0Globals;
141
142
143
144	/**
145	* Does global Ring-0 HWACCM initialization.
146	*
147	* @returns VBox status code.
148	*/
149	VMMR0DECL(int) HWACCMR0Init(void)
150	{
151	int rc;
152
153	memset(&HWACCMR0Globals, 0, sizeof(HWACCMR0Globals));
154	HWACCMR0Globals.enmHwAccmState = HWACCMSTATE_UNINITIALIZED;
155	for (unsigned i = 0; i < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); i++)
156	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
157
158	/* Fill in all callbacks with placeholders. */
159	HWACCMR0Globals.pfnEnterSession = HWACCMR0DummyEnter;
160	HWACCMR0Globals.pfnLeaveSession = HWACCMR0DummyLeave;
161	HWACCMR0Globals.pfnSaveHostState = HWACCMR0DummySaveHostState;
162	HWACCMR0Globals.pfnLoadGuestState = HWACCMR0DummyLoadGuestState;
163	HWACCMR0Globals.pfnRunGuestCode = HWACCMR0DummyRunGuestCode;
164	HWACCMR0Globals.pfnEnableCpu = HWACCMR0DummyEnableCpu;
165	HWACCMR0Globals.pfnDisableCpu = HWACCMR0DummyDisableCpu;
166	HWACCMR0Globals.pfnInitVM = HWACCMR0DummyInitVM;
167	HWACCMR0Globals.pfnTermVM = HWACCMR0DummyTermVM;
168	HWACCMR0Globals.pfnSetupVM = HWACCMR0DummySetupVM;
169
170	/* Default is global VT-x/AMD-V init */
171	HWACCMR0Globals.fGlobalInit = true;
172
173	/*
174	* Check for VT-x and AMD-V capabilities
175	*/
176	if (ASMHasCpuId())
177	{
178	uint32_t u32FeaturesECX;
179	uint32_t u32Dummy;
180	uint32_t u32FeaturesEDX;
181	uint32_t u32VendorEBX, u32VendorECX, u32VendorEDX;
182
183	ASMCpuId(0, &u32Dummy, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
184	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
185	/* Query AMD features. */
186	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy, &HWACCMR0Globals.cpuid.u32AMDFeatureECX, &HWACCMR0Globals.cpuid.u32AMDFeatureEDX);
187
188	if ( u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX
189	&& u32VendorECX == X86_CPUID_VENDOR_INTEL_ECX
190	&& u32VendorEDX == X86_CPUID_VENDOR_INTEL_EDX
191	)
192	{
193	/*
194	* Read all VMX MSRs if VMX is available. (same goes for RDMSR/WRMSR)
195	* We also assume all VMX-enabled CPUs support fxsave/fxrstor.
196	*/
197	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
198	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
199	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
200	)
201	{
202	int aRc[RTCPUSET_MAX_CPUS];
203	RTCPUID idCpu = 0;
204
205	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
206
207	/*
208	* First try use native kernel API for controlling VT-x.
209	* (This is only supported by some Mac OS X kernels atm.)
210	*/
211	HWACCMR0Globals.lLastError = rc = SUPR0EnableVTx(true /* fEnable */);
212	if (rc != VERR_NOT_SUPPORTED)
213	{
214	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
215	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = true;
216	if (RT_SUCCESS(rc))
217	{
218	HWACCMR0Globals.vmx.fSupported = true;
219	rc = SUPR0EnableVTx(false /* fEnable */);
220	AssertRC(rc);
221	}
222	}
223	else
224	{
225	HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx = false;
226
227	/* We need to check if VT-x has been properly initialized on all CPUs. Some BIOSes do a lousy job. */
228	memset(aRc, 0, sizeof(aRc));
229	HWACCMR0Globals.lLastError = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
230
231	/* Check the return code of all invocations. */
232	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
233	HWACCMR0Globals.lLastError = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
234	}
235	if (RT_SUCCESS(HWACCMR0Globals.lLastError))
236	{
237	/* Reread in case we've changed it. */
238	HWACCMR0Globals.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
239
240	if ( (HWACCMR0Globals.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
241	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
242	{
243	RTR0MEMOBJ pScatchMemObj;
244	void *pvScatchPage;
245	RTHCPHYS pScatchPagePhys;
246
247	HWACCMR0Globals.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
248	HWACCMR0Globals.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
249	HWACCMR0Globals.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
250	HWACCMR0Globals.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
251	HWACCMR0Globals.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
252	HWACCMR0Globals.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
253	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
254	HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
255	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
256	HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
257	HWACCMR0Globals.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
258	/* VPID 16 bits ASID. */
259	HWACCMR0Globals.uMaxASID = 0x10000; /* exclusive */
260
261	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
262	{
263	HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
264	if (HWACCMR0Globals.vmx.msr.vmx_proc_ctls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT\|VMX_VMCS_CTRL_PROC_EXEC2_VPID))
265	HWACCMR0Globals.vmx.msr.vmx_eptcaps = ASMRdMsr(MSR_IA32_VMX_EPT_CAPS);
266	}
267
268	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
269	{
270	HWACCMR0Globals.vmx.hostCR4 = ASMGetCR4();
271
272	rc = RTR0MemObjAllocCont(&pScatchMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
273	if (RT_FAILURE(rc))
274	return rc;
275
276	pvScatchPage = RTR0MemObjAddress(pScatchMemObj);
277	pScatchPagePhys = RTR0MemObjGetPagePhysAddr(pScatchMemObj, 0);
278	memset(pvScatchPage, 0, PAGE_SIZE);
279
280	/* Set revision dword at the beginning of the structure. */
281	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(HWACCMR0Globals.vmx.msr.vmx_basic_info);
282
283	/* Make sure we don't get rescheduled to another cpu during this probe. */
284	RTCCUINTREG fFlags = ASMIntDisableFlags();
285
286	/*
287	* Check CR4.VMXE
288	*/
289	if (!(HWACCMR0Globals.vmx.hostCR4 & X86_CR4_VMXE))
290	{
291	/* In theory this bit could be cleared behind our back. Which would cause #UD faults when we
292	* try to execute the VMX instructions...
293	*/
294	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4 \| X86_CR4_VMXE);
295	}
296
297	/* Enter VMX Root Mode */
298	rc = VMXEnable(pScatchPagePhys);
299	if (RT_FAILURE(rc))
300	{
301	/* KVM leaves the CPU in VMX root mode. Not only is this not allowed, it will crash the host when we enter raw mode, because
302	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify this bit)
303	* (b) turning off paging causes a #GP (unavoidable when switching from long to 32 bits mode or 32 bits to PAE)
304	*
305	* They should fix their code, but until they do we simply refuse to run.
306	*/
307	HWACCMR0Globals.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
308	}
309	else
310	{
311	HWACCMR0Globals.vmx.fSupported = true;
312	VMXDisable();
313	}
314
315	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it wasn't so before (some software could incorrectly think it's in VMX mode) */
316	ASMSetCR4(HWACCMR0Globals.vmx.hostCR4);
317	ASMSetFlags(fFlags);
318
319	RTR0MemObjFree(pScatchMemObj, false);
320	if (RT_FAILURE(HWACCMR0Globals.lLastError))
321	return HWACCMR0Globals.lLastError;
322	}
323	}
324	else
325	{
326	AssertFailed(); /* can't hit this case anymore */
327	HWACCMR0Globals.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
328	}
329	}
330	#ifdef LOG_ENABLED
331	else
332	SUPR0Printf("HWACCMR0InitCPU failed with rc=%d\n", HWACCMR0Globals.lLastError);
333	#endif
334	}
335	else
336	HWACCMR0Globals.lLastError = VERR_VMX_NO_VMX;
337	}
338	else
339	if ( u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX
340	&& u32VendorECX == X86_CPUID_VENDOR_AMD_ECX
341	&& u32VendorEDX == X86_CPUID_VENDOR_AMD_EDX
342	)
343	{
344	/*
345	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
346	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
347	*/
348	if ( (HWACCMR0Globals.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
349	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
350	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
351	)
352	{
353	int aRc[RTCPUSET_MAX_CPUS];
354	RTCPUID idCpu = 0;
355
356	/* We need to check if AMD-V has been properly initialized on all CPUs. Some BIOSes might do a poor job. */
357	memset(aRc, 0, sizeof(aRc));
358	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)u32VendorEBX, aRc);
359	AssertRC(rc);
360
361	/* Check the return code of all invocations. */
362	if (RT_SUCCESS(rc))
363	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
364
365	#ifndef DEBUG_bird
366	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE, ("HWACCMR0InitCPU failed for cpu %d with rc=%d\n", idCpu, rc));
367	#endif
368	if (RT_SUCCESS(rc))
369	{
370	/* Query AMD features. */
371	ASMCpuId(0x8000000A, &HWACCMR0Globals.svm.u32Rev, &HWACCMR0Globals.uMaxASID, &u32Dummy, &HWACCMR0Globals.svm.u32Features);
372	/* Read the HWCR msr for diagnostics. */
373	HWACCMR0Globals.svm.msrHWCR = ASMRdMsr(MSR_K8_HWCR);
374	HWACCMR0Globals.svm.fSupported = true;
375	}
376	else
377	HWACCMR0Globals.lLastError = rc;
378	}
379	else
380	HWACCMR0Globals.lLastError = VERR_SVM_NO_SVM;
381	}
382	else
383	HWACCMR0Globals.lLastError = VERR_HWACCM_UNKNOWN_CPU;
384	}
385	else
386	HWACCMR0Globals.lLastError = VERR_HWACCM_NO_CPUID;
387
388	if (HWACCMR0Globals.vmx.fSupported)
389	{
390	HWACCMR0Globals.pfnEnterSession = VMXR0Enter;
391	HWACCMR0Globals.pfnLeaveSession = VMXR0Leave;
392	HWACCMR0Globals.pfnSaveHostState = VMXR0SaveHostState;
393	HWACCMR0Globals.pfnLoadGuestState = VMXR0LoadGuestState;
394	HWACCMR0Globals.pfnRunGuestCode = VMXR0RunGuestCode;
395	HWACCMR0Globals.pfnEnableCpu = VMXR0EnableCpu;
396	HWACCMR0Globals.pfnDisableCpu = VMXR0DisableCpu;
397	HWACCMR0Globals.pfnInitVM = VMXR0InitVM;
398	HWACCMR0Globals.pfnTermVM = VMXR0TermVM;
399	HWACCMR0Globals.pfnSetupVM = VMXR0SetupVM;
400	}
401	else
402	if (HWACCMR0Globals.svm.fSupported)
403	{
404	HWACCMR0Globals.pfnEnterSession = SVMR0Enter;
405	HWACCMR0Globals.pfnLeaveSession = SVMR0Leave;
406	HWACCMR0Globals.pfnSaveHostState = SVMR0SaveHostState;
407	HWACCMR0Globals.pfnLoadGuestState = SVMR0LoadGuestState;
408	HWACCMR0Globals.pfnRunGuestCode = SVMR0RunGuestCode;
409	HWACCMR0Globals.pfnEnableCpu = SVMR0EnableCpu;
410	HWACCMR0Globals.pfnDisableCpu = SVMR0DisableCpu;
411	HWACCMR0Globals.pfnInitVM = SVMR0InitVM;
412	HWACCMR0Globals.pfnTermVM = SVMR0TermVM;
413	HWACCMR0Globals.pfnSetupVM = SVMR0SetupVM;
414	}
415
416	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
417	{
418	rc = RTPowerNotificationRegister(hwaccmR0PowerCallback, 0);
419	AssertRC(rc);
420	}
421
422	return VINF_SUCCESS;
423	}
424
425
426	/**
427	* Checks the error code array filled in for each cpu in the system.
428	*
429	* @returns VBox status code.
430	* @param paRc Error code array
431	* @param cErrorCodes Array size
432	* @param pidCpu Value of the first cpu that set an error (out)
433	*/
434	static int hwaccmR0CheckCpuRcArray(int paRc, unsigned cErrorCodes, RTCPUID pidCpu)
435	{
436	int rc = VINF_SUCCESS;
437
438	Assert(cErrorCodes == RTCPUSET_MAX_CPUS);
439
440	for (unsigned i=0;i<cErrorCodes;i++)
441	{
442	if (RTMpIsCpuOnline(i))
443	{
444	if (RT_FAILURE(paRc[i]))
445	{
446	rc = paRc[i];
447	*pidCpu = i;
448	break;
449	}
450	}
451	}
452	return rc;
453	}
454
455	/**
456	* Does global Ring-0 HWACCM termination.
457	*
458	* @returns VBox status code.
459	*/
460	VMMR0DECL(int) HWACCMR0Term(void)
461	{
462	int rc;
463	if ( HWACCMR0Globals.vmx.fSupported
464	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
465	{
466	Assert(HWACCMR0Globals.fGlobalInit);
467	rc = SUPR0EnableVTx(false /* fEnable */);
468	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
469	{
470	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = false;
471	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
472	}
473	}
474	else
475	{
476	Assert(!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
477	if (!HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
478	{
479	rc = RTPowerNotificationDeregister(hwaccmR0PowerCallback, 0);
480	Assert(RT_SUCCESS(rc));
481	}
482	else
483	rc = VINF_SUCCESS;
484
485	/* Only disable VT-x/AMD-V on all CPUs if we enabled it before. */
486	if (HWACCMR0Globals.fGlobalInit)
487	{
488	int aRc[RTCPUSET_MAX_CPUS];
489
490	memset(aRc, 0, sizeof(aRc));
491	rc = RTMpOnAll(hwaccmR0DisableCpuCallback, aRc, NULL);
492	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
493	#ifdef VBOX_STRICT
494	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
495	AssertMsgRC(aRc[i], ("hwaccmR0DisableCpuCallback failed for cpu %d with rc=%d\n", i, aRc[i]));
496	#endif
497	}
498
499	/* Free the per-cpu pages used for VT-x and AMD-V */
500	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
501	{
502	if (HWACCMR0Globals.aCpuInfo[i].pMemObj != NIL_RTR0MEMOBJ)
503	{
504	RTR0MemObjFree(HWACCMR0Globals.aCpuInfo[i].pMemObj, false);
505	HWACCMR0Globals.aCpuInfo[i].pMemObj = NIL_RTR0MEMOBJ;
506	}
507	}
508	}
509	return rc;
510	}
511
512
513	/**
514	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
515	* is to be called on the target cpus.
516	*
517	* @param idCpu The identifier for the CPU the function is called on.
518	* @param pvUser1 The 1st user argument.
519	* @param pvUser2 The 2nd user argument.
520	*/
521	static DECLCALLBACK(void) HWACCMR0InitCPU(RTCPUID idCpu, void pvUser1, void pvUser2)
522	{
523	unsigned u32VendorEBX = (uintptr_t)pvUser1;
524	int paRc = (int )pvUser2;
525	uint64_t val;
526
527	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
528	SUPR0Printf("HWACCMR0InitCPU cpu %d\n", idCpu);
529	#endif
530	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
531
532	if (u32VendorEBX == X86_CPUID_VENDOR_INTEL_EBX)
533	{
534	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
535
536	/*
537	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
538	* Once the lock bit is set, this MSR can no longer be modified.
539	*/
540	if ( !(val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
541	\|\| ((val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK)) == MSR_IA32_FEATURE_CONTROL_VMXON) /* Some BIOSes forget to set the locked bit. */
542	)
543	{
544	/* MSR is not yet locked; we can change it ourselves here */
545	ASMWrMsr(MSR_IA32_FEATURE_CONTROL, HWACCMR0Globals.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
546	val = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
547	}
548	if ( (val & (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
549	== (MSR_IA32_FEATURE_CONTROL_VMXON\|MSR_IA32_FEATURE_CONTROL_LOCK))
550	paRc[idCpu] = VINF_SUCCESS;
551	else
552	paRc[idCpu] = VERR_VMX_MSR_LOCKED_OR_DISABLED;
553	}
554	else
555	if (u32VendorEBX == X86_CPUID_VENDOR_AMD_EBX)
556	{
557	/* Check if SVM is disabled */
558	val = ASMRdMsr(MSR_K8_VM_CR);
559	if (!(val & MSR_K8_VM_CR_SVM_DISABLE))
560	{
561	/* Turn on SVM in the EFER MSR. */
562	val = ASMRdMsr(MSR_K6_EFER);
563	if (val & MSR_K6_EFER_SVME)
564	{
565	paRc[idCpu] = VERR_SVM_IN_USE;
566	}
567	else
568	{
569	ASMWrMsr(MSR_K6_EFER, val \| MSR_K6_EFER_SVME);
570
571	/* Paranoia. */
572	val = ASMRdMsr(MSR_K6_EFER);
573	if (val & MSR_K6_EFER_SVME)
574	{
575	/* Restore previous value. */
576	ASMWrMsr(MSR_K6_EFER, val & ~MSR_K6_EFER_SVME);
577	paRc[idCpu] = VINF_SUCCESS;
578	}
579	else
580	paRc[idCpu] = VERR_SVM_ILLEGAL_EFER_MSR;
581	}
582	}
583	else
584	paRc[idCpu] = VERR_SVM_DISABLED;
585	}
586	else
587	AssertFailed(); /* can't happen */
588	return;
589	}
590
591
592	/**
593	* Sets up HWACCM on all cpus.
594	*
595	* @returns VBox status code.
596	* @param pVM The VM to operate on.
597	*
598	*/
599	VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM)
600	{
601	AssertCompile(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
602
603	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
604	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
605	return VERR_HWACCM_SUSPEND_PENDING;
606
607	if (ASMAtomicCmpXchgU32((volatile uint32_t *)&HWACCMR0Globals.enmHwAccmState, HWACCMSTATE_ENABLED, HWACCMSTATE_UNINITIALIZED))
608	{
609	int rc;
610
611	HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit;
612
613	if ( HWACCMR0Globals.vmx.fSupported
614	&& HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx)
615	{
616	rc = SUPR0EnableVTx(true /* fEnable */);
617	if (RT_SUCCESS(rc))
618	{
619	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo); iCpu++)
620	{
621	HWACCMR0Globals.aCpuInfo[iCpu].fConfigured = true;
622	Assert(HWACCMR0Globals.aCpuInfo[iCpu].pMemObj == NIL_RTR0MEMOBJ);
623	}
624	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
625	HWACCMR0Globals.fGlobalInit = pVM->hwaccm.s.fGlobalInit = true;
626	}
627	else
628	AssertMsgFailed(("HWACCMR0EnableAllCpus/SUPR0EnableVTx: rc=%Rrc\n", rc));
629	}
630	else
631	{
632	int aRc[RTCPUSET_MAX_CPUS];
633	RTCPUID idCpu = 0;
634
635	memset(aRc, 0, sizeof(aRc));
636
637	/* Allocate one page per cpu for the global vt-x and amd-v pages */
638	for (unsigned i=0;i<RT_ELEMENTS(HWACCMR0Globals.aCpuInfo);i++)
639	{
640	Assert(!HWACCMR0Globals.aCpuInfo[i].pMemObj);
641
642	/** @todo this is rather dangerous if cpus can be taken offline; we don't care for now */
643	if (RTMpIsCpuOnline(i))
644	{
645	rc = RTR0MemObjAllocCont(&HWACCMR0Globals.aCpuInfo[i].pMemObj, 1 << PAGE_SHIFT, true /* executable R0 mapping */);
646	AssertRC(rc);
647	if (RT_FAILURE(rc))
648	return rc;
649
650	void *pvR0 = RTR0MemObjAddress(HWACCMR0Globals.aCpuInfo[i].pMemObj);
651	Assert(pvR0);
652	ASMMemZeroPage(pvR0);
653
654	#if defined(LOG_ENABLED) && !defined(DEBUG_bird)
655	SUPR0Printf("address %x phys %x\n", pvR0, (uint32_t)RTR0MemObjGetPagePhysAddr(HWACCMR0Globals.aCpuInfo[i].pMemObj, 0));
656	#endif
657	}
658	}
659	if (HWACCMR0Globals.fGlobalInit)
660	{
661	/* First time, so initialize each cpu/core */
662	rc = RTMpOnAll(hwaccmR0EnableCpuCallback, (void *)pVM, aRc);
663
664	/* Check the return code of all invocations. */
665	if (RT_SUCCESS(rc))
666	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
667	AssertMsgRC(rc, ("HWACCMR0EnableAllCpus failed for cpu %d with rc=%d\n", idCpu, rc));
668	}
669	else
670	rc = VINF_SUCCESS;
671	}
672
673	return rc;
674	}
675	return VINF_SUCCESS;
676	}
677
678	/**
679	* Disable VT-x or AMD-V on the current CPU
680	*
681	* @returns VBox status code.
682	* @param pVM VM handle (can be 0!)
683	* @param idCpu The identifier for the CPU the function is called on.
684	*/
685	static int hwaccmR0EnableCpu(PVM pVM, RTCPUID idCpu)
686	{
687	void *pvPageCpu;
688	RTHCPHYS pPageCpuPhys;
689	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
690
691	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
692	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
693	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
694	Assert(!pCpu->fConfigured);
695	Assert(!HWACCMR0Globals.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
696
697	pCpu->idCpu = idCpu;
698
699	/* Make sure we start with a clean TLB. */
700	pCpu->fFlushTLB = true;
701
702	pCpu->uCurrentASID = 0; /* we'll aways increment this the first time (host uses ASID 0) */
703	pCpu->cTLBFlushes = 0;
704
705	/* Should never happen */
706	if (!pCpu->pMemObj)
707	{
708	AssertFailed();
709	return VERR_INTERNAL_ERROR;
710	}
711
712	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
713	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
714
715	int rc = HWACCMR0Globals.pfnEnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
716	AssertRC(rc);
717	if (RT_SUCCESS(rc))
718	pCpu->fConfigured = true;
719
720	return rc;
721	}
722
723
724	/**
725	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
726	* is to be called on the target cpus.
727	*
728	* @param idCpu The identifier for the CPU the function is called on.
729	* @param pvUser1 The 1st user argument.
730	* @param pvUser2 The 2nd user argument.
731	*/
732	static DECLCALLBACK(void) hwaccmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
733	{
734	PVM pVM = (PVM)pvUser1; /* can be NULL! */
735	int paRc = (int )pvUser2;
736
737	if (!HWACCMR0Globals.fGlobalInit)
738	{
739	paRc[idCpu] = VINF_SUCCESS;
740	AssertFailed();
741	return;
742	}
743
744	paRc[idCpu] = hwaccmR0EnableCpu(pVM, idCpu);
745	}
746
747
748	/**
749	* Disable VT-x or AMD-V on the current CPU
750	*
751	* @returns VBox status code.
752	* @param idCpu The identifier for the CPU the function is called on.
753	*/
754	static int hwaccmR0DisableCpu(RTCPUID idCpu)
755	{
756	void *pvPageCpu;
757	RTHCPHYS pPageCpuPhys;
758	int rc;
759	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
760
761	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
762	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
763	Assert(idCpu < RT_ELEMENTS(HWACCMR0Globals.aCpuInfo));
764	Assert(!HWACCMR0Globals.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
765	Assert(!pCpu->fConfigured \|\| pCpu->pMemObj);
766
767	if (!pCpu->pMemObj)
768	return (pCpu->fConfigured) ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
769
770	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
771	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
772
773	if (pCpu->fConfigured)
774	{
775	rc = HWACCMR0Globals.pfnDisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
776	AssertRC(rc);
777	pCpu->fConfigured = false;
778	}
779	else
780	rc = VINF_SUCCESS; /* nothing to do */
781
782	pCpu->uCurrentASID = 0;
783	return rc;
784	}
785
786	/**
787	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
788	* is to be called on the target cpus.
789	*
790	* @param idCpu The identifier for the CPU the function is called on.
791	* @param pvUser1 The 1st user argument.
792	* @param pvUser2 The 2nd user argument.
793	*/
794	static DECLCALLBACK(void) hwaccmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
795	{
796	int paRc = (int )pvUser1;
797
798	if (!HWACCMR0Globals.fGlobalInit)
799	{
800	paRc[idCpu] = VINF_SUCCESS;
801	AssertFailed();
802	return;
803	}
804
805	paRc[idCpu] = hwaccmR0DisableCpu(idCpu);
806	}
807
808	/**
809	* Called whenever a system power state change occurs.
810	*
811	* @param enmEvent Power event
812	* @param pvUser User argument
813	*/
814	static DECLCALLBACK(void) hwaccmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
815	{
816	NOREF(pvUser);
817	Assert(!HWACCMR0Globals.vmx.fSupported \|\| !HWACCMR0Globals.vmx.fUsingSUPR0EnableVTx);
818
819	#ifdef LOG_ENABLED
820	if (enmEvent == RTPOWEREVENT_SUSPEND)
821	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
822	else
823	SUPR0Printf("hwaccmR0PowerCallback RTPOWEREVENT_RESUME\n");
824	#endif
825
826	if (enmEvent == RTPOWEREVENT_SUSPEND)
827	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, true);
828
829	if (HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED)
830	{
831	int aRc[RTCPUSET_MAX_CPUS];
832	int rc;
833	RTCPUID idCpu;
834
835	memset(aRc, 0, sizeof(aRc));
836	if (enmEvent == RTPOWEREVENT_SUSPEND)
837	{
838	if (HWACCMR0Globals.fGlobalInit)
839	{
840	/* Turn off VT-x or AMD-V on all CPUs. */
841	rc = RTMpOnAll(hwaccmR0DisableCpuCallback, aRc, NULL);
842	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
843	}
844	/* else nothing to do here for the local init case */
845	}
846	else
847	{
848	/* Reinit the CPUs from scratch as the suspend state might have messed with the MSRs. (lousy BIOSes as usual) */
849	rc = RTMpOnAll(HWACCMR0InitCPU, (void *)((HWACCMR0Globals.vmx.fSupported) ? X86_CPUID_VENDOR_INTEL_EBX : X86_CPUID_VENDOR_AMD_EBX), aRc);
850	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
851
852	if (RT_SUCCESS(rc))
853	rc = hwaccmR0CheckCpuRcArray(aRc, RT_ELEMENTS(aRc), &idCpu);
854	#ifdef LOG_ENABLED
855	if (RT_FAILURE(rc))
856	SUPR0Printf("hwaccmR0PowerCallback HWACCMR0InitCPU failed with %d\n", rc);
857	#endif
858
859	if (HWACCMR0Globals.fGlobalInit)
860	{
861	/* Turn VT-x or AMD-V back on on all CPUs. */
862	rc = RTMpOnAll(hwaccmR0EnableCpuCallback, NULL, aRc);
863	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
864	}
865	/* else nothing to do here for the local init case */
866	}
867	}
868	if (enmEvent == RTPOWEREVENT_RESUME)
869	ASMAtomicWriteBool(&HWACCMR0Globals.fSuspended, false);
870	}
871
872
873	/**
874	* Does Ring-0 per VM HWACCM initialization.
875	*
876	* This is mainly to check that the Host CPU mode is compatible
877	* with VMX.
878	*
879	* @returns VBox status code.
880	* @param pVM The VM to operate on.
881	*/
882	VMMR0DECL(int) HWACCMR0InitVM(PVM pVM)
883	{
884	int rc;
885
886	AssertReturn(pVM, VERR_INVALID_PARAMETER);
887
888	#ifdef LOG_ENABLED
889	SUPR0Printf("HWACCMR0InitVM: %p\n", pVM);
890	#endif
891
892	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
893	if (ASMAtomicReadBool(&HWACCMR0Globals.fSuspended))
894	return VERR_HWACCM_SUSPEND_PENDING;
895
896	pVM->hwaccm.s.vmx.fSupported = HWACCMR0Globals.vmx.fSupported;
897	pVM->hwaccm.s.svm.fSupported = HWACCMR0Globals.svm.fSupported;
898
899	pVM->hwaccm.s.vmx.msr.feature_ctrl = HWACCMR0Globals.vmx.msr.feature_ctrl;
900	pVM->hwaccm.s.vmx.hostCR4 = HWACCMR0Globals.vmx.hostCR4;
901	pVM->hwaccm.s.vmx.msr.vmx_basic_info = HWACCMR0Globals.vmx.msr.vmx_basic_info;
902	pVM->hwaccm.s.vmx.msr.vmx_pin_ctls = HWACCMR0Globals.vmx.msr.vmx_pin_ctls;
903	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls = HWACCMR0Globals.vmx.msr.vmx_proc_ctls;
904	pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2 = HWACCMR0Globals.vmx.msr.vmx_proc_ctls2;
905	pVM->hwaccm.s.vmx.msr.vmx_exit = HWACCMR0Globals.vmx.msr.vmx_exit;
906	pVM->hwaccm.s.vmx.msr.vmx_entry = HWACCMR0Globals.vmx.msr.vmx_entry;
907	pVM->hwaccm.s.vmx.msr.vmx_misc = HWACCMR0Globals.vmx.msr.vmx_misc;
908	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed0;
909	pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr0_fixed1;
910	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed0;
911	pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1 = HWACCMR0Globals.vmx.msr.vmx_cr4_fixed1;
912	pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum = HWACCMR0Globals.vmx.msr.vmx_vmcs_enum;
913	pVM->hwaccm.s.vmx.msr.vmx_eptcaps = HWACCMR0Globals.vmx.msr.vmx_eptcaps;
914	pVM->hwaccm.s.svm.msrHWCR = HWACCMR0Globals.svm.msrHWCR;
915	pVM->hwaccm.s.svm.u32Rev = HWACCMR0Globals.svm.u32Rev;
916	pVM->hwaccm.s.svm.u32Features = HWACCMR0Globals.svm.u32Features;
917	pVM->hwaccm.s.cpuid.u32AMDFeatureECX = HWACCMR0Globals.cpuid.u32AMDFeatureECX;
918	pVM->hwaccm.s.cpuid.u32AMDFeatureEDX = HWACCMR0Globals.cpuid.u32AMDFeatureEDX;
919	pVM->hwaccm.s.lLastError = HWACCMR0Globals.lLastError;
920
921	pVM->hwaccm.s.uMaxASID = HWACCMR0Globals.uMaxASID;
922
923
924	if (!pVM->hwaccm.s.cMaxResumeLoops) /* allow ring-3 overrides */
925	{
926	pVM->hwaccm.s.cMaxResumeLoops = 1024;
927	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
928	if (RTThreadPreemptIsPendingTrusty())
929	pVM->hwaccm.s.cMaxResumeLoops = 8192;
930	#endif
931	}
932
933	for (VMCPUID i = 0; i < pVM->cCpus; i++)
934	{
935	PVMCPU pVCpu = &pVM->aCpus[i];
936
937	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
938
939	/* Invalidate the last cpu we were running on. */
940	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
941
942	/* we'll aways increment this the first time (host uses ASID 0) */
943	pVCpu->hwaccm.s.uCurrentASID = 0;
944	}
945
946	RTCCUINTREG fFlags = ASMIntDisableFlags();
947	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
948
949	/* Note: Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
950	ASMAtomicWriteBool(&pCpu->fInUse, true);
951	ASMSetFlags(fFlags);
952
953	/* Init a VT-x or AMD-V VM. */
954	rc = HWACCMR0Globals.pfnInitVM(pVM);
955
956	ASMAtomicWriteBool(&pCpu->fInUse, false);
957	return rc;
958	}
959
960
961	/**
962	* Does Ring-0 per VM HWACCM termination.
963	*
964	* @returns VBox status code.
965	* @param pVM The VM to operate on.
966	*/
967	VMMR0DECL(int) HWACCMR0TermVM(PVM pVM)
968	{
969	int rc;
970
971	AssertReturn(pVM, VERR_INVALID_PARAMETER);
972
973	#ifdef LOG_ENABLED
974	SUPR0Printf("HWACCMR0TermVM: %p\n", pVM);
975	#endif
976
977	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
978	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
979
980	/* @note Not correct as we can be rescheduled to a different cpu, but the fInUse case is mostly for debugging. */
981	RTCCUINTREG fFlags = ASMIntDisableFlags();
982	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
983
984	ASMAtomicWriteBool(&pCpu->fInUse, true);
985	ASMSetFlags(fFlags);
986
987	/* Terminate a VT-x or AMD-V VM. */
988	rc = HWACCMR0Globals.pfnTermVM(pVM);
989
990	ASMAtomicWriteBool(&pCpu->fInUse, false);
991	return rc;
992	}
993
994
995	/**
996	* Sets up a VT-x or AMD-V session
997	*
998	* @returns VBox status code.
999	* @param pVM The VM to operate on.
1000	*/
1001	VMMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
1002	{
1003	int rc;
1004	RTCPUID idCpu = RTMpCpuId();
1005	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1006
1007	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1008
1009	/* Make sure we don't touch hwaccm after we've disabled hwaccm in preparation of a suspend. */
1010	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1011
1012	#ifdef LOG_ENABLED
1013	SUPR0Printf("HWACCMR0SetupVM: %p\n", pVM);
1014	#endif
1015
1016	ASMAtomicWriteBool(&pCpu->fInUse, true);
1017
1018	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1019	{
1020	/* On first entry we'll sync everything. */
1021	pVM->aCpus[i].hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1022	}
1023
1024	/* Enable VT-x or AMD-V if local init is required. */
1025	if (!HWACCMR0Globals.fGlobalInit)
1026	{
1027	rc = hwaccmR0EnableCpu(pVM, idCpu);
1028	AssertRCReturn(rc, rc);
1029	}
1030
1031	/* Setup VT-x or AMD-V. */
1032	rc = HWACCMR0Globals.pfnSetupVM(pVM);
1033
1034	/* Disable VT-x or AMD-V if local init was done before. */
1035	if (!HWACCMR0Globals.fGlobalInit)
1036	{
1037	rc = hwaccmR0DisableCpu(idCpu);
1038	AssertRC(rc);
1039	}
1040
1041	ASMAtomicWriteBool(&pCpu->fInUse, false);
1042
1043	return rc;
1044	}
1045
1046
1047	/**
1048	* Enters the VT-x or AMD-V session
1049	*
1050	* @returns VBox status code.
1051	* @param pVM The VM to operate on.
1052	* @param pVCpu VMCPUD id.
1053	*/
1054	VMMR0DECL(int) HWACCMR0Enter(PVM pVM, PVMCPU pVCpu)
1055	{
1056	PCPUMCTX pCtx;
1057	int rc;
1058	RTCPUID idCpu = RTMpCpuId();
1059	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1060
1061	/* Make sure we can't enter a session after we've disabled hwaccm in preparation of a suspend. */
1062	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1063	ASMAtomicWriteBool(&pCpu->fInUse, true);
1064
1065	AssertMsg(pVCpu->hwaccm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVCpu->hwaccm.s.idEnteredCpu));
1066	pVCpu->hwaccm.s.idEnteredCpu = idCpu;
1067
1068	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1069
1070	/* Always load the guest's FPU/XMM state on-demand. */
1071	CPUMDeactivateGuestFPUState(pVCpu);
1072
1073	/* Always load the guest's debug state on-demand. */
1074	CPUMDeactivateGuestDebugState(pVCpu);
1075
1076	/* Always reload the host context and the guest's CR0 register. (!!!!) */
1077	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0 \| HWACCM_CHANGED_HOST_CONTEXT;
1078
1079	/* Setup the register and mask according to the current execution mode. */
1080	if (pCtx->msrEFER & MSR_K6_EFER_LMA)
1081	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFFFFFFFFFF);
1082	else
1083	pVM->hwaccm.s.u64RegisterMask = UINT64_C(0xFFFFFFFF);
1084
1085	/* Enable VT-x or AMD-V if local init is required. */
1086	if (!HWACCMR0Globals.fGlobalInit)
1087	{
1088	rc = hwaccmR0EnableCpu(pVM, idCpu);
1089	AssertRCReturn(rc, rc);
1090	}
1091
1092	rc = HWACCMR0Globals.pfnEnterSession(pVM, pVCpu, pCpu);
1093	AssertRC(rc);
1094	/* We must save the host context here (VT-x) as we might be rescheduled on a different cpu after a long jump back to ring 3. */
1095	rc \|= HWACCMR0Globals.pfnSaveHostState(pVM, pVCpu);
1096	AssertRC(rc);
1097	rc \|= HWACCMR0Globals.pfnLoadGuestState(pVM, pVCpu, pCtx);
1098	AssertRC(rc);
1099
1100	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1101	if (RT_SUCCESS(rc))
1102	{
1103	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1104	PGMDynMapMigrateAutoSet(pVCpu);
1105	#endif
1106	}
1107	else
1108	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1109	return rc;
1110	}
1111
1112
1113	/**
1114	* Leaves the VT-x or AMD-V session
1115	*
1116	* @returns VBox status code.
1117	* @param pVM The VM to operate on.
1118	* @param pVCpu VMCPUD id.
1119	*/
1120	VMMR0DECL(int) HWACCMR0Leave(PVM pVM, PVMCPU pVCpu)
1121	{
1122	PCPUMCTX pCtx;
1123	int rc;
1124	RTCPUID idCpu = RTMpCpuId();
1125	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1126
1127	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1128
1129	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1130
1131	/* Note: It's rather tricky with longjmps done by e.g. Log statements or the page fault handler.
1132	* We must restore the host FPU here to make absolutely sure we don't leave the guest FPU state active
1133	* or trash somebody else's FPU state.
1134	*/
1135	/* Save the guest FPU and XMM state if necessary. */
1136	if (CPUMIsGuestFPUStateActive(pVCpu))
1137	{
1138	Log2(("CPUMR0SaveGuestFPU\n"));
1139	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1140
1141	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_GUEST_CR0;
1142	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1143	}
1144
1145	rc = HWACCMR0Globals.pfnLeaveSession(pVM, pVCpu, pCtx);
1146
1147	/* keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1148	#ifdef RT_STRICT
1149	if (RT_UNLIKELY( pVCpu->hwaccm.s.idEnteredCpu != idCpu
1150	&& RT_FAILURE(rc)))
1151	{
1152	AssertMsgFailed(("Owner is %d, I'm %d", (int)pVCpu->hwaccm.s.idEnteredCpu, (int)idCpu));
1153	rc = VERR_INTERNAL_ERROR;
1154	}
1155	#endif
1156	pVCpu->hwaccm.s.idEnteredCpu = NIL_RTCPUID;
1157
1158	/* Disable VT-x or AMD-V if local init was done before. */
1159	if (!HWACCMR0Globals.fGlobalInit)
1160	{
1161	rc = hwaccmR0DisableCpu(idCpu);
1162	AssertRC(rc);
1163
1164	/* Reset these to force a TLB flush for the next entry. (-> EXPENSIVE) */
1165	pVCpu->hwaccm.s.idLastCpu = NIL_RTCPUID;
1166	pVCpu->hwaccm.s.uCurrentASID = 0;
1167	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1168	}
1169
1170	ASMAtomicWriteBool(&pCpu->fInUse, false);
1171	return rc;
1172	}
1173
1174	/**
1175	* Runs guest code in a hardware accelerated VM.
1176	*
1177	* @returns VBox status code.
1178	* @param pVM The VM to operate on.
1179	* @param pVCpu VMCPUD id.
1180	*/
1181	VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1182	{
1183	CPUMCTX *pCtx;
1184	int rc;
1185	#ifdef VBOX_STRICT
1186	RTCPUID idCpu = RTMpCpuId(); NOREF(idCpu);
1187	PHWACCM_CPUINFO pCpu = &HWACCMR0Globals.aCpuInfo[idCpu];
1188	#endif
1189
1190	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1191	Assert(HWACCMR0Globals.aCpuInfo[idCpu].fConfigured);
1192	AssertReturn(!ASMAtomicReadBool(&HWACCMR0Globals.fSuspended), VERR_HWACCM_SUSPEND_PENDING);
1193	Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
1194
1195	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1196	PGMDynMapStartAutoSet(pVCpu);
1197	#endif
1198
1199	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1200
1201	rc = HWACCMR0Globals.pfnRunGuestCode(pVM, pVCpu, pCtx);
1202
1203	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1204	PGMDynMapReleaseAutoSet(pVCpu);
1205	#endif
1206	return rc;
1207	}
1208
1209
1210	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1211	/**
1212	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1213	*
1214	* @returns VBox status code.
1215	* @param pVM VM handle.
1216	* @param pVCpu VMCPU handle.
1217	* @param pCtx CPU context
1218	*/
1219	VMMR0DECL(int) HWACCMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1220	{
1221	if (pVM->hwaccm.s.vmx.fSupported)
1222	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1223
1224	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestFPU64, 0, NULL);
1225	}
1226
1227	/**
1228	* Save guest debug state (64 bits guest mode & 32 bits host only)
1229	*
1230	* @returns VBox status code.
1231	* @param pVM VM handle.
1232	* @param pVCpu VMCPU handle.
1233	* @param pCtx CPU context
1234	*/
1235	VMMR0DECL(int) HWACCMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1236	{
1237	if (pVM->hwaccm.s.vmx.fSupported)
1238	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1239
1240	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnSaveGuestDebug64, 0, NULL);
1241	}
1242
1243	/**
1244	* Test the 32->64 bits switcher
1245	*
1246	* @returns VBox status code.
1247	* @param pVM VM handle.
1248	*/
1249	VMMR0DECL(int) HWACCMR0TestSwitcher3264(PVM pVM)
1250	{
1251	PVMCPU pVCpu = &pVM->aCpus[0];
1252	CPUMCTX *pCtx;
1253	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1254	int rc;
1255
1256	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1257
1258	STAM_PROFILE_ADV_START(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1259	if (pVM->hwaccm.s.vmx.fSupported)
1260	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1261	else
1262	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, pVM->hwaccm.s.pfnTest64, 5, &aParam[0]);
1263	STAM_PROFILE_ADV_STOP(&pVCpu->hwaccm.s.StatWorldSwitch3264, z);
1264	return rc;
1265	}
1266
1267	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1268
1269	/**
1270	* Returns suspend status of the host
1271	*
1272	* @returns Suspend pending or not
1273	*/
1274	VMMR0DECL(bool) HWACCMR0SuspendPending()
1275	{
1276	return ASMAtomicReadBool(&HWACCMR0Globals.fSuspended);
1277	}
1278
1279	/**
1280	* Returns the cpu structure for the current cpu.
1281	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1282	*
1283	* @returns cpu structure pointer
1284	*/
1285	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
1286	{
1287	RTCPUID idCpu = RTMpCpuId();
1288
1289	return &HWACCMR0Globals.aCpuInfo[idCpu];
1290	}
1291
1292	/**
1293	* Returns the cpu structure for the current cpu.
1294	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1295	*
1296	* @returns cpu structure pointer
1297	* @param idCpu id of the VCPU
1298	*/
1299	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu)
1300	{
1301	return &HWACCMR0Globals.aCpuInfo[idCpu];
1302	}
1303
1304	/**
1305	* Returns the VMCPU of the current EMT thread.
1306	*
1307	* @param pVM The VM to operate on.
1308	*/
1309	VMMR0DECL(PVMCPU) HWACCMR0GetVMCPU(PVM pVM)
1310	{
1311	/* RTMpCpuId had better be cheap. */
1312	RTCPUID idHostCpu = RTMpCpuId();
1313
1314	/** @todo optimize for large number of VCPUs when that becomes more common. */
1315	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1316	{
1317	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1318
1319	if (pVCpu->hwaccm.s.idEnteredCpu == idHostCpu)
1320	return pVCpu;
1321	}
1322	return NULL;
1323	}
1324
1325	/**
1326	* Returns the VMCPU id of the current EMT thread.
1327	*
1328	* @param pVM The VM to operate on.
1329	*/
1330	VMMR0DECL(VMCPUID) HWACCMR0GetVMCPUId(PVM pVM)
1331	{
1332	PVMCPU pVCpu = HWACCMR0GetVMCPU(pVM);
1333	if (pVCpu)
1334	return pVCpu->idCpu;
1335
1336	return 0;
1337	}
1338
1339	/**
1340	* Save a pending IO read.
1341	*
1342	* @param pVCpu The VMCPU to operate on.
1343	* @param GCPtrRip Address of IO instruction
1344	* @param GCPtrRipNext Address of the next instruction
1345	* @param uPort Port address
1346	* @param uAndVal And mask for saving the result in eax
1347	* @param cbSize Read size
1348	*/
1349	VMMR0DECL(void) HWACCMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1350	{
1351	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_READ;
1352	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1353	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1354	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1355	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1356	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1357	return;
1358	}
1359
1360	/**
1361	* Save a pending IO write.
1362	*
1363	* @param pVCpu The VMCPU to operate on.
1364	* @param GCPtrRIP Address of IO instruction
1365	* @param uPort Port address
1366	* @param uAndVal And mask for fetching the result from eax
1367	* @param cbSize Read size
1368	*/
1369	VMMR0DECL(void) HWACCMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext, unsigned uPort, unsigned uAndVal, unsigned cbSize)
1370	{
1371	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_PORT_WRITE;
1372	pVCpu->hwaccm.s.PendingIO.GCPtrRip = GCPtrRip;
1373	pVCpu->hwaccm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1374	pVCpu->hwaccm.s.PendingIO.s.Port.uPort = uPort;
1375	pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal = uAndVal;
1376	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize = cbSize;
1377	return;
1378	}
1379
1380	/**
1381	* Disable VT-x if it's active and the current switcher turns off paging
1382	*
1383	* @returns VBox status code.
1384	* @param pVM VM handle.
1385	* @param pfVTxDisabled VT-x was disabled or not (out)
1386	*/
1387	VMMR0DECL(int) HWACCMR0EnterSwitcher(PVM pVM, bool *pfVTxDisabled)
1388	{
1389	Assert(!(ASMGetFlags() & X86_EFL_IF));
1390
1391	*pfVTxDisabled = false;
1392
1393	if ( HWACCMR0Globals.enmHwAccmState != HWACCMSTATE_ENABLED
1394	\|\| !HWACCMR0Globals.vmx.fSupported /* no such issues with AMD-V */
1395	\|\| !HWACCMR0Globals.fGlobalInit /* Local init implies the CPU is currently not in VMX root mode. */)
1396	return VINF_SUCCESS; /* nothing to do */
1397
1398	switch(VMMGetSwitcher(pVM))
1399	{
1400	case VMMSWITCHER_32_TO_32:
1401	case VMMSWITCHER_PAE_TO_PAE:
1402	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1403
1404	case VMMSWITCHER_32_TO_PAE:
1405	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1406	case VMMSWITCHER_AMD64_TO_32:
1407	case VMMSWITCHER_AMD64_TO_PAE:
1408	break; /* unsafe switchers */
1409
1410	default:
1411	AssertFailed();
1412	return VERR_INTERNAL_ERROR;
1413	}
1414
1415	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1416	void *pvPageCpu;
1417	RTHCPHYS pPageCpuPhys;
1418
1419	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1420	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1421	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1422
1423	*pfVTxDisabled = true;
1424	return VMXR0DisableCpu(pCpu, pvPageCpu, pPageCpuPhys);
1425	}
1426
1427	/**
1428	* Reeable VT-x if was active and the current switcher turned off paging
1429	*
1430	* @returns VBox status code.
1431	* @param pVM VM handle.
1432	* @param fVTxDisabled VT-x was disabled or not
1433	*/
1434	VMMR0DECL(int) HWACCMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1435	{
1436	Assert(!(ASMGetFlags() & X86_EFL_IF));
1437
1438	if (!fVTxDisabled)
1439	return VINF_SUCCESS; /* nothing to do */
1440
1441	Assert( HWACCMR0Globals.enmHwAccmState == HWACCMSTATE_ENABLED
1442	&& HWACCMR0Globals.vmx.fSupported
1443	&& HWACCMR0Globals.fGlobalInit);
1444
1445	PHWACCM_CPUINFO pCpu = HWACCMR0GetCurrentCpu();
1446	void *pvPageCpu;
1447	RTHCPHYS pPageCpuPhys;
1448
1449	AssertReturn(pCpu && pCpu->pMemObj, VERR_INTERNAL_ERROR);
1450	pvPageCpu = RTR0MemObjAddress(pCpu->pMemObj);
1451	pPageCpuPhys = RTR0MemObjGetPagePhysAddr(pCpu->pMemObj, 0);
1452
1453	return VMXR0EnableCpu(pCpu, pVM, pvPageCpu, pPageCpuPhys);
1454	}
1455
1456	#ifdef VBOX_STRICT
1457	/**
1458	* Dumps a descriptor.
1459	*
1460	* @param pDesc Descriptor to dump.
1461	* @param Sel Selector number.
1462	* @param pszMsg Message to prepend the log entry with.
1463	*/
1464	VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1465	{
1466	/*
1467	* Make variable description string.
1468	*/
1469	static struct
1470	{
1471	unsigned cch;
1472	const char *psz;
1473	} const s_aTypes[32] =
1474	{
1475	# define STRENTRY(str) { sizeof(str) - 1, str }
1476
1477	/* system */
1478	# if HC_ARCH_BITS == 64
1479	STRENTRY("Reserved0 "), /* 0x00 */
1480	STRENTRY("Reserved1 "), /* 0x01 */
1481	STRENTRY("LDT "), /* 0x02 */
1482	STRENTRY("Reserved3 "), /* 0x03 */
1483	STRENTRY("Reserved4 "), /* 0x04 */
1484	STRENTRY("Reserved5 "), /* 0x05 */
1485	STRENTRY("Reserved6 "), /* 0x06 */
1486	STRENTRY("Reserved7 "), /* 0x07 */
1487	STRENTRY("Reserved8 "), /* 0x08 */
1488	STRENTRY("TSS64Avail "), /* 0x09 */
1489	STRENTRY("ReservedA "), /* 0x0a */
1490	STRENTRY("TSS64Busy "), /* 0x0b */
1491	STRENTRY("Call64 "), /* 0x0c */
1492	STRENTRY("ReservedD "), /* 0x0d */
1493	STRENTRY("Int64 "), /* 0x0e */
1494	STRENTRY("Trap64 "), /* 0x0f */
1495	# else
1496	STRENTRY("Reserved0 "), /* 0x00 */
1497	STRENTRY("TSS16Avail "), /* 0x01 */
1498	STRENTRY("LDT "), /* 0x02 */
1499	STRENTRY("TSS16Busy "), /* 0x03 */
1500	STRENTRY("Call16 "), /* 0x04 */
1501	STRENTRY("Task "), /* 0x05 */
1502	STRENTRY("Int16 "), /* 0x06 */
1503	STRENTRY("Trap16 "), /* 0x07 */
1504	STRENTRY("Reserved8 "), /* 0x08 */
1505	STRENTRY("TSS32Avail "), /* 0x09 */
1506	STRENTRY("ReservedA "), /* 0x0a */
1507	STRENTRY("TSS32Busy "), /* 0x0b */
1508	STRENTRY("Call32 "), /* 0x0c */
1509	STRENTRY("ReservedD "), /* 0x0d */
1510	STRENTRY("Int32 "), /* 0x0e */
1511	STRENTRY("Trap32 "), /* 0x0f */
1512	# endif
1513	/* non system */
1514	STRENTRY("DataRO "), /* 0x10 */
1515	STRENTRY("DataRO Accessed "), /* 0x11 */
1516	STRENTRY("DataRW "), /* 0x12 */
1517	STRENTRY("DataRW Accessed "), /* 0x13 */
1518	STRENTRY("DataDownRO "), /* 0x14 */
1519	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1520	STRENTRY("DataDownRW "), /* 0x16 */
1521	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1522	STRENTRY("CodeEO "), /* 0x18 */
1523	STRENTRY("CodeEO Accessed "), /* 0x19 */
1524	STRENTRY("CodeER "), /* 0x1a */
1525	STRENTRY("CodeER Accessed "), /* 0x1b */
1526	STRENTRY("CodeConfEO "), /* 0x1c */
1527	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1528	STRENTRY("CodeConfER "), /* 0x1e */
1529	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1530	# undef SYSENTRY
1531	};
1532	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1533	char szMsg[128];
1534	char *psz = &szMsg[0];
1535	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1536	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1537	psz += s_aTypes[i].cch;
1538
1539	if (pDesc->Gen.u1Present)
1540	ADD_STR(psz, "Present ");
1541	else
1542	ADD_STR(psz, "Not-Present ");
1543	# if HC_ARCH_BITS == 64
1544	if (pDesc->Gen.u1Long)
1545	ADD_STR(psz, "64-bit ");
1546	else
1547	ADD_STR(psz, "Comp ");
1548	# else
1549	if (pDesc->Gen.u1Granularity)
1550	ADD_STR(psz, "Page ");
1551	if (pDesc->Gen.u1DefBig)
1552	ADD_STR(psz, "32-bit ");
1553	else
1554	ADD_STR(psz, "16-bit ");
1555	# endif
1556	# undef ADD_STR
1557	*psz = '\0';
1558
1559	/*
1560	* Limit and Base and format the output.
1561	*/
1562	uint32_t u32Limit = X86DESC_LIMIT(*pDesc);
1563	if (pDesc->Gen.u1Granularity)
1564	u32Limit = u32Limit << PAGE_SHIFT \| PAGE_OFFSET_MASK;
1565
1566	# if HC_ARCH_BITS == 64
1567	uint64_t u32Base = X86DESC64_BASE(*pDesc);
1568
1569	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1570	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1571	# else
1572	uint32_t u32Base = X86DESC_BASE(*pDesc);
1573
1574	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1575	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1576	# endif
1577	}
1578
1579	/**
1580	* Formats a full register dump.
1581	*
1582	* @param pVM The VM to operate on.
1583	* @param pVCpu The VMCPU to operate on.
1584	* @param pCtx The context to format.
1585	*/
1586	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1587	{
1588	/*
1589	* Format the flags.
1590	*/
1591	static struct
1592	{
1593	const char pszSet; const char pszClear; uint32_t fFlag;
1594	} aFlags[] =
1595	{
1596	{ "vip",NULL, X86_EFL_VIP },
1597	{ "vif",NULL, X86_EFL_VIF },
1598	{ "ac", NULL, X86_EFL_AC },
1599	{ "vm", NULL, X86_EFL_VM },
1600	{ "rf", NULL, X86_EFL_RF },
1601	{ "nt", NULL, X86_EFL_NT },
1602	{ "ov", "nv", X86_EFL_OF },
1603	{ "dn", "up", X86_EFL_DF },
1604	{ "ei", "di", X86_EFL_IF },
1605	{ "tf", NULL, X86_EFL_TF },
1606	{ "nt", "pl", X86_EFL_SF },
1607	{ "nz", "zr", X86_EFL_ZF },
1608	{ "ac", "na", X86_EFL_AF },
1609	{ "po", "pe", X86_EFL_PF },
1610	{ "cy", "nc", X86_EFL_CF },
1611	};
1612	char szEFlags[80];
1613	char *psz = szEFlags;
1614	uint32_t efl = pCtx->eflags.u32;
1615	for (unsigned i = 0; i < RT_ELEMENTS(aFlags); i++)
1616	{
1617	const char *pszAdd = aFlags[i].fFlag & efl ? aFlags[i].pszSet : aFlags[i].pszClear;
1618	if (pszAdd)
1619	{
1620	strcpy(psz, pszAdd);
1621	psz += strlen(pszAdd);
1622	*psz++ = ' ';
1623	}
1624	}
1625	psz[-1] = '\0';
1626
1627
1628	/*
1629	* Format the registers.
1630	*/
1631	if (CPUMIsGuestIn64BitCode(pVCpu, CPUMCTX2CORE(pCtx)))
1632	{
1633	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1634	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1635	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1636	"r14=%016RX64 r15=%016RX64\n"
1637	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1638	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1639	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1640	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1641	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1642	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1643	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1644	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1645	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1646	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1647	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1648	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1649	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1650	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1651	,
1652	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1653	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1654	pCtx->r14, pCtx->r15,
1655	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1656	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
1657	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
1658	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
1659	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
1660	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
1661	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
1662	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1663	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1664	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1665	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1666	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1667	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1668	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1669	}
1670	else
1671	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1672	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1673	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1674	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1675	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1676	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1677	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1678	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1679	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1680	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1681	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1682	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1683	,
1684	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1685	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
1686	(RTSEL)pCtx->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pCtx->dr[0], pCtx->dr[1],
1687	(RTSEL)pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pCtx->dr[2], pCtx->dr[3],
1688	(RTSEL)pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pCtx->dr[4], pCtx->dr[5],
1689	(RTSEL)pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pCtx->dr[6], pCtx->dr[7],
1690	(RTSEL)pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pCtx->cr0, pCtx->cr2,
1691	(RTSEL)pCtx->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pCtx->cr3, pCtx->cr4,
1692	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
1693	(RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
1694	(RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
1695	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1696
1697	Log(("FPU:\n"
1698	"FCW=%04x FSW=%04x FTW=%02x\n"
1699	"FOP=%04x FPUIP=%08x CS=%04x Rsvrd1=%04x\n"
1700	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1701	,
1702	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1703	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsvrd1,
1704	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1705	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1706
1707
1708	Log(("MSR:\n"
1709	"EFER =%016RX64\n"
1710	"PAT =%016RX64\n"
1711	"STAR =%016RX64\n"
1712	"CSTAR =%016RX64\n"
1713	"LSTAR =%016RX64\n"
1714	"SFMASK =%016RX64\n"
1715	"KERNELGSBASE =%016RX64\n",
1716	pCtx->msrEFER,
1717	pCtx->msrPAT,
1718	pCtx->msrSTAR,
1719	pCtx->msrCSTAR,
1720	pCtx->msrLSTAR,
1721	pCtx->msrSFMASK,
1722	pCtx->msrKERNELGSBASE));
1723
1724	}
1725	#endif /* VBOX_STRICT */
1726
1727	/* Dummy callback handlers. */
1728	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu)
1729	{
1730	return VINF_SUCCESS;
1731	}
1732
1733	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1734	{
1735	return VINF_SUCCESS;
1736	}
1737
1738	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1739	{
1740	return VINF_SUCCESS;
1741	}
1742
1743	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
1744	{
1745	return VINF_SUCCESS;
1746	}
1747
1748	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM)
1749	{
1750	return VINF_SUCCESS;
1751	}
1752
1753	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM)
1754	{
1755	return VINF_SUCCESS;
1756	}
1757
1758	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM)
1759	{
1760	return VINF_SUCCESS;
1761	}
1762
1763	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1764	{
1765	return VINF_SUCCESS;
1766	}
1767
1768	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
1769	{
1770	return VINF_SUCCESS;
1771	}
1772
1773	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1774	{
1775	return VINF_SUCCESS;
1776	}

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source: vbox/trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp@ 25193

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