VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp@ 76042

Last change on this file since 76042 was 76042, checked in by vboxsync, 6 years ago

VMM/HMVMXR0: Nested VMX: bugref:9180 Guest/nested-guest state fixes and missing VMLAUNCH/VMRESUME calls to IEM.
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1/* $Id: HMVMXR0.cpp 76042 2018-12-07 08:36:12Z vboxsync $ */
2/** @file
3 * HM VMX (Intel VT-x) - Host Context Ring-0.
4 */
5
6/*
7 * Copyright (C) 2012-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_HM
23#define VMCPU_INCL_CPUM_GST_CTX
24#include <iprt/x86.h>
25#include <iprt/asm-amd64-x86.h>
26#include <iprt/thread.h>
27
28#include <VBox/vmm/pdmapi.h>
29#include <VBox/vmm/dbgf.h>
30#include <VBox/vmm/iem.h>
31#include <VBox/vmm/iom.h>
32#include <VBox/vmm/selm.h>
33#include <VBox/vmm/tm.h>
34#include <VBox/vmm/em.h>
35#include <VBox/vmm/gim.h>
36#include <VBox/vmm/apic.h>
37#ifdef VBOX_WITH_REM
38# include <VBox/vmm/rem.h>
39#endif
40#include "HMInternal.h"
41#include <VBox/vmm/vm.h>
42#include "HMVMXR0.h"
43#include "dtrace/VBoxVMM.h"
44
45#ifdef DEBUG_ramshankar
46# define HMVMX_ALWAYS_SAVE_GUEST_RFLAGS
47# define HMVMX_ALWAYS_SAVE_FULL_GUEST_STATE
48# define HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE
49# define HMVMX_ALWAYS_CHECK_GUEST_STATE
50# define HMVMX_ALWAYS_TRAP_ALL_XCPTS
51# define HMVMX_ALWAYS_TRAP_PF
52# define HMVMX_ALWAYS_FLUSH_TLB
53# define HMVMX_ALWAYS_SWAP_EFER
54#endif
55
56
57/*********************************************************************************************************************************
58* Defined Constants And Macros *
59*********************************************************************************************************************************/
60/** Use the function table. */
61#define HMVMX_USE_FUNCTION_TABLE
62
63/** Determine which tagged-TLB flush handler to use. */
64#define HMVMX_FLUSH_TAGGED_TLB_EPT_VPID 0
65#define HMVMX_FLUSH_TAGGED_TLB_EPT 1
66#define HMVMX_FLUSH_TAGGED_TLB_VPID 2
67#define HMVMX_FLUSH_TAGGED_TLB_NONE 3
68
69/** @name HMVMX_READ_XXX
70 * Flags to skip redundant reads of some common VMCS fields that are not part of
71 * the guest-CPU or VCPU state but are needed while handling VM-exits.
72 */
73#define HMVMX_READ_IDT_VECTORING_INFO RT_BIT_32(0)
74#define HMVMX_READ_IDT_VECTORING_ERROR_CODE RT_BIT_32(1)
75#define HMVMX_READ_EXIT_QUALIFICATION RT_BIT_32(2)
76#define HMVMX_READ_EXIT_INSTR_LEN RT_BIT_32(3)
77#define HMVMX_READ_EXIT_INTERRUPTION_INFO RT_BIT_32(4)
78#define HMVMX_READ_EXIT_INTERRUPTION_ERROR_CODE RT_BIT_32(5)
79#define HMVMX_READ_EXIT_INSTR_INFO RT_BIT_32(6)
80#define HMVMX_READ_GUEST_LINEAR_ADDR RT_BIT_32(7)
81/** @} */
82
83/**
84 * States of the VMCS.
85 *
86 * This does not reflect all possible VMCS states but currently only those
87 * needed for maintaining the VMCS consistently even when thread-context hooks
88 * are used. Maybe later this can be extended (i.e. Nested Virtualization).
89 */
90#define HMVMX_VMCS_STATE_CLEAR RT_BIT(0)
91#define HMVMX_VMCS_STATE_ACTIVE RT_BIT(1)
92#define HMVMX_VMCS_STATE_LAUNCHED RT_BIT(2)
93
94/**
95 * Subset of the guest-CPU state that is kept by VMX R0 code while executing the
96 * guest using hardware-assisted VMX.
97 *
98 * This excludes state like GPRs (other than RSP) which are always are
99 * swapped and restored across the world-switch and also registers like EFER,
100 * MSR which cannot be modified by the guest without causing a VM-exit.
101 */
102#define HMVMX_CPUMCTX_EXTRN_ALL ( CPUMCTX_EXTRN_RIP \
103 | CPUMCTX_EXTRN_RFLAGS \
104 | CPUMCTX_EXTRN_RSP \
105 | CPUMCTX_EXTRN_SREG_MASK \
106 | CPUMCTX_EXTRN_TABLE_MASK \
107 | CPUMCTX_EXTRN_KERNEL_GS_BASE \
108 | CPUMCTX_EXTRN_SYSCALL_MSRS \
109 | CPUMCTX_EXTRN_SYSENTER_MSRS \
110 | CPUMCTX_EXTRN_TSC_AUX \
111 | CPUMCTX_EXTRN_OTHER_MSRS \
112 | CPUMCTX_EXTRN_CR0 \
113 | CPUMCTX_EXTRN_CR3 \
114 | CPUMCTX_EXTRN_CR4 \
115 | CPUMCTX_EXTRN_DR7 \
116 | CPUMCTX_EXTRN_HM_VMX_MASK)
117
118/**
119 * Exception bitmap mask for real-mode guests (real-on-v86).
120 *
121 * We need to intercept all exceptions manually except:
122 * - \#AC and \#DB are always intercepted to prevent the CPU from deadlocking
123 * due to bugs in Intel CPUs.
124 * - \#PF need not be intercepted even in real-mode if we have Nested Paging
125 * support.
126 */
127#define HMVMX_REAL_MODE_XCPT_MASK ( RT_BIT(X86_XCPT_DE) /* always: | RT_BIT(X86_XCPT_DB) */ | RT_BIT(X86_XCPT_NMI) \
128 | RT_BIT(X86_XCPT_BP) | RT_BIT(X86_XCPT_OF) | RT_BIT(X86_XCPT_BR) \
129 | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_DF) \
130 | RT_BIT(X86_XCPT_CO_SEG_OVERRUN) | RT_BIT(X86_XCPT_TS) | RT_BIT(X86_XCPT_NP) \
131 | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) /* RT_BIT(X86_XCPT_PF) */ \
132 | RT_BIT(X86_XCPT_MF) /* always: | RT_BIT(X86_XCPT_AC) */ | RT_BIT(X86_XCPT_MC) \
133 | RT_BIT(X86_XCPT_XF))
134
135/** Maximum VM-instruction error number. */
136#define HMVMX_INSTR_ERROR_MAX 28
137
138/** Profiling macro. */
139#ifdef HM_PROFILE_EXIT_DISPATCH
140# define HMVMX_START_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitDispatch, ed)
141# define HMVMX_STOP_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitDispatch, ed)
142#else
143# define HMVMX_START_EXIT_DISPATCH_PROF() do { } while (0)
144# define HMVMX_STOP_EXIT_DISPATCH_PROF() do { } while (0)
145#endif
146
147/** Assert that preemption is disabled or covered by thread-context hooks. */
148#define HMVMX_ASSERT_PREEMPT_SAFE(a_pVCpu) Assert( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
149 || !RTThreadPreemptIsEnabled(NIL_RTTHREAD))
150
151/** Assert that we haven't migrated CPUs when thread-context hooks are not
152 * used. */
153#define HMVMX_ASSERT_CPU_SAFE(a_pVCpu) AssertMsg( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
154 || (a_pVCpu)->hm.s.idEnteredCpu == RTMpCpuId(), \
155 ("Illegal migration! Entered on CPU %u Current %u\n", \
156 (a_pVCpu)->hm.s.idEnteredCpu, RTMpCpuId()))
157
158/** Asserts that the given CPUMCTX_EXTRN_XXX bits are present in the guest-CPU
159 * context. */
160#define HMVMX_CPUMCTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
161 ("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", \
162 (a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz)))
163
164/** Macro for importing guest state from the VMCS back into CPUMCTX (intended to be
165 * used only from VM-exit handlers). */
166#define HMVMX_CPUMCTX_IMPORT_STATE(a_pVCpu, a_fWhat) (hmR0VmxImportGuestState((a_pVCpu), (a_fWhat)))
167
168/** Helper macro for VM-exit handlers called unexpectedly. */
169#define HMVMX_UNEXPECTED_EXIT_RET(a_pVCpu, a_pVmxTransient) \
170 do { \
171 (a_pVCpu)->hm.s.u32HMError = (a_pVmxTransient)->uExitReason; \
172 return VERR_VMX_UNEXPECTED_EXIT; \
173 } while (0)
174
175/** Macro for importing segment registers to the VMCS from the guest-CPU context. */
176#ifdef VMX_USE_CACHED_VMCS_ACCESSES
177# define HMVMX_IMPORT_SREG(Sel, a_pCtxSelReg) \
178 hmR0VmxImportGuestSegmentReg(pVCpu, VMX_VMCS16_GUEST_##Sel##_SEL, VMX_VMCS32_GUEST_##Sel##_LIMIT, \
179 VMX_VMCS_GUEST_##Sel##_BASE_CACHE_IDX, VMX_VMCS32_GUEST_##Sel##_ACCESS_RIGHTS, (a_pCtxSelReg))
180#else
181# define HMVMX_IMPORT_SREG(Sel, a_pCtxSelReg) \
182 hmR0VmxImportGuestSegmentReg(pVCpu, VMX_VMCS16_GUEST_##Sel##_SEL, VMX_VMCS32_GUEST_##Sel##_LIMIT, \
183 VMX_VMCS_GUEST_##Sel##_BASE, VMX_VMCS32_GUEST_##Sel##_ACCESS_RIGHTS, (a_pCtxSelReg))
184#endif
185
186/** Macro for exporting segment registers to the VMCS from the guest-CPU context. */
187#define HMVMX_EXPORT_SREG(Sel, a_pCtxSelReg) \
188 hmR0VmxExportGuestSegmentReg(pVCpu, VMX_VMCS16_GUEST_##Sel##_SEL, VMX_VMCS32_GUEST_##Sel##_LIMIT, \
189 VMX_VMCS_GUEST_##Sel##_BASE, VMX_VMCS32_GUEST_##Sel##_ACCESS_RIGHTS, (a_pCtxSelReg))
190
191#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
192/** Macro that does the necessary privilege checks and intercepted VM-exits for
193 * guests that attempted to execute a VMX instruction. */
194# define HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(a_pVCpu, a_uExitReason) \
195 do \
196 { \
197 VBOXSTRICTRC rcStrictTmp = hmR0VmxCheckExitDueToVmxInstr((a_pVCpu), (a_uExitReason)); \
198 if (rcStrictTmp == VINF_SUCCESS) \
199 { /* likely */ } \
200 else if (rcStrictTmp == VINF_HM_PENDING_XCPT) \
201 { \
202 Assert((a_pVCpu)->hm.s.Event.fPending); \
203 Log4Func(("Privilege checks failed -> %#x\n", VMX_ENTRY_INT_INFO_VECTOR((a_pVCpu)->hm.s.Event.u64IntInfo))); \
204 return VINF_SUCCESS; \
205 } \
206 else \
207 { \
208 int rcTmp = VBOXSTRICTRC_VAL(rcStrictTmp); \
209 AssertMsgFailedReturn(("Unexpected failure. rc=%Rrc", rcTmp), rcTmp); \
210 } \
211 } while (0)
212
213/** Macro that decodes a memory operand for an instruction VM-exit. */
214# define HMVMX_DECODE_MEM_OPERAND(a_pVCpu, a_uExitInstrInfo, a_uExitQual, a_enmMemAccess, a_pGCPtrEffAddr) \
215 do \
216 { \
217 VBOXSTRICTRC rcStrictTmp = hmR0VmxDecodeMemOperand((a_pVCpu), (a_uExitInstrInfo), (a_uExitQual), (a_enmMemAccess), \
218 (a_pGCPtrEffAddr)); \
219 if (rcStrictTmp == VINF_SUCCESS) \
220 { /* likely */ } \
221 else if (rcStrictTmp == VINF_HM_PENDING_XCPT) \
222 { \
223 uint8_t const uXcptTmp = VMX_ENTRY_INT_INFO_VECTOR((a_pVCpu)->hm.s.Event.u64IntInfo); \
224 Log4Func(("Memory operand decoding failed, raising xcpt %#x\n", uXcptTmp)); \
225 return VINF_SUCCESS; \
226 } \
227 else \
228 { \
229 Log4Func(("hmR0VmxCheckExitDueToVmxInstr failed. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrictTmp))); \
230 return rcStrictTmp; \
231 } \
232 } while (0)
233
234#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
235
236
237/*********************************************************************************************************************************
238* Structures and Typedefs *
239*********************************************************************************************************************************/
240/**
241 * VMX transient state.
242 *
243 * A state structure for holding miscellaneous information across
244 * VMX non-root operation and restored after the transition.
245 */
246typedef struct VMXTRANSIENT
247{
248 /** The host's rflags/eflags. */
249 RTCCUINTREG fEFlags;
250#if HC_ARCH_BITS == 32
251 uint32_t u32Alignment0;
252#endif
253 /** The guest's TPR value used for TPR shadowing. */
254 uint8_t u8GuestTpr;
255 /** Alignment. */
256 uint8_t abAlignment0[7];
257
258 /** The basic VM-exit reason. */
259 uint16_t uExitReason;
260 /** Alignment. */
261 uint16_t u16Alignment0;
262 /** The VM-exit interruption error code. */
263 uint32_t uExitIntErrorCode;
264 /** The VM-exit exit code qualification. */
265 uint64_t uExitQual;
266 /** The Guest-linear address. */
267 uint64_t uGuestLinearAddr;
268
269 /** The VM-exit interruption-information field. */
270 uint32_t uExitIntInfo;
271 /** The VM-exit instruction-length field. */
272 uint32_t cbInstr;
273 /** The VM-exit instruction-information field. */
274 VMXEXITINSTRINFO ExitInstrInfo;
275 /** Whether the VM-entry failed or not. */
276 bool fVMEntryFailed;
277 /** Alignment. */
278 uint8_t abAlignment1[3];
279
280 /** The VM-entry interruption-information field. */
281 uint32_t uEntryIntInfo;
282 /** The VM-entry exception error code field. */
283 uint32_t uEntryXcptErrorCode;
284 /** The VM-entry instruction length field. */
285 uint32_t cbEntryInstr;
286
287 /** IDT-vectoring information field. */
288 uint32_t uIdtVectoringInfo;
289 /** IDT-vectoring error code. */
290 uint32_t uIdtVectoringErrorCode;
291
292 /** Mask of currently read VMCS fields; HMVMX_READ_XXX. */
293 uint32_t fVmcsFieldsRead;
294
295 /** Whether the guest debug state was active at the time of VM-exit. */
296 bool fWasGuestDebugStateActive;
297 /** Whether the hyper debug state was active at the time of VM-exit. */
298 bool fWasHyperDebugStateActive;
299 /** Whether TSC-offsetting should be setup before VM-entry. */
300 bool fUpdateTscOffsettingAndPreemptTimer;
301 /** Whether the VM-exit was caused by a page-fault during delivery of a
302 * contributory exception or a page-fault. */
303 bool fVectoringDoublePF;
304 /** Whether the VM-exit was caused by a page-fault during delivery of an
305 * external interrupt or NMI. */
306 bool fVectoringPF;
307} VMXTRANSIENT;
308AssertCompileMemberAlignment(VMXTRANSIENT, uExitReason, sizeof(uint64_t));
309AssertCompileMemberAlignment(VMXTRANSIENT, uExitIntInfo, sizeof(uint64_t));
310AssertCompileMemberAlignment(VMXTRANSIENT, uEntryIntInfo, sizeof(uint64_t));
311AssertCompileMemberAlignment(VMXTRANSIENT, fWasGuestDebugStateActive, sizeof(uint64_t));
312AssertCompileMemberSize(VMXTRANSIENT, ExitInstrInfo, sizeof(uint32_t));
313/** Pointer to VMX transient state. */
314typedef VMXTRANSIENT *PVMXTRANSIENT;
315
316/**
317 * Memory operand read or write access.
318 */
319typedef enum VMXMEMACCESS
320{
321 VMXMEMACCESS_READ = 0,
322 VMXMEMACCESS_WRITE = 1
323} VMXMEMACCESS;
324
325/**
326 * VMX VM-exit handler.
327 *
328 * @returns Strict VBox status code (i.e. informational status codes too).
329 * @param pVCpu The cross context virtual CPU structure.
330 * @param pVmxTransient Pointer to the VMX-transient structure.
331 */
332#ifndef HMVMX_USE_FUNCTION_TABLE
333typedef VBOXSTRICTRC FNVMXEXITHANDLER(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
334#else
335typedef DECLCALLBACK(VBOXSTRICTRC) FNVMXEXITHANDLER(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
336/** Pointer to VM-exit handler. */
337typedef FNVMXEXITHANDLER *PFNVMXEXITHANDLER;
338#endif
339
340/**
341 * VMX VM-exit handler, non-strict status code.
342 *
343 * This is generally the same as FNVMXEXITHANDLER, the NSRC bit is just FYI.
344 *
345 * @returns VBox status code, no informational status code returned.
346 * @param pVCpu The cross context virtual CPU structure.
347 * @param pVmxTransient Pointer to the VMX-transient structure.
348 *
349 * @remarks This is not used on anything returning VERR_EM_INTERPRETER as the
350 * use of that status code will be replaced with VINF_EM_SOMETHING
351 * later when switching over to IEM.
352 */
353#ifndef HMVMX_USE_FUNCTION_TABLE
354typedef int FNVMXEXITHANDLERNSRC(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
355#else
356typedef FNVMXEXITHANDLER FNVMXEXITHANDLERNSRC;
357#endif
358
359
360/*********************************************************************************************************************************
361* Internal Functions *
362*********************************************************************************************************************************/
363static void hmR0VmxFlushEpt(PVMCPU pVCpu, VMXTLBFLUSHEPT enmTlbFlush);
364static void hmR0VmxFlushVpid(PVMCPU pVCpu, VMXTLBFLUSHVPID enmTlbFlush, RTGCPTR GCPtr);
365static void hmR0VmxClearIntNmiWindowsVmcs(PVMCPU pVCpu);
366static int hmR0VmxImportGuestState(PVMCPU pVCpu, uint64_t fWhat);
367static VBOXSTRICTRC hmR0VmxInjectEventVmcs(PVMCPU pVCpu, uint64_t u64IntInfo, uint32_t cbInstr, uint32_t u32ErrCode,
368 RTGCUINTREG GCPtrFaultAddress, bool fStepping, uint32_t *pfIntrState);
369#if HC_ARCH_BITS == 32
370static int hmR0VmxInitVmcsReadCache(PVMCPU pVCpu);
371#endif
372#ifndef HMVMX_USE_FUNCTION_TABLE
373DECLINLINE(VBOXSTRICTRC) hmR0VmxHandleExit(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, uint32_t rcReason);
374# define HMVMX_EXIT_DECL DECLINLINE(VBOXSTRICTRC)
375# define HMVMX_EXIT_NSRC_DECL DECLINLINE(int)
376#else
377# define HMVMX_EXIT_DECL static DECLCALLBACK(VBOXSTRICTRC)
378# define HMVMX_EXIT_NSRC_DECL HMVMX_EXIT_DECL
379#endif
380
381/** @name VM-exit handlers.
382 * @{
383 */
384static FNVMXEXITHANDLER hmR0VmxExitXcptOrNmi;
385static FNVMXEXITHANDLER hmR0VmxExitExtInt;
386static FNVMXEXITHANDLER hmR0VmxExitTripleFault;
387static FNVMXEXITHANDLERNSRC hmR0VmxExitInitSignal;
388static FNVMXEXITHANDLERNSRC hmR0VmxExitSipi;
389static FNVMXEXITHANDLERNSRC hmR0VmxExitIoSmi;
390static FNVMXEXITHANDLERNSRC hmR0VmxExitSmi;
391static FNVMXEXITHANDLERNSRC hmR0VmxExitIntWindow;
392static FNVMXEXITHANDLERNSRC hmR0VmxExitNmiWindow;
393static FNVMXEXITHANDLER hmR0VmxExitTaskSwitch;
394static FNVMXEXITHANDLER hmR0VmxExitCpuid;
395static FNVMXEXITHANDLER hmR0VmxExitGetsec;
396static FNVMXEXITHANDLER hmR0VmxExitHlt;
397static FNVMXEXITHANDLERNSRC hmR0VmxExitInvd;
398static FNVMXEXITHANDLER hmR0VmxExitInvlpg;
399static FNVMXEXITHANDLER hmR0VmxExitRdpmc;
400static FNVMXEXITHANDLER hmR0VmxExitVmcall;
401#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
402static FNVMXEXITHANDLER hmR0VmxExitVmclear;
403static FNVMXEXITHANDLER hmR0VmxExitVmlaunch;
404static FNVMXEXITHANDLER hmR0VmxExitVmptrld;
405static FNVMXEXITHANDLER hmR0VmxExitVmptrst;
406static FNVMXEXITHANDLER hmR0VmxExitVmread;
407static FNVMXEXITHANDLER hmR0VmxExitVmresume;
408static FNVMXEXITHANDLER hmR0VmxExitVmwrite;
409static FNVMXEXITHANDLER hmR0VmxExitVmxoff;
410static FNVMXEXITHANDLER hmR0VmxExitVmxon;
411#endif
412static FNVMXEXITHANDLER hmR0VmxExitRdtsc;
413static FNVMXEXITHANDLERNSRC hmR0VmxExitRsm;
414static FNVMXEXITHANDLERNSRC hmR0VmxExitSetPendingXcptUD;
415static FNVMXEXITHANDLER hmR0VmxExitMovCRx;
416static FNVMXEXITHANDLER hmR0VmxExitMovDRx;
417static FNVMXEXITHANDLER hmR0VmxExitIoInstr;
418static FNVMXEXITHANDLER hmR0VmxExitRdmsr;
419static FNVMXEXITHANDLER hmR0VmxExitWrmsr;
420static FNVMXEXITHANDLERNSRC hmR0VmxExitErrInvalidGuestState;
421static FNVMXEXITHANDLERNSRC hmR0VmxExitErrMsrLoad;
422static FNVMXEXITHANDLERNSRC hmR0VmxExitErrUndefined;
423static FNVMXEXITHANDLER hmR0VmxExitMwait;
424static FNVMXEXITHANDLER hmR0VmxExitMtf;
425static FNVMXEXITHANDLER hmR0VmxExitMonitor;
426static FNVMXEXITHANDLER hmR0VmxExitPause;
427static FNVMXEXITHANDLERNSRC hmR0VmxExitErrMachineCheck;
428static FNVMXEXITHANDLERNSRC hmR0VmxExitTprBelowThreshold;
429static FNVMXEXITHANDLER hmR0VmxExitApicAccess;
430static FNVMXEXITHANDLER hmR0VmxExitXdtrAccess;
431static FNVMXEXITHANDLER hmR0VmxExitEptViolation;
432static FNVMXEXITHANDLER hmR0VmxExitEptMisconfig;
433static FNVMXEXITHANDLER hmR0VmxExitRdtscp;
434static FNVMXEXITHANDLER hmR0VmxExitPreemptTimer;
435static FNVMXEXITHANDLERNSRC hmR0VmxExitWbinvd;
436static FNVMXEXITHANDLER hmR0VmxExitXsetbv;
437static FNVMXEXITHANDLER hmR0VmxExitRdrand;
438static FNVMXEXITHANDLER hmR0VmxExitInvpcid;
439/** @} */
440
441static int hmR0VmxExitXcptPF(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
442static int hmR0VmxExitXcptMF(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
443static int hmR0VmxExitXcptDB(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
444static int hmR0VmxExitXcptBP(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
445static int hmR0VmxExitXcptGP(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
446static int hmR0VmxExitXcptAC(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
447static int hmR0VmxExitXcptGeneric(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient);
448static uint32_t hmR0VmxCheckGuestState(PVMCPU pVCpu);
449
450
451/*********************************************************************************************************************************
452* Global Variables *
453*********************************************************************************************************************************/
454#ifdef HMVMX_USE_FUNCTION_TABLE
455
456/**
457 * VMX_EXIT dispatch table.
458 */
459static const PFNVMXEXITHANDLER g_apfnVMExitHandlers[VMX_EXIT_MAX + 1] =
460{
461 /* 00 VMX_EXIT_XCPT_OR_NMI */ hmR0VmxExitXcptOrNmi,
462 /* 01 VMX_EXIT_EXT_INT */ hmR0VmxExitExtInt,
463 /* 02 VMX_EXIT_TRIPLE_FAULT */ hmR0VmxExitTripleFault,
464 /* 03 VMX_EXIT_INIT_SIGNAL */ hmR0VmxExitInitSignal,
465 /* 04 VMX_EXIT_SIPI */ hmR0VmxExitSipi,
466 /* 05 VMX_EXIT_IO_SMI */ hmR0VmxExitIoSmi,
467 /* 06 VMX_EXIT_SMI */ hmR0VmxExitSmi,
468 /* 07 VMX_EXIT_INT_WINDOW */ hmR0VmxExitIntWindow,
469 /* 08 VMX_EXIT_NMI_WINDOW */ hmR0VmxExitNmiWindow,
470 /* 09 VMX_EXIT_TASK_SWITCH */ hmR0VmxExitTaskSwitch,
471 /* 10 VMX_EXIT_CPUID */ hmR0VmxExitCpuid,
472 /* 11 VMX_EXIT_GETSEC */ hmR0VmxExitGetsec,
473 /* 12 VMX_EXIT_HLT */ hmR0VmxExitHlt,
474 /* 13 VMX_EXIT_INVD */ hmR0VmxExitInvd,
475 /* 14 VMX_EXIT_INVLPG */ hmR0VmxExitInvlpg,
476 /* 15 VMX_EXIT_RDPMC */ hmR0VmxExitRdpmc,
477 /* 16 VMX_EXIT_RDTSC */ hmR0VmxExitRdtsc,
478 /* 17 VMX_EXIT_RSM */ hmR0VmxExitRsm,
479 /* 18 VMX_EXIT_VMCALL */ hmR0VmxExitVmcall,
480#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
481 /* 19 VMX_EXIT_VMCLEAR */ hmR0VmxExitVmclear,
482 /* 20 VMX_EXIT_VMLAUNCH */ hmR0VmxExitVmlaunch,
483 /* 21 VMX_EXIT_VMPTRLD */ hmR0VmxExitVmptrld,
484 /* 22 VMX_EXIT_VMPTRST */ hmR0VmxExitVmptrst,
485 /* 23 VMX_EXIT_VMREAD */ hmR0VmxExitVmread,
486 /* 24 VMX_EXIT_VMRESUME */ hmR0VmxExitVmresume,
487 /* 25 VMX_EXIT_VMWRITE */ hmR0VmxExitVmwrite,
488 /* 26 VMX_EXIT_VMXOFF */ hmR0VmxExitVmxoff,
489 /* 27 VMX_EXIT_VMXON */ hmR0VmxExitVmxon,
490#else
491 /* 19 VMX_EXIT_VMCLEAR */ hmR0VmxExitSetPendingXcptUD,
492 /* 20 VMX_EXIT_VMLAUNCH */ hmR0VmxExitSetPendingXcptUD,
493 /* 21 VMX_EXIT_VMPTRLD */ hmR0VmxExitSetPendingXcptUD,
494 /* 22 VMX_EXIT_VMPTRST */ hmR0VmxExitSetPendingXcptUD,
495 /* 23 VMX_EXIT_VMREAD */ hmR0VmxExitSetPendingXcptUD,
496 /* 24 VMX_EXIT_VMRESUME */ hmR0VmxExitSetPendingXcptUD,
497 /* 25 VMX_EXIT_VMWRITE */ hmR0VmxExitSetPendingXcptUD,
498 /* 26 VMX_EXIT_VMXOFF */ hmR0VmxExitSetPendingXcptUD,
499 /* 27 VMX_EXIT_VMXON */ hmR0VmxExitSetPendingXcptUD,
500#endif
501 /* 28 VMX_EXIT_MOV_CRX */ hmR0VmxExitMovCRx,
502 /* 29 VMX_EXIT_MOV_DRX */ hmR0VmxExitMovDRx,
503 /* 30 VMX_EXIT_IO_INSTR */ hmR0VmxExitIoInstr,
504 /* 31 VMX_EXIT_RDMSR */ hmR0VmxExitRdmsr,
505 /* 32 VMX_EXIT_WRMSR */ hmR0VmxExitWrmsr,
506 /* 33 VMX_EXIT_ERR_INVALID_GUEST_STATE */ hmR0VmxExitErrInvalidGuestState,
507 /* 34 VMX_EXIT_ERR_MSR_LOAD */ hmR0VmxExitErrMsrLoad,
508 /* 35 UNDEFINED */ hmR0VmxExitErrUndefined,
509 /* 36 VMX_EXIT_MWAIT */ hmR0VmxExitMwait,
510 /* 37 VMX_EXIT_MTF */ hmR0VmxExitMtf,
511 /* 38 UNDEFINED */ hmR0VmxExitErrUndefined,
512 /* 39 VMX_EXIT_MONITOR */ hmR0VmxExitMonitor,
513 /* 40 UNDEFINED */ hmR0VmxExitPause,
514 /* 41 VMX_EXIT_PAUSE */ hmR0VmxExitErrMachineCheck,
515 /* 42 VMX_EXIT_ERR_MACHINE_CHECK */ hmR0VmxExitErrUndefined,
516 /* 43 VMX_EXIT_TPR_BELOW_THRESHOLD */ hmR0VmxExitTprBelowThreshold,
517 /* 44 VMX_EXIT_APIC_ACCESS */ hmR0VmxExitApicAccess,
518 /* 45 UNDEFINED */ hmR0VmxExitErrUndefined,
519 /* 46 VMX_EXIT_GDTR_IDTR_ACCESS */ hmR0VmxExitXdtrAccess,
520 /* 47 VMX_EXIT_LDTR_TR_ACCESS */ hmR0VmxExitXdtrAccess,
521 /* 48 VMX_EXIT_EPT_VIOLATION */ hmR0VmxExitEptViolation,
522 /* 49 VMX_EXIT_EPT_MISCONFIG */ hmR0VmxExitEptMisconfig,
523 /* 50 VMX_EXIT_INVEPT */ hmR0VmxExitSetPendingXcptUD,
524 /* 51 VMX_EXIT_RDTSCP */ hmR0VmxExitRdtscp,
525 /* 52 VMX_EXIT_PREEMPT_TIMER */ hmR0VmxExitPreemptTimer,
526 /* 53 VMX_EXIT_INVVPID */ hmR0VmxExitSetPendingXcptUD,
527 /* 54 VMX_EXIT_WBINVD */ hmR0VmxExitWbinvd,
528 /* 55 VMX_EXIT_XSETBV */ hmR0VmxExitXsetbv,
529 /* 56 VMX_EXIT_APIC_WRITE */ hmR0VmxExitErrUndefined,
530 /* 57 VMX_EXIT_RDRAND */ hmR0VmxExitRdrand,
531 /* 58 VMX_EXIT_INVPCID */ hmR0VmxExitInvpcid,
532 /* 59 VMX_EXIT_VMFUNC */ hmR0VmxExitSetPendingXcptUD,
533 /* 60 VMX_EXIT_ENCLS */ hmR0VmxExitErrUndefined,
534 /* 61 VMX_EXIT_RDSEED */ hmR0VmxExitErrUndefined, /* only spurious exits, so undefined */
535 /* 62 VMX_EXIT_PML_FULL */ hmR0VmxExitErrUndefined,
536 /* 63 VMX_EXIT_XSAVES */ hmR0VmxExitSetPendingXcptUD,
537 /* 64 VMX_EXIT_XRSTORS */ hmR0VmxExitSetPendingXcptUD,
538};
539#endif /* HMVMX_USE_FUNCTION_TABLE */
540
541#if defined(VBOX_STRICT) && defined(LOG_ENABLED)
542static const char * const g_apszVmxInstrErrors[HMVMX_INSTR_ERROR_MAX + 1] =
543{
544 /* 0 */ "(Not Used)",
545 /* 1 */ "VMCALL executed in VMX root operation.",
546 /* 2 */ "VMCLEAR with invalid physical address.",
547 /* 3 */ "VMCLEAR with VMXON pointer.",
548 /* 4 */ "VMLAUNCH with non-clear VMCS.",
549 /* 5 */ "VMRESUME with non-launched VMCS.",
550 /* 6 */ "VMRESUME after VMXOFF",
551 /* 7 */ "VM-entry with invalid control fields.",
552 /* 8 */ "VM-entry with invalid host state fields.",
553 /* 9 */ "VMPTRLD with invalid physical address.",
554 /* 10 */ "VMPTRLD with VMXON pointer.",
555 /* 11 */ "VMPTRLD with incorrect revision identifier.",
556 /* 12 */ "VMREAD/VMWRITE from/to unsupported VMCS component.",
557 /* 13 */ "VMWRITE to read-only VMCS component.",
558 /* 14 */ "(Not Used)",
559 /* 15 */ "VMXON executed in VMX root operation.",
560 /* 16 */ "VM-entry with invalid executive-VMCS pointer.",
561 /* 17 */ "VM-entry with non-launched executing VMCS.",
562 /* 18 */ "VM-entry with executive-VMCS pointer not VMXON pointer.",
563 /* 19 */ "VMCALL with non-clear VMCS.",
564 /* 20 */ "VMCALL with invalid VM-exit control fields.",
565 /* 21 */ "(Not Used)",
566 /* 22 */ "VMCALL with incorrect MSEG revision identifier.",
567 /* 23 */ "VMXOFF under dual monitor treatment of SMIs and SMM.",
568 /* 24 */ "VMCALL with invalid SMM-monitor features.",
569 /* 25 */ "VM-entry with invalid VM-execution control fields in executive VMCS.",
570 /* 26 */ "VM-entry with events blocked by MOV SS.",
571 /* 27 */ "(Not Used)",
572 /* 28 */ "Invalid operand to INVEPT/INVVPID."
573};
574#endif /* VBOX_STRICT */
575
576
577/**
578 * Updates the VM's last error record.
579 *
580 * If there was a VMX instruction error, reads the error data from the VMCS and
581 * updates VCPU's last error record as well.
582 *
583 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
584 * Can be NULL if @a rc is not VERR_VMX_UNABLE_TO_START_VM or
585 * VERR_VMX_INVALID_VMCS_FIELD.
586 * @param rc The error code.
587 */
588static void hmR0VmxUpdateErrorRecord(PVMCPU pVCpu, int rc)
589{
590 if ( rc == VERR_VMX_INVALID_VMCS_FIELD
591 || rc == VERR_VMX_UNABLE_TO_START_VM)
592 {
593 AssertPtrReturnVoid(pVCpu);
594 VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError);
595 }
596 pVCpu->CTX_SUFF(pVM)->hm.s.rcInit = rc;
597}
598
599
600/**
601 * Reads the VM-entry interruption-information field from the VMCS into the VMX
602 * transient structure.
603 *
604 * @returns VBox status code.
605 * @param pVmxTransient Pointer to the VMX transient structure.
606 *
607 * @remarks No-long-jump zone!!!
608 */
609DECLINLINE(int) hmR0VmxReadEntryIntInfoVmcs(PVMXTRANSIENT pVmxTransient)
610{
611 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &pVmxTransient->uEntryIntInfo);
612 AssertRCReturn(rc, rc);
613 return VINF_SUCCESS;
614}
615
616#ifdef VBOX_STRICT
617/**
618 * Reads the VM-entry exception error code field from the VMCS into
619 * the VMX transient structure.
620 *
621 * @returns VBox status code.
622 * @param pVmxTransient Pointer to the VMX transient structure.
623 *
624 * @remarks No-long-jump zone!!!
625 */
626DECLINLINE(int) hmR0VmxReadEntryXcptErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
627{
628 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, &pVmxTransient->uEntryXcptErrorCode);
629 AssertRCReturn(rc, rc);
630 return VINF_SUCCESS;
631}
632
633
634/**
635 * Reads the VM-entry exception error code field from the VMCS into
636 * the VMX transient structure.
637 *
638 * @returns VBox status code.
639 * @param pVmxTransient Pointer to the VMX transient structure.
640 *
641 * @remarks No-long-jump zone!!!
642 */
643DECLINLINE(int) hmR0VmxReadEntryInstrLenVmcs(PVMXTRANSIENT pVmxTransient)
644{
645 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, &pVmxTransient->cbEntryInstr);
646 AssertRCReturn(rc, rc);
647 return VINF_SUCCESS;
648}
649#endif /* VBOX_STRICT */
650
651
652/**
653 * Reads the VM-exit interruption-information field from the VMCS into the VMX
654 * transient structure.
655 *
656 * @returns VBox status code.
657 * @param pVmxTransient Pointer to the VMX transient structure.
658 */
659DECLINLINE(int) hmR0VmxReadExitIntInfoVmcs(PVMXTRANSIENT pVmxTransient)
660{
661 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_INTERRUPTION_INFO))
662 {
663 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &pVmxTransient->uExitIntInfo);
664 AssertRCReturn(rc,rc);
665 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_INTERRUPTION_INFO;
666 }
667 return VINF_SUCCESS;
668}
669
670
671/**
672 * Reads the VM-exit interruption error code from the VMCS into the VMX
673 * transient structure.
674 *
675 * @returns VBox status code.
676 * @param pVmxTransient Pointer to the VMX transient structure.
677 */
678DECLINLINE(int) hmR0VmxReadExitIntErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
679{
680 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_INTERRUPTION_ERROR_CODE))
681 {
682 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE, &pVmxTransient->uExitIntErrorCode);
683 AssertRCReturn(rc, rc);
684 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_INTERRUPTION_ERROR_CODE;
685 }
686 return VINF_SUCCESS;
687}
688
689
690/**
691 * Reads the VM-exit instruction length field from the VMCS into the VMX
692 * transient structure.
693 *
694 * @returns VBox status code.
695 * @param pVmxTransient Pointer to the VMX transient structure.
696 */
697DECLINLINE(int) hmR0VmxReadExitInstrLenVmcs(PVMXTRANSIENT pVmxTransient)
698{
699 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_INSTR_LEN))
700 {
701 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &pVmxTransient->cbInstr);
702 AssertRCReturn(rc, rc);
703 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_INSTR_LEN;
704 }
705 return VINF_SUCCESS;
706}
707
708
709/**
710 * Reads the VM-exit instruction-information field from the VMCS into
711 * the VMX transient structure.
712 *
713 * @returns VBox status code.
714 * @param pVmxTransient Pointer to the VMX transient structure.
715 */
716DECLINLINE(int) hmR0VmxReadExitInstrInfoVmcs(PVMXTRANSIENT pVmxTransient)
717{
718 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_INSTR_INFO))
719 {
720 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_INFO, &pVmxTransient->ExitInstrInfo.u);
721 AssertRCReturn(rc, rc);
722 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_INSTR_INFO;
723 }
724 return VINF_SUCCESS;
725}
726
727
728/**
729 * Reads the VM-exit Qualification from the VMCS into the VMX transient structure.
730 *
731 * @returns VBox status code.
732 * @param pVCpu The cross context virtual CPU structure of the
733 * calling EMT. (Required for the VMCS cache case.)
734 * @param pVmxTransient Pointer to the VMX transient structure.
735 */
736DECLINLINE(int) hmR0VmxReadExitQualVmcs(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
737{
738 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_EXIT_QUALIFICATION))
739 {
740 int rc = VMXReadVmcsGstN(VMX_VMCS_RO_EXIT_QUALIFICATION, &pVmxTransient->uExitQual); NOREF(pVCpu);
741 AssertRCReturn(rc, rc);
742 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_EXIT_QUALIFICATION;
743 }
744 return VINF_SUCCESS;
745}
746
747
748/**
749 * Reads the Guest-linear address from the VMCS into the VMX transient structure.
750 *
751 * @returns VBox status code.
752 * @param pVCpu The cross context virtual CPU structure of the
753 * calling EMT. (Required for the VMCS cache case.)
754 * @param pVmxTransient Pointer to the VMX transient structure.
755 */
756DECLINLINE(int) hmR0VmxReadGuestLinearAddrVmcs(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
757{
758 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_GUEST_LINEAR_ADDR))
759 {
760 int rc = VMXReadVmcsGstN(VMX_VMCS_RO_GUEST_LINEAR_ADDR, &pVmxTransient->uGuestLinearAddr); NOREF(pVCpu);
761 AssertRCReturn(rc, rc);
762 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_GUEST_LINEAR_ADDR;
763 }
764 return VINF_SUCCESS;
765}
766
767
768/**
769 * Reads the IDT-vectoring information field from the VMCS into the VMX
770 * transient structure.
771 *
772 * @returns VBox status code.
773 * @param pVmxTransient Pointer to the VMX transient structure.
774 *
775 * @remarks No-long-jump zone!!!
776 */
777DECLINLINE(int) hmR0VmxReadIdtVectoringInfoVmcs(PVMXTRANSIENT pVmxTransient)
778{
779 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_IDT_VECTORING_INFO))
780 {
781 int rc = VMXReadVmcs32(VMX_VMCS32_RO_IDT_VECTORING_INFO, &pVmxTransient->uIdtVectoringInfo);
782 AssertRCReturn(rc, rc);
783 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_IDT_VECTORING_INFO;
784 }
785 return VINF_SUCCESS;
786}
787
788
789/**
790 * Reads the IDT-vectoring error code from the VMCS into the VMX
791 * transient structure.
792 *
793 * @returns VBox status code.
794 * @param pVmxTransient Pointer to the VMX transient structure.
795 */
796DECLINLINE(int) hmR0VmxReadIdtVectoringErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
797{
798 if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_READ_IDT_VECTORING_ERROR_CODE))
799 {
800 int rc = VMXReadVmcs32(VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE, &pVmxTransient->uIdtVectoringErrorCode);
801 AssertRCReturn(rc, rc);
802 pVmxTransient->fVmcsFieldsRead |= HMVMX_READ_IDT_VECTORING_ERROR_CODE;
803 }
804 return VINF_SUCCESS;
805}
806
807
808/**
809 * Enters VMX root mode operation on the current CPU.
810 *
811 * @returns VBox status code.
812 * @param pVM The cross context VM structure. Can be
813 * NULL, after a resume.
814 * @param HCPhysCpuPage Physical address of the VMXON region.
815 * @param pvCpuPage Pointer to the VMXON region.
816 */
817static int hmR0VmxEnterRootMode(PVM pVM, RTHCPHYS HCPhysCpuPage, void *pvCpuPage)
818{
819 Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
820 Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
821 Assert(pvCpuPage);
822 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
823
824 if (pVM)
825 {
826 /* Write the VMCS revision dword to the VMXON region. */
827 *(uint32_t *)pvCpuPage = RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_ID);
828 }
829
830 /* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with CR4. */
831 RTCCUINTREG fEFlags = ASMIntDisableFlags();
832
833 /* Enable the VMX bit in CR4 if necessary. */
834 RTCCUINTREG uOldCr4 = SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
835
836 /* Enter VMX root mode. */
837 int rc = VMXEnable(HCPhysCpuPage);
838 if (RT_FAILURE(rc))
839 {
840 if (!(uOldCr4 & X86_CR4_VMXE))
841 SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
842
843 if (pVM)
844 pVM->hm.s.vmx.HCPhysVmxEnableError = HCPhysCpuPage;
845 }
846
847 /* Restore interrupts. */
848 ASMSetFlags(fEFlags);
849 return rc;
850}
851
852
853/**
854 * Exits VMX root mode operation on the current CPU.
855 *
856 * @returns VBox status code.
857 */
858static int hmR0VmxLeaveRootMode(void)
859{
860 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
861
862 /* Paranoid: Disable interrupts as, in theory, interrupts handlers might mess with CR4. */
863 RTCCUINTREG fEFlags = ASMIntDisableFlags();
864
865 /* If we're for some reason not in VMX root mode, then don't leave it. */
866 RTCCUINTREG uHostCR4 = ASMGetCR4();
867
868 int rc;
869 if (uHostCR4 & X86_CR4_VMXE)
870 {
871 /* Exit VMX root mode and clear the VMX bit in CR4. */
872 VMXDisable();
873 SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
874 rc = VINF_SUCCESS;
875 }
876 else
877 rc = VERR_VMX_NOT_IN_VMX_ROOT_MODE;
878
879 /* Restore interrupts. */
880 ASMSetFlags(fEFlags);
881 return rc;
882}
883
884
885/**
886 * Allocates and maps one physically contiguous page. The allocated page is
887 * zero'd out. (Used by various VT-x structures).
888 *
889 * @returns IPRT status code.
890 * @param pMemObj Pointer to the ring-0 memory object.
891 * @param ppVirt Where to store the virtual address of the
892 * allocation.
893 * @param pHCPhys Where to store the physical address of the
894 * allocation.
895 */
896static int hmR0VmxPageAllocZ(PRTR0MEMOBJ pMemObj, PRTR0PTR ppVirt, PRTHCPHYS pHCPhys)
897{
898 AssertPtrReturn(pMemObj, VERR_INVALID_PARAMETER);
899 AssertPtrReturn(ppVirt, VERR_INVALID_PARAMETER);
900 AssertPtrReturn(pHCPhys, VERR_INVALID_PARAMETER);
901
902 int rc = RTR0MemObjAllocCont(pMemObj, PAGE_SIZE, false /* fExecutable */);
903 if (RT_FAILURE(rc))
904 return rc;
905 *ppVirt = RTR0MemObjAddress(*pMemObj);
906 *pHCPhys = RTR0MemObjGetPagePhysAddr(*pMemObj, 0 /* iPage */);
907 ASMMemZero32(*ppVirt, PAGE_SIZE);
908 return VINF_SUCCESS;
909}
910
911
912/**
913 * Frees and unmaps an allocated physical page.
914 *
915 * @param pMemObj Pointer to the ring-0 memory object.
916 * @param ppVirt Where to re-initialize the virtual address of
917 * allocation as 0.
918 * @param pHCPhys Where to re-initialize the physical address of the
919 * allocation as 0.
920 */
921static void hmR0VmxPageFree(PRTR0MEMOBJ pMemObj, PRTR0PTR ppVirt, PRTHCPHYS pHCPhys)
922{
923 AssertPtr(pMemObj);
924 AssertPtr(ppVirt);
925 AssertPtr(pHCPhys);
926 if (*pMemObj != NIL_RTR0MEMOBJ)
927 {
928 int rc = RTR0MemObjFree(*pMemObj, true /* fFreeMappings */);
929 AssertRC(rc);
930 *pMemObj = NIL_RTR0MEMOBJ;
931 *ppVirt = 0;
932 *pHCPhys = 0;
933 }
934}
935
936
937/**
938 * Worker function to free VT-x related structures.
939 *
940 * @returns IPRT status code.
941 * @param pVM The cross context VM structure.
942 */
943static void hmR0VmxStructsFree(PVM pVM)
944{
945 for (VMCPUID i = 0; i < pVM->cCpus; i++)
946 {
947 PVMCPU pVCpu = &pVM->aCpus[i];
948 AssertPtr(pVCpu);
949
950 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjHostMsr, &pVCpu->hm.s.vmx.pvHostMsr, &pVCpu->hm.s.vmx.HCPhysHostMsr);
951 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjGuestMsr, &pVCpu->hm.s.vmx.pvGuestMsr, &pVCpu->hm.s.vmx.HCPhysGuestMsr);
952
953 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
954 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjMsrBitmap, &pVCpu->hm.s.vmx.pvMsrBitmap, &pVCpu->hm.s.vmx.HCPhysMsrBitmap);
955
956 hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjVmcs, &pVCpu->hm.s.vmx.pvVmcs, &pVCpu->hm.s.vmx.HCPhysVmcs);
957 }
958
959 hmR0VmxPageFree(&pVM->hm.s.vmx.hMemObjApicAccess, (PRTR0PTR)&pVM->hm.s.vmx.pbApicAccess, &pVM->hm.s.vmx.HCPhysApicAccess);
960#ifdef VBOX_WITH_CRASHDUMP_MAGIC
961 hmR0VmxPageFree(&pVM->hm.s.vmx.hMemObjScratch, &pVM->hm.s.vmx.pbScratch, &pVM->hm.s.vmx.HCPhysScratch);
962#endif
963}
964
965
966/**
967 * Worker function to allocate VT-x related VM structures.
968 *
969 * @returns IPRT status code.
970 * @param pVM The cross context VM structure.
971 */
972static int hmR0VmxStructsAlloc(PVM pVM)
973{
974 /*
975 * Initialize members up-front so we can cleanup properly on allocation failure.
976 */
977#define VMXLOCAL_INIT_VM_MEMOBJ(a_Name, a_VirtPrefix) \
978 pVM->hm.s.vmx.hMemObj##a_Name = NIL_RTR0MEMOBJ; \
979 pVM->hm.s.vmx.a_VirtPrefix##a_Name = 0; \
980 pVM->hm.s.vmx.HCPhys##a_Name = 0;
981
982#define VMXLOCAL_INIT_VMCPU_MEMOBJ(a_Name, a_VirtPrefix) \
983 pVCpu->hm.s.vmx.hMemObj##a_Name = NIL_RTR0MEMOBJ; \
984 pVCpu->hm.s.vmx.a_VirtPrefix##a_Name = 0; \
985 pVCpu->hm.s.vmx.HCPhys##a_Name = 0;
986
987#ifdef VBOX_WITH_CRASHDUMP_MAGIC
988 VMXLOCAL_INIT_VM_MEMOBJ(Scratch, pv);
989#endif
990 VMXLOCAL_INIT_VM_MEMOBJ(ApicAccess, pb);
991
992 AssertCompile(sizeof(VMCPUID) == sizeof(pVM->cCpus));
993 for (VMCPUID i = 0; i < pVM->cCpus; i++)
994 {
995 PVMCPU pVCpu = &pVM->aCpus[i];
996 VMXLOCAL_INIT_VMCPU_MEMOBJ(Vmcs, pv);
997 VMXLOCAL_INIT_VMCPU_MEMOBJ(MsrBitmap, pv);
998 VMXLOCAL_INIT_VMCPU_MEMOBJ(GuestMsr, pv);
999 VMXLOCAL_INIT_VMCPU_MEMOBJ(HostMsr, pv);
1000 }
1001#undef VMXLOCAL_INIT_VMCPU_MEMOBJ
1002#undef VMXLOCAL_INIT_VM_MEMOBJ
1003
1004 /* The VMCS size cannot be more than 4096 bytes. See Intel spec. Appendix A.1 "Basic VMX Information". */
1005 AssertReturnStmt(RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_SIZE) <= PAGE_SIZE,
1006 (&pVM->aCpus[0])->hm.s.u32HMError = VMX_UFC_INVALID_VMCS_SIZE,
1007 VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO);
1008
1009 /*
1010 * Allocate all the VT-x structures.
1011 */
1012 int rc = VINF_SUCCESS;
1013#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1014 rc = hmR0VmxPageAllocZ(&pVM->hm.s.vmx.hMemObjScratch, &pVM->hm.s.vmx.pbScratch, &pVM->hm.s.vmx.HCPhysScratch);
1015 if (RT_FAILURE(rc))
1016 goto cleanup;
1017 strcpy((char *)pVM->hm.s.vmx.pbScratch, "SCRATCH Magic");
1018 *(uint64_t *)(pVM->hm.s.vmx.pbScratch + 16) = UINT64_C(0xdeadbeefdeadbeef);
1019#endif
1020
1021 /* Allocate the APIC-access page for trapping APIC accesses from the guest. */
1022 if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
1023 {
1024 rc = hmR0VmxPageAllocZ(&pVM->hm.s.vmx.hMemObjApicAccess, (PRTR0PTR)&pVM->hm.s.vmx.pbApicAccess,
1025 &pVM->hm.s.vmx.HCPhysApicAccess);
1026 if (RT_FAILURE(rc))
1027 goto cleanup;
1028 }
1029
1030 /*
1031 * Initialize per-VCPU VT-x structures.
1032 */
1033 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1034 {
1035 PVMCPU pVCpu = &pVM->aCpus[i];
1036 AssertPtr(pVCpu);
1037
1038 /* Allocate the VM control structure (VMCS). */
1039 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjVmcs, &pVCpu->hm.s.vmx.pvVmcs, &pVCpu->hm.s.vmx.HCPhysVmcs);
1040 if (RT_FAILURE(rc))
1041 goto cleanup;
1042
1043 /* Get the allocated virtual-APIC page from the APIC device for transparent TPR accesses. */
1044 if ( PDMHasApic(pVM)
1045 && (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TPR_SHADOW))
1046 {
1047 rc = APICGetApicPageForCpu(pVCpu, &pVCpu->hm.s.vmx.HCPhysVirtApic, (PRTR0PTR)&pVCpu->hm.s.vmx.pbVirtApic,
1048 NULL /* pR3Ptr */, NULL /* pRCPtr */);
1049 if (RT_FAILURE(rc))
1050 goto cleanup;
1051 }
1052
1053 /*
1054 * Allocate the MSR-bitmap if supported by the CPU. The MSR-bitmap is for
1055 * transparent accesses of specific MSRs.
1056 *
1057 * If the condition for enabling MSR bitmaps changes here, don't forget to
1058 * update HMAreMsrBitmapsAvailable().
1059 */
1060 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
1061 {
1062 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjMsrBitmap, &pVCpu->hm.s.vmx.pvMsrBitmap,
1063 &pVCpu->hm.s.vmx.HCPhysMsrBitmap);
1064 if (RT_FAILURE(rc))
1065 goto cleanup;
1066 ASMMemFill32(pVCpu->hm.s.vmx.pvMsrBitmap, PAGE_SIZE, UINT32_C(0xffffffff));
1067 }
1068
1069 /* Allocate the VM-entry MSR-load and VM-exit MSR-store page for the guest MSRs. */
1070 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjGuestMsr, &pVCpu->hm.s.vmx.pvGuestMsr, &pVCpu->hm.s.vmx.HCPhysGuestMsr);
1071 if (RT_FAILURE(rc))
1072 goto cleanup;
1073
1074 /* Allocate the VM-exit MSR-load page for the host MSRs. */
1075 rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjHostMsr, &pVCpu->hm.s.vmx.pvHostMsr, &pVCpu->hm.s.vmx.HCPhysHostMsr);
1076 if (RT_FAILURE(rc))
1077 goto cleanup;
1078 }
1079
1080 return VINF_SUCCESS;
1081
1082cleanup:
1083 hmR0VmxStructsFree(pVM);
1084 return rc;
1085}
1086
1087
1088/**
1089 * Does global VT-x initialization (called during module initialization).
1090 *
1091 * @returns VBox status code.
1092 */
1093VMMR0DECL(int) VMXR0GlobalInit(void)
1094{
1095#ifdef HMVMX_USE_FUNCTION_TABLE
1096 AssertCompile(VMX_EXIT_MAX + 1 == RT_ELEMENTS(g_apfnVMExitHandlers));
1097# ifdef VBOX_STRICT
1098 for (unsigned i = 0; i < RT_ELEMENTS(g_apfnVMExitHandlers); i++)
1099 Assert(g_apfnVMExitHandlers[i]);
1100# endif
1101#endif
1102 return VINF_SUCCESS;
1103}
1104
1105
1106/**
1107 * Does global VT-x termination (called during module termination).
1108 */
1109VMMR0DECL(void) VMXR0GlobalTerm()
1110{
1111 /* Nothing to do currently. */
1112}
1113
1114
1115/**
1116 * Sets up and activates VT-x on the current CPU.
1117 *
1118 * @returns VBox status code.
1119 * @param pHostCpu Pointer to the global CPU info struct.
1120 * @param pVM The cross context VM structure. Can be
1121 * NULL after a host resume operation.
1122 * @param pvCpuPage Pointer to the VMXON region (can be NULL if @a
1123 * fEnabledByHost is @c true).
1124 * @param HCPhysCpuPage Physical address of the VMXON region (can be 0 if
1125 * @a fEnabledByHost is @c true).
1126 * @param fEnabledByHost Set if SUPR0EnableVTx() or similar was used to
1127 * enable VT-x on the host.
1128 * @param pvMsrs Opaque pointer to VMXMSRS struct.
1129 */
1130VMMR0DECL(int) VMXR0EnableCpu(PHMGLOBALCPUINFO pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
1131 void *pvMsrs)
1132{
1133 Assert(pHostCpu);
1134 Assert(pvMsrs);
1135 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1136
1137 /* Enable VT-x if it's not already enabled by the host. */
1138 if (!fEnabledByHost)
1139 {
1140 int rc = hmR0VmxEnterRootMode(pVM, HCPhysCpuPage, pvCpuPage);
1141 if (RT_FAILURE(rc))
1142 return rc;
1143 }
1144
1145 /*
1146 * Flush all EPT tagged-TLB entries (in case VirtualBox or any other hypervisor have been
1147 * using EPTPs) so we don't retain any stale guest-physical mappings which won't get
1148 * invalidated when flushing by VPID.
1149 */
1150 PVMXMSRS pMsrs = (PVMXMSRS)pvMsrs;
1151 if (pMsrs->u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
1152 {
1153 hmR0VmxFlushEpt(NULL /* pVCpu */, VMXTLBFLUSHEPT_ALL_CONTEXTS);
1154 pHostCpu->fFlushAsidBeforeUse = false;
1155 }
1156 else
1157 pHostCpu->fFlushAsidBeforeUse = true;
1158
1159 /* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}. */
1160 ++pHostCpu->cTlbFlushes;
1161
1162 return VINF_SUCCESS;
1163}
1164
1165
1166/**
1167 * Deactivates VT-x on the current CPU.
1168 *
1169 * @returns VBox status code.
1170 * @param pHostCpu Pointer to the global CPU info struct.
1171 * @param pvCpuPage Pointer to the VMXON region.
1172 * @param HCPhysCpuPage Physical address of the VMXON region.
1173 *
1174 * @remarks This function should never be called when SUPR0EnableVTx() or
1175 * similar was used to enable VT-x on the host.
1176 */
1177VMMR0DECL(int) VMXR0DisableCpu(PHMGLOBALCPUINFO pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
1178{
1179 RT_NOREF3(pHostCpu, pvCpuPage, HCPhysCpuPage);
1180
1181 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1182 return hmR0VmxLeaveRootMode();
1183}
1184
1185
1186/**
1187 * Sets the permission bits for the specified MSR in the MSR bitmap.
1188 *
1189 * @param pVCpu The cross context virtual CPU structure.
1190 * @param uMsr The MSR value.
1191 * @param enmRead Whether reading this MSR causes a VM-exit.
1192 * @param enmWrite Whether writing this MSR causes a VM-exit.
1193 */
1194static void hmR0VmxSetMsrPermission(PVMCPU pVCpu, uint32_t uMsr, VMXMSREXITREAD enmRead, VMXMSREXITWRITE enmWrite)
1195{
1196 int32_t iBit;
1197 uint8_t *pbMsrBitmap = (uint8_t *)pVCpu->hm.s.vmx.pvMsrBitmap;
1198
1199 /*
1200 * MSR Layout:
1201 * Byte index MSR range Interpreted as
1202 * 0x000 - 0x3ff 0x00000000 - 0x00001fff Low MSR read bits.
1203 * 0x400 - 0x7ff 0xc0000000 - 0xc0001fff High MSR read bits.
1204 * 0x800 - 0xbff 0x00000000 - 0x00001fff Low MSR write bits.
1205 * 0xc00 - 0xfff 0xc0000000 - 0xc0001fff High MSR write bits.
1206 *
1207 * A bit corresponding to an MSR within the above range causes a VM-exit
1208 * if the bit is 1 on executions of RDMSR/WRMSR.
1209 *
1210 * If an MSR falls out of the MSR range, it always cause a VM-exit.
1211 *
1212 * See Intel spec. 24.6.9 "MSR-Bitmap Address".
1213 */
1214 if (uMsr <= 0x00001fff)
1215 iBit = uMsr;
1216 else if (uMsr - UINT32_C(0xc0000000) <= UINT32_C(0x00001fff))
1217 {
1218 iBit = uMsr - UINT32_C(0xc0000000);
1219 pbMsrBitmap += 0x400;
1220 }
1221 else
1222 AssertMsgFailedReturnVoid(("hmR0VmxSetMsrPermission: Invalid MSR %#RX32\n", uMsr));
1223
1224 Assert(iBit <= 0x1fff);
1225 if (enmRead == VMXMSREXIT_INTERCEPT_READ)
1226 ASMBitSet(pbMsrBitmap, iBit);
1227 else
1228 ASMBitClear(pbMsrBitmap, iBit);
1229
1230 if (enmWrite == VMXMSREXIT_INTERCEPT_WRITE)
1231 ASMBitSet(pbMsrBitmap + 0x800, iBit);
1232 else
1233 ASMBitClear(pbMsrBitmap + 0x800, iBit);
1234}
1235
1236
1237/**
1238 * Updates the VMCS with the number of effective MSRs in the auto-load/store MSR
1239 * area.
1240 *
1241 * @returns VBox status code.
1242 * @param pVCpu The cross context virtual CPU structure.
1243 * @param cMsrs The number of MSRs.
1244 */
1245static int hmR0VmxSetAutoLoadStoreMsrCount(PVMCPU pVCpu, uint32_t cMsrs)
1246{
1247 /* Shouldn't ever happen but there -is- a number. We're well within the recommended 512. */
1248 uint64_t const uVmxMiscMsr = pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.u64Misc;
1249 uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(uVmxMiscMsr);
1250 if (RT_UNLIKELY(cMsrs > cMaxSupportedMsrs))
1251 {
1252 LogRel(("CPU auto-load/store MSR count in VMCS exceeded cMsrs=%u Supported=%u.\n", cMsrs, cMaxSupportedMsrs));
1253 pVCpu->hm.s.u32HMError = VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE;
1254 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
1255 }
1256
1257 /* Update number of guest MSRs to load/store across the world-switch. */
1258 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, cMsrs);
1259 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, cMsrs);
1260
1261 /* Update number of host MSRs to load after the world-switch. Identical to guest-MSR count as it's always paired. */
1262 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, cMsrs);
1263 AssertRCReturn(rc, rc);
1264
1265 /* Update the VCPU's copy of the MSR count. */
1266 pVCpu->hm.s.vmx.cMsrs = cMsrs;
1267
1268 return VINF_SUCCESS;
1269}
1270
1271
1272/**
1273 * Adds a new (or updates the value of an existing) guest/host MSR
1274 * pair to be swapped during the world-switch as part of the
1275 * auto-load/store MSR area in the VMCS.
1276 *
1277 * @returns VBox status code.
1278 * @param pVCpu The cross context virtual CPU structure.
1279 * @param uMsr The MSR.
1280 * @param uGuestMsrValue Value of the guest MSR.
1281 * @param fUpdateHostMsr Whether to update the value of the host MSR if
1282 * necessary.
1283 * @param pfAddedAndUpdated Where to store whether the MSR was added -and-
1284 * its value was updated. Optional, can be NULL.
1285 */
1286static int hmR0VmxAddAutoLoadStoreMsr(PVMCPU pVCpu, uint32_t uMsr, uint64_t uGuestMsrValue, bool fUpdateHostMsr,
1287 bool *pfAddedAndUpdated)
1288{
1289 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1290 uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1291 uint32_t i;
1292 for (i = 0; i < cMsrs; i++)
1293 {
1294 if (pGuestMsr->u32Msr == uMsr)
1295 break;
1296 pGuestMsr++;
1297 }
1298
1299 bool fAdded = false;
1300 if (i == cMsrs)
1301 {
1302 ++cMsrs;
1303 int rc = hmR0VmxSetAutoLoadStoreMsrCount(pVCpu, cMsrs);
1304 AssertMsgRCReturn(rc, ("hmR0VmxAddAutoLoadStoreMsr: Insufficient space to add MSR %u\n", uMsr), rc);
1305
1306 /* Now that we're swapping MSRs during the world-switch, allow the guest to read/write them without causing VM-exits. */
1307 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
1308 hmR0VmxSetMsrPermission(pVCpu, uMsr, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
1309
1310 fAdded = true;
1311 }
1312
1313 /* Update the MSR values in the auto-load/store MSR area. */
1314 pGuestMsr->u32Msr = uMsr;
1315 pGuestMsr->u64Value = uGuestMsrValue;
1316
1317 /* Create/update the MSR slot in the host MSR area. */
1318 PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1319 pHostMsr += i;
1320 pHostMsr->u32Msr = uMsr;
1321
1322 /*
1323 * Update the host MSR only when requested by the caller AND when we're
1324 * adding it to the auto-load/store area. Otherwise, it would have been
1325 * updated by hmR0VmxExportHostMsrs(). We do this for performance reasons.
1326 */
1327 bool fUpdatedMsrValue = false;
1328 if ( fAdded
1329 && fUpdateHostMsr)
1330 {
1331 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1332 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1333 pHostMsr->u64Value = ASMRdMsr(pHostMsr->u32Msr);
1334 fUpdatedMsrValue = true;
1335 }
1336
1337 if (pfAddedAndUpdated)
1338 *pfAddedAndUpdated = fUpdatedMsrValue;
1339 return VINF_SUCCESS;
1340}
1341
1342
1343/**
1344 * Removes a guest/host MSR pair to be swapped during the world-switch from the
1345 * auto-load/store MSR area in the VMCS.
1346 *
1347 * @returns VBox status code.
1348 * @param pVCpu The cross context virtual CPU structure.
1349 * @param uMsr The MSR.
1350 */
1351static int hmR0VmxRemoveAutoLoadStoreMsr(PVMCPU pVCpu, uint32_t uMsr)
1352{
1353 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1354 uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1355 for (uint32_t i = 0; i < cMsrs; i++)
1356 {
1357 /* Find the MSR. */
1358 if (pGuestMsr->u32Msr == uMsr)
1359 {
1360 /* If it's the last MSR, simply reduce the count. */
1361 if (i == cMsrs - 1)
1362 {
1363 --cMsrs;
1364 break;
1365 }
1366
1367 /* Remove it by swapping the last MSR in place of it, and reducing the count. */
1368 PVMXAUTOMSR pLastGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1369 pLastGuestMsr += cMsrs - 1;
1370 pGuestMsr->u32Msr = pLastGuestMsr->u32Msr;
1371 pGuestMsr->u64Value = pLastGuestMsr->u64Value;
1372
1373 PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1374 PVMXAUTOMSR pLastHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1375 pLastHostMsr += cMsrs - 1;
1376 pHostMsr->u32Msr = pLastHostMsr->u32Msr;
1377 pHostMsr->u64Value = pLastHostMsr->u64Value;
1378 --cMsrs;
1379 break;
1380 }
1381 pGuestMsr++;
1382 }
1383
1384 /* Update the VMCS if the count changed (meaning the MSR was found). */
1385 if (cMsrs != pVCpu->hm.s.vmx.cMsrs)
1386 {
1387 int rc = hmR0VmxSetAutoLoadStoreMsrCount(pVCpu, cMsrs);
1388 AssertRCReturn(rc, rc);
1389
1390 /* We're no longer swapping MSRs during the world-switch, intercept guest read/writes to them. */
1391 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
1392 hmR0VmxSetMsrPermission(pVCpu, uMsr, VMXMSREXIT_INTERCEPT_READ, VMXMSREXIT_INTERCEPT_WRITE);
1393
1394 Log4Func(("Removed MSR %#RX32 new cMsrs=%u\n", uMsr, pVCpu->hm.s.vmx.cMsrs));
1395 return VINF_SUCCESS;
1396 }
1397
1398 return VERR_NOT_FOUND;
1399}
1400
1401
1402/**
1403 * Checks if the specified guest MSR is part of the auto-load/store area in
1404 * the VMCS.
1405 *
1406 * @returns true if found, false otherwise.
1407 * @param pVCpu The cross context virtual CPU structure.
1408 * @param uMsr The MSR to find.
1409 */
1410static bool hmR0VmxIsAutoLoadStoreGuestMsr(PVMCPU pVCpu, uint32_t uMsr)
1411{
1412 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1413 uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1414
1415 for (uint32_t i = 0; i < cMsrs; i++, pGuestMsr++)
1416 {
1417 if (pGuestMsr->u32Msr == uMsr)
1418 return true;
1419 }
1420 return false;
1421}
1422
1423
1424/**
1425 * Updates the value of all host MSRs in the auto-load/store area in the VMCS.
1426 *
1427 * @param pVCpu The cross context virtual CPU structure.
1428 *
1429 * @remarks No-long-jump zone!!!
1430 */
1431static void hmR0VmxUpdateAutoLoadStoreHostMsrs(PVMCPU pVCpu)
1432{
1433 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1434 PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1435 PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1436 uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1437
1438 for (uint32_t i = 0; i < cMsrs; i++, pHostMsr++, pGuestMsr++)
1439 {
1440 AssertReturnVoid(pHostMsr->u32Msr == pGuestMsr->u32Msr);
1441
1442 /*
1443 * Performance hack for the host EFER MSR. We use the cached value rather than re-read it.
1444 * Strict builds will catch mismatches in hmR0VmxCheckAutoLoadStoreMsrs(). See @bugref{7368}.
1445 */
1446 if (pHostMsr->u32Msr == MSR_K6_EFER)
1447 pHostMsr->u64Value = pVCpu->CTX_SUFF(pVM)->hm.s.vmx.u64HostEfer;
1448 else
1449 pHostMsr->u64Value = ASMRdMsr(pHostMsr->u32Msr);
1450 }
1451
1452 pVCpu->hm.s.vmx.fUpdatedHostMsrs = true;
1453}
1454
1455
1456/**
1457 * Saves a set of host MSRs to allow read/write passthru access to the guest and
1458 * perform lazy restoration of the host MSRs while leaving VT-x.
1459 *
1460 * @param pVCpu The cross context virtual CPU structure.
1461 *
1462 * @remarks No-long-jump zone!!!
1463 */
1464static void hmR0VmxLazySaveHostMsrs(PVMCPU pVCpu)
1465{
1466 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1467
1468 /*
1469 * Note: If you're adding MSRs here, make sure to update the MSR-bitmap permissions in hmR0VmxSetupProcCtls().
1470 */
1471 if (!(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST))
1472 {
1473 Assert(!(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)); /* Guest MSRs better not be loaded now. */
1474#if HC_ARCH_BITS == 64
1475 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1476 {
1477 pVCpu->hm.s.vmx.u64HostLStarMsr = ASMRdMsr(MSR_K8_LSTAR);
1478 pVCpu->hm.s.vmx.u64HostStarMsr = ASMRdMsr(MSR_K6_STAR);
1479 pVCpu->hm.s.vmx.u64HostSFMaskMsr = ASMRdMsr(MSR_K8_SF_MASK);
1480 pVCpu->hm.s.vmx.u64HostKernelGSBaseMsr = ASMRdMsr(MSR_K8_KERNEL_GS_BASE);
1481 }
1482#endif
1483 pVCpu->hm.s.vmx.fLazyMsrs |= VMX_LAZY_MSRS_SAVED_HOST;
1484 }
1485}
1486
1487
1488/**
1489 * Checks whether the MSR belongs to the set of guest MSRs that we restore
1490 * lazily while leaving VT-x.
1491 *
1492 * @returns true if it does, false otherwise.
1493 * @param pVCpu The cross context virtual CPU structure.
1494 * @param uMsr The MSR to check.
1495 */
1496static bool hmR0VmxIsLazyGuestMsr(PVMCPU pVCpu, uint32_t uMsr)
1497{
1498 NOREF(pVCpu);
1499#if HC_ARCH_BITS == 64
1500 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1501 {
1502 switch (uMsr)
1503 {
1504 case MSR_K8_LSTAR:
1505 case MSR_K6_STAR:
1506 case MSR_K8_SF_MASK:
1507 case MSR_K8_KERNEL_GS_BASE:
1508 return true;
1509 }
1510 }
1511#else
1512 RT_NOREF(pVCpu, uMsr);
1513#endif
1514 return false;
1515}
1516
1517
1518/**
1519 * Loads a set of guests MSRs to allow read/passthru to the guest.
1520 *
1521 * The name of this function is slightly confusing. This function does NOT
1522 * postpone loading, but loads the MSR right now. "hmR0VmxLazy" is simply a
1523 * common prefix for functions dealing with "lazy restoration" of the shared
1524 * MSRs.
1525 *
1526 * @param pVCpu The cross context virtual CPU structure.
1527 *
1528 * @remarks No-long-jump zone!!!
1529 */
1530static void hmR0VmxLazyLoadGuestMsrs(PVMCPU pVCpu)
1531{
1532 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1533 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1534
1535 Assert(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST);
1536#if HC_ARCH_BITS == 64
1537 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1538 {
1539 /*
1540 * If the guest MSRs are not loaded -and- if all the guest MSRs are identical
1541 * to the MSRs on the CPU (which are the saved host MSRs, see assertion above) then
1542 * we can skip a few MSR writes.
1543 *
1544 * Otherwise, it implies either 1. they're not loaded, or 2. they're loaded but the
1545 * guest MSR values in the guest-CPU context might be different to what's currently
1546 * loaded in the CPU. In either case, we need to write the new guest MSR values to the
1547 * CPU, see @bugref{8728}.
1548 */
1549 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1550 if ( !(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
1551 && pCtx->msrKERNELGSBASE == pVCpu->hm.s.vmx.u64HostKernelGSBaseMsr
1552 && pCtx->msrLSTAR == pVCpu->hm.s.vmx.u64HostLStarMsr
1553 && pCtx->msrSTAR == pVCpu->hm.s.vmx.u64HostStarMsr
1554 && pCtx->msrSFMASK == pVCpu->hm.s.vmx.u64HostSFMaskMsr)
1555 {
1556#ifdef VBOX_STRICT
1557 Assert(ASMRdMsr(MSR_K8_KERNEL_GS_BASE) == pCtx->msrKERNELGSBASE);
1558 Assert(ASMRdMsr(MSR_K8_LSTAR) == pCtx->msrLSTAR);
1559 Assert(ASMRdMsr(MSR_K6_STAR) == pCtx->msrSTAR);
1560 Assert(ASMRdMsr(MSR_K8_SF_MASK) == pCtx->msrSFMASK);
1561#endif
1562 }
1563 else
1564 {
1565 ASMWrMsr(MSR_K8_KERNEL_GS_BASE, pCtx->msrKERNELGSBASE);
1566 ASMWrMsr(MSR_K8_LSTAR, pCtx->msrLSTAR);
1567 ASMWrMsr(MSR_K6_STAR, pCtx->msrSTAR);
1568 ASMWrMsr(MSR_K8_SF_MASK, pCtx->msrSFMASK);
1569 }
1570 }
1571#endif
1572 pVCpu->hm.s.vmx.fLazyMsrs |= VMX_LAZY_MSRS_LOADED_GUEST;
1573}
1574
1575
1576/**
1577 * Performs lazy restoration of the set of host MSRs if they were previously
1578 * loaded with guest MSR values.
1579 *
1580 * @param pVCpu The cross context virtual CPU structure.
1581 *
1582 * @remarks No-long-jump zone!!!
1583 * @remarks The guest MSRs should have been saved back into the guest-CPU
1584 * context by hmR0VmxImportGuestState()!!!
1585 */
1586static void hmR0VmxLazyRestoreHostMsrs(PVMCPU pVCpu)
1587{
1588 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1589 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1590
1591 if (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
1592 {
1593 Assert(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST);
1594#if HC_ARCH_BITS == 64
1595 if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1596 {
1597 ASMWrMsr(MSR_K8_LSTAR, pVCpu->hm.s.vmx.u64HostLStarMsr);
1598 ASMWrMsr(MSR_K6_STAR, pVCpu->hm.s.vmx.u64HostStarMsr);
1599 ASMWrMsr(MSR_K8_SF_MASK, pVCpu->hm.s.vmx.u64HostSFMaskMsr);
1600 ASMWrMsr(MSR_K8_KERNEL_GS_BASE, pVCpu->hm.s.vmx.u64HostKernelGSBaseMsr);
1601 }
1602#endif
1603 }
1604 pVCpu->hm.s.vmx.fLazyMsrs &= ~(VMX_LAZY_MSRS_LOADED_GUEST | VMX_LAZY_MSRS_SAVED_HOST);
1605}
1606
1607
1608/**
1609 * Verifies that our cached values of the VMCS fields are all consistent with
1610 * what's actually present in the VMCS.
1611 *
1612 * @returns VBox status code.
1613 * @retval VINF_SUCCESS if all our caches match their respective VMCS fields.
1614 * @retval VERR_VMX_VMCS_FIELD_CACHE_INVALID if a cache field doesn't match the
1615 * VMCS content. HMCPU error-field is
1616 * updated, see VMX_VCI_XXX.
1617 * @param pVCpu The cross context virtual CPU structure.
1618 */
1619static int hmR0VmxCheckVmcsCtls(PVMCPU pVCpu)
1620{
1621 uint32_t u32Val;
1622 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val);
1623 AssertRCReturn(rc, rc);
1624 AssertMsgReturnStmt(pVCpu->hm.s.vmx.u32EntryCtls == u32Val,
1625 ("Cache=%#RX32 VMCS=%#RX32\n", pVCpu->hm.s.vmx.u32EntryCtls, u32Val),
1626 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_ENTRY,
1627 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1628
1629 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT, &u32Val);
1630 AssertRCReturn(rc, rc);
1631 AssertMsgReturnStmt(pVCpu->hm.s.vmx.u32ExitCtls == u32Val,
1632 ("Cache=%#RX32 VMCS=%#RX32\n", pVCpu->hm.s.vmx.u32ExitCtls, u32Val),
1633 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_EXIT,
1634 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1635
1636 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, &u32Val);
1637 AssertRCReturn(rc, rc);
1638 AssertMsgReturnStmt(pVCpu->hm.s.vmx.u32PinCtls == u32Val,
1639 ("Cache=%#RX32 VMCS=%#RX32\n", pVCpu->hm.s.vmx.u32PinCtls, u32Val),
1640 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_PIN_EXEC,
1641 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1642
1643 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, &u32Val);
1644 AssertRCReturn(rc, rc);
1645 AssertMsgReturnStmt(pVCpu->hm.s.vmx.u32ProcCtls == u32Val,
1646 ("Cache=%#RX32 VMCS=%#RX32\n", pVCpu->hm.s.vmx.u32ProcCtls, u32Val),
1647 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_PROC_EXEC,
1648 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1649
1650 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1651 {
1652 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val);
1653 AssertRCReturn(rc, rc);
1654 AssertMsgReturnStmt(pVCpu->hm.s.vmx.u32ProcCtls2 == u32Val,
1655 ("Cache=%#RX32 VMCS=%#RX32\n", pVCpu->hm.s.vmx.u32ProcCtls2, u32Val),
1656 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_PROC_EXEC2,
1657 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1658 }
1659
1660 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, &u32Val);
1661 AssertRCReturn(rc, rc);
1662 AssertMsgReturnStmt(pVCpu->hm.s.vmx.u32XcptBitmap == u32Val,
1663 ("Cache=%#RX32 VMCS=%#RX32\n", pVCpu->hm.s.vmx.u32XcptBitmap, u32Val),
1664 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_XCPT_BITMAP,
1665 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1666
1667 uint64_t u64Val;
1668 rc = VMXReadVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, &u64Val);
1669 AssertRCReturn(rc, rc);
1670 AssertMsgReturnStmt(pVCpu->hm.s.vmx.u64TscOffset == u64Val,
1671 ("Cache=%#RX64 VMCS=%#RX64\n", pVCpu->hm.s.vmx.u64TscOffset, u64Val),
1672 pVCpu->hm.s.u32HMError = VMX_VCI_CTRL_TSC_OFFSET,
1673 VERR_VMX_VMCS_FIELD_CACHE_INVALID);
1674
1675 return VINF_SUCCESS;
1676}
1677
1678
1679#ifdef VBOX_STRICT
1680/**
1681 * Verifies that our cached host EFER value has not changed
1682 * since we cached it.
1683 *
1684 * @param pVCpu The cross context virtual CPU structure.
1685 */
1686static void hmR0VmxCheckHostEferMsr(PVMCPU pVCpu)
1687{
1688 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1689
1690 if (pVCpu->hm.s.vmx.u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1691 {
1692 uint64_t u64Val;
1693 int rc = VMXReadVmcs64(VMX_VMCS64_HOST_EFER_FULL, &u64Val);
1694 AssertRC(rc);
1695
1696 uint64_t u64HostEferMsr = ASMRdMsr(MSR_K6_EFER);
1697 AssertMsgReturnVoid(u64HostEferMsr == u64Val, ("u64HostEferMsr=%#RX64 u64Val=%#RX64\n", u64HostEferMsr, u64Val));
1698 }
1699}
1700
1701
1702/**
1703 * Verifies whether the guest/host MSR pairs in the auto-load/store area in the
1704 * VMCS are correct.
1705 *
1706 * @param pVCpu The cross context virtual CPU structure.
1707 */
1708static void hmR0VmxCheckAutoLoadStoreMsrs(PVMCPU pVCpu)
1709{
1710 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1711
1712 /* Verify MSR counts in the VMCS are what we think it should be. */
1713 uint32_t cMsrs;
1714 int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, &cMsrs); AssertRC(rc);
1715 Assert(cMsrs == pVCpu->hm.s.vmx.cMsrs);
1716
1717 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, &cMsrs); AssertRC(rc);
1718 Assert(cMsrs == pVCpu->hm.s.vmx.cMsrs);
1719
1720 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, &cMsrs); AssertRC(rc);
1721 Assert(cMsrs == pVCpu->hm.s.vmx.cMsrs);
1722
1723 PCVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1724 PCVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1725 for (uint32_t i = 0; i < cMsrs; i++, pHostMsr++, pGuestMsr++)
1726 {
1727 /* Verify that the MSRs are paired properly and that the host MSR has the correct value. */
1728 AssertMsgReturnVoid(pHostMsr->u32Msr == pGuestMsr->u32Msr, ("HostMsr=%#RX32 GuestMsr=%#RX32 cMsrs=%u\n", pHostMsr->u32Msr,
1729 pGuestMsr->u32Msr, cMsrs));
1730
1731 uint64_t u64Msr = ASMRdMsr(pHostMsr->u32Msr);
1732 AssertMsgReturnVoid(pHostMsr->u64Value == u64Msr, ("u32Msr=%#RX32 VMCS Value=%#RX64 ASMRdMsr=%#RX64 cMsrs=%u\n",
1733 pHostMsr->u32Msr, pHostMsr->u64Value, u64Msr, cMsrs));
1734
1735 /* Verify that the permissions are as expected in the MSR bitmap. */
1736 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
1737 {
1738 VMXMSREXITREAD enmRead;
1739 VMXMSREXITWRITE enmWrite;
1740 rc = HMVmxGetMsrPermission(pVCpu->hm.s.vmx.pvMsrBitmap, pGuestMsr->u32Msr, &enmRead, &enmWrite);
1741 AssertMsgReturnVoid(rc == VINF_SUCCESS, ("HMVmxGetMsrPermission! failed. rc=%Rrc\n", rc));
1742 if (pGuestMsr->u32Msr == MSR_K6_EFER)
1743 {
1744 AssertMsgReturnVoid(enmRead == VMXMSREXIT_INTERCEPT_READ, ("Passthru read for EFER!?\n"));
1745 AssertMsgReturnVoid(enmWrite == VMXMSREXIT_INTERCEPT_WRITE, ("Passthru write for EFER!?\n"));
1746 }
1747 else
1748 {
1749 AssertMsgReturnVoid(enmRead == VMXMSREXIT_PASSTHRU_READ, ("u32Msr=%#RX32 cMsrs=%u No passthru read!\n",
1750 pGuestMsr->u32Msr, cMsrs));
1751 AssertMsgReturnVoid(enmWrite == VMXMSREXIT_PASSTHRU_WRITE, ("u32Msr=%#RX32 cMsrs=%u No passthru write!\n",
1752 pGuestMsr->u32Msr, cMsrs));
1753 }
1754 }
1755 }
1756}
1757#endif /* VBOX_STRICT */
1758
1759
1760/**
1761 * Flushes the TLB using EPT.
1762 *
1763 * @returns VBox status code.
1764 * @param pVCpu The cross context virtual CPU structure of the calling
1765 * EMT. Can be NULL depending on @a enmTlbFlush.
1766 * @param enmTlbFlush Type of flush.
1767 *
1768 * @remarks Caller is responsible for making sure this function is called only
1769 * when NestedPaging is supported and providing @a enmTlbFlush that is
1770 * supported by the CPU.
1771 * @remarks Can be called with interrupts disabled.
1772 */
1773static void hmR0VmxFlushEpt(PVMCPU pVCpu, VMXTLBFLUSHEPT enmTlbFlush)
1774{
1775 uint64_t au64Descriptor[2];
1776 if (enmTlbFlush == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1777 au64Descriptor[0] = 0;
1778 else
1779 {
1780 Assert(pVCpu);
1781 au64Descriptor[0] = pVCpu->hm.s.vmx.HCPhysEPTP;
1782 }
1783 au64Descriptor[1] = 0; /* MBZ. Intel spec. 33.3 "VMX Instructions" */
1784
1785 int rc = VMXR0InvEPT(enmTlbFlush, &au64Descriptor[0]);
1786 AssertMsg(rc == VINF_SUCCESS,
1787 ("VMXR0InvEPT %#x %RGv failed with %Rrc\n", enmTlbFlush, pVCpu ? pVCpu->hm.s.vmx.HCPhysEPTP : 0, rc));
1788
1789 if ( RT_SUCCESS(rc)
1790 && pVCpu)
1791 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushNestedPaging);
1792}
1793
1794
1795/**
1796 * Flushes the TLB using VPID.
1797 *
1798 * @returns VBox status code.
1799 * @param pVCpu The cross context virtual CPU structure of the calling
1800 * EMT. Can be NULL depending on @a enmTlbFlush.
1801 * @param enmTlbFlush Type of flush.
1802 * @param GCPtr Virtual address of the page to flush (can be 0 depending
1803 * on @a enmTlbFlush).
1804 *
1805 * @remarks Can be called with interrupts disabled.
1806 */
1807static void hmR0VmxFlushVpid(PVMCPU pVCpu, VMXTLBFLUSHVPID enmTlbFlush, RTGCPTR GCPtr)
1808{
1809 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fVpid);
1810
1811 uint64_t au64Descriptor[2];
1812 if (enmTlbFlush == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1813 {
1814 au64Descriptor[0] = 0;
1815 au64Descriptor[1] = 0;
1816 }
1817 else
1818 {
1819 AssertPtr(pVCpu);
1820 AssertMsg(pVCpu->hm.s.uCurrentAsid != 0, ("VMXR0InvVPID: invalid ASID %lu\n", pVCpu->hm.s.uCurrentAsid));
1821 AssertMsg(pVCpu->hm.s.uCurrentAsid <= UINT16_MAX, ("VMXR0InvVPID: invalid ASID %lu\n", pVCpu->hm.s.uCurrentAsid));
1822 au64Descriptor[0] = pVCpu->hm.s.uCurrentAsid;
1823 au64Descriptor[1] = GCPtr;
1824 }
1825
1826 int rc = VMXR0InvVPID(enmTlbFlush, &au64Descriptor[0]);
1827 AssertMsg(rc == VINF_SUCCESS,
1828 ("VMXR0InvVPID %#x %u %RGv failed with %Rrc\n", enmTlbFlush, pVCpu ? pVCpu->hm.s.uCurrentAsid : 0, GCPtr, rc));
1829
1830 if ( RT_SUCCESS(rc)
1831 && pVCpu)
1832 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1833 NOREF(rc);
1834}
1835
1836
1837/**
1838 * Invalidates a guest page by guest virtual address. Only relevant for
1839 * EPT/VPID, otherwise there is nothing really to invalidate.
1840 *
1841 * @returns VBox status code.
1842 * @param pVCpu The cross context virtual CPU structure.
1843 * @param GCVirt Guest virtual address of the page to invalidate.
1844 */
1845VMMR0DECL(int) VMXR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)
1846{
1847 AssertPtr(pVCpu);
1848 LogFlowFunc(("pVCpu=%p GCVirt=%RGv\n", pVCpu, GCVirt));
1849
1850 bool fFlushPending = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1851 if (!fFlushPending)
1852 {
1853 /*
1854 * We must invalidate the guest TLB entry in either case, we cannot ignore it even for
1855 * the EPT case. See @bugref{6043} and @bugref{6177}.
1856 *
1857 * Set the VMCPU_FF_TLB_FLUSH force flag and flush before VM-entry in hmR0VmxFlushTLB*()
1858 * as this function maybe called in a loop with individual addresses.
1859 */
1860 PVM pVM = pVCpu->CTX_SUFF(pVM);
1861 if (pVM->hm.s.vmx.fVpid)
1862 {
1863 bool fVpidFlush = RT_BOOL(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1864
1865#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1866 /*
1867 * Workaround Erratum BV75, AAJ159 and others that affect several Intel CPUs
1868 * where executing INVVPID outside 64-bit mode does not flush translations of
1869 * 64-bit linear addresses, see @bugref{6208#c72}.
1870 */
1871 if (RT_HI_U32(GCVirt))
1872 fVpidFlush = false;
1873#endif
1874
1875 if (fVpidFlush)
1876 {
1877 hmR0VmxFlushVpid(pVCpu, VMXTLBFLUSHVPID_INDIV_ADDR, GCVirt);
1878 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1879 }
1880 else
1881 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1882 }
1883 else if (pVM->hm.s.fNestedPaging)
1884 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1885 }
1886
1887 return VINF_SUCCESS;
1888}
1889
1890
1891/**
1892 * Dummy placeholder for tagged-TLB flush handling before VM-entry. Used in the
1893 * case where neither EPT nor VPID is supported by the CPU.
1894 *
1895 * @param pVCpu The cross context virtual CPU structure.
1896 * @param pCpu Pointer to the global HM struct.
1897 *
1898 * @remarks Called with interrupts disabled.
1899 */
1900static void hmR0VmxFlushTaggedTlbNone(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1901{
1902 AssertPtr(pVCpu);
1903 AssertPtr(pCpu);
1904
1905 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
1906
1907 Assert(pCpu->idCpu != NIL_RTCPUID);
1908 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1909 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1910 pVCpu->hm.s.fForceTLBFlush = false;
1911 return;
1912}
1913
1914
1915/**
1916 * Flushes the tagged-TLB entries for EPT+VPID CPUs as necessary.
1917 *
1918 * @param pVCpu The cross context virtual CPU structure.
1919 * @param pCpu Pointer to the global HM CPU struct.
1920 *
1921 * @remarks All references to "ASID" in this function pertains to "VPID" in Intel's
1922 * nomenclature. The reason is, to avoid confusion in compare statements
1923 * since the host-CPU copies are named "ASID".
1924 *
1925 * @remarks Called with interrupts disabled.
1926 */
1927static void hmR0VmxFlushTaggedTlbBoth(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1928{
1929#ifdef VBOX_WITH_STATISTICS
1930 bool fTlbFlushed = false;
1931# define HMVMX_SET_TAGGED_TLB_FLUSHED() do { fTlbFlushed = true; } while (0)
1932# define HMVMX_UPDATE_FLUSH_SKIPPED_STAT() do { \
1933 if (!fTlbFlushed) \
1934 STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch); \
1935 } while (0)
1936#else
1937# define HMVMX_SET_TAGGED_TLB_FLUSHED() do { } while (0)
1938# define HMVMX_UPDATE_FLUSH_SKIPPED_STAT() do { } while (0)
1939#endif
1940
1941 AssertPtr(pCpu);
1942 AssertPtr(pVCpu);
1943 Assert(pCpu->idCpu != NIL_RTCPUID);
1944
1945 PVM pVM = pVCpu->CTX_SUFF(pVM);
1946 AssertMsg(pVM->hm.s.fNestedPaging && pVM->hm.s.vmx.fVpid,
1947 ("hmR0VmxFlushTaggedTlbBoth cannot be invoked unless NestedPaging & VPID are enabled."
1948 "fNestedPaging=%RTbool fVpid=%RTbool", pVM->hm.s.fNestedPaging, pVM->hm.s.vmx.fVpid));
1949
1950 /*
1951 * Force a TLB flush for the first world-switch if the current CPU differs from the one we
1952 * ran on last. If the TLB flush count changed, another VM (VCPU rather) has hit the ASID
1953 * limit while flushing the TLB or the host CPU is online after a suspend/resume, so we
1954 * cannot reuse the current ASID anymore.
1955 */
1956 if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
1957 || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
1958 {
1959 ++pCpu->uCurrentAsid;
1960 if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1961 {
1962 pCpu->uCurrentAsid = 1; /* Wraparound to 1; host uses 0. */
1963 pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
1964 pCpu->fFlushAsidBeforeUse = true; /* All VCPUs that run on this host CPU must flush their new VPID before use. */
1965 }
1966
1967 pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
1968 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1969 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1970
1971 /*
1972 * Flush by EPT when we get rescheduled to a new host CPU to ensure EPT-only tagged mappings are also
1973 * invalidated. We don't need to flush-by-VPID here as flushing by EPT covers it. See @bugref{6568}.
1974 */
1975 hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmTlbFlushEpt);
1976 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1977 HMVMX_SET_TAGGED_TLB_FLUSHED();
1978 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
1979 }
1980 else if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH)) /* Check for explicit TLB flushes. */
1981 {
1982 /*
1983 * Changes to the EPT paging structure by VMM requires flushing-by-EPT as the CPU
1984 * creates guest-physical (ie. only EPT-tagged) mappings while traversing the EPT
1985 * tables when EPT is in use. Flushing-by-VPID will only flush linear (only
1986 * VPID-tagged) and combined (EPT+VPID tagged) mappings but not guest-physical
1987 * mappings, see @bugref{6568}.
1988 *
1989 * See Intel spec. 28.3.2 "Creating and Using Cached Translation Information".
1990 */
1991 hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmTlbFlushEpt);
1992 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1993 HMVMX_SET_TAGGED_TLB_FLUSHED();
1994 }
1995
1996 pVCpu->hm.s.fForceTLBFlush = false;
1997 HMVMX_UPDATE_FLUSH_SKIPPED_STAT();
1998
1999 Assert(pVCpu->hm.s.idLastCpu == pCpu->idCpu);
2000 Assert(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes);
2001 AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
2002 ("Flush count mismatch for cpu %d (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
2003 AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
2004 ("Cpu[%u] uCurrentAsid=%u cTlbFlushes=%u pVCpu->idLastCpu=%u pVCpu->cTlbFlushes=%u\n", pCpu->idCpu,
2005 pCpu->uCurrentAsid, pCpu->cTlbFlushes, pVCpu->hm.s.idLastCpu, pVCpu->hm.s.cTlbFlushes));
2006 AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
2007 ("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
2008
2009 /* Update VMCS with the VPID. */
2010 int rc = VMXWriteVmcs32(VMX_VMCS16_VPID, pVCpu->hm.s.uCurrentAsid);
2011 AssertRC(rc);
2012
2013#undef HMVMX_SET_TAGGED_TLB_FLUSHED
2014}
2015
2016
2017/**
2018 * Flushes the tagged-TLB entries for EPT CPUs as necessary.
2019 *
2020 * @returns VBox status code.
2021 * @param pVCpu The cross context virtual CPU structure.
2022 * @param pCpu Pointer to the global HM CPU struct.
2023 *
2024 * @remarks Called with interrupts disabled.
2025 */
2026static void hmR0VmxFlushTaggedTlbEpt(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
2027{
2028 AssertPtr(pVCpu);
2029 AssertPtr(pCpu);
2030 Assert(pCpu->idCpu != NIL_RTCPUID);
2031 AssertMsg(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging, ("hmR0VmxFlushTaggedTlbEpt cannot be invoked without NestedPaging."));
2032 AssertMsg(!pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fVpid, ("hmR0VmxFlushTaggedTlbEpt cannot be invoked with VPID."));
2033
2034 /*
2035 * Force a TLB flush for the first world-switch if the current CPU differs from the one we ran on last.
2036 * A change in the TLB flush count implies the host CPU is online after a suspend/resume.
2037 */
2038 if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
2039 || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
2040 {
2041 pVCpu->hm.s.fForceTLBFlush = true;
2042 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
2043 }
2044
2045 /* Check for explicit TLB flushes. */
2046 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
2047 {
2048 pVCpu->hm.s.fForceTLBFlush = true;
2049 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
2050 }
2051
2052 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
2053 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
2054
2055 if (pVCpu->hm.s.fForceTLBFlush)
2056 {
2057 hmR0VmxFlushEpt(pVCpu, pVCpu->CTX_SUFF(pVM)->hm.s.vmx.enmTlbFlushEpt);
2058 pVCpu->hm.s.fForceTLBFlush = false;
2059 }
2060}
2061
2062
2063/**
2064 * Flushes the tagged-TLB entries for VPID CPUs as necessary.
2065 *
2066 * @returns VBox status code.
2067 * @param pVCpu The cross context virtual CPU structure.
2068 * @param pCpu Pointer to the global HM CPU struct.
2069 *
2070 * @remarks Called with interrupts disabled.
2071 */
2072static void hmR0VmxFlushTaggedTlbVpid(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
2073{
2074 AssertPtr(pVCpu);
2075 AssertPtr(pCpu);
2076 Assert(pCpu->idCpu != NIL_RTCPUID);
2077 AssertMsg(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fVpid, ("hmR0VmxFlushTlbVpid cannot be invoked without VPID."));
2078 AssertMsg(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging, ("hmR0VmxFlushTlbVpid cannot be invoked with NestedPaging"));
2079
2080 /*
2081 * Force a TLB flush for the first world switch if the current CPU differs from the one we
2082 * ran on last. If the TLB flush count changed, another VM (VCPU rather) has hit the ASID
2083 * limit while flushing the TLB or the host CPU is online after a suspend/resume, so we
2084 * cannot reuse the current ASID anymore.
2085 */
2086 if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
2087 || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
2088 {
2089 pVCpu->hm.s.fForceTLBFlush = true;
2090 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
2091 }
2092
2093 /* Check for explicit TLB flushes. */
2094 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
2095 {
2096 /*
2097 * If we ever support VPID flush combinations other than ALL or SINGLE-context (see
2098 * hmR0VmxSetupTaggedTlb()) we would need to explicitly flush in this case (add an
2099 * fExplicitFlush = true here and change the pCpu->fFlushAsidBeforeUse check below to
2100 * include fExplicitFlush's too) - an obscure corner case.
2101 */
2102 pVCpu->hm.s.fForceTLBFlush = true;
2103 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
2104 }
2105
2106 PVM pVM = pVCpu->CTX_SUFF(pVM);
2107 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
2108 if (pVCpu->hm.s.fForceTLBFlush)
2109 {
2110 ++pCpu->uCurrentAsid;
2111 if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
2112 {
2113 pCpu->uCurrentAsid = 1; /* Wraparound to 1; host uses 0 */
2114 pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
2115 pCpu->fFlushAsidBeforeUse = true; /* All VCPUs that run on this host CPU must flush their new VPID before use. */
2116 }
2117
2118 pVCpu->hm.s.fForceTLBFlush = false;
2119 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
2120 pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
2121 if (pCpu->fFlushAsidBeforeUse)
2122 {
2123 if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
2124 hmR0VmxFlushVpid(pVCpu, VMXTLBFLUSHVPID_SINGLE_CONTEXT, 0 /* GCPtr */);
2125 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
2126 {
2127 hmR0VmxFlushVpid(pVCpu, VMXTLBFLUSHVPID_ALL_CONTEXTS, 0 /* GCPtr */);
2128 pCpu->fFlushAsidBeforeUse = false;
2129 }
2130 else
2131 {
2132 /* hmR0VmxSetupTaggedTlb() ensures we never get here. Paranoia. */
2133 AssertMsgFailed(("Unsupported VPID-flush context type.\n"));
2134 }
2135 }
2136 }
2137
2138 AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
2139 ("Flush count mismatch for cpu %d (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
2140 AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
2141 ("Cpu[%u] uCurrentAsid=%u cTlbFlushes=%u pVCpu->idLastCpu=%u pVCpu->cTlbFlushes=%u\n", pCpu->idCpu,
2142 pCpu->uCurrentAsid, pCpu->cTlbFlushes, pVCpu->hm.s.idLastCpu, pVCpu->hm.s.cTlbFlushes));
2143 AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
2144 ("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
2145
2146 int rc = VMXWriteVmcs32(VMX_VMCS16_VPID, pVCpu->hm.s.uCurrentAsid);
2147 AssertRC(rc);
2148}
2149
2150
2151/**
2152 * Flushes the guest TLB entry based on CPU capabilities.
2153 *
2154 * @param pVCpu The cross context virtual CPU structure.
2155 * @param pCpu Pointer to the global HM CPU struct.
2156 */
2157DECLINLINE(void) hmR0VmxFlushTaggedTlb(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
2158{
2159#ifdef HMVMX_ALWAYS_FLUSH_TLB
2160 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2161#endif
2162 PVM pVM = pVCpu->CTX_SUFF(pVM);
2163 switch (pVM->hm.s.vmx.enmTlbFlushType)
2164 {
2165 case VMXTLBFLUSHTYPE_EPT_VPID: hmR0VmxFlushTaggedTlbBoth(pVCpu, pCpu); break;
2166 case VMXTLBFLUSHTYPE_EPT: hmR0VmxFlushTaggedTlbEpt(pVCpu, pCpu); break;
2167 case VMXTLBFLUSHTYPE_VPID: hmR0VmxFlushTaggedTlbVpid(pVCpu, pCpu); break;
2168 case VMXTLBFLUSHTYPE_NONE: hmR0VmxFlushTaggedTlbNone(pVCpu, pCpu); break;
2169 default:
2170 AssertMsgFailed(("Invalid flush-tag function identifier\n"));
2171 break;
2172 }
2173 /* Don't assert that VMCPU_FF_TLB_FLUSH should no longer be pending. It can be set by other EMTs. */
2174}
2175
2176
2177/**
2178 * Sets up the appropriate tagged TLB-flush level and handler for flushing guest
2179 * TLB entries from the host TLB before VM-entry.
2180 *
2181 * @returns VBox status code.
2182 * @param pVM The cross context VM structure.
2183 */
2184static int hmR0VmxSetupTaggedTlb(PVM pVM)
2185{
2186 /*
2187 * Determine optimal flush type for Nested Paging.
2188 * We cannot ignore EPT if no suitable flush-types is supported by the CPU as we've already setup unrestricted
2189 * guest execution (see hmR3InitFinalizeR0()).
2190 */
2191 if (pVM->hm.s.fNestedPaging)
2192 {
2193 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT)
2194 {
2195 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT)
2196 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_SINGLE_CONTEXT;
2197 else if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
2198 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_ALL_CONTEXTS;
2199 else
2200 {
2201 /* Shouldn't happen. EPT is supported but no suitable flush-types supported. */
2202 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NOT_SUPPORTED;
2203 pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED;
2204 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2205 }
2206
2207 /* Make sure the write-back cacheable memory type for EPT is supported. */
2208 if (RT_UNLIKELY(!(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB)))
2209 {
2210 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NOT_SUPPORTED;
2211 pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_MEM_TYPE_NOT_WB;
2212 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2213 }
2214
2215 /* EPT requires a page-walk length of 4. */
2216 if (RT_UNLIKELY(!(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4)))
2217 {
2218 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NOT_SUPPORTED;
2219 pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED;
2220 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2221 }
2222 }
2223 else
2224 {
2225 /* Shouldn't happen. EPT is supported but INVEPT instruction is not supported. */
2226 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NOT_SUPPORTED;
2227 pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_INVEPT_UNAVAILABLE;
2228 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2229 }
2230 }
2231
2232 /*
2233 * Determine optimal flush type for VPID.
2234 */
2235 if (pVM->hm.s.vmx.fVpid)
2236 {
2237 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID)
2238 {
2239 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT)
2240 pVM->hm.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_SINGLE_CONTEXT;
2241 else if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS)
2242 pVM->hm.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_ALL_CONTEXTS;
2243 else
2244 {
2245 /* Neither SINGLE nor ALL-context flush types for VPID is supported by the CPU. Ignore VPID capability. */
2246 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
2247 LogRelFunc(("Only INDIV_ADDR supported. Ignoring VPID.\n"));
2248 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
2249 LogRelFunc(("Only SINGLE_CONTEXT_RETAIN_GLOBALS supported. Ignoring VPID.\n"));
2250 pVM->hm.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_NOT_SUPPORTED;
2251 pVM->hm.s.vmx.fVpid = false;
2252 }
2253 }
2254 else
2255 {
2256 /* Shouldn't happen. VPID is supported but INVVPID is not supported by the CPU. Ignore VPID capability. */
2257 Log4Func(("VPID supported without INVEPT support. Ignoring VPID.\n"));
2258 pVM->hm.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_NOT_SUPPORTED;
2259 pVM->hm.s.vmx.fVpid = false;
2260 }
2261 }
2262
2263 /*
2264 * Setup the handler for flushing tagged-TLBs.
2265 */
2266 if (pVM->hm.s.fNestedPaging && pVM->hm.s.vmx.fVpid)
2267 pVM->hm.s.vmx.enmTlbFlushType = VMXTLBFLUSHTYPE_EPT_VPID;
2268 else if (pVM->hm.s.fNestedPaging)
2269 pVM->hm.s.vmx.enmTlbFlushType = VMXTLBFLUSHTYPE_EPT;
2270 else if (pVM->hm.s.vmx.fVpid)
2271 pVM->hm.s.vmx.enmTlbFlushType = VMXTLBFLUSHTYPE_VPID;
2272 else
2273 pVM->hm.s.vmx.enmTlbFlushType = VMXTLBFLUSHTYPE_NONE;
2274 return VINF_SUCCESS;
2275}
2276
2277
2278/**
2279 * Sets up pin-based VM-execution controls in the VMCS.
2280 *
2281 * @returns VBox status code.
2282 * @param pVCpu The cross context virtual CPU structure.
2283 *
2284 * @remarks We don't really care about optimizing vmwrites here as it's done only
2285 * once per VM and hence we don't care about VMCS-field cache comparisons.
2286 */
2287static int hmR0VmxSetupPinCtls(PVMCPU pVCpu)
2288{
2289 PVM pVM = pVCpu->CTX_SUFF(pVM);
2290 uint32_t fVal = pVM->hm.s.vmx.Msrs.PinCtls.n.disallowed0; /* Bits set here must always be set. */
2291 uint32_t const fZap = pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1; /* Bits cleared here must always be cleared. */
2292
2293 fVal |= VMX_PIN_CTLS_EXT_INT_EXIT /* External interrupts cause a VM-exit. */
2294 | VMX_PIN_CTLS_NMI_EXIT; /* Non-maskable interrupts (NMIs) cause a VM-exit. */
2295
2296 if (pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_VIRT_NMI)
2297 fVal |= VMX_PIN_CTLS_VIRT_NMI; /* Use virtual NMIs and virtual-NMI blocking features. */
2298
2299 /* Enable the VMX preemption timer. */
2300 if (pVM->hm.s.vmx.fUsePreemptTimer)
2301 {
2302 Assert(pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_PREEMPT_TIMER);
2303 fVal |= VMX_PIN_CTLS_PREEMPT_TIMER;
2304 }
2305
2306#if 0
2307 /* Enable posted-interrupt processing. */
2308 if (pVM->hm.s.fPostedIntrs)
2309 {
2310 Assert(pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_POSTED_INT);
2311 Assert(pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT);
2312 fVal |= VMX_PIN_CTL_POSTED_INT;
2313 }
2314#endif
2315
2316 if ((fVal & fZap) != fVal)
2317 {
2318 LogRelFunc(("Invalid pin-based VM-execution controls combo! Cpu=%#RX64 fVal=%#RX64 fZap=%#RX64\n",
2319 pVM->hm.s.vmx.Msrs.PinCtls.n.disallowed0, fVal, fZap));
2320 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PIN_EXEC;
2321 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2322 }
2323
2324 /* Commit it to the VMCS and update our cache. */
2325 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, fVal);
2326 AssertRCReturn(rc, rc);
2327 pVCpu->hm.s.vmx.u32PinCtls = fVal;
2328
2329 return VINF_SUCCESS;
2330}
2331
2332
2333/**
2334 * Sets up secondary processor-based VM-execution controls in the VMCS.
2335 *
2336 * @returns VBox status code.
2337 * @param pVCpu The cross context virtual CPU structure.
2338 *
2339 * @remarks We don't really care about optimizing vmwrites here as it's done only
2340 * once per VM and hence we don't care about VMCS-field cache comparisons.
2341 */
2342static int hmR0VmxSetupProcCtls2(PVMCPU pVCpu)
2343{
2344 PVM pVM = pVCpu->CTX_SUFF(pVM);
2345 uint32_t fVal = pVM->hm.s.vmx.Msrs.ProcCtls2.n.disallowed0; /* Bits set here must be set in the VMCS. */
2346 uint32_t const fZap = pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
2347
2348 /* WBINVD causes a VM-exit. */
2349 if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_WBINVD_EXIT)
2350 fVal |= VMX_PROC_CTLS2_WBINVD_EXIT;
2351
2352 /* Enable EPT (aka nested-paging). */
2353 if (pVM->hm.s.fNestedPaging)
2354 fVal |= VMX_PROC_CTLS2_EPT;
2355
2356 /*
2357 * Enable the INVPCID instruction if supported by the hardware and we expose
2358 * it to the guest. Without this, guest executing INVPCID would cause a #UD.
2359 */
2360 if ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_INVPCID)
2361 && pVM->cpum.ro.GuestFeatures.fInvpcid)
2362 fVal |= VMX_PROC_CTLS2_INVPCID;
2363
2364 /* Enable VPID. */
2365 if (pVM->hm.s.vmx.fVpid)
2366 fVal |= VMX_PROC_CTLS2_VPID;
2367
2368 /* Enable Unrestricted guest execution. */
2369 if (pVM->hm.s.vmx.fUnrestrictedGuest)
2370 fVal |= VMX_PROC_CTLS2_UNRESTRICTED_GUEST;
2371
2372#if 0
2373 if (pVM->hm.s.fVirtApicRegs)
2374 {
2375 /* Enable APIC-register virtualization. */
2376 Assert(pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT);
2377 fVal |= VMX_PROC_CTLS2_APIC_REG_VIRT;
2378
2379 /* Enable virtual-interrupt delivery. */
2380 Assert(pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY);
2381 fVal |= VMX_PROC_CTLS2_VIRT_INTR_DELIVERY;
2382 }
2383#endif
2384
2385 /* Virtualize-APIC accesses if supported by the CPU. The virtual-APIC page is where the TPR shadow resides. */
2386 /** @todo VIRT_X2APIC support, it's mutually exclusive with this. So must be
2387 * done dynamically. */
2388 if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
2389 {
2390 Assert(pVM->hm.s.vmx.HCPhysApicAccess);
2391 Assert(!(pVM->hm.s.vmx.HCPhysApicAccess & 0xfff)); /* Bits 11:0 MBZ. */
2392 fVal |= VMX_PROC_CTLS2_VIRT_APIC_ACCESS; /* Virtualize APIC accesses. */
2393 int rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL, pVM->hm.s.vmx.HCPhysApicAccess);
2394 AssertRCReturn(rc, rc);
2395 }
2396
2397 /* Enable RDTSCP. */
2398 if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_RDTSCP)
2399 fVal |= VMX_PROC_CTLS2_RDTSCP;
2400
2401 /* Enable Pause-Loop exiting. */
2402 if ( pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT
2403 && pVM->hm.s.vmx.cPleGapTicks
2404 && pVM->hm.s.vmx.cPleWindowTicks)
2405 {
2406 fVal |= VMX_PROC_CTLS2_PAUSE_LOOP_EXIT;
2407
2408 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_GAP, pVM->hm.s.vmx.cPleGapTicks);
2409 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_WINDOW, pVM->hm.s.vmx.cPleWindowTicks);
2410 AssertRCReturn(rc, rc);
2411 }
2412
2413 if ((fVal & fZap) != fVal)
2414 {
2415 LogRelFunc(("Invalid secondary processor-based VM-execution controls combo! cpu=%#RX64 fVal=%#RX64 fZap=%#RX64\n",
2416 pVM->hm.s.vmx.Msrs.ProcCtls2.n.disallowed0, fVal, fZap));
2417 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC2;
2418 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2419 }
2420
2421 /* Commit it to the VMCS and update our cache. */
2422 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, fVal);
2423 AssertRCReturn(rc, rc);
2424 pVCpu->hm.s.vmx.u32ProcCtls2 = fVal;
2425
2426 return VINF_SUCCESS;
2427}
2428
2429
2430/**
2431 * Sets up processor-based VM-execution controls in the VMCS.
2432 *
2433 * @returns VBox status code.
2434 * @param pVCpu The cross context virtual CPU structure.
2435 *
2436 * @remarks We don't really care about optimizing vmwrites here as it's done only
2437 * once per VM and hence we don't care about VMCS-field cache comparisons.
2438 */
2439static int hmR0VmxSetupProcCtls(PVMCPU pVCpu)
2440{
2441 PVM pVM = pVCpu->CTX_SUFF(pVM);
2442 uint32_t fVal = pVM->hm.s.vmx.Msrs.ProcCtls.n.disallowed0; /* Bits set here must be set in the VMCS. */
2443 uint32_t const fZap = pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
2444
2445 fVal |= VMX_PROC_CTLS_HLT_EXIT /* HLT causes a VM-exit. */
2446 | VMX_PROC_CTLS_USE_TSC_OFFSETTING /* Use TSC-offsetting. */
2447 | VMX_PROC_CTLS_MOV_DR_EXIT /* MOV DRx causes a VM-exit. */
2448 | VMX_PROC_CTLS_UNCOND_IO_EXIT /* All IO instructions cause a VM-exit. */
2449 | VMX_PROC_CTLS_RDPMC_EXIT /* RDPMC causes a VM-exit. */
2450 | VMX_PROC_CTLS_MONITOR_EXIT /* MONITOR causes a VM-exit. */
2451 | VMX_PROC_CTLS_MWAIT_EXIT; /* MWAIT causes a VM-exit. */
2452
2453 /* We toggle VMX_PROC_CTLS_MOV_DR_EXIT later, check if it's not -always- needed to be set or clear. */
2454 if ( !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_MOV_DR_EXIT)
2455 || (pVM->hm.s.vmx.Msrs.ProcCtls.n.disallowed0 & VMX_PROC_CTLS_MOV_DR_EXIT))
2456 {
2457 LogRelFunc(("Unsupported VMX_PROC_CTLS_MOV_DR_EXIT combo!"));
2458 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_MOV_DRX_EXIT;
2459 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2460 }
2461
2462 /* Without Nested Paging, INVLPG (also affects INVPCID) and MOV CR3 instructions should cause VM-exits. */
2463 if (!pVM->hm.s.fNestedPaging)
2464 {
2465 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest); /* Paranoia. */
2466 fVal |= VMX_PROC_CTLS_INVLPG_EXIT
2467 | VMX_PROC_CTLS_CR3_LOAD_EXIT
2468 | VMX_PROC_CTLS_CR3_STORE_EXIT;
2469 }
2470
2471 /* Use TPR shadowing if supported by the CPU. */
2472 if ( PDMHasApic(pVM)
2473 && pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TPR_SHADOW)
2474 {
2475 Assert(pVCpu->hm.s.vmx.HCPhysVirtApic);
2476 Assert(!(pVCpu->hm.s.vmx.HCPhysVirtApic & 0xfff)); /* Bits 11:0 MBZ. */
2477 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, 0);
2478 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL, pVCpu->hm.s.vmx.HCPhysVirtApic);
2479 AssertRCReturn(rc, rc);
2480
2481 fVal |= VMX_PROC_CTLS_USE_TPR_SHADOW; /* CR8 reads from the Virtual-APIC page. */
2482 /* CR8 writes cause a VM-exit based on TPR threshold. */
2483 Assert(!(fVal & VMX_PROC_CTLS_CR8_STORE_EXIT));
2484 Assert(!(fVal & VMX_PROC_CTLS_CR8_LOAD_EXIT));
2485 }
2486 else
2487 {
2488 /*
2489 * Some 32-bit CPUs do not support CR8 load/store exiting as MOV CR8 is invalid on 32-bit Intel CPUs.
2490 * Set this control only for 64-bit guests.
2491 */
2492 if (pVM->hm.s.fAllow64BitGuests)
2493 {
2494 fVal |= VMX_PROC_CTLS_CR8_STORE_EXIT /* CR8 reads cause a VM-exit. */
2495 | VMX_PROC_CTLS_CR8_LOAD_EXIT; /* CR8 writes cause a VM-exit. */
2496 }
2497 }
2498
2499 /* Use MSR-bitmaps if supported by the CPU. */
2500 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
2501 {
2502 fVal |= VMX_PROC_CTLS_USE_MSR_BITMAPS;
2503
2504 Assert(pVCpu->hm.s.vmx.HCPhysMsrBitmap);
2505 Assert(!(pVCpu->hm.s.vmx.HCPhysMsrBitmap & 0xfff)); /* Bits 11:0 MBZ. */
2506 int rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_MSR_BITMAP_FULL, pVCpu->hm.s.vmx.HCPhysMsrBitmap);
2507 AssertRCReturn(rc, rc);
2508
2509 /*
2510 * The guest can access the following MSRs (read, write) without causing VM-exits; they are loaded/stored
2511 * automatically using dedicated fields in the VMCS.
2512 */
2513 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2514 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2515 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2516 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_GS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2517 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_FS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2518#if HC_ARCH_BITS == 64
2519 /*
2520 * Set passthru permissions for the following MSRs (mandatory for VT-x) required for 64-bit guests.
2521 */
2522 if (pVM->hm.s.fAllow64BitGuests)
2523 {
2524 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_LSTAR, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2525 hmR0VmxSetMsrPermission(pVCpu, MSR_K6_STAR, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2526 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_SF_MASK, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2527 hmR0VmxSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2528 }
2529#endif
2530 /*
2531 * The IA32_PRED_CMD MSR is write-only and has no state associated with it. We never need to intercept
2532 * access (writes need to be executed without exiting, reds will #GP-fault anyway).
2533 */
2534 if (pVM->cpum.ro.GuestFeatures.fIbpb)
2535 hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_PRED_CMD, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2536
2537 /* Though MSR_IA32_PERF_GLOBAL_CTRL is saved/restored lazily, we want intercept reads/write to it for now. */
2538 }
2539
2540 /* Use the secondary processor-based VM-execution controls if supported by the CPU. */
2541 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
2542 fVal |= VMX_PROC_CTLS_USE_SECONDARY_CTLS;
2543
2544 if ((fVal & fZap) != fVal)
2545 {
2546 LogRelFunc(("Invalid processor-based VM-execution controls combo! cpu=%#RX64 fVal=%#RX64 fZap=%#RX64\n",
2547 pVM->hm.s.vmx.Msrs.ProcCtls.n.disallowed0, fVal, fZap));
2548 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC;
2549 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2550 }
2551
2552 /* Commit it to the VMCS and update our cache. */
2553 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, fVal);
2554 AssertRCReturn(rc, rc);
2555 pVCpu->hm.s.vmx.u32ProcCtls = fVal;
2556
2557 /* Set up secondary processor-based VM-execution controls if the CPU supports it. */
2558 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
2559 return hmR0VmxSetupProcCtls2(pVCpu);
2560
2561 /* Sanity check, should not really happen. */
2562 if (RT_UNLIKELY(pVM->hm.s.vmx.fUnrestrictedGuest))
2563 {
2564 LogRelFunc(("Unrestricted Guest enabled when secondary processor-based VM-execution controls not available\n"));
2565 pVCpu->hm.s.u32HMError = VMX_UFC_INVALID_UX_COMBO;
2566 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2567 }
2568
2569 /* Old CPUs without secondary processor-based VM-execution controls would end up here. */
2570 return VINF_SUCCESS;
2571}
2572
2573
2574/**
2575 * Sets up miscellaneous (everything other than Pin & Processor-based
2576 * VM-execution) control fields in the VMCS.
2577 *
2578 * @returns VBox status code.
2579 * @param pVCpu The cross context virtual CPU structure.
2580 */
2581static int hmR0VmxSetupMiscCtls(PVMCPU pVCpu)
2582{
2583 AssertPtr(pVCpu);
2584
2585 int rc = VERR_GENERAL_FAILURE;
2586
2587 /* All fields are zero-initialized during allocation; but don't remove the commented block below. */
2588#if 0
2589 /* All CR3 accesses cause VM-exits. Later we optimize CR3 accesses (see hmR0VmxExportGuestCR3AndCR4())*/
2590 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, 0);
2591 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, 0);
2592
2593 /*
2594 * Set MASK & MATCH to 0. VMX checks if GuestPFErrCode & MASK == MATCH. If equal (in our case it always is)
2595 * and if the X86_XCPT_PF bit in the exception bitmap is set it causes a VM-exit, if clear doesn't cause an exit.
2596 * We thus use the exception bitmap to control it rather than use both.
2597 */
2598 rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, 0);
2599 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, 0);
2600
2601 /* All IO & IOIO instructions cause VM-exits. */
2602 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_A_FULL, 0);
2603 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_B_FULL, 0);
2604
2605 /* Initialize the MSR-bitmap area. */
2606 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, 0);
2607 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, 0);
2608 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, 0);
2609 AssertRCReturn(rc, rc);
2610#endif
2611
2612 /* Setup MSR auto-load/store area. */
2613 Assert(pVCpu->hm.s.vmx.HCPhysGuestMsr);
2614 Assert(!(pVCpu->hm.s.vmx.HCPhysGuestMsr & 0xf)); /* Lower 4 bits MBZ. */
2615 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
2616 rc |= VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
2617 AssertRCReturn(rc, rc);
2618
2619 Assert(pVCpu->hm.s.vmx.HCPhysHostMsr);
2620 Assert(!(pVCpu->hm.s.vmx.HCPhysHostMsr & 0xf)); /* Lower 4 bits MBZ. */
2621 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysHostMsr);
2622 AssertRCReturn(rc, rc);
2623
2624 /* Set VMCS link pointer. Reserved for future use, must be -1. Intel spec. 24.4 "Guest-State Area". */
2625 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, UINT64_C(0xffffffffffffffff));
2626 AssertRCReturn(rc, rc);
2627
2628 /* All fields are zero-initialized during allocation; but don't remove the commented block below. */
2629#if 0
2630 /* Setup debug controls */
2631 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, 0);
2632 rc |= VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, 0);
2633 AssertRCReturn(rc, rc);
2634#endif
2635
2636 return rc;
2637}
2638
2639
2640/**
2641 * Sets up the initial exception bitmap in the VMCS based on static conditions.
2642 *
2643 * We shall setup those exception intercepts that don't change during the
2644 * lifetime of the VM here. The rest are done dynamically while loading the
2645 * guest state.
2646 *
2647 * @returns VBox status code.
2648 * @param pVCpu The cross context virtual CPU structure.
2649 */
2650static int hmR0VmxInitXcptBitmap(PVMCPU pVCpu)
2651{
2652 AssertPtr(pVCpu);
2653
2654 uint32_t uXcptBitmap;
2655
2656 /* Must always intercept #AC to prevent the guest from hanging the CPU. */
2657 uXcptBitmap = RT_BIT_32(X86_XCPT_AC);
2658
2659 /* Because we need to maintain the DR6 state even when intercepting DRx reads
2660 and writes, and because recursive #DBs can cause the CPU hang, we must always
2661 intercept #DB. */
2662 uXcptBitmap |= RT_BIT_32(X86_XCPT_DB);
2663
2664 /* Without Nested Paging, #PF must cause a VM-exit so we can sync our shadow page tables. */
2665 if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
2666 uXcptBitmap |= RT_BIT(X86_XCPT_PF);
2667
2668 /* Commit it to the VMCS. */
2669 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, uXcptBitmap);
2670 AssertRCReturn(rc, rc);
2671
2672 /* Update our cache of the exception bitmap. */
2673 pVCpu->hm.s.vmx.u32XcptBitmap = uXcptBitmap;
2674 return VINF_SUCCESS;
2675}
2676
2677
2678/**
2679 * Does per-VM VT-x initialization.
2680 *
2681 * @returns VBox status code.
2682 * @param pVM The cross context VM structure.
2683 */
2684VMMR0DECL(int) VMXR0InitVM(PVM pVM)
2685{
2686 LogFlowFunc(("pVM=%p\n", pVM));
2687
2688 int rc = hmR0VmxStructsAlloc(pVM);
2689 if (RT_FAILURE(rc))
2690 {
2691 LogRelFunc(("hmR0VmxStructsAlloc failed! rc=%Rrc\n", rc));
2692 return rc;
2693 }
2694
2695 return VINF_SUCCESS;
2696}
2697
2698
2699/**
2700 * Does per-VM VT-x termination.
2701 *
2702 * @returns VBox status code.
2703 * @param pVM The cross context VM structure.
2704 */
2705VMMR0DECL(int) VMXR0TermVM(PVM pVM)
2706{
2707 LogFlowFunc(("pVM=%p\n", pVM));
2708
2709#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2710 if (pVM->hm.s.vmx.hMemObjScratch != NIL_RTR0MEMOBJ)
2711 ASMMemZero32(pVM->hm.s.vmx.pvScratch, PAGE_SIZE);
2712#endif
2713 hmR0VmxStructsFree(pVM);
2714 return VINF_SUCCESS;
2715}
2716
2717
2718/**
2719 * Sets up the VM for execution under VT-x.
2720 * This function is only called once per-VM during initialization.
2721 *
2722 * @returns VBox status code.
2723 * @param pVM The cross context VM structure.
2724 */
2725VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
2726{
2727 AssertPtrReturn(pVM, VERR_INVALID_PARAMETER);
2728 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2729
2730 LogFlowFunc(("pVM=%p\n", pVM));
2731
2732 /*
2733 * Without UnrestrictedGuest, pRealModeTSS and pNonPagingModeEPTPageTable *must* always be
2734 * allocated. We no longer support the highly unlikely case of UnrestrictedGuest without
2735 * pRealModeTSS, see hmR3InitFinalizeR0Intel().
2736 */
2737 if ( !pVM->hm.s.vmx.fUnrestrictedGuest
2738 && ( !pVM->hm.s.vmx.pNonPagingModeEPTPageTable
2739 || !pVM->hm.s.vmx.pRealModeTSS))
2740 {
2741 LogRelFunc(("Invalid real-on-v86 state.\n"));
2742 return VERR_INTERNAL_ERROR;
2743 }
2744
2745 /* Initialize these always, see hmR3InitFinalizeR0().*/
2746 pVM->hm.s.vmx.enmTlbFlushEpt = VMXTLBFLUSHEPT_NONE;
2747 pVM->hm.s.vmx.enmTlbFlushVpid = VMXTLBFLUSHVPID_NONE;
2748
2749 /* Setup the tagged-TLB flush handlers. */
2750 int rc = hmR0VmxSetupTaggedTlb(pVM);
2751 if (RT_FAILURE(rc))
2752 {
2753 LogRelFunc(("hmR0VmxSetupTaggedTlb failed! rc=%Rrc\n", rc));
2754 return rc;
2755 }
2756
2757 /* Check if we can use the VMCS controls for swapping the EFER MSR. */
2758 Assert(!pVM->hm.s.vmx.fSupportsVmcsEfer);
2759#if HC_ARCH_BITS == 64
2760 if ( (pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1 & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
2761 && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_LOAD_EFER_MSR)
2762 && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_SAVE_EFER_MSR))
2763 {
2764 pVM->hm.s.vmx.fSupportsVmcsEfer = true;
2765 }
2766#endif
2767
2768 /* At least verify VMX is enabled, since we can't check if we're in VMX root mode without #GP'ing. */
2769 RTCCUINTREG const uHostCR4 = ASMGetCR4();
2770 if (RT_UNLIKELY(!(uHostCR4 & X86_CR4_VMXE)))
2771 return VERR_VMX_NOT_IN_VMX_ROOT_MODE;
2772
2773 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2774 {
2775 PVMCPU pVCpu = &pVM->aCpus[i];
2776 AssertPtr(pVCpu);
2777 AssertPtr(pVCpu->hm.s.vmx.pvVmcs);
2778
2779 /* Log the VCPU pointers, useful for debugging SMP VMs. */
2780 Log4Func(("pVCpu=%p idCpu=%RU32\n", pVCpu, pVCpu->idCpu));
2781
2782 /* Set revision dword at the beginning of the VMCS structure. */
2783 *(uint32_t *)pVCpu->hm.s.vmx.pvVmcs = RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_ID);
2784
2785 /* Set the VMCS launch state to "clear", see Intel spec. 31.6 "Preparation and launch a virtual machine". */
2786 rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2787 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXClearVmcs failed! rc=%Rrc\n", rc),
2788 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2789
2790 /* Load this VMCS as the current VMCS. */
2791 rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2792 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXActivateVmcs failed! rc=%Rrc\n", rc),
2793 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2794
2795 rc = hmR0VmxSetupPinCtls(pVCpu);
2796 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupPinCtls failed! rc=%Rrc\n", rc),
2797 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2798
2799 rc = hmR0VmxSetupProcCtls(pVCpu);
2800 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupProcCtls failed! rc=%Rrc\n", rc),
2801 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2802
2803 rc = hmR0VmxSetupMiscCtls(pVCpu);
2804 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupMiscCtls failed! rc=%Rrc\n", rc),
2805 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2806
2807 rc = hmR0VmxInitXcptBitmap(pVCpu);
2808 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitXcptBitmap failed! rc=%Rrc\n", rc),
2809 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2810
2811#if HC_ARCH_BITS == 32
2812 rc = hmR0VmxInitVmcsReadCache(pVCpu);
2813 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitVmcsReadCache failed! rc=%Rrc\n", rc),
2814 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2815#endif
2816
2817 /* Sync any CPU internal VMCS data back into our VMCS in memory. */
2818 rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2819 AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXClearVmcs(2) failed! rc=%Rrc\n", rc),
2820 hmR0VmxUpdateErrorRecord(pVCpu, rc), rc);
2821
2822 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
2823
2824 hmR0VmxUpdateErrorRecord(pVCpu, rc);
2825 }
2826
2827 return VINF_SUCCESS;
2828}
2829
2830
2831/**
2832 * Saves the host control registers (CR0, CR3, CR4) into the host-state area in
2833 * the VMCS.
2834 *
2835 * @returns VBox status code.
2836 */
2837static int hmR0VmxExportHostControlRegs(void)
2838{
2839 RTCCUINTREG uReg = ASMGetCR0();
2840 int rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR0, uReg);
2841 AssertRCReturn(rc, rc);
2842
2843 uReg = ASMGetCR3();
2844 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR3, uReg);
2845 AssertRCReturn(rc, rc);
2846
2847 uReg = ASMGetCR4();
2848 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR4, uReg);
2849 AssertRCReturn(rc, rc);
2850 return rc;
2851}
2852
2853
2854/**
2855 * Saves the host segment registers and GDTR, IDTR, (TR, GS and FS bases) into
2856 * the host-state area in the VMCS.
2857 *
2858 * @returns VBox status code.
2859 * @param pVCpu The cross context virtual CPU structure.
2860 */
2861static int hmR0VmxExportHostSegmentRegs(PVMCPU pVCpu)
2862{
2863#if HC_ARCH_BITS == 64
2864/**
2865 * Macro for adjusting host segment selectors to satisfy VT-x's VM-entry
2866 * requirements. See hmR0VmxExportHostSegmentRegs().
2867 */
2868# define VMXLOCAL_ADJUST_HOST_SEG(seg, selValue) \
2869 if ((selValue) & (X86_SEL_RPL | X86_SEL_LDT)) \
2870 { \
2871 bool fValidSelector = true; \
2872 if ((selValue) & X86_SEL_LDT) \
2873 { \
2874 uint32_t uAttr = ASMGetSegAttr((selValue)); \
2875 fValidSelector = RT_BOOL(uAttr != UINT32_MAX && (uAttr & X86_DESC_P)); \
2876 } \
2877 if (fValidSelector) \
2878 { \
2879 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_##seg; \
2880 pVCpu->hm.s.vmx.RestoreHost.uHostSel##seg = (selValue); \
2881 } \
2882 (selValue) = 0; \
2883 }
2884
2885 /*
2886 * If we've executed guest code using VT-x, the host-state bits will be messed up. We
2887 * should -not- save the messed up state without restoring the original host-state,
2888 * see @bugref{7240}.
2889 *
2890 * This apparently can happen (most likely the FPU changes), deal with it rather than
2891 * asserting. Was observed booting Solaris 10u10 32-bit guest.
2892 */
2893 if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
2894 && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
2895 {
2896 Log4Func(("Restoring Host State: fRestoreHostFlags=%#RX32 HostCpuId=%u\n", pVCpu->hm.s.vmx.fRestoreHostFlags,
2897 pVCpu->idCpu));
2898 VMXRestoreHostState(pVCpu->hm.s.vmx.fRestoreHostFlags, &pVCpu->hm.s.vmx.RestoreHost);
2899 }
2900 pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
2901#else
2902 RT_NOREF(pVCpu);
2903#endif
2904
2905 /*
2906 * Host DS, ES, FS and GS segment registers.
2907 */
2908#if HC_ARCH_BITS == 64
2909 RTSEL uSelDS = ASMGetDS();
2910 RTSEL uSelES = ASMGetES();
2911 RTSEL uSelFS = ASMGetFS();
2912 RTSEL uSelGS = ASMGetGS();
2913#else
2914 RTSEL uSelDS = 0;
2915 RTSEL uSelES = 0;
2916 RTSEL uSelFS = 0;
2917 RTSEL uSelGS = 0;
2918#endif
2919
2920 /*
2921 * Host CS and SS segment registers.
2922 */
2923 RTSEL uSelCS = ASMGetCS();
2924 RTSEL uSelSS = ASMGetSS();
2925
2926 /*
2927 * Host TR segment register.
2928 */
2929 RTSEL uSelTR = ASMGetTR();
2930
2931#if HC_ARCH_BITS == 64
2932 /*
2933 * Determine if the host segment registers are suitable for VT-x. Otherwise use zero to
2934 * gain VM-entry and restore them before we get preempted.
2935 *
2936 * See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
2937 */
2938 VMXLOCAL_ADJUST_HOST_SEG(DS, uSelDS);
2939 VMXLOCAL_ADJUST_HOST_SEG(ES, uSelES);
2940 VMXLOCAL_ADJUST_HOST_SEG(FS, uSelFS);
2941 VMXLOCAL_ADJUST_HOST_SEG(GS, uSelGS);
2942# undef VMXLOCAL_ADJUST_HOST_SEG
2943#endif
2944
2945 /* Verification based on Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers" */
2946 Assert(!(uSelCS & X86_SEL_RPL)); Assert(!(uSelCS & X86_SEL_LDT));
2947 Assert(!(uSelSS & X86_SEL_RPL)); Assert(!(uSelSS & X86_SEL_LDT));
2948 Assert(!(uSelDS & X86_SEL_RPL)); Assert(!(uSelDS & X86_SEL_LDT));
2949 Assert(!(uSelES & X86_SEL_RPL)); Assert(!(uSelES & X86_SEL_LDT));
2950 Assert(!(uSelFS & X86_SEL_RPL)); Assert(!(uSelFS & X86_SEL_LDT));
2951 Assert(!(uSelGS & X86_SEL_RPL)); Assert(!(uSelGS & X86_SEL_LDT));
2952 Assert(!(uSelTR & X86_SEL_RPL)); Assert(!(uSelTR & X86_SEL_LDT));
2953 Assert(uSelCS);
2954 Assert(uSelTR);
2955
2956 /* Assertion is right but we would not have updated u32ExitCtls yet. */
2957#if 0
2958 if (!(pVCpu->hm.s.vmx.u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE))
2959 Assert(uSelSS != 0);
2960#endif
2961
2962 /* Write these host selector fields into the host-state area in the VMCS. */
2963 int rc = VMXWriteVmcs32(VMX_VMCS16_HOST_CS_SEL, uSelCS);
2964 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_SS_SEL, uSelSS);
2965#if HC_ARCH_BITS == 64
2966 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_DS_SEL, uSelDS);
2967 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_ES_SEL, uSelES);
2968 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_FS_SEL, uSelFS);
2969 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_GS_SEL, uSelGS);
2970#else
2971 NOREF(uSelDS);
2972 NOREF(uSelES);
2973 NOREF(uSelFS);
2974 NOREF(uSelGS);
2975#endif
2976 rc |= VMXWriteVmcs32(VMX_VMCS16_HOST_TR_SEL, uSelTR);
2977 AssertRCReturn(rc, rc);
2978
2979 /*
2980 * Host GDTR and IDTR.
2981 */
2982 RTGDTR Gdtr;
2983 RTIDTR Idtr;
2984 RT_ZERO(Gdtr);
2985 RT_ZERO(Idtr);
2986 ASMGetGDTR(&Gdtr);
2987 ASMGetIDTR(&Idtr);
2988 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, Gdtr.pGdt);
2989 rc |= VMXWriteVmcsHstN(VMX_VMCS_HOST_IDTR_BASE, Idtr.pIdt);
2990 AssertRCReturn(rc, rc);
2991
2992#if HC_ARCH_BITS == 64
2993 /*
2994 * Determine if we need to manually need to restore the GDTR and IDTR limits as VT-x zaps
2995 * them to the maximum limit (0xffff) on every VM-exit.
2996 */
2997 if (Gdtr.cbGdt != 0xffff)
2998 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_GDTR;
2999
3000 /*
3001 * IDT limit is effectively capped at 0xfff. (See Intel spec. 6.14.1 "64-Bit Mode IDT" and
3002 * Intel spec. 6.2 "Exception and Interrupt Vectors".) Therefore if the host has the limit
3003 * as 0xfff, VT-x bloating the limit to 0xffff shouldn't cause any different CPU behavior.
3004 * However, several hosts either insists on 0xfff being the limit (Windows Patch Guard) or
3005 * uses the limit for other purposes (darwin puts the CPU ID in there but botches sidt
3006 * alignment in at least one consumer). So, we're only allowing the IDTR.LIMIT to be left
3007 * at 0xffff on hosts where we are sure it won't cause trouble.
3008 */
3009# if defined(RT_OS_LINUX) || defined(RT_OS_SOLARIS)
3010 if (Idtr.cbIdt < 0x0fff)
3011# else
3012 if (Idtr.cbIdt != 0xffff)
3013# endif
3014 {
3015 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_IDTR;
3016 AssertCompile(sizeof(Idtr) == sizeof(X86XDTR64));
3017 memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostIdtr, &Idtr, sizeof(X86XDTR64));
3018 }
3019#endif
3020
3021 /*
3022 * Host TR base. Verify that TR selector doesn't point past the GDT. Masking off the TI
3023 * and RPL bits is effectively what the CPU does for "scaling by 8". TI is always 0 and
3024 * RPL should be too in most cases.
3025 */
3026 AssertMsgReturn((uSelTR | X86_SEL_RPL_LDT) <= Gdtr.cbGdt,
3027 ("TR selector exceeds limit. TR=%RTsel cbGdt=%#x\n", uSelTR, Gdtr.cbGdt), VERR_VMX_INVALID_HOST_STATE);
3028
3029 PCX86DESCHC pDesc = (PCX86DESCHC)(Gdtr.pGdt + (uSelTR & X86_SEL_MASK));
3030#if HC_ARCH_BITS == 64
3031 uintptr_t uTRBase = X86DESC64_BASE(pDesc);
3032
3033 /*
3034 * VT-x unconditionally restores the TR limit to 0x67 and type to 11 (32-bit busy TSS) on
3035 * all VM-exits. The type is the same for 64-bit busy TSS[1]. The limit needs manual
3036 * restoration if the host has something else. Task switching is not supported in 64-bit
3037 * mode[2], but the limit still matters as IOPM is supported in 64-bit mode. Restoring the
3038 * limit lazily while returning to ring-3 is safe because IOPM is not applicable in ring-0.
3039 *
3040 * [1] See Intel spec. 3.5 "System Descriptor Types".
3041 * [2] See Intel spec. 7.2.3 "TSS Descriptor in 64-bit mode".
3042 */
3043 PVM pVM = pVCpu->CTX_SUFF(pVM);
3044 Assert(pDesc->System.u4Type == 11);
3045 if ( pDesc->System.u16LimitLow != 0x67
3046 || pDesc->System.u4LimitHigh)
3047 {
3048 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_SEL_TR;
3049 /* If the host has made GDT read-only, we would need to temporarily toggle CR0.WP before writing the GDT. */
3050 if (pVM->hm.s.fHostKernelFeatures & SUPKERNELFEATURES_GDT_READ_ONLY)
3051 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_GDT_READ_ONLY;
3052 pVCpu->hm.s.vmx.RestoreHost.uHostSelTR = uSelTR;
3053 }
3054
3055 /*
3056 * Store the GDTR as we need it when restoring the GDT and while restoring the TR.
3057 */
3058 if (pVCpu->hm.s.vmx.fRestoreHostFlags & (VMX_RESTORE_HOST_GDTR | VMX_RESTORE_HOST_SEL_TR))
3059 {
3060 AssertCompile(sizeof(Gdtr) == sizeof(X86XDTR64));
3061 memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostGdtr, &Gdtr, sizeof(X86XDTR64));
3062 if (pVM->hm.s.fHostKernelFeatures & SUPKERNELFEATURES_GDT_NEED_WRITABLE)
3063 {
3064 /* The GDT is read-only but the writable GDT is available. */
3065 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_GDT_NEED_WRITABLE;
3066 pVCpu->hm.s.vmx.RestoreHost.HostGdtrRw.cb = Gdtr.cbGdt;
3067 rc = SUPR0GetCurrentGdtRw(&pVCpu->hm.s.vmx.RestoreHost.HostGdtrRw.uAddr);
3068 AssertRCReturn(rc, rc);
3069 }
3070 }
3071#else
3072 uintptr_t uTRBase = X86DESC_BASE(pDesc);
3073#endif
3074 rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_TR_BASE, uTRBase);
3075 AssertRCReturn(rc, rc);
3076
3077 /*
3078 * Host FS base and GS base.
3079 */
3080#if HC_ARCH_BITS == 64
3081 uint64_t u64FSBase = ASMRdMsr(MSR_K8_FS_BASE);
3082 uint64_t u64GSBase = ASMRdMsr(MSR_K8_GS_BASE);
3083 rc = VMXWriteVmcs64(VMX_VMCS_HOST_FS_BASE, u64FSBase);
3084 rc |= VMXWriteVmcs64(VMX_VMCS_HOST_GS_BASE, u64GSBase);
3085 AssertRCReturn(rc, rc);
3086
3087 /* Store the base if we have to restore FS or GS manually as we need to restore the base as well. */
3088 if (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_SEL_FS)
3089 pVCpu->hm.s.vmx.RestoreHost.uHostFSBase = u64FSBase;
3090 if (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_SEL_GS)
3091 pVCpu->hm.s.vmx.RestoreHost.uHostGSBase = u64GSBase;
3092#endif
3093 return VINF_SUCCESS;
3094}
3095
3096
3097/**
3098 * Exports certain host MSRs in the VM-exit MSR-load area and some in the
3099 * host-state area of the VMCS.
3100 *
3101 * Theses MSRs will be automatically restored on the host after every successful
3102 * VM-exit.
3103 *
3104 * @returns VBox status code.
3105 * @param pVCpu The cross context virtual CPU structure.
3106 *
3107 * @remarks No-long-jump zone!!!
3108 */
3109static int hmR0VmxExportHostMsrs(PVMCPU pVCpu)
3110{
3111 AssertPtr(pVCpu);
3112 AssertPtr(pVCpu->hm.s.vmx.pvHostMsr);
3113
3114 /*
3115 * Save MSRs that we restore lazily (due to preemption or transition to ring-3)
3116 * rather than swapping them on every VM-entry.
3117 */
3118 hmR0VmxLazySaveHostMsrs(pVCpu);
3119
3120 /*
3121 * Host Sysenter MSRs.
3122 */
3123 int rc = VMXWriteVmcs32(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
3124#if HC_ARCH_BITS == 32
3125 rc |= VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
3126 rc |= VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
3127#else
3128 rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
3129 rc |= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
3130#endif
3131 AssertRCReturn(rc, rc);
3132
3133 /*
3134 * Host EFER MSR.
3135 *
3136 * If the CPU supports the newer VMCS controls for managing EFER, use it. Otherwise it's
3137 * done as part of auto-load/store MSR area in the VMCS, see hmR0VmxExportGuestMsrs().
3138 */
3139 PVM pVM = pVCpu->CTX_SUFF(pVM);
3140 if (pVM->hm.s.vmx.fSupportsVmcsEfer)
3141 {
3142 rc = VMXWriteVmcs64(VMX_VMCS64_HOST_EFER_FULL, pVM->hm.s.vmx.u64HostEfer);
3143 AssertRCReturn(rc, rc);
3144 }
3145
3146 /** @todo IA32_PERF_GLOBALCTRL, IA32_PAT also see hmR0VmxExportGuestExitCtls(). */
3147
3148 return VINF_SUCCESS;
3149}
3150
3151
3152/**
3153 * Figures out if we need to swap the EFER MSR which is particularly expensive.
3154 *
3155 * We check all relevant bits. For now, that's everything besides LMA/LME, as
3156 * these two bits are handled by VM-entry, see hmR0VmxExportGuestExitCtls() and
3157 * hmR0VMxExportGuestEntryCtls().
3158 *
3159 * @returns true if we need to load guest EFER, false otherwise.
3160 * @param pVCpu The cross context virtual CPU structure.
3161 *
3162 * @remarks Requires EFER, CR4.
3163 * @remarks No-long-jump zone!!!
3164 */
3165static bool hmR0VmxShouldSwapEferMsr(PVMCPU pVCpu)
3166{
3167#ifdef HMVMX_ALWAYS_SWAP_EFER
3168 RT_NOREF(pVCpu);
3169 return true;
3170#else
3171
3172 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3173#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
3174 /* For 32-bit hosts running 64-bit guests, we always swap EFER in the world-switcher. Nothing to do here. */
3175 if (CPUMIsGuestInLongModeEx(pCtx))
3176 return false;
3177#endif
3178
3179 PVM pVM = pVCpu->CTX_SUFF(pVM);
3180 uint64_t const u64HostEfer = pVM->hm.s.vmx.u64HostEfer;
3181 uint64_t const u64GuestEfer = pCtx->msrEFER;
3182
3183 /*
3184 * For 64-bit guests, if EFER.SCE bit differs, we need to swap EFER to ensure that the
3185 * guest's SYSCALL behaviour isn't broken, see @bugref{7386}.
3186 */
3187 if ( CPUMIsGuestInLongModeEx(pCtx)
3188 && (u64GuestEfer & MSR_K6_EFER_SCE) != (u64HostEfer & MSR_K6_EFER_SCE))
3189 {
3190 return true;
3191 }
3192
3193 /*
3194 * If the guest uses PAE and EFER.NXE bit differs, we need to swap EFER as it
3195 * affects guest paging. 64-bit paging implies CR4.PAE as well.
3196 * See Intel spec. 4.5 "IA-32e Paging" and Intel spec. 4.1.1 "Three Paging Modes".
3197 */
3198 if ( (pCtx->cr4 & X86_CR4_PAE)
3199 && (pCtx->cr0 & X86_CR0_PG)
3200 && (u64GuestEfer & MSR_K6_EFER_NXE) != (u64HostEfer & MSR_K6_EFER_NXE))
3201 {
3202 /* Assert that host is NX capable. */
3203 Assert(pVCpu->CTX_SUFF(pVM)->cpum.ro.HostFeatures.fNoExecute);
3204 return true;
3205 }
3206
3207 return false;
3208#endif
3209}
3210
3211
3212/**
3213 * Exports the guest state with appropriate VM-entry controls in the VMCS.
3214 *
3215 * These controls can affect things done on VM-exit; e.g. "load debug controls",
3216 * see Intel spec. 24.8.1 "VM-entry controls".
3217 *
3218 * @returns VBox status code.
3219 * @param pVCpu The cross context virtual CPU structure.
3220 *
3221 * @remarks Requires EFER.
3222 * @remarks No-long-jump zone!!!
3223 */
3224static int hmR0VmxExportGuestEntryCtls(PVMCPU pVCpu)
3225{
3226 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_VMX_ENTRY_CTLS)
3227 {
3228 PVM pVM = pVCpu->CTX_SUFF(pVM);
3229 uint32_t fVal = pVM->hm.s.vmx.Msrs.EntryCtls.n.disallowed0; /* Bits set here must be set in the VMCS. */
3230 uint32_t const fZap = pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
3231
3232 /* Load debug controls (DR7 & IA32_DEBUGCTL_MSR). The first VT-x capable CPUs only supports the 1-setting of this bit. */
3233 fVal |= VMX_ENTRY_CTLS_LOAD_DEBUG;
3234
3235 /* Set if the guest is in long mode. This will set/clear the EFER.LMA bit on VM-entry. */
3236 if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx))
3237 {
3238 fVal |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
3239 Log4Func(("VMX_ENTRY_CTLS_IA32E_MODE_GUEST\n"));
3240 }
3241 else
3242 Assert(!(fVal & VMX_ENTRY_CTLS_IA32E_MODE_GUEST));
3243
3244 /* If the CPU supports the newer VMCS controls for managing guest/host EFER, use it. */
3245 if ( pVM->hm.s.vmx.fSupportsVmcsEfer
3246 && hmR0VmxShouldSwapEferMsr(pVCpu))
3247 {
3248 fVal |= VMX_ENTRY_CTLS_LOAD_EFER_MSR;
3249 Log4Func(("VMX_ENTRY_CTLS_LOAD_EFER_MSR\n"));
3250 }
3251
3252 /*
3253 * The following should -not- be set (since we're not in SMM mode):
3254 * - VMX_ENTRY_CTLS_ENTRY_TO_SMM
3255 * - VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON
3256 */
3257
3258 /** @todo VMX_ENTRY_CTLS_LOAD_PERF_MSR,
3259 * VMX_ENTRY_CTLS_LOAD_PAT_MSR. */
3260
3261 if ((fVal & fZap) != fVal)
3262 {
3263 Log4Func(("Invalid VM-entry controls combo! Cpu=%RX64 fVal=%RX64 fZap=%RX64\n",
3264 pVM->hm.s.vmx.Msrs.EntryCtls.n.disallowed0, fVal, fZap));
3265 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_ENTRY;
3266 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3267 }
3268
3269 /* Commit it to the VMCS and update our cache. */
3270 if (pVCpu->hm.s.vmx.u32EntryCtls != fVal)
3271 {
3272 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY, fVal);
3273 AssertRCReturn(rc, rc);
3274 pVCpu->hm.s.vmx.u32EntryCtls = fVal;
3275 }
3276
3277 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_VMX_ENTRY_CTLS);
3278 }
3279 return VINF_SUCCESS;
3280}
3281
3282
3283/**
3284 * Exports the guest state with appropriate VM-exit controls in the VMCS.
3285 *
3286 * @returns VBox status code.
3287 * @param pVCpu The cross context virtual CPU structure.
3288 *
3289 * @remarks Requires EFER.
3290 */
3291static int hmR0VmxExportGuestExitCtls(PVMCPU pVCpu)
3292{
3293 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_VMX_EXIT_CTLS)
3294 {
3295 PVM pVM = pVCpu->CTX_SUFF(pVM);
3296 uint32_t fVal = pVM->hm.s.vmx.Msrs.ExitCtls.n.disallowed0; /* Bits set here must be set in the VMCS. */
3297 uint32_t const fZap = pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
3298
3299 /* Save debug controls (DR7 & IA32_DEBUGCTL_MSR). The first VT-x CPUs only supported the 1-setting of this bit. */
3300 fVal |= VMX_EXIT_CTLS_SAVE_DEBUG;
3301
3302 /*
3303 * Set the host long mode active (EFER.LMA) bit (which Intel calls "Host address-space size") if necessary.
3304 * On VM-exit, VT-x sets both the host EFER.LMA and EFER.LME bit to this value. See assertion in
3305 * hmR0VmxExportHostMsrs().
3306 */
3307#if HC_ARCH_BITS == 64
3308 fVal |= VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE;
3309 Log4Func(("VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE\n"));
3310#else
3311 Assert( pVCpu->hm.s.vmx.pfnStartVM == VMXR0SwitcherStartVM64
3312 || pVCpu->hm.s.vmx.pfnStartVM == VMXR0StartVM32);
3313 /* Set the host address-space size based on the switcher, not guest state. See @bugref{8432}. */
3314 if (pVCpu->hm.s.vmx.pfnStartVM == VMXR0SwitcherStartVM64)
3315 {
3316 /* The switcher returns to long mode, EFER is managed by the switcher. */
3317 fVal |= VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE;
3318 Log4Func(("VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE\n"));
3319 }
3320 else
3321 Assert(!(fVal & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE));
3322#endif
3323
3324 /* If the newer VMCS fields for managing EFER exists, use it. */
3325 if ( pVM->hm.s.vmx.fSupportsVmcsEfer
3326 && hmR0VmxShouldSwapEferMsr(pVCpu))
3327 {
3328 fVal |= VMX_EXIT_CTLS_SAVE_EFER_MSR
3329 | VMX_EXIT_CTLS_LOAD_EFER_MSR;
3330 Log4Func(("VMX_EXIT_CTLS_SAVE_EFER_MSR and VMX_EXIT_CTLS_LOAD_EFER_MSR\n"));
3331 }
3332
3333 /* Don't acknowledge external interrupts on VM-exit. We want to let the host do that. */
3334 Assert(!(fVal & VMX_EXIT_CTLS_ACK_EXT_INT));
3335
3336 /** @todo VMX_EXIT_CTLS_LOAD_PERF_MSR,
3337 * VMX_EXIT_CTLS_SAVE_PAT_MSR,
3338 * VMX_EXIT_CTLS_LOAD_PAT_MSR. */
3339
3340 /* Enable saving of the VMX preemption timer value on VM-exit. */
3341 if ( pVM->hm.s.vmx.fUsePreemptTimer
3342 && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER))
3343 fVal |= VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER;
3344
3345 if ((fVal & fZap) != fVal)
3346 {
3347 LogRelFunc(("Invalid VM-exit controls combo! cpu=%RX64 fVal=%RX64 fZap=%RX64\n",
3348 pVM->hm.s.vmx.Msrs.ExitCtls.n.disallowed0, fVal, fZap));
3349 pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_EXIT;
3350 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3351 }
3352
3353 /* Commit it to the VMCS and update our cache. */
3354 if (pVCpu->hm.s.vmx.u32ExitCtls != fVal)
3355 {
3356 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT, fVal);
3357 AssertRCReturn(rc, rc);
3358 pVCpu->hm.s.vmx.u32ExitCtls = fVal;
3359 }
3360
3361 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_VMX_EXIT_CTLS);
3362 }
3363 return VINF_SUCCESS;
3364}
3365
3366
3367/**
3368 * Sets the TPR threshold in the VMCS.
3369 *
3370 * @returns VBox status code.
3371 * @param pVCpu The cross context virtual CPU structure.
3372 * @param u32TprThreshold The TPR threshold (task-priority class only).
3373 */
3374DECLINLINE(int) hmR0VmxApicSetTprThreshold(PVMCPU pVCpu, uint32_t u32TprThreshold)
3375{
3376 Assert(!(u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)); /* Bits 31:4 MBZ. */
3377 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW); RT_NOREF_PV(pVCpu);
3378 return VMXWriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, u32TprThreshold);
3379}
3380
3381
3382/**
3383 * Exports the guest APIC TPR state into the VMCS.
3384 *
3385 * @returns VBox status code.
3386 * @param pVCpu The cross context virtual CPU structure.
3387 *
3388 * @remarks No-long-jump zone!!!
3389 */
3390static int hmR0VmxExportGuestApicTpr(PVMCPU pVCpu)
3391{
3392 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_APIC_TPR)
3393 {
3394 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_APIC_TPR);
3395
3396 if ( PDMHasApic(pVCpu->CTX_SUFF(pVM))
3397 && APICIsEnabled(pVCpu))
3398 {
3399 /*
3400 * Setup TPR shadowing.
3401 */
3402 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
3403 {
3404 Assert(pVCpu->hm.s.vmx.HCPhysVirtApic);
3405
3406 bool fPendingIntr = false;
3407 uint8_t u8Tpr = 0;
3408 uint8_t u8PendingIntr = 0;
3409 int rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, &u8PendingIntr);
3410 AssertRCReturn(rc, rc);
3411
3412 /*
3413 * If there are interrupts pending but masked by the TPR, instruct VT-x to
3414 * cause a TPR-below-threshold VM-exit when the guest lowers its TPR below the
3415 * priority of the pending interrupt so we can deliver the interrupt. If there
3416 * are no interrupts pending, set threshold to 0 to not cause any
3417 * TPR-below-threshold VM-exits.
3418 */
3419 pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR] = u8Tpr;
3420 uint32_t u32TprThreshold = 0;
3421 if (fPendingIntr)
3422 {
3423 /* Bits 3:0 of the TPR threshold field correspond to bits 7:4 of the TPR (which is the Task-Priority Class). */
3424 const uint8_t u8PendingPriority = u8PendingIntr >> 4;
3425 const uint8_t u8TprPriority = u8Tpr >> 4;
3426 if (u8PendingPriority <= u8TprPriority)
3427 u32TprThreshold = u8PendingPriority;
3428 }
3429
3430 rc = hmR0VmxApicSetTprThreshold(pVCpu, u32TprThreshold);
3431 AssertRCReturn(rc, rc);
3432 }
3433 }
3434 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_APIC_TPR);
3435 }
3436 return VINF_SUCCESS;
3437}
3438
3439
3440/**
3441 * Gets the guest's interruptibility-state ("interrupt shadow" as AMD calls it).
3442 *
3443 * @returns Guest's interruptibility-state.
3444 * @param pVCpu The cross context virtual CPU structure.
3445 *
3446 * @remarks No-long-jump zone!!!
3447 */
3448static uint32_t hmR0VmxGetGuestIntrState(PVMCPU pVCpu)
3449{
3450 /*
3451 * Check if we should inhibit interrupt delivery due to instructions like STI and MOV SS.
3452 */
3453 uint32_t fIntrState = 0;
3454 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3455 {
3456 /* If inhibition is active, RIP & RFLAGS should've been accessed
3457 (i.e. read previously from the VMCS or from ring-3). */
3458 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3459#ifdef VBOX_STRICT
3460 uint64_t const fExtrn = ASMAtomicUoReadU64(&pCtx->fExtrn);
3461 AssertMsg(!(fExtrn & (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS)), ("%#x\n", fExtrn));
3462#endif
3463 if (pCtx->rip == EMGetInhibitInterruptsPC(pVCpu))
3464 {
3465 if (pCtx->eflags.Bits.u1IF)
3466 fIntrState = VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
3467 else
3468 fIntrState = VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS;
3469 }
3470 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3471 {
3472 /*
3473 * We can clear the inhibit force flag as even if we go back to the recompiler
3474 * without executing guest code in VT-x, the flag's condition to be cleared is
3475 * met and thus the cleared state is correct.
3476 */
3477 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3478 }
3479 }
3480
3481 /*
3482 * NMIs to the guest are blocked after an NMI is injected until the guest executes an IRET. We only
3483 * bother with virtual-NMI blocking when we have support for virtual NMIs in the CPU, otherwise
3484 * setting this would block host-NMIs and IRET will not clear the blocking.
3485 *
3486 * See Intel spec. 26.6.1 "Interruptibility state". See @bugref{7445}.
3487 */
3488 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS)
3489 && (pVCpu->hm.s.vmx.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
3490 {
3491 fIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
3492 }
3493
3494 return fIntrState;
3495}
3496
3497
3498/**
3499 * Exports the exception intercepts required for guest execution in the VMCS.
3500 *
3501 * @returns VBox status code.
3502 * @param pVCpu The cross context virtual CPU structure.
3503 *
3504 * @remarks No-long-jump zone!!!
3505 */
3506static int hmR0VmxExportGuestXcptIntercepts(PVMCPU pVCpu)
3507{
3508 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_VMX_GUEST_XCPT_INTERCEPTS)
3509 {
3510 uint32_t uXcptBitmap = pVCpu->hm.s.vmx.u32XcptBitmap;
3511
3512 /* The remaining exception intercepts are handled elsewhere, e.g. in hmR0VmxExportSharedCR0(). */
3513 if (pVCpu->hm.s.fGIMTrapXcptUD)
3514 uXcptBitmap |= RT_BIT(X86_XCPT_UD);
3515#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
3516 else
3517 uXcptBitmap &= ~RT_BIT(X86_XCPT_UD);
3518#endif
3519
3520 Assert(uXcptBitmap & RT_BIT_32(X86_XCPT_AC));
3521 Assert(uXcptBitmap & RT_BIT_32(X86_XCPT_DB));
3522
3523 if (uXcptBitmap != pVCpu->hm.s.vmx.u32XcptBitmap)
3524 {
3525 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, uXcptBitmap);
3526 AssertRCReturn(rc, rc);
3527 pVCpu->hm.s.vmx.u32XcptBitmap = uXcptBitmap;
3528 }
3529
3530 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_VMX_GUEST_XCPT_INTERCEPTS);
3531 Log4Func(("VMX_VMCS32_CTRL_EXCEPTION_BITMAP=%#RX64\n", uXcptBitmap));
3532 }
3533 return VINF_SUCCESS;
3534}
3535
3536
3537/**
3538 * Exports the guest's RIP into the guest-state area in the VMCS.
3539 *
3540 * @returns VBox status code.
3541 * @param pVCpu The cross context virtual CPU structure.
3542 *
3543 * @remarks No-long-jump zone!!!
3544 */
3545static int hmR0VmxExportGuestRip(PVMCPU pVCpu)
3546{
3547 int rc = VINF_SUCCESS;
3548 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_RIP)
3549 {
3550 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RIP);
3551
3552 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_RIP, pVCpu->cpum.GstCtx.rip);
3553 AssertRCReturn(rc, rc);
3554
3555 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_RIP);
3556 Log4Func(("RIP=%#RX64\n", pVCpu->cpum.GstCtx.rip));
3557 }
3558 return rc;
3559}
3560
3561
3562/**
3563 * Exports the guest's RSP into the guest-state area in the VMCS.
3564 *
3565 * @returns VBox status code.
3566 * @param pVCpu The cross context virtual CPU structure.
3567 *
3568 * @remarks No-long-jump zone!!!
3569 */
3570static int hmR0VmxExportGuestRsp(PVMCPU pVCpu)
3571{
3572 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_RSP)
3573 {
3574 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RSP);
3575
3576 int rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_RSP, pVCpu->cpum.GstCtx.rsp);
3577 AssertRCReturn(rc, rc);
3578
3579 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_RSP);
3580 }
3581 return VINF_SUCCESS;
3582}
3583
3584
3585/**
3586 * Exports the guest's RFLAGS into the guest-state area in the VMCS.
3587 *
3588 * @returns VBox status code.
3589 * @param pVCpu The cross context virtual CPU structure.
3590 *
3591 * @remarks No-long-jump zone!!!
3592 */
3593static int hmR0VmxExportGuestRflags(PVMCPU pVCpu)
3594{
3595 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_RFLAGS)
3596 {
3597 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RFLAGS);
3598
3599 /* Intel spec. 2.3.1 "System Flags and Fields in IA-32e Mode" claims the upper 32-bits of RFLAGS are reserved (MBZ).
3600 Let us assert it as such and use 32-bit VMWRITE. */
3601 Assert(!RT_HI_U32(pVCpu->cpum.GstCtx.rflags.u64));
3602 X86EFLAGS fEFlags = pVCpu->cpum.GstCtx.eflags;
3603 Assert(fEFlags.u32 & X86_EFL_RA1_MASK);
3604 Assert(!(fEFlags.u32 & ~(X86_EFL_1 | X86_EFL_LIVE_MASK)));
3605
3606 /*
3607 * If we're emulating real-mode using Virtual 8086 mode, save the real-mode eflags so
3608 * we can restore them on VM-exit. Modify the real-mode guest's eflags so that VT-x
3609 * can run the real-mode guest code under Virtual 8086 mode.
3610 */
3611 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3612 {
3613 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
3614 Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
3615 pVCpu->hm.s.vmx.RealMode.Eflags.u32 = fEFlags.u32; /* Save the original eflags of the real-mode guest. */
3616 fEFlags.Bits.u1VM = 1; /* Set the Virtual 8086 mode bit. */
3617 fEFlags.Bits.u2IOPL = 0; /* Change IOPL to 0, otherwise certain instructions won't fault. */
3618 }
3619
3620 int rc = VMXWriteVmcs32(VMX_VMCS_GUEST_RFLAGS, fEFlags.u32);
3621 AssertRCReturn(rc, rc);
3622
3623 /*
3624 * Setup pending debug exceptions if the guest is single-stepping using EFLAGS.TF.
3625 *
3626 * We must avoid setting any automatic debug exceptions delivery when single-stepping
3627 * through the hypervisor debugger using EFLAGS.TF.
3628 */
3629 if ( !pVCpu->hm.s.fSingleInstruction
3630 && fEFlags.Bits.u1TF)
3631 {
3632 /** @todo r=ramshankar: Warning! We ASSUME EFLAGS.TF will not cleared on
3633 * premature trips to ring-3 esp since IEM does not yet handle it. */
3634 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS);
3635 AssertRCReturn(rc, rc);
3636 }
3637
3638 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_RFLAGS);
3639 Log4Func(("EFlags=%#RX32\n", fEFlags.u32));
3640 }
3641 return VINF_SUCCESS;
3642}
3643
3644
3645/**
3646 * Exports the guest CR0 control register into the guest-state area in the VMCS.
3647 *
3648 * The guest FPU state is always pre-loaded hence we don't need to bother about
3649 * sharing FPU related CR0 bits between the guest and host.
3650 *
3651 * @returns VBox status code.
3652 * @param pVCpu The cross context virtual CPU structure.
3653 *
3654 * @remarks No-long-jump zone!!!
3655 */
3656static int hmR0VmxExportGuestCR0(PVMCPU pVCpu)
3657{
3658 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_CR0)
3659 {
3660 PVM pVM = pVCpu->CTX_SUFF(pVM);
3661 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
3662 Assert(!RT_HI_U32(pVCpu->cpum.GstCtx.cr0));
3663
3664 uint32_t const u32ShadowCr0 = pVCpu->cpum.GstCtx.cr0;
3665 uint32_t u32GuestCr0 = pVCpu->cpum.GstCtx.cr0;
3666
3667 /*
3668 * Setup VT-x's view of the guest CR0.
3669 * Minimize VM-exits due to CR3 changes when we have NestedPaging.
3670 */
3671 uint32_t uProcCtls = pVCpu->hm.s.vmx.u32ProcCtls;
3672 if (pVM->hm.s.fNestedPaging)
3673 {
3674 if (CPUMIsGuestPagingEnabled(pVCpu))
3675 {
3676 /* The guest has paging enabled, let it access CR3 without causing a VM-exit if supported. */
3677 uProcCtls &= ~( VMX_PROC_CTLS_CR3_LOAD_EXIT
3678 | VMX_PROC_CTLS_CR3_STORE_EXIT);
3679 }
3680 else
3681 {
3682 /* The guest doesn't have paging enabled, make CR3 access cause a VM-exit to update our shadow. */
3683 uProcCtls |= VMX_PROC_CTLS_CR3_LOAD_EXIT
3684 | VMX_PROC_CTLS_CR3_STORE_EXIT;
3685 }
3686
3687 /* If we have unrestricted guest execution, we never have to intercept CR3 reads. */
3688 if (pVM->hm.s.vmx.fUnrestrictedGuest)
3689 uProcCtls &= ~VMX_PROC_CTLS_CR3_STORE_EXIT;
3690 }
3691 else
3692 {
3693 /* Guest CPL 0 writes to its read-only pages should cause a #PF VM-exit. */
3694 u32GuestCr0 |= X86_CR0_WP;
3695 }
3696
3697 /*
3698 * Guest FPU bits.
3699 *
3700 * Since we pre-load the guest FPU always before VM-entry there is no need to track lazy state
3701 * using CR0.TS.
3702 *
3703 * Intel spec. 23.8 "Restrictions on VMX operation" mentions that CR0.NE bit must always be
3704 * set on the first CPUs to support VT-x and no mention of with regards to UX in VM-entry checks.
3705 */
3706 u32GuestCr0 |= X86_CR0_NE;
3707
3708 /* If CR0.NE isn't set, we need to intercept #MF exceptions and report them to the guest differently. */
3709 bool const fInterceptMF = !(u32ShadowCr0 & X86_CR0_NE);
3710
3711 /*
3712 * Update exception intercepts.
3713 */
3714 uint32_t uXcptBitmap = pVCpu->hm.s.vmx.u32XcptBitmap;
3715 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3716 {
3717 Assert(PDMVmmDevHeapIsEnabled(pVM));
3718 Assert(pVM->hm.s.vmx.pRealModeTSS);
3719 uXcptBitmap |= HMVMX_REAL_MODE_XCPT_MASK;
3720 }
3721 else
3722 {
3723 /* For now, cleared here as mode-switches can happen outside HM/VT-x. See @bugref{7626#c11}. */
3724 uXcptBitmap &= ~HMVMX_REAL_MODE_XCPT_MASK;
3725 if (fInterceptMF)
3726 uXcptBitmap |= RT_BIT(X86_XCPT_MF);
3727 }
3728
3729 /* Additional intercepts for debugging, define these yourself explicitly. */
3730#ifdef HMVMX_ALWAYS_TRAP_ALL_XCPTS
3731 uXcptBitmap |= 0
3732 | RT_BIT(X86_XCPT_BP)
3733 | RT_BIT(X86_XCPT_DE)
3734 | RT_BIT(X86_XCPT_NM)
3735 | RT_BIT(X86_XCPT_TS)
3736 | RT_BIT(X86_XCPT_UD)
3737 | RT_BIT(X86_XCPT_NP)
3738 | RT_BIT(X86_XCPT_SS)
3739 | RT_BIT(X86_XCPT_GP)
3740 | RT_BIT(X86_XCPT_PF)
3741 | RT_BIT(X86_XCPT_MF)
3742 ;
3743#elif defined(HMVMX_ALWAYS_TRAP_PF)
3744 uXcptBitmap |= RT_BIT(X86_XCPT_PF);
3745#endif
3746 if (pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv)
3747 uXcptBitmap |= RT_BIT(X86_XCPT_GP);
3748 Assert(pVM->hm.s.fNestedPaging || (uXcptBitmap & RT_BIT(X86_XCPT_PF)));
3749
3750 /*
3751 * Set/clear the CR0 specific bits along with their exceptions (PE, PG, CD, NW).
3752 */
3753 uint32_t fSetCr0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
3754 uint32_t fZapCr0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
3755 if (pVM->hm.s.vmx.fUnrestrictedGuest) /* Exceptions for unrestricted-guests for fixed CR0 bits (PE, PG). */
3756 fSetCr0 &= ~(X86_CR0_PE | X86_CR0_PG);
3757 else
3758 Assert((fSetCr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG));
3759
3760 u32GuestCr0 |= fSetCr0;
3761 u32GuestCr0 &= fZapCr0;
3762 u32GuestCr0 &= ~(X86_CR0_CD | X86_CR0_NW); /* Always enable caching. */
3763
3764 /*
3765 * CR0 is shared between host and guest along with a CR0 read shadow. Therefore, certain bits must not be changed
3766 * by the guest because VT-x ignores saving/restoring them (namely CD, ET, NW) and for certain other bits
3767 * we want to be notified immediately of guest CR0 changes (e.g. PG to update our shadow page tables).
3768 */
3769 uint32_t u32Cr0Mask = X86_CR0_PE
3770 | X86_CR0_NE
3771 | (pVM->hm.s.fNestedPaging ? 0 : X86_CR0_WP)
3772 | X86_CR0_PG
3773 | X86_CR0_ET /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.ET */
3774 | X86_CR0_CD /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.CD */
3775 | X86_CR0_NW; /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.NW */
3776
3777 /** @todo Avoid intercepting CR0.PE with unrestricted guests. Fix PGM
3778 * enmGuestMode to be in-sync with the current mode. See @bugref{6398}
3779 * and @bugref{6944}. */
3780#if 0
3781 if (pVM->hm.s.vmx.fUnrestrictedGuest)
3782 u32Cr0Mask &= ~X86_CR0_PE;
3783#endif
3784 /*
3785 * Finally, update VMCS fields with the CR0 values and the exception bitmap.
3786 */
3787 int rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR0, u32GuestCr0);
3788 rc |= VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_READ_SHADOW, u32ShadowCr0);
3789 if (u32Cr0Mask != pVCpu->hm.s.vmx.u32Cr0Mask)
3790 rc |= VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_MASK, u32Cr0Mask);
3791 if (uProcCtls != pVCpu->hm.s.vmx.u32ProcCtls)
3792 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls);
3793 if (uXcptBitmap != pVCpu->hm.s.vmx.u32XcptBitmap)
3794 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, uXcptBitmap);
3795 AssertRCReturn(rc, rc);
3796
3797 /* Update our caches. */
3798 pVCpu->hm.s.vmx.u32Cr0Mask = u32Cr0Mask;
3799 pVCpu->hm.s.vmx.u32ProcCtls = uProcCtls;
3800 pVCpu->hm.s.vmx.u32XcptBitmap = uXcptBitmap;
3801
3802 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_CR0);
3803
3804 Log4Func(("u32Cr0Mask=%#RX32 u32ShadowCr0=%#RX32 u32GuestCr0=%#RX32 (fSetCr0=%#RX32 fZapCr0=%#RX32\n", u32Cr0Mask,
3805 u32ShadowCr0, u32GuestCr0, fSetCr0, fZapCr0));
3806 }
3807
3808 return VINF_SUCCESS;
3809}
3810
3811
3812/**
3813 * Exports the guest control registers (CR3, CR4) into the guest-state area
3814 * in the VMCS.
3815 *
3816 * @returns VBox strict status code.
3817 * @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
3818 * without unrestricted guest access and the VMMDev is not presently
3819 * mapped (e.g. EFI32).
3820 *
3821 * @param pVCpu The cross context virtual CPU structure.
3822 *
3823 * @remarks No-long-jump zone!!!
3824 */
3825static VBOXSTRICTRC hmR0VmxExportGuestCR3AndCR4(PVMCPU pVCpu)
3826{
3827 int rc = VINF_SUCCESS;
3828 PVM pVM = pVCpu->CTX_SUFF(pVM);
3829
3830 /*
3831 * Guest CR2.
3832 * It's always loaded in the assembler code. Nothing to do here.
3833 */
3834
3835 /*
3836 * Guest CR3.
3837 */
3838 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_CR3)
3839 {
3840 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
3841
3842 RTGCPHYS GCPhysGuestCR3 = NIL_RTGCPHYS;
3843 if (pVM->hm.s.fNestedPaging)
3844 {
3845 pVCpu->hm.s.vmx.HCPhysEPTP = PGMGetHyperCR3(pVCpu);
3846
3847 /* Validate. See Intel spec. 28.2.2 "EPT Translation Mechanism" and 24.6.11 "Extended-Page-Table Pointer (EPTP)" */
3848 Assert(pVCpu->hm.s.vmx.HCPhysEPTP);
3849 Assert(!(pVCpu->hm.s.vmx.HCPhysEPTP & UINT64_C(0xfff0000000000000)));
3850 Assert(!(pVCpu->hm.s.vmx.HCPhysEPTP & 0xfff));
3851
3852 /* VMX_EPT_MEMTYPE_WB support is already checked in hmR0VmxSetupTaggedTlb(). */
3853 pVCpu->hm.s.vmx.HCPhysEPTP |= VMX_EPT_MEMTYPE_WB
3854 | (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
3855
3856 /* Validate. See Intel spec. 26.2.1 "Checks on VMX Controls" */
3857 AssertMsg( ((pVCpu->hm.s.vmx.HCPhysEPTP >> 3) & 0x07) == 3 /* Bits 3:5 (EPT page walk length - 1) must be 3. */
3858 && ((pVCpu->hm.s.vmx.HCPhysEPTP >> 7) & 0x1f) == 0, /* Bits 7:11 MBZ. */
3859 ("EPTP %#RX64\n", pVCpu->hm.s.vmx.HCPhysEPTP));
3860 AssertMsg( !((pVCpu->hm.s.vmx.HCPhysEPTP >> 6) & 0x01) /* Bit 6 (EPT accessed & dirty bit). */
3861 || (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY),
3862 ("EPTP accessed/dirty bit not supported by CPU but set %#RX64\n", pVCpu->hm.s.vmx.HCPhysEPTP));
3863
3864 rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, pVCpu->hm.s.vmx.HCPhysEPTP);
3865 AssertRCReturn(rc, rc);
3866
3867 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3868 if ( pVM->hm.s.vmx.fUnrestrictedGuest
3869 || CPUMIsGuestPagingEnabledEx(pCtx))
3870 {
3871 /* If the guest is in PAE mode, pass the PDPEs to VT-x using the VMCS fields. */
3872 if (CPUMIsGuestInPAEModeEx(pCtx))
3873 {
3874 rc = PGMGstGetPaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
3875 AssertRCReturn(rc, rc);
3876 rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, pVCpu->hm.s.aPdpes[0].u);
3877 rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, pVCpu->hm.s.aPdpes[1].u);
3878 rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, pVCpu->hm.s.aPdpes[2].u);
3879 rc |= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, pVCpu->hm.s.aPdpes[3].u);
3880 AssertRCReturn(rc, rc);
3881 }
3882
3883 /*
3884 * The guest's view of its CR3 is unblemished with Nested Paging when the
3885 * guest is using paging or we have unrestricted guest execution to handle
3886 * the guest when it's not using paging.
3887 */
3888 GCPhysGuestCR3 = pCtx->cr3;
3889 }
3890 else
3891 {
3892 /*
3893 * The guest is not using paging, but the CPU (VT-x) has to. While the guest
3894 * thinks it accesses physical memory directly, we use our identity-mapped
3895 * page table to map guest-linear to guest-physical addresses. EPT takes care
3896 * of translating it to host-physical addresses.
3897 */
3898 RTGCPHYS GCPhys;
3899 Assert(pVM->hm.s.vmx.pNonPagingModeEPTPageTable);
3900
3901 /* We obtain it here every time as the guest could have relocated this PCI region. */
3902 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
3903 if (RT_SUCCESS(rc))
3904 { /* likely */ }
3905 else if (rc == VERR_PDM_DEV_HEAP_R3_TO_GCPHYS)
3906 {
3907 Log4Func(("VERR_PDM_DEV_HEAP_R3_TO_GCPHYS -> VINF_EM_RESCHEDULE_REM\n"));
3908 return VINF_EM_RESCHEDULE_REM; /* We cannot execute now, switch to REM/IEM till the guest maps in VMMDev. */
3909 }
3910 else
3911 AssertMsgFailedReturn(("%Rrc\n", rc), rc);
3912
3913 GCPhysGuestCR3 = GCPhys;
3914 }
3915
3916 Log4Func(("u32GuestCr3=%#RGp (GstN)\n", GCPhysGuestCR3));
3917 rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_CR3, GCPhysGuestCR3);
3918 AssertRCReturn(rc, rc);
3919 }
3920 else
3921 {
3922 /* Non-nested paging case, just use the hypervisor's CR3. */
3923 RTHCPHYS HCPhysGuestCR3 = PGMGetHyperCR3(pVCpu);
3924
3925 Log4Func(("u32GuestCr3=%#RHv (HstN)\n", HCPhysGuestCR3));
3926 rc = VMXWriteVmcsHstN(VMX_VMCS_GUEST_CR3, HCPhysGuestCR3);
3927 AssertRCReturn(rc, rc);
3928 }
3929
3930 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_CR3);
3931 }
3932
3933 /*
3934 * Guest CR4.
3935 * ASSUMES this is done everytime we get in from ring-3! (XCR0)
3936 */
3937 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_CR4)
3938 {
3939 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3940 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
3941 Assert(!RT_HI_U32(pCtx->cr4));
3942
3943 uint32_t u32GuestCr4 = pCtx->cr4;
3944 uint32_t const u32ShadowCr4 = pCtx->cr4;
3945
3946 /*
3947 * Setup VT-x's view of the guest CR4.
3948 *
3949 * If we're emulating real-mode using virtual-8086 mode, we want to redirect software
3950 * interrupts to the 8086 program interrupt handler. Clear the VME bit (the interrupt
3951 * redirection bitmap is already all 0, see hmR3InitFinalizeR0())
3952 *
3953 * See Intel spec. 20.2 "Software Interrupt Handling Methods While in Virtual-8086 Mode".
3954 */
3955 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3956 {
3957 Assert(pVM->hm.s.vmx.pRealModeTSS);
3958 Assert(PDMVmmDevHeapIsEnabled(pVM));
3959 u32GuestCr4 &= ~X86_CR4_VME;
3960 }
3961
3962 if (pVM->hm.s.fNestedPaging)
3963 {
3964 if ( !CPUMIsGuestPagingEnabledEx(pCtx)
3965 && !pVM->hm.s.vmx.fUnrestrictedGuest)
3966 {
3967 /* We use 4 MB pages in our identity mapping page table when the guest doesn't have paging. */
3968 u32GuestCr4 |= X86_CR4_PSE;
3969 /* Our identity mapping is a 32-bit page directory. */
3970 u32GuestCr4 &= ~X86_CR4_PAE;
3971 }
3972 /* else use guest CR4.*/
3973 }
3974 else
3975 {
3976 /*
3977 * The shadow paging modes and guest paging modes are different, the shadow is in accordance with the host
3978 * paging mode and thus we need to adjust VT-x's view of CR4 depending on our shadow page tables.
3979 */
3980 switch (pVCpu->hm.s.enmShadowMode)
3981 {
3982 case PGMMODE_REAL: /* Real-mode. */
3983 case PGMMODE_PROTECTED: /* Protected mode without paging. */
3984 case PGMMODE_32_BIT: /* 32-bit paging. */
3985 {
3986 u32GuestCr4 &= ~X86_CR4_PAE;
3987 break;
3988 }
3989
3990 case PGMMODE_PAE: /* PAE paging. */
3991 case PGMMODE_PAE_NX: /* PAE paging with NX. */
3992 {
3993 u32GuestCr4 |= X86_CR4_PAE;
3994 break;
3995 }
3996
3997 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
3998 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
3999#ifdef VBOX_ENABLE_64_BITS_GUESTS
4000 break;
4001#endif
4002 default:
4003 AssertFailed();
4004 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
4005 }
4006 }
4007
4008 /* We need to set and clear the CR4 specific bits here (mainly the X86_CR4_VMXE bit). */
4009 uint64_t const fSetCr4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
4010 uint64_t const fZapCr4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
4011 u32GuestCr4 |= fSetCr4;
4012 u32GuestCr4 &= fZapCr4;
4013
4014 /* Setup CR4 mask. CR4 flags owned by the host, if the guest attempts to change them,
4015 that would cause a VM-exit. */
4016 uint32_t u32Cr4Mask = X86_CR4_VME
4017 | X86_CR4_PAE
4018 | X86_CR4_PGE
4019 | X86_CR4_PSE
4020 | X86_CR4_VMXE;
4021 if (pVM->cpum.ro.HostFeatures.fXSaveRstor)
4022 u32Cr4Mask |= X86_CR4_OSXSAVE;
4023 if (pVM->cpum.ro.GuestFeatures.fPcid)
4024 u32Cr4Mask |= X86_CR4_PCIDE;
4025
4026 /* Write VT-x's view of the guest CR4, the CR4 modify mask and the read-only CR4 shadow
4027 into the VMCS and update our cache. */
4028 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR4, u32GuestCr4);
4029 rc |= VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_READ_SHADOW, u32ShadowCr4);
4030 if (pVCpu->hm.s.vmx.u32Cr4Mask != u32Cr4Mask)
4031 rc |= VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_MASK, u32Cr4Mask);
4032 AssertRCReturn(rc, rc);
4033 pVCpu->hm.s.vmx.u32Cr4Mask = u32Cr4Mask;
4034
4035 /* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
4036 pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
4037
4038 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_CR4);
4039
4040 Log4Func(("u32GuestCr4=%#RX32 u32ShadowCr4=%#RX32 (fSetCr4=%#RX32 fZapCr4=%#RX32)\n", u32GuestCr4, u32ShadowCr4, fSetCr4,
4041 fZapCr4));
4042 }
4043 return rc;
4044}
4045
4046
4047/**
4048 * Exports the guest debug registers into the guest-state area in the VMCS.
4049 * The guest debug bits are partially shared with the host (e.g. DR6, DR0-3).
4050 *
4051 * This also sets up whether \#DB and MOV DRx accesses cause VM-exits.
4052 *
4053 * @returns VBox status code.
4054 * @param pVCpu The cross context virtual CPU structure.
4055 *
4056 * @remarks No-long-jump zone!!!
4057 */
4058static int hmR0VmxExportSharedDebugState(PVMCPU pVCpu)
4059{
4060 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4061
4062#ifdef VBOX_STRICT
4063 /* Validate. Intel spec. 26.3.1.1 "Checks on Guest Controls Registers, Debug Registers, MSRs" */
4064 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
4065 {
4066 /* Validate. Intel spec. 17.2 "Debug Registers", recompiler paranoia checks. */
4067 Assert((pVCpu->cpum.GstCtx.dr[7] & (X86_DR7_MBZ_MASK | X86_DR7_RAZ_MASK)) == 0);
4068 Assert((pVCpu->cpum.GstCtx.dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK);
4069 }
4070#endif
4071
4072 bool fSteppingDB = false;
4073 bool fInterceptMovDRx = false;
4074 uint32_t uProcCtls = pVCpu->hm.s.vmx.u32ProcCtls;
4075 if (pVCpu->hm.s.fSingleInstruction)
4076 {
4077 /* If the CPU supports the monitor trap flag, use it for single stepping in DBGF and avoid intercepting #DB. */
4078 PVM pVM = pVCpu->CTX_SUFF(pVM);
4079 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
4080 {
4081 uProcCtls |= VMX_PROC_CTLS_MONITOR_TRAP_FLAG;
4082 Assert(fSteppingDB == false);
4083 }
4084 else
4085 {
4086 pVCpu->cpum.GstCtx.eflags.u32 |= X86_EFL_TF;
4087 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_GUEST_RFLAGS;
4088 pVCpu->hm.s.fClearTrapFlag = true;
4089 fSteppingDB = true;
4090 }
4091 }
4092
4093 uint32_t u32GuestDr7;
4094 if ( fSteppingDB
4095 || (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
4096 {
4097 /*
4098 * Use the combined guest and host DRx values found in the hypervisor register set
4099 * because the debugger has breakpoints active or someone is single stepping on the
4100 * host side without a monitor trap flag.
4101 *
4102 * Note! DBGF expects a clean DR6 state before executing guest code.
4103 */
4104#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4105 if ( CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx)
4106 && !CPUMIsHyperDebugStateActivePending(pVCpu))
4107 {
4108 CPUMR0LoadHyperDebugState(pVCpu, true /* include DR6 */);
4109 Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
4110 Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
4111 }
4112 else
4113#endif
4114 if (!CPUMIsHyperDebugStateActive(pVCpu))
4115 {
4116 CPUMR0LoadHyperDebugState(pVCpu, true /* include DR6 */);
4117 Assert(CPUMIsHyperDebugStateActive(pVCpu));
4118 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
4119 }
4120
4121 /* Update DR7 with the hypervisor value (other DRx registers are handled by CPUM one way or another). */
4122 u32GuestDr7 = (uint32_t)CPUMGetHyperDR7(pVCpu);
4123 pVCpu->hm.s.fUsingHyperDR7 = true;
4124 fInterceptMovDRx = true;
4125 }
4126 else
4127 {
4128 /*
4129 * If the guest has enabled debug registers, we need to load them prior to
4130 * executing guest code so they'll trigger at the right time.
4131 */
4132 if (pVCpu->cpum.GstCtx.dr[7] & (X86_DR7_ENABLED_MASK | X86_DR7_GD))
4133 {
4134#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4135 if ( CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx)
4136 && !CPUMIsGuestDebugStateActivePending(pVCpu))
4137 {
4138 CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
4139 Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
4140 Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
4141 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
4142 }
4143 else
4144#endif
4145 if (!CPUMIsGuestDebugStateActive(pVCpu))
4146 {
4147 CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
4148 Assert(CPUMIsGuestDebugStateActive(pVCpu));
4149 Assert(!CPUMIsHyperDebugStateActive(pVCpu));
4150 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
4151 }
4152 Assert(!fInterceptMovDRx);
4153 }
4154 /*
4155 * If no debugging enabled, we'll lazy load DR0-3. Unlike on AMD-V, we
4156 * must intercept #DB in order to maintain a correct DR6 guest value, and
4157 * because we need to intercept it to prevent nested #DBs from hanging the
4158 * CPU, we end up always having to intercept it. See hmR0VmxInitXcptBitmap.
4159 */
4160#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4161 else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
4162 && !CPUMIsGuestDebugStateActive(pVCpu))
4163#else
4164 else if (!CPUMIsGuestDebugStateActive(pVCpu))
4165#endif
4166 {
4167 fInterceptMovDRx = true;
4168 }
4169
4170 /* Update DR7 with the actual guest value. */
4171 u32GuestDr7 = pVCpu->cpum.GstCtx.dr[7];
4172 pVCpu->hm.s.fUsingHyperDR7 = false;
4173 }
4174
4175 if (fInterceptMovDRx)
4176 uProcCtls |= VMX_PROC_CTLS_MOV_DR_EXIT;
4177 else
4178 uProcCtls &= ~VMX_PROC_CTLS_MOV_DR_EXIT;
4179
4180 /*
4181 * Update the processor-based VM-execution controls with the MOV-DRx intercepts and the
4182 * monitor-trap flag and update our cache.
4183 */
4184 if (uProcCtls != pVCpu->hm.s.vmx.u32ProcCtls)
4185 {
4186 int rc2 = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls);
4187 AssertRCReturn(rc2, rc2);
4188 pVCpu->hm.s.vmx.u32ProcCtls = uProcCtls;
4189 }
4190
4191 /*
4192 * Update guest DR7.
4193 */
4194 int rc = VMXWriteVmcs32(VMX_VMCS_GUEST_DR7, u32GuestDr7);
4195 AssertRCReturn(rc, rc);
4196
4197 /*
4198 * If we have forced EFLAGS.TF to be set because we're single-stepping in the hypervisor debugger,
4199 * we need to clear interrupt inhibition if any as otherwise it causes a VM-entry failure.
4200 *
4201 * See Intel spec. 26.3.1.5 "Checks on Guest Non-Register State".
4202 */
4203 if (fSteppingDB)
4204 {
4205 Assert(pVCpu->hm.s.fSingleInstruction);
4206 Assert(pVCpu->cpum.GstCtx.eflags.Bits.u1TF);
4207
4208 uint32_t fIntrState = 0;
4209 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &fIntrState);
4210 AssertRCReturn(rc, rc);
4211
4212 if (fIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
4213 {
4214 fIntrState &= ~(VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS);
4215 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_INT_STATE, fIntrState);
4216 AssertRCReturn(rc, rc);
4217 }
4218 }
4219
4220 return VINF_SUCCESS;
4221}
4222
4223
4224#ifdef VBOX_STRICT
4225/**
4226 * Strict function to validate segment registers.
4227 *
4228 * @param pVCpu The cross context virtual CPU structure.
4229 *
4230 * @remarks Will import guest CR0 on strict builds during validation of
4231 * segments.
4232 */
4233static void hmR0VmxValidateSegmentRegs(PVMCPU pVCpu)
4234{
4235 /*
4236 * Validate segment registers. See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
4237 *
4238 * The reason we check for attribute value 0 in this function and not just the unusable bit is
4239 * because hmR0VmxExportGuestSegmentReg() only updates the VMCS' copy of the value with the unusable bit
4240 * and doesn't change the guest-context value.
4241 */
4242 PVM pVM = pVCpu->CTX_SUFF(pVM);
4243 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4244 hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CR0);
4245 if ( !pVM->hm.s.vmx.fUnrestrictedGuest
4246 && ( !CPUMIsGuestInRealModeEx(pCtx)
4247 && !CPUMIsGuestInV86ModeEx(pCtx)))
4248 {
4249 /* Protected mode checks */
4250 /* CS */
4251 Assert(pCtx->cs.Attr.n.u1Present);
4252 Assert(!(pCtx->cs.Attr.u & 0xf00));
4253 Assert(!(pCtx->cs.Attr.u & 0xfffe0000));
4254 Assert( (pCtx->cs.u32Limit & 0xfff) == 0xfff
4255 || !(pCtx->cs.Attr.n.u1Granularity));
4256 Assert( !(pCtx->cs.u32Limit & 0xfff00000)
4257 || (pCtx->cs.Attr.n.u1Granularity));
4258 /* CS cannot be loaded with NULL in protected mode. */
4259 Assert(pCtx->cs.Attr.u && !(pCtx->cs.Attr.u & X86DESCATTR_UNUSABLE)); /** @todo is this really true even for 64-bit CS? */
4260 if (pCtx->cs.Attr.n.u4Type == 9 || pCtx->cs.Attr.n.u4Type == 11)
4261 Assert(pCtx->cs.Attr.n.u2Dpl == pCtx->ss.Attr.n.u2Dpl);
4262 else if (pCtx->cs.Attr.n.u4Type == 13 || pCtx->cs.Attr.n.u4Type == 15)
4263 Assert(pCtx->cs.Attr.n.u2Dpl <= pCtx->ss.Attr.n.u2Dpl);
4264 else
4265 AssertMsgFailed(("Invalid CS Type %#x\n", pCtx->cs.Attr.n.u2Dpl));
4266 /* SS */
4267 Assert((pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL));
4268 Assert(pCtx->ss.Attr.n.u2Dpl == (pCtx->ss.Sel & X86_SEL_RPL));
4269 if ( !(pCtx->cr0 & X86_CR0_PE)
4270 || pCtx->cs.Attr.n.u4Type == 3)
4271 {
4272 Assert(!pCtx->ss.Attr.n.u2Dpl);
4273 }
4274 if (pCtx->ss.Attr.u && !(pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE))
4275 {
4276 Assert((pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL));
4277 Assert(pCtx->ss.Attr.n.u4Type == 3 || pCtx->ss.Attr.n.u4Type == 7);
4278 Assert(pCtx->ss.Attr.n.u1Present);
4279 Assert(!(pCtx->ss.Attr.u & 0xf00));
4280 Assert(!(pCtx->ss.Attr.u & 0xfffe0000));
4281 Assert( (pCtx->ss.u32Limit & 0xfff) == 0xfff
4282 || !(pCtx->ss.Attr.n.u1Granularity));
4283 Assert( !(pCtx->ss.u32Limit & 0xfff00000)
4284 || (pCtx->ss.Attr.n.u1Granularity));
4285 }
4286 /* DS, ES, FS, GS - only check for usable selectors, see hmR0VmxExportGuestSegmentReg(). */
4287 if (pCtx->ds.Attr.u && !(pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE))
4288 {
4289 Assert(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4290 Assert(pCtx->ds.Attr.n.u1Present);
4291 Assert(pCtx->ds.Attr.n.u4Type > 11 || pCtx->ds.Attr.n.u2Dpl >= (pCtx->ds.Sel & X86_SEL_RPL));
4292 Assert(!(pCtx->ds.Attr.u & 0xf00));
4293 Assert(!(pCtx->ds.Attr.u & 0xfffe0000));
4294 Assert( (pCtx->ds.u32Limit & 0xfff) == 0xfff
4295 || !(pCtx->ds.Attr.n.u1Granularity));
4296 Assert( !(pCtx->ds.u32Limit & 0xfff00000)
4297 || (pCtx->ds.Attr.n.u1Granularity));
4298 Assert( !(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4299 || (pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_READ));
4300 }
4301 if (pCtx->es.Attr.u && !(pCtx->es.Attr.u & X86DESCATTR_UNUSABLE))
4302 {
4303 Assert(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4304 Assert(pCtx->es.Attr.n.u1Present);
4305 Assert(pCtx->es.Attr.n.u4Type > 11 || pCtx->es.Attr.n.u2Dpl >= (pCtx->es.Sel & X86_SEL_RPL));
4306 Assert(!(pCtx->es.Attr.u & 0xf00));
4307 Assert(!(pCtx->es.Attr.u & 0xfffe0000));
4308 Assert( (pCtx->es.u32Limit & 0xfff) == 0xfff
4309 || !(pCtx->es.Attr.n.u1Granularity));
4310 Assert( !(pCtx->es.u32Limit & 0xfff00000)
4311 || (pCtx->es.Attr.n.u1Granularity));
4312 Assert( !(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4313 || (pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_READ));
4314 }
4315 if (pCtx->fs.Attr.u && !(pCtx->fs.Attr.u & X86DESCATTR_UNUSABLE))
4316 {
4317 Assert(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4318 Assert(pCtx->fs.Attr.n.u1Present);
4319 Assert(pCtx->fs.Attr.n.u4Type > 11 || pCtx->fs.Attr.n.u2Dpl >= (pCtx->fs.Sel & X86_SEL_RPL));
4320 Assert(!(pCtx->fs.Attr.u & 0xf00));
4321 Assert(!(pCtx->fs.Attr.u & 0xfffe0000));
4322 Assert( (pCtx->fs.u32Limit & 0xfff) == 0xfff
4323 || !(pCtx->fs.Attr.n.u1Granularity));
4324 Assert( !(pCtx->fs.u32Limit & 0xfff00000)
4325 || (pCtx->fs.Attr.n.u1Granularity));
4326 Assert( !(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4327 || (pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_READ));
4328 }
4329 if (pCtx->gs.Attr.u && !(pCtx->gs.Attr.u & X86DESCATTR_UNUSABLE))
4330 {
4331 Assert(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4332 Assert(pCtx->gs.Attr.n.u1Present);
4333 Assert(pCtx->gs.Attr.n.u4Type > 11 || pCtx->gs.Attr.n.u2Dpl >= (pCtx->gs.Sel & X86_SEL_RPL));
4334 Assert(!(pCtx->gs.Attr.u & 0xf00));
4335 Assert(!(pCtx->gs.Attr.u & 0xfffe0000));
4336 Assert( (pCtx->gs.u32Limit & 0xfff) == 0xfff
4337 || !(pCtx->gs.Attr.n.u1Granularity));
4338 Assert( !(pCtx->gs.u32Limit & 0xfff00000)
4339 || (pCtx->gs.Attr.n.u1Granularity));
4340 Assert( !(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4341 || (pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_READ));
4342 }
4343 /* 64-bit capable CPUs. */
4344# if HC_ARCH_BITS == 64
4345 Assert(!RT_HI_U32(pCtx->cs.u64Base));
4346 Assert(!pCtx->ss.Attr.u || !RT_HI_U32(pCtx->ss.u64Base));
4347 Assert(!pCtx->ds.Attr.u || !RT_HI_U32(pCtx->ds.u64Base));
4348 Assert(!pCtx->es.Attr.u || !RT_HI_U32(pCtx->es.u64Base));
4349# endif
4350 }
4351 else if ( CPUMIsGuestInV86ModeEx(pCtx)
4352 || ( CPUMIsGuestInRealModeEx(pCtx)
4353 && !pVM->hm.s.vmx.fUnrestrictedGuest))
4354 {
4355 /* Real and v86 mode checks. */
4356 /* hmR0VmxExportGuestSegmentReg() writes the modified in VMCS. We want what we're feeding to VT-x. */
4357 uint32_t u32CSAttr, u32SSAttr, u32DSAttr, u32ESAttr, u32FSAttr, u32GSAttr;
4358 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4359 {
4360 u32CSAttr = 0xf3; u32SSAttr = 0xf3; u32DSAttr = 0xf3; u32ESAttr = 0xf3; u32FSAttr = 0xf3; u32GSAttr = 0xf3;
4361 }
4362 else
4363 {
4364 u32CSAttr = pCtx->cs.Attr.u; u32SSAttr = pCtx->ss.Attr.u; u32DSAttr = pCtx->ds.Attr.u;
4365 u32ESAttr = pCtx->es.Attr.u; u32FSAttr = pCtx->fs.Attr.u; u32GSAttr = pCtx->gs.Attr.u;
4366 }
4367
4368 /* CS */
4369 AssertMsg((pCtx->cs.u64Base == (uint64_t)pCtx->cs.Sel << 4), ("CS base %#x %#x\n", pCtx->cs.u64Base, pCtx->cs.Sel));
4370 Assert(pCtx->cs.u32Limit == 0xffff);
4371 Assert(u32CSAttr == 0xf3);
4372 /* SS */
4373 Assert(pCtx->ss.u64Base == (uint64_t)pCtx->ss.Sel << 4);
4374 Assert(pCtx->ss.u32Limit == 0xffff);
4375 Assert(u32SSAttr == 0xf3);
4376 /* DS */
4377 Assert(pCtx->ds.u64Base == (uint64_t)pCtx->ds.Sel << 4);
4378 Assert(pCtx->ds.u32Limit == 0xffff);
4379 Assert(u32DSAttr == 0xf3);
4380 /* ES */
4381 Assert(pCtx->es.u64Base == (uint64_t)pCtx->es.Sel << 4);
4382 Assert(pCtx->es.u32Limit == 0xffff);
4383 Assert(u32ESAttr == 0xf3);
4384 /* FS */
4385 Assert(pCtx->fs.u64Base == (uint64_t)pCtx->fs.Sel << 4);
4386 Assert(pCtx->fs.u32Limit == 0xffff);
4387 Assert(u32FSAttr == 0xf3);
4388 /* GS */
4389 Assert(pCtx->gs.u64Base == (uint64_t)pCtx->gs.Sel << 4);
4390 Assert(pCtx->gs.u32Limit == 0xffff);
4391 Assert(u32GSAttr == 0xf3);
4392 /* 64-bit capable CPUs. */
4393# if HC_ARCH_BITS == 64
4394 Assert(!RT_HI_U32(pCtx->cs.u64Base));
4395 Assert(!u32SSAttr || !RT_HI_U32(pCtx->ss.u64Base));
4396 Assert(!u32DSAttr || !RT_HI_U32(pCtx->ds.u64Base));
4397 Assert(!u32ESAttr || !RT_HI_U32(pCtx->es.u64Base));
4398# endif
4399 }
4400}
4401#endif /* VBOX_STRICT */
4402
4403
4404/**
4405 * Exports a guest segment register into the guest-state area in the VMCS.
4406 *
4407 * @returns VBox status code.
4408 * @param pVCpu The cross context virtual CPU structure.
4409 * @param idxSel Index of the selector in the VMCS.
4410 * @param idxLimit Index of the segment limit in the VMCS.
4411 * @param idxBase Index of the segment base in the VMCS.
4412 * @param idxAccess Index of the access rights of the segment in the VMCS.
4413 * @param pSelReg Pointer to the segment selector.
4414 *
4415 * @remarks No-long-jump zone!!!
4416 */
4417static int hmR0VmxExportGuestSegmentReg(PVMCPU pVCpu, uint32_t idxSel, uint32_t idxLimit, uint32_t idxBase, uint32_t idxAccess,
4418 PCCPUMSELREG pSelReg)
4419{
4420 int rc = VMXWriteVmcs32(idxSel, pSelReg->Sel); /* 16-bit guest selector field. */
4421 rc |= VMXWriteVmcs32(idxLimit, pSelReg->u32Limit); /* 32-bit guest segment limit field. */
4422 rc |= VMXWriteVmcsGstN(idxBase, pSelReg->u64Base); /* Natural width guest segment base field.*/
4423 AssertRCReturn(rc, rc);
4424
4425 uint32_t u32Access = pSelReg->Attr.u;
4426 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4427 {
4428 /* VT-x requires our real-using-v86 mode hack to override the segment access-right bits. */
4429 u32Access = 0xf3;
4430 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
4431 Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
4432 }
4433 else
4434 {
4435 /*
4436 * The way to differentiate between whether this is really a null selector or was just
4437 * a selector loaded with 0 in real-mode is using the segment attributes. A selector
4438 * loaded in real-mode with the value 0 is valid and usable in protected-mode and we
4439 * should -not- mark it as an unusable segment. Both the recompiler & VT-x ensures
4440 * NULL selectors loaded in protected-mode have their attribute as 0.
4441 */
4442 if (!u32Access)
4443 u32Access = X86DESCATTR_UNUSABLE;
4444 }
4445
4446 /* Validate segment access rights. Refer to Intel spec. "26.3.1.2 Checks on Guest Segment Registers". */
4447 AssertMsg((u32Access & X86DESCATTR_UNUSABLE) || (u32Access & X86_SEL_TYPE_ACCESSED),
4448 ("Access bit not set for usable segment. idx=%#x sel=%#x attr %#x\n", idxBase, pSelReg, pSelReg->Attr.u));
4449
4450 rc = VMXWriteVmcs32(idxAccess, u32Access); /* 32-bit guest segment access-rights field. */
4451 AssertRCReturn(rc, rc);
4452 return rc;
4453}
4454
4455
4456/**
4457 * Exports the guest segment registers, GDTR, IDTR, LDTR, (TR, FS and GS bases)
4458 * into the guest-state area in the VMCS.
4459 *
4460 * @returns VBox status code.
4461 * @param pVCpu The cross context virtual CPU structure.
4462 *
4463 * @remarks Will import guest CR0 on strict builds during validation of
4464 * segments.
4465 * @remarks No-long-jump zone!!!
4466 */
4467static int hmR0VmxExportGuestSegmentRegs(PVMCPU pVCpu)
4468{
4469 int rc = VERR_INTERNAL_ERROR_5;
4470 PVM pVM = pVCpu->CTX_SUFF(pVM);
4471 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4472
4473 /*
4474 * Guest Segment registers: CS, SS, DS, ES, FS, GS.
4475 */
4476 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SREG_MASK)
4477 {
4478#ifdef VBOX_WITH_REM
4479 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
4480 {
4481 Assert(pVM->hm.s.vmx.pRealModeTSS);
4482 AssertCompile(PGMMODE_REAL < PGMMODE_PROTECTED);
4483 if ( pVCpu->hm.s.vmx.fWasInRealMode
4484 && PGMGetGuestMode(pVCpu) >= PGMMODE_PROTECTED)
4485 {
4486 /* Signal that the recompiler must flush its code-cache as the guest -may- rewrite code it will later execute
4487 in real-mode (e.g. OpenBSD 4.0) */
4488 REMFlushTBs(pVM);
4489 Log4Func(("Switch to protected mode detected!\n"));
4490 pVCpu->hm.s.vmx.fWasInRealMode = false;
4491 }
4492 }
4493#endif
4494 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_CS)
4495 {
4496 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS);
4497 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4498 pVCpu->hm.s.vmx.RealMode.AttrCS.u = pCtx->cs.Attr.u;
4499 rc = HMVMX_EXPORT_SREG(CS, &pCtx->cs);
4500 AssertRCReturn(rc, rc);
4501 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_CS);
4502 }
4503
4504 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SS)
4505 {
4506 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SS);
4507 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4508 pVCpu->hm.s.vmx.RealMode.AttrSS.u = pCtx->ss.Attr.u;
4509 rc = HMVMX_EXPORT_SREG(SS, &pCtx->ss);
4510 AssertRCReturn(rc, rc);
4511 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_SS);
4512 }
4513
4514 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_DS)
4515 {
4516 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DS);
4517 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4518 pVCpu->hm.s.vmx.RealMode.AttrDS.u = pCtx->ds.Attr.u;
4519 rc = HMVMX_EXPORT_SREG(DS, &pCtx->ds);
4520 AssertRCReturn(rc, rc);
4521 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_DS);
4522 }
4523
4524 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_ES)
4525 {
4526 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_ES);
4527 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4528 pVCpu->hm.s.vmx.RealMode.AttrES.u = pCtx->es.Attr.u;
4529 rc = HMVMX_EXPORT_SREG(ES, &pCtx->es);
4530 AssertRCReturn(rc, rc);
4531 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_ES);
4532 }
4533
4534 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_FS)
4535 {
4536 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_FS);
4537 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4538 pVCpu->hm.s.vmx.RealMode.AttrFS.u = pCtx->fs.Attr.u;
4539 rc = HMVMX_EXPORT_SREG(FS, &pCtx->fs);
4540 AssertRCReturn(rc, rc);
4541 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_FS);
4542 }
4543
4544 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_GS)
4545 {
4546 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_GS);
4547 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4548 pVCpu->hm.s.vmx.RealMode.AttrGS.u = pCtx->gs.Attr.u;
4549 rc = HMVMX_EXPORT_SREG(GS, &pCtx->gs);
4550 AssertRCReturn(rc, rc);
4551 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_GS);
4552 }
4553
4554#ifdef VBOX_STRICT
4555 hmR0VmxValidateSegmentRegs(pVCpu);
4556#endif
4557
4558 Log4Func(("CS=%#RX16 Base=%#RX64 Limit=%#RX32 Attr=%#RX32\n", pCtx->cs.Sel, pCtx->cs.u64Base,
4559 pCtx->cs.u32Limit, pCtx->cs.Attr.u));
4560 }
4561
4562 /*
4563 * Guest TR.
4564 */
4565 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_TR)
4566 {
4567 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_TR);
4568
4569 /*
4570 * Real-mode emulation using virtual-8086 mode with CR4.VME. Interrupt redirection is
4571 * achieved using the interrupt redirection bitmap (all bits cleared to let the guest
4572 * handle INT-n's) in the TSS. See hmR3InitFinalizeR0() to see how pRealModeTSS is setup.
4573 */
4574 uint16_t u16Sel = 0;
4575 uint32_t u32Limit = 0;
4576 uint64_t u64Base = 0;
4577 uint32_t u32AccessRights = 0;
4578
4579 if (!pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4580 {
4581 u16Sel = pCtx->tr.Sel;
4582 u32Limit = pCtx->tr.u32Limit;
4583 u64Base = pCtx->tr.u64Base;
4584 u32AccessRights = pCtx->tr.Attr.u;
4585 }
4586 else
4587 {
4588 Assert(pVM->hm.s.vmx.pRealModeTSS);
4589 Assert(PDMVmmDevHeapIsEnabled(pVM)); /* Guaranteed by HMCanExecuteGuest() -XXX- what about inner loop changes? */
4590
4591 /* We obtain it here every time as PCI regions could be reconfigured in the guest, changing the VMMDev base. */
4592 RTGCPHYS GCPhys;
4593 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
4594 AssertRCReturn(rc, rc);
4595
4596 X86DESCATTR DescAttr;
4597 DescAttr.u = 0;
4598 DescAttr.n.u1Present = 1;
4599 DescAttr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
4600
4601 u16Sel = 0;
4602 u32Limit = HM_VTX_TSS_SIZE;
4603 u64Base = GCPhys; /* in real-mode phys = virt. */
4604 u32AccessRights = DescAttr.u;
4605 }
4606
4607 /* Validate. */
4608 Assert(!(u16Sel & RT_BIT(2)));
4609 AssertMsg( (u32AccessRights & 0xf) == X86_SEL_TYPE_SYS_386_TSS_BUSY
4610 || (u32AccessRights & 0xf) == X86_SEL_TYPE_SYS_286_TSS_BUSY, ("TSS is not busy!? %#x\n", u32AccessRights));
4611 AssertMsg(!(u32AccessRights & X86DESCATTR_UNUSABLE), ("TR unusable bit is not clear!? %#x\n", u32AccessRights));
4612 Assert(!(u32AccessRights & RT_BIT(4))); /* System MBZ.*/
4613 Assert(u32AccessRights & RT_BIT(7)); /* Present MB1.*/
4614 Assert(!(u32AccessRights & 0xf00)); /* 11:8 MBZ. */
4615 Assert(!(u32AccessRights & 0xfffe0000)); /* 31:17 MBZ. */
4616 Assert( (u32Limit & 0xfff) == 0xfff
4617 || !(u32AccessRights & RT_BIT(15))); /* Granularity MBZ. */
4618 Assert( !(pCtx->tr.u32Limit & 0xfff00000)
4619 || (u32AccessRights & RT_BIT(15))); /* Granularity MB1. */
4620
4621 rc = VMXWriteVmcs32(VMX_VMCS16_GUEST_TR_SEL, u16Sel);
4622 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_LIMIT, u32Limit);
4623 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, u32AccessRights);
4624 rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_TR_BASE, u64Base);
4625 AssertRCReturn(rc, rc);
4626
4627 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_TR);
4628 Log4Func(("TR base=%#RX64\n", pCtx->tr.u64Base));
4629 }
4630
4631 /*
4632 * Guest GDTR.
4633 */
4634 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_GDTR)
4635 {
4636 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_GDTR);
4637
4638 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, pCtx->gdtr.cbGdt);
4639 rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE, pCtx->gdtr.pGdt);
4640 AssertRCReturn(rc, rc);
4641
4642 /* Validate. */
4643 Assert(!(pCtx->gdtr.cbGdt & 0xffff0000)); /* Bits 31:16 MBZ. */
4644
4645 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_GDTR);
4646 Log4Func(("GDTR base=%#RX64\n", pCtx->gdtr.pGdt));
4647 }
4648
4649 /*
4650 * Guest LDTR.
4651 */
4652 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_LDTR)
4653 {
4654 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_LDTR);
4655
4656 /* The unusable bit is specific to VT-x, if it's a null selector mark it as an unusable segment. */
4657 uint32_t u32Access = 0;
4658 if (!pCtx->ldtr.Attr.u)
4659 u32Access = X86DESCATTR_UNUSABLE;
4660 else
4661 u32Access = pCtx->ldtr.Attr.u;
4662
4663 rc = VMXWriteVmcs32(VMX_VMCS16_GUEST_LDTR_SEL, pCtx->ldtr.Sel);
4664 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_LIMIT, pCtx->ldtr.u32Limit);
4665 rc |= VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, u32Access);
4666 rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_LDTR_BASE, pCtx->ldtr.u64Base);
4667 AssertRCReturn(rc, rc);
4668
4669 /* Validate. */
4670 if (!(u32Access & X86DESCATTR_UNUSABLE))
4671 {
4672 Assert(!(pCtx->ldtr.Sel & RT_BIT(2))); /* TI MBZ. */
4673 Assert(pCtx->ldtr.Attr.n.u4Type == 2); /* Type MB2 (LDT). */
4674 Assert(!pCtx->ldtr.Attr.n.u1DescType); /* System MBZ. */
4675 Assert(pCtx->ldtr.Attr.n.u1Present == 1); /* Present MB1. */
4676 Assert(!pCtx->ldtr.Attr.n.u4LimitHigh); /* 11:8 MBZ. */
4677 Assert(!(pCtx->ldtr.Attr.u & 0xfffe0000)); /* 31:17 MBZ. */
4678 Assert( (pCtx->ldtr.u32Limit & 0xfff) == 0xfff
4679 || !pCtx->ldtr.Attr.n.u1Granularity); /* Granularity MBZ. */
4680 Assert( !(pCtx->ldtr.u32Limit & 0xfff00000)
4681 || pCtx->ldtr.Attr.n.u1Granularity); /* Granularity MB1. */
4682 }
4683
4684 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_LDTR);
4685 Log4Func(("LDTR base=%#RX64\n", pCtx->ldtr.u64Base));
4686 }
4687
4688 /*
4689 * Guest IDTR.
4690 */
4691 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_IDTR)
4692 {
4693 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_IDTR);
4694
4695 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, pCtx->idtr.cbIdt);
4696 rc |= VMXWriteVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE, pCtx->idtr.pIdt);
4697 AssertRCReturn(rc, rc);
4698
4699 /* Validate. */
4700 Assert(!(pCtx->idtr.cbIdt & 0xffff0000)); /* Bits 31:16 MBZ. */
4701
4702 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_IDTR);
4703 Log4Func(("IDTR base=%#RX64\n", pCtx->idtr.pIdt));
4704 }
4705
4706 return VINF_SUCCESS;
4707}
4708
4709
4710/**
4711 * Exports certain guest MSRs into the VM-entry MSR-load and VM-exit MSR-store
4712 * areas.
4713 *
4714 * These MSRs will automatically be loaded to the host CPU on every successful
4715 * VM-entry and stored from the host CPU on every successful VM-exit. This also
4716 * creates/updates MSR slots for the host MSRs. The actual host MSR values are
4717 * -not- updated here for performance reasons. See hmR0VmxExportHostMsrs().
4718 *
4719 * Also exports the guest sysenter MSRs into the guest-state area in the VMCS.
4720 *
4721 * @returns VBox status code.
4722 * @param pVCpu The cross context virtual CPU structure.
4723 *
4724 * @remarks No-long-jump zone!!!
4725 */
4726static int hmR0VmxExportGuestMsrs(PVMCPU pVCpu)
4727{
4728 AssertPtr(pVCpu);
4729 AssertPtr(pVCpu->hm.s.vmx.pvGuestMsr);
4730
4731 /*
4732 * MSRs that we use the auto-load/store MSR area in the VMCS.
4733 * For 64-bit hosts, we load/restore them lazily, see hmR0VmxLazyLoadGuestMsrs().
4734 */
4735 PVM pVM = pVCpu->CTX_SUFF(pVM);
4736 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4737 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_VMX_GUEST_AUTO_MSRS)
4738 {
4739 if (pVM->hm.s.fAllow64BitGuests)
4740 {
4741#if HC_ARCH_BITS == 32
4742 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SYSCALL_MSRS | CPUMCTX_EXTRN_KERNEL_GS_BASE);
4743
4744 int rc = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_LSTAR, pCtx->msrLSTAR, false, NULL);
4745 rc |= hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K6_STAR, pCtx->msrSTAR, false, NULL);
4746 rc |= hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_SF_MASK, pCtx->msrSFMASK, false, NULL);
4747 rc |= hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_KERNEL_GS_BASE, pCtx->msrKERNELGSBASE, false, NULL);
4748 AssertRCReturn(rc, rc);
4749# ifdef LOG_ENABLED
4750 PCVMXAUTOMSR pMsr = (PCVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
4751 for (uint32_t i = 0; i < pVCpu->hm.s.vmx.cMsrs; i++, pMsr++)
4752 Log4Func(("MSR[%RU32]: u32Msr=%#RX32 u64Value=%#RX64\n", i, pMsr->u32Msr, pMsr->u64Value));
4753# endif
4754#endif
4755 }
4756 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_VMX_GUEST_AUTO_MSRS);
4757 }
4758
4759 /*
4760 * Guest Sysenter MSRs.
4761 * These flags are only set when MSR-bitmaps are not supported by the CPU and we cause
4762 * VM-exits on WRMSRs for these MSRs.
4763 */
4764 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SYSENTER_MSR_MASK)
4765 {
4766 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SYSENTER_MSRS);
4767
4768 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SYSENTER_CS_MSR)
4769 {
4770 int rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, pCtx->SysEnter.cs);
4771 AssertRCReturn(rc, rc);
4772 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_SYSENTER_CS_MSR);
4773 }
4774
4775 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SYSENTER_EIP_MSR)
4776 {
4777 int rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_EIP, pCtx->SysEnter.eip);
4778 AssertRCReturn(rc, rc);
4779 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_SYSENTER_EIP_MSR);
4780 }
4781
4782 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_SYSENTER_ESP_MSR)
4783 {
4784 int rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_ESP, pCtx->SysEnter.esp);
4785 AssertRCReturn(rc, rc);
4786 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_SYSENTER_ESP_MSR);
4787 }
4788 }
4789
4790 if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_EFER_MSR)
4791 {
4792 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
4793
4794 if (hmR0VmxShouldSwapEferMsr(pVCpu))
4795 {
4796 /*
4797 * If the CPU supports VMCS controls for swapping EFER, use it. Otherwise, we have no option
4798 * but to use the auto-load store MSR area in the VMCS for swapping EFER. See @bugref{7368}.
4799 */
4800 if (pVM->hm.s.vmx.fSupportsVmcsEfer)
4801 {
4802 int rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_EFER_FULL, pCtx->msrEFER);
4803 AssertRCReturn(rc,rc);
4804 Log4Func(("EFER=%#RX64\n", pCtx->msrEFER));
4805 }
4806 else
4807 {
4808 int rc = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K6_EFER, pCtx->msrEFER, false /* fUpdateHostMsr */,
4809 NULL /* pfAddedAndUpdated */);
4810 AssertRCReturn(rc, rc);
4811
4812 /* We need to intercept reads too, see @bugref{7386#c16}. */
4813 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
4814 hmR0VmxSetMsrPermission(pVCpu, MSR_K6_EFER, VMXMSREXIT_INTERCEPT_READ, VMXMSREXIT_INTERCEPT_WRITE);
4815 Log4Func(("MSR[--]: u32Msr=%#RX32 u64Value=%#RX64 cMsrs=%u\n", MSR_K6_EFER, pCtx->msrEFER,
4816 pVCpu->hm.s.vmx.cMsrs));
4817 }
4818 }
4819 else if (!pVM->hm.s.vmx.fSupportsVmcsEfer)
4820 hmR0VmxRemoveAutoLoadStoreMsr(pVCpu, MSR_K6_EFER);
4821 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_EFER_MSR);
4822 }
4823
4824 return VINF_SUCCESS;
4825}
4826
4827
4828#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
4829/**
4830 * Check if guest state allows safe use of 32-bit switcher again.
4831 *
4832 * Segment bases and protected mode structures must be 32-bit addressable
4833 * because the 32-bit switcher will ignore high dword when writing these VMCS
4834 * fields. See @bugref{8432} for details.
4835 *
4836 * @returns true if safe, false if must continue to use the 64-bit switcher.
4837 * @param pCtx Pointer to the guest-CPU context.
4838 *
4839 * @remarks No-long-jump zone!!!
4840 */
4841static bool hmR0VmxIs32BitSwitcherSafe(PCCPUMCTX pCtx)
4842{
4843 if (pCtx->gdtr.pGdt & UINT64_C(0xffffffff00000000)) return false;
4844 if (pCtx->idtr.pIdt & UINT64_C(0xffffffff00000000)) return false;
4845 if (pCtx->ldtr.u64Base & UINT64_C(0xffffffff00000000)) return false;
4846 if (pCtx->tr.u64Base & UINT64_C(0xffffffff00000000)) return false;
4847 if (pCtx->es.u64Base & UINT64_C(0xffffffff00000000)) return false;
4848 if (pCtx->cs.u64Base & UINT64_C(0xffffffff00000000)) return false;
4849 if (pCtx->ss.u64Base & UINT64_C(0xffffffff00000000)) return false;
4850 if (pCtx->ds.u64Base & UINT64_C(0xffffffff00000000)) return false;
4851 if (pCtx->fs.u64Base & UINT64_C(0xffffffff00000000)) return false;
4852 if (pCtx->gs.u64Base & UINT64_C(0xffffffff00000000)) return false;
4853
4854 /* All good, bases are 32-bit. */
4855 return true;
4856}
4857#endif
4858
4859
4860/**
4861 * Selects up the appropriate function to run guest code.
4862 *
4863 * @returns VBox status code.
4864 * @param pVCpu The cross context virtual CPU structure.
4865 *
4866 * @remarks No-long-jump zone!!!
4867 */
4868static int hmR0VmxSelectVMRunHandler(PVMCPU pVCpu)
4869{
4870 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4871 if (CPUMIsGuestInLongModeEx(pCtx))
4872 {
4873#ifndef VBOX_ENABLE_64_BITS_GUESTS
4874 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
4875#endif
4876 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
4877#if HC_ARCH_BITS == 32
4878 /* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
4879 if (pVCpu->hm.s.vmx.pfnStartVM != VMXR0SwitcherStartVM64)
4880 {
4881#ifdef VBOX_STRICT
4882 if (pVCpu->hm.s.vmx.pfnStartVM != NULL) /* Very first entry would have saved host-state already, ignore it. */
4883 {
4884 /* Currently, all mode changes sends us back to ring-3, so these should be set. See @bugref{6944}. */
4885 uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
4886 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4887 AssertMsg(fCtxChanged & ( HM_CHANGED_VMX_EXIT_CTLS
4888 | HM_CHANGED_VMX_ENTRY_CTLS
4889 | HM_CHANGED_GUEST_EFER_MSR), ("fCtxChanged=%#RX64\n", fCtxChanged));
4890 }
4891#endif
4892 pVCpu->hm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
4893
4894 /* Mark that we've switched to 64-bit handler, we can't safely switch back to 32-bit for
4895 the rest of the VM run (until VM reset). See @bugref{8432#c7}. */
4896 pVCpu->hm.s.vmx.fSwitchedTo64on32 = true;
4897 Log4Func(("Selected 64-bit switcher\n"));
4898 }
4899#else
4900 /* 64-bit host. */
4901 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM64;
4902#endif
4903 }
4904 else
4905 {
4906 /* Guest is not in long mode, use the 32-bit handler. */
4907#if HC_ARCH_BITS == 32
4908 if ( pVCpu->hm.s.vmx.pfnStartVM != VMXR0StartVM32
4909 && !pVCpu->hm.s.vmx.fSwitchedTo64on32 /* If set, guest mode change does not imply switcher change. */
4910 && pVCpu->hm.s.vmx.pfnStartVM != NULL) /* Very first entry would have saved host-state already, ignore it. */
4911 {
4912# ifdef VBOX_STRICT
4913 /* Currently, all mode changes sends us back to ring-3, so these should be set. See @bugref{6944}. */
4914 uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
4915 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
4916 AssertMsg(fCtxChanged & ( HM_CHANGED_VMX_EXIT_CTLS
4917 | HM_CHANGED_VMX_ENTRY_CTLS
4918 | HM_CHANGED_GUEST_EFER_MSR), ("fCtxChanged=%#RX64\n", fCtxChanged));
4919# endif
4920 }
4921# ifdef VBOX_ENABLE_64_BITS_GUESTS
4922 /*
4923 * Keep using the 64-bit switcher even though we're in 32-bit because of bad Intel
4924 * design, see @bugref{8432#c7}. If real-on-v86 mode is active, clear the 64-bit
4925 * switcher flag because now we know the guest is in a sane state where it's safe
4926 * to use the 32-bit switcher. Otherwise check the guest state if it's safe to use
4927 * the much faster 32-bit switcher again.
4928 */
4929 if (!pVCpu->hm.s.vmx.fSwitchedTo64on32)
4930 {
4931 if (pVCpu->hm.s.vmx.pfnStartVM != VMXR0StartVM32)
4932 Log4Func(("Selected 32-bit switcher\n"));
4933 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4934 }
4935 else
4936 {
4937 Assert(pVCpu->hm.s.vmx.pfnStartVM == VMXR0SwitcherStartVM64);
4938 if ( pVCpu->hm.s.vmx.RealMode.fRealOnV86Active
4939 || hmR0VmxIs32BitSwitcherSafe(pCtx))
4940 {
4941 pVCpu->hm.s.vmx.fSwitchedTo64on32 = false;
4942 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4943 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_EFER_MSR
4944 | HM_CHANGED_VMX_ENTRY_CTLS
4945 | HM_CHANGED_VMX_EXIT_CTLS
4946 | HM_CHANGED_HOST_CONTEXT);
4947 Log4Func(("Selected 32-bit switcher (safe)\n"));
4948 }
4949 }
4950# else
4951 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4952# endif
4953#else
4954 pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4955#endif
4956 }
4957 Assert(pVCpu->hm.s.vmx.pfnStartVM);
4958 return VINF_SUCCESS;
4959}
4960
4961
4962/**
4963 * Wrapper for running the guest code in VT-x.
4964 *
4965 * @returns VBox status code, no informational status codes.
4966 * @param pVCpu The cross context virtual CPU structure.
4967 *
4968 * @remarks No-long-jump zone!!!
4969 */
4970DECLINLINE(int) hmR0VmxRunGuest(PVMCPU pVCpu)
4971{
4972 /* Mark that HM is the keeper of all guest-CPU registers now that we're going to execute guest code. */
4973 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4974 pCtx->fExtrn |= HMVMX_CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_KEEPER_HM;
4975
4976 /*
4977 * 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses
4978 * floating-point operations using SSE instructions. Some XMM registers (XMM6-XMM15) are
4979 * callee-saved and thus the need for this XMM wrapper.
4980 *
4981 * See MSDN "Configuring Programs for 64-bit/x64 Software Conventions / Register Usage".
4982 */
4983 bool const fResumeVM = RT_BOOL(pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_LAUNCHED);
4984 /** @todo Add stats for resume vs launch. */
4985 PVM pVM = pVCpu->CTX_SUFF(pVM);
4986#ifdef VBOX_WITH_KERNEL_USING_XMM
4987 int rc = hmR0VMXStartVMWrapXMM(fResumeVM, pCtx, &pVCpu->hm.s.vmx.VMCSCache, pVM, pVCpu, pVCpu->hm.s.vmx.pfnStartVM);
4988#else
4989 int rc = pVCpu->hm.s.vmx.pfnStartVM(fResumeVM, pCtx, &pVCpu->hm.s.vmx.VMCSCache, pVM, pVCpu);
4990#endif
4991 AssertMsg(rc <= VINF_SUCCESS, ("%Rrc\n", rc));
4992 return rc;
4993}
4994
4995
4996/**
4997 * Reports world-switch error and dumps some useful debug info.
4998 *
4999 * @param pVCpu The cross context virtual CPU structure.
5000 * @param rcVMRun The return code from VMLAUNCH/VMRESUME.
5001 * @param pVmxTransient Pointer to the VMX transient structure (only
5002 * exitReason updated).
5003 */
5004static void hmR0VmxReportWorldSwitchError(PVMCPU pVCpu, int rcVMRun, PVMXTRANSIENT pVmxTransient)
5005{
5006 Assert(pVCpu);
5007 Assert(pVmxTransient);
5008 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
5009
5010 Log4Func(("VM-entry failure: %Rrc\n", rcVMRun));
5011 switch (rcVMRun)
5012 {
5013 case VERR_VMX_INVALID_VMXON_PTR:
5014 AssertFailed();
5015 break;
5016 case VINF_SUCCESS: /* VMLAUNCH/VMRESUME succeeded but VM-entry failed... yeah, true story. */
5017 case VERR_VMX_UNABLE_TO_START_VM: /* VMLAUNCH/VMRESUME itself failed. */
5018 {
5019 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_REASON, &pVCpu->hm.s.vmx.LastError.u32ExitReason);
5020 rc |= VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError);
5021 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
5022 AssertRC(rc);
5023
5024 pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hm.s.idEnteredCpu;
5025 /* LastError.idCurrentCpu was already updated in hmR0VmxPreRunGuestCommitted().
5026 Cannot do it here as we may have been long preempted. */
5027
5028#ifdef VBOX_STRICT
5029 Log4(("uExitReason %#RX32 (VmxTransient %#RX16)\n", pVCpu->hm.s.vmx.LastError.u32ExitReason,
5030 pVmxTransient->uExitReason));
5031 Log4(("Exit Qualification %#RX64\n", pVmxTransient->uExitQual));
5032 Log4(("InstrError %#RX32\n", pVCpu->hm.s.vmx.LastError.u32InstrError));
5033 if (pVCpu->hm.s.vmx.LastError.u32InstrError <= HMVMX_INSTR_ERROR_MAX)
5034 Log4(("InstrError Desc. \"%s\"\n", g_apszVmxInstrErrors[pVCpu->hm.s.vmx.LastError.u32InstrError]));
5035 else
5036 Log4(("InstrError Desc. Range exceeded %u\n", HMVMX_INSTR_ERROR_MAX));
5037 Log4(("Entered host CPU %u\n", pVCpu->hm.s.vmx.LastError.idEnteredCpu));
5038 Log4(("Current host CPU %u\n", pVCpu->hm.s.vmx.LastError.idCurrentCpu));
5039
5040 /* VMX control bits. */
5041 uint32_t u32Val;
5042 uint64_t u64Val;
5043 RTHCUINTREG uHCReg;
5044 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, &u32Val); AssertRC(rc);
5045 Log4(("VMX_VMCS32_CTRL_PIN_EXEC %#RX32\n", u32Val));
5046 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, &u32Val); AssertRC(rc);
5047 Log4(("VMX_VMCS32_CTRL_PROC_EXEC %#RX32\n", u32Val));
5048 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
5049 {
5050 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val); AssertRC(rc);
5051 Log4(("VMX_VMCS32_CTRL_PROC_EXEC2 %#RX32\n", u32Val));
5052 }
5053 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val); AssertRC(rc);
5054 Log4(("VMX_VMCS32_CTRL_ENTRY %#RX32\n", u32Val));
5055 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT, &u32Val); AssertRC(rc);
5056 Log4(("VMX_VMCS32_CTRL_EXIT %#RX32\n", u32Val));
5057 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, &u32Val); AssertRC(rc);
5058 Log4(("VMX_VMCS32_CTRL_CR3_TARGET_COUNT %#RX32\n", u32Val));
5059 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &u32Val); AssertRC(rc);
5060 Log4(("VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO %#RX32\n", u32Val));
5061 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, &u32Val); AssertRC(rc);
5062 Log4(("VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE %#RX32\n", u32Val));
5063 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, &u32Val); AssertRC(rc);
5064 Log4(("VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH %u\n", u32Val));
5065 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, &u32Val); AssertRC(rc);
5066 Log4(("VMX_VMCS32_CTRL_TPR_THRESHOLD %u\n", u32Val));
5067 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, &u32Val); AssertRC(rc);
5068 Log4(("VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT %u (guest MSRs)\n", u32Val));
5069 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, &u32Val); AssertRC(rc);
5070 Log4(("VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT %u (host MSRs)\n", u32Val));
5071 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, &u32Val); AssertRC(rc);
5072 Log4(("VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT %u (guest MSRs)\n", u32Val));
5073 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, &u32Val); AssertRC(rc);
5074 Log4(("VMX_VMCS32_CTRL_EXCEPTION_BITMAP %#RX32\n", u32Val));
5075 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, &u32Val); AssertRC(rc);
5076 Log4(("VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK %#RX32\n", u32Val));
5077 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, &u32Val); AssertRC(rc);
5078 Log4(("VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH %#RX32\n", u32Val));
5079 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_MASK, &uHCReg); AssertRC(rc);
5080 Log4(("VMX_VMCS_CTRL_CR0_MASK %#RHr\n", uHCReg));
5081 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_READ_SHADOW, &uHCReg); AssertRC(rc);
5082 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
5083 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_MASK, &uHCReg); AssertRC(rc);
5084 Log4(("VMX_VMCS_CTRL_CR4_MASK %#RHr\n", uHCReg));
5085 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uHCReg); AssertRC(rc);
5086 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
5087 if (pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
5088 {
5089 rc = VMXReadVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, &u64Val); AssertRC(rc);
5090 Log4(("VMX_VMCS64_CTRL_EPTP_FULL %#RX64\n", u64Val));
5091 }
5092
5093 /* Guest bits. */
5094 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &u64Val); AssertRC(rc);
5095 Log4(("Old Guest Rip %#RX64 New %#RX64\n", pVCpu->cpum.GstCtx.rip, u64Val));
5096 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &u64Val); AssertRC(rc);
5097 Log4(("Old Guest Rsp %#RX64 New %#RX64\n", pVCpu->cpum.GstCtx.rsp, u64Val));
5098 rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Val); AssertRC(rc);
5099 Log4(("Old Guest Rflags %#RX32 New %#RX32\n", pVCpu->cpum.GstCtx.eflags.u32, u32Val));
5100 if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fVpid)
5101 {
5102 rc = VMXReadVmcs32(VMX_VMCS16_VPID, &u32Val); AssertRC(rc);
5103 Log4(("VMX_VMCS16_VPID %u\n", u32Val));
5104 }
5105
5106 /* Host bits. */
5107 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR0, &uHCReg); AssertRC(rc);
5108 Log4(("Host CR0 %#RHr\n", uHCReg));
5109 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR3, &uHCReg); AssertRC(rc);
5110 Log4(("Host CR3 %#RHr\n", uHCReg));
5111 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR4, &uHCReg); AssertRC(rc);
5112 Log4(("Host CR4 %#RHr\n", uHCReg));
5113
5114 RTGDTR HostGdtr;
5115 PCX86DESCHC pDesc;
5116 ASMGetGDTR(&HostGdtr);
5117 rc = VMXReadVmcs32(VMX_VMCS16_HOST_CS_SEL, &u32Val); AssertRC(rc);
5118 Log4(("Host CS %#08x\n", u32Val));
5119 if (u32Val < HostGdtr.cbGdt)
5120 {
5121 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5122 hmR0DumpDescriptor(pDesc, u32Val, "CS: ");
5123 }
5124
5125 rc = VMXReadVmcs32(VMX_VMCS16_HOST_DS_SEL, &u32Val); AssertRC(rc);
5126 Log4(("Host DS %#08x\n", u32Val));
5127 if (u32Val < HostGdtr.cbGdt)
5128 {
5129 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5130 hmR0DumpDescriptor(pDesc, u32Val, "DS: ");
5131 }
5132
5133 rc = VMXReadVmcs32(VMX_VMCS16_HOST_ES_SEL, &u32Val); AssertRC(rc);
5134 Log4(("Host ES %#08x\n", u32Val));
5135 if (u32Val < HostGdtr.cbGdt)
5136 {
5137 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5138 hmR0DumpDescriptor(pDesc, u32Val, "ES: ");
5139 }
5140
5141 rc = VMXReadVmcs32(VMX_VMCS16_HOST_FS_SEL, &u32Val); AssertRC(rc);
5142 Log4(("Host FS %#08x\n", u32Val));
5143 if (u32Val < HostGdtr.cbGdt)
5144 {
5145 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5146 hmR0DumpDescriptor(pDesc, u32Val, "FS: ");
5147 }
5148
5149 rc = VMXReadVmcs32(VMX_VMCS16_HOST_GS_SEL, &u32Val); AssertRC(rc);
5150 Log4(("Host GS %#08x\n", u32Val));
5151 if (u32Val < HostGdtr.cbGdt)
5152 {
5153 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5154 hmR0DumpDescriptor(pDesc, u32Val, "GS: ");
5155 }
5156
5157 rc = VMXReadVmcs32(VMX_VMCS16_HOST_SS_SEL, &u32Val); AssertRC(rc);
5158 Log4(("Host SS %#08x\n", u32Val));
5159 if (u32Val < HostGdtr.cbGdt)
5160 {
5161 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5162 hmR0DumpDescriptor(pDesc, u32Val, "SS: ");
5163 }
5164
5165 rc = VMXReadVmcs32(VMX_VMCS16_HOST_TR_SEL, &u32Val); AssertRC(rc);
5166 Log4(("Host TR %#08x\n", u32Val));
5167 if (u32Val < HostGdtr.cbGdt)
5168 {
5169 pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5170 hmR0DumpDescriptor(pDesc, u32Val, "TR: ");
5171 }
5172
5173 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_TR_BASE, &uHCReg); AssertRC(rc);
5174 Log4(("Host TR Base %#RHv\n", uHCReg));
5175 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, &uHCReg); AssertRC(rc);
5176 Log4(("Host GDTR Base %#RHv\n", uHCReg));
5177 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_IDTR_BASE, &uHCReg); AssertRC(rc);
5178 Log4(("Host IDTR Base %#RHv\n", uHCReg));
5179 rc = VMXReadVmcs32(VMX_VMCS32_HOST_SYSENTER_CS, &u32Val); AssertRC(rc);
5180 Log4(("Host SYSENTER CS %#08x\n", u32Val));
5181 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_SYSENTER_EIP, &uHCReg); AssertRC(rc);
5182 Log4(("Host SYSENTER EIP %#RHv\n", uHCReg));
5183 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_SYSENTER_ESP, &uHCReg); AssertRC(rc);
5184 Log4(("Host SYSENTER ESP %#RHv\n", uHCReg));
5185 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_RSP, &uHCReg); AssertRC(rc);
5186 Log4(("Host RSP %#RHv\n", uHCReg));
5187 rc = VMXReadVmcsHstN(VMX_VMCS_HOST_RIP, &uHCReg); AssertRC(rc);
5188 Log4(("Host RIP %#RHv\n", uHCReg));
5189# if HC_ARCH_BITS == 64
5190 Log4(("MSR_K6_EFER = %#RX64\n", ASMRdMsr(MSR_K6_EFER)));
5191 Log4(("MSR_K8_CSTAR = %#RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
5192 Log4(("MSR_K8_LSTAR = %#RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
5193 Log4(("MSR_K6_STAR = %#RX64\n", ASMRdMsr(MSR_K6_STAR)));
5194 Log4(("MSR_K8_SF_MASK = %#RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
5195 Log4(("MSR_K8_KERNEL_GS_BASE = %#RX64\n", ASMRdMsr(MSR_K8_KERNEL_GS_BASE)));
5196# endif
5197#endif /* VBOX_STRICT */
5198 break;
5199 }
5200
5201 default:
5202 /* Impossible */
5203 AssertMsgFailed(("hmR0VmxReportWorldSwitchError %Rrc (%#x)\n", rcVMRun, rcVMRun));
5204 break;
5205 }
5206}
5207
5208
5209#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
5210#ifndef VMX_USE_CACHED_VMCS_ACCESSES
5211# error "VMX_USE_CACHED_VMCS_ACCESSES not defined when it should be!"
5212#endif
5213#ifdef VBOX_STRICT
5214static bool hmR0VmxIsValidWriteField(uint32_t idxField)
5215{
5216 switch (idxField)
5217 {
5218 case VMX_VMCS_GUEST_RIP:
5219 case VMX_VMCS_GUEST_RSP:
5220 case VMX_VMCS_GUEST_SYSENTER_EIP:
5221 case VMX_VMCS_GUEST_SYSENTER_ESP:
5222 case VMX_VMCS_GUEST_GDTR_BASE:
5223 case VMX_VMCS_GUEST_IDTR_BASE:
5224 case VMX_VMCS_GUEST_CS_BASE:
5225 case VMX_VMCS_GUEST_DS_BASE:
5226 case VMX_VMCS_GUEST_ES_BASE:
5227 case VMX_VMCS_GUEST_FS_BASE:
5228 case VMX_VMCS_GUEST_GS_BASE:
5229 case VMX_VMCS_GUEST_SS_BASE:
5230 case VMX_VMCS_GUEST_LDTR_BASE:
5231 case VMX_VMCS_GUEST_TR_BASE:
5232 case VMX_VMCS_GUEST_CR3:
5233 return true;
5234 }
5235 return false;
5236}
5237
5238static bool hmR0VmxIsValidReadField(uint32_t idxField)
5239{
5240 switch (idxField)
5241 {
5242 /* Read-only fields. */
5243 case VMX_VMCS_RO_EXIT_QUALIFICATION:
5244 return true;
5245 }
5246 /* Remaining readable fields should also be writable. */
5247 return hmR0VmxIsValidWriteField(idxField);
5248}
5249#endif /* VBOX_STRICT */
5250
5251
5252/**
5253 * Executes the specified handler in 64-bit mode.
5254 *
5255 * @returns VBox status code (no informational status codes).
5256 * @param pVCpu The cross context virtual CPU structure.
5257 * @param enmOp The operation to perform.
5258 * @param cParams Number of parameters.
5259 * @param paParam Array of 32-bit parameters.
5260 */
5261VMMR0DECL(int) VMXR0Execute64BitsHandler(PVMCPU pVCpu, HM64ON32OP enmOp, uint32_t cParams, uint32_t *paParam)
5262{
5263 PVM pVM = pVCpu->CTX_SUFF(pVM);
5264 AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
5265 Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
5266 Assert(pVCpu->hm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hm.s.vmx.VMCSCache.Write.aField));
5267 Assert(pVCpu->hm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hm.s.vmx.VMCSCache.Read.aField));
5268
5269#ifdef VBOX_STRICT
5270 for (uint32_t i = 0; i < pVCpu->hm.s.vmx.VMCSCache.Write.cValidEntries; i++)
5271 Assert(hmR0VmxIsValidWriteField(pVCpu->hm.s.vmx.VMCSCache.Write.aField[i]));
5272
5273 for (uint32_t i = 0; i <pVCpu->hm.s.vmx.VMCSCache.Read.cValidEntries; i++)
5274 Assert(hmR0VmxIsValidReadField(pVCpu->hm.s.vmx.VMCSCache.Read.aField[i]));
5275#endif
5276
5277 /* Disable interrupts. */
5278 RTCCUINTREG fOldEFlags = ASMIntDisableFlags();
5279
5280#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
5281 RTCPUID idHostCpu = RTMpCpuId();
5282 CPUMR0SetLApic(pVCpu, idHostCpu);
5283#endif
5284
5285 PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
5286 RTHCPHYS HCPhysCpuPage = pCpu->HCPhysMemObj;
5287
5288 /* Clear VMCS. Marking it inactive, clearing implementation-specific data and writing VMCS data back to memory. */
5289 VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
5290 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
5291
5292 /* Leave VMX Root Mode. */
5293 VMXDisable();
5294
5295 SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
5296
5297 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
5298 CPUMSetHyperEIP(pVCpu, enmOp);
5299 for (int i = (int)cParams - 1; i >= 0; i--)
5300 CPUMPushHyper(pVCpu, paParam[i]);
5301
5302 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
5303
5304 /* Call the switcher. */
5305 int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_UOFFSETOF_DYN(VM, aCpus[pVCpu->idCpu].cpum) - RT_UOFFSETOF(VM, cpum));
5306 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
5307
5308 /** @todo replace with hmR0VmxEnterRootMode() and hmR0VmxLeaveRootMode(). */
5309 /* Make sure the VMX instructions don't cause #UD faults. */
5310 SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
5311
5312 /* Re-enter VMX Root Mode */
5313 int rc2 = VMXEnable(HCPhysCpuPage);
5314 if (RT_FAILURE(rc2))
5315 {
5316 SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
5317 ASMSetFlags(fOldEFlags);
5318 pVM->hm.s.vmx.HCPhysVmxEnableError = HCPhysCpuPage;
5319 return rc2;
5320 }
5321
5322 rc2 = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
5323 AssertRC(rc2);
5324 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_ACTIVE;
5325 Assert(!(ASMGetFlags() & X86_EFL_IF));
5326 ASMSetFlags(fOldEFlags);
5327 return rc;
5328}
5329
5330
5331/**
5332 * Prepares for and executes VMLAUNCH (64-bit guests) for 32-bit hosts
5333 * supporting 64-bit guests.
5334 *
5335 * @returns VBox status code.
5336 * @param fResume Whether to VMLAUNCH or VMRESUME.
5337 * @param pCtx Pointer to the guest-CPU context.
5338 * @param pCache Pointer to the VMCS cache.
5339 * @param pVM The cross context VM structure.
5340 * @param pVCpu The cross context virtual CPU structure.
5341 */
5342DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
5343{
5344 NOREF(fResume);
5345
5346 PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
5347 RTHCPHYS HCPhysCpuPage = pCpu->HCPhysMemObj;
5348
5349#ifdef VBOX_WITH_CRASHDUMP_MAGIC
5350 pCache->uPos = 1;
5351 pCache->interPD = PGMGetInterPaeCR3(pVM);
5352 pCache->pSwitcher = (uint64_t)pVM->hm.s.pfnHost32ToGuest64R0;
5353#endif
5354
5355#if defined(DEBUG) && defined(VMX_USE_CACHED_VMCS_ACCESSES)
5356 pCache->TestIn.HCPhysCpuPage = 0;
5357 pCache->TestIn.HCPhysVmcs = 0;
5358 pCache->TestIn.pCache = 0;
5359 pCache->TestOut.HCPhysVmcs = 0;
5360 pCache->TestOut.pCache = 0;
5361 pCache->TestOut.pCtx = 0;
5362 pCache->TestOut.eflags = 0;
5363#else
5364 NOREF(pCache);
5365#endif
5366
5367 uint32_t aParam[10];
5368 aParam[0] = RT_LO_U32(HCPhysCpuPage); /* Param 1: VMXON physical address - Lo. */
5369 aParam[1] = RT_HI_U32(HCPhysCpuPage); /* Param 1: VMXON physical address - Hi. */
5370 aParam[2] = RT_LO_U32(pVCpu->hm.s.vmx.HCPhysVmcs); /* Param 2: VMCS physical address - Lo. */
5371 aParam[3] = RT_HI_U32(pVCpu->hm.s.vmx.HCPhysVmcs); /* Param 2: VMCS physical address - Hi. */
5372 aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache);
5373 aParam[5] = 0;
5374 aParam[6] = VM_RC_ADDR(pVM, pVM);
5375 aParam[7] = 0;
5376 aParam[8] = VM_RC_ADDR(pVM, pVCpu);
5377 aParam[9] = 0;
5378
5379#ifdef VBOX_WITH_CRASHDUMP_MAGIC
5380 pCtx->dr[4] = pVM->hm.s.vmx.pScratchPhys + 16 + 8;
5381 *(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) = 1;
5382#endif
5383 int rc = VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_VMXRCStartVM64, RT_ELEMENTS(aParam), &aParam[0]);
5384
5385#ifdef VBOX_WITH_CRASHDUMP_MAGIC
5386 Assert(*(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) == 5);
5387 Assert(pCtx->dr[4] == 10);
5388 *(uint32_t *)(pVM->hm.s.vmx.pScratch + 16 + 8) = 0xff;
5389#endif
5390
5391#if defined(DEBUG) && defined(VMX_USE_CACHED_VMCS_ACCESSES)
5392 AssertMsg(pCache->TestIn.HCPhysCpuPage == HCPhysCpuPage, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysCpuPage, HCPhysCpuPage));
5393 AssertMsg(pCache->TestIn.HCPhysVmcs == pVCpu->hm.s.vmx.HCPhysVmcs, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVmcs,
5394 pVCpu->hm.s.vmx.HCPhysVmcs));
5395 AssertMsg(pCache->TestIn.HCPhysVmcs == pCache->TestOut.HCPhysVmcs, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVmcs,
5396 pCache->TestOut.HCPhysVmcs));
5397 AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache,
5398 pCache->TestOut.pCache));
5399 AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache),
5400 ("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache)));
5401 AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx,
5402 pCache->TestOut.pCtx));
5403 Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
5404#endif
5405 NOREF(pCtx);
5406 return rc;
5407}
5408
5409
5410/**
5411 * Initialize the VMCS-Read cache.
5412 *
5413 * The VMCS cache is used for 32-bit hosts running 64-bit guests (except 32-bit
5414 * Darwin which runs with 64-bit paging in 32-bit mode) for 64-bit fields that
5415 * cannot be accessed in 32-bit mode. Some 64-bit fields -can- be accessed
5416 * (those that have a 32-bit FULL & HIGH part).
5417 *
5418 * @returns VBox status code.
5419 * @param pVCpu The cross context virtual CPU structure.
5420 */
5421static int hmR0VmxInitVmcsReadCache(PVMCPU pVCpu)
5422{
5423#define VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, idxField) \
5424 do { \
5425 Assert(pCache->Read.aField[idxField##_CACHE_IDX] == 0); \
5426 pCache->Read.aField[idxField##_CACHE_IDX] = idxField; \
5427 pCache->Read.aFieldVal[idxField##_CACHE_IDX] = 0; \
5428 ++cReadFields; \
5429 } while (0)
5430
5431 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
5432 uint32_t cReadFields = 0;
5433
5434 /*
5435 * Don't remove the #if 0'd fields in this code. They're listed here for consistency
5436 * and serve to indicate exceptions to the rules.
5437 */
5438
5439 /* Guest-natural selector base fields. */
5440#if 0
5441 /* These are 32-bit in practice. See Intel spec. 2.5 "Control Registers". */
5442 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR0);
5443 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR4);
5444#endif
5445 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_ES_BASE);
5446 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CS_BASE);
5447 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SS_BASE);
5448 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_DS_BASE);
5449 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_FS_BASE);
5450 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_GS_BASE);
5451 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_LDTR_BASE);
5452 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_TR_BASE);
5453 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_GDTR_BASE);
5454 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_IDTR_BASE);
5455 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_RSP);
5456 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_RIP);
5457#if 0
5458 /* Unused natural width guest-state fields. */
5459 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS);
5460 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR3); /* Handled in Nested Paging case */
5461#endif
5462 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SYSENTER_ESP);
5463 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SYSENTER_EIP);
5464
5465 /* 64-bit guest-state fields; unused as we use two 32-bit VMREADs for
5466 these 64-bit fields (using "FULL" and "HIGH" fields). */
5467#if 0
5468 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL);
5469 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_DEBUGCTL_FULL);
5470 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PAT_FULL);
5471 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_EFER_FULL);
5472 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL);
5473 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE0_FULL);
5474 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE1_FULL);
5475 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE2_FULL);
5476 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE3_FULL);
5477#endif
5478
5479 /* Natural width guest-state fields. */
5480 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
5481 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_RO_GUEST_LINEAR_ADDR);
5482
5483 if (pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
5484 {
5485 VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR3);
5486 AssertMsg(cReadFields == VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX, ("cReadFields=%u expected %u\n", cReadFields,
5487 VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX));
5488 pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
5489 }
5490 else
5491 {
5492 AssertMsg(cReadFields == VMX_VMCS_MAX_CACHE_IDX, ("cReadFields=%u expected %u\n", cReadFields, VMX_VMCS_MAX_CACHE_IDX));
5493 pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
5494 }
5495
5496#undef VMXLOCAL_INIT_READ_CACHE_FIELD
5497 return VINF_SUCCESS;
5498}
5499
5500
5501/**
5502 * Writes a field into the VMCS. This can either directly invoke a VMWRITE or
5503 * queue up the VMWRITE by using the VMCS write cache (on 32-bit hosts, except
5504 * darwin, running 64-bit guests).
5505 *
5506 * @returns VBox status code.
5507 * @param pVCpu The cross context virtual CPU structure.
5508 * @param idxField The VMCS field encoding.
5509 * @param u64Val 16, 32 or 64-bit value.
5510 */
5511VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
5512{
5513 int rc;
5514 switch (idxField)
5515 {
5516 /*
5517 * These fields consists of a "FULL" and a "HIGH" part which can be written to individually.
5518 */
5519 /* 64-bit Control fields. */
5520 case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
5521 case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
5522 case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
5523 case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
5524 case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
5525 case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
5526 case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
5527 case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
5528 case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
5529 case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
5530 case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
5531 case VMX_VMCS64_CTRL_EPTP_FULL:
5532 case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
5533 /* 64-bit Guest-state fields. */
5534 case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
5535 case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
5536 case VMX_VMCS64_GUEST_PAT_FULL:
5537 case VMX_VMCS64_GUEST_EFER_FULL:
5538 case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
5539 case VMX_VMCS64_GUEST_PDPTE0_FULL:
5540 case VMX_VMCS64_GUEST_PDPTE1_FULL:
5541 case VMX_VMCS64_GUEST_PDPTE2_FULL:
5542 case VMX_VMCS64_GUEST_PDPTE3_FULL:
5543 /* 64-bit Host-state fields. */
5544 case VMX_VMCS64_HOST_PAT_FULL:
5545 case VMX_VMCS64_HOST_EFER_FULL:
5546 case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
5547 {
5548 rc = VMXWriteVmcs32(idxField, RT_LO_U32(u64Val));
5549 rc |= VMXWriteVmcs32(idxField + 1, RT_HI_U32(u64Val));
5550 break;
5551 }
5552
5553 /*
5554 * These fields do not have high and low parts. Queue up the VMWRITE by using the VMCS write-cache (for 64-bit
5555 * values). When we switch the host to 64-bit mode for running 64-bit guests, these VMWRITEs get executed then.
5556 */
5557 /* Natural-width Guest-state fields. */
5558 case VMX_VMCS_GUEST_CR3:
5559 case VMX_VMCS_GUEST_ES_BASE:
5560 case VMX_VMCS_GUEST_CS_BASE:
5561 case VMX_VMCS_GUEST_SS_BASE:
5562 case VMX_VMCS_GUEST_DS_BASE:
5563 case VMX_VMCS_GUEST_FS_BASE:
5564 case VMX_VMCS_GUEST_GS_BASE:
5565 case VMX_VMCS_GUEST_LDTR_BASE:
5566 case VMX_VMCS_GUEST_TR_BASE:
5567 case VMX_VMCS_GUEST_GDTR_BASE:
5568 case VMX_VMCS_GUEST_IDTR_BASE:
5569 case VMX_VMCS_GUEST_RSP:
5570 case VMX_VMCS_GUEST_RIP:
5571 case VMX_VMCS_GUEST_SYSENTER_ESP:
5572 case VMX_VMCS_GUEST_SYSENTER_EIP:
5573 {
5574 if (!(RT_HI_U32(u64Val)))
5575 {
5576 /* If this field is 64-bit, VT-x will zero out the top bits. */
5577 rc = VMXWriteVmcs32(idxField, RT_LO_U32(u64Val));
5578 }
5579 else
5580 {
5581 /* Assert that only the 32->64 switcher case should ever come here. */
5582 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests);
5583 rc = VMXWriteCachedVmcsEx(pVCpu, idxField, u64Val);
5584 }
5585 break;
5586 }
5587
5588 default:
5589 {
5590 AssertMsgFailed(("VMXWriteVmcs64Ex: Invalid field %#RX32 (pVCpu=%p u64Val=%#RX64)\n", idxField, pVCpu, u64Val));
5591 rc = VERR_INVALID_PARAMETER;
5592 break;
5593 }
5594 }
5595 AssertRCReturn(rc, rc);
5596 return rc;
5597}
5598
5599
5600/**
5601 * Queue up a VMWRITE by using the VMCS write cache.
5602 * This is only used on 32-bit hosts (except darwin) for 64-bit guests.
5603 *
5604 * @param pVCpu The cross context virtual CPU structure.
5605 * @param idxField The VMCS field encoding.
5606 * @param u64Val 16, 32 or 64-bit value.
5607 */
5608VMMR0DECL(int) VMXWriteCachedVmcsEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
5609{
5610 AssertPtr(pVCpu);
5611 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
5612
5613 AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1,
5614 ("entries=%u\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
5615
5616 /* Make sure there are no duplicates. */
5617 for (uint32_t i = 0; i < pCache->Write.cValidEntries; i++)
5618 {
5619 if (pCache->Write.aField[i] == idxField)
5620 {
5621 pCache->Write.aFieldVal[i] = u64Val;
5622 return VINF_SUCCESS;
5623 }
5624 }
5625
5626 pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
5627 pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
5628 pCache->Write.cValidEntries++;
5629 return VINF_SUCCESS;
5630}
5631#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
5632
5633
5634/**
5635 * Sets up the usage of TSC-offsetting and updates the VMCS.
5636 *
5637 * If offsetting is not possible, cause VM-exits on RDTSC(P)s. Also sets up the
5638 * VMX preemption timer.
5639 *
5640 * @returns VBox status code.
5641 * @param pVCpu The cross context virtual CPU structure.
5642 *
5643 * @remarks No-long-jump zone!!!
5644 */
5645static void hmR0VmxUpdateTscOffsettingAndPreemptTimer(PVMCPU pVCpu)
5646{
5647 bool fOffsettedTsc;
5648 bool fParavirtTsc;
5649 PVM pVM = pVCpu->CTX_SUFF(pVM);
5650 uint64_t uTscOffset;
5651 if (pVM->hm.s.vmx.fUsePreemptTimer)
5652 {
5653 uint64_t cTicksToDeadline = TMCpuTickGetDeadlineAndTscOffset(pVM, pVCpu, &uTscOffset, &fOffsettedTsc, &fParavirtTsc);
5654
5655 /* Make sure the returned values have sane upper and lower boundaries. */
5656 uint64_t u64CpuHz = SUPGetCpuHzFromGipBySetIndex(g_pSUPGlobalInfoPage, pVCpu->iHostCpuSet);
5657 cTicksToDeadline = RT_MIN(cTicksToDeadline, u64CpuHz / 64); /* 1/64th of a second */
5658 cTicksToDeadline = RT_MAX(cTicksToDeadline, u64CpuHz / 2048); /* 1/2048th of a second */
5659 cTicksToDeadline >>= pVM->hm.s.vmx.cPreemptTimerShift;
5660
5661 uint32_t cPreemptionTickCount = (uint32_t)RT_MIN(cTicksToDeadline, UINT32_MAX - 16);
5662 int rc = VMXWriteVmcs32(VMX_VMCS32_PREEMPT_TIMER_VALUE, cPreemptionTickCount);
5663 AssertRC(rc);
5664 }
5665 else
5666 fOffsettedTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &uTscOffset, &fParavirtTsc);
5667
5668 if (fParavirtTsc)
5669 {
5670 /* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
5671 information before every VM-entry, hence disable it for performance sake. */
5672#if 0
5673 int rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
5674 AssertRC(rc);
5675#endif
5676 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
5677 }
5678
5679 uint32_t uProcCtls = pVCpu->hm.s.vmx.u32ProcCtls;
5680 if ( fOffsettedTsc
5681 && RT_LIKELY(!pVCpu->hm.s.fDebugWantRdTscExit))
5682 {
5683 if (pVCpu->hm.s.vmx.u64TscOffset != uTscOffset)
5684 {
5685 int rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, uTscOffset);
5686 AssertRC(rc);
5687 pVCpu->hm.s.vmx.u64TscOffset = uTscOffset;
5688 }
5689
5690 if (uProcCtls & VMX_PROC_CTLS_RDTSC_EXIT)
5691 {
5692 uProcCtls &= ~VMX_PROC_CTLS_RDTSC_EXIT;
5693 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls);
5694 AssertRC(rc);
5695 pVCpu->hm.s.vmx.u32ProcCtls = uProcCtls;
5696 }
5697 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
5698 }
5699 else
5700 {
5701 /* We can't use TSC-offsetting (non-fixed TSC, warp drive active etc.), VM-exit on RDTSC(P). */
5702 if (!(uProcCtls & VMX_PROC_CTLS_RDTSC_EXIT))
5703 {
5704 uProcCtls |= VMX_PROC_CTLS_RDTSC_EXIT;
5705 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls);
5706 AssertRC(rc);
5707 pVCpu->hm.s.vmx.u32ProcCtls = uProcCtls;
5708 }
5709 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
5710 }
5711}
5712
5713
5714/**
5715 * Gets the IEM exception flags for the specified vector and IDT vectoring /
5716 * VM-exit interruption info type.
5717 *
5718 * @returns The IEM exception flags.
5719 * @param uVector The event vector.
5720 * @param uVmxVectorType The VMX event type.
5721 *
5722 * @remarks This function currently only constructs flags required for
5723 * IEMEvaluateRecursiveXcpt and not the complete flags (e.g, error-code
5724 * and CR2 aspects of an exception are not included).
5725 */
5726static uint32_t hmR0VmxGetIemXcptFlags(uint8_t uVector, uint32_t uVmxVectorType)
5727{
5728 uint32_t fIemXcptFlags;
5729 switch (uVmxVectorType)
5730 {
5731 case VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT:
5732 case VMX_IDT_VECTORING_INFO_TYPE_NMI:
5733 fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5734 break;
5735
5736 case VMX_IDT_VECTORING_INFO_TYPE_EXT_INT:
5737 fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5738 break;
5739
5740 case VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT:
5741 fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT | IEM_XCPT_FLAGS_ICEBP_INSTR;
5742 break;
5743
5744 case VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT:
5745 {
5746 fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5747 if (uVector == X86_XCPT_BP)
5748 fIemXcptFlags |= IEM_XCPT_FLAGS_BP_INSTR;
5749 else if (uVector == X86_XCPT_OF)
5750 fIemXcptFlags |= IEM_XCPT_FLAGS_OF_INSTR;
5751 else
5752 {
5753 fIemXcptFlags = 0;
5754 AssertMsgFailed(("Unexpected vector for software int. uVector=%#x", uVector));
5755 }
5756 break;
5757 }
5758
5759 case VMX_IDT_VECTORING_INFO_TYPE_SW_INT:
5760 fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5761 break;
5762
5763 default:
5764 fIemXcptFlags = 0;
5765 AssertMsgFailed(("Unexpected vector type! uVmxVectorType=%#x uVector=%#x", uVmxVectorType, uVector));
5766 break;
5767 }
5768 return fIemXcptFlags;
5769}
5770
5771
5772/**
5773 * Sets an event as a pending event to be injected into the guest.
5774 *
5775 * @param pVCpu The cross context virtual CPU structure.
5776 * @param u32IntInfo The VM-entry interruption-information field.
5777 * @param cbInstr The VM-entry instruction length in bytes (for software
5778 * interrupts, exceptions and privileged software
5779 * exceptions).
5780 * @param u32ErrCode The VM-entry exception error code.
5781 * @param GCPtrFaultAddress The fault-address (CR2) in case it's a
5782 * page-fault.
5783 *
5784 * @remarks Statistics counter assumes this is a guest event being injected or
5785 * re-injected into the guest, i.e. 'StatInjectPendingReflect' is
5786 * always incremented.
5787 */
5788DECLINLINE(void) hmR0VmxSetPendingEvent(PVMCPU pVCpu, uint32_t u32IntInfo, uint32_t cbInstr, uint32_t u32ErrCode,
5789 RTGCUINTPTR GCPtrFaultAddress)
5790{
5791 Assert(!pVCpu->hm.s.Event.fPending);
5792 pVCpu->hm.s.Event.fPending = true;
5793 pVCpu->hm.s.Event.u64IntInfo = u32IntInfo;
5794 pVCpu->hm.s.Event.u32ErrCode = u32ErrCode;
5795 pVCpu->hm.s.Event.cbInstr = cbInstr;
5796 pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
5797}
5798
5799
5800/**
5801 * Sets a double-fault (\#DF) exception as pending-for-injection into the VM.
5802 *
5803 * @param pVCpu The cross context virtual CPU structure.
5804 */
5805DECLINLINE(void) hmR0VmxSetPendingXcptDF(PVMCPU pVCpu)
5806{
5807 uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DF)
5808 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
5809 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 1)
5810 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
5811 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
5812}
5813
5814
5815/**
5816 * Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
5817 *
5818 * @param pVCpu The cross context virtual CPU structure.
5819 */
5820DECLINLINE(void) hmR0VmxSetPendingXcptUD(PVMCPU pVCpu)
5821{
5822 uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_UD)
5823 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
5824 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 0)
5825 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
5826 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
5827}
5828
5829
5830/**
5831 * Sets a debug (\#DB) exception as pending-for-injection into the VM.
5832 *
5833 * @param pVCpu The cross context virtual CPU structure.
5834 */
5835DECLINLINE(void) hmR0VmxSetPendingXcptDB(PVMCPU pVCpu)
5836{
5837 uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_DB)
5838 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
5839 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 0)
5840 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
5841 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
5842}
5843
5844
5845#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
5846/**
5847 * Sets a general-protection (\#GP) exception as pending-for-injection into the VM.
5848 *
5849 * @param pVCpu The cross context virtual CPU structure.
5850 * @param u32ErrCode The error code for the general-protection exception.
5851 */
5852DECLINLINE(void) hmR0VmxSetPendingXcptGP(PVMCPU pVCpu, uint32_t u32ErrCode)
5853{
5854 uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_GP)
5855 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
5856 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 1)
5857 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
5858 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, u32ErrCode, 0 /* GCPtrFaultAddress */);
5859}
5860
5861
5862/**
5863 * Sets a stack (\#SS) exception as pending-for-injection into the VM.
5864 *
5865 * @param pVCpu The cross context virtual CPU structure.
5866 * @param u32ErrCode The error code for the stack exception.
5867 */
5868DECLINLINE(void) hmR0VmxSetPendingXcptSS(PVMCPU pVCpu, uint32_t u32ErrCode)
5869{
5870 uint32_t const u32IntInfo = RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VECTOR, X86_XCPT_SS)
5871 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_TYPE, VMX_EXIT_INT_INFO_TYPE_HW_XCPT)
5872 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID, 1)
5873 | RT_BF_MAKE(VMX_BF_ENTRY_INT_INFO_VALID, 1);
5874 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, u32ErrCode, 0 /* GCPtrFaultAddress */);
5875}
5876
5877
5878/**
5879 * Decodes the memory operand of an instruction that caused a VM-exit.
5880 *
5881 * The VM-exit qualification field provides the displacement field for memory
5882 * operand instructions, if any.
5883 *
5884 * @returns Strict VBox status code (i.e. informational status codes too).
5885 * @retval VINF_SUCCESS if the operand was successfully decoded.
5886 * @retval VINF_HM_PENDING_XCPT if an exception was raised while decoding the
5887 * operand.
5888 * @param pVCpu The cross context virtual CPU structure.
5889 * @param uExitInstrInfo The VM-exit instruction information field.
5890 * @param enmMemAccess The memory operand's access type (read or write).
5891 * @param GCPtrDisp The instruction displacement field, if any. For
5892 * RIP-relative addressing pass RIP + displacement here.
5893 * @param pGCPtrMem Where to store the effective destination memory address.
5894 */
5895static VBOXSTRICTRC hmR0VmxDecodeMemOperand(PVMCPU pVCpu, uint32_t uExitInstrInfo, RTGCPTR GCPtrDisp, VMXMEMACCESS enmMemAccess,
5896 PRTGCPTR pGCPtrMem)
5897{
5898 Assert(pGCPtrMem);
5899 Assert(!CPUMIsGuestInRealOrV86Mode(pVCpu));
5900 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_EFER
5901 | CPUMCTX_EXTRN_CR0);
5902
5903 static uint64_t const s_auAddrSizeMasks[] = { UINT64_C(0xffff), UINT64_C(0xffffffff), UINT64_C(0xffffffffffffffff) };
5904 static uint64_t const s_auAccessSizeMasks[] = { sizeof(uint16_t), sizeof(uint32_t), sizeof(uint64_t) };
5905 AssertCompile(RT_ELEMENTS(s_auAccessSizeMasks) == RT_ELEMENTS(s_auAddrSizeMasks));
5906
5907 VMXEXITINSTRINFO ExitInstrInfo;
5908 ExitInstrInfo.u = uExitInstrInfo;
5909 uint8_t const uAddrSize = ExitInstrInfo.All.u3AddrSize;
5910 uint8_t const iSegReg = ExitInstrInfo.All.iSegReg;
5911 bool const fIdxRegValid = !ExitInstrInfo.All.fIdxRegInvalid;
5912 uint8_t const iIdxReg = ExitInstrInfo.All.iIdxReg;
5913 uint8_t const uScale = ExitInstrInfo.All.u2Scaling;
5914 bool const fBaseRegValid = !ExitInstrInfo.All.fBaseRegInvalid;
5915 uint8_t const iBaseReg = ExitInstrInfo.All.iBaseReg;
5916 bool const fIsMemOperand = !ExitInstrInfo.All.fIsRegOperand;
5917 bool const fIsLongMode = CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx);
5918
5919 /*
5920 * Validate instruction information.
5921 * This shouldn't happen on real hardware but useful while testing our nested hardware-virtualization code.
5922 */
5923 AssertLogRelMsgReturn(uAddrSize < RT_ELEMENTS(s_auAddrSizeMasks),
5924 ("Invalid address size. ExitInstrInfo=%#RX32\n", ExitInstrInfo.u), VERR_VMX_IPE_1);
5925 AssertLogRelMsgReturn(iSegReg < X86_SREG_COUNT,
5926 ("Invalid segment register. ExitInstrInfo=%#RX32\n", ExitInstrInfo.u), VERR_VMX_IPE_2);
5927 AssertLogRelMsgReturn(fIsMemOperand,
5928 ("Expected memory operand. ExitInstrInfo=%#RX32\n", ExitInstrInfo.u), VERR_VMX_IPE_3);
5929
5930 /*
5931 * Compute the complete effective address.
5932 *
5933 * See AMD instruction spec. 1.4.2 "SIB Byte Format"
5934 * See AMD spec. 4.5.2 "Segment Registers".
5935 */
5936 RTGCPTR GCPtrMem = GCPtrDisp;
5937 if (fBaseRegValid)
5938 GCPtrMem += pVCpu->cpum.GstCtx.aGRegs[iBaseReg].u64;
5939 if (fIdxRegValid)
5940 GCPtrMem += pVCpu->cpum.GstCtx.aGRegs[iIdxReg].u64 << uScale;
5941
5942 RTGCPTR const GCPtrOff = GCPtrMem;
5943 if ( !fIsLongMode
5944 || iSegReg >= X86_SREG_FS)
5945 GCPtrMem += pVCpu->cpum.GstCtx.aSRegs[iSegReg].u64Base;
5946 GCPtrMem &= s_auAddrSizeMasks[uAddrSize];
5947
5948 /*
5949 * Validate effective address.
5950 * See AMD spec. 4.5.3 "Segment Registers in 64-Bit Mode".
5951 */
5952 uint8_t const cbAccess = s_auAccessSizeMasks[uAddrSize];
5953 Assert(cbAccess > 0);
5954 if (fIsLongMode)
5955 {
5956 if (X86_IS_CANONICAL(GCPtrMem))
5957 {
5958 *pGCPtrMem = GCPtrMem;
5959 return VINF_SUCCESS;
5960 }
5961
5962 /** @todo r=ramshankar: We should probably raise \#SS or \#GP. See AMD spec. 4.12.2
5963 * "Data Limit Checks in 64-bit Mode". */
5964 Log4Func(("Long mode effective address is not canonical GCPtrMem=%#RX64\n", GCPtrMem));
5965 hmR0VmxSetPendingXcptGP(pVCpu, 0);
5966 return VINF_HM_PENDING_XCPT;
5967 }
5968
5969 /*
5970 * This is a watered down version of iemMemApplySegment().
5971 * Parts that are not applicable for VMX instructions like real-or-v8086 mode
5972 * and segment CPL/DPL checks are skipped.
5973 */
5974 RTGCPTR32 const GCPtrFirst32 = (RTGCPTR32)GCPtrOff;
5975 RTGCPTR32 const GCPtrLast32 = GCPtrFirst32 + cbAccess - 1;
5976 PCCPUMSELREG pSel = &pVCpu->cpum.GstCtx.aSRegs[iSegReg];
5977
5978 /* Check if the segment is present and usable. */
5979 if ( pSel->Attr.n.u1Present
5980 && !pSel->Attr.n.u1Unusable)
5981 {
5982 Assert(pSel->Attr.n.u1DescType);
5983 if (!(pSel->Attr.n.u4Type & X86_SEL_TYPE_CODE))
5984 {
5985 /* Check permissions for the data segment. */
5986 if ( enmMemAccess == VMXMEMACCESS_WRITE
5987 && !(pSel->Attr.n.u4Type & X86_SEL_TYPE_WRITE))
5988 {
5989 Log4Func(("Data segment access invalid. iSegReg=%#x Attr=%#RX32\n", iSegReg, pSel->Attr.u));
5990 hmR0VmxSetPendingXcptGP(pVCpu, iSegReg);
5991 return VINF_HM_PENDING_XCPT;
5992 }
5993
5994 /* Check limits if it's a normal data segment. */
5995 if (!(pSel->Attr.n.u4Type & X86_SEL_TYPE_DOWN))
5996 {
5997 if ( GCPtrFirst32 > pSel->u32Limit
5998 || GCPtrLast32 > pSel->u32Limit)
5999 {
6000 Log4Func(("Data segment limit exceeded."
6001 "iSegReg=%#x GCPtrFirst32=%#RX32 GCPtrLast32=%#RX32 u32Limit=%#RX32\n", iSegReg, GCPtrFirst32,
6002 GCPtrLast32, pSel->u32Limit));
6003 if (iSegReg == X86_SREG_SS)
6004 hmR0VmxSetPendingXcptSS(pVCpu, 0);
6005 else
6006 hmR0VmxSetPendingXcptGP(pVCpu, 0);
6007 return VINF_HM_PENDING_XCPT;
6008 }
6009 }
6010 else
6011 {
6012 /* Check limits if it's an expand-down data segment.
6013 Note! The upper boundary is defined by the B bit, not the G bit! */
6014 if ( GCPtrFirst32 < pSel->u32Limit + UINT32_C(1)
6015 || GCPtrLast32 > (pSel->Attr.n.u1DefBig ? UINT32_MAX : UINT32_C(0xffff)))
6016 {
6017 Log4Func(("Expand-down data segment limit exceeded."
6018 "iSegReg=%#x GCPtrFirst32=%#RX32 GCPtrLast32=%#RX32 u32Limit=%#RX32\n", iSegReg, GCPtrFirst32,
6019 GCPtrLast32, pSel->u32Limit));
6020 if (iSegReg == X86_SREG_SS)
6021 hmR0VmxSetPendingXcptSS(pVCpu, 0);
6022 else
6023 hmR0VmxSetPendingXcptGP(pVCpu, 0);
6024 return VINF_HM_PENDING_XCPT;
6025 }
6026 }
6027 }
6028 else
6029 {
6030 /* Check permissions for the code segment. */
6031 if ( enmMemAccess == VMXMEMACCESS_WRITE
6032 || ( enmMemAccess == VMXMEMACCESS_READ
6033 && !(pSel->Attr.n.u4Type & X86_SEL_TYPE_READ)))
6034 {
6035 Log4Func(("Code segment access invalid. Attr=%#RX32\n", pSel->Attr.u));
6036 Assert(!CPUMIsGuestInRealOrV86ModeEx(&pVCpu->cpum.GstCtx));
6037 hmR0VmxSetPendingXcptGP(pVCpu, 0);
6038 return VINF_HM_PENDING_XCPT;
6039 }
6040
6041 /* Check limits for the code segment (normal/expand-down not applicable for code segments). */
6042 if ( GCPtrFirst32 > pSel->u32Limit
6043 || GCPtrLast32 > pSel->u32Limit)
6044 {
6045 Log4Func(("Code segment limit exceeded. GCPtrFirst32=%#RX32 GCPtrLast32=%#RX32 u32Limit=%#RX32\n",
6046 GCPtrFirst32, GCPtrLast32, pSel->u32Limit));
6047 if (iSegReg == X86_SREG_SS)
6048 hmR0VmxSetPendingXcptSS(pVCpu, 0);
6049 else
6050 hmR0VmxSetPendingXcptGP(pVCpu, 0);
6051 return VINF_HM_PENDING_XCPT;
6052 }
6053 }
6054 }
6055 else
6056 {
6057 Log4Func(("Not present or unusable segment. iSegReg=%#x Attr=%#RX32\n", iSegReg, pSel->Attr.u));
6058 hmR0VmxSetPendingXcptGP(pVCpu, 0);
6059 return VINF_HM_PENDING_XCPT;
6060 }
6061
6062 *pGCPtrMem = GCPtrMem;
6063 return VINF_SUCCESS;
6064}
6065
6066
6067/**
6068 * Perform the relevant VMX instruction checks for VM-exits that occurred due to the
6069 * guest attempting to execute a VMX instruction.
6070 *
6071 * @returns Strict VBox status code (i.e. informational status codes too).
6072 * @retval VINF_SUCCESS if we should continue handling the VM-exit.
6073 * @retval VINF_HM_PENDING_XCPT if an exception was raised.
6074 *
6075 * @param pVCpu The cross context virtual CPU structure.
6076 * @param uExitReason The VM-exit reason.
6077 *
6078 * @todo NstVmx: Document other error codes when VM-exit is implemented.
6079 * @remarks No-long-jump zone!!!
6080 */
6081static VBOXSTRICTRC hmR0VmxCheckExitDueToVmxInstr(PVMCPU pVCpu, uint32_t uExitReason)
6082{
6083 HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS
6084 | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
6085
6086 if ( CPUMIsGuestInRealOrV86ModeEx(&pVCpu->cpum.GstCtx)
6087 || ( CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx)
6088 && !CPUMIsGuestIn64BitCodeEx(&pVCpu->cpum.GstCtx)))
6089 {
6090 Log4Func(("In real/v86-mode or long-mode outside 64-bit code segment -> #UD\n"));
6091 hmR0VmxSetPendingXcptUD(pVCpu);
6092 return VINF_HM_PENDING_XCPT;
6093 }
6094
6095 if (uExitReason == VMX_EXIT_VMXON)
6096 {
6097 /*
6098 * We check CR4.VMXE because it is required to be always set while in VMX operation
6099 * by physical CPUs and our CR4 read shadow is only consulted when executing specific
6100 * instructions (CLTS, LMSW, MOV CR, and SMSW) and thus doesn't affect CPU operation
6101 * otherwise (i.e. physical CPU won't automatically #UD if Cr4Shadow.VMXE is 0).
6102 */
6103 if (!CPUMIsGuestVmxEnabled(&pVCpu->cpum.GstCtx))
6104 {
6105 Log4Func(("CR4.VMXE is not set -> #UD\n"));
6106 hmR0VmxSetPendingXcptUD(pVCpu);
6107 return VINF_HM_PENDING_XCPT;
6108 }
6109 }
6110 else if (!CPUMIsGuestInVmxRootMode(&pVCpu->cpum.GstCtx))
6111 {
6112 /*
6113 * The guest has not entered VMX operation but attempted to execute a VMX instruction
6114 * (other than VMXON), we need to raise a #UD.
6115 */
6116 Log4Func(("Not in VMX root mode -> #UD\n"));
6117 hmR0VmxSetPendingXcptUD(pVCpu);
6118 return VINF_HM_PENDING_XCPT;
6119 }
6120
6121 if (CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx))
6122 {
6123 /*
6124 * The nested-guest attempted to execute a VMX instruction, cause a VM-exit and let
6125 * the guest hypervisor deal with it.
6126 */
6127 /** @todo NSTVMX: Trigger a VM-exit */
6128 }
6129
6130 /*
6131 * VMX instructions require CPL 0 except in VMX non-root mode where the VM-exit intercept
6132 * (above) takes preceedence over the CPL check.
6133 */
6134 if (CPUMGetGuestCPL(pVCpu) > 0)
6135 {
6136 Log4Func(("CPL > 0 -> #GP(0)\n"));
6137 hmR0VmxSetPendingXcptGP(pVCpu, 0);
6138 return VINF_HM_PENDING_XCPT;
6139 }
6140
6141 return VINF_SUCCESS;
6142}
6143
6144#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
6145
6146
6147/**
6148 * Handle a condition that occurred while delivering an event through the guest
6149 * IDT.
6150 *
6151 * @returns Strict VBox status code (i.e. informational status codes too).
6152 * @retval VINF_SUCCESS if we should continue handling the VM-exit.
6153 * @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought
6154 * to continue execution of the guest which will delivery the \#DF.
6155 * @retval VINF_EM_RESET if we detected a triple-fault condition.
6156 * @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
6157 *
6158 * @param pVCpu The cross context virtual CPU structure.
6159 * @param pVmxTransient Pointer to the VMX transient structure.
6160 *
6161 * @remarks No-long-jump zone!!!
6162 */
6163static VBOXSTRICTRC hmR0VmxCheckExitDueToEventDelivery(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
6164{
6165 uint32_t const uExitVector = VMX_EXIT_INT_INFO_VECTOR(pVmxTransient->uExitIntInfo);
6166
6167 int rc2 = hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient);
6168 rc2 |= hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
6169 AssertRCReturn(rc2, rc2);
6170
6171 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
6172 if (VMX_IDT_VECTORING_INFO_IS_VALID(pVmxTransient->uIdtVectoringInfo))
6173 {
6174 uint32_t const uIdtVectorType = VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uIdtVectoringInfo);
6175 uint32_t const uIdtVector = VMX_IDT_VECTORING_INFO_VECTOR(pVmxTransient->uIdtVectoringInfo);
6176
6177 /*
6178 * If the event was a software interrupt (generated with INT n) or a software exception
6179 * (generated by INT3/INTO) or a privileged software exception (generated by INT1), we
6180 * can handle the VM-exit and continue guest execution which will re-execute the
6181 * instruction rather than re-injecting the exception, as that can cause premature
6182 * trips to ring-3 before injection and involve TRPM which currently has no way of
6183 * storing that these exceptions were caused by these instructions (ICEBP's #DB poses
6184 * the problem).
6185 */
6186 IEMXCPTRAISE enmRaise;
6187 IEMXCPTRAISEINFO fRaiseInfo;
6188 if ( uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
6189 || uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT
6190 || uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT)
6191 {
6192 enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
6193 fRaiseInfo = IEMXCPTRAISEINFO_NONE;
6194 }
6195 else if (VMX_EXIT_INT_INFO_IS_VALID(pVmxTransient->uExitIntInfo))
6196 {
6197 uint32_t const uExitVectorType = VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uExitIntInfo);
6198 uint32_t const fIdtVectorFlags = hmR0VmxGetIemXcptFlags(uIdtVector, uIdtVectorType);
6199 uint32_t const fExitVectorFlags = hmR0VmxGetIemXcptFlags(uExitVector, uExitVectorType);
6200 /** @todo Make AssertMsgReturn as just AssertMsg later. */
6201 AssertMsgReturn(uExitVectorType == VMX_EXIT_INT_INFO_TYPE_HW_XCPT,
6202 ("hmR0VmxCheckExitDueToEventDelivery: Unexpected VM-exit interruption info. %#x!\n",
6203 uExitVectorType), VERR_VMX_IPE_5);
6204
6205 enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
6206
6207 /* Determine a vectoring #PF condition, see comment in hmR0VmxExitXcptPF(). */
6208 if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF | IEMXCPTRAISEINFO_NMI_PF))
6209 {
6210 pVmxTransient->fVectoringPF = true;
6211 enmRaise = IEMXCPTRAISE_PREV_EVENT;
6212 }
6213 }
6214 else
6215 {
6216 /*
6217 * If an exception or hardware interrupt delivery caused an EPT violation/misconfig or APIC access
6218 * VM-exit, then the VM-exit interruption-information will not be valid and we end up here.
6219 * It is sufficient to reflect the original event to the guest after handling the VM-exit.
6220 */
6221 Assert( uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
6222 || uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_NMI
6223 || uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT);
6224 enmRaise = IEMXCPTRAISE_PREV_EVENT;
6225 fRaiseInfo = IEMXCPTRAISEINFO_NONE;
6226 }
6227
6228 /*
6229 * On CPUs that support Virtual NMIs, if this VM-exit (be it an exception or EPT violation/misconfig
6230 * etc.) occurred while delivering the NMI, we need to clear the block-by-NMI field in the guest
6231 * interruptibility-state before re-delivering the NMI after handling the VM-exit. Otherwise the
6232 * subsequent VM-entry would fail.
6233 *
6234 * See Intel spec. 30.7.1.2 "Resuming Guest Software after Handling an Exception". See @bugref{7445}.
6235 */
6236 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS)
6237 && uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_NMI
6238 && ( enmRaise == IEMXCPTRAISE_PREV_EVENT
6239 || (fRaiseInfo & IEMXCPTRAISEINFO_NMI_PF))
6240 && (pVCpu->hm.s.vmx.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6241 {
6242 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6243 }
6244
6245 switch (enmRaise)
6246 {
6247 case IEMXCPTRAISE_CURRENT_XCPT:
6248 {
6249 Log4Func(("IDT: Pending secondary Xcpt: uIdtVectoringInfo=%#RX64 uExitIntInfo=%#RX64\n",
6250 pVmxTransient->uIdtVectoringInfo, pVmxTransient->uExitIntInfo));
6251 Assert(rcStrict == VINF_SUCCESS);
6252 break;
6253 }
6254
6255 case IEMXCPTRAISE_PREV_EVENT:
6256 {
6257 uint32_t u32ErrCode;
6258 if (VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(pVmxTransient->uIdtVectoringInfo))
6259 {
6260 rc2 = hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
6261 AssertRCReturn(rc2, rc2);
6262 u32ErrCode = pVmxTransient->uIdtVectoringErrorCode;
6263 }
6264 else
6265 u32ErrCode = 0;
6266
6267 /* If uExitVector is #PF, CR2 value will be updated from the VMCS if it's a guest #PF, see hmR0VmxExitXcptPF(). */
6268 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6269 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(pVmxTransient->uIdtVectoringInfo),
6270 0 /* cbInstr */, u32ErrCode, pVCpu->cpum.GstCtx.cr2);
6271
6272 Log4Func(("IDT: Pending vectoring event %#RX64 Err=%#RX32\n", pVCpu->hm.s.Event.u64IntInfo,
6273 pVCpu->hm.s.Event.u32ErrCode));
6274 Assert(rcStrict == VINF_SUCCESS);
6275 break;
6276 }
6277
6278 case IEMXCPTRAISE_REEXEC_INSTR:
6279 Assert(rcStrict == VINF_SUCCESS);
6280 break;
6281
6282 case IEMXCPTRAISE_DOUBLE_FAULT:
6283 {
6284 /*
6285 * Determing a vectoring double #PF condition. Used later, when PGM evaluates the
6286 * second #PF as a guest #PF (and not a shadow #PF) and needs to be converted into a #DF.
6287 */
6288 if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
6289 {
6290 pVmxTransient->fVectoringDoublePF = true;
6291 Log4Func(("IDT: Vectoring double #PF %#RX64 cr2=%#RX64\n", pVCpu->hm.s.Event.u64IntInfo,
6292 pVCpu->cpum.GstCtx.cr2));
6293 rcStrict = VINF_SUCCESS;
6294 }
6295 else
6296 {
6297 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6298 hmR0VmxSetPendingXcptDF(pVCpu);
6299 Log4Func(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
6300 uIdtVector, uExitVector));
6301 rcStrict = VINF_HM_DOUBLE_FAULT;
6302 }
6303 break;
6304 }
6305
6306 case IEMXCPTRAISE_TRIPLE_FAULT:
6307 {
6308 Log4Func(("IDT: Pending vectoring triple-fault uIdt=%#x uExit=%#x\n", uIdtVector, uExitVector));
6309 rcStrict = VINF_EM_RESET;
6310 break;
6311 }
6312
6313 case IEMXCPTRAISE_CPU_HANG:
6314 {
6315 Log4Func(("IDT: Bad guest! Entering CPU hang. fRaiseInfo=%#x\n", fRaiseInfo));
6316 rcStrict = VERR_EM_GUEST_CPU_HANG;
6317 break;
6318 }
6319
6320 default:
6321 {
6322 AssertMsgFailed(("IDT: vcpu[%RU32] Unexpected/invalid value! enmRaise=%#x\n", pVCpu->idCpu, enmRaise));
6323 rcStrict = VERR_VMX_IPE_2;
6324 break;
6325 }
6326 }
6327 }
6328 else if ( VMX_EXIT_INT_INFO_IS_VALID(pVmxTransient->uExitIntInfo)
6329 && VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(pVmxTransient->uExitIntInfo)
6330 && uExitVector != X86_XCPT_DF
6331 && (pVCpu->hm.s.vmx.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
6332 {
6333 /*
6334 * Execution of IRET caused this fault when NMI blocking was in effect (i.e we're in the guest NMI handler).
6335 * We need to set the block-by-NMI field so that NMIs remain blocked until the IRET execution is restarted.
6336 * See Intel spec. 30.7.1.2 "Resuming guest software after handling an exception".
6337 */
6338 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6339 {
6340 Log4Func(("Setting VMCPU_FF_BLOCK_NMIS. fValid=%RTbool uExitReason=%u\n",
6341 VMX_EXIT_INT_INFO_IS_VALID(pVmxTransient->uExitIntInfo), pVmxTransient->uExitReason));
6342 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6343 }
6344 }
6345
6346 Assert( rcStrict == VINF_SUCCESS || rcStrict == VINF_HM_DOUBLE_FAULT
6347 || rcStrict == VINF_EM_RESET || rcStrict == VERR_EM_GUEST_CPU_HANG);
6348 return rcStrict;
6349}
6350
6351
6352/**
6353 * Imports a guest segment register from the current VMCS into
6354 * the guest-CPU context.
6355 *
6356 * @returns VBox status code.
6357 * @param pVCpu The cross context virtual CPU structure.
6358 * @param idxSel Index of the selector in the VMCS.
6359 * @param idxLimit Index of the segment limit in the VMCS.
6360 * @param idxBase Index of the segment base in the VMCS.
6361 * @param idxAccess Index of the access rights of the segment in the VMCS.
6362 * @param pSelReg Pointer to the segment selector.
6363 *
6364 * @remarks Called with interrupts and/or preemption disabled, try not to assert and
6365 * do not log!
6366 *
6367 * @remarks Never call this function directly!!! Use the
6368 * HMVMX_IMPORT_SREG() macro as that takes care
6369 * of whether to read from the VMCS cache or not.
6370 */
6371static int hmR0VmxImportGuestSegmentReg(PVMCPU pVCpu, uint32_t idxSel, uint32_t idxLimit, uint32_t idxBase, uint32_t idxAccess,
6372 PCPUMSELREG pSelReg)
6373{
6374 NOREF(pVCpu);
6375
6376 uint32_t u32Sel;
6377 uint32_t u32Limit;
6378 uint32_t u32Attr;
6379 uint64_t u64Base;
6380 int rc = VMXReadVmcs32(idxSel, &u32Sel);
6381 rc |= VMXReadVmcs32(idxLimit, &u32Limit);
6382 rc |= VMXReadVmcs32(idxAccess, &u32Attr);
6383 rc |= VMXReadVmcsGstNByIdxVal(idxBase, &u64Base);
6384 AssertRCReturn(rc, rc);
6385
6386 pSelReg->Sel = (uint16_t)u32Sel;
6387 pSelReg->ValidSel = (uint16_t)u32Sel;
6388 pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6389 pSelReg->u32Limit = u32Limit;
6390 pSelReg->u64Base = u64Base;
6391 pSelReg->Attr.u = u32Attr;
6392
6393 /*
6394 * If VT-x marks the segment as unusable, most other bits remain undefined:
6395 * - For CS the L, D and G bits have meaning.
6396 * - For SS the DPL has meaning (it -is- the CPL for Intel and VBox).
6397 * - For the remaining data segments no bits are defined.
6398 *
6399 * The present bit and the unusable bit has been observed to be set at the
6400 * same time (the selector was supposed to be invalid as we started executing
6401 * a V8086 interrupt in ring-0).
6402 *
6403 * What should be important for the rest of the VBox code, is that the P bit is
6404 * cleared. Some of the other VBox code recognizes the unusable bit, but
6405 * AMD-V certainly don't, and REM doesn't really either. So, to be on the
6406 * safe side here, we'll strip off P and other bits we don't care about. If
6407 * any code breaks because Attr.u != 0 when Sel < 4, it should be fixed.
6408 *
6409 * See Intel spec. 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
6410 */
6411 if (pSelReg->Attr.u & X86DESCATTR_UNUSABLE)
6412 {
6413 Assert(idxSel != VMX_VMCS16_GUEST_TR_SEL); /* TR is the only selector that can never be unusable. */
6414
6415 /* Masking off: X86DESCATTR_P, X86DESCATTR_LIMIT_HIGH, and X86DESCATTR_AVL. The latter two are really irrelevant. */
6416 pSelReg->Attr.u &= X86DESCATTR_UNUSABLE | X86DESCATTR_L | X86DESCATTR_D | X86DESCATTR_G
6417 | X86DESCATTR_DPL | X86DESCATTR_TYPE | X86DESCATTR_DT;
6418#ifdef VBOX_STRICT
6419 VMMRZCallRing3Disable(pVCpu);
6420 Log4Func(("Unusable idxSel=%#x attr=%#x -> %#x\n", idxSel, u32Sel, pSelReg->Attr.u));
6421# ifdef DEBUG_bird
6422 AssertMsg((u32Attr & ~X86DESCATTR_P) == pSelReg->Attr.u,
6423 ("%#x: %#x != %#x (sel=%#x base=%#llx limit=%#x)\n",
6424 idxSel, u32Sel, pSelReg->Attr.u, pSelReg->Sel, pSelReg->u64Base, pSelReg->u32Limit));
6425# endif
6426 VMMRZCallRing3Enable(pVCpu);
6427#endif
6428 }
6429 return VINF_SUCCESS;
6430}
6431
6432
6433/**
6434 * Imports the guest RIP from the VMCS back into the guest-CPU context.
6435 *
6436 * @returns VBox status code.
6437 * @param pVCpu The cross context virtual CPU structure.
6438 *
6439 * @remarks Called with interrupts and/or preemption disabled, should not assert!
6440 * @remarks Do -not- call this function directly, use hmR0VmxImportGuestState()
6441 * instead!!!
6442 */
6443DECLINLINE(int) hmR0VmxImportGuestRip(PVMCPU pVCpu)
6444{
6445 uint64_t u64Val;
6446 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6447 if (pCtx->fExtrn & CPUMCTX_EXTRN_RIP)
6448 {
6449 int rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &u64Val);
6450 if (RT_SUCCESS(rc))
6451 {
6452 pCtx->rip = u64Val;
6453 EMR0HistoryUpdatePC(pVCpu, pCtx->rip, false);
6454 pCtx->fExtrn &= ~CPUMCTX_EXTRN_RIP;
6455 }
6456 return rc;
6457 }
6458 return VINF_SUCCESS;
6459}
6460
6461
6462/**
6463 * Imports the guest RFLAGS from the VMCS back into the guest-CPU context.
6464 *
6465 * @returns VBox status code.
6466 * @param pVCpu The cross context virtual CPU structure.
6467 *
6468 * @remarks Called with interrupts and/or preemption disabled, should not assert!
6469 * @remarks Do -not- call this function directly, use hmR0VmxImportGuestState()
6470 * instead!!!
6471 */
6472DECLINLINE(int) hmR0VmxImportGuestRFlags(PVMCPU pVCpu)
6473{
6474 uint32_t u32Val;
6475 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6476 if (pCtx->fExtrn & CPUMCTX_EXTRN_RFLAGS)
6477 {
6478 int rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Val);
6479 if (RT_SUCCESS(rc))
6480 {
6481 pCtx->eflags.u32 = u32Val;
6482
6483 /* Restore eflags for real-on-v86-mode hack. */
6484 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6485 {
6486 pCtx->eflags.Bits.u1VM = 0;
6487 pCtx->eflags.Bits.u2IOPL = pVCpu->hm.s.vmx.RealMode.Eflags.Bits.u2IOPL;
6488 }
6489 }
6490 pCtx->fExtrn &= ~CPUMCTX_EXTRN_RFLAGS;
6491 return rc;
6492 }
6493 return VINF_SUCCESS;
6494}
6495
6496
6497/**
6498 * Imports the guest interruptibility-state from the VMCS back into the guest-CPU
6499 * context.
6500 *
6501 * @returns VBox status code.
6502 * @param pVCpu The cross context virtual CPU structure.
6503 *
6504 * @remarks Called with interrupts and/or preemption disabled, try not to assert and
6505 * do not log!
6506 * @remarks Do -not- call this function directly, use hmR0VmxImportGuestState()
6507 * instead!!!
6508 */
6509DECLINLINE(int) hmR0VmxImportGuestIntrState(PVMCPU pVCpu)
6510{
6511 uint32_t u32Val;
6512 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6513 int rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &u32Val);
6514 AssertRCReturn(rc, rc);
6515
6516 /*
6517 * We additionally have a requirement to import RIP, RFLAGS depending on whether we
6518 * might need them in hmR0VmxEvaluatePendingEvent().
6519 */
6520 if (!u32Val)
6521 {
6522 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6523 {
6524 rc = hmR0VmxImportGuestRip(pVCpu);
6525 rc |= hmR0VmxImportGuestRFlags(pVCpu);
6526 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6527 }
6528
6529 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6530 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6531 }
6532 else
6533 {
6534 rc = hmR0VmxImportGuestRip(pVCpu);
6535 rc |= hmR0VmxImportGuestRFlags(pVCpu);
6536
6537 if (u32Val & ( VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS
6538 | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))
6539 {
6540 EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
6541 }
6542 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6543 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6544
6545 if (u32Val & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
6546 {
6547 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6548 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6549 }
6550 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
6551 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6552 }
6553
6554 return VINF_SUCCESS;
6555}
6556
6557
6558/**
6559 * Worker for VMXR0ImportStateOnDemand.
6560 *
6561 * @returns VBox status code.
6562 * @param pVCpu The cross context virtual CPU structure.
6563 * @param fWhat What to import, CPUMCTX_EXTRN_XXX.
6564 */
6565static int hmR0VmxImportGuestState(PVMCPU pVCpu, uint64_t fWhat)
6566{
6567#define VMXLOCAL_BREAK_RC(a_rc) \
6568 if (RT_FAILURE(a_rc)) \
6569 break
6570
6571 int rc = VINF_SUCCESS;
6572 PVM pVM = pVCpu->CTX_SUFF(pVM);
6573 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6574 uint64_t u64Val;
6575 uint32_t u32Val;
6576
6577 Log4Func(("fExtrn=%#RX64 fWhat=%#RX64\n", pCtx->fExtrn, fWhat));
6578 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatImportGuestState, x);
6579
6580 /*
6581 * We disable interrupts to make the updating of the state and in particular
6582 * the fExtrn modification atomic wrt to preemption hooks.
6583 */
6584 RTCCUINTREG const fEFlags = ASMIntDisableFlags();
6585
6586 fWhat &= pCtx->fExtrn;
6587 if (fWhat)
6588 {
6589 do
6590 {
6591 if (fWhat & CPUMCTX_EXTRN_RIP)
6592 {
6593 rc = hmR0VmxImportGuestRip(pVCpu);
6594 VMXLOCAL_BREAK_RC(rc);
6595 }
6596
6597 if (fWhat & CPUMCTX_EXTRN_RFLAGS)
6598 {
6599 rc = hmR0VmxImportGuestRFlags(pVCpu);
6600 VMXLOCAL_BREAK_RC(rc);
6601 }
6602
6603 if (fWhat & CPUMCTX_EXTRN_HM_VMX_INT_STATE)
6604 {
6605 rc = hmR0VmxImportGuestIntrState(pVCpu);
6606 VMXLOCAL_BREAK_RC(rc);
6607 }
6608
6609 if (fWhat & CPUMCTX_EXTRN_RSP)
6610 {
6611 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &u64Val);
6612 VMXLOCAL_BREAK_RC(rc);
6613 pCtx->rsp = u64Val;
6614 }
6615
6616 if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
6617 {
6618 if (fWhat & CPUMCTX_EXTRN_CS)
6619 {
6620 rc = HMVMX_IMPORT_SREG(CS, &pCtx->cs);
6621 rc |= hmR0VmxImportGuestRip(pVCpu);
6622 VMXLOCAL_BREAK_RC(rc);
6623 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6624 pCtx->cs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrCS.u;
6625 EMR0HistoryUpdatePC(pVCpu, pCtx->cs.u64Base + pCtx->rip, true);
6626 }
6627 if (fWhat & CPUMCTX_EXTRN_SS)
6628 {
6629 rc = HMVMX_IMPORT_SREG(SS, &pCtx->ss);
6630 VMXLOCAL_BREAK_RC(rc);
6631 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6632 pCtx->ss.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrSS.u;
6633 }
6634 if (fWhat & CPUMCTX_EXTRN_DS)
6635 {
6636 rc = HMVMX_IMPORT_SREG(DS, &pCtx->ds);
6637 VMXLOCAL_BREAK_RC(rc);
6638 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6639 pCtx->ds.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrDS.u;
6640 }
6641 if (fWhat & CPUMCTX_EXTRN_ES)
6642 {
6643 rc = HMVMX_IMPORT_SREG(ES, &pCtx->es);
6644 VMXLOCAL_BREAK_RC(rc);
6645 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6646 pCtx->es.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrES.u;
6647 }
6648 if (fWhat & CPUMCTX_EXTRN_FS)
6649 {
6650 rc = HMVMX_IMPORT_SREG(FS, &pCtx->fs);
6651 VMXLOCAL_BREAK_RC(rc);
6652 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6653 pCtx->fs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrFS.u;
6654 }
6655 if (fWhat & CPUMCTX_EXTRN_GS)
6656 {
6657 rc = HMVMX_IMPORT_SREG(GS, &pCtx->gs);
6658 VMXLOCAL_BREAK_RC(rc);
6659 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6660 pCtx->gs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrGS.u;
6661 }
6662 }
6663
6664 if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
6665 {
6666 if (fWhat & CPUMCTX_EXTRN_LDTR)
6667 {
6668 rc = HMVMX_IMPORT_SREG(LDTR, &pCtx->ldtr);
6669 VMXLOCAL_BREAK_RC(rc);
6670 }
6671
6672 if (fWhat & CPUMCTX_EXTRN_GDTR)
6673 {
6674 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE, &u64Val);
6675 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val);
6676 VMXLOCAL_BREAK_RC(rc);
6677 pCtx->gdtr.pGdt = u64Val;
6678 pCtx->gdtr.cbGdt = u32Val;
6679 }
6680
6681 /* Guest IDTR. */
6682 if (fWhat & CPUMCTX_EXTRN_IDTR)
6683 {
6684 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE, &u64Val);
6685 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val);
6686 VMXLOCAL_BREAK_RC(rc);
6687 pCtx->idtr.pIdt = u64Val;
6688 pCtx->idtr.cbIdt = u32Val;
6689 }
6690
6691 /* Guest TR. */
6692 if (fWhat & CPUMCTX_EXTRN_TR)
6693 {
6694 /* Real-mode emulation using virtual-8086 mode has the fake TSS (pRealModeTSS) in TR, don't save that one. */
6695 if (!pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6696 {
6697 rc = HMVMX_IMPORT_SREG(TR, &pCtx->tr);
6698 VMXLOCAL_BREAK_RC(rc);
6699 }
6700 }
6701 }
6702
6703 if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
6704 {
6705 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_SYSENTER_EIP, &pCtx->SysEnter.eip);
6706 rc |= VMXReadVmcsGstN(VMX_VMCS_GUEST_SYSENTER_ESP, &pCtx->SysEnter.esp);
6707 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, &u32Val);
6708 pCtx->SysEnter.cs = u32Val;
6709 VMXLOCAL_BREAK_RC(rc);
6710 }
6711
6712#if HC_ARCH_BITS == 64
6713 if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
6714 {
6715 if ( pVM->hm.s.fAllow64BitGuests
6716 && (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST))
6717 pCtx->msrKERNELGSBASE = ASMRdMsr(MSR_K8_KERNEL_GS_BASE);
6718 }
6719
6720 if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
6721 {
6722 if ( pVM->hm.s.fAllow64BitGuests
6723 && (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST))
6724 {
6725 pCtx->msrLSTAR = ASMRdMsr(MSR_K8_LSTAR);
6726 pCtx->msrSTAR = ASMRdMsr(MSR_K6_STAR);
6727 pCtx->msrSFMASK = ASMRdMsr(MSR_K8_SF_MASK);
6728 }
6729 }
6730#endif
6731
6732 if ( (fWhat & (CPUMCTX_EXTRN_TSC_AUX | CPUMCTX_EXTRN_OTHER_MSRS))
6733#if HC_ARCH_BITS == 32
6734 || (fWhat & (CPUMCTX_EXTRN_KERNEL_GS_BASE | CPUMCTX_EXTRN_SYSCALL_MSRS))
6735#endif
6736 )
6737 {
6738 PCVMXAUTOMSR pMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
6739 uint32_t const cMsrs = pVCpu->hm.s.vmx.cMsrs;
6740 for (uint32_t i = 0; i < cMsrs; i++, pMsr++)
6741 {
6742 switch (pMsr->u32Msr)
6743 {
6744#if HC_ARCH_BITS == 32
6745 case MSR_K8_LSTAR: pCtx->msrLSTAR = pMsr->u64Value; break;
6746 case MSR_K6_STAR: pCtx->msrSTAR = pMsr->u64Value; break;
6747 case MSR_K8_SF_MASK: pCtx->msrSFMASK = pMsr->u64Value; break;
6748 case MSR_K8_KERNEL_GS_BASE: pCtx->msrKERNELGSBASE = pMsr->u64Value; break;
6749#endif
6750 case MSR_IA32_SPEC_CTRL: CPUMSetGuestSpecCtrl(pVCpu, pMsr->u64Value); break;
6751 case MSR_K8_TSC_AUX: CPUMSetGuestTscAux(pVCpu, pMsr->u64Value); break;
6752 case MSR_K6_EFER: /* EFER can't be changed without causing a VM-exit */ break;
6753 default:
6754 {
6755 pVCpu->hm.s.u32HMError = pMsr->u32Msr;
6756 ASMSetFlags(fEFlags);
6757 AssertMsgFailed(("Unexpected MSR in auto-load/store area. uMsr=%#RX32 cMsrs=%u\n", pMsr->u32Msr,
6758 cMsrs));
6759 return VERR_HM_UNEXPECTED_LD_ST_MSR;
6760 }
6761 }
6762 }
6763 }
6764
6765 if (fWhat & CPUMCTX_EXTRN_DR7)
6766 {
6767 if (!pVCpu->hm.s.fUsingHyperDR7)
6768 {
6769 /* Upper 32-bits are always zero. See Intel spec. 2.7.3 "Loading and Storing Debug Registers". */
6770 rc = VMXReadVmcs32(VMX_VMCS_GUEST_DR7, &u32Val);
6771 VMXLOCAL_BREAK_RC(rc);
6772 pCtx->dr[7] = u32Val;
6773 }
6774 }
6775
6776 if (fWhat & CPUMCTX_EXTRN_CR_MASK)
6777 {
6778 uint32_t u32Shadow;
6779 if (fWhat & CPUMCTX_EXTRN_CR0)
6780 {
6781 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &u32Val);
6782 rc |= VMXReadVmcs32(VMX_VMCS_CTRL_CR0_READ_SHADOW, &u32Shadow);
6783 VMXLOCAL_BREAK_RC(rc);
6784 u32Val = (u32Val & ~pVCpu->hm.s.vmx.u32Cr0Mask)
6785 | (u32Shadow & pVCpu->hm.s.vmx.u32Cr0Mask);
6786 VMMRZCallRing3Disable(pVCpu); /* Calls into PGM which has Log statements. */
6787 CPUMSetGuestCR0(pVCpu, u32Val);
6788 VMMRZCallRing3Enable(pVCpu);
6789 }
6790
6791 if (fWhat & CPUMCTX_EXTRN_CR4)
6792 {
6793 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR4, &u32Val);
6794 rc |= VMXReadVmcs32(VMX_VMCS_CTRL_CR4_READ_SHADOW, &u32Shadow);
6795 VMXLOCAL_BREAK_RC(rc);
6796 u32Val = (u32Val & ~pVCpu->hm.s.vmx.u32Cr4Mask)
6797 | (u32Shadow & pVCpu->hm.s.vmx.u32Cr4Mask);
6798 CPUMSetGuestCR4(pVCpu, u32Val);
6799 }
6800
6801 if (fWhat & CPUMCTX_EXTRN_CR3)
6802 {
6803 /* CR0.PG bit changes are always intercepted, so it's up to date. */
6804 if ( pVM->hm.s.vmx.fUnrestrictedGuest
6805 || ( pVM->hm.s.fNestedPaging
6806 && CPUMIsGuestPagingEnabledEx(pCtx)))
6807 {
6808 rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_CR3, &u64Val);
6809 if (pCtx->cr3 != u64Val)
6810 {
6811 CPUMSetGuestCR3(pVCpu, u64Val);
6812 VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
6813 }
6814
6815 /* If the guest is in PAE mode, sync back the PDPE's into the guest state.
6816 Note: CR4.PAE, CR0.PG, EFER bit changes are always intercepted, so they're up to date. */
6817 if (CPUMIsGuestInPAEModeEx(pCtx))
6818 {
6819 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &pVCpu->hm.s.aPdpes[0].u);
6820 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &pVCpu->hm.s.aPdpes[1].u);
6821 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &pVCpu->hm.s.aPdpes[2].u);
6822 rc |= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &pVCpu->hm.s.aPdpes[3].u);
6823 VMXLOCAL_BREAK_RC(rc);
6824 VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
6825 }
6826 }
6827 }
6828 }
6829 } while (0);
6830
6831 if (RT_SUCCESS(rc))
6832 {
6833 /* Update fExtrn. */
6834 pCtx->fExtrn &= ~fWhat;
6835
6836 /* If everything has been imported, clear the HM keeper bit. */
6837 if (!(pCtx->fExtrn & HMVMX_CPUMCTX_EXTRN_ALL))
6838 {
6839 pCtx->fExtrn &= ~CPUMCTX_EXTRN_KEEPER_HM;
6840 Assert(!pCtx->fExtrn);
6841 }
6842 }
6843 }
6844 else
6845 AssertMsg(!pCtx->fExtrn || (pCtx->fExtrn & HMVMX_CPUMCTX_EXTRN_ALL), ("%#RX64\n", pCtx->fExtrn));
6846
6847 ASMSetFlags(fEFlags);
6848
6849 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatImportGuestState, x);
6850
6851 /*
6852 * Honor any pending CR3 updates.
6853 *
6854 * Consider this scenario: VM-exit -> VMMRZCallRing3Enable() -> do stuff that causes a longjmp -> hmR0VmxCallRing3Callback()
6855 * -> VMMRZCallRing3Disable() -> hmR0VmxImportGuestState() -> Sets VMCPU_FF_HM_UPDATE_CR3 pending -> return from the longjmp
6856 * -> continue with VM-exit handling -> hmR0VmxImportGuestState() and here we are.
6857 *
6858 * The reason for such complicated handling is because VM-exits that call into PGM expect CR3 to be up-to-date and thus
6859 * if any CR3-saves -before- the VM-exit (longjmp) postponed the CR3 update via the force-flag, any VM-exit handler that
6860 * calls into PGM when it re-saves CR3 will end up here and we call PGMUpdateCR3(). This is why the code below should
6861 * -NOT- check if CPUMCTX_EXTRN_CR3 is set!
6862 *
6863 * The longjmp exit path can't check these CR3 force-flags and call code that takes a lock again. We cover for it here.
6864 */
6865 if (VMMRZCallRing3IsEnabled(pVCpu))
6866 {
6867 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
6868 {
6869 Assert(!(ASMAtomicUoReadU64(&pCtx->fExtrn) & CPUMCTX_EXTRN_CR3));
6870 PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
6871 }
6872
6873 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
6874 PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
6875
6876 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
6877 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
6878 }
6879
6880 return VINF_SUCCESS;
6881#undef VMXLOCAL_BREAK_RC
6882}
6883
6884
6885/**
6886 * Saves the guest state from the VMCS into the guest-CPU context.
6887 *
6888 * @returns VBox status code.
6889 * @param pVCpu The cross context virtual CPU structure.
6890 * @param fWhat What to import, CPUMCTX_EXTRN_XXX.
6891 */
6892VMMR0DECL(int) VMXR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat)
6893{
6894 return hmR0VmxImportGuestState(pVCpu, fWhat);
6895}
6896
6897
6898/**
6899 * Check per-VM and per-VCPU force flag actions that require us to go back to
6900 * ring-3 for one reason or another.
6901 *
6902 * @returns Strict VBox status code (i.e. informational status codes too)
6903 * @retval VINF_SUCCESS if we don't have any actions that require going back to
6904 * ring-3.
6905 * @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
6906 * @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
6907 * interrupts)
6908 * @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
6909 * all EMTs to be in ring-3.
6910 * @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
6911 * @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
6912 * to the EM loop.
6913 *
6914 * @param pVCpu The cross context virtual CPU structure.
6915 * @param fStepping Running in hmR0VmxRunGuestCodeStep().
6916 */
6917static VBOXSTRICTRC hmR0VmxCheckForceFlags(PVMCPU pVCpu, bool fStepping)
6918{
6919 Assert(VMMRZCallRing3IsEnabled(pVCpu));
6920
6921 /*
6922 * Anything pending? Should be more likely than not if we're doing a good job.
6923 */
6924 PVM pVM = pVCpu->CTX_SUFF(pVM);
6925 if ( !fStepping
6926 ? !VM_FF_IS_ANY_SET(pVM, VM_FF_HP_R0_PRE_HM_MASK)
6927 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HP_R0_PRE_HM_MASK)
6928 : !VM_FF_IS_ANY_SET(pVM, VM_FF_HP_R0_PRE_HM_STEP_MASK)
6929 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
6930 return VINF_SUCCESS;
6931
6932 /* Pending PGM C3 sync. */
6933 if (VMCPU_FF_IS_ANY_SET(pVCpu,VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
6934 {
6935 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6936 Assert(!(ASMAtomicUoReadU64(&pCtx->fExtrn) & (CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4)));
6937 VBOXSTRICTRC rcStrict2 = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4,
6938 VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
6939 if (rcStrict2 != VINF_SUCCESS)
6940 {
6941 AssertRC(VBOXSTRICTRC_VAL(rcStrict2));
6942 Log4Func(("PGMSyncCR3 forcing us back to ring-3. rc2=%d\n", VBOXSTRICTRC_VAL(rcStrict2)));
6943 return rcStrict2;
6944 }
6945 }
6946
6947 /* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
6948 if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HM_TO_R3_MASK)
6949 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
6950 {
6951 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
6952 int rc2 = RT_LIKELY(!VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_RAW_TO_R3 : VINF_EM_NO_MEMORY;
6953 Log4Func(("HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc2));
6954 return rc2;
6955 }
6956
6957 /* Pending VM request packets, such as hardware interrupts. */
6958 if ( VM_FF_IS_SET(pVM, VM_FF_REQUEST)
6959 || VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_REQUEST))
6960 {
6961 Log4Func(("Pending VM request forcing us back to ring-3\n"));
6962 return VINF_EM_PENDING_REQUEST;
6963 }
6964
6965 /* Pending PGM pool flushes. */
6966 if (VM_FF_IS_SET(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
6967 {
6968 Log4Func(("PGM pool flush pending forcing us back to ring-3\n"));
6969 return VINF_PGM_POOL_FLUSH_PENDING;
6970 }
6971
6972 /* Pending DMA requests. */
6973 if (VM_FF_IS_SET(pVM, VM_FF_PDM_DMA))
6974 {
6975 Log4Func(("Pending DMA request forcing us back to ring-3\n"));
6976 return VINF_EM_RAW_TO_R3;
6977 }
6978
6979 return VINF_SUCCESS;
6980}
6981
6982
6983/**
6984 * Converts any TRPM trap into a pending HM event. This is typically used when
6985 * entering from ring-3 (not longjmp returns).
6986 *
6987 * @param pVCpu The cross context virtual CPU structure.
6988 */
6989static void hmR0VmxTrpmTrapToPendingEvent(PVMCPU pVCpu)
6990{
6991 Assert(TRPMHasTrap(pVCpu));
6992 Assert(!pVCpu->hm.s.Event.fPending);
6993
6994 uint8_t uVector;
6995 TRPMEVENT enmTrpmEvent;
6996 RTGCUINT uErrCode;
6997 RTGCUINTPTR GCPtrFaultAddress;
6998 uint8_t cbInstr;
6999
7000 int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
7001 AssertRC(rc);
7002
7003 /* Refer Intel spec. 24.8.3 "VM-entry Controls for Event Injection" for the format of u32IntInfo. */
7004 uint32_t u32IntInfo = uVector | VMX_EXIT_INT_INFO_VALID;
7005 if (enmTrpmEvent == TRPM_TRAP)
7006 {
7007 switch (uVector)
7008 {
7009 case X86_XCPT_NMI:
7010 u32IntInfo |= (VMX_EXIT_INT_INFO_TYPE_NMI << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7011 break;
7012
7013 case X86_XCPT_BP:
7014 case X86_XCPT_OF:
7015 u32IntInfo |= (VMX_EXIT_INT_INFO_TYPE_SW_XCPT << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7016 break;
7017
7018 case X86_XCPT_PF:
7019 case X86_XCPT_DF:
7020 case X86_XCPT_TS:
7021 case X86_XCPT_NP:
7022 case X86_XCPT_SS:
7023 case X86_XCPT_GP:
7024 case X86_XCPT_AC:
7025 u32IntInfo |= VMX_EXIT_INT_INFO_ERROR_CODE_VALID;
7026 RT_FALL_THRU();
7027 default:
7028 u32IntInfo |= (VMX_EXIT_INT_INFO_TYPE_HW_XCPT << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7029 break;
7030 }
7031 }
7032 else if (enmTrpmEvent == TRPM_HARDWARE_INT)
7033 u32IntInfo |= (VMX_EXIT_INT_INFO_TYPE_EXT_INT << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7034 else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
7035 u32IntInfo |= (VMX_EXIT_INT_INFO_TYPE_SW_INT << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7036 else
7037 AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
7038
7039 rc = TRPMResetTrap(pVCpu);
7040 AssertRC(rc);
7041 Log4(("TRPM->HM event: u32IntInfo=%#RX32 enmTrpmEvent=%d cbInstr=%u uErrCode=%#RX32 GCPtrFaultAddress=%#RGv\n",
7042 u32IntInfo, enmTrpmEvent, cbInstr, uErrCode, GCPtrFaultAddress));
7043
7044 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, cbInstr, uErrCode, GCPtrFaultAddress);
7045}
7046
7047
7048/**
7049 * Converts the pending HM event into a TRPM trap.
7050 *
7051 * @param pVCpu The cross context virtual CPU structure.
7052 */
7053static void hmR0VmxPendingEventToTrpmTrap(PVMCPU pVCpu)
7054{
7055 Assert(pVCpu->hm.s.Event.fPending);
7056
7057 uint32_t uVectorType = VMX_IDT_VECTORING_INFO_TYPE(pVCpu->hm.s.Event.u64IntInfo);
7058 uint32_t uVector = VMX_IDT_VECTORING_INFO_VECTOR(pVCpu->hm.s.Event.u64IntInfo);
7059 bool fErrorCodeValid = VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(pVCpu->hm.s.Event.u64IntInfo);
7060 uint32_t uErrorCode = pVCpu->hm.s.Event.u32ErrCode;
7061
7062 /* If a trap was already pending, we did something wrong! */
7063 Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo */, NULL /* pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
7064
7065 TRPMEVENT enmTrapType;
7066 switch (uVectorType)
7067 {
7068 case VMX_IDT_VECTORING_INFO_TYPE_EXT_INT:
7069 enmTrapType = TRPM_HARDWARE_INT;
7070 break;
7071
7072 case VMX_IDT_VECTORING_INFO_TYPE_SW_INT:
7073 enmTrapType = TRPM_SOFTWARE_INT;
7074 break;
7075
7076 case VMX_IDT_VECTORING_INFO_TYPE_NMI:
7077 case VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT:
7078 case VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7079 case VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT:
7080 enmTrapType = TRPM_TRAP;
7081 break;
7082
7083 default:
7084 AssertMsgFailed(("Invalid trap type %#x\n", uVectorType));
7085 enmTrapType = TRPM_32BIT_HACK;
7086 break;
7087 }
7088
7089 Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, enmTrapType));
7090
7091 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7092 AssertRC(rc);
7093
7094 if (fErrorCodeValid)
7095 TRPMSetErrorCode(pVCpu, uErrorCode);
7096
7097 if ( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
7098 && uVector == X86_XCPT_PF)
7099 {
7100 TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
7101 }
7102 else if ( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
7103 || uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT
7104 || uVectorType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT)
7105 {
7106 AssertMsg( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
7107 || (uVector == X86_XCPT_BP || uVector == X86_XCPT_OF),
7108 ("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
7109 TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
7110 }
7111
7112 /* Clear the events from the VMCS. */
7113 VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, 0);
7114
7115 /* We're now done converting the pending event. */
7116 pVCpu->hm.s.Event.fPending = false;
7117}
7118
7119
7120/**
7121 * Does the necessary state syncing before returning to ring-3 for any reason
7122 * (longjmp, preemption, voluntary exits to ring-3) from VT-x.
7123 *
7124 * @returns VBox status code.
7125 * @param pVCpu The cross context virtual CPU structure.
7126 * @param fImportState Whether to import the guest state from the VMCS back
7127 * to the guest-CPU context.
7128 *
7129 * @remarks No-long-jmp zone!!!
7130 */
7131static int hmR0VmxLeave(PVMCPU pVCpu, bool fImportState)
7132{
7133 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
7134 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
7135
7136 RTCPUID idCpu = RTMpCpuId();
7137 Log4Func(("HostCpuId=%u\n", idCpu));
7138
7139 /*
7140 * !!! IMPORTANT !!!
7141 * If you modify code here, check whether hmR0VmxCallRing3Callback() needs to be updated too.
7142 */
7143
7144 /* Save the guest state if necessary. */
7145 if (fImportState)
7146 {
7147 int rc = hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
7148 AssertRCReturn(rc, rc);
7149 }
7150
7151 /* Restore host FPU state if necessary. We will resync on next R0 reentry. */
7152 CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
7153 Assert(!CPUMIsGuestFPUStateActive(pVCpu));
7154
7155 /* Restore host debug registers if necessary. We will resync on next R0 reentry. */
7156#ifdef VBOX_STRICT
7157 if (CPUMIsHyperDebugStateActive(pVCpu))
7158 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
7159#endif
7160 CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, true /* save DR6 */);
7161 Assert(!CPUMIsGuestDebugStateActive(pVCpu) && !CPUMIsGuestDebugStateActivePending(pVCpu));
7162 Assert(!CPUMIsHyperDebugStateActive(pVCpu) && !CPUMIsHyperDebugStateActivePending(pVCpu));
7163
7164#if HC_ARCH_BITS == 64
7165 /* Restore host-state bits that VT-x only restores partially. */
7166 if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
7167 && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
7168 {
7169 Log4Func(("Restoring Host State: fRestoreHostFlags=%#RX32 HostCpuId=%u\n", pVCpu->hm.s.vmx.fRestoreHostFlags, idCpu));
7170 VMXRestoreHostState(pVCpu->hm.s.vmx.fRestoreHostFlags, &pVCpu->hm.s.vmx.RestoreHost);
7171 }
7172 pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
7173#endif
7174
7175 /* Restore the lazy host MSRs as we're leaving VT-x context. */
7176 if (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
7177 {
7178 /* We shouldn't restore the host MSRs without saving the guest MSRs first. */
7179 if (!fImportState)
7180 {
7181 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_KERNEL_GS_BASE | CPUMCTX_EXTRN_SYSCALL_MSRS);
7182 AssertRCReturn(rc, rc);
7183 }
7184 hmR0VmxLazyRestoreHostMsrs(pVCpu);
7185 Assert(!pVCpu->hm.s.vmx.fLazyMsrs);
7186 }
7187 else
7188 pVCpu->hm.s.vmx.fLazyMsrs = 0;
7189
7190 /* Update auto-load/store host MSRs values when we re-enter VT-x (as we could be on a different CPU). */
7191 pVCpu->hm.s.vmx.fUpdatedHostMsrs = false;
7192
7193 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
7194 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatImportGuestState);
7195 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExportGuestState);
7196 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatPreExit);
7197 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitHandling);
7198 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitIO);
7199 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitMovCRx);
7200 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitXcptNmi);
7201 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
7202
7203 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
7204
7205 /** @todo This partially defeats the purpose of having preemption hooks.
7206 * The problem is, deregistering the hooks should be moved to a place that
7207 * lasts until the EMT is about to be destroyed not everytime while leaving HM
7208 * context.
7209 */
7210 if (pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_ACTIVE)
7211 {
7212 int rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
7213 AssertRCReturn(rc, rc);
7214
7215 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
7216 Log4Func(("Cleared Vmcs. HostCpuId=%u\n", idCpu));
7217 }
7218 Assert(!(pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_LAUNCHED));
7219 NOREF(idCpu);
7220
7221 return VINF_SUCCESS;
7222}
7223
7224
7225/**
7226 * Leaves the VT-x session.
7227 *
7228 * @returns VBox status code.
7229 * @param pVCpu The cross context virtual CPU structure.
7230 *
7231 * @remarks No-long-jmp zone!!!
7232 */
7233static int hmR0VmxLeaveSession(PVMCPU pVCpu)
7234{
7235 HM_DISABLE_PREEMPT(pVCpu);
7236 HMVMX_ASSERT_CPU_SAFE(pVCpu);
7237 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
7238 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
7239
7240 /* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
7241 and done this from the VMXR0ThreadCtxCallback(). */
7242 if (!pVCpu->hm.s.fLeaveDone)
7243 {
7244 int rc2 = hmR0VmxLeave(pVCpu, true /* fImportState */);
7245 AssertRCReturnStmt(rc2, HM_RESTORE_PREEMPT(), rc2);
7246 pVCpu->hm.s.fLeaveDone = true;
7247 }
7248 Assert(!pVCpu->cpum.GstCtx.fExtrn);
7249
7250 /*
7251 * !!! IMPORTANT !!!
7252 * If you modify code here, make sure to check whether hmR0VmxCallRing3Callback() needs to be updated too.
7253 */
7254
7255 /* Deregister hook now that we've left HM context before re-enabling preemption. */
7256 /** @todo Deregistering here means we need to VMCLEAR always
7257 * (longjmp/exit-to-r3) in VT-x which is not efficient, eliminate need
7258 * for calling VMMR0ThreadCtxHookDisable here! */
7259 VMMR0ThreadCtxHookDisable(pVCpu);
7260
7261 /* Leave HM context. This takes care of local init (term). */
7262 int rc = HMR0LeaveCpu(pVCpu);
7263
7264 HM_RESTORE_PREEMPT();
7265 return rc;
7266}
7267
7268
7269/**
7270 * Does the necessary state syncing before doing a longjmp to ring-3.
7271 *
7272 * @returns VBox status code.
7273 * @param pVCpu The cross context virtual CPU structure.
7274 *
7275 * @remarks No-long-jmp zone!!!
7276 */
7277DECLINLINE(int) hmR0VmxLongJmpToRing3(PVMCPU pVCpu)
7278{
7279 return hmR0VmxLeaveSession(pVCpu);
7280}
7281
7282
7283/**
7284 * Take necessary actions before going back to ring-3.
7285 *
7286 * An action requires us to go back to ring-3. This function does the necessary
7287 * steps before we can safely return to ring-3. This is not the same as longjmps
7288 * to ring-3, this is voluntary and prepares the guest so it may continue
7289 * executing outside HM (recompiler/IEM).
7290 *
7291 * @returns VBox status code.
7292 * @param pVCpu The cross context virtual CPU structure.
7293 * @param rcExit The reason for exiting to ring-3. Can be
7294 * VINF_VMM_UNKNOWN_RING3_CALL.
7295 */
7296static int hmR0VmxExitToRing3(PVMCPU pVCpu, VBOXSTRICTRC rcExit)
7297{
7298 Assert(pVCpu);
7299 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
7300
7301 if (RT_UNLIKELY(rcExit == VERR_VMX_INVALID_VMCS_PTR))
7302 {
7303 VMXGetActivatedVmcs(&pVCpu->hm.s.vmx.LastError.u64VMCSPhys);
7304 pVCpu->hm.s.vmx.LastError.u32VMCSRevision = *(uint32_t *)pVCpu->hm.s.vmx.pvVmcs;
7305 pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hm.s.idEnteredCpu;
7306 /* LastError.idCurrentCpu was updated in hmR0VmxPreRunGuestCommitted(). */
7307 }
7308
7309 /* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
7310 VMMRZCallRing3Disable(pVCpu);
7311 Log4Func(("rcExit=%d\n", VBOXSTRICTRC_VAL(rcExit)));
7312
7313 /* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
7314 if (pVCpu->hm.s.Event.fPending)
7315 {
7316 hmR0VmxPendingEventToTrpmTrap(pVCpu);
7317 Assert(!pVCpu->hm.s.Event.fPending);
7318 }
7319
7320 /* Clear interrupt-window and NMI-window controls as we re-evaluate it when we return from ring-3. */
7321 hmR0VmxClearIntNmiWindowsVmcs(pVCpu);
7322
7323 /* If we're emulating an instruction, we shouldn't have any TRPM traps pending
7324 and if we're injecting an event we should have a TRPM trap pending. */
7325 AssertMsg(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT || TRPMHasTrap(pVCpu), ("%Rrc\n", VBOXSTRICTRC_VAL(rcExit)));
7326#ifndef DEBUG_bird /* Triggered after firing an NMI against NT4SP1, possibly a triple fault in progress. */
7327 AssertMsg(rcExit != VINF_EM_RAW_EMULATE_INSTR || !TRPMHasTrap(pVCpu), ("%Rrc\n", VBOXSTRICTRC_VAL(rcExit)));
7328#endif
7329
7330 /* Save guest state and restore host state bits. */
7331 int rc = hmR0VmxLeaveSession(pVCpu);
7332 AssertRCReturn(rc, rc);
7333 STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
7334 /* Thread-context hooks are unregistered at this point!!! */
7335
7336 /* Sync recompiler state. */
7337 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
7338 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
7339 | CPUM_CHANGED_LDTR
7340 | CPUM_CHANGED_GDTR
7341 | CPUM_CHANGED_IDTR
7342 | CPUM_CHANGED_TR
7343 | CPUM_CHANGED_HIDDEN_SEL_REGS);
7344 if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
7345 && CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx))
7346 {
7347 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
7348 }
7349
7350 Assert(!pVCpu->hm.s.fClearTrapFlag);
7351
7352 /* Update the exit-to-ring 3 reason. */
7353 pVCpu->hm.s.rcLastExitToR3 = VBOXSTRICTRC_VAL(rcExit);
7354
7355 /* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
7356 if (rcExit != VINF_EM_RAW_INTERRUPT)
7357 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7358
7359 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
7360
7361 /* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
7362 VMMRZCallRing3RemoveNotification(pVCpu);
7363 VMMRZCallRing3Enable(pVCpu);
7364
7365 return rc;
7366}
7367
7368
7369/**
7370 * VMMRZCallRing3() callback wrapper which saves the guest state before we
7371 * longjump to ring-3 and possibly get preempted.
7372 *
7373 * @returns VBox status code.
7374 * @param pVCpu The cross context virtual CPU structure.
7375 * @param enmOperation The operation causing the ring-3 longjump.
7376 * @param pvUser User argument, currently unused, NULL.
7377 */
7378static DECLCALLBACK(int) hmR0VmxCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
7379{
7380 RT_NOREF(pvUser);
7381 if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
7382 {
7383 /*
7384 * !!! IMPORTANT !!!
7385 * If you modify code here, check whether hmR0VmxLeave() and hmR0VmxLeaveSession() needs to be updated too.
7386 * This is a stripped down version which gets out ASAP, trying to not trigger any further assertions.
7387 */
7388 VMMRZCallRing3RemoveNotification(pVCpu);
7389 VMMRZCallRing3Disable(pVCpu);
7390 RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
7391 RTThreadPreemptDisable(&PreemptState);
7392
7393 hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
7394 CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
7395 CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, true /* save DR6 */);
7396
7397#if HC_ARCH_BITS == 64
7398 /* Restore host-state bits that VT-x only restores partially. */
7399 if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
7400 && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
7401 VMXRestoreHostState(pVCpu->hm.s.vmx.fRestoreHostFlags, &pVCpu->hm.s.vmx.RestoreHost);
7402 pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
7403#endif
7404
7405 /* Restore the lazy host MSRs as we're leaving VT-x context. */
7406 if (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
7407 hmR0VmxLazyRestoreHostMsrs(pVCpu);
7408
7409 /* Update auto-load/store host MSRs values when we re-enter VT-x (as we could be on a different CPU). */
7410 pVCpu->hm.s.vmx.fUpdatedHostMsrs = false;
7411 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
7412 if (pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_ACTIVE)
7413 {
7414 VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
7415 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
7416 }
7417
7418 /** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
7419 VMMR0ThreadCtxHookDisable(pVCpu);
7420 HMR0LeaveCpu(pVCpu);
7421 RTThreadPreemptRestore(&PreemptState);
7422 return VINF_SUCCESS;
7423 }
7424
7425 Assert(pVCpu);
7426 Assert(pvUser);
7427 Assert(VMMRZCallRing3IsEnabled(pVCpu));
7428 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
7429
7430 VMMRZCallRing3Disable(pVCpu);
7431 Assert(VMMR0IsLogFlushDisabled(pVCpu));
7432
7433 Log4Func((" -> hmR0VmxLongJmpToRing3 enmOperation=%d\n", enmOperation));
7434
7435 int rc = hmR0VmxLongJmpToRing3(pVCpu);
7436 AssertRCReturn(rc, rc);
7437
7438 VMMRZCallRing3Enable(pVCpu);
7439 return VINF_SUCCESS;
7440}
7441
7442
7443/**
7444 * Sets the interrupt-window exiting control in the VMCS which instructs VT-x to
7445 * cause a VM-exit as soon as the guest is in a state to receive interrupts.
7446 *
7447 * @param pVCpu The cross context virtual CPU structure.
7448 */
7449DECLINLINE(void) hmR0VmxSetIntWindowExitVmcs(PVMCPU pVCpu)
7450{
7451 if (RT_LIKELY(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_INT_WINDOW_EXIT))
7452 {
7453 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
7454 {
7455 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_PROC_CTLS_INT_WINDOW_EXIT;
7456 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
7457 AssertRC(rc);
7458 Log4Func(("Setup interrupt-window exiting\n"));
7459 }
7460 } /* else we will deliver interrupts whenever the guest exits next and is in a state to receive events. */
7461}
7462
7463
7464/**
7465 * Clears the interrupt-window exiting control in the VMCS.
7466 *
7467 * @param pVCpu The cross context virtual CPU structure.
7468 */
7469DECLINLINE(void) hmR0VmxClearIntWindowExitVmcs(PVMCPU pVCpu)
7470{
7471 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
7472 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_PROC_CTLS_INT_WINDOW_EXIT;
7473 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
7474 AssertRC(rc);
7475 Log4Func(("Cleared interrupt-window exiting\n"));
7476}
7477
7478
7479/**
7480 * Sets the NMI-window exiting control in the VMCS which instructs VT-x to
7481 * cause a VM-exit as soon as the guest is in a state to receive NMIs.
7482 *
7483 * @param pVCpu The cross context virtual CPU structure.
7484 */
7485DECLINLINE(void) hmR0VmxSetNmiWindowExitVmcs(PVMCPU pVCpu)
7486{
7487 if (RT_LIKELY(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
7488 {
7489 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
7490 {
7491 pVCpu->hm.s.vmx.u32ProcCtls |= VMX_PROC_CTLS_NMI_WINDOW_EXIT;
7492 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
7493 AssertRC(rc);
7494 Log4Func(("Setup NMI-window exiting\n"));
7495 }
7496 } /* else we will deliver NMIs whenever we VM-exit next, even possibly nesting NMIs. Can't be helped on ancient CPUs. */
7497}
7498
7499
7500/**
7501 * Clears the NMI-window exiting control in the VMCS.
7502 *
7503 * @param pVCpu The cross context virtual CPU structure.
7504 */
7505DECLINLINE(void) hmR0VmxClearNmiWindowExitVmcs(PVMCPU pVCpu)
7506{
7507 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
7508 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_PROC_CTLS_NMI_WINDOW_EXIT;
7509 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
7510 AssertRC(rc);
7511 Log4Func(("Cleared NMI-window exiting\n"));
7512}
7513
7514
7515/**
7516 * Evaluates the event to be delivered to the guest and sets it as the pending
7517 * event.
7518 *
7519 * @returns The VT-x guest-interruptibility state.
7520 * @param pVCpu The cross context virtual CPU structure.
7521 */
7522static uint32_t hmR0VmxEvaluatePendingEvent(PVMCPU pVCpu)
7523{
7524 /* Get the current interruptibility-state of the guest and then figure out what can be injected. */
7525 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7526 uint32_t const fIntrState = hmR0VmxGetGuestIntrState(pVCpu);
7527 bool const fBlockMovSS = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS);
7528 bool const fBlockSti = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI);
7529 bool const fBlockNmi = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI);
7530
7531 Assert(!fBlockSti || !(ASMAtomicUoReadU64(&pCtx->fExtrn) & CPUMCTX_EXTRN_RFLAGS));
7532 Assert(!(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI)); /* We don't support block-by-SMI yet.*/
7533 Assert(!fBlockSti || pCtx->eflags.Bits.u1IF); /* Cannot set block-by-STI when interrupts are disabled. */
7534 Assert(!TRPMHasTrap(pVCpu));
7535
7536 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
7537 APICUpdatePendingInterrupts(pVCpu);
7538
7539 /*
7540 * Toggling of interrupt force-flags here is safe since we update TRPM on premature exits
7541 * to ring-3 before executing guest code, see hmR0VmxExitToRing3(). We must NOT restore these force-flags.
7542 */
7543 /** @todo SMI. SMIs take priority over NMIs. */
7544 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts. */
7545 {
7546 /* On some CPUs block-by-STI also blocks NMIs. See Intel spec. 26.3.1.5 "Checks On Guest Non-Register State". */
7547 if ( !pVCpu->hm.s.Event.fPending
7548 && !fBlockNmi
7549 && !fBlockSti
7550 && !fBlockMovSS)
7551 {
7552 Log4Func(("Pending NMI\n"));
7553 uint32_t u32IntInfo = X86_XCPT_NMI | VMX_EXIT_INT_INFO_VALID;
7554 u32IntInfo |= (VMX_EXIT_INT_INFO_TYPE_NMI << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7555
7556 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */);
7557 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
7558 }
7559 else
7560 hmR0VmxSetNmiWindowExitVmcs(pVCpu);
7561 }
7562 /*
7563 * Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt() returns
7564 * a valid interrupt we must- deliver the interrupt. We can no longer re-request it from the APIC.
7565 */
7566 else if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)
7567 && !pVCpu->hm.s.fSingleInstruction)
7568 {
7569 Assert(!DBGFIsStepping(pVCpu));
7570 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_RFLAGS);
7571 AssertRCReturn(rc, 0);
7572 bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
7573 if ( !pVCpu->hm.s.Event.fPending
7574 && !fBlockInt
7575 && !fBlockSti
7576 && !fBlockMovSS)
7577 {
7578 uint8_t u8Interrupt;
7579 rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
7580 if (RT_SUCCESS(rc))
7581 {
7582 Log4Func(("Pending external interrupt u8Interrupt=%#x\n", u8Interrupt));
7583 uint32_t u32IntInfo = u8Interrupt
7584 | VMX_EXIT_INT_INFO_VALID
7585 | (VMX_EXIT_INT_INFO_TYPE_EXT_INT << VMX_EXIT_INT_INFO_TYPE_SHIFT);
7586
7587 hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrfaultAddress */);
7588 }
7589 else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
7590 {
7591 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
7592 hmR0VmxApicSetTprThreshold(pVCpu, u8Interrupt >> 4);
7593 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
7594
7595 /*
7596 * If the CPU doesn't have TPR shadowing, we will always get a VM-exit on TPR changes and
7597 * APICSetTpr() will end up setting the VMCPU_FF_INTERRUPT_APIC if required, so there is no
7598 * need to re-set this force-flag here.
7599 */
7600 }
7601 else
7602 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
7603 }
7604 else
7605 hmR0VmxSetIntWindowExitVmcs(pVCpu);
7606 }
7607
7608 return fIntrState;
7609}
7610
7611
7612/**
7613 * Injects any pending events into the guest if the guest is in a state to
7614 * receive them.
7615 *
7616 * @returns Strict VBox status code (i.e. informational status codes too).
7617 * @param pVCpu The cross context virtual CPU structure.
7618 * @param fIntrState The VT-x guest-interruptibility state.
7619 * @param fStepping Running in hmR0VmxRunGuestCodeStep() and we should
7620 * return VINF_EM_DBG_STEPPED if the event was
7621 * dispatched directly.
7622 */
7623static VBOXSTRICTRC hmR0VmxInjectPendingEvent(PVMCPU pVCpu, uint32_t fIntrState, bool fStepping)
7624{
7625 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
7626 Assert(VMMRZCallRing3IsEnabled(pVCpu));
7627
7628 bool const fBlockMovSS = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS);
7629 bool const fBlockSti = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI);
7630
7631 Assert(!fBlockSti || !(ASMAtomicUoReadU64(&pVCpu->cpum.GstCtx.fExtrn) & CPUMCTX_EXTRN_RFLAGS));
7632 Assert(!(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI)); /* We don't support block-by-SMI yet.*/
7633 Assert(!fBlockSti || pVCpu->cpum.GstCtx.eflags.Bits.u1IF); /* Cannot set block-by-STI when interrupts are disabled. */
7634 Assert(!TRPMHasTrap(pVCpu));
7635
7636 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
7637 if (pVCpu->hm.s.Event.fPending)
7638 {
7639 /*
7640 * Do -not- clear any interrupt-window exiting control here. We might have an interrupt
7641 * pending even while injecting an event and in this case, we want a VM-exit as soon as
7642 * the guest is ready for the next interrupt, see @bugref{6208#c45}.
7643 *
7644 * See Intel spec. 26.6.5 "Interrupt-Window Exiting and Virtual-Interrupt Delivery".
7645 */
7646 uint32_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVCpu->hm.s.Event.u64IntInfo);
7647#ifdef VBOX_STRICT
7648 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
7649 {
7650 bool const fBlockInt = !(pVCpu->cpum.GstCtx.eflags.u32 & X86_EFL_IF);
7651 Assert(!fBlockInt);
7652 Assert(!fBlockSti);
7653 Assert(!fBlockMovSS);
7654 }
7655 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI)
7656 {
7657 bool const fBlockNmi = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI);
7658 Assert(!fBlockSti);
7659 Assert(!fBlockMovSS);
7660 Assert(!fBlockNmi);
7661 }
7662#endif
7663 Log4(("Injecting pending event vcpu[%RU32] u64IntInfo=%#RX64 Type=%#RX32\n", pVCpu->idCpu, pVCpu->hm.s.Event.u64IntInfo,
7664 uIntType));
7665
7666 /*
7667 * Inject the event and get any changes to the guest-interruptibility state.
7668 *
7669 * The guest-interruptibility state may need to be updated if we inject the event
7670 * into the guest IDT ourselves (for real-on-v86 guest injecting software interrupts).
7671 */
7672 rcStrict = hmR0VmxInjectEventVmcs(pVCpu, pVCpu->hm.s.Event.u64IntInfo, pVCpu->hm.s.Event.cbInstr,
7673 pVCpu->hm.s.Event.u32ErrCode, pVCpu->hm.s.Event.GCPtrFaultAddress, fStepping,
7674 &fIntrState);
7675 AssertRCReturn(VBOXSTRICTRC_VAL(rcStrict), rcStrict);
7676
7677 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT)
7678 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
7679 else
7680 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
7681 }
7682
7683 /*
7684 * Update the guest-interruptibility state.
7685 *
7686 * This is required for the real-on-v86 software interrupt injection case above, as well as
7687 * updates to the guest state from ring-3 or IEM/REM.
7688 */
7689 int rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_INT_STATE, fIntrState);
7690 AssertRCReturn(rc, rc);
7691
7692 /*
7693 * There's no need to clear the VM-entry interruption-information field here if we're not
7694 * injecting anything. VT-x clears the valid bit on every VM-exit.
7695 *
7696 * See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7697 */
7698
7699 Assert(rcStrict == VINF_SUCCESS || rcStrict == VINF_EM_RESET || (rcStrict == VINF_EM_DBG_STEPPED && fStepping));
7700 NOREF(fBlockMovSS); NOREF(fBlockSti);
7701 return rcStrict;
7702}
7703
7704
7705/**
7706 * Injects a double-fault (\#DF) exception into the VM.
7707 *
7708 * @returns Strict VBox status code (i.e. informational status codes too).
7709 * @param pVCpu The cross context virtual CPU structure.
7710 * @param fStepping Whether we're running in hmR0VmxRunGuestCodeStep()
7711 * and should return VINF_EM_DBG_STEPPED if the event
7712 * is injected directly (register modified by us, not
7713 * by hardware on VM-entry).
7714 * @param pfIntrState Pointer to the current guest interruptibility-state.
7715 * This interruptibility-state will be updated if
7716 * necessary. This cannot not be NULL.
7717 */
7718DECLINLINE(VBOXSTRICTRC) hmR0VmxInjectXcptDF(PVMCPU pVCpu, bool fStepping, uint32_t *pfIntrState)
7719{
7720 uint32_t const u32IntInfo = X86_XCPT_DF | VMX_EXIT_INT_INFO_VALID
7721 | (VMX_EXIT_INT_INFO_TYPE_HW_XCPT << VMX_EXIT_INT_INFO_TYPE_SHIFT)
7722 | VMX_EXIT_INT_INFO_ERROR_CODE_VALID;
7723 return hmR0VmxInjectEventVmcs(pVCpu, u32IntInfo, 0 /* cbInstr */, 0 /* u32ErrCode */, 0 /* GCPtrFaultAddress */, fStepping,
7724 pfIntrState);
7725}
7726
7727
7728/**
7729 * Injects a general-protection (\#GP) fault into the VM.
7730 *
7731 * @returns Strict VBox status code (i.e. informational status codes too).
7732 * @param pVCpu The cross context virtual CPU structure.
7733 * @param fErrorCodeValid Whether the error code is valid (depends on the CPU
7734 * mode, i.e. in real-mode it's not valid).
7735 * @param u32ErrorCode The error code associated with the \#GP.
7736 * @param fStepping Whether we're running in
7737 * hmR0VmxRunGuestCodeStep() and should return
7738 * VINF_EM_DBG_STEPPED if the event is injected
7739 * directly (register modified by us, not by
7740 * hardware on VM-entry).
7741 * @param pfIntrState Pointer to the current guest interruptibility-state.
7742 * This interruptibility-state will be updated if
7743 * necessary. This cannot not be NULL.
7744 */
7745DECLINLINE(VBOXSTRICTRC) hmR0VmxInjectXcptGP(PVMCPU pVCpu, bool fErrorCodeValid, uint32_t u32ErrorCode, bool fStepping,
7746 uint32_t *pfIntrState)
7747{
7748 uint32_t const u32IntInfo = X86_XCPT_GP | VMX_EXIT_INT_INFO_VALID
7749 | (VMX_EXIT_INT_INFO_TYPE_HW_XCPT << VMX_EXIT_INT_INFO_TYPE_SHIFT)
7750 | (fErrorCodeValid ? VMX_EXIT_INT_INFO_ERROR_CODE_VALID : 0);
7751 return hmR0VmxInjectEventVmcs(pVCpu, u32IntInfo, 0 /* cbInstr */, u32ErrorCode, 0 /* GCPtrFaultAddress */, fStepping,
7752 pfIntrState);
7753}
7754
7755
7756/**
7757 * Pushes a 2-byte value onto the real-mode (in virtual-8086 mode) guest's
7758 * stack.
7759 *
7760 * @returns Strict VBox status code (i.e. informational status codes too).
7761 * @retval VINF_EM_RESET if pushing a value to the stack caused a triple-fault.
7762 * @param pVCpu The cross context virtual CPU structure.
7763 * @param uValue The value to push to the guest stack.
7764 */
7765static VBOXSTRICTRC hmR0VmxRealModeGuestStackPush(PVMCPU pVCpu, uint16_t uValue)
7766{
7767 /*
7768 * The stack limit is 0xffff in real-on-virtual 8086 mode. Real-mode with weird stack limits cannot be run in
7769 * virtual 8086 mode in VT-x. See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
7770 * See Intel Instruction reference for PUSH and Intel spec. 22.33.1 "Segment Wraparound".
7771 */
7772 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7773 if (pCtx->sp == 1)
7774 return VINF_EM_RESET;
7775 pCtx->sp -= sizeof(uint16_t); /* May wrap around which is expected behaviour. */
7776 int rc = PGMPhysSimpleWriteGCPhys(pVCpu->CTX_SUFF(pVM), pCtx->ss.u64Base + pCtx->sp, &uValue, sizeof(uint16_t));
7777 AssertRC(rc);
7778 return rc;
7779}
7780
7781
7782/**
7783 * Injects an event into the guest upon VM-entry by updating the relevant fields
7784 * in the VM-entry area in the VMCS.
7785 *
7786 * @returns Strict VBox status code (i.e. informational status codes too).
7787 * @retval VINF_SUCCESS if the event is successfully injected into the VMCS.
7788 * @retval VINF_EM_RESET if event injection resulted in a triple-fault.
7789 *
7790 * @param pVCpu The cross context virtual CPU structure.
7791 * @param u64IntInfo The VM-entry interruption-information field.
7792 * @param cbInstr The VM-entry instruction length in bytes (for
7793 * software interrupts, exceptions and privileged
7794 * software exceptions).
7795 * @param u32ErrCode The VM-entry exception error code.
7796 * @param GCPtrFaultAddress The page-fault address for \#PF exceptions.
7797 * @param pfIntrState Pointer to the current guest interruptibility-state.
7798 * This interruptibility-state will be updated if
7799 * necessary. This cannot not be NULL.
7800 * @param fStepping Whether we're running in
7801 * hmR0VmxRunGuestCodeStep() and should return
7802 * VINF_EM_DBG_STEPPED if the event is injected
7803 * directly (register modified by us, not by
7804 * hardware on VM-entry).
7805 */
7806static VBOXSTRICTRC hmR0VmxInjectEventVmcs(PVMCPU pVCpu, uint64_t u64IntInfo, uint32_t cbInstr, uint32_t u32ErrCode,
7807 RTGCUINTREG GCPtrFaultAddress, bool fStepping, uint32_t *pfIntrState)
7808{
7809 /* Intel spec. 24.8.3 "VM-Entry Controls for Event Injection" specifies the interruption-information field to be 32-bits. */
7810 AssertMsg(!RT_HI_U32(u64IntInfo), ("%#RX64\n", u64IntInfo));
7811 Assert(pfIntrState);
7812
7813 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7814 uint32_t u32IntInfo = (uint32_t)u64IntInfo;
7815 uint32_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(u32IntInfo);
7816 uint32_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(u32IntInfo);
7817
7818#ifdef VBOX_STRICT
7819 /*
7820 * Validate the error-code-valid bit for hardware exceptions.
7821 * No error codes for exceptions in real-mode.
7822 *
7823 * See Intel spec. 20.1.4 "Interrupt and Exception Handling"
7824 */
7825 if ( uIntType == VMX_EXIT_INT_INFO_TYPE_HW_XCPT
7826 && !CPUMIsGuestInRealModeEx(pCtx))
7827 {
7828 switch (uVector)
7829 {
7830 case X86_XCPT_PF:
7831 case X86_XCPT_DF:
7832 case X86_XCPT_TS:
7833 case X86_XCPT_NP:
7834 case X86_XCPT_SS:
7835 case X86_XCPT_GP:
7836 case X86_XCPT_AC:
7837 AssertMsg(VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(u32IntInfo),
7838 ("Error-code-valid bit not set for exception that has an error code uVector=%#x\n", uVector));
7839 RT_FALL_THRU();
7840 default:
7841 break;
7842 }
7843 }
7844#endif
7845
7846 /* Cannot inject an NMI when block-by-MOV SS is in effect. */
7847 Assert( uIntType != VMX_EXIT_INT_INFO_TYPE_NMI
7848 || !(*pfIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS));
7849
7850 STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[uVector & MASK_INJECT_IRQ_STAT]);
7851
7852 /*
7853 * Hardware interrupts & exceptions cannot be delivered through the software interrupt
7854 * redirection bitmap to the real mode task in virtual-8086 mode. We must jump to the
7855 * interrupt handler in the (real-mode) guest.
7856 *
7857 * See Intel spec. 20.3 "Interrupt and Exception handling in Virtual-8086 Mode".
7858 * See Intel spec. 20.1.4 "Interrupt and Exception Handling" for real-mode interrupt handling.
7859 */
7860 if (CPUMIsGuestInRealModeEx(pCtx)) /* CR0.PE bit changes are always intercepted, so it's up to date. */
7861 {
7862 if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fUnrestrictedGuest)
7863 {
7864 /*
7865 * For unrestricted execution enabled CPUs running real-mode guests, we must not
7866 * set the deliver-error-code bit.
7867 *
7868 * See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
7869 */
7870 u32IntInfo &= ~VMX_ENTRY_INT_INFO_ERROR_CODE_VALID;
7871 }
7872 else
7873 {
7874 PVM pVM = pVCpu->CTX_SUFF(pVM);
7875 Assert(PDMVmmDevHeapIsEnabled(pVM));
7876 Assert(pVM->hm.s.vmx.pRealModeTSS);
7877
7878 /* We require RIP, RSP, RFLAGS, CS, IDTR, import them. */
7879 int rc2 = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_TABLE_MASK | CPUMCTX_EXTRN_RIP
7880 | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_RFLAGS);
7881 AssertRCReturn(rc2, rc2);
7882
7883 /* Check if the interrupt handler is present in the IVT (real-mode IDT). IDT limit is (4N - 1). */
7884 size_t const cbIdtEntry = sizeof(X86IDTR16);
7885 if (uVector * cbIdtEntry + (cbIdtEntry - 1) > pCtx->idtr.cbIdt)
7886 {
7887 /* If we are trying to inject a #DF with no valid IDT entry, return a triple-fault. */
7888 if (uVector == X86_XCPT_DF)
7889 return VINF_EM_RESET;
7890
7891 /* If we're injecting a #GP with no valid IDT entry, inject a double-fault. */
7892 if (uVector == X86_XCPT_GP)
7893 return hmR0VmxInjectXcptDF(pVCpu, fStepping, pfIntrState);
7894
7895 /*
7896 * If we're injecting an event with no valid IDT entry, inject a #GP.
7897 * No error codes for exceptions in real-mode.
7898 *
7899 * See Intel spec. 20.1.4 "Interrupt and Exception Handling"
7900 */
7901 return hmR0VmxInjectXcptGP(pVCpu, false /* fErrCodeValid */, 0 /* u32ErrCode */, fStepping, pfIntrState);
7902 }
7903
7904 /* Software exceptions (#BP and #OF exceptions thrown as a result of INT3 or INTO) */
7905 uint16_t uGuestIp = pCtx->ip;
7906 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_SW_XCPT)
7907 {
7908 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF);
7909 /* #BP and #OF are both benign traps, we need to resume the next instruction. */
7910 uGuestIp = pCtx->ip + (uint16_t)cbInstr;
7911 }
7912 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_SW_INT)
7913 uGuestIp = pCtx->ip + (uint16_t)cbInstr;
7914
7915 /* Get the code segment selector and offset from the IDT entry for the interrupt handler. */
7916 X86IDTR16 IdtEntry;
7917 RTGCPHYS GCPhysIdtEntry = (RTGCPHYS)pCtx->idtr.pIdt + uVector * cbIdtEntry;
7918 rc2 = PGMPhysSimpleReadGCPhys(pVM, &IdtEntry, GCPhysIdtEntry, cbIdtEntry);
7919 AssertRCReturn(rc2, rc2);
7920
7921 /* Construct the stack frame for the interrupt/exception handler. */
7922 VBOXSTRICTRC rcStrict;
7923 rcStrict = hmR0VmxRealModeGuestStackPush(pVCpu, pCtx->eflags.u32);
7924 if (rcStrict == VINF_SUCCESS)
7925 rcStrict = hmR0VmxRealModeGuestStackPush(pVCpu, pCtx->cs.Sel);
7926 if (rcStrict == VINF_SUCCESS)
7927 rcStrict = hmR0VmxRealModeGuestStackPush(pVCpu, uGuestIp);
7928
7929 /* Clear the required eflag bits and jump to the interrupt/exception handler. */
7930 if (rcStrict == VINF_SUCCESS)
7931 {
7932 pCtx->eflags.u32 &= ~(X86_EFL_IF | X86_EFL_TF | X86_EFL_RF | X86_EFL_AC);
7933 pCtx->rip = IdtEntry.offSel;
7934 pCtx->cs.Sel = IdtEntry.uSel;
7935 pCtx->cs.ValidSel = IdtEntry.uSel;
7936 pCtx->cs.u64Base = IdtEntry.uSel << cbIdtEntry;
7937 if ( uIntType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
7938 && uVector == X86_XCPT_PF)
7939 pCtx->cr2 = GCPtrFaultAddress;
7940
7941 /* If any other guest-state bits are changed here, make sure to update
7942 hmR0VmxPreRunGuestCommitted() when thread-context hooks are used. */
7943 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CS | HM_CHANGED_GUEST_CR2
7944 | HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS
7945 | HM_CHANGED_GUEST_RSP);
7946
7947 /* We're clearing interrupts, which means no block-by-STI interrupt-inhibition. */
7948 if (*pfIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
7949 {
7950 Assert( uIntType != VMX_ENTRY_INT_INFO_TYPE_NMI
7951 && uIntType != VMX_ENTRY_INT_INFO_TYPE_EXT_INT);
7952 Log4Func(("Clearing inhibition due to STI\n"));
7953 *pfIntrState &= ~VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
7954 }
7955 Log4(("Injecting real-mode: u32IntInfo=%#x u32ErrCode=%#x cbInstr=%#x Eflags=%#x CS:EIP=%04x:%04x\n",
7956 u32IntInfo, u32ErrCode, cbInstr, pCtx->eflags.u, pCtx->cs.Sel, pCtx->eip));
7957
7958 /* The event has been truly dispatched. Mark it as no longer pending so we don't attempt to 'undo'
7959 it, if we are returning to ring-3 before executing guest code. */
7960 pVCpu->hm.s.Event.fPending = false;
7961
7962 /* Make hmR0VmxPreRunGuest() return if we're stepping since we've changed cs:rip. */
7963 if (fStepping)
7964 rcStrict = VINF_EM_DBG_STEPPED;
7965 }
7966 AssertMsg(rcStrict == VINF_SUCCESS || rcStrict == VINF_EM_RESET || (rcStrict == VINF_EM_DBG_STEPPED && fStepping),
7967 ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7968 return rcStrict;
7969 }
7970 }
7971
7972 /* Validate. */
7973 Assert(VMX_ENTRY_INT_INFO_IS_VALID(u32IntInfo)); /* Bit 31 (Valid bit) must be set by caller. */
7974 Assert(!(u32IntInfo & VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK)); /* Bits 30:12 MBZ. */
7975
7976 /* Inject. */
7977 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, u32IntInfo);
7978 if (VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(u32IntInfo))
7979 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, u32ErrCode);
7980 rc |= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
7981 AssertRCReturn(rc, rc);
7982
7983 /* Update CR2. */
7984 if ( VMX_ENTRY_INT_INFO_TYPE(u32IntInfo) == VMX_EXIT_INT_INFO_TYPE_HW_XCPT
7985 && uVector == X86_XCPT_PF)
7986 pCtx->cr2 = GCPtrFaultAddress;
7987
7988 Log4(("Injecting u32IntInfo=%#x u32ErrCode=%#x cbInstr=%#x CR2=%#RX64\n", u32IntInfo, u32ErrCode, cbInstr, pCtx->cr2));
7989
7990 return VINF_SUCCESS;
7991}
7992
7993
7994/**
7995 * Clears the interrupt-window exiting control in the VMCS and if necessary
7996 * clears the current event in the VMCS as well.
7997 *
7998 * @returns VBox status code.
7999 * @param pVCpu The cross context virtual CPU structure.
8000 *
8001 * @remarks Use this function only to clear events that have not yet been
8002 * delivered to the guest but are injected in the VMCS!
8003 * @remarks No-long-jump zone!!!
8004 */
8005static void hmR0VmxClearIntNmiWindowsVmcs(PVMCPU pVCpu)
8006{
8007 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
8008 {
8009 hmR0VmxClearIntWindowExitVmcs(pVCpu);
8010 Log4Func(("Cleared interrupt window\n"));
8011 }
8012
8013 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
8014 {
8015 hmR0VmxClearNmiWindowExitVmcs(pVCpu);
8016 Log4Func(("Cleared NMI window\n"));
8017 }
8018}
8019
8020
8021/**
8022 * Enters the VT-x session.
8023 *
8024 * @returns VBox status code.
8025 * @param pVCpu The cross context virtual CPU structure.
8026 * @param pHostCpu Pointer to the global CPU info struct.
8027 */
8028VMMR0DECL(int) VMXR0Enter(PVMCPU pVCpu, PHMGLOBALCPUINFO pHostCpu)
8029{
8030 AssertPtr(pVCpu);
8031 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported);
8032 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8033 RT_NOREF(pHostCpu);
8034
8035 LogFlowFunc(("pVCpu=%p\n", pVCpu));
8036 Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
8037 == (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
8038
8039#ifdef VBOX_STRICT
8040 /* At least verify VMX is enabled, since we can't check if we're in VMX root mode without #GP'ing. */
8041 RTCCUINTREG uHostCR4 = ASMGetCR4();
8042 if (!(uHostCR4 & X86_CR4_VMXE))
8043 {
8044 LogRelFunc(("X86_CR4_VMXE bit in CR4 is not set!\n"));
8045 return VERR_VMX_X86_CR4_VMXE_CLEARED;
8046 }
8047#endif
8048
8049 /*
8050 * Load the VCPU's VMCS as the current (and active) one.
8051 */
8052 Assert(pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_CLEAR);
8053 int rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
8054 if (RT_FAILURE(rc))
8055 return rc;
8056
8057 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_ACTIVE;
8058 pVCpu->hm.s.fLeaveDone = false;
8059 Log4Func(("Activated Vmcs. HostCpuId=%u\n", RTMpCpuId()));
8060
8061 return VINF_SUCCESS;
8062}
8063
8064
8065/**
8066 * The thread-context callback (only on platforms which support it).
8067 *
8068 * @param enmEvent The thread-context event.
8069 * @param pVCpu The cross context virtual CPU structure.
8070 * @param fGlobalInit Whether global VT-x/AMD-V init. was used.
8071 * @thread EMT(pVCpu)
8072 */
8073VMMR0DECL(void) VMXR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
8074{
8075 NOREF(fGlobalInit);
8076
8077 switch (enmEvent)
8078 {
8079 case RTTHREADCTXEVENT_OUT:
8080 {
8081 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8082 Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
8083 VMCPU_ASSERT_EMT(pVCpu);
8084
8085 /* No longjmps (logger flushes, locks) in this fragile context. */
8086 VMMRZCallRing3Disable(pVCpu);
8087 Log4Func(("Preempting: HostCpuId=%u\n", RTMpCpuId()));
8088
8089 /*
8090 * Restore host-state (FPU, debug etc.)
8091 */
8092 if (!pVCpu->hm.s.fLeaveDone)
8093 {
8094 /*
8095 * Do -not- import the guest-state here as we might already be in the middle of importing
8096 * it, esp. bad if we're holding the PGM lock, see comment in hmR0VmxImportGuestState().
8097 */
8098 hmR0VmxLeave(pVCpu, false /* fImportState */);
8099 pVCpu->hm.s.fLeaveDone = true;
8100 }
8101
8102 /* Leave HM context, takes care of local init (term). */
8103 int rc = HMR0LeaveCpu(pVCpu);
8104 AssertRC(rc); NOREF(rc);
8105
8106 /* Restore longjmp state. */
8107 VMMRZCallRing3Enable(pVCpu);
8108 STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
8109 break;
8110 }
8111
8112 case RTTHREADCTXEVENT_IN:
8113 {
8114 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8115 Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
8116 VMCPU_ASSERT_EMT(pVCpu);
8117
8118 /* No longjmps here, as we don't want to trigger preemption (& its hook) while resuming. */
8119 VMMRZCallRing3Disable(pVCpu);
8120 Log4Func(("Resumed: HostCpuId=%u\n", RTMpCpuId()));
8121
8122 /* Initialize the bare minimum state required for HM. This takes care of
8123 initializing VT-x if necessary (onlined CPUs, local init etc.) */
8124 int rc = hmR0EnterCpu(pVCpu);
8125 AssertRC(rc);
8126 Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
8127 == (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
8128
8129 /* Load the active VMCS as the current one. */
8130 if (pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_CLEAR)
8131 {
8132 rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
8133 AssertRC(rc); NOREF(rc);
8134 pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_ACTIVE;
8135 Log4Func(("Resumed: Activated Vmcs. HostCpuId=%u\n", RTMpCpuId()));
8136 }
8137 pVCpu->hm.s.fLeaveDone = false;
8138
8139 /* Restore longjmp state. */
8140 VMMRZCallRing3Enable(pVCpu);
8141 break;
8142 }
8143
8144 default:
8145 break;
8146 }
8147}
8148
8149
8150/**
8151 * Exports the host state into the VMCS host-state area.
8152 * Sets up the VM-exit MSR-load area.
8153 *
8154 * The CPU state will be loaded from these fields on every successful VM-exit.
8155 *
8156 * @returns VBox status code.
8157 * @param pVCpu The cross context virtual CPU structure.
8158 *
8159 * @remarks No-long-jump zone!!!
8160 */
8161static int hmR0VmxExportHostState(PVMCPU pVCpu)
8162{
8163 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8164
8165 int rc = VINF_SUCCESS;
8166 if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_HOST_CONTEXT)
8167 {
8168 rc = hmR0VmxExportHostControlRegs();
8169 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8170
8171 rc = hmR0VmxExportHostSegmentRegs(pVCpu);
8172 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8173
8174 rc = hmR0VmxExportHostMsrs(pVCpu);
8175 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8176
8177 pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_HOST_CONTEXT;
8178 }
8179 return rc;
8180}
8181
8182
8183/**
8184 * Saves the host state in the VMCS host-state.
8185 *
8186 * @returns VBox status code.
8187 * @param pVCpu The cross context virtual CPU structure.
8188 *
8189 * @remarks No-long-jump zone!!!
8190 */
8191VMMR0DECL(int) VMXR0ExportHostState(PVMCPU pVCpu)
8192{
8193 AssertPtr(pVCpu);
8194 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8195
8196 /*
8197 * Export the host state here while entering HM context.
8198 * When thread-context hooks are used, we might get preempted and have to re-save the host
8199 * state but most of the time we won't be, so do it here before we disable interrupts.
8200 */
8201 return hmR0VmxExportHostState(pVCpu);
8202}
8203
8204
8205/**
8206 * Exports the guest state into the VMCS guest-state area.
8207 *
8208 * The will typically be done before VM-entry when the guest-CPU state and the
8209 * VMCS state may potentially be out of sync.
8210 *
8211 * Sets up the VM-entry MSR-load and VM-exit MSR-store areas. Sets up the
8212 * VM-entry controls.
8213 * Sets up the appropriate VMX non-root function to execute guest code based on
8214 * the guest CPU mode.
8215 *
8216 * @returns VBox strict status code.
8217 * @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
8218 * without unrestricted guest access and the VMMDev is not presently
8219 * mapped (e.g. EFI32).
8220 *
8221 * @param pVCpu The cross context virtual CPU structure.
8222 *
8223 * @remarks No-long-jump zone!!!
8224 */
8225static VBOXSTRICTRC hmR0VmxExportGuestState(PVMCPU pVCpu)
8226{
8227 AssertPtr(pVCpu);
8228 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
8229
8230 LogFlowFunc(("pVCpu=%p\n", pVCpu));
8231
8232 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExportGuestState, x);
8233
8234 /* Determine real-on-v86 mode. */
8235 pVCpu->hm.s.vmx.RealMode.fRealOnV86Active = false;
8236 if ( !pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fUnrestrictedGuest
8237 && CPUMIsGuestInRealModeEx(&pVCpu->cpum.GstCtx))
8238 pVCpu->hm.s.vmx.RealMode.fRealOnV86Active = true;
8239
8240 /*
8241 * Any ordering dependency among the sub-functions below must be explicitly stated using comments.
8242 * Ideally, assert that the cross-dependent bits are up-to-date at the point of using it.
8243 */
8244 int rc = hmR0VmxSelectVMRunHandler(pVCpu);
8245 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8246
8247 /* This needs to be done after hmR0VmxSelectVMRunHandler() as changing pfnStartVM may require VM-entry control updates. */
8248 rc = hmR0VmxExportGuestEntryCtls(pVCpu);
8249 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8250
8251 /* This needs to be done after hmR0VmxSelectVMRunHandler() as changing pfnStartVM may require VM-exit control updates. */
8252 rc = hmR0VmxExportGuestExitCtls(pVCpu);
8253 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8254
8255 rc = hmR0VmxExportGuestCR0(pVCpu);
8256 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8257
8258 VBOXSTRICTRC rcStrict = hmR0VmxExportGuestCR3AndCR4(pVCpu);
8259 if (rcStrict == VINF_SUCCESS)
8260 { /* likely */ }
8261 else
8262 {
8263 Assert(rcStrict == VINF_EM_RESCHEDULE_REM || RT_FAILURE_NP(rcStrict));
8264 return rcStrict;
8265 }
8266
8267 rc = hmR0VmxExportGuestSegmentRegs(pVCpu);
8268 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8269
8270 /* This needs to be done after hmR0VmxExportGuestEntryCtls() and hmR0VmxExportGuestExitCtls() as it
8271 may alter controls if we determine we don't have to swap EFER after all. */
8272 rc = hmR0VmxExportGuestMsrs(pVCpu);
8273 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8274
8275 rc = hmR0VmxExportGuestApicTpr(pVCpu);
8276 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8277
8278 rc = hmR0VmxExportGuestXcptIntercepts(pVCpu);
8279 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8280
8281 rc = hmR0VmxExportGuestRip(pVCpu);
8282 rc |= hmR0VmxExportGuestRsp(pVCpu);
8283 rc |= hmR0VmxExportGuestRflags(pVCpu);
8284 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
8285
8286 /* Clear any bits that may be set but exported unconditionally or unused/reserved bits. */
8287 ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~( (HM_CHANGED_GUEST_GPRS_MASK & ~HM_CHANGED_GUEST_RSP)
8288 | HM_CHANGED_GUEST_CR2
8289 | (HM_CHANGED_GUEST_DR_MASK & ~HM_CHANGED_GUEST_DR7)
8290 | HM_CHANGED_GUEST_X87
8291 | HM_CHANGED_GUEST_SSE_AVX
8292 | HM_CHANGED_GUEST_OTHER_XSAVE
8293 | HM_CHANGED_GUEST_XCRx
8294 | HM_CHANGED_GUEST_KERNEL_GS_BASE /* Part of lazy or auto load-store MSRs. */
8295 | HM_CHANGED_GUEST_SYSCALL_MSRS /* Part of lazy or auto load-store MSRs. */
8296 | HM_CHANGED_GUEST_TSC_AUX
8297 | HM_CHANGED_GUEST_OTHER_MSRS
8298 | HM_CHANGED_GUEST_HWVIRT
8299 | (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_VMX_MASK)));
8300
8301 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExportGuestState, x);
8302 return rc;
8303}
8304
8305
8306/**
8307 * Exports the state shared between the host and guest into the VMCS.
8308 *
8309 * @param pVCpu The cross context virtual CPU structure.
8310 *
8311 * @remarks No-long-jump zone!!!
8312 */
8313static void hmR0VmxExportSharedState(PVMCPU pVCpu)
8314{
8315 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8316 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8317
8318 if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DR_MASK)
8319 {
8320 int rc = hmR0VmxExportSharedDebugState(pVCpu);
8321 AssertRC(rc);
8322 pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_DR_MASK;
8323
8324 /* Loading shared debug bits might have changed eflags.TF bit for debugging purposes. */
8325 if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_RFLAGS)
8326 {
8327 rc = hmR0VmxExportGuestRflags(pVCpu);
8328 AssertRC(rc);
8329 }
8330 }
8331
8332 if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_VMX_GUEST_LAZY_MSRS)
8333 {
8334 hmR0VmxLazyLoadGuestMsrs(pVCpu);
8335 pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_VMX_GUEST_LAZY_MSRS;
8336 }
8337
8338 AssertMsg(!(pVCpu->hm.s.fCtxChanged & HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE),
8339 ("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
8340}
8341
8342
8343/**
8344 * Worker for loading the guest-state bits in the inner VT-x execution loop.
8345 *
8346 * @returns Strict VBox status code (i.e. informational status codes too).
8347 * @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
8348 * without unrestricted guest access and the VMMDev is not presently
8349 * mapped (e.g. EFI32).
8350 *
8351 * @param pVCpu The cross context virtual CPU structure.
8352 *
8353 * @remarks No-long-jump zone!!!
8354 */
8355static VBOXSTRICTRC hmR0VmxExportGuestStateOptimal(PVMCPU pVCpu)
8356{
8357 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
8358 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8359 Assert(VMMR0IsLogFlushDisabled(pVCpu));
8360
8361#ifdef HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE
8362 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
8363#endif
8364
8365 /*
8366 * For many exits it's only RIP that changes and hence try to export it first
8367 * without going through a lot of change flag checks.
8368 */
8369 VBOXSTRICTRC rcStrict;
8370 uint64_t fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
8371 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
8372 if ((fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE)) == HM_CHANGED_GUEST_RIP)
8373 {
8374 rcStrict = hmR0VmxExportGuestRip(pVCpu);
8375 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8376 { /* likely */}
8377 else
8378 AssertMsgFailedReturn(("hmR0VmxExportGuestRip failed! rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), rcStrict);
8379 STAM_COUNTER_INC(&pVCpu->hm.s.StatExportMinimal);
8380 }
8381 else if (fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
8382 {
8383 rcStrict = hmR0VmxExportGuestState(pVCpu);
8384 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8385 { /* likely */}
8386 else
8387 {
8388 AssertMsg(rcStrict == VINF_EM_RESCHEDULE_REM, ("hmR0VmxExportGuestState failed! rc=%Rrc\n",
8389 VBOXSTRICTRC_VAL(rcStrict)));
8390 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8391 return rcStrict;
8392 }
8393 STAM_COUNTER_INC(&pVCpu->hm.s.StatExportFull);
8394 }
8395 else
8396 rcStrict = VINF_SUCCESS;
8397
8398#ifdef VBOX_STRICT
8399 /* All the guest state bits should be loaded except maybe the host context and/or the shared host/guest bits. */
8400 fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
8401 RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
8402 AssertMsg(!(fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE)),
8403 ("fCtxChanged=%#RX64\n", fCtxChanged));
8404#endif
8405 return rcStrict;
8406}
8407
8408
8409/**
8410 * Does the preparations before executing guest code in VT-x.
8411 *
8412 * This may cause longjmps to ring-3 and may even result in rescheduling to the
8413 * recompiler/IEM. We must be cautious what we do here regarding committing
8414 * guest-state information into the VMCS assuming we assuredly execute the
8415 * guest in VT-x mode.
8416 *
8417 * If we fall back to the recompiler/IEM after updating the VMCS and clearing
8418 * the common-state (TRPM/forceflags), we must undo those changes so that the
8419 * recompiler/IEM can (and should) use them when it resumes guest execution.
8420 * Otherwise such operations must be done when we can no longer exit to ring-3.
8421 *
8422 * @returns Strict VBox status code (i.e. informational status codes too).
8423 * @retval VINF_SUCCESS if we can proceed with running the guest, interrupts
8424 * have been disabled.
8425 * @retval VINF_EM_RESET if a triple-fault occurs while injecting a
8426 * double-fault into the guest.
8427 * @retval VINF_EM_DBG_STEPPED if @a fStepping is true and an event was
8428 * dispatched directly.
8429 * @retval VINF_* scheduling changes, we have to go back to ring-3.
8430 *
8431 * @param pVCpu The cross context virtual CPU structure.
8432 * @param pVmxTransient Pointer to the VMX transient structure.
8433 * @param fStepping Set if called from hmR0VmxRunGuestCodeStep(). Makes
8434 * us ignore some of the reasons for returning to
8435 * ring-3, and return VINF_EM_DBG_STEPPED if event
8436 * dispatching took place.
8437 */
8438static VBOXSTRICTRC hmR0VmxPreRunGuest(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, bool fStepping)
8439{
8440 Assert(VMMRZCallRing3IsEnabled(pVCpu));
8441
8442#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
8443 if (CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx))
8444 {
8445 Log2(("hmR0VmxPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
8446 RT_NOREF3(pVCpu, pVmxTransient, fStepping);
8447 return VINF_EM_RESCHEDULE_REM;
8448 }
8449#endif
8450
8451#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
8452 PGMRZDynMapFlushAutoSet(pVCpu);
8453#endif
8454
8455 /* Check force flag actions that might require us to go back to ring-3. */
8456 VBOXSTRICTRC rcStrict = hmR0VmxCheckForceFlags(pVCpu, fStepping);
8457 if (rcStrict == VINF_SUCCESS)
8458 { /* FFs doesn't get set all the time. */ }
8459 else
8460 return rcStrict;
8461
8462 /*
8463 * Setup the virtualized-APIC accesses.
8464 *
8465 * Note! This can cause a longjumps to R3 due to the acquisition of the PGM lock
8466 * in both PGMHandlerPhysicalReset() and IOMMMIOMapMMIOHCPage(), see @bugref{8721}.
8467 *
8468 * This is the reason we do it here and not in hmR0VmxExportGuestState().
8469 */
8470 PVM pVM = pVCpu->CTX_SUFF(pVM);
8471 if ( !pVCpu->hm.s.vmx.u64MsrApicBase
8472 && (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
8473 && PDMHasApic(pVM))
8474 {
8475 uint64_t const u64MsrApicBase = APICGetBaseMsrNoCheck(pVCpu);
8476 Assert(u64MsrApicBase);
8477 Assert(pVM->hm.s.vmx.HCPhysApicAccess);
8478
8479 RTGCPHYS const GCPhysApicBase = u64MsrApicBase & PAGE_BASE_GC_MASK;
8480
8481 /* Unalias any existing mapping. */
8482 int rc = PGMHandlerPhysicalReset(pVM, GCPhysApicBase);
8483 AssertRCReturn(rc, rc);
8484
8485 /* Map the HC APIC-access page in place of the MMIO page, also updates the shadow page tables if necessary. */
8486 Log4Func(("Mapped HC APIC-access page at %#RGp\n", GCPhysApicBase));
8487 rc = IOMMMIOMapMMIOHCPage(pVM, pVCpu, GCPhysApicBase, pVM->hm.s.vmx.HCPhysApicAccess, X86_PTE_RW | X86_PTE_P);
8488 AssertRCReturn(rc, rc);
8489
8490 /* Update the per-VCPU cache of the APIC base MSR. */
8491 pVCpu->hm.s.vmx.u64MsrApicBase = u64MsrApicBase;
8492 }
8493
8494 if (TRPMHasTrap(pVCpu))
8495 hmR0VmxTrpmTrapToPendingEvent(pVCpu);
8496 uint32_t fIntrState = hmR0VmxEvaluatePendingEvent(pVCpu);
8497
8498 /*
8499 * Event injection may take locks (currently the PGM lock for real-on-v86 case) and thus
8500 * needs to be done with longjmps or interrupts + preemption enabled. Event injection might
8501 * also result in triple-faulting the VM.
8502 */
8503 rcStrict = hmR0VmxInjectPendingEvent(pVCpu, fIntrState, fStepping);
8504 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8505 { /* likely */ }
8506 else
8507 {
8508 AssertMsg(rcStrict == VINF_EM_RESET || (rcStrict == VINF_EM_DBG_STEPPED && fStepping),
8509 ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8510 return rcStrict;
8511 }
8512
8513 /*
8514 * A longjump might result in importing CR3 even for VM-exits that don't necessarily
8515 * import CR3 themselves. We will need to update them here, as even as late as the above
8516 * hmR0VmxInjectPendingEvent() call may lazily import guest-CPU state on demand causing
8517 * the below force flags to be set.
8518 */
8519 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
8520 {
8521 Assert(!(ASMAtomicUoReadU64(&pVCpu->cpum.GstCtx.fExtrn) & CPUMCTX_EXTRN_CR3));
8522 int rc2 = PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
8523 AssertMsgReturn(rc2 == VINF_SUCCESS || rc2 == VINF_PGM_SYNC_CR3,
8524 ("%Rrc\n", rc2), RT_FAILURE_NP(rc2) ? rc2 : VERR_IPE_UNEXPECTED_INFO_STATUS);
8525 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
8526 }
8527 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
8528 {
8529 PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
8530 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
8531 }
8532
8533 /*
8534 * No longjmps to ring-3 from this point on!!!
8535 * Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
8536 * This also disables flushing of the R0-logger instance (if any).
8537 */
8538 VMMRZCallRing3Disable(pVCpu);
8539
8540 /*
8541 * Export the guest state bits.
8542 *
8543 * We cannot perform longjmps while loading the guest state because we do not preserve the
8544 * host/guest state (although the VMCS will be preserved) across longjmps which can cause
8545 * CPU migration.
8546 *
8547 * If we are injecting events to a real-on-v86 mode guest, we will have to update
8548 * RIP and some segment registers, i.e. hmR0VmxInjectPendingEvent()->hmR0VmxInjectEventVmcs().
8549 * Hence, loading of the guest state needs to be done -after- injection of events.
8550 */
8551 rcStrict = hmR0VmxExportGuestStateOptimal(pVCpu);
8552 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8553 { /* likely */ }
8554 else
8555 {
8556 VMMRZCallRing3Enable(pVCpu);
8557 return rcStrict;
8558 }
8559
8560 /*
8561 * We disable interrupts so that we don't miss any interrupts that would flag preemption
8562 * (IPI/timers etc.) when thread-context hooks aren't used and we've been running with
8563 * preemption disabled for a while. Since this is purly to aid the
8564 * RTThreadPreemptIsPending() code, it doesn't matter that it may temporarily reenable and
8565 * disable interrupt on NT.
8566 *
8567 * We need to check for force-flags that could've possible been altered since we last
8568 * checked them (e.g. by PDMGetInterrupt() leaving the PDM critical section,
8569 * see @bugref{6398}).
8570 *
8571 * We also check a couple of other force-flags as a last opportunity to get the EMT back
8572 * to ring-3 before executing guest code.
8573 */
8574 pVmxTransient->fEFlags = ASMIntDisableFlags();
8575
8576 if ( ( !VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS | VM_FF_TM_VIRTUAL_SYNC)
8577 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
8578 || ( fStepping /* Optimized for the non-stepping case, so a bit of unnecessary work when stepping. */
8579 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK & ~(VMCPU_FF_TIMER | VMCPU_FF_PDM_CRITSECT))) )
8580 {
8581 if (!RTThreadPreemptIsPending(NIL_RTTHREAD))
8582 {
8583 pVCpu->hm.s.Event.fPending = false;
8584
8585 /*
8586 * We've injected any pending events. This is really the point of no return (to ring-3).
8587 *
8588 * Note! The caller expects to continue with interrupts & longjmps disabled on successful
8589 * returns from this function, so don't enable them here.
8590 */
8591 return VINF_SUCCESS;
8592 }
8593
8594 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPendingHostIrq);
8595 rcStrict = VINF_EM_RAW_INTERRUPT;
8596 }
8597 else
8598 {
8599 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
8600 rcStrict = VINF_EM_RAW_TO_R3;
8601 }
8602
8603 ASMSetFlags(pVmxTransient->fEFlags);
8604 VMMRZCallRing3Enable(pVCpu);
8605
8606 return rcStrict;
8607}
8608
8609
8610/**
8611 * Prepares to run guest code in VT-x and we've committed to doing so. This
8612 * means there is no backing out to ring-3 or anywhere else at this
8613 * point.
8614 *
8615 * @param pVCpu The cross context virtual CPU structure.
8616 * @param pVmxTransient Pointer to the VMX transient structure.
8617 *
8618 * @remarks Called with preemption disabled.
8619 * @remarks No-long-jump zone!!!
8620 */
8621static void hmR0VmxPreRunGuestCommitted(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
8622{
8623 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8624 Assert(VMMR0IsLogFlushDisabled(pVCpu));
8625 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8626
8627 /*
8628 * Indicate start of guest execution and where poking EMT out of guest-context is recognized.
8629 */
8630 VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
8631 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
8632
8633 PVM pVM = pVCpu->CTX_SUFF(pVM);
8634 if (!CPUMIsGuestFPUStateActive(pVCpu))
8635 {
8636 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestFpuState, x);
8637 if (CPUMR0LoadGuestFPU(pVM, pVCpu) == VINF_CPUM_HOST_CR0_MODIFIED)
8638 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_HOST_CONTEXT;
8639 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestFpuState, x);
8640 STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadGuestFpu);
8641 }
8642
8643 /*
8644 * Lazy-update of the host MSRs values in the auto-load/store MSR area.
8645 */
8646 if ( !pVCpu->hm.s.vmx.fUpdatedHostMsrs
8647 && pVCpu->hm.s.vmx.cMsrs > 0)
8648 hmR0VmxUpdateAutoLoadStoreHostMsrs(pVCpu);
8649
8650 /*
8651 * Re-save the host state bits as we may've been preempted (only happens when
8652 * thread-context hooks are used or when hmR0VmxSetupVMRunHandler() changes pfnStartVM).
8653 * Note that the 64-on-32 switcher saves the (64-bit) host state into the VMCS and
8654 * if we change the switcher back to 32-bit, we *must* save the 32-bit host state here.
8655 * See @bugref{8432}.
8656 */
8657 if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_HOST_CONTEXT)
8658 {
8659 int rc = hmR0VmxExportHostState(pVCpu);
8660 AssertRC(rc);
8661 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreemptExportHostState);
8662 }
8663 Assert(!(pVCpu->hm.s.fCtxChanged & HM_CHANGED_HOST_CONTEXT));
8664
8665 /*
8666 * Export the state shared between host and guest (FPU, debug, lazy MSRs).
8667 */
8668 if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE)
8669 hmR0VmxExportSharedState(pVCpu);
8670 AssertMsg(!pVCpu->hm.s.fCtxChanged, ("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
8671
8672 /* Store status of the shared guest-host state at the time of VM-entry. */
8673#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
8674 if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx))
8675 {
8676 pVmxTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
8677 pVmxTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
8678 }
8679 else
8680#endif
8681 {
8682 pVmxTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
8683 pVmxTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
8684 }
8685
8686 /*
8687 * Cache the TPR-shadow for checking on every VM-exit if it might have changed.
8688 */
8689 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
8690 pVmxTransient->u8GuestTpr = pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR];
8691
8692 PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
8693 RTCPUID idCurrentCpu = pCpu->idCpu;
8694 if ( pVmxTransient->fUpdateTscOffsettingAndPreemptTimer
8695 || idCurrentCpu != pVCpu->hm.s.idLastCpu)
8696 {
8697 hmR0VmxUpdateTscOffsettingAndPreemptTimer(pVCpu);
8698 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = false;
8699 }
8700
8701 ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
8702 hmR0VmxFlushTaggedTlb(pVCpu, pCpu); /* Invalidate the appropriate guest entries from the TLB. */
8703 Assert(idCurrentCpu == pVCpu->hm.s.idLastCpu);
8704 pVCpu->hm.s.vmx.LastError.idCurrentCpu = idCurrentCpu; /* Update the error reporting info. with the current host CPU. */
8705
8706 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
8707
8708 TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
8709 to start executing. */
8710
8711 /*
8712 * Load the TSC_AUX MSR when we are not intercepting RDTSCP.
8713 */
8714 if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_PROC_CTLS2_RDTSCP)
8715 {
8716 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_RDTSC_EXIT))
8717 {
8718 bool fMsrUpdated;
8719 hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_TSC_AUX);
8720 int rc2 = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_TSC_AUX, CPUMGetGuestTscAux(pVCpu), true /* fUpdateHostMsr */,
8721 &fMsrUpdated);
8722 AssertRC(rc2);
8723 Assert(fMsrUpdated || pVCpu->hm.s.vmx.fUpdatedHostMsrs);
8724 /* Finally, mark that all host MSR values are updated so we don't redo it without leaving VT-x. See @bugref{6956}. */
8725 pVCpu->hm.s.vmx.fUpdatedHostMsrs = true;
8726 }
8727 else
8728 {
8729 hmR0VmxRemoveAutoLoadStoreMsr(pVCpu, MSR_K8_TSC_AUX);
8730 Assert(!pVCpu->hm.s.vmx.cMsrs || pVCpu->hm.s.vmx.fUpdatedHostMsrs);
8731 }
8732 }
8733
8734 if (pVM->cpum.ro.GuestFeatures.fIbrs)
8735 {
8736 bool fMsrUpdated;
8737 hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_OTHER_MSRS);
8738 int rc2 = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_IA32_SPEC_CTRL, CPUMGetGuestSpecCtrl(pVCpu), true /* fUpdateHostMsr */,
8739 &fMsrUpdated);
8740 AssertRC(rc2);
8741 Assert(fMsrUpdated || pVCpu->hm.s.vmx.fUpdatedHostMsrs);
8742 /* Finally, mark that all host MSR values are updated so we don't redo it without leaving VT-x. See @bugref{6956}. */
8743 pVCpu->hm.s.vmx.fUpdatedHostMsrs = true;
8744 }
8745
8746#ifdef VBOX_STRICT
8747 hmR0VmxCheckAutoLoadStoreMsrs(pVCpu);
8748 hmR0VmxCheckHostEferMsr(pVCpu);
8749 AssertRC(hmR0VmxCheckVmcsCtls(pVCpu));
8750#endif
8751#ifdef HMVMX_ALWAYS_CHECK_GUEST_STATE
8752 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS))
8753 {
8754 uint32_t uInvalidReason = hmR0VmxCheckGuestState(pVCpu);
8755 if (uInvalidReason != VMX_IGS_REASON_NOT_FOUND)
8756 Log4(("hmR0VmxCheckGuestState returned %#x\n", uInvalidReason));
8757 }
8758#endif
8759}
8760
8761
8762/**
8763 * Performs some essential restoration of state after running guest code in
8764 * VT-x.
8765 *
8766 * @param pVCpu The cross context virtual CPU structure.
8767 * @param pVmxTransient Pointer to the VMX transient structure.
8768 * @param rcVMRun Return code of VMLAUNCH/VMRESUME.
8769 *
8770 * @remarks Called with interrupts disabled, and returns with interrupts enabled!
8771 *
8772 * @remarks No-long-jump zone!!! This function will however re-enable longjmps
8773 * unconditionally when it is safe to do so.
8774 */
8775static void hmR0VmxPostRunGuest(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, int rcVMRun)
8776{
8777 uint64_t const uHostTsc = ASMReadTSC();
8778 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8779
8780 ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
8781 ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
8782 pVCpu->hm.s.fCtxChanged = 0; /* Exits/longjmps to ring-3 requires saving the guest state. */
8783 pVmxTransient->fVmcsFieldsRead = 0; /* Transient fields need to be read from the VMCS. */
8784 pVmxTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
8785 pVmxTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
8786
8787 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_RDTSC_EXIT))
8788 TMCpuTickSetLastSeen(pVCpu, uHostTsc + pVCpu->hm.s.vmx.u64TscOffset);
8789
8790 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatPreExit, x);
8791 TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
8792 Assert(!ASMIntAreEnabled());
8793 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
8794
8795#if HC_ARCH_BITS == 64
8796 pVCpu->hm.s.vmx.fRestoreHostFlags |= VMX_RESTORE_HOST_REQUIRED; /* Host state messed up by VT-x, we must restore. */
8797#endif
8798#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
8799 /* The 64-on-32 switcher maintains uVmcsState on its own and we need to leave it alone here. */
8800 if (pVCpu->hm.s.vmx.pfnStartVM != VMXR0SwitcherStartVM64)
8801 pVCpu->hm.s.vmx.uVmcsState |= HMVMX_VMCS_STATE_LAUNCHED; /* Use VMRESUME instead of VMLAUNCH in the next run. */
8802#else
8803 pVCpu->hm.s.vmx.uVmcsState |= HMVMX_VMCS_STATE_LAUNCHED; /* Use VMRESUME instead of VMLAUNCH in the next run. */
8804#endif
8805#ifdef VBOX_STRICT
8806 hmR0VmxCheckHostEferMsr(pVCpu); /* Verify that VMRUN/VMLAUNCH didn't modify host EFER. */
8807#endif
8808 ASMSetFlags(pVmxTransient->fEFlags); /* Enable interrupts. */
8809
8810 /* Save the basic VM-exit reason. Refer Intel spec. 24.9.1 "Basic VM-exit Information". */
8811 uint32_t uExitReason;
8812 int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_REASON, &uExitReason);
8813 rc |= hmR0VmxReadEntryIntInfoVmcs(pVmxTransient);
8814 AssertRC(rc);
8815 pVmxTransient->uExitReason = VMX_EXIT_REASON_BASIC(uExitReason);
8816 pVmxTransient->fVMEntryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
8817
8818 if (rcVMRun == VINF_SUCCESS)
8819 {
8820 /*
8821 * Update the VM-exit history array here even if the VM-entry failed due to:
8822 * - Invalid guest state.
8823 * - MSR loading.
8824 * - Machine-check event.
8825 *
8826 * In any of the above cases we will still have a "valid" VM-exit reason
8827 * despite @a fVMEntryFailed being false.
8828 *
8829 * See Intel spec. 26.7 "VM-Entry failures during or after loading guest state".
8830 *
8831 * Note! We don't have CS or RIP at this point. Will probably address that later
8832 * by amending the history entry added here.
8833 */
8834 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_VMX, pVmxTransient->uExitReason & EMEXIT_F_TYPE_MASK),
8835 UINT64_MAX, uHostTsc);
8836
8837 if (!pVmxTransient->fVMEntryFailed)
8838 {
8839 VMMRZCallRing3Enable(pVCpu);
8840
8841 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
8842 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
8843
8844#if defined(HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE) || defined(HMVMX_ALWAYS_SAVE_FULL_GUEST_STATE)
8845 rc = hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
8846 AssertRC(rc);
8847#elif defined(HMVMX_ALWAYS_SAVE_GUEST_RFLAGS)
8848 rc = hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_RFLAGS);
8849 AssertRC(rc);
8850#else
8851 /*
8852 * Import the guest-interruptibility state always as we need it while evaluating
8853 * injecting events on re-entry.
8854 *
8855 * We don't import CR0 (when Unrestricted guest execution is unavailable) despite
8856 * checking for real-mode while exporting the state because all bits that cause
8857 * mode changes wrt CR0 are intercepted.
8858 */
8859 rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_HM_VMX_INT_STATE);
8860 AssertRC(rc);
8861#endif
8862
8863 /*
8864 * Sync the TPR shadow with our APIC state.
8865 */
8866 if ( (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
8867 && pVmxTransient->u8GuestTpr != pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR])
8868 {
8869 rc = APICSetTpr(pVCpu, pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR]);
8870 AssertRC(rc);
8871 ASMAtomicOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
8872 }
8873
8874 Assert(VMMRZCallRing3IsEnabled(pVCpu));
8875 return;
8876 }
8877 }
8878 else
8879 Log4Func(("VM-entry failure: rcVMRun=%Rrc fVMEntryFailed=%RTbool\n", rcVMRun, pVmxTransient->fVMEntryFailed));
8880
8881 VMMRZCallRing3Enable(pVCpu);
8882}
8883
8884
8885/**
8886 * Runs the guest code using VT-x the normal way.
8887 *
8888 * @returns VBox status code.
8889 * @param pVCpu The cross context virtual CPU structure.
8890 *
8891 * @note Mostly the same as hmR0VmxRunGuestCodeStep().
8892 */
8893static VBOXSTRICTRC hmR0VmxRunGuestCodeNormal(PVMCPU pVCpu)
8894{
8895 VMXTRANSIENT VmxTransient;
8896 VmxTransient.fUpdateTscOffsettingAndPreemptTimer = true;
8897 VBOXSTRICTRC rcStrict = VERR_INTERNAL_ERROR_5;
8898 uint32_t cLoops = 0;
8899
8900 for (;; cLoops++)
8901 {
8902 Assert(!HMR0SuspendPending());
8903 HMVMX_ASSERT_CPU_SAFE(pVCpu);
8904
8905 /* Preparatory work for running guest code, this may force us to return
8906 to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
8907 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
8908 rcStrict = hmR0VmxPreRunGuest(pVCpu, &VmxTransient, false /* fStepping */);
8909 if (rcStrict != VINF_SUCCESS)
8910 break;
8911
8912 hmR0VmxPreRunGuestCommitted(pVCpu, &VmxTransient);
8913 int rcRun = hmR0VmxRunGuest(pVCpu);
8914
8915 /* Restore any residual host-state and save any bits shared between host
8916 and guest into the guest-CPU state. Re-enables interrupts! */
8917 hmR0VmxPostRunGuest(pVCpu, &VmxTransient, rcRun);
8918
8919 /* Check for errors with running the VM (VMLAUNCH/VMRESUME). */
8920 if (RT_SUCCESS(rcRun))
8921 { /* very likely */ }
8922 else
8923 {
8924 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
8925 hmR0VmxReportWorldSwitchError(pVCpu, rcRun, &VmxTransient);
8926 return rcRun;
8927 }
8928
8929 /* Profile the VM-exit. */
8930 AssertMsg(VmxTransient.uExitReason <= VMX_EXIT_MAX, ("%#x\n", VmxTransient.uExitReason));
8931 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll);
8932 STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);
8933 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
8934 HMVMX_START_EXIT_DISPATCH_PROF();
8935
8936 VBOXVMM_R0_HMVMX_VMEXIT_NOCTX(pVCpu, &pVCpu->cpum.GstCtx, VmxTransient.uExitReason);
8937
8938 /* Handle the VM-exit. */
8939#ifdef HMVMX_USE_FUNCTION_TABLE
8940 rcStrict = g_apfnVMExitHandlers[VmxTransient.uExitReason](pVCpu, &VmxTransient);
8941#else
8942 rcStrict = hmR0VmxHandleExit(pVCpu, &VmxTransient, VmxTransient.uExitReason);
8943#endif
8944 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
8945 if (rcStrict == VINF_SUCCESS)
8946 {
8947 if (cLoops <= pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops)
8948 continue; /* likely */
8949 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
8950 rcStrict = VINF_EM_RAW_INTERRUPT;
8951 }
8952 break;
8953 }
8954
8955 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
8956 return rcStrict;
8957}
8958
8959
8960
8961/** @name Execution loop for single stepping, DBGF events and expensive Dtrace
8962 * probes.
8963 *
8964 * The following few functions and associated structure contains the bloat
8965 * necessary for providing detailed debug events and dtrace probes as well as
8966 * reliable host side single stepping. This works on the principle of
8967 * "subclassing" the normal execution loop and workers. We replace the loop
8968 * method completely and override selected helpers to add necessary adjustments
8969 * to their core operation.
8970 *
8971 * The goal is to keep the "parent" code lean and mean, so as not to sacrifice
8972 * any performance for debug and analysis features.
8973 *
8974 * @{
8975 */
8976
8977/**
8978 * Transient per-VCPU debug state of VMCS and related info. we save/restore in
8979 * the debug run loop.
8980 */
8981typedef struct VMXRUNDBGSTATE
8982{
8983 /** The RIP we started executing at. This is for detecting that we stepped. */
8984 uint64_t uRipStart;
8985 /** The CS we started executing with. */
8986 uint16_t uCsStart;
8987
8988 /** Whether we've actually modified the 1st execution control field. */
8989 bool fModifiedProcCtls : 1;
8990 /** Whether we've actually modified the 2nd execution control field. */
8991 bool fModifiedProcCtls2 : 1;
8992 /** Whether we've actually modified the exception bitmap. */
8993 bool fModifiedXcptBitmap : 1;
8994
8995 /** We desire the modified the CR0 mask to be cleared. */
8996 bool fClearCr0Mask : 1;
8997 /** We desire the modified the CR4 mask to be cleared. */
8998 bool fClearCr4Mask : 1;
8999 /** Stuff we need in VMX_VMCS32_CTRL_PROC_EXEC. */
9000 uint32_t fCpe1Extra;
9001 /** Stuff we do not want in VMX_VMCS32_CTRL_PROC_EXEC. */
9002 uint32_t fCpe1Unwanted;
9003 /** Stuff we need in VMX_VMCS32_CTRL_PROC_EXEC2. */
9004 uint32_t fCpe2Extra;
9005 /** Extra stuff we need in VMX_VMCS32_CTRL_EXCEPTION_BITMAP. */
9006 uint32_t bmXcptExtra;
9007 /** The sequence number of the Dtrace provider settings the state was
9008 * configured against. */
9009 uint32_t uDtraceSettingsSeqNo;
9010 /** VM-exits to check (one bit per VM-exit). */
9011 uint32_t bmExitsToCheck[3];
9012
9013 /** The initial VMX_VMCS32_CTRL_PROC_EXEC value (helps with restore). */
9014 uint32_t fProcCtlsInitial;
9015 /** The initial VMX_VMCS32_CTRL_PROC_EXEC2 value (helps with restore). */
9016 uint32_t fProcCtls2Initial;
9017 /** The initial VMX_VMCS32_CTRL_EXCEPTION_BITMAP value (helps with restore). */
9018 uint32_t bmXcptInitial;
9019} VMXRUNDBGSTATE;
9020AssertCompileMemberSize(VMXRUNDBGSTATE, bmExitsToCheck, (VMX_EXIT_MAX + 1 + 31) / 32 * 4);
9021typedef VMXRUNDBGSTATE *PVMXRUNDBGSTATE;
9022
9023
9024/**
9025 * Initializes the VMXRUNDBGSTATE structure.
9026 *
9027 * @param pVCpu The cross context virtual CPU structure of the
9028 * calling EMT.
9029 * @param pDbgState The structure to initialize.
9030 */
9031static void hmR0VmxRunDebugStateInit(PVMCPU pVCpu, PVMXRUNDBGSTATE pDbgState)
9032{
9033 pDbgState->uRipStart = pVCpu->cpum.GstCtx.rip;
9034 pDbgState->uCsStart = pVCpu->cpum.GstCtx.cs.Sel;
9035
9036 pDbgState->fModifiedProcCtls = false;
9037 pDbgState->fModifiedProcCtls2 = false;
9038 pDbgState->fModifiedXcptBitmap = false;
9039 pDbgState->fClearCr0Mask = false;
9040 pDbgState->fClearCr4Mask = false;
9041 pDbgState->fCpe1Extra = 0;
9042 pDbgState->fCpe1Unwanted = 0;
9043 pDbgState->fCpe2Extra = 0;
9044 pDbgState->bmXcptExtra = 0;
9045 pDbgState->fProcCtlsInitial = pVCpu->hm.s.vmx.u32ProcCtls;
9046 pDbgState->fProcCtls2Initial = pVCpu->hm.s.vmx.u32ProcCtls2;
9047 pDbgState->bmXcptInitial = pVCpu->hm.s.vmx.u32XcptBitmap;
9048}
9049
9050
9051/**
9052 * Updates the VMSC fields with changes requested by @a pDbgState.
9053 *
9054 * This is performed after hmR0VmxPreRunGuestDebugStateUpdate as well
9055 * immediately before executing guest code, i.e. when interrupts are disabled.
9056 * We don't check status codes here as we cannot easily assert or return in the
9057 * latter case.
9058 *
9059 * @param pVCpu The cross context virtual CPU structure.
9060 * @param pDbgState The debug state.
9061 */
9062static void hmR0VmxPreRunGuestDebugStateApply(PVMCPU pVCpu, PVMXRUNDBGSTATE pDbgState)
9063{
9064 /*
9065 * Ensure desired flags in VMCS control fields are set.
9066 * (Ignoring write failure here, as we're committed and it's just debug extras.)
9067 *
9068 * Note! We load the shadow CR0 & CR4 bits when we flag the clearing, so
9069 * there should be no stale data in pCtx at this point.
9070 */
9071 if ( (pVCpu->hm.s.vmx.u32ProcCtls & pDbgState->fCpe1Extra) != pDbgState->fCpe1Extra
9072 || (pVCpu->hm.s.vmx.u32ProcCtls & pDbgState->fCpe1Unwanted))
9073 {
9074 pVCpu->hm.s.vmx.u32ProcCtls |= pDbgState->fCpe1Extra;
9075 pVCpu->hm.s.vmx.u32ProcCtls &= ~pDbgState->fCpe1Unwanted;
9076 VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
9077 Log6Func(("VMX_VMCS32_CTRL_PROC_EXEC: %#RX32\n", pVCpu->hm.s.vmx.u32ProcCtls));
9078 pDbgState->fModifiedProcCtls = true;
9079 }
9080
9081 if ((pVCpu->hm.s.vmx.u32ProcCtls2 & pDbgState->fCpe2Extra) != pDbgState->fCpe2Extra)
9082 {
9083 pVCpu->hm.s.vmx.u32ProcCtls2 |= pDbgState->fCpe2Extra;
9084 VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, pVCpu->hm.s.vmx.u32ProcCtls2);
9085 Log6Func(("VMX_VMCS32_CTRL_PROC_EXEC2: %#RX32\n", pVCpu->hm.s.vmx.u32ProcCtls2));
9086 pDbgState->fModifiedProcCtls2 = true;
9087 }
9088
9089 if ((pVCpu->hm.s.vmx.u32XcptBitmap & pDbgState->bmXcptExtra) != pDbgState->bmXcptExtra)
9090 {
9091 pVCpu->hm.s.vmx.u32XcptBitmap |= pDbgState->bmXcptExtra;
9092 VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap);
9093 Log6Func(("VMX_VMCS32_CTRL_EXCEPTION_BITMAP: %#RX32\n", pVCpu->hm.s.vmx.u32XcptBitmap));
9094 pDbgState->fModifiedXcptBitmap = true;
9095 }
9096
9097 if (pDbgState->fClearCr0Mask && pVCpu->hm.s.vmx.u32Cr0Mask != 0)
9098 {
9099 pVCpu->hm.s.vmx.u32Cr0Mask = 0;
9100 VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_MASK, 0);
9101 Log6Func(("VMX_VMCS_CTRL_CR0_MASK: 0\n"));
9102 }
9103
9104 if (pDbgState->fClearCr4Mask && pVCpu->hm.s.vmx.u32Cr4Mask != 0)
9105 {
9106 pVCpu->hm.s.vmx.u32Cr4Mask = 0;
9107 VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_MASK, 0);
9108 Log6Func(("VMX_VMCS_CTRL_CR4_MASK: 0\n"));
9109 }
9110}
9111
9112
9113/**
9114 * Restores VMCS fields that were changed by hmR0VmxPreRunGuestDebugStateApply for
9115 * re-entry next time around.
9116 *
9117 * @returns Strict VBox status code (i.e. informational status codes too).
9118 * @param pVCpu The cross context virtual CPU structure.
9119 * @param pDbgState The debug state.
9120 * @param rcStrict The return code from executing the guest using single
9121 * stepping.
9122 */
9123static VBOXSTRICTRC hmR0VmxRunDebugStateRevert(PVMCPU pVCpu, PVMXRUNDBGSTATE pDbgState, VBOXSTRICTRC rcStrict)
9124{
9125 /*
9126 * Restore VM-exit control settings as we may not reenter this function the
9127 * next time around.
9128 */
9129 /* We reload the initial value, trigger what we can of recalculations the
9130 next time around. From the looks of things, that's all that's required atm. */
9131 if (pDbgState->fModifiedProcCtls)
9132 {
9133 if (!(pDbgState->fProcCtlsInitial & VMX_PROC_CTLS_MOV_DR_EXIT) && CPUMIsHyperDebugStateActive(pVCpu))
9134 pDbgState->fProcCtlsInitial |= VMX_PROC_CTLS_MOV_DR_EXIT; /* Avoid assertion in hmR0VmxLeave */
9135 int rc2 = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pDbgState->fProcCtlsInitial);
9136 AssertRCReturn(rc2, rc2);
9137 pVCpu->hm.s.vmx.u32ProcCtls = pDbgState->fProcCtlsInitial;
9138 }
9139
9140 /* We're currently the only ones messing with this one, so just restore the
9141 cached value and reload the field. */
9142 if ( pDbgState->fModifiedProcCtls2
9143 && pVCpu->hm.s.vmx.u32ProcCtls2 != pDbgState->fProcCtls2Initial)
9144 {
9145 int rc2 = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, pDbgState->fProcCtls2Initial);
9146 AssertRCReturn(rc2, rc2);
9147 pVCpu->hm.s.vmx.u32ProcCtls2 = pDbgState->fProcCtls2Initial;
9148 }
9149
9150 /* If we've modified the exception bitmap, we restore it and trigger
9151 reloading and partial recalculation the next time around. */
9152 if (pDbgState->fModifiedXcptBitmap)
9153 pVCpu->hm.s.vmx.u32XcptBitmap = pDbgState->bmXcptInitial;
9154
9155 return rcStrict;
9156}
9157
9158
9159/**
9160 * Configures VM-exit controls for current DBGF and DTrace settings.
9161 *
9162 * This updates @a pDbgState and the VMCS execution control fields to reflect
9163 * the necessary VM-exits demanded by DBGF and DTrace.
9164 *
9165 * @param pVCpu The cross context virtual CPU structure.
9166 * @param pDbgState The debug state.
9167 * @param pVmxTransient Pointer to the VMX transient structure. May update
9168 * fUpdateTscOffsettingAndPreemptTimer.
9169 */
9170static void hmR0VmxPreRunGuestDebugStateUpdate(PVMCPU pVCpu, PVMXRUNDBGSTATE pDbgState, PVMXTRANSIENT pVmxTransient)
9171{
9172 /*
9173 * Take down the dtrace serial number so we can spot changes.
9174 */
9175 pDbgState->uDtraceSettingsSeqNo = VBOXVMM_GET_SETTINGS_SEQ_NO();
9176 ASMCompilerBarrier();
9177
9178 /*
9179 * We'll rebuild most of the middle block of data members (holding the
9180 * current settings) as we go along here, so start by clearing it all.
9181 */
9182 pDbgState->bmXcptExtra = 0;
9183 pDbgState->fCpe1Extra = 0;
9184 pDbgState->fCpe1Unwanted = 0;
9185 pDbgState->fCpe2Extra = 0;
9186 for (unsigned i = 0; i < RT_ELEMENTS(pDbgState->bmExitsToCheck); i++)
9187 pDbgState->bmExitsToCheck[i] = 0;
9188
9189 /*
9190 * Software interrupts (INT XXh) - no idea how to trigger these...
9191 */
9192 PVM pVM = pVCpu->CTX_SUFF(pVM);
9193 if ( DBGF_IS_EVENT_ENABLED(pVM, DBGFEVENT_INTERRUPT_SOFTWARE)
9194 || VBOXVMM_INT_SOFTWARE_ENABLED())
9195 {
9196 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_XCPT_OR_NMI);
9197 }
9198
9199 /*
9200 * INT3 breakpoints - triggered by #BP exceptions.
9201 */
9202 if (pVM->dbgf.ro.cEnabledInt3Breakpoints > 0)
9203 pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_BP);
9204
9205 /*
9206 * Exception bitmap and XCPT events+probes.
9207 */
9208 for (int iXcpt = 0; iXcpt < (DBGFEVENT_XCPT_LAST - DBGFEVENT_XCPT_FIRST + 1); iXcpt++)
9209 if (DBGF_IS_EVENT_ENABLED(pVM, (DBGFEVENTTYPE)(DBGFEVENT_XCPT_FIRST + iXcpt)))
9210 pDbgState->bmXcptExtra |= RT_BIT_32(iXcpt);
9211
9212 if (VBOXVMM_XCPT_DE_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_DE);
9213 if (VBOXVMM_XCPT_DB_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_DB);
9214 if (VBOXVMM_XCPT_BP_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_BP);
9215 if (VBOXVMM_XCPT_OF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_OF);
9216 if (VBOXVMM_XCPT_BR_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_BR);
9217 if (VBOXVMM_XCPT_UD_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_UD);
9218 if (VBOXVMM_XCPT_NM_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_NM);
9219 if (VBOXVMM_XCPT_DF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_DF);
9220 if (VBOXVMM_XCPT_TS_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_TS);
9221 if (VBOXVMM_XCPT_NP_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_NP);
9222 if (VBOXVMM_XCPT_SS_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_SS);
9223 if (VBOXVMM_XCPT_GP_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_GP);
9224 if (VBOXVMM_XCPT_PF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_PF);
9225 if (VBOXVMM_XCPT_MF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_MF);
9226 if (VBOXVMM_XCPT_AC_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_AC);
9227 if (VBOXVMM_XCPT_XF_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_XF);
9228 if (VBOXVMM_XCPT_VE_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_VE);
9229 if (VBOXVMM_XCPT_SX_ENABLED()) pDbgState->bmXcptExtra |= RT_BIT_32(X86_XCPT_SX);
9230
9231 if (pDbgState->bmXcptExtra)
9232 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_XCPT_OR_NMI);
9233
9234 /*
9235 * Process events and probes for VM-exits, making sure we get the wanted VM-exits.
9236 *
9237 * Note! This is the reverse of what hmR0VmxHandleExitDtraceEvents does.
9238 * So, when adding/changing/removing please don't forget to update it.
9239 *
9240 * Some of the macros are picking up local variables to save horizontal space,
9241 * (being able to see it in a table is the lesser evil here).
9242 */
9243#define IS_EITHER_ENABLED(a_pVM, a_EventSubName) \
9244 ( DBGF_IS_EVENT_ENABLED(a_pVM, RT_CONCAT(DBGFEVENT_, a_EventSubName)) \
9245 || RT_CONCAT3(VBOXVMM_, a_EventSubName, _ENABLED)() )
9246#define SET_ONLY_XBM_IF_EITHER_EN(a_EventSubName, a_uExit) \
9247 if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9248 { AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9249 ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9250 } else do { } while (0)
9251#define SET_CPE1_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fCtrlProcExec) \
9252 if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9253 { \
9254 (pDbgState)->fCpe1Extra |= (a_fCtrlProcExec); \
9255 AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9256 ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9257 } else do { } while (0)
9258#define SET_CPEU_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fUnwantedCtrlProcExec) \
9259 if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9260 { \
9261 (pDbgState)->fCpe1Unwanted |= (a_fUnwantedCtrlProcExec); \
9262 AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9263 ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9264 } else do { } while (0)
9265#define SET_CPE2_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fCtrlProcExec2) \
9266 if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9267 { \
9268 (pDbgState)->fCpe2Extra |= (a_fCtrlProcExec2); \
9269 AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9270 ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9271 } else do { } while (0)
9272
9273 SET_ONLY_XBM_IF_EITHER_EN(EXIT_TASK_SWITCH, VMX_EXIT_TASK_SWITCH); /* unconditional */
9274 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_EPT_VIOLATION, VMX_EXIT_EPT_VIOLATION); /* unconditional */
9275 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_EPT_MISCONFIG, VMX_EXIT_EPT_MISCONFIG); /* unconditional (unless #VE) */
9276 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VAPIC_ACCESS, VMX_EXIT_APIC_ACCESS); /* feature dependent, nothing to enable here */
9277 SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VAPIC_WRITE, VMX_EXIT_APIC_WRITE); /* feature dependent, nothing to enable here */
9278
9279 SET_ONLY_XBM_IF_EITHER_EN(INSTR_CPUID, VMX_EXIT_CPUID); /* unconditional */
9280 SET_ONLY_XBM_IF_EITHER_EN( EXIT_CPUID, VMX_EXIT_CPUID);
9281 SET_ONLY_XBM_IF_EITHER_EN(INSTR_GETSEC, VMX_EXIT_GETSEC); /* unconditional */
9282 SET_ONLY_XBM_IF_EITHER_EN( EXIT_GETSEC, VMX_EXIT_GETSEC);
9283 SET_CPE1_XBM_IF_EITHER_EN(INSTR_HALT, VMX_EXIT_HLT, VMX_PROC_CTLS_HLT_EXIT); /* paranoia */
9284 SET_ONLY_XBM_IF_EITHER_EN( EXIT_HALT, VMX_EXIT_HLT);
9285 SET_ONLY_XBM_IF_EITHER_EN(INSTR_INVD, VMX_EXIT_INVD); /* unconditional */
9286 SET_ONLY_XBM_IF_EITHER_EN( EXIT_INVD, VMX_EXIT_INVD);
9287 SET_CPE1_XBM_IF_EITHER_EN(INSTR_INVLPG, VMX_EXIT_INVLPG, VMX_PROC_CTLS_INVLPG_EXIT);
9288 SET_ONLY_XBM_IF_EITHER_EN( EXIT_INVLPG, VMX_EXIT_INVLPG);
9289 SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDPMC, VMX_EXIT_RDPMC, VMX_PROC_CTLS_RDPMC_EXIT);
9290 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDPMC, VMX_EXIT_RDPMC);
9291 SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDTSC, VMX_EXIT_RDTSC, VMX_PROC_CTLS_RDTSC_EXIT);
9292 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDTSC, VMX_EXIT_RDTSC);
9293 SET_ONLY_XBM_IF_EITHER_EN(INSTR_RSM, VMX_EXIT_RSM); /* unconditional */
9294 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RSM, VMX_EXIT_RSM);
9295 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMM_CALL, VMX_EXIT_VMCALL); /* unconditional */
9296 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMM_CALL, VMX_EXIT_VMCALL);
9297 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMCLEAR, VMX_EXIT_VMCLEAR); /* unconditional */
9298 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMCLEAR, VMX_EXIT_VMCLEAR);
9299 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMLAUNCH, VMX_EXIT_VMLAUNCH); /* unconditional */
9300 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMLAUNCH, VMX_EXIT_VMLAUNCH);
9301 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMPTRLD, VMX_EXIT_VMPTRLD); /* unconditional */
9302 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMPTRLD, VMX_EXIT_VMPTRLD);
9303 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMPTRST, VMX_EXIT_VMPTRST); /* unconditional */
9304 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMPTRST, VMX_EXIT_VMPTRST);
9305 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMREAD, VMX_EXIT_VMREAD); /* unconditional */
9306 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMREAD, VMX_EXIT_VMREAD);
9307 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMRESUME, VMX_EXIT_VMRESUME); /* unconditional */
9308 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMRESUME, VMX_EXIT_VMRESUME);
9309 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMWRITE, VMX_EXIT_VMWRITE); /* unconditional */
9310 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMWRITE, VMX_EXIT_VMWRITE);
9311 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMXOFF, VMX_EXIT_VMXOFF); /* unconditional */
9312 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMXOFF, VMX_EXIT_VMXOFF);
9313 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMXON, VMX_EXIT_VMXON); /* unconditional */
9314 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMXON, VMX_EXIT_VMXON);
9315
9316 if ( IS_EITHER_ENABLED(pVM, INSTR_CRX_READ)
9317 || IS_EITHER_ENABLED(pVM, INSTR_CRX_WRITE))
9318 {
9319 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_APIC_TPR);
9320 AssertRC(rc);
9321
9322#if 0 /** @todo fix me */
9323 pDbgState->fClearCr0Mask = true;
9324 pDbgState->fClearCr4Mask = true;
9325#endif
9326 if (IS_EITHER_ENABLED(pVM, INSTR_CRX_READ))
9327 pDbgState->fCpe1Extra |= VMX_PROC_CTLS_CR3_STORE_EXIT | VMX_PROC_CTLS_CR8_STORE_EXIT;
9328 if (IS_EITHER_ENABLED(pVM, INSTR_CRX_WRITE))
9329 pDbgState->fCpe1Extra |= VMX_PROC_CTLS_CR3_LOAD_EXIT | VMX_PROC_CTLS_CR8_LOAD_EXIT;
9330 pDbgState->fCpe1Unwanted |= VMX_PROC_CTLS_USE_TPR_SHADOW; /* risky? */
9331 /* Note! We currently don't use VMX_VMCS32_CTRL_CR3_TARGET_COUNT. It would
9332 require clearing here and in the loop if we start using it. */
9333 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_MOV_CRX);
9334 }
9335 else
9336 {
9337 if (pDbgState->fClearCr0Mask)
9338 {
9339 pDbgState->fClearCr0Mask = false;
9340 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
9341 }
9342 if (pDbgState->fClearCr4Mask)
9343 {
9344 pDbgState->fClearCr4Mask = false;
9345 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR4);
9346 }
9347 }
9348 SET_ONLY_XBM_IF_EITHER_EN( EXIT_CRX_READ, VMX_EXIT_MOV_CRX);
9349 SET_ONLY_XBM_IF_EITHER_EN( EXIT_CRX_WRITE, VMX_EXIT_MOV_CRX);
9350
9351 if ( IS_EITHER_ENABLED(pVM, INSTR_DRX_READ)
9352 || IS_EITHER_ENABLED(pVM, INSTR_DRX_WRITE))
9353 {
9354 /** @todo later, need to fix handler as it assumes this won't usually happen. */
9355 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_MOV_DRX);
9356 }
9357 SET_ONLY_XBM_IF_EITHER_EN( EXIT_DRX_READ, VMX_EXIT_MOV_DRX);
9358 SET_ONLY_XBM_IF_EITHER_EN( EXIT_DRX_WRITE, VMX_EXIT_MOV_DRX);
9359
9360 SET_CPEU_XBM_IF_EITHER_EN(INSTR_RDMSR, VMX_EXIT_RDMSR, VMX_PROC_CTLS_USE_MSR_BITMAPS); /* risky clearing this? */
9361 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDMSR, VMX_EXIT_RDMSR);
9362 SET_CPEU_XBM_IF_EITHER_EN(INSTR_WRMSR, VMX_EXIT_WRMSR, VMX_PROC_CTLS_USE_MSR_BITMAPS);
9363 SET_ONLY_XBM_IF_EITHER_EN( EXIT_WRMSR, VMX_EXIT_WRMSR);
9364 SET_CPE1_XBM_IF_EITHER_EN(INSTR_MWAIT, VMX_EXIT_MWAIT, VMX_PROC_CTLS_MWAIT_EXIT); /* paranoia */
9365 SET_ONLY_XBM_IF_EITHER_EN( EXIT_MWAIT, VMX_EXIT_MWAIT);
9366 SET_CPE1_XBM_IF_EITHER_EN(INSTR_MONITOR, VMX_EXIT_MONITOR, VMX_PROC_CTLS_MONITOR_EXIT); /* paranoia */
9367 SET_ONLY_XBM_IF_EITHER_EN( EXIT_MONITOR, VMX_EXIT_MONITOR);
9368#if 0 /** @todo too slow, fix handler. */
9369 SET_CPE1_XBM_IF_EITHER_EN(INSTR_PAUSE, VMX_EXIT_PAUSE, VMX_PROC_CTLS_PAUSE_EXIT);
9370#endif
9371 SET_ONLY_XBM_IF_EITHER_EN( EXIT_PAUSE, VMX_EXIT_PAUSE);
9372
9373 if ( IS_EITHER_ENABLED(pVM, INSTR_SGDT)
9374 || IS_EITHER_ENABLED(pVM, INSTR_SIDT)
9375 || IS_EITHER_ENABLED(pVM, INSTR_LGDT)
9376 || IS_EITHER_ENABLED(pVM, INSTR_LIDT))
9377 {
9378 pDbgState->fCpe2Extra |= VMX_PROC_CTLS2_DESC_TABLE_EXIT;
9379 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_GDTR_IDTR_ACCESS);
9380 }
9381 SET_ONLY_XBM_IF_EITHER_EN( EXIT_SGDT, VMX_EXIT_GDTR_IDTR_ACCESS);
9382 SET_ONLY_XBM_IF_EITHER_EN( EXIT_SIDT, VMX_EXIT_GDTR_IDTR_ACCESS);
9383 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LGDT, VMX_EXIT_GDTR_IDTR_ACCESS);
9384 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LIDT, VMX_EXIT_GDTR_IDTR_ACCESS);
9385
9386 if ( IS_EITHER_ENABLED(pVM, INSTR_SLDT)
9387 || IS_EITHER_ENABLED(pVM, INSTR_STR)
9388 || IS_EITHER_ENABLED(pVM, INSTR_LLDT)
9389 || IS_EITHER_ENABLED(pVM, INSTR_LTR))
9390 {
9391 pDbgState->fCpe2Extra |= VMX_PROC_CTLS2_DESC_TABLE_EXIT;
9392 ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_LDTR_TR_ACCESS);
9393 }
9394 SET_ONLY_XBM_IF_EITHER_EN( EXIT_SLDT, VMX_EXIT_LDTR_TR_ACCESS);
9395 SET_ONLY_XBM_IF_EITHER_EN( EXIT_STR, VMX_EXIT_LDTR_TR_ACCESS);
9396 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LLDT, VMX_EXIT_LDTR_TR_ACCESS);
9397 SET_ONLY_XBM_IF_EITHER_EN( EXIT_LTR, VMX_EXIT_LDTR_TR_ACCESS);
9398
9399 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_INVEPT, VMX_EXIT_INVEPT); /* unconditional */
9400 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVEPT, VMX_EXIT_INVEPT);
9401 SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDTSCP, VMX_EXIT_RDTSCP, VMX_PROC_CTLS_RDTSC_EXIT);
9402 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDTSCP, VMX_EXIT_RDTSCP);
9403 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_INVVPID, VMX_EXIT_INVVPID); /* unconditional */
9404 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVVPID, VMX_EXIT_INVVPID);
9405 SET_CPE2_XBM_IF_EITHER_EN(INSTR_WBINVD, VMX_EXIT_WBINVD, VMX_PROC_CTLS2_WBINVD_EXIT);
9406 SET_ONLY_XBM_IF_EITHER_EN( EXIT_WBINVD, VMX_EXIT_WBINVD);
9407 SET_ONLY_XBM_IF_EITHER_EN(INSTR_XSETBV, VMX_EXIT_XSETBV); /* unconditional */
9408 SET_ONLY_XBM_IF_EITHER_EN( EXIT_XSETBV, VMX_EXIT_XSETBV);
9409 SET_CPE2_XBM_IF_EITHER_EN(INSTR_RDRAND, VMX_EXIT_RDRAND, VMX_PROC_CTLS2_RDRAND_EXIT);
9410 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDRAND, VMX_EXIT_RDRAND);
9411 SET_CPE1_XBM_IF_EITHER_EN(INSTR_VMX_INVPCID, VMX_EXIT_INVPCID, VMX_PROC_CTLS_INVLPG_EXIT);
9412 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVPCID, VMX_EXIT_INVPCID);
9413 SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMFUNC, VMX_EXIT_VMFUNC); /* unconditional for the current setup */
9414 SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMFUNC, VMX_EXIT_VMFUNC);
9415 SET_CPE2_XBM_IF_EITHER_EN(INSTR_RDSEED, VMX_EXIT_RDSEED, VMX_PROC_CTLS2_RDSEED_EXIT);
9416 SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDSEED, VMX_EXIT_RDSEED);
9417 SET_ONLY_XBM_IF_EITHER_EN(INSTR_XSAVES, VMX_EXIT_XSAVES); /* unconditional (enabled by host, guest cfg) */
9418 SET_ONLY_XBM_IF_EITHER_EN(EXIT_XSAVES, VMX_EXIT_XSAVES);
9419 SET_ONLY_XBM_IF_EITHER_EN(INSTR_XRSTORS, VMX_EXIT_XRSTORS); /* unconditional (enabled by host, guest cfg) */
9420 SET_ONLY_XBM_IF_EITHER_EN( EXIT_XRSTORS, VMX_EXIT_XRSTORS);
9421
9422#undef IS_EITHER_ENABLED
9423#undef SET_ONLY_XBM_IF_EITHER_EN
9424#undef SET_CPE1_XBM_IF_EITHER_EN
9425#undef SET_CPEU_XBM_IF_EITHER_EN
9426#undef SET_CPE2_XBM_IF_EITHER_EN
9427
9428 /*
9429 * Sanitize the control stuff.
9430 */
9431 pDbgState->fCpe2Extra &= pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1;
9432 if (pDbgState->fCpe2Extra)
9433 pDbgState->fCpe1Extra |= VMX_PROC_CTLS_USE_SECONDARY_CTLS;
9434 pDbgState->fCpe1Extra &= pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1;
9435 pDbgState->fCpe1Unwanted &= ~pVM->hm.s.vmx.Msrs.ProcCtls.n.disallowed0;
9436 if (pVCpu->hm.s.fDebugWantRdTscExit != RT_BOOL(pDbgState->fCpe1Extra & VMX_PROC_CTLS_RDTSC_EXIT))
9437 {
9438 pVCpu->hm.s.fDebugWantRdTscExit ^= true;
9439 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
9440 }
9441
9442 Log6(("HM: debug state: cpe1=%#RX32 cpeu=%#RX32 cpe2=%#RX32%s%s\n",
9443 pDbgState->fCpe1Extra, pDbgState->fCpe1Unwanted, pDbgState->fCpe2Extra,
9444 pDbgState->fClearCr0Mask ? " clr-cr0" : "",
9445 pDbgState->fClearCr4Mask ? " clr-cr4" : ""));
9446}
9447
9448
9449/**
9450 * Fires off DBGF events and dtrace probes for a VM-exit, when it's
9451 * appropriate.
9452 *
9453 * The caller has checked the VM-exit against the
9454 * VMXRUNDBGSTATE::bmExitsToCheck bitmap. The caller has checked for NMIs
9455 * already, so we don't have to do that either.
9456 *
9457 * @returns Strict VBox status code (i.e. informational status codes too).
9458 * @param pVCpu The cross context virtual CPU structure.
9459 * @param pVmxTransient Pointer to the VMX-transient structure.
9460 * @param uExitReason The VM-exit reason.
9461 *
9462 * @remarks The name of this function is displayed by dtrace, so keep it short
9463 * and to the point. No longer than 33 chars long, please.
9464 */
9465static VBOXSTRICTRC hmR0VmxHandleExitDtraceEvents(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, uint32_t uExitReason)
9466{
9467 /*
9468 * Translate the event into a DBGF event (enmEvent + uEventArg) and at the
9469 * same time check whether any corresponding Dtrace event is enabled (fDtrace).
9470 *
9471 * Note! This is the reverse operation of what hmR0VmxPreRunGuestDebugStateUpdate
9472 * does. Must add/change/remove both places. Same ordering, please.
9473 *
9474 * Added/removed events must also be reflected in the next section
9475 * where we dispatch dtrace events.
9476 */
9477 bool fDtrace1 = false;
9478 bool fDtrace2 = false;
9479 DBGFEVENTTYPE enmEvent1 = DBGFEVENT_END;
9480 DBGFEVENTTYPE enmEvent2 = DBGFEVENT_END;
9481 uint32_t uEventArg = 0;
9482#define SET_EXIT(a_EventSubName) \
9483 do { \
9484 enmEvent2 = RT_CONCAT(DBGFEVENT_EXIT_, a_EventSubName); \
9485 fDtrace2 = RT_CONCAT3(VBOXVMM_EXIT_, a_EventSubName, _ENABLED)(); \
9486 } while (0)
9487#define SET_BOTH(a_EventSubName) \
9488 do { \
9489 enmEvent1 = RT_CONCAT(DBGFEVENT_INSTR_, a_EventSubName); \
9490 enmEvent2 = RT_CONCAT(DBGFEVENT_EXIT_, a_EventSubName); \
9491 fDtrace1 = RT_CONCAT3(VBOXVMM_INSTR_, a_EventSubName, _ENABLED)(); \
9492 fDtrace2 = RT_CONCAT3(VBOXVMM_EXIT_, a_EventSubName, _ENABLED)(); \
9493 } while (0)
9494 switch (uExitReason)
9495 {
9496 case VMX_EXIT_MTF:
9497 return hmR0VmxExitMtf(pVCpu, pVmxTransient);
9498
9499 case VMX_EXIT_XCPT_OR_NMI:
9500 {
9501 uint8_t const idxVector = VMX_EXIT_INT_INFO_VECTOR(pVmxTransient->uExitIntInfo);
9502 switch (VMX_EXIT_INT_INFO_TYPE(pVmxTransient->uExitIntInfo))
9503 {
9504 case VMX_EXIT_INT_INFO_TYPE_HW_XCPT:
9505 case VMX_EXIT_INT_INFO_TYPE_SW_XCPT:
9506 case VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT:
9507 if (idxVector <= (unsigned)(DBGFEVENT_XCPT_LAST - DBGFEVENT_XCPT_FIRST))
9508 {
9509 if (VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(pVmxTransient->uExitIntInfo))
9510 {
9511 hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
9512 uEventArg = pVmxTransient->uExitIntErrorCode;
9513 }
9514 enmEvent1 = (DBGFEVENTTYPE)(DBGFEVENT_XCPT_FIRST + idxVector);
9515 switch (enmEvent1)
9516 {
9517 case DBGFEVENT_XCPT_DE: fDtrace1 = VBOXVMM_XCPT_DE_ENABLED(); break;
9518 case DBGFEVENT_XCPT_DB: fDtrace1 = VBOXVMM_XCPT_DB_ENABLED(); break;
9519 case DBGFEVENT_XCPT_BP: fDtrace1 = VBOXVMM_XCPT_BP_ENABLED(); break;
9520 case DBGFEVENT_XCPT_OF: fDtrace1 = VBOXVMM_XCPT_OF_ENABLED(); break;
9521 case DBGFEVENT_XCPT_BR: fDtrace1 = VBOXVMM_XCPT_BR_ENABLED(); break;
9522 case DBGFEVENT_XCPT_UD: fDtrace1 = VBOXVMM_XCPT_UD_ENABLED(); break;
9523 case DBGFEVENT_XCPT_NM: fDtrace1 = VBOXVMM_XCPT_NM_ENABLED(); break;
9524 case DBGFEVENT_XCPT_DF: fDtrace1 = VBOXVMM_XCPT_DF_ENABLED(); break;
9525 case DBGFEVENT_XCPT_TS: fDtrace1 = VBOXVMM_XCPT_TS_ENABLED(); break;
9526 case DBGFEVENT_XCPT_NP: fDtrace1 = VBOXVMM_XCPT_NP_ENABLED(); break;
9527 case DBGFEVENT_XCPT_SS: fDtrace1 = VBOXVMM_XCPT_SS_ENABLED(); break;
9528 case DBGFEVENT_XCPT_GP: fDtrace1 = VBOXVMM_XCPT_GP_ENABLED(); break;
9529 case DBGFEVENT_XCPT_PF: fDtrace1 = VBOXVMM_XCPT_PF_ENABLED(); break;
9530 case DBGFEVENT_XCPT_MF: fDtrace1 = VBOXVMM_XCPT_MF_ENABLED(); break;
9531 case DBGFEVENT_XCPT_AC: fDtrace1 = VBOXVMM_XCPT_AC_ENABLED(); break;
9532 case DBGFEVENT_XCPT_XF: fDtrace1 = VBOXVMM_XCPT_XF_ENABLED(); break;
9533 case DBGFEVENT_XCPT_VE: fDtrace1 = VBOXVMM_XCPT_VE_ENABLED(); break;
9534 case DBGFEVENT_XCPT_SX: fDtrace1 = VBOXVMM_XCPT_SX_ENABLED(); break;
9535 default: break;
9536 }
9537 }
9538 else
9539 AssertFailed();
9540 break;
9541
9542 case VMX_EXIT_INT_INFO_TYPE_SW_INT:
9543 uEventArg = idxVector;
9544 enmEvent1 = DBGFEVENT_INTERRUPT_SOFTWARE;
9545 fDtrace1 = VBOXVMM_INT_SOFTWARE_ENABLED();
9546 break;
9547 }
9548 break;
9549 }
9550
9551 case VMX_EXIT_TRIPLE_FAULT:
9552 enmEvent1 = DBGFEVENT_TRIPLE_FAULT;
9553 //fDtrace1 = VBOXVMM_EXIT_TRIPLE_FAULT_ENABLED();
9554 break;
9555 case VMX_EXIT_TASK_SWITCH: SET_EXIT(TASK_SWITCH); break;
9556 case VMX_EXIT_EPT_VIOLATION: SET_EXIT(VMX_EPT_VIOLATION); break;
9557 case VMX_EXIT_EPT_MISCONFIG: SET_EXIT(VMX_EPT_MISCONFIG); break;
9558 case VMX_EXIT_APIC_ACCESS: SET_EXIT(VMX_VAPIC_ACCESS); break;
9559 case VMX_EXIT_APIC_WRITE: SET_EXIT(VMX_VAPIC_WRITE); break;
9560
9561 /* Instruction specific VM-exits: */
9562 case VMX_EXIT_CPUID: SET_BOTH(CPUID); break;
9563 case VMX_EXIT_GETSEC: SET_BOTH(GETSEC); break;
9564 case VMX_EXIT_HLT: SET_BOTH(HALT); break;
9565 case VMX_EXIT_INVD: SET_BOTH(INVD); break;
9566 case VMX_EXIT_INVLPG: SET_BOTH(INVLPG); break;
9567 case VMX_EXIT_RDPMC: SET_BOTH(RDPMC); break;
9568 case VMX_EXIT_RDTSC: SET_BOTH(RDTSC); break;
9569 case VMX_EXIT_RSM: SET_BOTH(RSM); break;
9570 case VMX_EXIT_VMCALL: SET_BOTH(VMM_CALL); break;
9571 case VMX_EXIT_VMCLEAR: SET_BOTH(VMX_VMCLEAR); break;
9572 case VMX_EXIT_VMLAUNCH: SET_BOTH(VMX_VMLAUNCH); break;
9573 case VMX_EXIT_VMPTRLD: SET_BOTH(VMX_VMPTRLD); break;
9574 case VMX_EXIT_VMPTRST: SET_BOTH(VMX_VMPTRST); break;
9575 case VMX_EXIT_VMREAD: SET_BOTH(VMX_VMREAD); break;
9576 case VMX_EXIT_VMRESUME: SET_BOTH(VMX_VMRESUME); break;
9577 case VMX_EXIT_VMWRITE: SET_BOTH(VMX_VMWRITE); break;
9578 case VMX_EXIT_VMXOFF: SET_BOTH(VMX_VMXOFF); break;
9579 case VMX_EXIT_VMXON: SET_BOTH(VMX_VMXON); break;
9580 case VMX_EXIT_MOV_CRX:
9581 hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
9582 if (VMX_EXIT_QUAL_CRX_ACCESS(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_CRX_ACCESS_READ)
9583 SET_BOTH(CRX_READ);
9584 else
9585 SET_BOTH(CRX_WRITE);
9586 uEventArg = VMX_EXIT_QUAL_CRX_REGISTER(pVmxTransient->uExitQual);
9587 break;
9588 case VMX_EXIT_MOV_DRX:
9589 hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
9590 if ( VMX_EXIT_QUAL_DRX_DIRECTION(pVmxTransient->uExitQual)
9591 == VMX_EXIT_QUAL_DRX_DIRECTION_READ)
9592 SET_BOTH(DRX_READ);
9593 else
9594 SET_BOTH(DRX_WRITE);
9595 uEventArg = VMX_EXIT_QUAL_DRX_REGISTER(pVmxTransient->uExitQual);
9596 break;
9597 case VMX_EXIT_RDMSR: SET_BOTH(RDMSR); break;
9598 case VMX_EXIT_WRMSR: SET_BOTH(WRMSR); break;
9599 case VMX_EXIT_MWAIT: SET_BOTH(MWAIT); break;
9600 case VMX_EXIT_MONITOR: SET_BOTH(MONITOR); break;
9601 case VMX_EXIT_PAUSE: SET_BOTH(PAUSE); break;
9602 case VMX_EXIT_GDTR_IDTR_ACCESS:
9603 hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
9604 switch (RT_BF_GET(pVmxTransient->ExitInstrInfo.u, VMX_BF_XDTR_INSINFO_INSTR_ID))
9605 {
9606 case VMX_XDTR_INSINFO_II_SGDT: SET_BOTH(SGDT); break;
9607 case VMX_XDTR_INSINFO_II_SIDT: SET_BOTH(SIDT); break;
9608 case VMX_XDTR_INSINFO_II_LGDT: SET_BOTH(LGDT); break;
9609 case VMX_XDTR_INSINFO_II_LIDT: SET_BOTH(LIDT); break;
9610 }
9611 break;
9612
9613 case VMX_EXIT_LDTR_TR_ACCESS:
9614 hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
9615 switch (RT_BF_GET(pVmxTransient->ExitInstrInfo.u, VMX_BF_YYTR_INSINFO_INSTR_ID))
9616 {
9617 case VMX_YYTR_INSINFO_II_SLDT: SET_BOTH(SLDT); break;
9618 case VMX_YYTR_INSINFO_II_STR: SET_BOTH(STR); break;
9619 case VMX_YYTR_INSINFO_II_LLDT: SET_BOTH(LLDT); break;
9620 case VMX_YYTR_INSINFO_II_LTR: SET_BOTH(LTR); break;
9621 }
9622 break;
9623
9624 case VMX_EXIT_INVEPT: SET_BOTH(VMX_INVEPT); break;
9625 case VMX_EXIT_RDTSCP: SET_BOTH(RDTSCP); break;
9626 case VMX_EXIT_INVVPID: SET_BOTH(VMX_INVVPID); break;
9627 case VMX_EXIT_WBINVD: SET_BOTH(WBINVD); break;
9628 case VMX_EXIT_XSETBV: SET_BOTH(XSETBV); break;
9629 case VMX_EXIT_RDRAND: SET_BOTH(RDRAND); break;
9630 case VMX_EXIT_INVPCID: SET_BOTH(VMX_INVPCID); break;
9631 case VMX_EXIT_VMFUNC: SET_BOTH(VMX_VMFUNC); break;
9632 case VMX_EXIT_RDSEED: SET_BOTH(RDSEED); break;
9633 case VMX_EXIT_XSAVES: SET_BOTH(XSAVES); break;
9634 case VMX_EXIT_XRSTORS: SET_BOTH(XRSTORS); break;
9635
9636 /* Events that aren't relevant at this point. */
9637 case VMX_EXIT_EXT_INT:
9638 case VMX_EXIT_INT_WINDOW:
9639 case VMX_EXIT_NMI_WINDOW:
9640 case VMX_EXIT_TPR_BELOW_THRESHOLD:
9641 case VMX_EXIT_PREEMPT_TIMER:
9642 case VMX_EXIT_IO_INSTR:
9643 break;
9644
9645 /* Errors and unexpected events. */
9646 case VMX_EXIT_INIT_SIGNAL:
9647 case VMX_EXIT_SIPI:
9648 case VMX_EXIT_IO_SMI:
9649 case VMX_EXIT_SMI:
9650 case VMX_EXIT_ERR_INVALID_GUEST_STATE:
9651 case VMX_EXIT_ERR_MSR_LOAD:
9652 case VMX_EXIT_ERR_MACHINE_CHECK:
9653 break;
9654
9655 default:
9656 AssertMsgFailed(("Unexpected VM-exit=%#x\n", uExitReason));
9657 break;
9658 }
9659#undef SET_BOTH
9660#undef SET_EXIT
9661
9662 /*
9663 * Dtrace tracepoints go first. We do them here at once so we don't
9664 * have to copy the guest state saving and stuff a few dozen times.
9665 * Down side is that we've got to repeat the switch, though this time
9666 * we use enmEvent since the probes are a subset of what DBGF does.
9667 */
9668 if (fDtrace1 || fDtrace2)
9669 {
9670 hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
9671 hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
9672 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
9673 switch (enmEvent1)
9674 {
9675 /** @todo consider which extra parameters would be helpful for each probe. */
9676 case DBGFEVENT_END: break;
9677 case DBGFEVENT_XCPT_DE: VBOXVMM_XCPT_DE(pVCpu, pCtx); break;
9678 case DBGFEVENT_XCPT_DB: VBOXVMM_XCPT_DB(pVCpu, pCtx, pCtx->dr[6]); break;
9679 case DBGFEVENT_XCPT_BP: VBOXVMM_XCPT_BP(pVCpu, pCtx); break;
9680 case DBGFEVENT_XCPT_OF: VBOXVMM_XCPT_OF(pVCpu, pCtx); break;
9681 case DBGFEVENT_XCPT_BR: VBOXVMM_XCPT_BR(pVCpu, pCtx); break;
9682 case DBGFEVENT_XCPT_UD: VBOXVMM_XCPT_UD(pVCpu, pCtx); break;
9683 case DBGFEVENT_XCPT_NM: VBOXVMM_XCPT_NM(pVCpu, pCtx); break;
9684 case DBGFEVENT_XCPT_DF: VBOXVMM_XCPT_DF(pVCpu, pCtx); break;
9685 case DBGFEVENT_XCPT_TS: VBOXVMM_XCPT_TS(pVCpu, pCtx, uEventArg); break;
9686 case DBGFEVENT_XCPT_NP: VBOXVMM_XCPT_NP(pVCpu, pCtx, uEventArg); break;
9687 case DBGFEVENT_XCPT_SS: VBOXVMM_XCPT_SS(pVCpu, pCtx, uEventArg); break;
9688 case DBGFEVENT_XCPT_GP: VBOXVMM_XCPT_GP(pVCpu, pCtx, uEventArg); break;
9689 case DBGFEVENT_XCPT_PF: VBOXVMM_XCPT_PF(pVCpu, pCtx, uEventArg, pCtx->cr2); break;
9690 case DBGFEVENT_XCPT_MF: VBOXVMM_XCPT_MF(pVCpu, pCtx); break;
9691 case DBGFEVENT_XCPT_AC: VBOXVMM_XCPT_AC(pVCpu, pCtx); break;
9692 case DBGFEVENT_XCPT_XF: VBOXVMM_XCPT_XF(pVCpu, pCtx); break;
9693 case DBGFEVENT_XCPT_VE: VBOXVMM_XCPT_VE(pVCpu, pCtx); break;
9694 case DBGFEVENT_XCPT_SX: VBOXVMM_XCPT_SX(pVCpu, pCtx, uEventArg); break;
9695 case DBGFEVENT_INTERRUPT_SOFTWARE: VBOXVMM_INT_SOFTWARE(pVCpu, pCtx, (uint8_t)uEventArg); break;
9696 case DBGFEVENT_INSTR_CPUID: VBOXVMM_INSTR_CPUID(pVCpu, pCtx, pCtx->eax, pCtx->ecx); break;
9697 case DBGFEVENT_INSTR_GETSEC: VBOXVMM_INSTR_GETSEC(pVCpu, pCtx); break;
9698 case DBGFEVENT_INSTR_HALT: VBOXVMM_INSTR_HALT(pVCpu, pCtx); break;
9699 case DBGFEVENT_INSTR_INVD: VBOXVMM_INSTR_INVD(pVCpu, pCtx); break;
9700 case DBGFEVENT_INSTR_INVLPG: VBOXVMM_INSTR_INVLPG(pVCpu, pCtx); break;
9701 case DBGFEVENT_INSTR_RDPMC: VBOXVMM_INSTR_RDPMC(pVCpu, pCtx); break;
9702 case DBGFEVENT_INSTR_RDTSC: VBOXVMM_INSTR_RDTSC(pVCpu, pCtx); break;
9703 case DBGFEVENT_INSTR_RSM: VBOXVMM_INSTR_RSM(pVCpu, pCtx); break;
9704 case DBGFEVENT_INSTR_CRX_READ: VBOXVMM_INSTR_CRX_READ(pVCpu, pCtx, (uint8_t)uEventArg); break;
9705 case DBGFEVENT_INSTR_CRX_WRITE: VBOXVMM_INSTR_CRX_WRITE(pVCpu, pCtx, (uint8_t)uEventArg); break;
9706 case DBGFEVENT_INSTR_DRX_READ: VBOXVMM_INSTR_DRX_READ(pVCpu, pCtx, (uint8_t)uEventArg); break;
9707 case DBGFEVENT_INSTR_DRX_WRITE: VBOXVMM_INSTR_DRX_WRITE(pVCpu, pCtx, (uint8_t)uEventArg); break;
9708 case DBGFEVENT_INSTR_RDMSR: VBOXVMM_INSTR_RDMSR(pVCpu, pCtx, pCtx->ecx); break;
9709 case DBGFEVENT_INSTR_WRMSR: VBOXVMM_INSTR_WRMSR(pVCpu, pCtx, pCtx->ecx,
9710 RT_MAKE_U64(pCtx->eax, pCtx->edx)); break;
9711 case DBGFEVENT_INSTR_MWAIT: VBOXVMM_INSTR_MWAIT(pVCpu, pCtx); break;
9712 case DBGFEVENT_INSTR_MONITOR: VBOXVMM_INSTR_MONITOR(pVCpu, pCtx); break;
9713 case DBGFEVENT_INSTR_PAUSE: VBOXVMM_INSTR_PAUSE(pVCpu, pCtx); break;
9714 case DBGFEVENT_INSTR_SGDT: VBOXVMM_INSTR_SGDT(pVCpu, pCtx); break;
9715 case DBGFEVENT_INSTR_SIDT: VBOXVMM_INSTR_SIDT(pVCpu, pCtx); break;
9716 case DBGFEVENT_INSTR_LGDT: VBOXVMM_INSTR_LGDT(pVCpu, pCtx); break;
9717 case DBGFEVENT_INSTR_LIDT: VBOXVMM_INSTR_LIDT(pVCpu, pCtx); break;
9718 case DBGFEVENT_INSTR_SLDT: VBOXVMM_INSTR_SLDT(pVCpu, pCtx); break;
9719 case DBGFEVENT_INSTR_STR: VBOXVMM_INSTR_STR(pVCpu, pCtx); break;
9720 case DBGFEVENT_INSTR_LLDT: VBOXVMM_INSTR_LLDT(pVCpu, pCtx); break;
9721 case DBGFEVENT_INSTR_LTR: VBOXVMM_INSTR_LTR(pVCpu, pCtx); break;
9722 case DBGFEVENT_INSTR_RDTSCP: VBOXVMM_INSTR_RDTSCP(pVCpu, pCtx); break;
9723 case DBGFEVENT_INSTR_WBINVD: VBOXVMM_INSTR_WBINVD(pVCpu, pCtx); break;
9724 case DBGFEVENT_INSTR_XSETBV: VBOXVMM_INSTR_XSETBV(pVCpu, pCtx); break;
9725 case DBGFEVENT_INSTR_RDRAND: VBOXVMM_INSTR_RDRAND(pVCpu, pCtx); break;
9726 case DBGFEVENT_INSTR_RDSEED: VBOXVMM_INSTR_RDSEED(pVCpu, pCtx); break;
9727 case DBGFEVENT_INSTR_XSAVES: VBOXVMM_INSTR_XSAVES(pVCpu, pCtx); break;
9728 case DBGFEVENT_INSTR_XRSTORS: VBOXVMM_INSTR_XRSTORS(pVCpu, pCtx); break;
9729 case DBGFEVENT_INSTR_VMM_CALL: VBOXVMM_INSTR_VMM_CALL(pVCpu, pCtx); break;
9730 case DBGFEVENT_INSTR_VMX_VMCLEAR: VBOXVMM_INSTR_VMX_VMCLEAR(pVCpu, pCtx); break;
9731 case DBGFEVENT_INSTR_VMX_VMLAUNCH: VBOXVMM_INSTR_VMX_VMLAUNCH(pVCpu, pCtx); break;
9732 case DBGFEVENT_INSTR_VMX_VMPTRLD: VBOXVMM_INSTR_VMX_VMPTRLD(pVCpu, pCtx); break;
9733 case DBGFEVENT_INSTR_VMX_VMPTRST: VBOXVMM_INSTR_VMX_VMPTRST(pVCpu, pCtx); break;
9734 case DBGFEVENT_INSTR_VMX_VMREAD: VBOXVMM_INSTR_VMX_VMREAD(pVCpu, pCtx); break;
9735 case DBGFEVENT_INSTR_VMX_VMRESUME: VBOXVMM_INSTR_VMX_VMRESUME(pVCpu, pCtx); break;
9736 case DBGFEVENT_INSTR_VMX_VMWRITE: VBOXVMM_INSTR_VMX_VMWRITE(pVCpu, pCtx); break;
9737 case DBGFEVENT_INSTR_VMX_VMXOFF: VBOXVMM_INSTR_VMX_VMXOFF(pVCpu, pCtx); break;
9738 case DBGFEVENT_INSTR_VMX_VMXON: VBOXVMM_INSTR_VMX_VMXON(pVCpu, pCtx); break;
9739 case DBGFEVENT_INSTR_VMX_INVEPT: VBOXVMM_INSTR_VMX_INVEPT(pVCpu, pCtx); break;
9740 case DBGFEVENT_INSTR_VMX_INVVPID: VBOXVMM_INSTR_VMX_INVVPID(pVCpu, pCtx); break;
9741 case DBGFEVENT_INSTR_VMX_INVPCID: VBOXVMM_INSTR_VMX_INVPCID(pVCpu, pCtx); break;
9742 case DBGFEVENT_INSTR_VMX_VMFUNC: VBOXVMM_INSTR_VMX_VMFUNC(pVCpu, pCtx); break;
9743 default: AssertMsgFailed(("enmEvent1=%d uExitReason=%d\n", enmEvent1, uExitReason)); break;
9744 }
9745 switch (enmEvent2)
9746 {
9747 /** @todo consider which extra parameters would be helpful for each probe. */
9748 case DBGFEVENT_END: break;
9749 case DBGFEVENT_EXIT_TASK_SWITCH: VBOXVMM_EXIT_TASK_SWITCH(pVCpu, pCtx); break;
9750 case DBGFEVENT_EXIT_CPUID: VBOXVMM_EXIT_CPUID(pVCpu, pCtx, pCtx->eax, pCtx->ecx); break;
9751 case DBGFEVENT_EXIT_GETSEC: VBOXVMM_EXIT_GETSEC(pVCpu, pCtx); break;
9752 case DBGFEVENT_EXIT_HALT: VBOXVMM_EXIT_HALT(pVCpu, pCtx); break;
9753 case DBGFEVENT_EXIT_INVD: VBOXVMM_EXIT_INVD(pVCpu, pCtx); break;
9754 case DBGFEVENT_EXIT_INVLPG: VBOXVMM_EXIT_INVLPG(pVCpu, pCtx); break;
9755 case DBGFEVENT_EXIT_RDPMC: VBOXVMM_EXIT_RDPMC(pVCpu, pCtx); break;
9756 case DBGFEVENT_EXIT_RDTSC: VBOXVMM_EXIT_RDTSC(pVCpu, pCtx); break;
9757 case DBGFEVENT_EXIT_RSM: VBOXVMM_EXIT_RSM(pVCpu, pCtx); break;
9758 case DBGFEVENT_EXIT_CRX_READ: VBOXVMM_EXIT_CRX_READ(pVCpu, pCtx, (uint8_t)uEventArg); break;
9759 case DBGFEVENT_EXIT_CRX_WRITE: VBOXVMM_EXIT_CRX_WRITE(pVCpu, pCtx, (uint8_t)uEventArg); break;
9760 case DBGFEVENT_EXIT_DRX_READ: VBOXVMM_EXIT_DRX_READ(pVCpu, pCtx, (uint8_t)uEventArg); break;
9761 case DBGFEVENT_EXIT_DRX_WRITE: VBOXVMM_EXIT_DRX_WRITE(pVCpu, pCtx, (uint8_t)uEventArg); break;
9762 case DBGFEVENT_EXIT_RDMSR: VBOXVMM_EXIT_RDMSR(pVCpu, pCtx, pCtx->ecx); break;
9763 case DBGFEVENT_EXIT_WRMSR: VBOXVMM_EXIT_WRMSR(pVCpu, pCtx, pCtx->ecx,
9764 RT_MAKE_U64(pCtx->eax, pCtx->edx)); break;
9765 case DBGFEVENT_EXIT_MWAIT: VBOXVMM_EXIT_MWAIT(pVCpu, pCtx); break;
9766 case DBGFEVENT_EXIT_MONITOR: VBOXVMM_EXIT_MONITOR(pVCpu, pCtx); break;
9767 case DBGFEVENT_EXIT_PAUSE: VBOXVMM_EXIT_PAUSE(pVCpu, pCtx); break;
9768 case DBGFEVENT_EXIT_SGDT: VBOXVMM_EXIT_SGDT(pVCpu, pCtx); break;
9769 case DBGFEVENT_EXIT_SIDT: VBOXVMM_EXIT_SIDT(pVCpu, pCtx); break;
9770 case DBGFEVENT_EXIT_LGDT: VBOXVMM_EXIT_LGDT(pVCpu, pCtx); break;
9771 case DBGFEVENT_EXIT_LIDT: VBOXVMM_EXIT_LIDT(pVCpu, pCtx); break;
9772 case DBGFEVENT_EXIT_SLDT: VBOXVMM_EXIT_SLDT(pVCpu, pCtx); break;
9773 case DBGFEVENT_EXIT_STR: VBOXVMM_EXIT_STR(pVCpu, pCtx); break;
9774 case DBGFEVENT_EXIT_LLDT: VBOXVMM_EXIT_LLDT(pVCpu, pCtx); break;
9775 case DBGFEVENT_EXIT_LTR: VBOXVMM_EXIT_LTR(pVCpu, pCtx); break;
9776 case DBGFEVENT_EXIT_RDTSCP: VBOXVMM_EXIT_RDTSCP(pVCpu, pCtx); break;
9777 case DBGFEVENT_EXIT_WBINVD: VBOXVMM_EXIT_WBINVD(pVCpu, pCtx); break;
9778 case DBGFEVENT_EXIT_XSETBV: VBOXVMM_EXIT_XSETBV(pVCpu, pCtx); break;
9779 case DBGFEVENT_EXIT_RDRAND: VBOXVMM_EXIT_RDRAND(pVCpu, pCtx); break;
9780 case DBGFEVENT_EXIT_RDSEED: VBOXVMM_EXIT_RDSEED(pVCpu, pCtx); break;
9781 case DBGFEVENT_EXIT_XSAVES: VBOXVMM_EXIT_XSAVES(pVCpu, pCtx); break;
9782 case DBGFEVENT_EXIT_XRSTORS: VBOXVMM_EXIT_XRSTORS(pVCpu, pCtx); break;
9783 case DBGFEVENT_EXIT_VMM_CALL: VBOXVMM_EXIT_VMM_CALL(pVCpu, pCtx); break;
9784 case DBGFEVENT_EXIT_VMX_VMCLEAR: VBOXVMM_EXIT_VMX_VMCLEAR(pVCpu, pCtx); break;
9785 case DBGFEVENT_EXIT_VMX_VMLAUNCH: VBOXVMM_EXIT_VMX_VMLAUNCH(pVCpu, pCtx); break;
9786 case DBGFEVENT_EXIT_VMX_VMPTRLD: VBOXVMM_EXIT_VMX_VMPTRLD(pVCpu, pCtx); break;
9787 case DBGFEVENT_EXIT_VMX_VMPTRST: VBOXVMM_EXIT_VMX_VMPTRST(pVCpu, pCtx); break;
9788 case DBGFEVENT_EXIT_VMX_VMREAD: VBOXVMM_EXIT_VMX_VMREAD(pVCpu, pCtx); break;
9789 case DBGFEVENT_EXIT_VMX_VMRESUME: VBOXVMM_EXIT_VMX_VMRESUME(pVCpu, pCtx); break;
9790 case DBGFEVENT_EXIT_VMX_VMWRITE: VBOXVMM_EXIT_VMX_VMWRITE(pVCpu, pCtx); break;
9791 case DBGFEVENT_EXIT_VMX_VMXOFF: VBOXVMM_EXIT_VMX_VMXOFF(pVCpu, pCtx); break;
9792 case DBGFEVENT_EXIT_VMX_VMXON: VBOXVMM_EXIT_VMX_VMXON(pVCpu, pCtx); break;
9793 case DBGFEVENT_EXIT_VMX_INVEPT: VBOXVMM_EXIT_VMX_INVEPT(pVCpu, pCtx); break;
9794 case DBGFEVENT_EXIT_VMX_INVVPID: VBOXVMM_EXIT_VMX_INVVPID(pVCpu, pCtx); break;
9795 case DBGFEVENT_EXIT_VMX_INVPCID: VBOXVMM_EXIT_VMX_INVPCID(pVCpu, pCtx); break;
9796 case DBGFEVENT_EXIT_VMX_VMFUNC: VBOXVMM_EXIT_VMX_VMFUNC(pVCpu, pCtx); break;
9797 case DBGFEVENT_EXIT_VMX_EPT_MISCONFIG: VBOXVMM_EXIT_VMX_EPT_MISCONFIG(pVCpu, pCtx); break;
9798 case DBGFEVENT_EXIT_VMX_EPT_VIOLATION: VBOXVMM_EXIT_VMX_EPT_VIOLATION(pVCpu, pCtx); break;
9799 case DBGFEVENT_EXIT_VMX_VAPIC_ACCESS: VBOXVMM_EXIT_VMX_VAPIC_ACCESS(pVCpu, pCtx); break;
9800 case DBGFEVENT_EXIT_VMX_VAPIC_WRITE: VBOXVMM_EXIT_VMX_VAPIC_WRITE(pVCpu, pCtx); break;
9801 default: AssertMsgFailed(("enmEvent2=%d uExitReason=%d\n", enmEvent2, uExitReason)); break;
9802 }
9803 }
9804
9805 /*
9806 * Fire of the DBGF event, if enabled (our check here is just a quick one,
9807 * the DBGF call will do a full check).
9808 *
9809 * Note! DBGF sets DBGFEVENT_INTERRUPT_SOFTWARE in the bitmap.
9810 * Note! If we have to events, we prioritize the first, i.e. the instruction
9811 * one, in order to avoid event nesting.
9812 */
9813 PVM pVM = pVCpu->CTX_SUFF(pVM);
9814 if ( enmEvent1 != DBGFEVENT_END
9815 && DBGF_IS_EVENT_ENABLED(pVM, enmEvent1))
9816 {
9817 HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RIP);
9818 VBOXSTRICTRC rcStrict = DBGFEventGenericWithArgs(pVM, pVCpu, enmEvent1, DBGFEVENTCTX_HM, 1, uEventArg);
9819 if (rcStrict != VINF_SUCCESS)
9820 return rcStrict;
9821 }
9822 else if ( enmEvent2 != DBGFEVENT_END
9823 && DBGF_IS_EVENT_ENABLED(pVM, enmEvent2))
9824 {
9825 HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RIP);
9826 VBOXSTRICTRC rcStrict = DBGFEventGenericWithArgs(pVM, pVCpu, enmEvent2, DBGFEVENTCTX_HM, 1, uEventArg);
9827 if (rcStrict != VINF_SUCCESS)
9828 return rcStrict;
9829 }
9830
9831 return VINF_SUCCESS;
9832}
9833
9834
9835/**
9836 * Single-stepping VM-exit filtering.
9837 *
9838 * This is preprocessing the VM-exits and deciding whether we've gotten far
9839 * enough to return VINF_EM_DBG_STEPPED already. If not, normal VM-exit
9840 * handling is performed.
9841 *
9842 * @returns Strict VBox status code (i.e. informational status codes too).
9843 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
9844 * @param pVmxTransient Pointer to the VMX-transient structure.
9845 * @param pDbgState The debug state.
9846 */
9847DECLINLINE(VBOXSTRICTRC) hmR0VmxRunDebugHandleExit(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, PVMXRUNDBGSTATE pDbgState)
9848{
9849 /*
9850 * Expensive (saves context) generic dtrace VM-exit probe.
9851 */
9852 uint32_t const uExitReason = pVmxTransient->uExitReason;
9853 if (!VBOXVMM_R0_HMVMX_VMEXIT_ENABLED())
9854 { /* more likely */ }
9855 else
9856 {
9857 hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
9858 int rc = hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
9859 AssertRC(rc);
9860 VBOXVMM_R0_HMVMX_VMEXIT(pVCpu, &pVCpu->cpum.GstCtx, pVmxTransient->uExitReason, pVmxTransient->uExitQual);
9861 }
9862
9863 /*
9864 * Check for host NMI, just to get that out of the way.
9865 */
9866 if (uExitReason != VMX_EXIT_XCPT_OR_NMI)
9867 { /* normally likely */ }
9868 else
9869 {
9870 int rc2 = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
9871 AssertRCReturn(rc2, rc2);
9872 uint32_t uIntType = VMX_EXIT_INT_INFO_TYPE(pVmxTransient->uExitIntInfo);
9873 if (uIntType == VMX_EXIT_INT_INFO_TYPE_NMI)
9874 return hmR0VmxExitXcptOrNmi(pVCpu, pVmxTransient);
9875 }
9876
9877 /*
9878 * Check for single stepping event if we're stepping.
9879 */
9880 if (pVCpu->hm.s.fSingleInstruction)
9881 {
9882 switch (uExitReason)
9883 {
9884 case VMX_EXIT_MTF:
9885 return hmR0VmxExitMtf(pVCpu, pVmxTransient);
9886
9887 /* Various events: */
9888 case VMX_EXIT_XCPT_OR_NMI:
9889 case VMX_EXIT_EXT_INT:
9890 case VMX_EXIT_TRIPLE_FAULT:
9891 case VMX_EXIT_INT_WINDOW:
9892 case VMX_EXIT_NMI_WINDOW:
9893 case VMX_EXIT_TASK_SWITCH:
9894 case VMX_EXIT_TPR_BELOW_THRESHOLD:
9895 case VMX_EXIT_APIC_ACCESS:
9896 case VMX_EXIT_EPT_VIOLATION:
9897 case VMX_EXIT_EPT_MISCONFIG:
9898 case VMX_EXIT_PREEMPT_TIMER:
9899
9900 /* Instruction specific VM-exits: */
9901 case VMX_EXIT_CPUID:
9902 case VMX_EXIT_GETSEC:
9903 case VMX_EXIT_HLT:
9904 case VMX_EXIT_INVD:
9905 case VMX_EXIT_INVLPG:
9906 case VMX_EXIT_RDPMC:
9907 case VMX_EXIT_RDTSC:
9908 case VMX_EXIT_RSM:
9909 case VMX_EXIT_VMCALL:
9910 case VMX_EXIT_VMCLEAR:
9911 case VMX_EXIT_VMLAUNCH:
9912 case VMX_EXIT_VMPTRLD:
9913 case VMX_EXIT_VMPTRST:
9914 case VMX_EXIT_VMREAD:
9915 case VMX_EXIT_VMRESUME:
9916 case VMX_EXIT_VMWRITE:
9917 case VMX_EXIT_VMXOFF:
9918 case VMX_EXIT_VMXON:
9919 case VMX_EXIT_MOV_CRX:
9920 case VMX_EXIT_MOV_DRX:
9921 case VMX_EXIT_IO_INSTR:
9922 case VMX_EXIT_RDMSR:
9923 case VMX_EXIT_WRMSR:
9924 case VMX_EXIT_MWAIT:
9925 case VMX_EXIT_MONITOR:
9926 case VMX_EXIT_PAUSE:
9927 case VMX_EXIT_GDTR_IDTR_ACCESS:
9928 case VMX_EXIT_LDTR_TR_ACCESS:
9929 case VMX_EXIT_INVEPT:
9930 case VMX_EXIT_RDTSCP:
9931 case VMX_EXIT_INVVPID:
9932 case VMX_EXIT_WBINVD:
9933 case VMX_EXIT_XSETBV:
9934 case VMX_EXIT_RDRAND:
9935 case VMX_EXIT_INVPCID:
9936 case VMX_EXIT_VMFUNC:
9937 case VMX_EXIT_RDSEED:
9938 case VMX_EXIT_XSAVES:
9939 case VMX_EXIT_XRSTORS:
9940 {
9941 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RIP);
9942 AssertRCReturn(rc, rc);
9943 if ( pVCpu->cpum.GstCtx.rip != pDbgState->uRipStart
9944 || pVCpu->cpum.GstCtx.cs.Sel != pDbgState->uCsStart)
9945 return VINF_EM_DBG_STEPPED;
9946 break;
9947 }
9948
9949 /* Errors and unexpected events: */
9950 case VMX_EXIT_INIT_SIGNAL:
9951 case VMX_EXIT_SIPI:
9952 case VMX_EXIT_IO_SMI:
9953 case VMX_EXIT_SMI:
9954 case VMX_EXIT_ERR_INVALID_GUEST_STATE:
9955 case VMX_EXIT_ERR_MSR_LOAD:
9956 case VMX_EXIT_ERR_MACHINE_CHECK:
9957 case VMX_EXIT_APIC_WRITE: /* Some talk about this being fault like, so I guess we must process it? */
9958 break;
9959
9960 default:
9961 AssertMsgFailed(("Unexpected VM-exit=%#x\n", uExitReason));
9962 break;
9963 }
9964 }
9965
9966 /*
9967 * Check for debugger event breakpoints and dtrace probes.
9968 */
9969 if ( uExitReason < RT_ELEMENTS(pDbgState->bmExitsToCheck) * 32U
9970 && ASMBitTest(pDbgState->bmExitsToCheck, uExitReason) )
9971 {
9972 VBOXSTRICTRC rcStrict = hmR0VmxHandleExitDtraceEvents(pVCpu, pVmxTransient, uExitReason);
9973 if (rcStrict != VINF_SUCCESS)
9974 return rcStrict;
9975 }
9976
9977 /*
9978 * Normal processing.
9979 */
9980#ifdef HMVMX_USE_FUNCTION_TABLE
9981 return g_apfnVMExitHandlers[uExitReason](pVCpu, pVmxTransient);
9982#else
9983 return hmR0VmxHandleExit(pVCpu, pVmxTransient, uExitReason);
9984#endif
9985}
9986
9987
9988/**
9989 * Single steps guest code using VT-x.
9990 *
9991 * @returns Strict VBox status code (i.e. informational status codes too).
9992 * @param pVCpu The cross context virtual CPU structure.
9993 *
9994 * @note Mostly the same as hmR0VmxRunGuestCodeNormal().
9995 */
9996static VBOXSTRICTRC hmR0VmxRunGuestCodeDebug(PVMCPU pVCpu)
9997{
9998 VMXTRANSIENT VmxTransient;
9999 VmxTransient.fUpdateTscOffsettingAndPreemptTimer = true;
10000
10001 /* Set HMCPU indicators. */
10002 bool const fSavedSingleInstruction = pVCpu->hm.s.fSingleInstruction;
10003 pVCpu->hm.s.fSingleInstruction = pVCpu->hm.s.fSingleInstruction || DBGFIsStepping(pVCpu);
10004 pVCpu->hm.s.fDebugWantRdTscExit = false;
10005 pVCpu->hm.s.fUsingDebugLoop = true;
10006
10007 /* State we keep to help modify and later restore the VMCS fields we alter, and for detecting steps. */
10008 VMXRUNDBGSTATE DbgState;
10009 hmR0VmxRunDebugStateInit(pVCpu, &DbgState);
10010 hmR0VmxPreRunGuestDebugStateUpdate(pVCpu, &DbgState, &VmxTransient);
10011
10012 /*
10013 * The loop.
10014 */
10015 VBOXSTRICTRC rcStrict = VERR_INTERNAL_ERROR_5;
10016 for (uint32_t cLoops = 0; ; cLoops++)
10017 {
10018 Assert(!HMR0SuspendPending());
10019 HMVMX_ASSERT_CPU_SAFE(pVCpu);
10020 bool fStepping = pVCpu->hm.s.fSingleInstruction;
10021
10022 /*
10023 * Preparatory work for running guest code, this may force us to return
10024 * to ring-3. This bugger disables interrupts on VINF_SUCCESS!
10025 */
10026 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
10027 hmR0VmxPreRunGuestDebugStateApply(pVCpu, &DbgState); /* Set up execute controls the next to can respond to. */
10028 rcStrict = hmR0VmxPreRunGuest(pVCpu, &VmxTransient, fStepping);
10029 if (rcStrict != VINF_SUCCESS)
10030 break;
10031
10032 hmR0VmxPreRunGuestCommitted(pVCpu, &VmxTransient);
10033 hmR0VmxPreRunGuestDebugStateApply(pVCpu, &DbgState); /* Override any obnoxious code in the above two calls. */
10034
10035 /*
10036 * Now we can run the guest code.
10037 */
10038 int rcRun = hmR0VmxRunGuest(pVCpu);
10039
10040 /*
10041 * Restore any residual host-state and save any bits shared between host
10042 * and guest into the guest-CPU state. Re-enables interrupts!
10043 */
10044 hmR0VmxPostRunGuest(pVCpu, &VmxTransient, rcRun);
10045
10046 /* Check for errors with running the VM (VMLAUNCH/VMRESUME). */
10047 if (RT_SUCCESS(rcRun))
10048 { /* very likely */ }
10049 else
10050 {
10051 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
10052 hmR0VmxReportWorldSwitchError(pVCpu, rcRun, &VmxTransient);
10053 return rcRun;
10054 }
10055
10056 /* Profile the VM-exit. */
10057 AssertMsg(VmxTransient.uExitReason <= VMX_EXIT_MAX, ("%#x\n", VmxTransient.uExitReason));
10058 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll);
10059 STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);
10060 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
10061 HMVMX_START_EXIT_DISPATCH_PROF();
10062
10063 VBOXVMM_R0_HMVMX_VMEXIT_NOCTX(pVCpu, &pVCpu->cpum.GstCtx, VmxTransient.uExitReason);
10064
10065 /*
10066 * Handle the VM-exit - we quit earlier on certain VM-exits, see hmR0VmxHandleExitDebug().
10067 */
10068 rcStrict = hmR0VmxRunDebugHandleExit(pVCpu, &VmxTransient, &DbgState);
10069 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
10070 if (rcStrict != VINF_SUCCESS)
10071 break;
10072 if (cLoops > pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops)
10073 {
10074 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
10075 rcStrict = VINF_EM_RAW_INTERRUPT;
10076 break;
10077 }
10078
10079 /*
10080 * Stepping: Did the RIP change, if so, consider it a single step.
10081 * Otherwise, make sure one of the TFs gets set.
10082 */
10083 if (fStepping)
10084 {
10085 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RIP);
10086 AssertRC(rc);
10087 if ( pVCpu->cpum.GstCtx.rip != DbgState.uRipStart
10088 || pVCpu->cpum.GstCtx.cs.Sel != DbgState.uCsStart)
10089 {
10090 rcStrict = VINF_EM_DBG_STEPPED;
10091 break;
10092 }
10093 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_DR7);
10094 }
10095
10096 /*
10097 * Update when dtrace settings changes (DBGF kicks us, so no need to check).
10098 */
10099 if (VBOXVMM_GET_SETTINGS_SEQ_NO() != DbgState.uDtraceSettingsSeqNo)
10100 hmR0VmxPreRunGuestDebugStateUpdate(pVCpu, &DbgState, &VmxTransient);
10101 }
10102
10103 /*
10104 * Clear the X86_EFL_TF if necessary.
10105 */
10106 if (pVCpu->hm.s.fClearTrapFlag)
10107 {
10108 int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_RFLAGS);
10109 AssertRC(rc);
10110 pVCpu->hm.s.fClearTrapFlag = false;
10111 pVCpu->cpum.GstCtx.eflags.Bits.u1TF = 0;
10112 }
10113 /** @todo there seems to be issues with the resume flag when the monitor trap
10114 * flag is pending without being used. Seen early in bios init when
10115 * accessing APIC page in protected mode. */
10116
10117 /*
10118 * Restore VM-exit control settings as we may not reenter this function the
10119 * next time around.
10120 */
10121 rcStrict = hmR0VmxRunDebugStateRevert(pVCpu, &DbgState, rcStrict);
10122
10123 /* Restore HMCPU indicators. */
10124 pVCpu->hm.s.fUsingDebugLoop = false;
10125 pVCpu->hm.s.fDebugWantRdTscExit = false;
10126 pVCpu->hm.s.fSingleInstruction = fSavedSingleInstruction;
10127
10128 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
10129 return rcStrict;
10130}
10131
10132
10133/** @} */
10134
10135
10136/**
10137 * Checks if any expensive dtrace probes are enabled and we should go to the
10138 * debug loop.
10139 *
10140 * @returns true if we should use debug loop, false if not.
10141 */
10142static bool hmR0VmxAnyExpensiveProbesEnabled(void)
10143{
10144 /* It's probably faster to OR the raw 32-bit counter variables together.
10145 Since the variables are in an array and the probes are next to one
10146 another (more or less), we have good locality. So, better read
10147 eight-nine cache lines ever time and only have one conditional, than
10148 128+ conditionals, right? */
10149 return ( VBOXVMM_R0_HMVMX_VMEXIT_ENABLED_RAW() /* expensive too due to context */
10150 | VBOXVMM_XCPT_DE_ENABLED_RAW()
10151 | VBOXVMM_XCPT_DB_ENABLED_RAW()
10152 | VBOXVMM_XCPT_BP_ENABLED_RAW()
10153 | VBOXVMM_XCPT_OF_ENABLED_RAW()
10154 | VBOXVMM_XCPT_BR_ENABLED_RAW()
10155 | VBOXVMM_XCPT_UD_ENABLED_RAW()
10156 | VBOXVMM_XCPT_NM_ENABLED_RAW()
10157 | VBOXVMM_XCPT_DF_ENABLED_RAW()
10158 | VBOXVMM_XCPT_TS_ENABLED_RAW()
10159 | VBOXVMM_XCPT_NP_ENABLED_RAW()
10160 | VBOXVMM_XCPT_SS_ENABLED_RAW()
10161 | VBOXVMM_XCPT_GP_ENABLED_RAW()
10162 | VBOXVMM_XCPT_PF_ENABLED_RAW()
10163 | VBOXVMM_XCPT_MF_ENABLED_RAW()
10164 | VBOXVMM_XCPT_AC_ENABLED_RAW()
10165 | VBOXVMM_XCPT_XF_ENABLED_RAW()
10166 | VBOXVMM_XCPT_VE_ENABLED_RAW()
10167 | VBOXVMM_XCPT_SX_ENABLED_RAW()
10168 | VBOXVMM_INT_SOFTWARE_ENABLED_RAW()
10169 | VBOXVMM_INT_HARDWARE_ENABLED_RAW()
10170 ) != 0
10171 || ( VBOXVMM_INSTR_HALT_ENABLED_RAW()
10172 | VBOXVMM_INSTR_MWAIT_ENABLED_RAW()
10173 | VBOXVMM_INSTR_MONITOR_ENABLED_RAW()
10174 | VBOXVMM_INSTR_CPUID_ENABLED_RAW()
10175 | VBOXVMM_INSTR_INVD_ENABLED_RAW()
10176 | VBOXVMM_INSTR_WBINVD_ENABLED_RAW()
10177 | VBOXVMM_INSTR_INVLPG_ENABLED_RAW()
10178 | VBOXVMM_INSTR_RDTSC_ENABLED_RAW()
10179 | VBOXVMM_INSTR_RDTSCP_ENABLED_RAW()
10180 | VBOXVMM_INSTR_RDPMC_ENABLED_RAW()
10181 | VBOXVMM_INSTR_RDMSR_ENABLED_RAW()
10182 | VBOXVMM_INSTR_WRMSR_ENABLED_RAW()
10183 | VBOXVMM_INSTR_CRX_READ_ENABLED_RAW()
10184 | VBOXVMM_INSTR_CRX_WRITE_ENABLED_RAW()
10185 | VBOXVMM_INSTR_DRX_READ_ENABLED_RAW()
10186 | VBOXVMM_INSTR_DRX_WRITE_ENABLED_RAW()
10187 | VBOXVMM_INSTR_PAUSE_ENABLED_RAW()
10188 | VBOXVMM_INSTR_XSETBV_ENABLED_RAW()
10189 | VBOXVMM_INSTR_SIDT_ENABLED_RAW()
10190 | VBOXVMM_INSTR_LIDT_ENABLED_RAW()
10191 | VBOXVMM_INSTR_SGDT_ENABLED_RAW()
10192 | VBOXVMM_INSTR_LGDT_ENABLED_RAW()
10193 | VBOXVMM_INSTR_SLDT_ENABLED_RAW()
10194 | VBOXVMM_INSTR_LLDT_ENABLED_RAW()
10195 | VBOXVMM_INSTR_STR_ENABLED_RAW()
10196 | VBOXVMM_INSTR_LTR_ENABLED_RAW()
10197 | VBOXVMM_INSTR_GETSEC_ENABLED_RAW()
10198 | VBOXVMM_INSTR_RSM_ENABLED_RAW()
10199 | VBOXVMM_INSTR_RDRAND_ENABLED_RAW()
10200 | VBOXVMM_INSTR_RDSEED_ENABLED_RAW()
10201 | VBOXVMM_INSTR_XSAVES_ENABLED_RAW()
10202 | VBOXVMM_INSTR_XRSTORS_ENABLED_RAW()
10203 | VBOXVMM_INSTR_VMM_CALL_ENABLED_RAW()
10204 | VBOXVMM_INSTR_VMX_VMCLEAR_ENABLED_RAW()
10205 | VBOXVMM_INSTR_VMX_VMLAUNCH_ENABLED_RAW()
10206 | VBOXVMM_INSTR_VMX_VMPTRLD_ENABLED_RAW()
10207 | VBOXVMM_INSTR_VMX_VMPTRST_ENABLED_RAW()
10208 | VBOXVMM_INSTR_VMX_VMREAD_ENABLED_RAW()
10209 | VBOXVMM_INSTR_VMX_VMRESUME_ENABLED_RAW()
10210 | VBOXVMM_INSTR_VMX_VMWRITE_ENABLED_RAW()
10211 | VBOXVMM_INSTR_VMX_VMXOFF_ENABLED_RAW()
10212 | VBOXVMM_INSTR_VMX_VMXON_ENABLED_RAW()
10213 | VBOXVMM_INSTR_VMX_VMFUNC_ENABLED_RAW()
10214 | VBOXVMM_INSTR_VMX_INVEPT_ENABLED_RAW()
10215 | VBOXVMM_INSTR_VMX_INVVPID_ENABLED_RAW()
10216 | VBOXVMM_INSTR_VMX_INVPCID_ENABLED_RAW()
10217 ) != 0
10218 || ( VBOXVMM_EXIT_TASK_SWITCH_ENABLED_RAW()
10219 | VBOXVMM_EXIT_HALT_ENABLED_RAW()
10220 | VBOXVMM_EXIT_MWAIT_ENABLED_RAW()
10221 | VBOXVMM_EXIT_MONITOR_ENABLED_RAW()
10222 | VBOXVMM_EXIT_CPUID_ENABLED_RAW()
10223 | VBOXVMM_EXIT_INVD_ENABLED_RAW()
10224 | VBOXVMM_EXIT_WBINVD_ENABLED_RAW()
10225 | VBOXVMM_EXIT_INVLPG_ENABLED_RAW()
10226 | VBOXVMM_EXIT_RDTSC_ENABLED_RAW()
10227 | VBOXVMM_EXIT_RDTSCP_ENABLED_RAW()
10228 | VBOXVMM_EXIT_RDPMC_ENABLED_RAW()
10229 | VBOXVMM_EXIT_RDMSR_ENABLED_RAW()
10230 | VBOXVMM_EXIT_WRMSR_ENABLED_RAW()
10231 | VBOXVMM_EXIT_CRX_READ_ENABLED_RAW()
10232 | VBOXVMM_EXIT_CRX_WRITE_ENABLED_RAW()
10233 | VBOXVMM_EXIT_DRX_READ_ENABLED_RAW()
10234 | VBOXVMM_EXIT_DRX_WRITE_ENABLED_RAW()
10235 | VBOXVMM_EXIT_PAUSE_ENABLED_RAW()
10236 | VBOXVMM_EXIT_XSETBV_ENABLED_RAW()
10237 | VBOXVMM_EXIT_SIDT_ENABLED_RAW()
10238 | VBOXVMM_EXIT_LIDT_ENABLED_RAW()
10239 | VBOXVMM_EXIT_SGDT_ENABLED_RAW()
10240 | VBOXVMM_EXIT_LGDT_ENABLED_RAW()
10241 | VBOXVMM_EXIT_SLDT_ENABLED_RAW()
10242 | VBOXVMM_EXIT_LLDT_ENABLED_RAW()
10243 | VBOXVMM_EXIT_STR_ENABLED_RAW()
10244 | VBOXVMM_EXIT_LTR_ENABLED_RAW()
10245 | VBOXVMM_EXIT_GETSEC_ENABLED_RAW()
10246 | VBOXVMM_EXIT_RSM_ENABLED_RAW()
10247 | VBOXVMM_EXIT_RDRAND_ENABLED_RAW()
10248 | VBOXVMM_EXIT_RDSEED_ENABLED_RAW()
10249 | VBOXVMM_EXIT_XSAVES_ENABLED_RAW()
10250 | VBOXVMM_EXIT_XRSTORS_ENABLED_RAW()
10251 | VBOXVMM_EXIT_VMM_CALL_ENABLED_RAW()
10252 | VBOXVMM_EXIT_VMX_VMCLEAR_ENABLED_RAW()
10253 | VBOXVMM_EXIT_VMX_VMLAUNCH_ENABLED_RAW()
10254 | VBOXVMM_EXIT_VMX_VMPTRLD_ENABLED_RAW()
10255 | VBOXVMM_EXIT_VMX_VMPTRST_ENABLED_RAW()
10256 | VBOXVMM_EXIT_VMX_VMREAD_ENABLED_RAW()
10257 | VBOXVMM_EXIT_VMX_VMRESUME_ENABLED_RAW()
10258 | VBOXVMM_EXIT_VMX_VMWRITE_ENABLED_RAW()
10259 | VBOXVMM_EXIT_VMX_VMXOFF_ENABLED_RAW()
10260 | VBOXVMM_EXIT_VMX_VMXON_ENABLED_RAW()
10261 | VBOXVMM_EXIT_VMX_VMFUNC_ENABLED_RAW()
10262 | VBOXVMM_EXIT_VMX_INVEPT_ENABLED_RAW()
10263 | VBOXVMM_EXIT_VMX_INVVPID_ENABLED_RAW()
10264 | VBOXVMM_EXIT_VMX_INVPCID_ENABLED_RAW()
10265 | VBOXVMM_EXIT_VMX_EPT_VIOLATION_ENABLED_RAW()
10266 | VBOXVMM_EXIT_VMX_EPT_MISCONFIG_ENABLED_RAW()
10267 | VBOXVMM_EXIT_VMX_VAPIC_ACCESS_ENABLED_RAW()
10268 | VBOXVMM_EXIT_VMX_VAPIC_WRITE_ENABLED_RAW()
10269 ) != 0;
10270}
10271
10272
10273/**
10274 * Runs the guest code using VT-x.
10275 *
10276 * @returns Strict VBox status code (i.e. informational status codes too).
10277 * @param pVCpu The cross context virtual CPU structure.
10278 */
10279VMMR0DECL(VBOXSTRICTRC) VMXR0RunGuestCode(PVMCPU pVCpu)
10280{
10281 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
10282 Assert(VMMRZCallRing3IsEnabled(pVCpu));
10283 Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
10284 HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
10285
10286 VMMRZCallRing3SetNotification(pVCpu, hmR0VmxCallRing3Callback, pCtx);
10287
10288 VBOXSTRICTRC rcStrict;
10289 if ( !pVCpu->hm.s.fUseDebugLoop
10290 && (!VBOXVMM_ANY_PROBES_ENABLED() || !hmR0VmxAnyExpensiveProbesEnabled())
10291 && !DBGFIsStepping(pVCpu)
10292 && !pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
10293 rcStrict = hmR0VmxRunGuestCodeNormal(pVCpu);
10294 else
10295 rcStrict = hmR0VmxRunGuestCodeDebug(pVCpu);
10296
10297 if (rcStrict == VERR_EM_INTERPRETER)
10298 rcStrict = VINF_EM_RAW_EMULATE_INSTR;
10299 else if (rcStrict == VINF_EM_RESET)
10300 rcStrict = VINF_EM_TRIPLE_FAULT;
10301
10302 int rc2 = hmR0VmxExitToRing3(pVCpu, rcStrict);
10303 if (RT_FAILURE(rc2))
10304 {
10305 pVCpu->hm.s.u32HMError = (uint32_t)VBOXSTRICTRC_VAL(rcStrict);
10306 rcStrict = rc2;
10307 }
10308 Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
10309 Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
10310 return rcStrict;
10311}
10312
10313
10314#ifndef HMVMX_USE_FUNCTION_TABLE
10315DECLINLINE(VBOXSTRICTRC) hmR0VmxHandleExit(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, uint32_t rcReason)
10316{
10317#ifdef DEBUG_ramshankar
10318#define VMEXIT_CALL_RET(a_fSave, a_CallExpr) \
10319 do { \
10320 if (a_fSave != 0) \
10321 hmR0VmxImportGuestState(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL); \
10322 VBOXSTRICTRC rcStrict = a_CallExpr; \
10323 if (a_fSave != 0) \
10324 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST); \
10325 return rcStrict; \
10326 } while (0)
10327#else
10328# define VMEXIT_CALL_RET(a_fSave, a_CallExpr) return a_CallExpr
10329#endif
10330 switch (rcReason)
10331 {
10332 case VMX_EXIT_EPT_MISCONFIG: VMEXIT_CALL_RET(0, hmR0VmxExitEptMisconfig(pVCpu, pVmxTransient));
10333 case VMX_EXIT_EPT_VIOLATION: VMEXIT_CALL_RET(0, hmR0VmxExitEptViolation(pVCpu, pVmxTransient));
10334 case VMX_EXIT_IO_INSTR: VMEXIT_CALL_RET(0, hmR0VmxExitIoInstr(pVCpu, pVmxTransient));
10335 case VMX_EXIT_CPUID: VMEXIT_CALL_RET(0, hmR0VmxExitCpuid(pVCpu, pVmxTransient));
10336 case VMX_EXIT_RDTSC: VMEXIT_CALL_RET(0, hmR0VmxExitRdtsc(pVCpu, pVmxTransient));
10337 case VMX_EXIT_RDTSCP: VMEXIT_CALL_RET(0, hmR0VmxExitRdtscp(pVCpu, pVmxTransient));
10338 case VMX_EXIT_APIC_ACCESS: VMEXIT_CALL_RET(0, hmR0VmxExitApicAccess(pVCpu, pVmxTransient));
10339 case VMX_EXIT_XCPT_OR_NMI: VMEXIT_CALL_RET(0, hmR0VmxExitXcptOrNmi(pVCpu, pVmxTransient));
10340 case VMX_EXIT_MOV_CRX: VMEXIT_CALL_RET(0, hmR0VmxExitMovCRx(pVCpu, pVmxTransient));
10341 case VMX_EXIT_EXT_INT: VMEXIT_CALL_RET(0, hmR0VmxExitExtInt(pVCpu, pVmxTransient));
10342 case VMX_EXIT_INT_WINDOW: VMEXIT_CALL_RET(0, hmR0VmxExitIntWindow(pVCpu, pVmxTransient));
10343 case VMX_EXIT_TPR_BELOW_THRESHOLD: VMEXIT_CALL_RET(0, hmR0VmxExitTprBelowThreshold(pVCpu, pVmxTransient));
10344 case VMX_EXIT_MWAIT: VMEXIT_CALL_RET(0, hmR0VmxExitMwait(pVCpu, pVmxTransient));
10345 case VMX_EXIT_MONITOR: VMEXIT_CALL_RET(0, hmR0VmxExitMonitor(pVCpu, pVmxTransient));
10346 case VMX_EXIT_TASK_SWITCH: VMEXIT_CALL_RET(0, hmR0VmxExitTaskSwitch(pVCpu, pVmxTransient));
10347 case VMX_EXIT_PREEMPT_TIMER: VMEXIT_CALL_RET(0, hmR0VmxExitPreemptTimer(pVCpu, pVmxTransient));
10348 case VMX_EXIT_RDMSR: VMEXIT_CALL_RET(0, hmR0VmxExitRdmsr(pVCpu, pVmxTransient));
10349 case VMX_EXIT_WRMSR: VMEXIT_CALL_RET(0, hmR0VmxExitWrmsr(pVCpu, pVmxTransient));
10350 case VMX_EXIT_VMCALL: VMEXIT_CALL_RET(0, hmR0VmxExitVmcall(pVCpu, pVmxTransient));
10351 case VMX_EXIT_MOV_DRX: VMEXIT_CALL_RET(0, hmR0VmxExitMovDRx(pVCpu, pVmxTransient));
10352 case VMX_EXIT_HLT: VMEXIT_CALL_RET(0, hmR0VmxExitHlt(pVCpu, pVmxTransient));
10353 case VMX_EXIT_INVD: VMEXIT_CALL_RET(0, hmR0VmxExitInvd(pVCpu, pVmxTransient));
10354 case VMX_EXIT_INVLPG: VMEXIT_CALL_RET(0, hmR0VmxExitInvlpg(pVCpu, pVmxTransient));
10355 case VMX_EXIT_RSM: VMEXIT_CALL_RET(0, hmR0VmxExitRsm(pVCpu, pVmxTransient));
10356 case VMX_EXIT_MTF: VMEXIT_CALL_RET(0, hmR0VmxExitMtf(pVCpu, pVmxTransient));
10357 case VMX_EXIT_PAUSE: VMEXIT_CALL_RET(0, hmR0VmxExitPause(pVCpu, pVmxTransient));
10358 case VMX_EXIT_GDTR_IDTR_ACCESS: VMEXIT_CALL_RET(0, hmR0VmxExitXdtrAccess(pVCpu, pVmxTransient));
10359 case VMX_EXIT_LDTR_TR_ACCESS: VMEXIT_CALL_RET(0, hmR0VmxExitXdtrAccess(pVCpu, pVmxTransient));
10360 case VMX_EXIT_WBINVD: VMEXIT_CALL_RET(0, hmR0VmxExitWbinvd(pVCpu, pVmxTransient));
10361 case VMX_EXIT_XSETBV: VMEXIT_CALL_RET(0, hmR0VmxExitXsetbv(pVCpu, pVmxTransient));
10362 case VMX_EXIT_RDRAND: VMEXIT_CALL_RET(0, hmR0VmxExitRdrand(pVCpu, pVmxTransient));
10363 case VMX_EXIT_INVPCID: VMEXIT_CALL_RET(0, hmR0VmxExitInvpcid(pVCpu, pVmxTransient));
10364 case VMX_EXIT_GETSEC: VMEXIT_CALL_RET(0, hmR0VmxExitGetsec(pVCpu, pVmxTransient));
10365 case VMX_EXIT_RDPMC: VMEXIT_CALL_RET(0, hmR0VmxExitRdpmc(pVCpu, pVmxTransient));
10366
10367 case VMX_EXIT_TRIPLE_FAULT: return hmR0VmxExitTripleFault(pVCpu, pVmxTransient);
10368 case VMX_EXIT_NMI_WINDOW: return hmR0VmxExitNmiWindow(pVCpu, pVmxTransient);
10369 case VMX_EXIT_INIT_SIGNAL: return hmR0VmxExitInitSignal(pVCpu, pVmxTransient);
10370 case VMX_EXIT_SIPI: return hmR0VmxExitSipi(pVCpu, pVmxTransient);
10371 case VMX_EXIT_IO_SMI: return hmR0VmxExitIoSmi(pVCpu, pVmxTransient);
10372 case VMX_EXIT_SMI: return hmR0VmxExitSmi(pVCpu, pVmxTransient);
10373 case VMX_EXIT_ERR_MSR_LOAD: return hmR0VmxExitErrMsrLoad(pVCpu, pVmxTransient);
10374 case VMX_EXIT_ERR_INVALID_GUEST_STATE: return hmR0VmxExitErrInvalidGuestState(pVCpu, pVmxTransient);
10375 case VMX_EXIT_ERR_MACHINE_CHECK: return hmR0VmxExitErrMachineCheck(pVCpu, pVmxTransient);
10376
10377 case VMX_EXIT_VMCLEAR:
10378 case VMX_EXIT_VMLAUNCH:
10379 case VMX_EXIT_VMPTRLD:
10380 case VMX_EXIT_VMPTRST:
10381 case VMX_EXIT_VMREAD:
10382 case VMX_EXIT_VMRESUME:
10383 case VMX_EXIT_VMWRITE:
10384 case VMX_EXIT_VMXOFF:
10385 case VMX_EXIT_VMXON:
10386 case VMX_EXIT_INVEPT:
10387 case VMX_EXIT_INVVPID:
10388 case VMX_EXIT_VMFUNC:
10389 case VMX_EXIT_XSAVES:
10390 case VMX_EXIT_XRSTORS:
10391 return hmR0VmxExitSetPendingXcptUD(pVCpu, pVmxTransient);
10392
10393 case VMX_EXIT_ENCLS:
10394 case VMX_EXIT_RDSEED: /* only spurious VM-exits, so undefined */
10395 case VMX_EXIT_PML_FULL:
10396 default:
10397 return hmR0VmxExitErrUndefined(pVCpu, pVmxTransient);
10398 }
10399#undef VMEXIT_CALL_RET
10400}
10401#endif /* !HMVMX_USE_FUNCTION_TABLE */
10402
10403
10404#ifdef VBOX_STRICT
10405/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
10406# define HMVMX_ASSERT_PREEMPT_CPUID_VAR() \
10407 RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
10408
10409# define HMVMX_ASSERT_PREEMPT_CPUID() \
10410 do { \
10411 RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
10412 AssertMsg(idAssertCpu == idAssertCpuNow, ("VMX %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
10413 } while (0)
10414
10415# define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) \
10416 do { \
10417 AssertPtr((a_pVCpu)); \
10418 AssertPtr((a_pVmxTransient)); \
10419 Assert((a_pVmxTransient)->fVMEntryFailed == false); \
10420 Assert(ASMIntAreEnabled()); \
10421 HMVMX_ASSERT_PREEMPT_SAFE(a_pVCpu); \
10422 HMVMX_ASSERT_PREEMPT_CPUID_VAR(); \
10423 Log4Func(("vcpu[%RU32] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v\n", (a_pVCpu)->idCpu)); \
10424 HMVMX_ASSERT_PREEMPT_SAFE(a_pVCpu); \
10425 if (VMMR0IsLogFlushDisabled((a_pVCpu))) \
10426 HMVMX_ASSERT_PREEMPT_CPUID(); \
10427 HMVMX_STOP_EXIT_DISPATCH_PROF(); \
10428 } while (0)
10429
10430# define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) \
10431 do { \
10432 Log4Func(("\n")); \
10433 } while (0)
10434#else
10435# define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) \
10436 do { \
10437 HMVMX_STOP_EXIT_DISPATCH_PROF(); \
10438 NOREF((a_pVCpu)); NOREF((a_pVmxTransient)); \
10439 } while (0)
10440# define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) do { } while (0)
10441#endif
10442
10443
10444/**
10445 * Advances the guest RIP by the specified number of bytes.
10446 *
10447 * @param pVCpu The cross context virtual CPU structure.
10448 * @param cbInstr Number of bytes to advance the RIP by.
10449 *
10450 * @remarks No-long-jump zone!!!
10451 */
10452DECLINLINE(void) hmR0VmxAdvanceGuestRipBy(PVMCPU pVCpu, uint32_t cbInstr)
10453{
10454 /* Advance the RIP. */
10455 pVCpu->cpum.GstCtx.rip += cbInstr;
10456 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP);
10457
10458 /* Update interrupt inhibition. */
10459 if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
10460 && pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
10461 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
10462}
10463
10464
10465/**
10466 * Advances the guest RIP after reading it from the VMCS.
10467 *
10468 * @returns VBox status code, no informational status codes.
10469 * @param pVCpu The cross context virtual CPU structure.
10470 * @param pVmxTransient Pointer to the VMX transient structure.
10471 *
10472 * @remarks No-long-jump zone!!!
10473 */
10474static int hmR0VmxAdvanceGuestRip(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
10475{
10476 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
10477 rc |= hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS);
10478 AssertRCReturn(rc, rc);
10479
10480 hmR0VmxAdvanceGuestRipBy(pVCpu, pVmxTransient->cbInstr);
10481 return VINF_SUCCESS;
10482}
10483
10484
10485/**
10486 * Tries to determine what part of the guest-state VT-x has deemed as invalid
10487 * and update error record fields accordingly.
10488 *
10489 * @return VMX_IGS_* return codes.
10490 * @retval VMX_IGS_REASON_NOT_FOUND if this function could not find anything
10491 * wrong with the guest state.
10492 *
10493 * @param pVCpu The cross context virtual CPU structure.
10494 *
10495 * @remarks This function assumes our cache of the VMCS controls
10496 * are valid, i.e. hmR0VmxCheckVmcsCtls() succeeded.
10497 */
10498static uint32_t hmR0VmxCheckGuestState(PVMCPU pVCpu)
10499{
10500#define HMVMX_ERROR_BREAK(err) { uError = (err); break; }
10501#define HMVMX_CHECK_BREAK(expr, err) if (!(expr)) { \
10502 uError = (err); \
10503 break; \
10504 } else do { } while (0)
10505
10506 int rc;
10507 PVM pVM = pVCpu->CTX_SUFF(pVM);
10508 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
10509 uint32_t uError = VMX_IGS_ERROR;
10510 uint32_t u32Val;
10511 bool const fUnrestrictedGuest = pVM->hm.s.vmx.fUnrestrictedGuest;
10512
10513 do
10514 {
10515 /*
10516 * CR0.
10517 */
10518 uint32_t fSetCr0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
10519 uint32_t const fZapCr0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
10520 /* Exceptions for unrestricted-guests for fixed CR0 bits (PE, PG).
10521 See Intel spec. 26.3.1 "Checks on Guest Control Registers, Debug Registers and MSRs." */
10522 if (fUnrestrictedGuest)
10523 fSetCr0 &= ~(X86_CR0_PE | X86_CR0_PG);
10524
10525 uint32_t u32GuestCr0;
10526 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &u32GuestCr0);
10527 AssertRCBreak(rc);
10528 HMVMX_CHECK_BREAK((u32GuestCr0 & fSetCr0) == fSetCr0, VMX_IGS_CR0_FIXED1);
10529 HMVMX_CHECK_BREAK(!(u32GuestCr0 & ~fZapCr0), VMX_IGS_CR0_FIXED0);
10530 if ( !fUnrestrictedGuest
10531 && (u32GuestCr0 & X86_CR0_PG)
10532 && !(u32GuestCr0 & X86_CR0_PE))
10533 {
10534 HMVMX_ERROR_BREAK(VMX_IGS_CR0_PG_PE_COMBO);
10535 }
10536
10537 /*
10538 * CR4.
10539 */
10540 uint64_t const fSetCr4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
10541 uint64_t const fZapCr4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
10542
10543 uint32_t u32GuestCr4;
10544 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR4, &u32GuestCr4);
10545 AssertRCBreak(rc);
10546 HMVMX_CHECK_BREAK((u32GuestCr4 & fSetCr4) == fSetCr4, VMX_IGS_CR4_FIXED1);
10547 HMVMX_CHECK_BREAK(!(u32GuestCr4 & ~fZapCr4), VMX_IGS_CR4_FIXED0);
10548
10549 /*
10550 * IA32_DEBUGCTL MSR.
10551 */
10552 uint64_t u64Val;
10553 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, &u64Val);
10554 AssertRCBreak(rc);
10555 if ( (pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
10556 && (u64Val & 0xfffffe3c)) /* Bits 31:9, bits 5:2 MBZ. */
10557 {
10558 HMVMX_ERROR_BREAK(VMX_IGS_DEBUGCTL_MSR_RESERVED);
10559 }
10560 uint64_t u64DebugCtlMsr = u64Val;
10561
10562#ifdef VBOX_STRICT
10563 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val);
10564 AssertRCBreak(rc);
10565 Assert(u32Val == pVCpu->hm.s.vmx.u32EntryCtls);
10566#endif
10567 bool const fLongModeGuest = RT_BOOL(pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
10568
10569 /*
10570 * RIP and RFLAGS.
10571 */
10572 uint32_t u32Eflags;
10573#if HC_ARCH_BITS == 64
10574 rc = VMXReadVmcs64(VMX_VMCS_GUEST_RIP, &u64Val);
10575 AssertRCBreak(rc);
10576 /* pCtx->rip can be different than the one in the VMCS (e.g. run guest code and VM-exits that don't update it). */
10577 if ( !fLongModeGuest
10578 || !pCtx->cs.Attr.n.u1Long)
10579 {
10580 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffff00000000)), VMX_IGS_LONGMODE_RIP_INVALID);
10581 }
10582 /** @todo If the processor supports N < 64 linear-address bits, bits 63:N
10583 * must be identical if the "IA-32e mode guest" VM-entry
10584 * control is 1 and CS.L is 1. No check applies if the
10585 * CPU supports 64 linear-address bits. */
10586
10587 /* Flags in pCtx can be different (real-on-v86 for instance). We are only concerned about the VMCS contents here. */
10588 rc = VMXReadVmcs64(VMX_VMCS_GUEST_RFLAGS, &u64Val);
10589 AssertRCBreak(rc);
10590 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffffffc08028)), /* Bit 63:22, Bit 15, 5, 3 MBZ. */
10591 VMX_IGS_RFLAGS_RESERVED);
10592 HMVMX_CHECK_BREAK((u64Val & X86_EFL_RA1_MASK), VMX_IGS_RFLAGS_RESERVED1); /* Bit 1 MB1. */
10593 u32Eflags = u64Val;
10594#else
10595 rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Eflags);
10596 AssertRCBreak(rc);
10597 HMVMX_CHECK_BREAK(!(u32Eflags & 0xffc08028), VMX_IGS_RFLAGS_RESERVED); /* Bit 31:22, Bit 15, 5, 3 MBZ. */
10598 HMVMX_CHECK_BREAK((u32Eflags & X86_EFL_RA1_MASK), VMX_IGS_RFLAGS_RESERVED1); /* Bit 1 MB1. */
10599#endif
10600
10601 if ( fLongModeGuest
10602 || ( fUnrestrictedGuest
10603 && !(u32GuestCr0 & X86_CR0_PE)))
10604 {
10605 HMVMX_CHECK_BREAK(!(u32Eflags & X86_EFL_VM), VMX_IGS_RFLAGS_VM_INVALID);
10606 }
10607
10608 uint32_t u32EntryInfo;
10609 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &u32EntryInfo);
10610 AssertRCBreak(rc);
10611 if ( VMX_ENTRY_INT_INFO_IS_VALID(u32EntryInfo)
10612 && VMX_ENTRY_INT_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INT_INFO_TYPE_EXT_INT)
10613 {
10614 HMVMX_CHECK_BREAK(u32Eflags & X86_EFL_IF, VMX_IGS_RFLAGS_IF_INVALID);
10615 }
10616
10617 /*
10618 * 64-bit checks.
10619 */
10620#if HC_ARCH_BITS == 64
10621 if (fLongModeGuest)
10622 {
10623 HMVMX_CHECK_BREAK(u32GuestCr0 & X86_CR0_PG, VMX_IGS_CR0_PG_LONGMODE);
10624 HMVMX_CHECK_BREAK(u32GuestCr4 & X86_CR4_PAE, VMX_IGS_CR4_PAE_LONGMODE);
10625 }
10626
10627 if ( !fLongModeGuest
10628 && (u32GuestCr4 & X86_CR4_PCIDE))
10629 {
10630 HMVMX_ERROR_BREAK(VMX_IGS_CR4_PCIDE);
10631 }
10632
10633 /** @todo CR3 field must be such that bits 63:52 and bits in the range
10634 * 51:32 beyond the processor's physical-address width are 0. */
10635
10636 if ( (pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
10637 && (pCtx->dr[7] & X86_DR7_MBZ_MASK))
10638 {
10639 HMVMX_ERROR_BREAK(VMX_IGS_DR7_RESERVED);
10640 }
10641
10642 rc = VMXReadVmcs64(VMX_VMCS_HOST_SYSENTER_ESP, &u64Val);
10643 AssertRCBreak(rc);
10644 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_SYSENTER_ESP_NOT_CANONICAL);
10645
10646 rc = VMXReadVmcs64(VMX_VMCS_HOST_SYSENTER_EIP, &u64Val);
10647 AssertRCBreak(rc);
10648 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_SYSENTER_EIP_NOT_CANONICAL);
10649#endif
10650
10651 /*
10652 * PERF_GLOBAL MSR.
10653 */
10654 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR)
10655 {
10656 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL, &u64Val);
10657 AssertRCBreak(rc);
10658 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xfffffff8fffffffc)),
10659 VMX_IGS_PERF_GLOBAL_MSR_RESERVED); /* Bits 63:35, bits 31:2 MBZ. */
10660 }
10661
10662 /*
10663 * PAT MSR.
10664 */
10665 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
10666 {
10667 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PAT_FULL, &u64Val);
10668 AssertRCBreak(rc);
10669 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0x707070707070707)), VMX_IGS_PAT_MSR_RESERVED);
10670 for (unsigned i = 0; i < 8; i++)
10671 {
10672 uint8_t u8Val = (u64Val & 0xff);
10673 if ( u8Val != 0 /* UC */
10674 && u8Val != 1 /* WC */
10675 && u8Val != 4 /* WT */
10676 && u8Val != 5 /* WP */
10677 && u8Val != 6 /* WB */
10678 && u8Val != 7 /* UC- */)
10679 {
10680 HMVMX_ERROR_BREAK(VMX_IGS_PAT_MSR_INVALID);
10681 }
10682 u64Val >>= 8;
10683 }
10684 }
10685
10686 /*
10687 * EFER MSR.
10688 */
10689 if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
10690 {
10691 Assert(pVM->hm.s.vmx.fSupportsVmcsEfer);
10692 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_EFER_FULL, &u64Val);
10693 AssertRCBreak(rc);
10694 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xfffffffffffff2fe)),
10695 VMX_IGS_EFER_MSR_RESERVED); /* Bits 63:12, bit 9, bits 7:1 MBZ. */
10696 HMVMX_CHECK_BREAK(RT_BOOL(u64Val & MSR_K6_EFER_LMA) == RT_BOOL( pVCpu->hm.s.vmx.u32EntryCtls
10697 & VMX_ENTRY_CTLS_IA32E_MODE_GUEST),
10698 VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH);
10699 /** @todo r=ramshankar: Unrestricted check here is probably wrong, see
10700 * iemVmxVmentryCheckGuestState(). */
10701 HMVMX_CHECK_BREAK( fUnrestrictedGuest
10702 || !(u32GuestCr0 & X86_CR0_PG)
10703 || RT_BOOL(u64Val & MSR_K6_EFER_LMA) == RT_BOOL(u64Val & MSR_K6_EFER_LME),
10704 VMX_IGS_EFER_LMA_LME_MISMATCH);
10705 }
10706
10707 /*
10708 * Segment registers.
10709 */
10710 HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
10711 || !(pCtx->ldtr.Sel & X86_SEL_LDT), VMX_IGS_LDTR_TI_INVALID);
10712 if (!(u32Eflags & X86_EFL_VM))
10713 {
10714 /* CS */
10715 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u1Present, VMX_IGS_CS_ATTR_P_INVALID);
10716 HMVMX_CHECK_BREAK(!(pCtx->cs.Attr.u & 0xf00), VMX_IGS_CS_ATTR_RESERVED);
10717 HMVMX_CHECK_BREAK(!(pCtx->cs.Attr.u & 0xfffe0000), VMX_IGS_CS_ATTR_RESERVED);
10718 HMVMX_CHECK_BREAK( (pCtx->cs.u32Limit & 0xfff) == 0xfff
10719 || !(pCtx->cs.Attr.n.u1Granularity), VMX_IGS_CS_ATTR_G_INVALID);
10720 HMVMX_CHECK_BREAK( !(pCtx->cs.u32Limit & 0xfff00000)
10721 || (pCtx->cs.Attr.n.u1Granularity), VMX_IGS_CS_ATTR_G_INVALID);
10722 /* CS cannot be loaded with NULL in protected mode. */
10723 HMVMX_CHECK_BREAK(pCtx->cs.Attr.u && !(pCtx->cs.Attr.u & X86DESCATTR_UNUSABLE), VMX_IGS_CS_ATTR_UNUSABLE);
10724 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u1DescType, VMX_IGS_CS_ATTR_S_INVALID);
10725 if (pCtx->cs.Attr.n.u4Type == 9 || pCtx->cs.Attr.n.u4Type == 11)
10726 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl == pCtx->ss.Attr.n.u2Dpl, VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL);
10727 else if (pCtx->cs.Attr.n.u4Type == 13 || pCtx->cs.Attr.n.u4Type == 15)
10728 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl <= pCtx->ss.Attr.n.u2Dpl, VMX_IGS_CS_SS_ATTR_DPL_MISMATCH);
10729 else if (pVM->hm.s.vmx.fUnrestrictedGuest && pCtx->cs.Attr.n.u4Type == 3)
10730 HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl == 0, VMX_IGS_CS_ATTR_DPL_INVALID);
10731 else
10732 HMVMX_ERROR_BREAK(VMX_IGS_CS_ATTR_TYPE_INVALID);
10733
10734 /* SS */
10735 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10736 || (pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL), VMX_IGS_SS_CS_RPL_UNEQUAL);
10737 HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u2Dpl == (pCtx->ss.Sel & X86_SEL_RPL), VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL);
10738 if ( !(pCtx->cr0 & X86_CR0_PE)
10739 || pCtx->cs.Attr.n.u4Type == 3)
10740 {
10741 HMVMX_CHECK_BREAK(!pCtx->ss.Attr.n.u2Dpl, VMX_IGS_SS_ATTR_DPL_INVALID);
10742 }
10743 if (!(pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE))
10744 {
10745 HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u4Type == 3 || pCtx->ss.Attr.n.u4Type == 7, VMX_IGS_SS_ATTR_TYPE_INVALID);
10746 HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u1Present, VMX_IGS_SS_ATTR_P_INVALID);
10747 HMVMX_CHECK_BREAK(!(pCtx->ss.Attr.u & 0xf00), VMX_IGS_SS_ATTR_RESERVED);
10748 HMVMX_CHECK_BREAK(!(pCtx->ss.Attr.u & 0xfffe0000), VMX_IGS_SS_ATTR_RESERVED);
10749 HMVMX_CHECK_BREAK( (pCtx->ss.u32Limit & 0xfff) == 0xfff
10750 || !(pCtx->ss.Attr.n.u1Granularity), VMX_IGS_SS_ATTR_G_INVALID);
10751 HMVMX_CHECK_BREAK( !(pCtx->ss.u32Limit & 0xfff00000)
10752 || (pCtx->ss.Attr.n.u1Granularity), VMX_IGS_SS_ATTR_G_INVALID);
10753 }
10754
10755 /* DS, ES, FS, GS - only check for usable selectors, see hmR0VmxExportGuestSegmenReg(). */
10756 if (!(pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE))
10757 {
10758 HMVMX_CHECK_BREAK(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_DS_ATTR_A_INVALID);
10759 HMVMX_CHECK_BREAK(pCtx->ds.Attr.n.u1Present, VMX_IGS_DS_ATTR_P_INVALID);
10760 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10761 || pCtx->ds.Attr.n.u4Type > 11
10762 || pCtx->ds.Attr.n.u2Dpl >= (pCtx->ds.Sel & X86_SEL_RPL), VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL);
10763 HMVMX_CHECK_BREAK(!(pCtx->ds.Attr.u & 0xf00), VMX_IGS_DS_ATTR_RESERVED);
10764 HMVMX_CHECK_BREAK(!(pCtx->ds.Attr.u & 0xfffe0000), VMX_IGS_DS_ATTR_RESERVED);
10765 HMVMX_CHECK_BREAK( (pCtx->ds.u32Limit & 0xfff) == 0xfff
10766 || !(pCtx->ds.Attr.n.u1Granularity), VMX_IGS_DS_ATTR_G_INVALID);
10767 HMVMX_CHECK_BREAK( !(pCtx->ds.u32Limit & 0xfff00000)
10768 || (pCtx->ds.Attr.n.u1Granularity), VMX_IGS_DS_ATTR_G_INVALID);
10769 HMVMX_CHECK_BREAK( !(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_CODE)
10770 || (pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_DS_ATTR_TYPE_INVALID);
10771 }
10772 if (!(pCtx->es.Attr.u & X86DESCATTR_UNUSABLE))
10773 {
10774 HMVMX_CHECK_BREAK(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_ES_ATTR_A_INVALID);
10775 HMVMX_CHECK_BREAK(pCtx->es.Attr.n.u1Present, VMX_IGS_ES_ATTR_P_INVALID);
10776 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10777 || pCtx->es.Attr.n.u4Type > 11
10778 || pCtx->es.Attr.n.u2Dpl >= (pCtx->es.Sel & X86_SEL_RPL), VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL);
10779 HMVMX_CHECK_BREAK(!(pCtx->es.Attr.u & 0xf00), VMX_IGS_ES_ATTR_RESERVED);
10780 HMVMX_CHECK_BREAK(!(pCtx->es.Attr.u & 0xfffe0000), VMX_IGS_ES_ATTR_RESERVED);
10781 HMVMX_CHECK_BREAK( (pCtx->es.u32Limit & 0xfff) == 0xfff
10782 || !(pCtx->es.Attr.n.u1Granularity), VMX_IGS_ES_ATTR_G_INVALID);
10783 HMVMX_CHECK_BREAK( !(pCtx->es.u32Limit & 0xfff00000)
10784 || (pCtx->es.Attr.n.u1Granularity), VMX_IGS_ES_ATTR_G_INVALID);
10785 HMVMX_CHECK_BREAK( !(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_CODE)
10786 || (pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_ES_ATTR_TYPE_INVALID);
10787 }
10788 if (!(pCtx->fs.Attr.u & X86DESCATTR_UNUSABLE))
10789 {
10790 HMVMX_CHECK_BREAK(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_FS_ATTR_A_INVALID);
10791 HMVMX_CHECK_BREAK(pCtx->fs.Attr.n.u1Present, VMX_IGS_FS_ATTR_P_INVALID);
10792 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10793 || pCtx->fs.Attr.n.u4Type > 11
10794 || pCtx->fs.Attr.n.u2Dpl >= (pCtx->fs.Sel & X86_SEL_RPL), VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL);
10795 HMVMX_CHECK_BREAK(!(pCtx->fs.Attr.u & 0xf00), VMX_IGS_FS_ATTR_RESERVED);
10796 HMVMX_CHECK_BREAK(!(pCtx->fs.Attr.u & 0xfffe0000), VMX_IGS_FS_ATTR_RESERVED);
10797 HMVMX_CHECK_BREAK( (pCtx->fs.u32Limit & 0xfff) == 0xfff
10798 || !(pCtx->fs.Attr.n.u1Granularity), VMX_IGS_FS_ATTR_G_INVALID);
10799 HMVMX_CHECK_BREAK( !(pCtx->fs.u32Limit & 0xfff00000)
10800 || (pCtx->fs.Attr.n.u1Granularity), VMX_IGS_FS_ATTR_G_INVALID);
10801 HMVMX_CHECK_BREAK( !(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
10802 || (pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_FS_ATTR_TYPE_INVALID);
10803 }
10804 if (!(pCtx->gs.Attr.u & X86DESCATTR_UNUSABLE))
10805 {
10806 HMVMX_CHECK_BREAK(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_GS_ATTR_A_INVALID);
10807 HMVMX_CHECK_BREAK(pCtx->gs.Attr.n.u1Present, VMX_IGS_GS_ATTR_P_INVALID);
10808 HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10809 || pCtx->gs.Attr.n.u4Type > 11
10810 || pCtx->gs.Attr.n.u2Dpl >= (pCtx->gs.Sel & X86_SEL_RPL), VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL);
10811 HMVMX_CHECK_BREAK(!(pCtx->gs.Attr.u & 0xf00), VMX_IGS_GS_ATTR_RESERVED);
10812 HMVMX_CHECK_BREAK(!(pCtx->gs.Attr.u & 0xfffe0000), VMX_IGS_GS_ATTR_RESERVED);
10813 HMVMX_CHECK_BREAK( (pCtx->gs.u32Limit & 0xfff) == 0xfff
10814 || !(pCtx->gs.Attr.n.u1Granularity), VMX_IGS_GS_ATTR_G_INVALID);
10815 HMVMX_CHECK_BREAK( !(pCtx->gs.u32Limit & 0xfff00000)
10816 || (pCtx->gs.Attr.n.u1Granularity), VMX_IGS_GS_ATTR_G_INVALID);
10817 HMVMX_CHECK_BREAK( !(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
10818 || (pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_GS_ATTR_TYPE_INVALID);
10819 }
10820 /* 64-bit capable CPUs. */
10821#if HC_ARCH_BITS == 64
10822 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->fs.u64Base), VMX_IGS_FS_BASE_NOT_CANONICAL);
10823 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->gs.u64Base), VMX_IGS_GS_BASE_NOT_CANONICAL);
10824 HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
10825 || X86_IS_CANONICAL(pCtx->ldtr.u64Base), VMX_IGS_LDTR_BASE_NOT_CANONICAL);
10826 HMVMX_CHECK_BREAK(!RT_HI_U32(pCtx->cs.u64Base), VMX_IGS_LONGMODE_CS_BASE_INVALID);
10827 HMVMX_CHECK_BREAK((pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->ss.u64Base),
10828 VMX_IGS_LONGMODE_SS_BASE_INVALID);
10829 HMVMX_CHECK_BREAK((pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->ds.u64Base),
10830 VMX_IGS_LONGMODE_DS_BASE_INVALID);
10831 HMVMX_CHECK_BREAK((pCtx->es.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->es.u64Base),
10832 VMX_IGS_LONGMODE_ES_BASE_INVALID);
10833#endif
10834 }
10835 else
10836 {
10837 /* V86 mode checks. */
10838 uint32_t u32CSAttr, u32SSAttr, u32DSAttr, u32ESAttr, u32FSAttr, u32GSAttr;
10839 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
10840 {
10841 u32CSAttr = 0xf3; u32SSAttr = 0xf3;
10842 u32DSAttr = 0xf3; u32ESAttr = 0xf3;
10843 u32FSAttr = 0xf3; u32GSAttr = 0xf3;
10844 }
10845 else
10846 {
10847 u32CSAttr = pCtx->cs.Attr.u; u32SSAttr = pCtx->ss.Attr.u;
10848 u32DSAttr = pCtx->ds.Attr.u; u32ESAttr = pCtx->es.Attr.u;
10849 u32FSAttr = pCtx->fs.Attr.u; u32GSAttr = pCtx->gs.Attr.u;
10850 }
10851
10852 /* CS */
10853 HMVMX_CHECK_BREAK((pCtx->cs.u64Base == (uint64_t)pCtx->cs.Sel << 4), VMX_IGS_V86_CS_BASE_INVALID);
10854 HMVMX_CHECK_BREAK(pCtx->cs.u32Limit == 0xffff, VMX_IGS_V86_CS_LIMIT_INVALID);
10855 HMVMX_CHECK_BREAK(u32CSAttr == 0xf3, VMX_IGS_V86_CS_ATTR_INVALID);
10856 /* SS */
10857 HMVMX_CHECK_BREAK((pCtx->ss.u64Base == (uint64_t)pCtx->ss.Sel << 4), VMX_IGS_V86_SS_BASE_INVALID);
10858 HMVMX_CHECK_BREAK(pCtx->ss.u32Limit == 0xffff, VMX_IGS_V86_SS_LIMIT_INVALID);
10859 HMVMX_CHECK_BREAK(u32SSAttr == 0xf3, VMX_IGS_V86_SS_ATTR_INVALID);
10860 /* DS */
10861 HMVMX_CHECK_BREAK((pCtx->ds.u64Base == (uint64_t)pCtx->ds.Sel << 4), VMX_IGS_V86_DS_BASE_INVALID);
10862 HMVMX_CHECK_BREAK(pCtx->ds.u32Limit == 0xffff, VMX_IGS_V86_DS_LIMIT_INVALID);
10863 HMVMX_CHECK_BREAK(u32DSAttr == 0xf3, VMX_IGS_V86_DS_ATTR_INVALID);
10864 /* ES */
10865 HMVMX_CHECK_BREAK((pCtx->es.u64Base == (uint64_t)pCtx->es.Sel << 4), VMX_IGS_V86_ES_BASE_INVALID);
10866 HMVMX_CHECK_BREAK(pCtx->es.u32Limit == 0xffff, VMX_IGS_V86_ES_LIMIT_INVALID);
10867 HMVMX_CHECK_BREAK(u32ESAttr == 0xf3, VMX_IGS_V86_ES_ATTR_INVALID);
10868 /* FS */
10869 HMVMX_CHECK_BREAK((pCtx->fs.u64Base == (uint64_t)pCtx->fs.Sel << 4), VMX_IGS_V86_FS_BASE_INVALID);
10870 HMVMX_CHECK_BREAK(pCtx->fs.u32Limit == 0xffff, VMX_IGS_V86_FS_LIMIT_INVALID);
10871 HMVMX_CHECK_BREAK(u32FSAttr == 0xf3, VMX_IGS_V86_FS_ATTR_INVALID);
10872 /* GS */
10873 HMVMX_CHECK_BREAK((pCtx->gs.u64Base == (uint64_t)pCtx->gs.Sel << 4), VMX_IGS_V86_GS_BASE_INVALID);
10874 HMVMX_CHECK_BREAK(pCtx->gs.u32Limit == 0xffff, VMX_IGS_V86_GS_LIMIT_INVALID);
10875 HMVMX_CHECK_BREAK(u32GSAttr == 0xf3, VMX_IGS_V86_GS_ATTR_INVALID);
10876 /* 64-bit capable CPUs. */
10877#if HC_ARCH_BITS == 64
10878 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->fs.u64Base), VMX_IGS_FS_BASE_NOT_CANONICAL);
10879 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->gs.u64Base), VMX_IGS_GS_BASE_NOT_CANONICAL);
10880 HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
10881 || X86_IS_CANONICAL(pCtx->ldtr.u64Base), VMX_IGS_LDTR_BASE_NOT_CANONICAL);
10882 HMVMX_CHECK_BREAK(!RT_HI_U32(pCtx->cs.u64Base), VMX_IGS_LONGMODE_CS_BASE_INVALID);
10883 HMVMX_CHECK_BREAK((pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->ss.u64Base),
10884 VMX_IGS_LONGMODE_SS_BASE_INVALID);
10885 HMVMX_CHECK_BREAK((pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->ds.u64Base),
10886 VMX_IGS_LONGMODE_DS_BASE_INVALID);
10887 HMVMX_CHECK_BREAK((pCtx->es.Attr.u & X86DESCATTR_UNUSABLE) || !RT_HI_U32(pCtx->es.u64Base),
10888 VMX_IGS_LONGMODE_ES_BASE_INVALID);
10889#endif
10890 }
10891
10892 /*
10893 * TR.
10894 */
10895 HMVMX_CHECK_BREAK(!(pCtx->tr.Sel & X86_SEL_LDT), VMX_IGS_TR_TI_INVALID);
10896 /* 64-bit capable CPUs. */
10897#if HC_ARCH_BITS == 64
10898 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->tr.u64Base), VMX_IGS_TR_BASE_NOT_CANONICAL);
10899#endif
10900 if (fLongModeGuest)
10901 {
10902 HMVMX_CHECK_BREAK(pCtx->tr.Attr.n.u4Type == 11, /* 64-bit busy TSS. */
10903 VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID);
10904 }
10905 else
10906 {
10907 HMVMX_CHECK_BREAK( pCtx->tr.Attr.n.u4Type == 3 /* 16-bit busy TSS. */
10908 || pCtx->tr.Attr.n.u4Type == 11, /* 32-bit busy TSS.*/
10909 VMX_IGS_TR_ATTR_TYPE_INVALID);
10910 }
10911 HMVMX_CHECK_BREAK(!pCtx->tr.Attr.n.u1DescType, VMX_IGS_TR_ATTR_S_INVALID);
10912 HMVMX_CHECK_BREAK(pCtx->tr.Attr.n.u1Present, VMX_IGS_TR_ATTR_P_INVALID);
10913 HMVMX_CHECK_BREAK(!(pCtx->tr.Attr.u & 0xf00), VMX_IGS_TR_ATTR_RESERVED); /* Bits 11:8 MBZ. */
10914 HMVMX_CHECK_BREAK( (pCtx->tr.u32Limit & 0xfff) == 0xfff
10915 || !(pCtx->tr.Attr.n.u1Granularity), VMX_IGS_TR_ATTR_G_INVALID);
10916 HMVMX_CHECK_BREAK( !(pCtx->tr.u32Limit & 0xfff00000)
10917 || (pCtx->tr.Attr.n.u1Granularity), VMX_IGS_TR_ATTR_G_INVALID);
10918 HMVMX_CHECK_BREAK(!(pCtx->tr.Attr.u & X86DESCATTR_UNUSABLE), VMX_IGS_TR_ATTR_UNUSABLE);
10919
10920 /*
10921 * GDTR and IDTR.
10922 */
10923#if HC_ARCH_BITS == 64
10924 rc = VMXReadVmcs64(VMX_VMCS_GUEST_GDTR_BASE, &u64Val);
10925 AssertRCBreak(rc);
10926 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_GDTR_BASE_NOT_CANONICAL);
10927
10928 rc = VMXReadVmcs64(VMX_VMCS_GUEST_IDTR_BASE, &u64Val);
10929 AssertRCBreak(rc);
10930 HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_IDTR_BASE_NOT_CANONICAL);
10931#endif
10932
10933 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val);
10934 AssertRCBreak(rc);
10935 HMVMX_CHECK_BREAK(!(u32Val & 0xffff0000), VMX_IGS_GDTR_LIMIT_INVALID); /* Bits 31:16 MBZ. */
10936
10937 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val);
10938 AssertRCBreak(rc);
10939 HMVMX_CHECK_BREAK(!(u32Val & 0xffff0000), VMX_IGS_IDTR_LIMIT_INVALID); /* Bits 31:16 MBZ. */
10940
10941 /*
10942 * Guest Non-Register State.
10943 */
10944 /* Activity State. */
10945 uint32_t u32ActivityState;
10946 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_ACTIVITY_STATE, &u32ActivityState);
10947 AssertRCBreak(rc);
10948 HMVMX_CHECK_BREAK( !u32ActivityState
10949 || (u32ActivityState & RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Misc, VMX_BF_MISC_ACTIVITY_STATES)),
10950 VMX_IGS_ACTIVITY_STATE_INVALID);
10951 HMVMX_CHECK_BREAK( !(pCtx->ss.Attr.n.u2Dpl)
10952 || u32ActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT, VMX_IGS_ACTIVITY_STATE_HLT_INVALID);
10953 uint32_t u32IntrState;
10954 rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &u32IntrState);
10955 AssertRCBreak(rc);
10956 if ( u32IntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS
10957 || u32IntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
10958 {
10959 HMVMX_CHECK_BREAK(u32ActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE, VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID);
10960 }
10961
10962 /** @todo Activity state and injecting interrupts. Left as a todo since we
10963 * currently don't use activity states but ACTIVE. */
10964
10965 HMVMX_CHECK_BREAK( !(pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)
10966 || u32ActivityState != VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT, VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID);
10967
10968 /* Guest interruptibility-state. */
10969 HMVMX_CHECK_BREAK(!(u32IntrState & 0xffffffe0), VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED);
10970 HMVMX_CHECK_BREAK((u32IntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS))
10971 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_STI | VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS),
10972 VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID);
10973 HMVMX_CHECK_BREAK( (u32Eflags & X86_EFL_IF)
10974 || !(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI),
10975 VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID);
10976 if (VMX_ENTRY_INT_INFO_IS_VALID(u32EntryInfo))
10977 {
10978 if (VMX_ENTRY_INT_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INT_INFO_TYPE_EXT_INT)
10979 {
10980 HMVMX_CHECK_BREAK( !(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
10981 && !(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS),
10982 VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID);
10983 }
10984 else if (VMX_ENTRY_INT_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INT_INFO_TYPE_NMI)
10985 {
10986 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS),
10987 VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID);
10988 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI),
10989 VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID);
10990 }
10991 }
10992 /** @todo Assumes the processor is not in SMM. */
10993 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI),
10994 VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID);
10995 HMVMX_CHECK_BREAK( !(pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)
10996 || (u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI),
10997 VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID);
10998 if ( (pVCpu->hm.s.vmx.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
10999 && VMX_ENTRY_INT_INFO_IS_VALID(u32EntryInfo)
11000 && VMX_ENTRY_INT_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INT_INFO_TYPE_NMI)
11001 {
11002 HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI),
11003 VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID);
11004 }
11005
11006 /* Pending debug exceptions. */
11007#if HC_ARCH_BITS == 64
11008 rc = VMXReadVmcs64(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, &u64Val);
11009 AssertRCBreak(rc);
11010 /* Bits 63:15, Bit 13, Bits 11:4 MBZ. */
11011 HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffffffffaff0)), VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED);
11012 u32Val = u64Val; /* For pending debug exceptions checks below. */
11013#else
11014 rc = VMXReadVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, &u32Val);
11015 AssertRCBreak(rc);
11016 /* Bits 31:15, Bit 13, Bits 11:4 MBZ. */
11017 HMVMX_CHECK_BREAK(!(u32Val & 0xffffaff0), VMX_IGS_PENDING_DEBUG_RESERVED);
11018#endif
11019
11020 if ( (u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
11021 || (u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS)
11022 || u32ActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
11023 {
11024 if ( (u32Eflags & X86_EFL_TF)
11025 && !(u64DebugCtlMsr & RT_BIT_64(1))) /* Bit 1 is IA32_DEBUGCTL.BTF. */
11026 {
11027 /* Bit 14 is PendingDebug.BS. */
11028 HMVMX_CHECK_BREAK(u32Val & RT_BIT(14), VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET);
11029 }
11030 if ( !(u32Eflags & X86_EFL_TF)
11031 || (u64DebugCtlMsr & RT_BIT_64(1))) /* Bit 1 is IA32_DEBUGCTL.BTF. */
11032 {
11033 /* Bit 14 is PendingDebug.BS. */
11034 HMVMX_CHECK_BREAK(!(u32Val & RT_BIT(14)), VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR);
11035 }
11036 }
11037
11038 /* VMCS link pointer. */
11039 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, &u64Val);
11040 AssertRCBreak(rc);
11041 if (u64Val != UINT64_C(0xffffffffffffffff))
11042 {
11043 HMVMX_CHECK_BREAK(!(u64Val & 0xfff), VMX_IGS_VMCS_LINK_PTR_RESERVED);
11044 /** @todo Bits beyond the processor's physical-address width MBZ. */
11045 /** @todo 32-bit located in memory referenced by value of this field (as a
11046 * physical address) must contain the processor's VMCS revision ID. */
11047 /** @todo SMM checks. */
11048 }
11049
11050 /** @todo Checks on Guest Page-Directory-Pointer-Table Entries when guest is
11051 * not using Nested Paging? */
11052 if ( pVM->hm.s.fNestedPaging
11053 && !fLongModeGuest
11054 && CPUMIsGuestInPAEModeEx(pCtx))
11055 {
11056 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &u64Val);
11057 AssertRCBreak(rc);
11058 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11059
11060 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &u64Val);
11061 AssertRCBreak(rc);
11062 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11063
11064 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &u64Val);
11065 AssertRCBreak(rc);
11066 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11067
11068 rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &u64Val);
11069 AssertRCBreak(rc);
11070 HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11071 }
11072
11073 /* Shouldn't happen but distinguish it from AssertRCBreak() errors. */
11074 if (uError == VMX_IGS_ERROR)
11075 uError = VMX_IGS_REASON_NOT_FOUND;
11076 } while (0);
11077
11078 pVCpu->hm.s.u32HMError = uError;
11079 return uError;
11080
11081#undef HMVMX_ERROR_BREAK
11082#undef HMVMX_CHECK_BREAK
11083}
11084
11085
11086/** @name VM-exit handlers.
11087 * @{
11088 */
11089/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
11090/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- VM-exit handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
11091/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
11092
11093/**
11094 * VM-exit handler for external interrupts (VMX_EXIT_EXT_INT).
11095 */
11096HMVMX_EXIT_DECL hmR0VmxExitExtInt(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11097{
11098 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11099 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
11100 /* Windows hosts (32-bit and 64-bit) have DPC latency issues. See @bugref{6853}. */
11101 if (VMMR0ThreadCtxHookIsEnabled(pVCpu))
11102 return VINF_SUCCESS;
11103 return VINF_EM_RAW_INTERRUPT;
11104}
11105
11106
11107/**
11108 * VM-exit handler for exceptions or NMIs (VMX_EXIT_XCPT_OR_NMI).
11109 */
11110HMVMX_EXIT_DECL hmR0VmxExitXcptOrNmi(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11111{
11112 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11113 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitXcptNmi, y3);
11114
11115 int rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
11116 AssertRCReturn(rc, rc);
11117
11118 uint32_t uIntType = VMX_EXIT_INT_INFO_TYPE(pVmxTransient->uExitIntInfo);
11119 Assert( !(pVCpu->hm.s.vmx.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
11120 && uIntType != VMX_EXIT_INT_INFO_TYPE_EXT_INT);
11121 Assert(VMX_EXIT_INT_INFO_IS_VALID(pVmxTransient->uExitIntInfo));
11122
11123 if (uIntType == VMX_EXIT_INT_INFO_TYPE_NMI)
11124 {
11125 /*
11126 * This cannot be a guest NMI as the only way for the guest to receive an NMI is if we
11127 * injected it ourselves and anything we inject is not going to cause a VM-exit directly
11128 * for the event being injected[1]. Go ahead and dispatch the NMI to the host[2].
11129 *
11130 * [1] -- See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
11131 * [2] -- See Intel spec. 27.5.5 "Updating Non-Register State".
11132 */
11133 VMXDispatchHostNmi();
11134 STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
11135 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
11136 return VINF_SUCCESS;
11137 }
11138
11139 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
11140 VBOXSTRICTRC rcStrictRc1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pVmxTransient);
11141 if (RT_UNLIKELY(rcStrictRc1 == VINF_SUCCESS))
11142 { /* likely */ }
11143 else
11144 {
11145 if (rcStrictRc1 == VINF_HM_DOUBLE_FAULT)
11146 rcStrictRc1 = VINF_SUCCESS;
11147 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
11148 return rcStrictRc1;
11149 }
11150
11151 uint32_t uExitIntInfo = pVmxTransient->uExitIntInfo;
11152 uint32_t uVector = VMX_EXIT_INT_INFO_VECTOR(uExitIntInfo);
11153 switch (uIntType)
11154 {
11155 case VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT: /* Privileged software exception. (#DB from ICEBP) */
11156 Assert(uVector == X86_XCPT_DB);
11157 RT_FALL_THRU();
11158 case VMX_EXIT_INT_INFO_TYPE_SW_XCPT: /* Software exception. (#BP or #OF) */
11159 Assert(uVector == X86_XCPT_BP || uVector == X86_XCPT_OF || uIntType == VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT);
11160 RT_FALL_THRU();
11161 case VMX_EXIT_INT_INFO_TYPE_HW_XCPT:
11162 {
11163 /*
11164 * If there's any exception caused as a result of event injection, the resulting
11165 * secondary/final execption will be pending, we shall continue guest execution
11166 * after injecting the event. The page-fault case is complicated and we manually
11167 * handle any currently pending event in hmR0VmxExitXcptPF.
11168 */
11169 if (!pVCpu->hm.s.Event.fPending)
11170 { /* likely */ }
11171 else if (uVector != X86_XCPT_PF)
11172 {
11173 rc = VINF_SUCCESS;
11174 break;
11175 }
11176
11177 switch (uVector)
11178 {
11179 case X86_XCPT_PF: rc = hmR0VmxExitXcptPF(pVCpu, pVmxTransient); break;
11180 case X86_XCPT_GP: rc = hmR0VmxExitXcptGP(pVCpu, pVmxTransient); break;
11181 case X86_XCPT_MF: rc = hmR0VmxExitXcptMF(pVCpu, pVmxTransient); break;
11182 case X86_XCPT_DB: rc = hmR0VmxExitXcptDB(pVCpu, pVmxTransient); break;
11183 case X86_XCPT_BP: rc = hmR0VmxExitXcptBP(pVCpu, pVmxTransient); break;
11184 case X86_XCPT_AC: rc = hmR0VmxExitXcptAC(pVCpu, pVmxTransient); break;
11185
11186 case X86_XCPT_NM: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
11187 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11188 case X86_XCPT_XF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXF);
11189 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11190 case X86_XCPT_DE: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
11191 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11192 case X86_XCPT_UD: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
11193 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11194 case X86_XCPT_SS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
11195 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11196 case X86_XCPT_NP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
11197 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11198 case X86_XCPT_TS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestTS);
11199 rc = hmR0VmxExitXcptGeneric(pVCpu, pVmxTransient); break;
11200 default:
11201 {
11202 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXcpUnk);
11203 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
11204 {
11205 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
11206 Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
11207 Assert(CPUMIsGuestInRealModeEx(&pVCpu->cpum.GstCtx));
11208
11209 rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR0);
11210 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11211 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
11212 AssertRCReturn(rc, rc);
11213 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(uExitIntInfo),
11214 pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode,
11215 0 /* GCPtrFaultAddress */);
11216 }
11217 else
11218 {
11219 AssertMsgFailed(("Unexpected VM-exit caused by exception %#x\n", uVector));
11220 pVCpu->hm.s.u32HMError = uVector;
11221 rc = VERR_VMX_UNEXPECTED_EXCEPTION;
11222 }
11223 break;
11224 }
11225 }
11226 break;
11227 }
11228
11229 default:
11230 {
11231 pVCpu->hm.s.u32HMError = uExitIntInfo;
11232 rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE;
11233 AssertMsgFailed(("Unexpected interruption info %#x\n", VMX_EXIT_INT_INFO_TYPE(uExitIntInfo)));
11234 break;
11235 }
11236 }
11237 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
11238 return rc;
11239}
11240
11241
11242/**
11243 * VM-exit handler for interrupt-window exiting (VMX_EXIT_INT_WINDOW).
11244 */
11245HMVMX_EXIT_NSRC_DECL hmR0VmxExitIntWindow(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11246{
11247 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11248
11249 /* Indicate that we no longer need to VM-exit when the guest is ready to receive interrupts, it is now ready. */
11250 hmR0VmxClearIntWindowExitVmcs(pVCpu);
11251
11252 /* Deliver the pending interrupts via hmR0VmxEvaluatePendingEvent() and resume guest execution. */
11253 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
11254 return VINF_SUCCESS;
11255}
11256
11257
11258/**
11259 * VM-exit handler for NMI-window exiting (VMX_EXIT_NMI_WINDOW).
11260 */
11261HMVMX_EXIT_NSRC_DECL hmR0VmxExitNmiWindow(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11262{
11263 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11264 if (RT_UNLIKELY(!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)))
11265 {
11266 AssertMsgFailed(("Unexpected NMI-window exit.\n"));
11267 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11268 }
11269
11270 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS));
11271
11272 /*
11273 * If block-by-STI is set when we get this VM-exit, it means the CPU doesn't block NMIs following STI.
11274 * It is therefore safe to unblock STI and deliver the NMI ourselves. See @bugref{7445}.
11275 */
11276 uint32_t fIntrState = 0;
11277 int rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &fIntrState);
11278 AssertRCReturn(rc, rc);
11279 Assert(!(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS));
11280 if (fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)
11281 {
11282 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
11283 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
11284
11285 fIntrState &= ~VMX_VMCS_GUEST_INT_STATE_BLOCK_STI;
11286 rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_INT_STATE, fIntrState);
11287 AssertRCReturn(rc, rc);
11288 }
11289
11290 /* Indicate that we no longer need to VM-exit when the guest is ready to receive NMIs, it is now ready */
11291 hmR0VmxClearNmiWindowExitVmcs(pVCpu);
11292
11293 /* Deliver the pending NMI via hmR0VmxEvaluatePendingEvent() and resume guest execution. */
11294 return VINF_SUCCESS;
11295}
11296
11297
11298/**
11299 * VM-exit handler for WBINVD (VMX_EXIT_WBINVD). Conditional VM-exit.
11300 */
11301HMVMX_EXIT_NSRC_DECL hmR0VmxExitWbinvd(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11302{
11303 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11304 return hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11305}
11306
11307
11308/**
11309 * VM-exit handler for INVD (VMX_EXIT_INVD). Unconditional VM-exit.
11310 */
11311HMVMX_EXIT_NSRC_DECL hmR0VmxExitInvd(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11312{
11313 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11314 return hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11315}
11316
11317
11318/**
11319 * VM-exit handler for CPUID (VMX_EXIT_CPUID). Unconditional VM-exit.
11320 */
11321HMVMX_EXIT_DECL hmR0VmxExitCpuid(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11322{
11323 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11324
11325 /*
11326 * Get the state we need and update the exit history entry.
11327 */
11328 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11329 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
11330 AssertRCReturn(rc, rc);
11331
11332 VBOXSTRICTRC rcStrict;
11333 PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
11334 EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_CPUID),
11335 pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
11336 if (!pExitRec)
11337 {
11338 /*
11339 * Regular CPUID instruction execution.
11340 */
11341 rcStrict = IEMExecDecodedCpuid(pVCpu, pVmxTransient->cbInstr);
11342 if (rcStrict == VINF_SUCCESS)
11343 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
11344 else if (rcStrict == VINF_IEM_RAISED_XCPT)
11345 {
11346 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
11347 rcStrict = VINF_SUCCESS;
11348 }
11349 }
11350 else
11351 {
11352 /*
11353 * Frequent exit or something needing probing. Get state and call EMHistoryExec.
11354 */
11355 int rc2 = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
11356 AssertRCReturn(rc2, rc2);
11357
11358 Log4(("CpuIdExit/%u: %04x:%08RX64: %#x/%#x -> EMHistoryExec\n",
11359 pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ecx));
11360
11361 rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
11362 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
11363
11364 Log4(("CpuIdExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
11365 pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
11366 VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
11367 }
11368 return rcStrict;
11369}
11370
11371
11372/**
11373 * VM-exit handler for GETSEC (VMX_EXIT_GETSEC). Unconditional VM-exit.
11374 */
11375HMVMX_EXIT_DECL hmR0VmxExitGetsec(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11376{
11377 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11378 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR4);
11379 AssertRCReturn(rc, rc);
11380
11381 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_SMXE)
11382 return VINF_EM_RAW_EMULATE_INSTR;
11383
11384 AssertMsgFailed(("hmR0VmxExitGetsec: unexpected VM-exit when CR4.SMXE is 0.\n"));
11385 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11386}
11387
11388
11389/**
11390 * VM-exit handler for RDTSC (VMX_EXIT_RDTSC). Conditional VM-exit.
11391 */
11392HMVMX_EXIT_DECL hmR0VmxExitRdtsc(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11393{
11394 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11395 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
11396 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11397 AssertRCReturn(rc, rc);
11398
11399 VBOXSTRICTRC rcStrict = IEMExecDecodedRdtsc(pVCpu, pVmxTransient->cbInstr);
11400 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
11401 {
11402 /* If we get a spurious VM-exit when offsetting is enabled,
11403 we must reset offsetting on VM-reentry. See @bugref{6634}. */
11404 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING)
11405 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
11406 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
11407 }
11408 else if (rcStrict == VINF_IEM_RAISED_XCPT)
11409 {
11410 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
11411 rcStrict = VINF_SUCCESS;
11412 }
11413 return rcStrict;
11414}
11415
11416
11417/**
11418 * VM-exit handler for RDTSCP (VMX_EXIT_RDTSCP). Conditional VM-exit.
11419 */
11420HMVMX_EXIT_DECL hmR0VmxExitRdtscp(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11421{
11422 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11423 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK | CPUMCTX_EXTRN_TSC_AUX);
11424 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11425 AssertRCReturn(rc, rc);
11426
11427 VBOXSTRICTRC rcStrict = IEMExecDecodedRdtscp(pVCpu, pVmxTransient->cbInstr);
11428 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
11429 {
11430 /* If we get a spurious VM-exit when offsetting is enabled,
11431 we must reset offsetting on VM-reentry. See @bugref{6634}. */
11432 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING)
11433 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
11434 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
11435 }
11436 else if (rcStrict == VINF_IEM_RAISED_XCPT)
11437 {
11438 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
11439 rcStrict = VINF_SUCCESS;
11440 }
11441 return rcStrict;
11442}
11443
11444
11445/**
11446 * VM-exit handler for RDPMC (VMX_EXIT_RDPMC). Conditional VM-exit.
11447 */
11448HMVMX_EXIT_DECL hmR0VmxExitRdpmc(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11449{
11450 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11451 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS);
11452 AssertRCReturn(rc, rc);
11453
11454 PVM pVM = pVCpu->CTX_SUFF(pVM);
11455 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
11456 rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
11457 if (RT_LIKELY(rc == VINF_SUCCESS))
11458 {
11459 rc = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11460 Assert(pVmxTransient->cbInstr == 2);
11461 }
11462 else
11463 {
11464 AssertMsgFailed(("hmR0VmxExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
11465 rc = VERR_EM_INTERPRETER;
11466 }
11467 return rc;
11468}
11469
11470
11471/**
11472 * VM-exit handler for VMCALL (VMX_EXIT_VMCALL). Unconditional VM-exit.
11473 */
11474HMVMX_EXIT_DECL hmR0VmxExitVmcall(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11475{
11476 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11477
11478 VBOXSTRICTRC rcStrict = VERR_VMX_IPE_3;
11479 if (EMAreHypercallInstructionsEnabled(pVCpu))
11480 {
11481 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_CR0
11482 | CPUMCTX_EXTRN_SS | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
11483 AssertRCReturn(rc, rc);
11484
11485 /* Perform the hypercall. */
11486 rcStrict = GIMHypercall(pVCpu, &pVCpu->cpum.GstCtx);
11487 if (rcStrict == VINF_SUCCESS)
11488 {
11489 rc = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11490 AssertRCReturn(rc, rc);
11491 }
11492 else
11493 Assert( rcStrict == VINF_GIM_R3_HYPERCALL
11494 || rcStrict == VINF_GIM_HYPERCALL_CONTINUING
11495 || RT_FAILURE(rcStrict));
11496
11497 /* If the hypercall changes anything other than guest's general-purpose registers,
11498 we would need to reload the guest changed bits here before VM-entry. */
11499 }
11500 else
11501 Log4Func(("Hypercalls not enabled\n"));
11502
11503 /* If hypercalls are disabled or the hypercall failed for some reason, raise #UD and continue. */
11504 if (RT_FAILURE(rcStrict))
11505 {
11506 hmR0VmxSetPendingXcptUD(pVCpu);
11507 rcStrict = VINF_SUCCESS;
11508 }
11509
11510 return rcStrict;
11511}
11512
11513
11514/**
11515 * VM-exit handler for INVLPG (VMX_EXIT_INVLPG). Conditional VM-exit.
11516 */
11517HMVMX_EXIT_DECL hmR0VmxExitInvlpg(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11518{
11519 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11520 Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging || pVCpu->hm.s.fUsingDebugLoop);
11521
11522 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
11523 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11524 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
11525 AssertRCReturn(rc, rc);
11526
11527 VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpg(pVCpu, pVmxTransient->cbInstr, pVmxTransient->uExitQual);
11528
11529 if (rcStrict == VINF_SUCCESS || rcStrict == VINF_PGM_SYNC_CR3)
11530 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
11531 else if (rcStrict == VINF_IEM_RAISED_XCPT)
11532 {
11533 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
11534 rcStrict = VINF_SUCCESS;
11535 }
11536 else
11537 AssertMsgFailed(("Unexpected IEMExecDecodedInvlpg(%#RX64) sttus: %Rrc\n", pVmxTransient->uExitQual,
11538 VBOXSTRICTRC_VAL(rcStrict)));
11539 return rcStrict;
11540}
11541
11542
11543/**
11544 * VM-exit handler for MONITOR (VMX_EXIT_MONITOR). Conditional VM-exit.
11545 */
11546HMVMX_EXIT_DECL hmR0VmxExitMonitor(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11547{
11548 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11549 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS);
11550 AssertRCReturn(rc, rc);
11551
11552 PVM pVM = pVCpu->CTX_SUFF(pVM);
11553 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
11554 rc = EMInterpretMonitor(pVM, pVCpu, CPUMCTX2CORE(pCtx));
11555 if (RT_LIKELY(rc == VINF_SUCCESS))
11556 rc = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11557 else
11558 {
11559 AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0VmxExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
11560 rc = VERR_EM_INTERPRETER;
11561 }
11562 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
11563 return rc;
11564}
11565
11566
11567/**
11568 * VM-exit handler for MWAIT (VMX_EXIT_MWAIT). Conditional VM-exit.
11569 */
11570HMVMX_EXIT_DECL hmR0VmxExitMwait(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11571{
11572 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11573 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS);
11574 AssertRCReturn(rc, rc);
11575
11576 PVM pVM = pVCpu->CTX_SUFF(pVM);
11577 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
11578 VBOXSTRICTRC rc2 = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pCtx));
11579 rc = VBOXSTRICTRC_VAL(rc2);
11580 if (RT_LIKELY( rc == VINF_SUCCESS
11581 || rc == VINF_EM_HALT))
11582 {
11583 int rc3 = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11584 AssertRCReturn(rc3, rc3);
11585
11586 if ( rc == VINF_EM_HALT
11587 && EMMonitorWaitShouldContinue(pVCpu, pCtx))
11588 rc = VINF_SUCCESS;
11589 }
11590 else
11591 {
11592 AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0VmxExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
11593 rc = VERR_EM_INTERPRETER;
11594 }
11595 AssertMsg(rc == VINF_SUCCESS || rc == VINF_EM_HALT || rc == VERR_EM_INTERPRETER,
11596 ("hmR0VmxExitMwait: failed, invalid error code %Rrc\n", rc));
11597 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
11598 return rc;
11599}
11600
11601
11602/**
11603 * VM-exit handler for RSM (VMX_EXIT_RSM). Unconditional VM-exit.
11604 */
11605HMVMX_EXIT_NSRC_DECL hmR0VmxExitRsm(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11606{
11607 /*
11608 * Execution of RSM outside of SMM mode causes #UD regardless of VMX root or VMX non-root
11609 * mode. In theory, we should never get this VM-exit. This can happen only if dual-monitor
11610 * treatment of SMI and VMX is enabled, which can (only?) be done by executing VMCALL in
11611 * VMX root operation. If we get here, something funny is going on.
11612 *
11613 * See Intel spec. 33.15.5 "Enabling the Dual-Monitor Treatment".
11614 */
11615 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11616 AssertMsgFailed(("Unexpected RSM VM-exit\n"));
11617 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11618}
11619
11620
11621/**
11622 * VM-exit handler for SMI (VMX_EXIT_SMI). Unconditional VM-exit.
11623 */
11624HMVMX_EXIT_NSRC_DECL hmR0VmxExitSmi(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11625{
11626 /*
11627 * This can only happen if we support dual-monitor treatment of SMI, which can be activated
11628 * by executing VMCALL in VMX root operation. Only an STM (SMM transfer monitor) would get
11629 * this VM-exit when we (the executive monitor) execute a VMCALL in VMX root mode or receive
11630 * an SMI. If we get here, something funny is going on.
11631 *
11632 * See Intel spec. 33.15.6 "Activating the Dual-Monitor Treatment"
11633 * See Intel spec. 25.3 "Other Causes of VM-Exits"
11634 */
11635 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11636 AssertMsgFailed(("Unexpected SMI VM-exit\n"));
11637 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11638}
11639
11640
11641/**
11642 * VM-exit handler for IO SMI (VMX_EXIT_IO_SMI). Unconditional VM-exit.
11643 */
11644HMVMX_EXIT_NSRC_DECL hmR0VmxExitIoSmi(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11645{
11646 /* Same treatment as VMX_EXIT_SMI. See comment in hmR0VmxExitSmi(). */
11647 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11648 AssertMsgFailed(("Unexpected IO SMI VM-exit\n"));
11649 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11650}
11651
11652
11653/**
11654 * VM-exit handler for SIPI (VMX_EXIT_SIPI). Conditional VM-exit.
11655 */
11656HMVMX_EXIT_NSRC_DECL hmR0VmxExitSipi(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11657{
11658 /*
11659 * SIPI exits can only occur in VMX non-root operation when the "wait-for-SIPI" guest activity state is used.
11660 * We don't make use of it as our guests don't have direct access to the host LAPIC.
11661 * See Intel spec. 25.3 "Other Causes of VM-exits".
11662 */
11663 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11664 AssertMsgFailed(("Unexpected SIPI VM-exit\n"));
11665 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11666}
11667
11668
11669/**
11670 * VM-exit handler for INIT signal (VMX_EXIT_INIT_SIGNAL). Unconditional
11671 * VM-exit.
11672 */
11673HMVMX_EXIT_NSRC_DECL hmR0VmxExitInitSignal(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11674{
11675 /*
11676 * INIT signals are blocked in VMX root operation by VMXON and by SMI in SMM.
11677 * See Intel spec. 33.14.1 Default Treatment of SMI Delivery" and Intel spec. 29.3 "VMX Instructions" for "VMXON".
11678 *
11679 * It is -NOT- blocked in VMX non-root operation so we can, in theory, still get these VM-exits.
11680 * See Intel spec. "23.8 Restrictions on VMX operation".
11681 */
11682 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11683 return VINF_SUCCESS;
11684}
11685
11686
11687/**
11688 * VM-exit handler for triple faults (VMX_EXIT_TRIPLE_FAULT). Unconditional
11689 * VM-exit.
11690 */
11691HMVMX_EXIT_DECL hmR0VmxExitTripleFault(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11692{
11693 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11694 return VINF_EM_RESET;
11695}
11696
11697
11698/**
11699 * VM-exit handler for HLT (VMX_EXIT_HLT). Conditional VM-exit.
11700 */
11701HMVMX_EXIT_DECL hmR0VmxExitHlt(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11702{
11703 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11704 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_HLT_EXIT);
11705
11706 int rc = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
11707 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_RFLAGS);
11708 AssertRCReturn(rc, rc);
11709
11710 if (EMShouldContinueAfterHalt(pVCpu, &pVCpu->cpum.GstCtx)) /* Requires eflags. */
11711 rc = VINF_SUCCESS;
11712 else
11713 rc = VINF_EM_HALT;
11714
11715 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
11716 if (rc != VINF_SUCCESS)
11717 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
11718 return rc;
11719}
11720
11721
11722/**
11723 * VM-exit handler for instructions that result in a \#UD exception delivered to
11724 * the guest.
11725 */
11726HMVMX_EXIT_NSRC_DECL hmR0VmxExitSetPendingXcptUD(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11727{
11728 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11729 hmR0VmxSetPendingXcptUD(pVCpu);
11730 return VINF_SUCCESS;
11731}
11732
11733
11734/**
11735 * VM-exit handler for expiry of the VMX preemption timer.
11736 */
11737HMVMX_EXIT_DECL hmR0VmxExitPreemptTimer(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11738{
11739 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11740
11741 /* If the preemption-timer has expired, reinitialize the preemption timer on next VM-entry. */
11742 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
11743
11744 /* If there are any timer events pending, fall back to ring-3, otherwise resume guest execution. */
11745 PVM pVM = pVCpu->CTX_SUFF(pVM);
11746 bool fTimersPending = TMTimerPollBool(pVM, pVCpu);
11747 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPreemptTimer);
11748 return fTimersPending ? VINF_EM_RAW_TIMER_PENDING : VINF_SUCCESS;
11749}
11750
11751
11752/**
11753 * VM-exit handler for XSETBV (VMX_EXIT_XSETBV). Unconditional VM-exit.
11754 */
11755HMVMX_EXIT_DECL hmR0VmxExitXsetbv(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11756{
11757 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11758
11759 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11760 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK | CPUMCTX_EXTRN_CR4);
11761 AssertRCReturn(rc, rc);
11762
11763 VBOXSTRICTRC rcStrict = IEMExecDecodedXsetbv(pVCpu, pVmxTransient->cbInstr);
11764 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, rcStrict != VINF_IEM_RAISED_XCPT ? HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS
11765 : HM_CHANGED_RAISED_XCPT_MASK);
11766
11767 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
11768 pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
11769
11770 return rcStrict;
11771}
11772
11773
11774/**
11775 * VM-exit handler for INVPCID (VMX_EXIT_INVPCID). Conditional VM-exit.
11776 */
11777HMVMX_EXIT_DECL hmR0VmxExitInvpcid(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11778{
11779 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11780 /** @todo Use VM-exit instruction information. */
11781 return VERR_EM_INTERPRETER;
11782}
11783
11784
11785/**
11786 * VM-exit handler for invalid-guest-state (VMX_EXIT_ERR_INVALID_GUEST_STATE).
11787 * Error VM-exit.
11788 */
11789HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrInvalidGuestState(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11790{
11791 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
11792 AssertRCReturn(rc, rc);
11793 rc = hmR0VmxCheckVmcsCtls(pVCpu);
11794 if (RT_FAILURE(rc))
11795 return rc;
11796
11797 uint32_t uInvalidReason = hmR0VmxCheckGuestState(pVCpu);
11798 NOREF(uInvalidReason);
11799
11800#ifdef VBOX_STRICT
11801 uint32_t fIntrState;
11802 RTHCUINTREG uHCReg;
11803 uint64_t u64Val;
11804 uint32_t u32Val;
11805
11806 rc = hmR0VmxReadEntryIntInfoVmcs(pVmxTransient);
11807 rc |= hmR0VmxReadEntryXcptErrorCodeVmcs(pVmxTransient);
11808 rc |= hmR0VmxReadEntryInstrLenVmcs(pVmxTransient);
11809 rc |= VMXReadVmcs32(VMX_VMCS32_GUEST_INT_STATE, &fIntrState);
11810 AssertRCReturn(rc, rc);
11811
11812 Log4(("uInvalidReason %u\n", uInvalidReason));
11813 Log4(("VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO %#RX32\n", pVmxTransient->uEntryIntInfo));
11814 Log4(("VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE %#RX32\n", pVmxTransient->uEntryXcptErrorCode));
11815 Log4(("VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH %#RX32\n", pVmxTransient->cbEntryInstr));
11816 Log4(("VMX_VMCS32_GUEST_INT_STATE %#RX32\n", fIntrState));
11817
11818 rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &u32Val); AssertRC(rc);
11819 Log4(("VMX_VMCS_GUEST_CR0 %#RX32\n", u32Val));
11820 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_MASK, &uHCReg); AssertRC(rc);
11821 Log4(("VMX_VMCS_CTRL_CR0_MASK %#RHr\n", uHCReg));
11822 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_READ_SHADOW, &uHCReg); AssertRC(rc);
11823 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
11824 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_MASK, &uHCReg); AssertRC(rc);
11825 Log4(("VMX_VMCS_CTRL_CR4_MASK %#RHr\n", uHCReg));
11826 rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uHCReg); AssertRC(rc);
11827 Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
11828 rc = VMXReadVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, &u64Val); AssertRC(rc);
11829 Log4(("VMX_VMCS64_CTRL_EPTP_FULL %#RX64\n", u64Val));
11830
11831 hmR0DumpRegs(pVCpu);
11832#else
11833 NOREF(pVmxTransient);
11834#endif
11835
11836 return VERR_VMX_INVALID_GUEST_STATE;
11837}
11838
11839
11840/**
11841 * VM-exit handler for VM-entry failure due to an MSR-load
11842 * (VMX_EXIT_ERR_MSR_LOAD). Error VM-exit.
11843 */
11844HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrMsrLoad(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11845{
11846 AssertMsgFailed(("Unexpected MSR-load exit\n"));
11847 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11848}
11849
11850
11851/**
11852 * VM-exit handler for VM-entry failure due to a machine-check event
11853 * (VMX_EXIT_ERR_MACHINE_CHECK). Error VM-exit.
11854 */
11855HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrMachineCheck(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11856{
11857 AssertMsgFailed(("Unexpected machine-check event exit\n"));
11858 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11859}
11860
11861
11862/**
11863 * VM-exit handler for all undefined reasons. Should never ever happen.. in
11864 * theory.
11865 */
11866HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrUndefined(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11867{
11868 RT_NOREF2(pVCpu, pVmxTransient);
11869 AssertMsgFailed(("Huh!? Undefined VM-exit reason %d\n", pVmxTransient->uExitReason));
11870 return VERR_VMX_UNDEFINED_EXIT_CODE;
11871}
11872
11873
11874/**
11875 * VM-exit handler for XDTR (LGDT, SGDT, LIDT, SIDT) accesses
11876 * (VMX_EXIT_GDTR_IDTR_ACCESS) and LDT and TR access (LLDT, LTR, SLDT, STR).
11877 * Conditional VM-exit.
11878 */
11879HMVMX_EXIT_DECL hmR0VmxExitXdtrAccess(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11880{
11881 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11882
11883 /* By default, we don't enable VMX_PROC_CTLS2_DESCRIPTOR_TABLE_EXIT. */
11884 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitXdtrAccess);
11885 if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT)
11886 return VERR_EM_INTERPRETER;
11887 AssertMsgFailed(("Unexpected XDTR access\n"));
11888 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11889}
11890
11891
11892/**
11893 * VM-exit handler for RDRAND (VMX_EXIT_RDRAND). Conditional VM-exit.
11894 */
11895HMVMX_EXIT_DECL hmR0VmxExitRdrand(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11896{
11897 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11898
11899 /* By default, we don't enable VMX_PROC_CTLS2_RDRAND_EXIT. */
11900 if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT)
11901 return VERR_EM_INTERPRETER;
11902 AssertMsgFailed(("Unexpected RDRAND exit\n"));
11903 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11904}
11905
11906
11907/**
11908 * VM-exit handler for RDMSR (VMX_EXIT_RDMSR).
11909 */
11910HMVMX_EXIT_DECL hmR0VmxExitRdmsr(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11911{
11912 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11913
11914 /** @todo Optimize this: We currently drag in in the whole MSR state
11915 * (CPUMCTX_EXTRN_ALL_MSRS) here. We should optimize this to only get
11916 * MSRs required. That would require changes to IEM and possibly CPUM too.
11917 * (Should probably do it lazy fashion from CPUMAllMsrs.cpp). */
11918 uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
11919 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11920 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_ALL_MSRS);
11921 switch (idMsr)
11922 {
11923 /* The FS and GS base MSRs are not part of the above all-MSRs mask. */
11924 case MSR_K8_FS_BASE: rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_FS); break;
11925 case MSR_K8_GS_BASE: rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_GS); break;
11926 }
11927 AssertRCReturn(rc, rc);
11928
11929 Log4Func(("ecx=%#RX32\n", idMsr));
11930
11931#ifdef VBOX_STRICT
11932 if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
11933 {
11934 if ( hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, idMsr)
11935 && idMsr != MSR_K6_EFER)
11936 {
11937 AssertMsgFailed(("Unexpected RDMSR for an MSR in the auto-load/store area in the VMCS. ecx=%#RX32\n", idMsr));
11938 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11939 }
11940 if (hmR0VmxIsLazyGuestMsr(pVCpu, idMsr))
11941 {
11942 VMXMSREXITREAD enmRead;
11943 VMXMSREXITWRITE enmWrite;
11944 int rc2 = HMVmxGetMsrPermission(pVCpu->hm.s.vmx.pvMsrBitmap, idMsr, &enmRead, &enmWrite);
11945 AssertRCReturn(rc2, rc2);
11946 if (enmRead == VMXMSREXIT_PASSTHRU_READ)
11947 {
11948 AssertMsgFailed(("Unexpected RDMSR for a passthru lazy-restore MSR. ecx=%#RX32\n", idMsr));
11949 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
11950 }
11951 }
11952 }
11953#endif
11954
11955 VBOXSTRICTRC rcStrict = IEMExecDecodedRdmsr(pVCpu, pVmxTransient->cbInstr);
11956 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
11957 if (rcStrict == VINF_SUCCESS)
11958 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS
11959 | HM_CHANGED_GUEST_RAX | HM_CHANGED_GUEST_RDX);
11960 else if (rcStrict == VINF_IEM_RAISED_XCPT)
11961 {
11962 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
11963 rcStrict = VINF_SUCCESS;
11964 }
11965 else
11966 AssertMsg(rcStrict == VINF_CPUM_R3_MSR_READ, ("Unexpected IEMExecDecodedRdmsr status: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
11967
11968 return rcStrict;
11969}
11970
11971
11972/**
11973 * VM-exit handler for WRMSR (VMX_EXIT_WRMSR).
11974 */
11975HMVMX_EXIT_DECL hmR0VmxExitWrmsr(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
11976{
11977 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
11978
11979 /** @todo Optimize this: We currently drag in in the whole MSR state
11980 * (CPUMCTX_EXTRN_ALL_MSRS) here. We should optimize this to only get
11981 * MSRs required. That would require changes to IEM and possibly CPUM too.
11982 * (Should probably do it lazy fashion from CPUMAllMsrs.cpp). */
11983 uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
11984 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11985 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK
11986 | CPUMCTX_EXTRN_ALL_MSRS);
11987 switch (idMsr)
11988 {
11989 /*
11990 * The FS and GS base MSRs are not part of the above all-MSRs mask.
11991 *
11992 * Although we don't need to fetch the base as it will be overwritten shortly, while
11993 * loading guest-state we would also load the entire segment register including limit
11994 * and attributes and thus we need to load them here.
11995 */
11996 case MSR_K8_FS_BASE: rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_FS); break;
11997 case MSR_K8_GS_BASE: rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_GS); break;
11998 }
11999 AssertRCReturn(rc, rc);
12000
12001 Log4Func(("ecx=%#RX32 edx:eax=%#RX32:%#RX32\n", idMsr, pVCpu->cpum.GstCtx.edx, pVCpu->cpum.GstCtx.eax));
12002
12003 VBOXSTRICTRC rcStrict = IEMExecDecodedWrmsr(pVCpu, pVmxTransient->cbInstr);
12004 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
12005
12006 if (rcStrict == VINF_SUCCESS)
12007 {
12008 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
12009
12010 /* If this is an X2APIC WRMSR access, update the APIC state as well. */
12011 if ( idMsr == MSR_IA32_APICBASE
12012 || ( idMsr >= MSR_IA32_X2APIC_START
12013 && idMsr <= MSR_IA32_X2APIC_END))
12014 {
12015 /*
12016 * We've already saved the APIC related guest-state (TPR) in hmR0VmxPostRunGuest(). When full APIC register
12017 * virtualization is implemented we'll have to make sure APIC state is saved from the VMCS before IEM changes it.
12018 */
12019 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
12020 }
12021 else if (idMsr == MSR_IA32_TSC) /* Windows 7 does this during bootup. See @bugref{6398}. */
12022 pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
12023 else if (idMsr == MSR_K6_EFER)
12024 {
12025 /*
12026 * If the guest touches EFER we need to update the VM-Entry and VM-Exit controls as well,
12027 * even if it is -not- touching bits that cause paging mode changes (LMA/LME). We care about
12028 * the other bits as well, SCE and NXE. See @bugref{7368}.
12029 */
12030 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_EFER_MSR | HM_CHANGED_VMX_ENTRY_CTLS
12031 | HM_CHANGED_VMX_EXIT_CTLS);
12032 }
12033
12034 /* Update MSRs that are part of the VMCS and auto-load/store area when MSR-bitmaps are not supported. */
12035 if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS))
12036 {
12037 switch (idMsr)
12038 {
12039 case MSR_IA32_SYSENTER_CS: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_CS_MSR); break;
12040 case MSR_IA32_SYSENTER_EIP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
12041 case MSR_IA32_SYSENTER_ESP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
12042 case MSR_K8_FS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS); break;
12043 case MSR_K8_GS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_GS); break;
12044 case MSR_K6_EFER: /* Nothing to do, already handled above. */ break;
12045 default:
12046 {
12047 if (hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, idMsr))
12048 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_VMX_GUEST_AUTO_MSRS);
12049 else if (hmR0VmxIsLazyGuestMsr(pVCpu, idMsr))
12050 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_VMX_GUEST_LAZY_MSRS);
12051 break;
12052 }
12053 }
12054 }
12055#ifdef VBOX_STRICT
12056 else
12057 {
12058 /* Paranoia. Validate that MSRs in the MSR-bitmaps with write-passthru are not intercepted. */
12059 switch (idMsr)
12060 {
12061 case MSR_IA32_SYSENTER_CS:
12062 case MSR_IA32_SYSENTER_EIP:
12063 case MSR_IA32_SYSENTER_ESP:
12064 case MSR_K8_FS_BASE:
12065 case MSR_K8_GS_BASE:
12066 {
12067 AssertMsgFailed(("Unexpected WRMSR for an MSR in the VMCS. ecx=%#RX32\n", idMsr));
12068 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
12069 }
12070
12071 /* Writes to MSRs in auto-load/store area/swapped MSRs, shouldn't cause VM-exits with MSR-bitmaps. */
12072 default:
12073 {
12074 if (hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, idMsr))
12075 {
12076 /* EFER writes are always intercepted, see hmR0VmxExportGuestMsrs(). */
12077 if (idMsr != MSR_K6_EFER)
12078 {
12079 AssertMsgFailed(("Unexpected WRMSR for an MSR in the auto-load/store area in the VMCS. ecx=%#RX32\n",
12080 idMsr));
12081 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
12082 }
12083 }
12084
12085 if (hmR0VmxIsLazyGuestMsr(pVCpu, idMsr))
12086 {
12087 VMXMSREXITREAD enmRead;
12088 VMXMSREXITWRITE enmWrite;
12089 int rc2 = HMVmxGetMsrPermission(pVCpu->hm.s.vmx.pvMsrBitmap, idMsr, &enmRead, &enmWrite);
12090 AssertRCReturn(rc2, rc2);
12091 if (enmWrite == VMXMSREXIT_PASSTHRU_WRITE)
12092 {
12093 AssertMsgFailed(("Unexpected WRMSR for passthru, lazy-restore MSR. ecx=%#RX32\n", idMsr));
12094 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
12095 }
12096 }
12097 break;
12098 }
12099 }
12100 }
12101#endif /* VBOX_STRICT */
12102 }
12103 else if (rcStrict == VINF_IEM_RAISED_XCPT)
12104 {
12105 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
12106 rcStrict = VINF_SUCCESS;
12107 }
12108 else
12109 AssertMsg(rcStrict == VINF_CPUM_R3_MSR_WRITE, ("Unexpected IEMExecDecodedWrmsr status: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12110
12111 return rcStrict;
12112}
12113
12114
12115/**
12116 * VM-exit handler for PAUSE (VMX_EXIT_PAUSE). Conditional VM-exit.
12117 */
12118HMVMX_EXIT_DECL hmR0VmxExitPause(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12119{
12120 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12121 /** @todo The guest has likely hit a contended spinlock. We might want to
12122 * poke a schedule different guest VCPU. */
12123 return VINF_EM_RAW_INTERRUPT;
12124}
12125
12126
12127/**
12128 * VM-exit handler for when the TPR value is lowered below the specified
12129 * threshold (VMX_EXIT_TPR_BELOW_THRESHOLD). Conditional VM-exit.
12130 */
12131HMVMX_EXIT_NSRC_DECL hmR0VmxExitTprBelowThreshold(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12132{
12133 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12134 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
12135
12136 /*
12137 * The TPR shadow would've been synced with the APIC TPR in hmR0VmxPostRunGuest(). We'll re-evaluate
12138 * pending interrupts and inject them before the next VM-entry so we can just continue execution here.
12139 */
12140 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTprBelowThreshold);
12141 return VINF_SUCCESS;
12142}
12143
12144
12145/**
12146 * VM-exit handler for control-register accesses (VMX_EXIT_MOV_CRX). Conditional
12147 * VM-exit.
12148 *
12149 * @retval VINF_SUCCESS when guest execution can continue.
12150 * @retval VINF_PGM_SYNC_CR3 CR3 sync is required, back to ring-3.
12151 * @retval VERR_EM_INTERPRETER when something unexpected happened, fallback to
12152 * interpreter.
12153 */
12154HMVMX_EXIT_DECL hmR0VmxExitMovCRx(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12155{
12156 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12157 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitMovCRx, y2);
12158
12159 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12160 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
12161 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
12162 AssertRCReturn(rc, rc);
12163
12164 VBOXSTRICTRC rcStrict;
12165 PVM pVM = pVCpu->CTX_SUFF(pVM);
12166 RTGCUINTPTR const uExitQual = pVmxTransient->uExitQual;
12167 uint32_t const uAccessType = VMX_EXIT_QUAL_CRX_ACCESS(uExitQual);
12168 switch (uAccessType)
12169 {
12170 case VMX_EXIT_QUAL_CRX_ACCESS_WRITE: /* MOV to CRx */
12171 {
12172 uint32_t const uOldCr0 = pVCpu->cpum.GstCtx.cr0;
12173 rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, pVmxTransient->cbInstr, VMX_EXIT_QUAL_CRX_REGISTER(uExitQual),
12174 VMX_EXIT_QUAL_CRX_GENREG(uExitQual));
12175 AssertMsg( rcStrict == VINF_SUCCESS
12176 || rcStrict == VINF_IEM_RAISED_XCPT
12177 || rcStrict == VINF_PGM_SYNC_CR3, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12178
12179 switch (VMX_EXIT_QUAL_CRX_REGISTER(uExitQual))
12180 {
12181 case 0:
12182 {
12183 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged,
12184 HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_CR0);
12185 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Write);
12186 Log4Func(("CR0 write rcStrict=%Rrc CR0=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cr0));
12187
12188 /*
12189 * This is a kludge for handling switches back to real mode when we try to use
12190 * V86 mode to run real mode code directly. Problem is that V86 mode cannot
12191 * deal with special selector values, so we have to return to ring-3 and run
12192 * there till the selector values are V86 mode compatible.
12193 *
12194 * Note! Using VINF_EM_RESCHEDULE_REM here rather than VINF_EM_RESCHEDULE since the
12195 * latter is an alias for VINF_IEM_RAISED_XCPT which is converted to VINF_SUCCESs
12196 * at the end of this function.
12197 */
12198 if ( rc == VINF_SUCCESS
12199 && !pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fUnrestrictedGuest
12200 && CPUMIsGuestInRealModeEx(&pVCpu->cpum.GstCtx)
12201 && (uOldCr0 & X86_CR0_PE)
12202 && !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_PE) )
12203 {
12204 /** @todo check selectors rather than returning all the time. */
12205 Log4Func(("CR0 write, back to real mode -> VINF_EM_RESCHEDULE_REM\n"));
12206 rcStrict = VINF_EM_RESCHEDULE_REM;
12207 }
12208 break;
12209 }
12210
12211 case 2:
12212 {
12213 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Write);
12214 /* Nothing to do here, CR2 it's not part of the VMCS. */
12215 break;
12216 }
12217
12218 case 3:
12219 {
12220 Assert( !pVM->hm.s.fNestedPaging
12221 || !CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx)
12222 || pVCpu->hm.s.fUsingDebugLoop);
12223 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Write);
12224 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged,
12225 HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_CR3);
12226 Log4Func(("CR3 write rcStrict=%Rrc CR3=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cr3));
12227 break;
12228 }
12229
12230 case 4:
12231 {
12232 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Write);
12233 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged,
12234 HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_CR4);
12235 Log4Func(("CR4 write rc=%Rrc CR4=%#RX64 fLoadSaveGuestXcr0=%u\n", VBOXSTRICTRC_VAL(rcStrict),
12236 pVCpu->cpum.GstCtx.cr4, pVCpu->hm.s.fLoadSaveGuestXcr0));
12237 break;
12238 }
12239
12240 case 8:
12241 {
12242 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Write);
12243 Assert(!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW));
12244 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged,
12245 HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_APIC_TPR);
12246 break;
12247 }
12248 default:
12249 AssertMsgFailed(("Invalid CRx register %#x\n", VMX_EXIT_QUAL_CRX_REGISTER(uExitQual)));
12250 break;
12251 }
12252 break;
12253 }
12254
12255 case VMX_EXIT_QUAL_CRX_ACCESS_READ: /* MOV from CRx */
12256 {
12257 Assert( !pVM->hm.s.fNestedPaging
12258 || !CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx)
12259 || pVCpu->hm.s.fUsingDebugLoop
12260 || VMX_EXIT_QUAL_CRX_REGISTER(uExitQual) != 3);
12261 /* CR8 reads only cause a VM-exit when the TPR shadow feature isn't enabled. */
12262 Assert( VMX_EXIT_QUAL_CRX_REGISTER(uExitQual) != 8
12263 || !(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW));
12264
12265 rcStrict = IEMExecDecodedMovCRxRead(pVCpu, pVmxTransient->cbInstr, VMX_EXIT_QUAL_CRX_GENREG(uExitQual),
12266 VMX_EXIT_QUAL_CRX_REGISTER(uExitQual));
12267 AssertMsg( rcStrict == VINF_SUCCESS
12268 || rcStrict == VINF_IEM_RAISED_XCPT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12269#ifdef VBOX_WITH_STATISTICS
12270 switch (VMX_EXIT_QUAL_CRX_REGISTER(uExitQual))
12271 {
12272 case 0: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Read); break;
12273 case 2: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Read); break;
12274 case 3: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Read); break;
12275 case 4: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Read); break;
12276 case 8: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Read); break;
12277 }
12278#endif
12279 Log4Func(("CR%d Read access rcStrict=%Rrc\n", VMX_EXIT_QUAL_CRX_REGISTER(uExitQual),
12280 VBOXSTRICTRC_VAL(rcStrict)));
12281 if (VMX_EXIT_QUAL_CRX_GENREG(uExitQual) == X86_GREG_xSP)
12282 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_RSP);
12283 else
12284 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
12285 break;
12286 }
12287
12288 case VMX_EXIT_QUAL_CRX_ACCESS_CLTS: /* CLTS (Clear Task-Switch Flag in CR0) */
12289 {
12290 rcStrict = IEMExecDecodedClts(pVCpu, pVmxTransient->cbInstr);
12291 AssertMsg( rcStrict == VINF_SUCCESS
12292 || rcStrict == VINF_IEM_RAISED_XCPT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12293
12294 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_CR0);
12295 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClts);
12296 Log4Func(("CLTS rcStrict=%d\n", VBOXSTRICTRC_VAL(rcStrict)));
12297 break;
12298 }
12299
12300 case VMX_EXIT_QUAL_CRX_ACCESS_LMSW: /* LMSW (Load Machine-Status Word into CR0) */
12301 {
12302 /* Note! LMSW cannot clear CR0.PE, so no fRealOnV86Active kludge needed here. */
12303 rc = hmR0VmxReadGuestLinearAddrVmcs(pVCpu, pVmxTransient);
12304 AssertRCReturn(rc, rc);
12305 rcStrict = IEMExecDecodedLmsw(pVCpu, pVmxTransient->cbInstr, VMX_EXIT_QUAL_CRX_LMSW_DATA(uExitQual),
12306 pVmxTransient->uGuestLinearAddr);
12307 AssertMsg( rcStrict == VINF_SUCCESS
12308 || rcStrict == VINF_IEM_RAISED_XCPT
12309 , ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12310
12311 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_CR0);
12312 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitLmsw);
12313 Log4Func(("LMSW rcStrict=%d\n", VBOXSTRICTRC_VAL(rcStrict)));
12314 break;
12315 }
12316
12317 default:
12318 AssertMsgFailedReturn(("Invalid access-type in Mov CRx VM-exit qualification %#x\n", uAccessType),
12319 VERR_VMX_UNEXPECTED_EXCEPTION);
12320 }
12321
12322 Assert( (pVCpu->hm.s.fCtxChanged & (HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS))
12323 == (HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS));
12324 if (rcStrict == VINF_IEM_RAISED_XCPT)
12325 {
12326 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
12327 rcStrict = VINF_SUCCESS;
12328 }
12329
12330 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitMovCRx, y2);
12331 NOREF(pVM);
12332 return rcStrict;
12333}
12334
12335
12336/**
12337 * VM-exit handler for I/O instructions (VMX_EXIT_IO_INSTR). Conditional
12338 * VM-exit.
12339 */
12340HMVMX_EXIT_DECL hmR0VmxExitIoInstr(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12341{
12342 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12343 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitIO, y1);
12344
12345 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
12346 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12347 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
12348 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK | CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_EFER);
12349 /* EFER also required for longmode checks in EMInterpretDisasCurrent(), but it's always up-to-date. */
12350 AssertRCReturn(rc, rc);
12351
12352 /* Refer Intel spec. 27-5. "Exit Qualifications for I/O Instructions" for the format. */
12353 uint32_t uIOPort = VMX_EXIT_QUAL_IO_PORT(pVmxTransient->uExitQual);
12354 uint8_t uIOWidth = VMX_EXIT_QUAL_IO_WIDTH(pVmxTransient->uExitQual);
12355 bool fIOWrite = (VMX_EXIT_QUAL_IO_DIRECTION(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_IO_DIRECTION_OUT);
12356 bool fIOString = VMX_EXIT_QUAL_IO_IS_STRING(pVmxTransient->uExitQual);
12357 bool fGstStepping = RT_BOOL(pCtx->eflags.Bits.u1TF);
12358 bool fDbgStepping = pVCpu->hm.s.fSingleInstruction;
12359 AssertReturn(uIOWidth <= 3 && uIOWidth != 2, VERR_VMX_IPE_1);
12360
12361 /*
12362 * Update exit history to see if this exit can be optimized.
12363 */
12364 VBOXSTRICTRC rcStrict;
12365 PCEMEXITREC pExitRec = NULL;
12366 if ( !fGstStepping
12367 && !fDbgStepping)
12368 pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
12369 !fIOString
12370 ? !fIOWrite
12371 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_IO_PORT_READ)
12372 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_IO_PORT_WRITE)
12373 : !fIOWrite
12374 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_READ)
12375 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_WRITE),
12376 pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
12377 if (!pExitRec)
12378 {
12379 /* I/O operation lookup arrays. */
12380 static uint32_t const s_aIOSizes[4] = { 1, 2, 0, 4 }; /* Size of the I/O accesses. */
12381 static uint32_t const s_aIOOpAnd[4] = { 0xff, 0xffff, 0, 0xffffffff }; /* AND masks for saving result in AL/AX/EAX. */
12382 uint32_t const cbValue = s_aIOSizes[uIOWidth];
12383 uint32_t const cbInstr = pVmxTransient->cbInstr;
12384 bool fUpdateRipAlready = false; /* ugly hack, should be temporary. */
12385 PVM pVM = pVCpu->CTX_SUFF(pVM);
12386 if (fIOString)
12387 {
12388 /*
12389 * INS/OUTS - I/O String instruction.
12390 *
12391 * Use instruction-information if available, otherwise fall back on
12392 * interpreting the instruction.
12393 */
12394 Log4Func(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, uIOPort, cbValue, fIOWrite ? 'w' : 'r'));
12395 AssertReturn(pCtx->dx == uIOPort, VERR_VMX_IPE_2);
12396 bool const fInsOutsInfo = RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
12397 if (fInsOutsInfo)
12398 {
12399 int rc2 = hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
12400 AssertRCReturn(rc2, rc2);
12401 AssertReturn(pVmxTransient->ExitInstrInfo.StrIo.u3AddrSize <= 2, VERR_VMX_IPE_3);
12402 AssertCompile(IEMMODE_16BIT == 0 && IEMMODE_32BIT == 1 && IEMMODE_64BIT == 2);
12403 IEMMODE const enmAddrMode = (IEMMODE)pVmxTransient->ExitInstrInfo.StrIo.u3AddrSize;
12404 bool const fRep = VMX_EXIT_QUAL_IO_IS_REP(pVmxTransient->uExitQual);
12405 if (fIOWrite)
12406 rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, fRep, cbInstr,
12407 pVmxTransient->ExitInstrInfo.StrIo.iSegReg, true /*fIoChecked*/);
12408 else
12409 {
12410 /*
12411 * The segment prefix for INS cannot be overridden and is always ES. We can safely assume X86_SREG_ES.
12412 * Hence "iSegReg" field is undefined in the instruction-information field in VT-x for INS.
12413 * See Intel Instruction spec. for "INS".
12414 * See Intel spec. Table 27-8 "Format of the VM-Exit Instruction-Information Field as Used for INS and OUTS".
12415 */
12416 rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, fRep, cbInstr, true /*fIoChecked*/);
12417 }
12418 }
12419 else
12420 rcStrict = IEMExecOne(pVCpu);
12421
12422 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP);
12423 fUpdateRipAlready = true;
12424 }
12425 else
12426 {
12427 /*
12428 * IN/OUT - I/O instruction.
12429 */
12430 Log4Func(("CS:RIP=%04x:%08RX64 %#06x/%u %c\n", pCtx->cs.Sel, pCtx->rip, uIOPort, cbValue, fIOWrite ? 'w' : 'r'));
12431 uint32_t const uAndVal = s_aIOOpAnd[uIOWidth];
12432 Assert(!VMX_EXIT_QUAL_IO_IS_REP(pVmxTransient->uExitQual));
12433 if (fIOWrite)
12434 {
12435 rcStrict = IOMIOPortWrite(pVM, pVCpu, uIOPort, pCtx->eax & uAndVal, cbValue);
12436 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
12437 if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
12438 && !pCtx->eflags.Bits.u1TF)
12439 rcStrict = EMRZSetPendingIoPortWrite(pVCpu, uIOPort, cbInstr, cbValue, pCtx->eax & uAndVal);
12440 }
12441 else
12442 {
12443 uint32_t u32Result = 0;
12444 rcStrict = IOMIOPortRead(pVM, pVCpu, uIOPort, &u32Result, cbValue);
12445 if (IOM_SUCCESS(rcStrict))
12446 {
12447 /* Save result of I/O IN instr. in AL/AX/EAX. */
12448 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Result & uAndVal);
12449 }
12450 if ( rcStrict == VINF_IOM_R3_IOPORT_READ
12451 && !pCtx->eflags.Bits.u1TF)
12452 rcStrict = EMRZSetPendingIoPortRead(pVCpu, uIOPort, cbInstr, cbValue);
12453 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
12454 }
12455 }
12456
12457 if (IOM_SUCCESS(rcStrict))
12458 {
12459 if (!fUpdateRipAlready)
12460 {
12461 hmR0VmxAdvanceGuestRipBy(pVCpu, cbInstr);
12462 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP);
12463 }
12464
12465 /*
12466 * INS/OUTS with REP prefix updates RFLAGS, can be observed with triple-fault guru
12467 * while booting Fedora 17 64-bit guest.
12468 *
12469 * See Intel Instruction reference for REP/REPE/REPZ/REPNE/REPNZ.
12470 */
12471 if (fIOString)
12472 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RFLAGS);
12473
12474 /*
12475 * If any I/O breakpoints are armed, we need to check if one triggered
12476 * and take appropriate action.
12477 * Note that the I/O breakpoint type is undefined if CR4.DE is 0.
12478 */
12479 rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_DR7);
12480 AssertRCReturn(rc, rc);
12481
12482 /** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
12483 * execution engines about whether hyper BPs and such are pending. */
12484 uint32_t const uDr7 = pCtx->dr[7];
12485 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
12486 && X86_DR7_ANY_RW_IO(uDr7)
12487 && (pCtx->cr4 & X86_CR4_DE))
12488 || DBGFBpIsHwIoArmed(pVM)))
12489 {
12490 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
12491
12492 /* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
12493 VMMRZCallRing3Disable(pVCpu);
12494 HM_DISABLE_PREEMPT(pVCpu);
12495
12496 bool fIsGuestDbgActive = CPUMR0DebugStateMaybeSaveGuest(pVCpu, true /* fDr6 */);
12497
12498 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, uIOPort, cbValue);
12499 if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
12500 {
12501 /* Raise #DB. */
12502 if (fIsGuestDbgActive)
12503 ASMSetDR6(pCtx->dr[6]);
12504 if (pCtx->dr[7] != uDr7)
12505 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_GUEST_DR7;
12506
12507 hmR0VmxSetPendingXcptDB(pVCpu);
12508 }
12509 /* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
12510 however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
12511 else if ( rcStrict2 != VINF_SUCCESS
12512 && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
12513 rcStrict = rcStrict2;
12514 AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
12515
12516 HM_RESTORE_PREEMPT();
12517 VMMRZCallRing3Enable(pVCpu);
12518 }
12519 }
12520
12521#ifdef VBOX_STRICT
12522 if ( rcStrict == VINF_IOM_R3_IOPORT_READ
12523 || rcStrict == VINF_EM_PENDING_R3_IOPORT_READ)
12524 Assert(!fIOWrite);
12525 else if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
12526 || rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE
12527 || rcStrict == VINF_EM_PENDING_R3_IOPORT_WRITE)
12528 Assert(fIOWrite);
12529 else
12530 {
12531# if 0 /** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
12532 * statuses, that the VMM device and some others may return. See
12533 * IOM_SUCCESS() for guidance. */
12534 AssertMsg( RT_FAILURE(rcStrict)
12535 || rcStrict == VINF_SUCCESS
12536 || rcStrict == VINF_EM_RAW_EMULATE_INSTR
12537 || rcStrict == VINF_EM_DBG_BREAKPOINT
12538 || rcStrict == VINF_EM_RAW_GUEST_TRAP
12539 || rcStrict == VINF_EM_RAW_TO_R3
12540 || rcStrict == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12541# endif
12542 }
12543#endif
12544 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitIO, y1);
12545 }
12546 else
12547 {
12548 /*
12549 * Frequent exit or something needing probing. Get state and call EMHistoryExec.
12550 */
12551 int rc2 = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
12552 AssertRCReturn(rc2, rc2);
12553 STAM_COUNTER_INC(!fIOString ? fIOWrite ? &pVCpu->hm.s.StatExitIOWrite : &pVCpu->hm.s.StatExitIORead
12554 : fIOWrite ? &pVCpu->hm.s.StatExitIOStringWrite : &pVCpu->hm.s.StatExitIOStringRead);
12555 Log4(("IOExit/%u: %04x:%08RX64: %s%s%s %#x LB %u -> EMHistoryExec\n",
12556 pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
12557 VMX_EXIT_QUAL_IO_IS_REP(pVmxTransient->uExitQual) ? "REP " : "",
12558 fIOWrite ? "OUT" : "IN", fIOString ? "S" : "", uIOPort, uIOWidth));
12559
12560 rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
12561 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
12562
12563 Log4(("IOExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
12564 pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
12565 VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
12566 }
12567 return rcStrict;
12568}
12569
12570
12571/**
12572 * VM-exit handler for task switches (VMX_EXIT_TASK_SWITCH). Unconditional
12573 * VM-exit.
12574 */
12575HMVMX_EXIT_DECL hmR0VmxExitTaskSwitch(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12576{
12577 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12578
12579 /* Check if this task-switch occurred while delivery an event through the guest IDT. */
12580 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12581 AssertRCReturn(rc, rc);
12582 if (VMX_EXIT_QUAL_TASK_SWITCH_TYPE(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT)
12583 {
12584 rc = hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient);
12585 AssertRCReturn(rc, rc);
12586 if (VMX_IDT_VECTORING_INFO_IS_VALID(pVmxTransient->uIdtVectoringInfo))
12587 {
12588 uint32_t uErrCode;
12589 RTGCUINTPTR GCPtrFaultAddress;
12590 uint32_t const uIntType = VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uIdtVectoringInfo);
12591 uint32_t const uVector = VMX_IDT_VECTORING_INFO_VECTOR(pVmxTransient->uIdtVectoringInfo);
12592 bool const fErrorCodeValid = VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(pVmxTransient->uIdtVectoringInfo);
12593 if (fErrorCodeValid)
12594 {
12595 rc = hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
12596 AssertRCReturn(rc, rc);
12597 uErrCode = pVmxTransient->uIdtVectoringErrorCode;
12598 }
12599 else
12600 uErrCode = 0;
12601
12602 if ( uIntType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
12603 && uVector == X86_XCPT_PF)
12604 GCPtrFaultAddress = pVCpu->cpum.GstCtx.cr2;
12605 else
12606 GCPtrFaultAddress = 0;
12607
12608 rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
12609 AssertRCReturn(rc, rc);
12610
12611 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(pVmxTransient->uIdtVectoringInfo),
12612 pVmxTransient->cbInstr, uErrCode, GCPtrFaultAddress);
12613
12614 Log4Func(("Pending event. uIntType=%#x uVector=%#x\n", uIntType, uVector));
12615 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
12616 return VINF_EM_RAW_INJECT_TRPM_EVENT;
12617 }
12618 }
12619
12620 /* Fall back to the interpreter to emulate the task-switch. */
12621 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
12622 return VERR_EM_INTERPRETER;
12623}
12624
12625
12626/**
12627 * VM-exit handler for monitor-trap-flag (VMX_EXIT_MTF). Conditional VM-exit.
12628 */
12629HMVMX_EXIT_DECL hmR0VmxExitMtf(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12630{
12631 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12632 Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
12633 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_PROC_CTLS_MONITOR_TRAP_FLAG;
12634 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
12635 AssertRCReturn(rc, rc);
12636 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMtf);
12637 return VINF_EM_DBG_STEPPED;
12638}
12639
12640
12641/**
12642 * VM-exit handler for APIC access (VMX_EXIT_APIC_ACCESS). Conditional VM-exit.
12643 */
12644HMVMX_EXIT_DECL hmR0VmxExitApicAccess(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12645{
12646 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12647
12648 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitApicAccess);
12649
12650 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
12651 VBOXSTRICTRC rcStrict1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pVmxTransient);
12652 if (RT_LIKELY(rcStrict1 == VINF_SUCCESS))
12653 {
12654 /* For some crazy guest, if an event delivery causes an APIC-access VM-exit, go to instruction emulation. */
12655 if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
12656 {
12657 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
12658 return VINF_EM_RAW_INJECT_TRPM_EVENT;
12659 }
12660 }
12661 else
12662 {
12663 if (rcStrict1 == VINF_HM_DOUBLE_FAULT)
12664 rcStrict1 = VINF_SUCCESS;
12665 return rcStrict1;
12666 }
12667
12668 /* IOMMIOPhysHandler() below may call into IEM, save the necessary state. */
12669 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
12670 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12671 AssertRCReturn(rc, rc);
12672
12673 /* See Intel spec. 27-6 "Exit Qualifications for APIC-access VM-exits from Linear Accesses & Guest-Phyiscal Addresses" */
12674 uint32_t uAccessType = VMX_EXIT_QUAL_APIC_ACCESS_TYPE(pVmxTransient->uExitQual);
12675 VBOXSTRICTRC rcStrict2;
12676 switch (uAccessType)
12677 {
12678 case VMX_APIC_ACCESS_TYPE_LINEAR_WRITE:
12679 case VMX_APIC_ACCESS_TYPE_LINEAR_READ:
12680 {
12681 AssertMsg( !(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
12682 || VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(pVmxTransient->uExitQual) != XAPIC_OFF_TPR,
12683 ("hmR0VmxExitApicAccess: can't access TPR offset while using TPR shadowing.\n"));
12684
12685 RTGCPHYS GCPhys = pVCpu->hm.s.vmx.u64MsrApicBase; /* Always up-to-date, u64MsrApicBase is not part of the VMCS. */
12686 GCPhys &= PAGE_BASE_GC_MASK;
12687 GCPhys += VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(pVmxTransient->uExitQual);
12688 PVM pVM = pVCpu->CTX_SUFF(pVM);
12689 Log4Func(("Linear access uAccessType=%#x GCPhys=%#RGp Off=%#x\n", uAccessType, GCPhys,
12690 VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(pVmxTransient->uExitQual)));
12691
12692 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
12693 rcStrict2 = IOMMMIOPhysHandler(pVM, pVCpu,
12694 uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ ? 0 : X86_TRAP_PF_RW,
12695 CPUMCTX2CORE(pCtx), GCPhys);
12696 Log4Func(("IOMMMIOPhysHandler returned %Rrc\n", VBOXSTRICTRC_VAL(rcStrict2)));
12697 if ( rcStrict2 == VINF_SUCCESS
12698 || rcStrict2 == VERR_PAGE_TABLE_NOT_PRESENT
12699 || rcStrict2 == VERR_PAGE_NOT_PRESENT)
12700 {
12701 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS
12702 | HM_CHANGED_GUEST_APIC_TPR);
12703 rcStrict2 = VINF_SUCCESS;
12704 }
12705 break;
12706 }
12707
12708 default:
12709 Log4Func(("uAccessType=%#x\n", uAccessType));
12710 rcStrict2 = VINF_EM_RAW_EMULATE_INSTR;
12711 break;
12712 }
12713
12714 if (rcStrict2 != VINF_SUCCESS)
12715 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchApicAccessToR3);
12716 return rcStrict2;
12717}
12718
12719
12720/**
12721 * VM-exit handler for debug-register accesses (VMX_EXIT_MOV_DRX). Conditional
12722 * VM-exit.
12723 */
12724HMVMX_EXIT_DECL hmR0VmxExitMovDRx(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12725{
12726 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12727
12728 /* We should -not- get this VM-exit if the guest's debug registers were active. */
12729 if (pVmxTransient->fWasGuestDebugStateActive)
12730 {
12731 AssertMsgFailed(("Unexpected MOV DRx exit\n"));
12732 HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
12733 }
12734
12735 if ( !pVCpu->hm.s.fSingleInstruction
12736 && !pVmxTransient->fWasHyperDebugStateActive)
12737 {
12738 Assert(!DBGFIsStepping(pVCpu));
12739 Assert(pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT_32(X86_XCPT_DB));
12740
12741 /* Don't intercept MOV DRx any more. */
12742 pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_PROC_CTLS_MOV_DR_EXIT;
12743 int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
12744 AssertRCReturn(rc, rc);
12745
12746 /* We're playing with the host CPU state here, make sure we can't preempt or longjmp. */
12747 VMMRZCallRing3Disable(pVCpu);
12748 HM_DISABLE_PREEMPT(pVCpu);
12749
12750 /* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
12751 CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
12752 Assert(CPUMIsGuestDebugStateActive(pVCpu) || HC_ARCH_BITS == 32);
12753
12754 HM_RESTORE_PREEMPT();
12755 VMMRZCallRing3Enable(pVCpu);
12756
12757#ifdef VBOX_WITH_STATISTICS
12758 rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12759 AssertRCReturn(rc, rc);
12760 if (VMX_EXIT_QUAL_DRX_DIRECTION(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_DRX_DIRECTION_WRITE)
12761 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
12762 else
12763 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
12764#endif
12765 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
12766 return VINF_SUCCESS;
12767 }
12768
12769 /*
12770 * EMInterpretDRx[Write|Read]() calls CPUMIsGuestIn64BitCode() which requires EFER, CS. EFER is always up-to-date.
12771 * Update the segment registers and DR7 from the CPU.
12772 */
12773 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
12774 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12775 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_DR7);
12776 AssertRCReturn(rc, rc);
12777 Log4Func(("CS:RIP=%04x:%08RX64\n", pCtx->cs.Sel, pCtx->rip));
12778
12779 PVM pVM = pVCpu->CTX_SUFF(pVM);
12780 if (VMX_EXIT_QUAL_DRX_DIRECTION(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_DRX_DIRECTION_WRITE)
12781 {
12782 rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
12783 VMX_EXIT_QUAL_DRX_REGISTER(pVmxTransient->uExitQual),
12784 VMX_EXIT_QUAL_DRX_GENREG(pVmxTransient->uExitQual));
12785 if (RT_SUCCESS(rc))
12786 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_DR7);
12787 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
12788 }
12789 else
12790 {
12791 rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
12792 VMX_EXIT_QUAL_DRX_GENREG(pVmxTransient->uExitQual),
12793 VMX_EXIT_QUAL_DRX_REGISTER(pVmxTransient->uExitQual));
12794 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
12795 }
12796
12797 Assert(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER);
12798 if (RT_SUCCESS(rc))
12799 {
12800 int rc2 = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
12801 AssertRCReturn(rc2, rc2);
12802 return VINF_SUCCESS;
12803 }
12804 return rc;
12805}
12806
12807
12808/**
12809 * VM-exit handler for EPT misconfiguration (VMX_EXIT_EPT_MISCONFIG).
12810 * Conditional VM-exit.
12811 */
12812HMVMX_EXIT_DECL hmR0VmxExitEptMisconfig(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12813{
12814 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12815 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
12816
12817 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
12818 VBOXSTRICTRC rcStrict1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pVmxTransient);
12819 if (RT_LIKELY(rcStrict1 == VINF_SUCCESS))
12820 {
12821 /* If event delivery causes an EPT misconfig (MMIO), go back to instruction emulation as otherwise
12822 injecting the original pending event would most likely cause the same EPT misconfig VM-exit. */
12823 if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
12824 {
12825 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
12826 return VINF_EM_RAW_INJECT_TRPM_EVENT;
12827 }
12828 }
12829 else
12830 {
12831 if (rcStrict1 == VINF_HM_DOUBLE_FAULT)
12832 rcStrict1 = VINF_SUCCESS;
12833 return rcStrict1;
12834 }
12835
12836 /*
12837 * Get sufficent state and update the exit history entry.
12838 */
12839 RTGCPHYS GCPhys;
12840 int rc = VMXReadVmcs64(VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL, &GCPhys);
12841 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
12842 AssertRCReturn(rc, rc);
12843
12844 VBOXSTRICTRC rcStrict;
12845 PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
12846 EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM | EMEXIT_F_HM, EMEXITTYPE_MMIO),
12847 pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
12848 if (!pExitRec)
12849 {
12850 /*
12851 * If we succeed, resume guest execution.
12852 * If we fail in interpreting the instruction because we couldn't get the guest physical address
12853 * of the page containing the instruction via the guest's page tables (we would invalidate the guest page
12854 * in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
12855 * weird case. See @bugref{6043}.
12856 */
12857 PVM pVM = pVCpu->CTX_SUFF(pVM);
12858 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
12859 rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, PGMMODE_EPT, CPUMCTX2CORE(pCtx), GCPhys, UINT32_MAX);
12860 Log4Func(("At %#RGp RIP=%#RX64 rc=%Rrc\n", GCPhys, pCtx->rip, VBOXSTRICTRC_VAL(rcStrict)));
12861 if ( rcStrict == VINF_SUCCESS
12862 || rcStrict == VERR_PAGE_TABLE_NOT_PRESENT
12863 || rcStrict == VERR_PAGE_NOT_PRESENT)
12864 {
12865 /* Successfully handled MMIO operation. */
12866 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS
12867 | HM_CHANGED_GUEST_APIC_TPR);
12868 rcStrict = VINF_SUCCESS;
12869 }
12870 }
12871 else
12872 {
12873 /*
12874 * Frequent exit or something needing probing. Get state and call EMHistoryExec.
12875 */
12876 int rc2 = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
12877 AssertRCReturn(rc2, rc2);
12878
12879 Log4(("EptMisscfgExit/%u: %04x:%08RX64: %RGp -> EMHistoryExec\n",
12880 pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPhys));
12881
12882 rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
12883 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
12884
12885 Log4(("EptMisscfgExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
12886 pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
12887 VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
12888 }
12889 return VBOXSTRICTRC_TODO(rcStrict);
12890}
12891
12892
12893/**
12894 * VM-exit handler for EPT violation (VMX_EXIT_EPT_VIOLATION). Conditional
12895 * VM-exit.
12896 */
12897HMVMX_EXIT_DECL hmR0VmxExitEptViolation(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12898{
12899 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12900 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
12901
12902 /* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
12903 VBOXSTRICTRC rcStrict1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pVmxTransient);
12904 if (RT_LIKELY(rcStrict1 == VINF_SUCCESS))
12905 {
12906 /* In the unlikely case that the EPT violation happened as a result of delivering an event, log it. */
12907 if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
12908 Log4Func(("EPT violation with an event pending u64IntInfo=%#RX64\n", pVCpu->hm.s.Event.u64IntInfo));
12909 }
12910 else
12911 {
12912 if (rcStrict1 == VINF_HM_DOUBLE_FAULT)
12913 rcStrict1 = VINF_SUCCESS;
12914 return rcStrict1;
12915 }
12916
12917 RTGCPHYS GCPhys;
12918 int rc = VMXReadVmcs64(VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL, &GCPhys);
12919 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
12920 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
12921 AssertRCReturn(rc, rc);
12922
12923 /* Intel spec. Table 27-7 "Exit Qualifications for EPT violations". */
12924 AssertMsg(((pVmxTransient->uExitQual >> 7) & 3) != 2, ("%#RX64", pVmxTransient->uExitQual));
12925
12926 RTGCUINT uErrorCode = 0;
12927 if (pVmxTransient->uExitQual & VMX_EXIT_QUAL_EPT_INSTR_FETCH)
12928 uErrorCode |= X86_TRAP_PF_ID;
12929 if (pVmxTransient->uExitQual & VMX_EXIT_QUAL_EPT_DATA_WRITE)
12930 uErrorCode |= X86_TRAP_PF_RW;
12931 if (pVmxTransient->uExitQual & VMX_EXIT_QUAL_EPT_ENTRY_PRESENT)
12932 uErrorCode |= X86_TRAP_PF_P;
12933
12934 TRPMAssertXcptPF(pVCpu, GCPhys, uErrorCode);
12935
12936
12937 /* Handle the pagefault trap for the nested shadow table. */
12938 PVM pVM = pVCpu->CTX_SUFF(pVM);
12939 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
12940
12941 Log4Func(("EPT violation %#x at %#RX64 ErrorCode %#x CS:RIP=%04x:%08RX64\n", pVmxTransient->uExitQual, GCPhys, uErrorCode,
12942 pCtx->cs.Sel, pCtx->rip));
12943
12944 VBOXSTRICTRC rcStrict2 = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, uErrorCode, CPUMCTX2CORE(pCtx), GCPhys);
12945 TRPMResetTrap(pVCpu);
12946
12947 /* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}. */
12948 if ( rcStrict2 == VINF_SUCCESS
12949 || rcStrict2 == VERR_PAGE_TABLE_NOT_PRESENT
12950 || rcStrict2 == VERR_PAGE_NOT_PRESENT)
12951 {
12952 /* Successfully synced our nested page tables. */
12953 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf);
12954 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS);
12955 return VINF_SUCCESS;
12956 }
12957
12958 Log4Func(("EPT return to ring-3 rcStrict2=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict2)));
12959 return rcStrict2;
12960}
12961
12962/** @} */
12963
12964/** @name VM-exit exception handlers.
12965 * @{
12966 */
12967/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
12968/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= VM-exit exception handlers =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
12969/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
12970
12971/**
12972 * VM-exit exception handler for \#MF (Math Fault: floating point exception).
12973 */
12974static int hmR0VmxExitXcptMF(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
12975{
12976 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
12977 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
12978
12979 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR0);
12980 AssertRCReturn(rc, rc);
12981
12982 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_NE))
12983 {
12984 /* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
12985 rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
12986
12987 /** @todo r=ramshankar: The Intel spec. does -not- specify that this VM-exit
12988 * provides VM-exit instruction length. If this causes problem later,
12989 * disassemble the instruction like it's done on AMD-V. */
12990 int rc2 = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
12991 AssertRCReturn(rc2, rc2);
12992 return rc;
12993 }
12994
12995 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), pVmxTransient->cbInstr,
12996 pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
12997 return rc;
12998}
12999
13000
13001/**
13002 * VM-exit exception handler for \#BP (Breakpoint exception).
13003 */
13004static int hmR0VmxExitXcptBP(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13005{
13006 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13007 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
13008
13009 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
13010 AssertRCReturn(rc, rc);
13011
13012 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
13013 rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
13014 if (rc == VINF_EM_RAW_GUEST_TRAP)
13015 {
13016 rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13017 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13018 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13019 AssertRCReturn(rc, rc);
13020
13021 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), pVmxTransient->cbInstr,
13022 pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13023 }
13024
13025 Assert(rc == VINF_SUCCESS || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_EM_DBG_BREAKPOINT);
13026 return rc;
13027}
13028
13029
13030/**
13031 * VM-exit exception handler for \#AC (alignment check exception).
13032 */
13033static int hmR0VmxExitXcptAC(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13034{
13035 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13036
13037 /*
13038 * Re-inject it. We'll detect any nesting before getting here.
13039 */
13040 int rc = hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13041 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13042 AssertRCReturn(rc, rc);
13043 Assert(ASMAtomicUoReadU32(&pVmxTransient->fVmcsFieldsRead) & HMVMX_READ_EXIT_INTERRUPTION_INFO);
13044
13045 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), pVmxTransient->cbInstr,
13046 pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13047 return VINF_SUCCESS;
13048}
13049
13050
13051/**
13052 * VM-exit exception handler for \#DB (Debug exception).
13053 */
13054static int hmR0VmxExitXcptDB(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13055{
13056 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13057 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
13058
13059 /*
13060 * Get the DR6-like values from the VM-exit qualification and pass it to DBGF
13061 * for processing.
13062 */
13063 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
13064
13065 /* Refer Intel spec. Table 27-1. "Exit Qualifications for debug exceptions" for the format. */
13066 uint64_t uDR6 = X86_DR6_INIT_VAL;
13067 uDR6 |= (pVmxTransient->uExitQual & (X86_DR6_B0 | X86_DR6_B1 | X86_DR6_B2 | X86_DR6_B3 | X86_DR6_BD | X86_DR6_BS));
13068
13069 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
13070 rc = DBGFRZTrap01Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), uDR6, pVCpu->hm.s.fSingleInstruction);
13071 Log6Func(("rc=%Rrc\n", rc));
13072 if (rc == VINF_EM_RAW_GUEST_TRAP)
13073 {
13074 /*
13075 * The exception was for the guest. Update DR6, DR7.GD and
13076 * IA32_DEBUGCTL.LBR before forwarding it.
13077 * (See Intel spec. 27.1 "Architectural State before a VM-Exit".)
13078 */
13079 VMMRZCallRing3Disable(pVCpu);
13080 HM_DISABLE_PREEMPT(pVCpu);
13081
13082 pCtx->dr[6] &= ~X86_DR6_B_MASK;
13083 pCtx->dr[6] |= uDR6;
13084 if (CPUMIsGuestDebugStateActive(pVCpu))
13085 ASMSetDR6(pCtx->dr[6]);
13086
13087 HM_RESTORE_PREEMPT();
13088 VMMRZCallRing3Enable(pVCpu);
13089
13090 rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_DR7);
13091 AssertRCReturn(rc, rc);
13092
13093 /* X86_DR7_GD will be cleared if DRx accesses should be trapped inside the guest. */
13094 pCtx->dr[7] &= ~X86_DR7_GD;
13095
13096 /* Paranoia. */
13097 pCtx->dr[7] &= ~X86_DR7_RAZ_MASK;
13098 pCtx->dr[7] |= X86_DR7_RA1_MASK;
13099
13100 rc = VMXWriteVmcs32(VMX_VMCS_GUEST_DR7, (uint32_t)pCtx->dr[7]);
13101 AssertRCReturn(rc, rc);
13102
13103 /*
13104 * Raise #DB in the guest.
13105 *
13106 * It is important to reflect exactly what the VM-exit gave us (preserving the
13107 * interruption-type) rather than use hmR0VmxSetPendingXcptDB() as the #DB could've
13108 * been raised while executing ICEBP (INT1) and not the regular #DB. Thus it may
13109 * trigger different handling in the CPU (like skipping DPL checks), see @bugref{6398}.
13110 *
13111 * Intel re-documented ICEBP/INT1 on May 2018 previously documented as part of
13112 * Intel 386, see Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
13113 */
13114 rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13115 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13116 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13117 AssertRCReturn(rc, rc);
13118 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), pVmxTransient->cbInstr,
13119 pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13120 return VINF_SUCCESS;
13121 }
13122
13123 /*
13124 * Not a guest trap, must be a hypervisor related debug event then.
13125 * Update DR6 in case someone is interested in it.
13126 */
13127 AssertMsg(rc == VINF_EM_DBG_STEPPED || rc == VINF_EM_DBG_BREAKPOINT, ("%Rrc\n", rc));
13128 AssertReturn(pVmxTransient->fWasHyperDebugStateActive, VERR_HM_IPE_5);
13129 CPUMSetHyperDR6(pVCpu, uDR6);
13130
13131 return rc;
13132}
13133
13134
13135/**
13136 * Hacks its way around the lovely mesa driver's backdoor accesses.
13137 *
13138 * @sa hmR0SvmHandleMesaDrvGp
13139 */
13140static int hmR0VmxHandleMesaDrvGp(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, PCPUMCTX pCtx)
13141{
13142 Log(("hmR0VmxHandleMesaDrvGp: at %04x:%08RX64 rcx=%RX64 rbx=%RX64\n", pCtx->cs.Sel, pCtx->rip, pCtx->rcx, pCtx->rbx));
13143 RT_NOREF(pCtx);
13144
13145 /* For now we'll just skip the instruction. */
13146 return hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
13147}
13148
13149
13150/**
13151 * Checks if the \#GP'ing instruction is the mesa driver doing it's lovely
13152 * backdoor logging w/o checking what it is running inside.
13153 *
13154 * This recognizes an "IN EAX,DX" instruction executed in flat ring-3, with the
13155 * backdoor port and magic numbers loaded in registers.
13156 *
13157 * @returns true if it is, false if it isn't.
13158 * @sa hmR0SvmIsMesaDrvGp
13159 */
13160DECLINLINE(bool) hmR0VmxIsMesaDrvGp(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient, PCPUMCTX pCtx)
13161{
13162 /* 0xed: IN eAX,dx */
13163 uint8_t abInstr[1];
13164 if (pVmxTransient->cbInstr != sizeof(abInstr))
13165 return false;
13166
13167 /* Check that it is #GP(0). */
13168 if (pVmxTransient->uExitIntErrorCode != 0)
13169 return false;
13170
13171 /* Check magic and port. */
13172 Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX | CPUMCTX_EXTRN_RCX)));
13173 /*Log(("hmR0VmxIsMesaDrvGp: rax=%RX64 rdx=%RX64\n", pCtx->rax, pCtx->rdx));*/
13174 if (pCtx->rax != UINT32_C(0x564d5868))
13175 return false;
13176 if (pCtx->dx != UINT32_C(0x5658))
13177 return false;
13178
13179 /* Flat ring-3 CS. */
13180 AssertCompile(HMVMX_CPUMCTX_EXTRN_ALL & CPUMCTX_EXTRN_CS);
13181 Assert(!(pCtx->fExtrn & CPUMCTX_EXTRN_CS));
13182 /*Log(("hmR0VmxIsMesaDrvGp: cs.Attr.n.u2Dpl=%d base=%Rx64\n", pCtx->cs.Attr.n.u2Dpl, pCtx->cs.u64Base));*/
13183 if (pCtx->cs.Attr.n.u2Dpl != 3)
13184 return false;
13185 if (pCtx->cs.u64Base != 0)
13186 return false;
13187
13188 /* Check opcode. */
13189 AssertCompile(HMVMX_CPUMCTX_EXTRN_ALL & CPUMCTX_EXTRN_RIP);
13190 Assert(!(pCtx->fExtrn & CPUMCTX_EXTRN_RIP));
13191 int rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pCtx->rip, sizeof(abInstr));
13192 /*Log(("hmR0VmxIsMesaDrvGp: PGMPhysSimpleReadGCPtr -> %Rrc %#x\n", rc, abInstr[0]));*/
13193 if (RT_FAILURE(rc))
13194 return false;
13195 if (abInstr[0] != 0xed)
13196 return false;
13197
13198 return true;
13199}
13200
13201
13202/**
13203 * VM-exit exception handler for \#GP (General-protection exception).
13204 *
13205 * @remarks Requires pVmxTransient->uExitIntInfo to be up-to-date.
13206 */
13207static int hmR0VmxExitXcptGP(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13208{
13209 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13210 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
13211
13212 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
13213 if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
13214 { /* likely */ }
13215 else
13216 {
13217#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
13218 Assert(pVCpu->hm.s.fUsingDebugLoop || pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv);
13219#endif
13220 /* If the guest is not in real-mode or we have unrestricted execution support, reflect #GP to the guest. */
13221 int rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13222 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13223 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13224 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
13225 AssertRCReturn(rc, rc);
13226 Log4Func(("Gst: CS:RIP %04x:%08RX64 ErrorCode=%#x CR0=%#RX64 CPL=%u TR=%#04x\n", pCtx->cs.Sel, pCtx->rip,
13227 pVmxTransient->uExitIntErrorCode, pCtx->cr0, CPUMGetGuestCPL(pVCpu), pCtx->tr.Sel));
13228
13229 if ( !pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv
13230 || !hmR0VmxIsMesaDrvGp(pVCpu, pVmxTransient, pCtx))
13231 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), pVmxTransient->cbInstr,
13232 pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13233 else
13234 rc = hmR0VmxHandleMesaDrvGp(pVCpu, pVmxTransient, pCtx);
13235 return rc;
13236 }
13237
13238 Assert(CPUMIsGuestInRealModeEx(pCtx));
13239 Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fUnrestrictedGuest);
13240
13241 int rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
13242 AssertRCReturn(rc, rc);
13243
13244 VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
13245 if (rcStrict == VINF_SUCCESS)
13246 {
13247 if (!CPUMIsGuestInRealModeEx(pCtx))
13248 {
13249 /*
13250 * The guest is no longer in real-mode, check if we can continue executing the
13251 * guest using hardware-assisted VMX. Otherwise, fall back to emulation.
13252 */
13253 if (HMVmxCanExecuteGuest(pVCpu, pCtx))
13254 {
13255 Log4Func(("Mode changed but guest still suitable for executing using VT-x\n"));
13256 pVCpu->hm.s.vmx.RealMode.fRealOnV86Active = false;
13257 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
13258 }
13259 else
13260 {
13261 Log4Func(("Mode changed -> VINF_EM_RESCHEDULE\n"));
13262 rcStrict = VINF_EM_RESCHEDULE;
13263 }
13264 }
13265 else
13266 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
13267 }
13268 else if (rcStrict == VINF_IEM_RAISED_XCPT)
13269 {
13270 rcStrict = VINF_SUCCESS;
13271 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13272 }
13273 return VBOXSTRICTRC_VAL(rcStrict);
13274}
13275
13276
13277/**
13278 * VM-exit exception handler wrapper for generic exceptions. Simply re-injects
13279 * the exception reported in the VMX transient structure back into the VM.
13280 *
13281 * @remarks Requires uExitIntInfo in the VMX transient structure to be
13282 * up-to-date.
13283 */
13284static int hmR0VmxExitXcptGeneric(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13285{
13286 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13287#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
13288 AssertMsg(pVCpu->hm.s.fUsingDebugLoop || pVCpu->hm.s.vmx.RealMode.fRealOnV86Active,
13289 ("uVector=%#x u32XcptBitmap=%#X32\n",
13290 VMX_EXIT_INT_INFO_VECTOR(pVmxTransient->uExitIntInfo), pVCpu->hm.s.vmx.u32XcptBitmap));
13291#endif
13292
13293 /* Re-inject the exception into the guest. This cannot be a double-fault condition which would have been handled in
13294 hmR0VmxCheckExitDueToEventDelivery(). */
13295 int rc = hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13296 rc |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13297 AssertRCReturn(rc, rc);
13298 Assert(ASMAtomicUoReadU32(&pVmxTransient->fVmcsFieldsRead) & HMVMX_READ_EXIT_INTERRUPTION_INFO);
13299
13300#ifdef DEBUG_ramshankar
13301 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RIP);
13302 uint8_t uVector = VMX_EXIT_INT_INFO_VECTOR(pVmxTransient->uExitIntInfo);
13303 Log(("hmR0VmxExitXcptGeneric: Reinjecting Xcpt. uVector=%#x cs:rip=%#04x:%#RX64\n", uVector, pCtx->cs.Sel, pCtx->rip));
13304#endif
13305
13306 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), pVmxTransient->cbInstr,
13307 pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13308 return VINF_SUCCESS;
13309}
13310
13311
13312/**
13313 * VM-exit exception handler for \#PF (Page-fault exception).
13314 */
13315static int hmR0VmxExitXcptPF(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13316{
13317 HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13318 PVM pVM = pVCpu->CTX_SUFF(pVM);
13319 int rc = hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
13320 rc |= hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13321 rc |= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13322 AssertRCReturn(rc, rc);
13323
13324 if (!pVM->hm.s.fNestedPaging)
13325 { /* likely */ }
13326 else
13327 {
13328#if !defined(HMVMX_ALWAYS_TRAP_ALL_XCPTS) && !defined(HMVMX_ALWAYS_TRAP_PF)
13329 Assert(pVCpu->hm.s.fUsingDebugLoop);
13330#endif
13331 pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
13332 if (RT_LIKELY(!pVmxTransient->fVectoringDoublePF))
13333 {
13334 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), 0 /* cbInstr */,
13335 pVmxTransient->uExitIntErrorCode, pVmxTransient->uExitQual);
13336 }
13337 else
13338 {
13339 /* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
13340 hmR0VmxSetPendingXcptDF(pVCpu);
13341 Log4Func(("Pending #DF due to vectoring #PF w/ NestedPaging\n"));
13342 }
13343 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
13344 return rc;
13345 }
13346
13347 /* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
13348 of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
13349 if (pVmxTransient->fVectoringPF)
13350 {
13351 Assert(pVCpu->hm.s.Event.fPending);
13352 return VINF_EM_RAW_INJECT_TRPM_EVENT;
13353 }
13354
13355 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
13356 rc = HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, HMVMX_CPUMCTX_EXTRN_ALL);
13357 AssertRCReturn(rc, rc);
13358
13359 Log4Func(("#PF: cr2=%#RX64 cs:rip=%#04x:%#RX64 uErrCode %#RX32 cr3=%#RX64\n", pVmxTransient->uExitQual, pCtx->cs.Sel,
13360 pCtx->rip, pVmxTransient->uExitIntErrorCode, pCtx->cr3));
13361
13362 TRPMAssertXcptPF(pVCpu, pVmxTransient->uExitQual, (RTGCUINT)pVmxTransient->uExitIntErrorCode);
13363 rc = PGMTrap0eHandler(pVCpu, pVmxTransient->uExitIntErrorCode, CPUMCTX2CORE(pCtx), (RTGCPTR)pVmxTransient->uExitQual);
13364
13365 Log4Func(("#PF: rc=%Rrc\n", rc));
13366 if (rc == VINF_SUCCESS)
13367 {
13368 /*
13369 * This is typically a shadow page table sync or a MMIO instruction. But we may have
13370 * emulated something like LTR or a far jump. Any part of the CPU context may have changed.
13371 */
13372 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
13373 TRPMResetTrap(pVCpu);
13374 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
13375 return rc;
13376 }
13377
13378 if (rc == VINF_EM_RAW_GUEST_TRAP)
13379 {
13380 if (!pVmxTransient->fVectoringDoublePF)
13381 {
13382 /* It's a guest page fault and needs to be reflected to the guest. */
13383 uint32_t uGstErrorCode = TRPMGetErrorCode(pVCpu);
13384 TRPMResetTrap(pVCpu);
13385 pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory #PF. */
13386 hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo), 0 /* cbInstr */,
13387 uGstErrorCode, pVmxTransient->uExitQual);
13388 }
13389 else
13390 {
13391 /* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
13392 TRPMResetTrap(pVCpu);
13393 pVCpu->hm.s.Event.fPending = false; /* Clear pending #PF to replace it with #DF. */
13394 hmR0VmxSetPendingXcptDF(pVCpu);
13395 Log4Func(("#PF: Pending #DF due to vectoring #PF\n"));
13396 }
13397
13398 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
13399 return VINF_SUCCESS;
13400 }
13401
13402 TRPMResetTrap(pVCpu);
13403 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
13404 return rc;
13405}
13406
13407/** @} */
13408
13409#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
13410/** @name Nested-guest VM-exit handlers.
13411 * @{
13412 */
13413/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
13414/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Nested-guest VM-exit handlers =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
13415/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
13416
13417/**
13418 * VM-exit handler for VMCLEAR (VMX_EXIT_VMCLEAR). Unconditional VM-exit.
13419 */
13420HMVMX_EXIT_DECL hmR0VmxExitVmclear(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13421{
13422 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13423
13424 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13425 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK
13426 | IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
13427 rc |= hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
13428 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
13429 AssertRCReturn(rc, rc);
13430
13431 HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
13432
13433 VMXVEXITINFO ExitInfo;
13434 RT_ZERO(ExitInfo);
13435 ExitInfo.uReason = pVmxTransient->uExitReason;
13436 ExitInfo.u64Qual = pVmxTransient->uExitQual;
13437 ExitInfo.InstrInfo.u = pVmxTransient->ExitInstrInfo.u;
13438 ExitInfo.cbInstr = pVmxTransient->cbInstr;
13439 HMVMX_DECODE_MEM_OPERAND(pVCpu, ExitInfo.InstrInfo.u, ExitInfo.u64Qual, VMXMEMACCESS_READ, &ExitInfo.GCPtrEffAddr);
13440
13441 VBOXSTRICTRC rcStrict = IEMExecDecodedVmclear(pVCpu, &ExitInfo);
13442 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
13443 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_HWVIRT);
13444 else if (rcStrict == VINF_IEM_RAISED_XCPT)
13445 {
13446 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13447 rcStrict = VINF_SUCCESS;
13448 }
13449 return rcStrict;
13450}
13451
13452
13453/**
13454 * VM-exit handler for VMLAUNCH (VMX_EXIT_VMLAUNCH). Unconditional VM-exit.
13455 */
13456HMVMX_EXIT_DECL hmR0VmxExitVmlaunch(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13457{
13458 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13459
13460 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13461 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK);
13462 AssertRCReturn(rc, rc);
13463
13464 HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
13465
13466 VBOXSTRICTRC rcStrict = IEMExecDecodedVmlaunchVmresume(pVCpu, pVmxTransient->cbInstr, VMXINSTRID_VMLAUNCH);
13467 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
13468 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
13469 Assert(rcStrict != VINF_IEM_RAISED_XCPT);
13470 return rcStrict;
13471}
13472
13473
13474/**
13475 * VM-exit handler for VMPTRLD (VMX_EXIT_VMPTRLD). Unconditional VM-exit.
13476 */
13477HMVMX_EXIT_DECL hmR0VmxExitVmptrld(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13478{
13479 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13480
13481 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13482 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK
13483 | IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
13484 rc |= hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
13485 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
13486 AssertRCReturn(rc, rc);
13487
13488 HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
13489
13490 VMXVEXITINFO ExitInfo;
13491 RT_ZERO(ExitInfo);
13492 ExitInfo.uReason = pVmxTransient->uExitReason;
13493 ExitInfo.u64Qual = pVmxTransient->uExitQual;
13494 ExitInfo.InstrInfo.u = pVmxTransient->ExitInstrInfo.u;
13495 ExitInfo.cbInstr = pVmxTransient->cbInstr;
13496 HMVMX_DECODE_MEM_OPERAND(pVCpu, ExitInfo.InstrInfo.u, ExitInfo.u64Qual, VMXMEMACCESS_READ, &ExitInfo.GCPtrEffAddr);
13497
13498 VBOXSTRICTRC rcStrict = IEMExecDecodedVmptrld(pVCpu, &ExitInfo);
13499 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
13500 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_HWVIRT);
13501 else if (rcStrict == VINF_IEM_RAISED_XCPT)
13502 {
13503 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13504 rcStrict = VINF_SUCCESS;
13505 }
13506 return rcStrict;
13507}
13508
13509
13510/**
13511 * VM-exit handler for VMPTRST (VMX_EXIT_VMPTRST). Unconditional VM-exit.
13512 */
13513HMVMX_EXIT_DECL hmR0VmxExitVmptrst(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13514{
13515 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13516
13517 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13518 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK
13519 | IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
13520 rc |= hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
13521 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
13522 AssertRCReturn(rc, rc);
13523
13524 HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
13525
13526 VMXVEXITINFO ExitInfo;
13527 RT_ZERO(ExitInfo);
13528 ExitInfo.uReason = pVmxTransient->uExitReason;
13529 ExitInfo.u64Qual = pVmxTransient->uExitQual;
13530 ExitInfo.InstrInfo.u = pVmxTransient->ExitInstrInfo.u;
13531 ExitInfo.cbInstr = pVmxTransient->cbInstr;
13532 HMVMX_DECODE_MEM_OPERAND(pVCpu, ExitInfo.InstrInfo.u, ExitInfo.u64Qual, VMXMEMACCESS_WRITE, &ExitInfo.GCPtrEffAddr);
13533
13534 VBOXSTRICTRC rcStrict = IEMExecDecodedVmptrst(pVCpu, &ExitInfo);
13535 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
13536 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_HWVIRT);
13537 else if (rcStrict == VINF_IEM_RAISED_XCPT)
13538 {
13539 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13540 rcStrict = VINF_SUCCESS;
13541 }
13542 return rcStrict;
13543}
13544
13545
13546/**
13547 * VM-exit handler for VMREAD (VMX_EXIT_VMREAD). Unconditional VM-exit.
13548 */
13549HMVMX_EXIT_DECL hmR0VmxExitVmread(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13550{
13551 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13552
13553 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13554 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK
13555 | IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
13556 rc |= hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
13557 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
13558 AssertRCReturn(rc, rc);
13559
13560 HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
13561
13562 VMXVEXITINFO ExitInfo;
13563 RT_ZERO(ExitInfo);
13564 ExitInfo.uReason = pVmxTransient->uExitReason;
13565 ExitInfo.u64Qual = pVmxTransient->uExitQual;
13566 ExitInfo.InstrInfo.u = pVmxTransient->ExitInstrInfo.u;
13567 ExitInfo.cbInstr = pVmxTransient->cbInstr;
13568 if (!ExitInfo.InstrInfo.VmreadVmwrite.fIsRegOperand)
13569 HMVMX_DECODE_MEM_OPERAND(pVCpu, ExitInfo.InstrInfo.u, ExitInfo.u64Qual, VMXMEMACCESS_WRITE, &ExitInfo.GCPtrEffAddr);
13570
13571 VBOXSTRICTRC rcStrict = IEMExecDecodedVmread(pVCpu, &ExitInfo);
13572 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
13573 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_HWVIRT);
13574 else if (rcStrict == VINF_IEM_RAISED_XCPT)
13575 {
13576 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13577 rcStrict = VINF_SUCCESS;
13578 }
13579 return rcStrict;
13580}
13581
13582
13583/**
13584 * VM-exit handler for VMRESUME (VMX_EXIT_VMRESUME). Unconditional VM-exit.
13585 */
13586HMVMX_EXIT_DECL hmR0VmxExitVmresume(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13587{
13588 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13589
13590 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13591 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK);
13592 AssertRCReturn(rc, rc);
13593
13594 HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
13595
13596 VBOXSTRICTRC rcStrict = IEMExecDecodedVmlaunchVmresume(pVCpu, pVmxTransient->cbInstr, VMXINSTRID_VMRESUME);
13597 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
13598 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
13599 Assert(rcStrict != VINF_IEM_RAISED_XCPT);
13600 return rcStrict;
13601}
13602
13603
13604/**
13605 * VM-exit handler for VMWRITE (VMX_EXIT_VMWRITE). Unconditional VM-exit.
13606 */
13607HMVMX_EXIT_DECL hmR0VmxExitVmwrite(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13608{
13609 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13610
13611 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13612 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK
13613 | IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
13614 rc |= hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
13615 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
13616 AssertRCReturn(rc, rc);
13617
13618 HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
13619
13620 VMXVEXITINFO ExitInfo;
13621 RT_ZERO(ExitInfo);
13622 ExitInfo.uReason = pVmxTransient->uExitReason;
13623 ExitInfo.u64Qual = pVmxTransient->uExitQual;
13624 ExitInfo.InstrInfo.u = pVmxTransient->ExitInstrInfo.u;
13625 ExitInfo.cbInstr = pVmxTransient->cbInstr;
13626 if (!ExitInfo.InstrInfo.VmreadVmwrite.fIsRegOperand)
13627 HMVMX_DECODE_MEM_OPERAND(pVCpu, ExitInfo.InstrInfo.u, ExitInfo.u64Qual, VMXMEMACCESS_READ, &ExitInfo.GCPtrEffAddr);
13628
13629 VBOXSTRICTRC rcStrict = IEMExecDecodedVmwrite(pVCpu, &ExitInfo);
13630 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
13631 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_HWVIRT);
13632 else if (rcStrict == VINF_IEM_RAISED_XCPT)
13633 {
13634 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13635 rcStrict = VINF_SUCCESS;
13636 }
13637 return rcStrict;
13638}
13639
13640
13641/**
13642 * VM-exit handler for VMXOFF (VMX_EXIT_VMXOFF). Unconditional VM-exit.
13643 */
13644HMVMX_EXIT_DECL hmR0VmxExitVmxoff(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13645{
13646 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13647
13648 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13649 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR4 | IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
13650 AssertRCReturn(rc, rc);
13651
13652 HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
13653
13654 VBOXSTRICTRC rcStrict = IEMExecDecodedVmxoff(pVCpu, pVmxTransient->cbInstr);
13655 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
13656 {
13657 /* VMXOFF changes the internal hwvirt. state but not anything that's visible to the guest other than RIP. */
13658 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_HWVIRT);
13659 }
13660 else if (rcStrict == VINF_IEM_RAISED_XCPT)
13661 {
13662 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13663 rcStrict = VINF_SUCCESS;
13664 }
13665 return rcStrict;
13666}
13667
13668
13669/**
13670 * VM-exit handler for VMXON (VMX_EXIT_VMXON). Unconditional VM-exit.
13671 */
13672HMVMX_EXIT_DECL hmR0VmxExitVmxon(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
13673{
13674 HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
13675
13676 int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13677 rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_SREG_MASK
13678 | IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
13679 rc |= hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
13680 rc |= hmR0VmxReadExitQualVmcs(pVCpu, pVmxTransient);
13681 AssertRCReturn(rc, rc);
13682
13683 HMVMX_CHECK_EXIT_DUE_TO_VMX_INSTR(pVCpu, pVmxTransient->uExitReason);
13684
13685 VMXVEXITINFO ExitInfo;
13686 RT_ZERO(ExitInfo);
13687 ExitInfo.uReason = pVmxTransient->uExitReason;
13688 ExitInfo.u64Qual = pVmxTransient->uExitQual;
13689 ExitInfo.InstrInfo.u = pVmxTransient->ExitInstrInfo.u;
13690 ExitInfo.cbInstr = pVmxTransient->cbInstr;
13691 HMVMX_DECODE_MEM_OPERAND(pVCpu, ExitInfo.InstrInfo.u, ExitInfo.u64Qual, VMXMEMACCESS_READ, &ExitInfo.GCPtrEffAddr);
13692
13693 VBOXSTRICTRC rcStrict = IEMExecDecodedVmxon(pVCpu, &ExitInfo);
13694 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
13695 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_HWVIRT);
13696 else if (rcStrict == VINF_IEM_RAISED_XCPT)
13697 {
13698 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
13699 rcStrict = VINF_SUCCESS;
13700 }
13701 return rcStrict;
13702}
13703
13704/** @} */
13705#endif /* VBOX_WITH_NESTED_HWVIRT_VMX */
13706
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