HMVMXR0.cpp@ 65697

Last change on this file since 65697 was 65697, checked in by vboxsync, 8 years ago
VMM/HMVMXR0: Set HM_CHANGED_ALL_GUEST after saving the guest state to avoid assertions that verify the guest-CPU state isn't overwritten with stale info. from the VMCS.
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1	/* $Id: HMVMXR0.cpp 65697 2017-02-09 12:24:35Z vboxsync $ */
2	/** @file
3	* HM VMX (Intel VT-x) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2012-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <iprt/x86.h>
24	#include <iprt/asm-amd64-x86.h>
25	#include <iprt/thread.h>
26
27	#include <VBox/vmm/pdmapi.h>
28	#include <VBox/vmm/dbgf.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/selm.h>
32	#include <VBox/vmm/tm.h>
33	#include <VBox/vmm/gim.h>
34	#include <VBox/vmm/apic.h>
35	#ifdef VBOX_WITH_REM
36	# include <VBox/vmm/rem.h>
37	#endif
38	#include "HMInternal.h"
39	#include <VBox/vmm/vm.h>
40	#include "HMVMXR0.h"
41	#include "dtrace/VBoxVMM.h"
42
43	#ifdef DEBUG_ramshankar
44	# define HMVMX_ALWAYS_SAVE_GUEST_RFLAGS
45	# define HMVMX_ALWAYS_SAVE_FULL_GUEST_STATE
46	# define HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE
47	# define HMVMX_ALWAYS_CHECK_GUEST_STATE
48	# define HMVMX_ALWAYS_TRAP_ALL_XCPTS
49	# define HMVMX_ALWAYS_TRAP_PF
50	# define HMVMX_ALWAYS_SWAP_FPU_STATE
51	# define HMVMX_ALWAYS_FLUSH_TLB
52	# define HMVMX_ALWAYS_SWAP_EFER
53	#endif
54
55
56	/*********************************************************************************************************************************
57	* Defined Constants And Macros *
58	*********************************************************************************************************************************/
59	/** Use the function table. */
60	#define HMVMX_USE_FUNCTION_TABLE
61
62	/** Determine which tagged-TLB flush handler to use. */
63	#define HMVMX_FLUSH_TAGGED_TLB_EPT_VPID 0
64	#define HMVMX_FLUSH_TAGGED_TLB_EPT 1
65	#define HMVMX_FLUSH_TAGGED_TLB_VPID 2
66	#define HMVMX_FLUSH_TAGGED_TLB_NONE 3
67
68	/** @name Updated-guest-state flags.
69	* @{ */
70	#define HMVMX_UPDATED_GUEST_RIP RT_BIT(0)
71	#define HMVMX_UPDATED_GUEST_RSP RT_BIT(1)
72	#define HMVMX_UPDATED_GUEST_RFLAGS RT_BIT(2)
73	#define HMVMX_UPDATED_GUEST_CR0 RT_BIT(3)
74	#define HMVMX_UPDATED_GUEST_CR3 RT_BIT(4)
75	#define HMVMX_UPDATED_GUEST_CR4 RT_BIT(5)
76	#define HMVMX_UPDATED_GUEST_GDTR RT_BIT(6)
77	#define HMVMX_UPDATED_GUEST_IDTR RT_BIT(7)
78	#define HMVMX_UPDATED_GUEST_LDTR RT_BIT(8)
79	#define HMVMX_UPDATED_GUEST_TR RT_BIT(9)
80	#define HMVMX_UPDATED_GUEST_SEGMENT_REGS RT_BIT(10)
81	#define HMVMX_UPDATED_GUEST_DR7 RT_BIT(11)
82	#define HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR RT_BIT(12)
83	#define HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR RT_BIT(13)
84	#define HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR RT_BIT(14)
85	#define HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS RT_BIT(15)
86	#define HMVMX_UPDATED_GUEST_LAZY_MSRS RT_BIT(16)
87	#define HMVMX_UPDATED_GUEST_ACTIVITY_STATE RT_BIT(17)
88	#define HMVMX_UPDATED_GUEST_INTR_STATE RT_BIT(18)
89	#define HMVMX_UPDATED_GUEST_APIC_STATE RT_BIT(19)
90	#define HMVMX_UPDATED_GUEST_ALL ( HMVMX_UPDATED_GUEST_RIP \
91	\| HMVMX_UPDATED_GUEST_RSP \
92	\| HMVMX_UPDATED_GUEST_RFLAGS \
93	\| HMVMX_UPDATED_GUEST_CR0 \
94	\| HMVMX_UPDATED_GUEST_CR3 \
95	\| HMVMX_UPDATED_GUEST_CR4 \
96	\| HMVMX_UPDATED_GUEST_GDTR \
97	\| HMVMX_UPDATED_GUEST_IDTR \
98	\| HMVMX_UPDATED_GUEST_LDTR \
99	\| HMVMX_UPDATED_GUEST_TR \
100	\| HMVMX_UPDATED_GUEST_SEGMENT_REGS \
101	\| HMVMX_UPDATED_GUEST_DR7 \
102	\| HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR \
103	\| HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR \
104	\| HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR \
105	\| HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS \
106	\| HMVMX_UPDATED_GUEST_LAZY_MSRS \
107	\| HMVMX_UPDATED_GUEST_ACTIVITY_STATE \
108	\| HMVMX_UPDATED_GUEST_INTR_STATE \
109	\| HMVMX_UPDATED_GUEST_APIC_STATE)
110	/** @} */
111
112	/** @name
113	* Flags to skip redundant reads of some common VMCS fields that are not part of
114	* the guest-CPU state but are in the transient structure.
115	*/
116	#define HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_INFO RT_BIT(0)
117	#define HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_ERROR_CODE RT_BIT(1)
118	#define HMVMX_UPDATED_TRANSIENT_EXIT_QUALIFICATION RT_BIT(2)
119	#define HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_LEN RT_BIT(3)
120	#define HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO RT_BIT(4)
121	#define HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_ERROR_CODE RT_BIT(5)
122	#define HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_INFO RT_BIT(6)
123	/** @} */
124
125	/** @name
126	* States of the VMCS.
127	*
128	* This does not reflect all possible VMCS states but currently only those
129	* needed for maintaining the VMCS consistently even when thread-context hooks
130	* are used. Maybe later this can be extended (i.e. Nested Virtualization).
131	*/
132	#define HMVMX_VMCS_STATE_CLEAR RT_BIT(0)
133	#define HMVMX_VMCS_STATE_ACTIVE RT_BIT(1)
134	#define HMVMX_VMCS_STATE_LAUNCHED RT_BIT(2)
135	/** @} */
136
137	/**
138	* Exception bitmap mask for real-mode guests (real-on-v86).
139	*
140	* We need to intercept all exceptions manually except:
141	* - \#NM, \#MF handled in hmR0VmxLoadSharedCR0().
142	* - \#AC and \#DB are always intercepted to prevent the CPU from deadlocking
143	* due to bugs in Intel CPUs.
144	* - \#PF need not be intercepted even in real-mode if we have Nested Paging
145	* support.
146	*/
147	#define HMVMX_REAL_MODE_XCPT_MASK ( RT_BIT(X86_XCPT_DE) /* always: \| RT_BIT(X86_XCPT_DB) */ \| RT_BIT(X86_XCPT_NMI) \
148	\| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \
149	\| RT_BIT(X86_XCPT_UD) /* RT_BIT(X86_XCPT_NM) */ \| RT_BIT(X86_XCPT_DF) \
150	\| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \
151	\| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) /* RT_BIT(X86_XCPT_PF) */ \
152	/* RT_BIT(X86_XCPT_MF) always: \| RT_BIT(X86_XCPT_AC) */ \| RT_BIT(X86_XCPT_MC) \
153	\| RT_BIT(X86_XCPT_XF))
154
155	/**
156	* Exception bitmap mask for all contributory exceptions.
157	*
158	* Page fault is deliberately excluded here as it's conditional as to whether
159	* it's contributory or benign. Page faults are handled separately.
160	*/
161	#define HMVMX_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
162	\| RT_BIT(X86_XCPT_DE))
163
164	/** Maximum VM-instruction error number. */
165	#define HMVMX_INSTR_ERROR_MAX 28
166
167	/** Profiling macro. */
168	#ifdef HM_PROFILE_EXIT_DISPATCH
169	# define HMVMX_START_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitDispatch, ed)
170	# define HMVMX_STOP_EXIT_DISPATCH_PROF() STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitDispatch, ed)
171	#else
172	# define HMVMX_START_EXIT_DISPATCH_PROF() do { } while (0)
173	# define HMVMX_STOP_EXIT_DISPATCH_PROF() do { } while (0)
174	#endif
175
176	/** Assert that preemption is disabled or covered by thread-context hooks. */
177	#define HMVMX_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
178	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
179
180	/** Assert that we haven't migrated CPUs when thread-context hooks are not
181	* used. */
182	#define HMVMX_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
183	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
184	("Illegal migration! Entered on CPU %u Current %u\n", \
185	pVCpu->hm.s.idEnteredCpu, RTMpCpuId())); \
186
187	/** Helper macro for VM-exit handlers called unexpectedly. */
188	#define HMVMX_RETURN_UNEXPECTED_EXIT() \
189	do { \
190	pVCpu->hm.s.u32HMError = pVmxTransient->uExitReason; \
191	return VERR_VMX_UNEXPECTED_EXIT; \
192	} while (0)
193
194
195	/*********************************************************************************************************************************
196	* Structures and Typedefs *
197	*********************************************************************************************************************************/
198	/**
199	* VMX transient state.
200	*
201	* A state structure for holding miscellaneous information across
202	* VMX non-root operation and restored after the transition.
203	*/
204	typedef struct VMXTRANSIENT
205	{
206	/** The host's rflags/eflags. */
207	RTCCUINTREG fEFlags;
208	#if HC_ARCH_BITS == 32
209	uint32_t u32Alignment0;
210	#endif
211	/** The guest's TPR value used for TPR shadowing. */
212	uint8_t u8GuestTpr;
213	/** Alignment. */
214	uint8_t abAlignment0[7];
215
216	/** The basic VM-exit reason. */
217	uint16_t uExitReason;
218	/** Alignment. */
219	uint16_t u16Alignment0;
220	/** The VM-exit interruption error code. */
221	uint32_t uExitIntErrorCode;
222	/** The VM-exit exit code qualification. */
223	uint64_t uExitQualification;
224
225	/** The VM-exit interruption-information field. */
226	uint32_t uExitIntInfo;
227	/** The VM-exit instruction-length field. */
228	uint32_t cbInstr;
229	/** The VM-exit instruction-information field. */
230	union
231	{
232	/** Plain unsigned int representation. */
233	uint32_t u;
234	/** INS and OUTS information. */
235	struct
236	{
237	uint32_t u7Reserved0 : 7;
238	/** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
239	uint32_t u3AddrSize : 3;
240	uint32_t u5Reserved1 : 5;
241	/** The segment register (X86_SREG_XXX). */
242	uint32_t iSegReg : 3;
243	uint32_t uReserved2 : 14;
244	} StrIo;
245	} ExitInstrInfo;
246	/** Whether the VM-entry failed or not. */
247	bool fVMEntryFailed;
248	/** Alignment. */
249	uint8_t abAlignment1[3];
250
251	/** The VM-entry interruption-information field. */
252	uint32_t uEntryIntInfo;
253	/** The VM-entry exception error code field. */
254	uint32_t uEntryXcptErrorCode;
255	/** The VM-entry instruction length field. */
256	uint32_t cbEntryInstr;
257
258	/** IDT-vectoring information field. */
259	uint32_t uIdtVectoringInfo;
260	/** IDT-vectoring error code. */
261	uint32_t uIdtVectoringErrorCode;
262
263	/** Mask of currently read VMCS fields; HMVMX_UPDATED_TRANSIENT_. /
264	uint32_t fVmcsFieldsRead;
265
266	/** Whether the guest FPU was active at the time of VM-exit. */
267	bool fWasGuestFPUStateActive;
268	/** Whether the guest debug state was active at the time of VM-exit. */
269	bool fWasGuestDebugStateActive;
270	/** Whether the hyper debug state was active at the time of VM-exit. */
271	bool fWasHyperDebugStateActive;
272	/** Whether TSC-offsetting should be setup before VM-entry. */
273	bool fUpdateTscOffsettingAndPreemptTimer;
274	/** Whether the VM-exit was caused by a page-fault during delivery of a
275	* contributory exception or a page-fault. */
276	bool fVectoringDoublePF;
277	/** Whether the VM-exit was caused by a page-fault during delivery of an
278	* external interrupt or NMI. */
279	bool fVectoringPF;
280	} VMXTRANSIENT;
281	AssertCompileMemberAlignment(VMXTRANSIENT, uExitReason, sizeof(uint64_t));
282	AssertCompileMemberAlignment(VMXTRANSIENT, uExitIntInfo, sizeof(uint64_t));
283	AssertCompileMemberAlignment(VMXTRANSIENT, uEntryIntInfo, sizeof(uint64_t));
284	AssertCompileMemberAlignment(VMXTRANSIENT, fWasGuestFPUStateActive, sizeof(uint64_t));
285	AssertCompileMemberSize(VMXTRANSIENT, ExitInstrInfo, sizeof(uint32_t));
286	/** Pointer to VMX transient state. */
287	typedef VMXTRANSIENT *PVMXTRANSIENT;
288
289
290	/**
291	* MSR-bitmap read permissions.
292	*/
293	typedef enum VMXMSREXITREAD
294	{
295	/** Reading this MSR causes a VM-exit. */
296	VMXMSREXIT_INTERCEPT_READ = 0xb,
297	/** Reading this MSR does not cause a VM-exit. */
298	VMXMSREXIT_PASSTHRU_READ
299	} VMXMSREXITREAD;
300	/** Pointer to MSR-bitmap read permissions. */
301	typedef VMXMSREXITREAD* PVMXMSREXITREAD;
302
303	/**
304	* MSR-bitmap write permissions.
305	*/
306	typedef enum VMXMSREXITWRITE
307	{
308	/** Writing to this MSR causes a VM-exit. */
309	VMXMSREXIT_INTERCEPT_WRITE = 0xd,
310	/** Writing to this MSR does not cause a VM-exit. */
311	VMXMSREXIT_PASSTHRU_WRITE
312	} VMXMSREXITWRITE;
313	/** Pointer to MSR-bitmap write permissions. */
314	typedef VMXMSREXITWRITE* PVMXMSREXITWRITE;
315
316
317	/**
318	* VMX VM-exit handler.
319	*
320	* @returns Strict VBox status code (i.e. informational status codes too).
321	* @param pVCpu The cross context virtual CPU structure.
322	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
323	* out-of-sync. Make sure to update the required
324	* fields before using them.
325	* @param pVmxTransient Pointer to the VMX-transient structure.
326	*/
327	#ifndef HMVMX_USE_FUNCTION_TABLE
328	typedef VBOXSTRICTRC FNVMXEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
329	#else
330	typedef DECLCALLBACK(VBOXSTRICTRC) FNVMXEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
331	/** Pointer to VM-exit handler. */
332	typedef FNVMXEXITHANDLER *PFNVMXEXITHANDLER;
333	#endif
334
335	/**
336	* VMX VM-exit handler, non-strict status code.
337	*
338	* This is generally the same as FNVMXEXITHANDLER, the NSRC bit is just FYI.
339	*
340	* @returns VBox status code, no informational status code returned.
341	* @param pVCpu The cross context virtual CPU structure.
342	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
343	* out-of-sync. Make sure to update the required
344	* fields before using them.
345	* @param pVmxTransient Pointer to the VMX-transient structure.
346	*
347	* @remarks This is not used on anything returning VERR_EM_INTERPRETER as the
348	* use of that status code will be replaced with VINF_EM_SOMETHING
349	* later when switching over to IEM.
350	*/
351	#ifndef HMVMX_USE_FUNCTION_TABLE
352	typedef int FNVMXEXITHANDLERNSRC(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
353	#else
354	typedef FNVMXEXITHANDLER FNVMXEXITHANDLERNSRC;
355	#endif
356
357
358	/*********************************************************************************************************************************
359	* Internal Functions *
360	*********************************************************************************************************************************/
361	static void hmR0VmxFlushEpt(PVMCPU pVCpu, VMXFLUSHEPT enmFlush);
362	static void hmR0VmxFlushVpid(PVM pVM, PVMCPU pVCpu, VMXFLUSHVPID enmFlush, RTGCPTR GCPtr);
363	static void hmR0VmxClearIntNmiWindowsVmcs(PVMCPU pVCpu);
364	static VBOXSTRICTRC hmR0VmxInjectEventVmcs(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint64_t u64IntInfo, uint32_t cbInstr,
365	uint32_t u32ErrCode, RTGCUINTREG GCPtrFaultAddress,
366	bool fStepping, uint32_t *puIntState);
367	#if HC_ARCH_BITS == 32
368	static int hmR0VmxInitVmcsReadCache(PVM pVM, PVMCPU pVCpu);
369	#endif
370	#ifndef HMVMX_USE_FUNCTION_TABLE
371	DECLINLINE(VBOXSTRICTRC) hmR0VmxHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, uint32_t rcReason);
372	# define HMVMX_EXIT_DECL DECLINLINE(VBOXSTRICTRC)
373	# define HMVMX_EXIT_NSRC_DECL DECLINLINE(int)
374	#else
375	# define HMVMX_EXIT_DECL static DECLCALLBACK(VBOXSTRICTRC)
376	# define HMVMX_EXIT_NSRC_DECL HMVMX_EXIT_DECL
377	#endif
378
379
380	/** @name VM-exit handlers.
381	* @{
382	*/
383	static FNVMXEXITHANDLER hmR0VmxExitXcptOrNmi;
384	static FNVMXEXITHANDLER hmR0VmxExitExtInt;
385	static FNVMXEXITHANDLER hmR0VmxExitTripleFault;
386	static FNVMXEXITHANDLERNSRC hmR0VmxExitInitSignal;
387	static FNVMXEXITHANDLERNSRC hmR0VmxExitSipi;
388	static FNVMXEXITHANDLERNSRC hmR0VmxExitIoSmi;
389	static FNVMXEXITHANDLERNSRC hmR0VmxExitSmi;
390	static FNVMXEXITHANDLERNSRC hmR0VmxExitIntWindow;
391	static FNVMXEXITHANDLERNSRC hmR0VmxExitNmiWindow;
392	static FNVMXEXITHANDLER hmR0VmxExitTaskSwitch;
393	static FNVMXEXITHANDLER hmR0VmxExitCpuid;
394	static FNVMXEXITHANDLER hmR0VmxExitGetsec;
395	static FNVMXEXITHANDLER hmR0VmxExitHlt;
396	static FNVMXEXITHANDLERNSRC hmR0VmxExitInvd;
397	static FNVMXEXITHANDLER hmR0VmxExitInvlpg;
398	static FNVMXEXITHANDLER hmR0VmxExitRdpmc;
399	static FNVMXEXITHANDLER hmR0VmxExitVmcall;
400	static FNVMXEXITHANDLER hmR0VmxExitRdtsc;
401	static FNVMXEXITHANDLERNSRC hmR0VmxExitRsm;
402	static FNVMXEXITHANDLERNSRC hmR0VmxExitSetPendingXcptUD;
403	static FNVMXEXITHANDLER hmR0VmxExitMovCRx;
404	static FNVMXEXITHANDLER hmR0VmxExitMovDRx;
405	static FNVMXEXITHANDLER hmR0VmxExitIoInstr;
406	static FNVMXEXITHANDLER hmR0VmxExitRdmsr;
407	static FNVMXEXITHANDLER hmR0VmxExitWrmsr;
408	static FNVMXEXITHANDLERNSRC hmR0VmxExitErrInvalidGuestState;
409	static FNVMXEXITHANDLERNSRC hmR0VmxExitErrMsrLoad;
410	static FNVMXEXITHANDLERNSRC hmR0VmxExitErrUndefined;
411	static FNVMXEXITHANDLER hmR0VmxExitMwait;
412	static FNVMXEXITHANDLER hmR0VmxExitMtf;
413	static FNVMXEXITHANDLER hmR0VmxExitMonitor;
414	static FNVMXEXITHANDLER hmR0VmxExitPause;
415	static FNVMXEXITHANDLERNSRC hmR0VmxExitErrMachineCheck;
416	static FNVMXEXITHANDLERNSRC hmR0VmxExitTprBelowThreshold;
417	static FNVMXEXITHANDLER hmR0VmxExitApicAccess;
418	static FNVMXEXITHANDLER hmR0VmxExitXdtrAccess;
419	static FNVMXEXITHANDLER hmR0VmxExitXdtrAccess;
420	static FNVMXEXITHANDLER hmR0VmxExitEptViolation;
421	static FNVMXEXITHANDLER hmR0VmxExitEptMisconfig;
422	static FNVMXEXITHANDLER hmR0VmxExitRdtscp;
423	static FNVMXEXITHANDLER hmR0VmxExitPreemptTimer;
424	static FNVMXEXITHANDLERNSRC hmR0VmxExitWbinvd;
425	static FNVMXEXITHANDLER hmR0VmxExitXsetbv;
426	static FNVMXEXITHANDLER hmR0VmxExitRdrand;
427	static FNVMXEXITHANDLER hmR0VmxExitInvpcid;
428	/** @} */
429
430	static int hmR0VmxExitXcptNM(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
431	static int hmR0VmxExitXcptPF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
432	static int hmR0VmxExitXcptMF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
433	static int hmR0VmxExitXcptDB(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
434	static int hmR0VmxExitXcptBP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
435	static int hmR0VmxExitXcptGP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
436	static int hmR0VmxExitXcptAC(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
437	static int hmR0VmxExitXcptGeneric(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient);
438	static uint32_t hmR0VmxCheckGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
439
440
441	/*********************************************************************************************************************************
442	* Global Variables *
443	*********************************************************************************************************************************/
444	#ifdef HMVMX_USE_FUNCTION_TABLE
445
446	/**
447	* VMX_EXIT dispatch table.
448	*/
449	static const PFNVMXEXITHANDLER g_apfnVMExitHandlers[VMX_EXIT_MAX + 1] =
450	{
451	/* 00 VMX_EXIT_XCPT_OR_NMI */ hmR0VmxExitXcptOrNmi,
452	/* 01 VMX_EXIT_EXT_INT */ hmR0VmxExitExtInt,
453	/* 02 VMX_EXIT_TRIPLE_FAULT */ hmR0VmxExitTripleFault,
454	/* 03 VMX_EXIT_INIT_SIGNAL */ hmR0VmxExitInitSignal,
455	/* 04 VMX_EXIT_SIPI */ hmR0VmxExitSipi,
456	/* 05 VMX_EXIT_IO_SMI */ hmR0VmxExitIoSmi,
457	/* 06 VMX_EXIT_SMI */ hmR0VmxExitSmi,
458	/* 07 VMX_EXIT_INT_WINDOW */ hmR0VmxExitIntWindow,
459	/* 08 VMX_EXIT_NMI_WINDOW */ hmR0VmxExitNmiWindow,
460	/* 09 VMX_EXIT_TASK_SWITCH */ hmR0VmxExitTaskSwitch,
461	/* 10 VMX_EXIT_CPUID */ hmR0VmxExitCpuid,
462	/* 11 VMX_EXIT_GETSEC */ hmR0VmxExitGetsec,
463	/* 12 VMX_EXIT_HLT */ hmR0VmxExitHlt,
464	/* 13 VMX_EXIT_INVD */ hmR0VmxExitInvd,
465	/* 14 VMX_EXIT_INVLPG */ hmR0VmxExitInvlpg,
466	/* 15 VMX_EXIT_RDPMC */ hmR0VmxExitRdpmc,
467	/* 16 VMX_EXIT_RDTSC */ hmR0VmxExitRdtsc,
468	/* 17 VMX_EXIT_RSM */ hmR0VmxExitRsm,
469	/* 18 VMX_EXIT_VMCALL */ hmR0VmxExitVmcall,
470	/* 19 VMX_EXIT_VMCLEAR */ hmR0VmxExitSetPendingXcptUD,
471	/* 20 VMX_EXIT_VMLAUNCH */ hmR0VmxExitSetPendingXcptUD,
472	/* 21 VMX_EXIT_VMPTRLD */ hmR0VmxExitSetPendingXcptUD,
473	/* 22 VMX_EXIT_VMPTRST */ hmR0VmxExitSetPendingXcptUD,
474	/* 23 VMX_EXIT_VMREAD */ hmR0VmxExitSetPendingXcptUD,
475	/* 24 VMX_EXIT_VMRESUME */ hmR0VmxExitSetPendingXcptUD,
476	/* 25 VMX_EXIT_VMWRITE */ hmR0VmxExitSetPendingXcptUD,
477	/* 26 VMX_EXIT_VMXOFF */ hmR0VmxExitSetPendingXcptUD,
478	/* 27 VMX_EXIT_VMXON */ hmR0VmxExitSetPendingXcptUD,
479	/* 28 VMX_EXIT_MOV_CRX */ hmR0VmxExitMovCRx,
480	/* 29 VMX_EXIT_MOV_DRX */ hmR0VmxExitMovDRx,
481	/* 30 VMX_EXIT_IO_INSTR */ hmR0VmxExitIoInstr,
482	/* 31 VMX_EXIT_RDMSR */ hmR0VmxExitRdmsr,
483	/* 32 VMX_EXIT_WRMSR */ hmR0VmxExitWrmsr,
484	/* 33 VMX_EXIT_ERR_INVALID_GUEST_STATE */ hmR0VmxExitErrInvalidGuestState,
485	/* 34 VMX_EXIT_ERR_MSR_LOAD */ hmR0VmxExitErrMsrLoad,
486	/* 35 UNDEFINED */ hmR0VmxExitErrUndefined,
487	/* 36 VMX_EXIT_MWAIT */ hmR0VmxExitMwait,
488	/* 37 VMX_EXIT_MTF */ hmR0VmxExitMtf,
489	/* 38 UNDEFINED */ hmR0VmxExitErrUndefined,
490	/* 39 VMX_EXIT_MONITOR */ hmR0VmxExitMonitor,
491	/* 40 UNDEFINED */ hmR0VmxExitPause,
492	/* 41 VMX_EXIT_PAUSE */ hmR0VmxExitErrMachineCheck,
493	/* 42 VMX_EXIT_ERR_MACHINE_CHECK */ hmR0VmxExitErrUndefined,
494	/* 43 VMX_EXIT_TPR_BELOW_THRESHOLD */ hmR0VmxExitTprBelowThreshold,
495	/* 44 VMX_EXIT_APIC_ACCESS */ hmR0VmxExitApicAccess,
496	/* 45 UNDEFINED */ hmR0VmxExitErrUndefined,
497	/* 46 VMX_EXIT_XDTR_ACCESS */ hmR0VmxExitXdtrAccess,
498	/* 47 VMX_EXIT_TR_ACCESS */ hmR0VmxExitXdtrAccess,
499	/* 48 VMX_EXIT_EPT_VIOLATION */ hmR0VmxExitEptViolation,
500	/* 49 VMX_EXIT_EPT_MISCONFIG */ hmR0VmxExitEptMisconfig,
501	/* 50 VMX_EXIT_INVEPT */ hmR0VmxExitSetPendingXcptUD,
502	/* 51 VMX_EXIT_RDTSCP */ hmR0VmxExitRdtscp,
503	/* 52 VMX_EXIT_PREEMPT_TIMER */ hmR0VmxExitPreemptTimer,
504	/* 53 VMX_EXIT_INVVPID */ hmR0VmxExitSetPendingXcptUD,
505	/* 54 VMX_EXIT_WBINVD */ hmR0VmxExitWbinvd,
506	/* 55 VMX_EXIT_XSETBV */ hmR0VmxExitXsetbv,
507	/* 56 VMX_EXIT_APIC_WRITE */ hmR0VmxExitErrUndefined,
508	/* 57 VMX_EXIT_RDRAND */ hmR0VmxExitRdrand,
509	/* 58 VMX_EXIT_INVPCID */ hmR0VmxExitInvpcid,
510	/* 59 VMX_EXIT_VMFUNC */ hmR0VmxExitSetPendingXcptUD,
511	/* 60 VMX_EXIT_ENCLS */ hmR0VmxExitErrUndefined,
512	/* 61 VMX_EXIT_RDSEED / hmR0VmxExitErrUndefined, / only spurious exits, so undefined */
513	/* 62 VMX_EXIT_PML_FULL */ hmR0VmxExitErrUndefined,
514	/* 63 VMX_EXIT_XSAVES */ hmR0VmxExitSetPendingXcptUD,
515	/* 64 VMX_EXIT_XRSTORS */ hmR0VmxExitSetPendingXcptUD,
516	};
517	#endif /* HMVMX_USE_FUNCTION_TABLE */
518
519	#ifdef VBOX_STRICT
520	static const char * const g_apszVmxInstrErrors[HMVMX_INSTR_ERROR_MAX + 1] =
521	{
522	/* 0 */ "(Not Used)",
523	/* 1 */ "VMCALL executed in VMX root operation.",
524	/* 2 */ "VMCLEAR with invalid physical address.",
525	/* 3 */ "VMCLEAR with VMXON pointer.",
526	/* 4 */ "VMLAUNCH with non-clear VMCS.",
527	/* 5 */ "VMRESUME with non-launched VMCS.",
528	/* 6 */ "VMRESUME after VMXOFF",
529	/* 7 */ "VM-entry with invalid control fields.",
530	/* 8 */ "VM-entry with invalid host state fields.",
531	/* 9 */ "VMPTRLD with invalid physical address.",
532	/* 10 */ "VMPTRLD with VMXON pointer.",
533	/* 11 */ "VMPTRLD with incorrect revision identifier.",
534	/* 12 */ "VMREAD/VMWRITE from/to unsupported VMCS component.",
535	/* 13 */ "VMWRITE to read-only VMCS component.",
536	/* 14 */ "(Not Used)",
537	/* 15 */ "VMXON executed in VMX root operation.",
538	/* 16 */ "VM-entry with invalid executive-VMCS pointer.",
539	/* 17 */ "VM-entry with non-launched executing VMCS.",
540	/* 18 */ "VM-entry with executive-VMCS pointer not VMXON pointer.",
541	/* 19 */ "VMCALL with non-clear VMCS.",
542	/* 20 */ "VMCALL with invalid VM-exit control fields.",
543	/* 21 */ "(Not Used)",
544	/* 22 */ "VMCALL with incorrect MSEG revision identifier.",
545	/* 23 */ "VMXOFF under dual monitor treatment of SMIs and SMM.",
546	/* 24 */ "VMCALL with invalid SMM-monitor features.",
547	/* 25 */ "VM-entry with invalid VM-execution control fields in executive VMCS.",
548	/* 26 */ "VM-entry with events blocked by MOV SS.",
549	/* 27 */ "(Not Used)",
550	/* 28 */ "Invalid operand to INVEPT/INVVPID."
551	};
552	#endif /* VBOX_STRICT */
553
554
555
556	/**
557	* Updates the VM's last error record.
558	*
559	* If there was a VMX instruction error, reads the error data from the VMCS and
560	* updates VCPU's last error record as well.
561	*
562	* @param pVM The cross context VM structure.
563	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
564	* Can be NULL if @a rc is not VERR_VMX_UNABLE_TO_START_VM or
565	* VERR_VMX_INVALID_VMCS_FIELD.
566	* @param rc The error code.
567	*/
568	static void hmR0VmxUpdateErrorRecord(PVM pVM, PVMCPU pVCpu, int rc)
569	{
570	AssertPtr(pVM);
571	if ( rc == VERR_VMX_INVALID_VMCS_FIELD
572	\|\| rc == VERR_VMX_UNABLE_TO_START_VM)
573	{
574	AssertPtrReturnVoid(pVCpu);
575	VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError);
576	}
577	pVM->hm.s.lLastError = rc;
578	}
579
580
581	/**
582	* Reads the VM-entry interruption-information field from the VMCS into the VMX
583	* transient structure.
584	*
585	* @returns VBox status code.
586	* @param pVmxTransient Pointer to the VMX transient structure.
587	*
588	* @remarks No-long-jump zone!!!
589	*/
590	DECLINLINE(int) hmR0VmxReadEntryIntInfoVmcs(PVMXTRANSIENT pVmxTransient)
591	{
592	int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &pVmxTransient->uEntryIntInfo);
593	AssertRCReturn(rc, rc);
594	return VINF_SUCCESS;
595	}
596
597
598	#ifdef VBOX_STRICT
599	/**
600	* Reads the VM-entry exception error code field from the VMCS into
601	* the VMX transient structure.
602	*
603	* @returns VBox status code.
604	* @param pVmxTransient Pointer to the VMX transient structure.
605	*
606	* @remarks No-long-jump zone!!!
607	*/
608	DECLINLINE(int) hmR0VmxReadEntryXcptErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
609	{
610	int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, &pVmxTransient->uEntryXcptErrorCode);
611	AssertRCReturn(rc, rc);
612	return VINF_SUCCESS;
613	}
614	#endif /* VBOX_STRICT */
615
616
617	#ifdef VBOX_STRICT
618	/**
619	* Reads the VM-entry exception error code field from the VMCS into
620	* the VMX transient structure.
621	*
622	* @returns VBox status code.
623	* @param pVmxTransient Pointer to the VMX transient structure.
624	*
625	* @remarks No-long-jump zone!!!
626	*/
627	DECLINLINE(int) hmR0VmxReadEntryInstrLenVmcs(PVMXTRANSIENT pVmxTransient)
628	{
629	int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, &pVmxTransient->cbEntryInstr);
630	AssertRCReturn(rc, rc);
631	return VINF_SUCCESS;
632	}
633	#endif /* VBOX_STRICT */
634
635
636	/**
637	* Reads the VM-exit interruption-information field from the VMCS into the VMX
638	* transient structure.
639	*
640	* @returns VBox status code.
641	* @param pVmxTransient Pointer to the VMX transient structure.
642	*/
643	DECLINLINE(int) hmR0VmxReadExitIntInfoVmcs(PVMXTRANSIENT pVmxTransient)
644	{
645	if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO))
646	{
647	int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO, &pVmxTransient->uExitIntInfo);
648	AssertRCReturn(rc, rc);
649	pVmxTransient->fVmcsFieldsRead \|= HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO;
650	}
651	return VINF_SUCCESS;
652	}
653
654
655	/**
656	* Reads the VM-exit interruption error code from the VMCS into the VMX
657	* transient structure.
658	*
659	* @returns VBox status code.
660	* @param pVmxTransient Pointer to the VMX transient structure.
661	*/
662	DECLINLINE(int) hmR0VmxReadExitIntErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
663	{
664	if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_ERROR_CODE))
665	{
666	int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE, &pVmxTransient->uExitIntErrorCode);
667	AssertRCReturn(rc, rc);
668	pVmxTransient->fVmcsFieldsRead \|= HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_ERROR_CODE;
669	}
670	return VINF_SUCCESS;
671	}
672
673
674	/**
675	* Reads the VM-exit instruction length field from the VMCS into the VMX
676	* transient structure.
677	*
678	* @returns VBox status code.
679	* @param pVmxTransient Pointer to the VMX transient structure.
680	*/
681	DECLINLINE(int) hmR0VmxReadExitInstrLenVmcs(PVMXTRANSIENT pVmxTransient)
682	{
683	if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_LEN))
684	{
685	int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_LENGTH, &pVmxTransient->cbInstr);
686	AssertRCReturn(rc, rc);
687	pVmxTransient->fVmcsFieldsRead \|= HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_LEN;
688	}
689	return VINF_SUCCESS;
690	}
691
692
693	/**
694	* Reads the VM-exit instruction-information field from the VMCS into
695	* the VMX transient structure.
696	*
697	* @returns VBox status code.
698	* @param pVmxTransient Pointer to the VMX transient structure.
699	*/
700	DECLINLINE(int) hmR0VmxReadExitInstrInfoVmcs(PVMXTRANSIENT pVmxTransient)
701	{
702	if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_INFO))
703	{
704	int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_INSTR_INFO, &pVmxTransient->ExitInstrInfo.u);
705	AssertRCReturn(rc, rc);
706	pVmxTransient->fVmcsFieldsRead \|= HMVMX_UPDATED_TRANSIENT_EXIT_INSTR_INFO;
707	}
708	return VINF_SUCCESS;
709	}
710
711
712	/**
713	* Reads the exit code qualification from the VMCS into the VMX transient
714	* structure.
715	*
716	* @returns VBox status code.
717	* @param pVCpu The cross context virtual CPU structure of the
718	* calling EMT. (Required for the VMCS cache case.)
719	* @param pVmxTransient Pointer to the VMX transient structure.
720	*/
721	DECLINLINE(int) hmR0VmxReadExitQualificationVmcs(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
722	{
723	if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_QUALIFICATION))
724	{
725	int rc = VMXReadVmcsGstN(VMX_VMCS_RO_EXIT_QUALIFICATION, &pVmxTransient->uExitQualification); NOREF(pVCpu);
726	AssertRCReturn(rc, rc);
727	pVmxTransient->fVmcsFieldsRead \|= HMVMX_UPDATED_TRANSIENT_EXIT_QUALIFICATION;
728	}
729	return VINF_SUCCESS;
730	}
731
732
733	/**
734	* Reads the IDT-vectoring information field from the VMCS into the VMX
735	* transient structure.
736	*
737	* @returns VBox status code.
738	* @param pVmxTransient Pointer to the VMX transient structure.
739	*
740	* @remarks No-long-jump zone!!!
741	*/
742	DECLINLINE(int) hmR0VmxReadIdtVectoringInfoVmcs(PVMXTRANSIENT pVmxTransient)
743	{
744	if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_INFO))
745	{
746	int rc = VMXReadVmcs32(VMX_VMCS32_RO_IDT_INFO, &pVmxTransient->uIdtVectoringInfo);
747	AssertRCReturn(rc, rc);
748	pVmxTransient->fVmcsFieldsRead \|= HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_INFO;
749	}
750	return VINF_SUCCESS;
751	}
752
753
754	/**
755	* Reads the IDT-vectoring error code from the VMCS into the VMX
756	* transient structure.
757	*
758	* @returns VBox status code.
759	* @param pVmxTransient Pointer to the VMX transient structure.
760	*/
761	DECLINLINE(int) hmR0VmxReadIdtVectoringErrorCodeVmcs(PVMXTRANSIENT pVmxTransient)
762	{
763	if (!(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_ERROR_CODE))
764	{
765	int rc = VMXReadVmcs32(VMX_VMCS32_RO_IDT_ERROR_CODE, &pVmxTransient->uIdtVectoringErrorCode);
766	AssertRCReturn(rc, rc);
767	pVmxTransient->fVmcsFieldsRead \|= HMVMX_UPDATED_TRANSIENT_IDT_VECTORING_ERROR_CODE;
768	}
769	return VINF_SUCCESS;
770	}
771
772
773	/**
774	* Enters VMX root mode operation on the current CPU.
775	*
776	* @returns VBox status code.
777	* @param pVM The cross context VM structure. Can be
778	* NULL, after a resume.
779	* @param HCPhysCpuPage Physical address of the VMXON region.
780	* @param pvCpuPage Pointer to the VMXON region.
781	*/
782	static int hmR0VmxEnterRootMode(PVM pVM, RTHCPHYS HCPhysCpuPage, void *pvCpuPage)
783	{
784	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
785	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
786	Assert(pvCpuPage);
787	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
788
789	if (pVM)
790	{
791	/* Write the VMCS revision dword to the VMXON region. */
792	(uint32_t )pvCpuPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo);
793	}
794
795	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with CR4. */
796	RTCCUINTREG fEFlags = ASMIntDisableFlags();
797
798	/* Enable the VMX bit in CR4 if necessary. */
799	RTCCUINTREG uOldCr4 = SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
800
801	/* Enter VMX root mode. */
802	int rc = VMXEnable(HCPhysCpuPage);
803	if (RT_FAILURE(rc))
804	{
805	if (!(uOldCr4 & X86_CR4_VMXE))
806	SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
807
808	if (pVM)
809	pVM->hm.s.vmx.HCPhysVmxEnableError = HCPhysCpuPage;
810	}
811
812	/* Restore interrupts. */
813	ASMSetFlags(fEFlags);
814	return rc;
815	}
816
817
818	/**
819	* Exits VMX root mode operation on the current CPU.
820	*
821	* @returns VBox status code.
822	*/
823	static int hmR0VmxLeaveRootMode(void)
824	{
825	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
826
827	/* Paranoid: Disable interrupts as, in theory, interrupts handlers might mess with CR4. */
828	RTCCUINTREG fEFlags = ASMIntDisableFlags();
829
830	/* If we're for some reason not in VMX root mode, then don't leave it. */
831	RTCCUINTREG uHostCR4 = ASMGetCR4();
832
833	int rc;
834	if (uHostCR4 & X86_CR4_VMXE)
835	{
836	/* Exit VMX root mode and clear the VMX bit in CR4. */
837	VMXDisable();
838	SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
839	rc = VINF_SUCCESS;
840	}
841	else
842	rc = VERR_VMX_NOT_IN_VMX_ROOT_MODE;
843
844	/* Restore interrupts. */
845	ASMSetFlags(fEFlags);
846	return rc;
847	}
848
849
850	/**
851	* Allocates and maps one physically contiguous page. The allocated page is
852	* zero'd out. (Used by various VT-x structures).
853	*
854	* @returns IPRT status code.
855	* @param pMemObj Pointer to the ring-0 memory object.
856	* @param ppVirt Where to store the virtual address of the
857	* allocation.
858	* @param pHCPhys Where to store the physical address of the
859	* allocation.
860	*/
861	DECLINLINE(int) hmR0VmxPageAllocZ(PRTR0MEMOBJ pMemObj, PRTR0PTR ppVirt, PRTHCPHYS pHCPhys)
862	{
863	AssertPtrReturn(pMemObj, VERR_INVALID_PARAMETER);
864	AssertPtrReturn(ppVirt, VERR_INVALID_PARAMETER);
865	AssertPtrReturn(pHCPhys, VERR_INVALID_PARAMETER);
866
867	int rc = RTR0MemObjAllocCont(pMemObj, PAGE_SIZE, false /* fExecutable */);
868	if (RT_FAILURE(rc))
869	return rc;
870	ppVirt = RTR0MemObjAddress(pMemObj);
871	pHCPhys = RTR0MemObjGetPagePhysAddr(pMemObj, 0 /* iPage */);
872	ASMMemZero32(*ppVirt, PAGE_SIZE);
873	return VINF_SUCCESS;
874	}
875
876
877	/**
878	* Frees and unmaps an allocated physical page.
879	*
880	* @param pMemObj Pointer to the ring-0 memory object.
881	* @param ppVirt Where to re-initialize the virtual address of
882	* allocation as 0.
883	* @param pHCPhys Where to re-initialize the physical address of the
884	* allocation as 0.
885	*/
886	DECLINLINE(void) hmR0VmxPageFree(PRTR0MEMOBJ pMemObj, PRTR0PTR ppVirt, PRTHCPHYS pHCPhys)
887	{
888	AssertPtr(pMemObj);
889	AssertPtr(ppVirt);
890	AssertPtr(pHCPhys);
891	if (*pMemObj != NIL_RTR0MEMOBJ)
892	{
893	int rc = RTR0MemObjFree(pMemObj, true / fFreeMappings */);
894	AssertRC(rc);
895	*pMemObj = NIL_RTR0MEMOBJ;
896	*ppVirt = 0;
897	*pHCPhys = 0;
898	}
899	}
900
901
902	/**
903	* Worker function to free VT-x related structures.
904	*
905	* @returns IPRT status code.
906	* @param pVM The cross context VM structure.
907	*/
908	static void hmR0VmxStructsFree(PVM pVM)
909	{
910	for (VMCPUID i = 0; i < pVM->cCpus; i++)
911	{
912	PVMCPU pVCpu = &pVM->aCpus[i];
913	AssertPtr(pVCpu);
914
915	hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjHostMsr, &pVCpu->hm.s.vmx.pvHostMsr, &pVCpu->hm.s.vmx.HCPhysHostMsr);
916	hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjGuestMsr, &pVCpu->hm.s.vmx.pvGuestMsr, &pVCpu->hm.s.vmx.HCPhysGuestMsr);
917
918	if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
919	hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjMsrBitmap, &pVCpu->hm.s.vmx.pvMsrBitmap, &pVCpu->hm.s.vmx.HCPhysMsrBitmap);
920
921	hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjVmcs, &pVCpu->hm.s.vmx.pvVmcs, &pVCpu->hm.s.vmx.HCPhysVmcs);
922	}
923
924	hmR0VmxPageFree(&pVM->hm.s.vmx.hMemObjApicAccess, (PRTR0PTR)&pVM->hm.s.vmx.pbApicAccess, &pVM->hm.s.vmx.HCPhysApicAccess);
925	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
926	hmR0VmxPageFree(&pVM->hm.s.vmx.hMemObjScratch, &pVM->hm.s.vmx.pbScratch, &pVM->hm.s.vmx.HCPhysScratch);
927	#endif
928	}
929
930
931	/**
932	* Worker function to allocate VT-x related VM structures.
933	*
934	* @returns IPRT status code.
935	* @param pVM The cross context VM structure.
936	*/
937	static int hmR0VmxStructsAlloc(PVM pVM)
938	{
939	/*
940	* Initialize members up-front so we can cleanup properly on allocation failure.
941	*/
942	#define VMXLOCAL_INIT_VM_MEMOBJ(a_Name, a_VirtPrefix) \
943	pVM->hm.s.vmx.hMemObj##a_Name = NIL_RTR0MEMOBJ; \
944	pVM->hm.s.vmx.a_VirtPrefix##a_Name = 0; \
945	pVM->hm.s.vmx.HCPhys##a_Name = 0;
946
947	#define VMXLOCAL_INIT_VMCPU_MEMOBJ(a_Name, a_VirtPrefix) \
948	pVCpu->hm.s.vmx.hMemObj##a_Name = NIL_RTR0MEMOBJ; \
949	pVCpu->hm.s.vmx.a_VirtPrefix##a_Name = 0; \
950	pVCpu->hm.s.vmx.HCPhys##a_Name = 0;
951
952	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
953	VMXLOCAL_INIT_VM_MEMOBJ(Scratch, pv);
954	#endif
955	VMXLOCAL_INIT_VM_MEMOBJ(ApicAccess, pb);
956
957	AssertCompile(sizeof(VMCPUID) == sizeof(pVM->cCpus));
958	for (VMCPUID i = 0; i < pVM->cCpus; i++)
959	{
960	PVMCPU pVCpu = &pVM->aCpus[i];
961	VMXLOCAL_INIT_VMCPU_MEMOBJ(Vmcs, pv);
962	VMXLOCAL_INIT_VMCPU_MEMOBJ(MsrBitmap, pv);
963	VMXLOCAL_INIT_VMCPU_MEMOBJ(GuestMsr, pv);
964	VMXLOCAL_INIT_VMCPU_MEMOBJ(HostMsr, pv);
965	}
966	#undef VMXLOCAL_INIT_VMCPU_MEMOBJ
967	#undef VMXLOCAL_INIT_VM_MEMOBJ
968
969	/* The VMCS size cannot be more than 4096 bytes. See Intel spec. Appendix A.1 "Basic VMX Information". */
970	AssertReturnStmt(MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo) <= PAGE_SIZE,
971	(&pVM->aCpus[0])->hm.s.u32HMError = VMX_UFC_INVALID_VMCS_SIZE,
972	VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO);
973
974	/*
975	* Allocate all the VT-x structures.
976	*/
977	int rc = VINF_SUCCESS;
978	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
979	rc = hmR0VmxPageAllocZ(&pVM->hm.s.vmx.hMemObjScratch, &pVM->hm.s.vmx.pbScratch, &pVM->hm.s.vmx.HCPhysScratch);
980	if (RT_FAILURE(rc))
981	goto cleanup;
982	strcpy((char *)pVM->hm.s.vmx.pbScratch, "SCRATCH Magic");
983	(uint64_t )(pVM->hm.s.vmx.pbScratch + 16) = UINT64_C(0xdeadbeefdeadbeef);
984	#endif
985
986	/* Allocate the APIC-access page for trapping APIC accesses from the guest. */
987	if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
988	{
989	rc = hmR0VmxPageAllocZ(&pVM->hm.s.vmx.hMemObjApicAccess, (PRTR0PTR)&pVM->hm.s.vmx.pbApicAccess,
990	&pVM->hm.s.vmx.HCPhysApicAccess);
991	if (RT_FAILURE(rc))
992	goto cleanup;
993	}
994
995	/*
996	* Initialize per-VCPU VT-x structures.
997	*/
998	for (VMCPUID i = 0; i < pVM->cCpus; i++)
999	{
1000	PVMCPU pVCpu = &pVM->aCpus[i];
1001	AssertPtr(pVCpu);
1002
1003	/* Allocate the VM control structure (VMCS). */
1004	rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjVmcs, &pVCpu->hm.s.vmx.pvVmcs, &pVCpu->hm.s.vmx.HCPhysVmcs);
1005	if (RT_FAILURE(rc))
1006	goto cleanup;
1007
1008	/* Get the allocated virtual-APIC page from the APIC device for transparent TPR accesses. */
1009	if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
1010	{
1011	rc = APICGetApicPageForCpu(pVCpu, &pVCpu->hm.s.vmx.HCPhysVirtApic, (PRTR0PTR)&pVCpu->hm.s.vmx.pbVirtApic,
1012	NULL /* pR3Ptr /, NULL / pRCPtr */);
1013	if (RT_FAILURE(rc))
1014	goto cleanup;
1015	}
1016
1017	/*
1018	* Allocate the MSR-bitmap if supported by the CPU. The MSR-bitmap is for
1019	* transparent accesses of specific MSRs.
1020	*
1021	* If the condition for enabling MSR bitmaps changes here, don't forget to
1022	* update HMAreMsrBitmapsAvailable().
1023	*/
1024	if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
1025	{
1026	rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjMsrBitmap, &pVCpu->hm.s.vmx.pvMsrBitmap,
1027	&pVCpu->hm.s.vmx.HCPhysMsrBitmap);
1028	if (RT_FAILURE(rc))
1029	goto cleanup;
1030	ASMMemFill32(pVCpu->hm.s.vmx.pvMsrBitmap, PAGE_SIZE, UINT32_C(0xffffffff));
1031	}
1032
1033	/* Allocate the VM-entry MSR-load and VM-exit MSR-store page for the guest MSRs. */
1034	rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjGuestMsr, &pVCpu->hm.s.vmx.pvGuestMsr, &pVCpu->hm.s.vmx.HCPhysGuestMsr);
1035	if (RT_FAILURE(rc))
1036	goto cleanup;
1037
1038	/* Allocate the VM-exit MSR-load page for the host MSRs. */
1039	rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjHostMsr, &pVCpu->hm.s.vmx.pvHostMsr, &pVCpu->hm.s.vmx.HCPhysHostMsr);
1040	if (RT_FAILURE(rc))
1041	goto cleanup;
1042	}
1043
1044	return VINF_SUCCESS;
1045
1046	cleanup:
1047	hmR0VmxStructsFree(pVM);
1048	return rc;
1049	}
1050
1051
1052	/**
1053	* Does global VT-x initialization (called during module initialization).
1054	*
1055	* @returns VBox status code.
1056	*/
1057	VMMR0DECL(int) VMXR0GlobalInit(void)
1058	{
1059	#ifdef HMVMX_USE_FUNCTION_TABLE
1060	AssertCompile(VMX_EXIT_MAX + 1 == RT_ELEMENTS(g_apfnVMExitHandlers));
1061	# ifdef VBOX_STRICT
1062	for (unsigned i = 0; i < RT_ELEMENTS(g_apfnVMExitHandlers); i++)
1063	Assert(g_apfnVMExitHandlers[i]);
1064	# endif
1065	#endif
1066	return VINF_SUCCESS;
1067	}
1068
1069
1070	/**
1071	* Does global VT-x termination (called during module termination).
1072	*/
1073	VMMR0DECL(void) VMXR0GlobalTerm()
1074	{
1075	/* Nothing to do currently. */
1076	}
1077
1078
1079	/**
1080	* Sets up and activates VT-x on the current CPU.
1081	*
1082	* @returns VBox status code.
1083	* @param pCpu Pointer to the global CPU info struct.
1084	* @param pVM The cross context VM structure. Can be
1085	* NULL after a host resume operation.
1086	* @param pvCpuPage Pointer to the VMXON region (can be NULL if @a
1087	* fEnabledByHost is @c true).
1088	* @param HCPhysCpuPage Physical address of the VMXON region (can be 0 if
1089	* @a fEnabledByHost is @c true).
1090	* @param fEnabledByHost Set if SUPR0EnableVTx() or similar was used to
1091	* enable VT-x on the host.
1092	* @param pvMsrs Opaque pointer to VMXMSRS struct.
1093	*/
1094	VMMR0DECL(int) VMXR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
1095	void *pvMsrs)
1096	{
1097	Assert(pCpu);
1098	Assert(pvMsrs);
1099	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1100
1101	/* Enable VT-x if it's not already enabled by the host. */
1102	if (!fEnabledByHost)
1103	{
1104	int rc = hmR0VmxEnterRootMode(pVM, HCPhysCpuPage, pvCpuPage);
1105	if (RT_FAILURE(rc))
1106	return rc;
1107	}
1108
1109	/*
1110	* Flush all EPT tagged-TLB entries (in case VirtualBox or any other hypervisor have been using EPTPs) so
1111	* we don't retain any stale guest-physical mappings which won't get invalidated when flushing by VPID.
1112	*/
1113	PVMXMSRS pMsrs = (PVMXMSRS)pvMsrs;
1114	if (pMsrs->u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
1115	{
1116	hmR0VmxFlushEpt(NULL /* pVCpu */, VMXFLUSHEPT_ALL_CONTEXTS);
1117	pCpu->fFlushAsidBeforeUse = false;
1118	}
1119	else
1120	pCpu->fFlushAsidBeforeUse = true;
1121
1122	/* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}. */
1123	++pCpu->cTlbFlushes;
1124
1125	return VINF_SUCCESS;
1126	}
1127
1128
1129	/**
1130	* Deactivates VT-x on the current CPU.
1131	*
1132	* @returns VBox status code.
1133	* @param pCpu Pointer to the global CPU info struct.
1134	* @param pvCpuPage Pointer to the VMXON region.
1135	* @param HCPhysCpuPage Physical address of the VMXON region.
1136	*
1137	* @remarks This function should never be called when SUPR0EnableVTx() or
1138	* similar was used to enable VT-x on the host.
1139	*/
1140	VMMR0DECL(int) VMXR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
1141	{
1142	NOREF(pCpu);
1143	NOREF(pvCpuPage);
1144	NOREF(HCPhysCpuPage);
1145
1146	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1147	return hmR0VmxLeaveRootMode();
1148	}
1149
1150
1151	/**
1152	* Sets the permission bits for the specified MSR in the MSR bitmap.
1153	*
1154	* @param pVCpu The cross context virtual CPU structure.
1155	* @param uMsr The MSR value.
1156	* @param enmRead Whether reading this MSR causes a VM-exit.
1157	* @param enmWrite Whether writing this MSR causes a VM-exit.
1158	*/
1159	static void hmR0VmxSetMsrPermission(PVMCPU pVCpu, uint32_t uMsr, VMXMSREXITREAD enmRead, VMXMSREXITWRITE enmWrite)
1160	{
1161	int32_t iBit;
1162	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.vmx.pvMsrBitmap;
1163
1164	/*
1165	* Layout:
1166	* 0x000 - 0x3ff - Low MSR read bits
1167	* 0x400 - 0x7ff - High MSR read bits
1168	* 0x800 - 0xbff - Low MSR write bits
1169	* 0xc00 - 0xfff - High MSR write bits
1170	*/
1171	if (uMsr <= 0x00001FFF)
1172	iBit = uMsr;
1173	else if (uMsr - UINT32_C(0xC0000000) <= UINT32_C(0x00001FFF))
1174	{
1175	iBit = uMsr - UINT32_C(0xC0000000);
1176	pbMsrBitmap += 0x400;
1177	}
1178	else
1179	AssertMsgFailedReturnVoid(("hmR0VmxSetMsrPermission: Invalid MSR %#RX32\n", uMsr));
1180
1181	Assert(iBit <= 0x1fff);
1182	if (enmRead == VMXMSREXIT_INTERCEPT_READ)
1183	ASMBitSet(pbMsrBitmap, iBit);
1184	else
1185	ASMBitClear(pbMsrBitmap, iBit);
1186
1187	if (enmWrite == VMXMSREXIT_INTERCEPT_WRITE)
1188	ASMBitSet(pbMsrBitmap + 0x800, iBit);
1189	else
1190	ASMBitClear(pbMsrBitmap + 0x800, iBit);
1191	}
1192
1193
1194	#ifdef VBOX_STRICT
1195	/**
1196	* Gets the permission bits for the specified MSR in the MSR bitmap.
1197	*
1198	* @returns VBox status code.
1199	* @retval VINF_SUCCESS if the specified MSR is found.
1200	* @retval VERR_NOT_FOUND if the specified MSR is not found.
1201	* @retval VERR_NOT_SUPPORTED if VT-x doesn't allow the MSR.
1202	*
1203	* @param pVCpu The cross context virtual CPU structure.
1204	* @param uMsr The MSR.
1205	* @param penmRead Where to store the read permissions.
1206	* @param penmWrite Where to store the write permissions.
1207	*/
1208	static int hmR0VmxGetMsrPermission(PVMCPU pVCpu, uint32_t uMsr, PVMXMSREXITREAD penmRead, PVMXMSREXITWRITE penmWrite)
1209	{
1210	AssertPtrReturn(penmRead, VERR_INVALID_PARAMETER);
1211	AssertPtrReturn(penmWrite, VERR_INVALID_PARAMETER);
1212	int32_t iBit;
1213	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.vmx.pvMsrBitmap;
1214
1215	/* See hmR0VmxSetMsrPermission() for the layout. */
1216	if (uMsr <= 0x00001FFF)
1217	iBit = uMsr;
1218	else if ( uMsr >= 0xC0000000
1219	&& uMsr <= 0xC0001FFF)
1220	{
1221	iBit = (uMsr - 0xC0000000);
1222	pbMsrBitmap += 0x400;
1223	}
1224	else
1225	AssertMsgFailedReturn(("hmR0VmxGetMsrPermission: Invalid MSR %#RX32\n", uMsr), VERR_NOT_SUPPORTED);
1226
1227	Assert(iBit <= 0x1fff);
1228	if (ASMBitTest(pbMsrBitmap, iBit))
1229	*penmRead = VMXMSREXIT_INTERCEPT_READ;
1230	else
1231	*penmRead = VMXMSREXIT_PASSTHRU_READ;
1232
1233	if (ASMBitTest(pbMsrBitmap + 0x800, iBit))
1234	*penmWrite = VMXMSREXIT_INTERCEPT_WRITE;
1235	else
1236	*penmWrite = VMXMSREXIT_PASSTHRU_WRITE;
1237	return VINF_SUCCESS;
1238	}
1239	#endif /* VBOX_STRICT */
1240
1241
1242	/**
1243	* Updates the VMCS with the number of effective MSRs in the auto-load/store MSR
1244	* area.
1245	*
1246	* @returns VBox status code.
1247	* @param pVCpu The cross context virtual CPU structure.
1248	* @param cMsrs The number of MSRs.
1249	*/
1250	DECLINLINE(int) hmR0VmxSetAutoLoadStoreMsrCount(PVMCPU pVCpu, uint32_t cMsrs)
1251	{
1252	/* Shouldn't ever happen but there -is- a number. We're well within the recommended 512. */
1253	uint32_t const cMaxSupportedMsrs = MSR_IA32_VMX_MISC_MAX_MSR(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.u64Misc);
1254	if (RT_UNLIKELY(cMsrs > cMaxSupportedMsrs))
1255	{
1256	LogRel(("CPU auto-load/store MSR count in VMCS exceeded cMsrs=%u Supported=%u.\n", cMsrs, cMaxSupportedMsrs));
1257	pVCpu->hm.s.u32HMError = VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE;
1258	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
1259	}
1260
1261	/* Update number of guest MSRs to load/store across the world-switch. */
1262	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, cMsrs);
1263	rc \|= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, cMsrs);
1264
1265	/* Update number of host MSRs to load after the world-switch. Identical to guest-MSR count as it's always paired. */
1266	rc \|= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, cMsrs);
1267	AssertRCReturn(rc, rc);
1268
1269	/* Update the VCPU's copy of the MSR count. */
1270	pVCpu->hm.s.vmx.cMsrs = cMsrs;
1271
1272	return VINF_SUCCESS;
1273	}
1274
1275
1276	/**
1277	* Adds a new (or updates the value of an existing) guest/host MSR
1278	* pair to be swapped during the world-switch as part of the
1279	* auto-load/store MSR area in the VMCS.
1280	*
1281	* @returns VBox status code.
1282	* @param pVCpu The cross context virtual CPU structure.
1283	* @param uMsr The MSR.
1284	* @param uGuestMsrValue Value of the guest MSR.
1285	* @param fUpdateHostMsr Whether to update the value of the host MSR if
1286	* necessary.
1287	* @param pfAddedAndUpdated Where to store whether the MSR was added -and-
1288	* its value was updated. Optional, can be NULL.
1289	*/
1290	static int hmR0VmxAddAutoLoadStoreMsr(PVMCPU pVCpu, uint32_t uMsr, uint64_t uGuestMsrValue, bool fUpdateHostMsr,
1291	bool *pfAddedAndUpdated)
1292	{
1293	PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1294	uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1295	uint32_t i;
1296	for (i = 0; i < cMsrs; i++)
1297	{
1298	if (pGuestMsr->u32Msr == uMsr)
1299	break;
1300	pGuestMsr++;
1301	}
1302
1303	bool fAdded = false;
1304	if (i == cMsrs)
1305	{
1306	++cMsrs;
1307	int rc = hmR0VmxSetAutoLoadStoreMsrCount(pVCpu, cMsrs);
1308	AssertMsgRCReturn(rc, ("hmR0VmxAddAutoLoadStoreMsr: Insufficient space to add MSR %u\n", uMsr), rc);
1309
1310	/* Now that we're swapping MSRs during the world-switch, allow the guest to read/write them without causing VM-exits. */
1311	if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
1312	hmR0VmxSetMsrPermission(pVCpu, uMsr, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
1313
1314	fAdded = true;
1315	}
1316
1317	/* Update the MSR values in the auto-load/store MSR area. */
1318	pGuestMsr->u32Msr = uMsr;
1319	pGuestMsr->u64Value = uGuestMsrValue;
1320
1321	/* Create/update the MSR slot in the host MSR area. */
1322	PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1323	pHostMsr += i;
1324	pHostMsr->u32Msr = uMsr;
1325
1326	/*
1327	* Update the host MSR only when requested by the caller AND when we're
1328	* adding it to the auto-load/store area. Otherwise, it would have been
1329	* updated by hmR0VmxSaveHostMsrs(). We do this for performance reasons.
1330	*/
1331	bool fUpdatedMsrValue = false;
1332	if ( fAdded
1333	&& fUpdateHostMsr)
1334	{
1335	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1336	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1337	pHostMsr->u64Value = ASMRdMsr(pHostMsr->u32Msr);
1338	fUpdatedMsrValue = true;
1339	}
1340
1341	if (pfAddedAndUpdated)
1342	*pfAddedAndUpdated = fUpdatedMsrValue;
1343	return VINF_SUCCESS;
1344	}
1345
1346
1347	/**
1348	* Removes a guest/host MSR pair to be swapped during the world-switch from the
1349	* auto-load/store MSR area in the VMCS.
1350	*
1351	* @returns VBox status code.
1352	* @param pVCpu The cross context virtual CPU structure.
1353	* @param uMsr The MSR.
1354	*/
1355	static int hmR0VmxRemoveAutoLoadStoreMsr(PVMCPU pVCpu, uint32_t uMsr)
1356	{
1357	PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1358	uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1359	for (uint32_t i = 0; i < cMsrs; i++)
1360	{
1361	/* Find the MSR. */
1362	if (pGuestMsr->u32Msr == uMsr)
1363	{
1364	/* If it's the last MSR, simply reduce the count. */
1365	if (i == cMsrs - 1)
1366	{
1367	--cMsrs;
1368	break;
1369	}
1370
1371	/* Remove it by swapping the last MSR in place of it, and reducing the count. */
1372	PVMXAUTOMSR pLastGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1373	pLastGuestMsr += cMsrs - 1;
1374	pGuestMsr->u32Msr = pLastGuestMsr->u32Msr;
1375	pGuestMsr->u64Value = pLastGuestMsr->u64Value;
1376
1377	PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1378	PVMXAUTOMSR pLastHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1379	pLastHostMsr += cMsrs - 1;
1380	pHostMsr->u32Msr = pLastHostMsr->u32Msr;
1381	pHostMsr->u64Value = pLastHostMsr->u64Value;
1382	--cMsrs;
1383	break;
1384	}
1385	pGuestMsr++;
1386	}
1387
1388	/* Update the VMCS if the count changed (meaning the MSR was found). */
1389	if (cMsrs != pVCpu->hm.s.vmx.cMsrs)
1390	{
1391	int rc = hmR0VmxSetAutoLoadStoreMsrCount(pVCpu, cMsrs);
1392	AssertRCReturn(rc, rc);
1393
1394	/* We're no longer swapping MSRs during the world-switch, intercept guest read/writes to them. */
1395	if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
1396	hmR0VmxSetMsrPermission(pVCpu, uMsr, VMXMSREXIT_INTERCEPT_READ, VMXMSREXIT_INTERCEPT_WRITE);
1397
1398	Log4(("Removed MSR %#RX32 new cMsrs=%u\n", uMsr, pVCpu->hm.s.vmx.cMsrs));
1399	return VINF_SUCCESS;
1400	}
1401
1402	return VERR_NOT_FOUND;
1403	}
1404
1405
1406	/**
1407	* Checks if the specified guest MSR is part of the auto-load/store area in
1408	* the VMCS.
1409	*
1410	* @returns true if found, false otherwise.
1411	* @param pVCpu The cross context virtual CPU structure.
1412	* @param uMsr The MSR to find.
1413	*/
1414	static bool hmR0VmxIsAutoLoadStoreGuestMsr(PVMCPU pVCpu, uint32_t uMsr)
1415	{
1416	PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1417	uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1418
1419	for (uint32_t i = 0; i < cMsrs; i++, pGuestMsr++)
1420	{
1421	if (pGuestMsr->u32Msr == uMsr)
1422	return true;
1423	}
1424	return false;
1425	}
1426
1427
1428	/**
1429	* Updates the value of all host MSRs in the auto-load/store area in the VMCS.
1430	*
1431	* @param pVCpu The cross context virtual CPU structure.
1432	*
1433	* @remarks No-long-jump zone!!!
1434	*/
1435	static void hmR0VmxUpdateAutoLoadStoreHostMsrs(PVMCPU pVCpu)
1436	{
1437	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1438	PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1439	PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1440	uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
1441
1442	for (uint32_t i = 0; i < cMsrs; i++, pHostMsr++, pGuestMsr++)
1443	{
1444	AssertReturnVoid(pHostMsr->u32Msr == pGuestMsr->u32Msr);
1445
1446	/*
1447	* Performance hack for the host EFER MSR. We use the cached value rather than re-read it.
1448	* Strict builds will catch mismatches in hmR0VmxCheckAutoLoadStoreMsrs(). See @bugref{7368}.
1449	*/
1450	if (pHostMsr->u32Msr == MSR_K6_EFER)
1451	pHostMsr->u64Value = pVCpu->CTX_SUFF(pVM)->hm.s.vmx.u64HostEfer;
1452	else
1453	pHostMsr->u64Value = ASMRdMsr(pHostMsr->u32Msr);
1454	}
1455
1456	pVCpu->hm.s.vmx.fUpdatedHostMsrs = true;
1457	}
1458
1459
1460	/**
1461	* Saves a set of host MSRs to allow read/write passthru access to the guest and
1462	* perform lazy restoration of the host MSRs while leaving VT-x.
1463	*
1464	* @param pVCpu The cross context virtual CPU structure.
1465	*
1466	* @remarks No-long-jump zone!!!
1467	*/
1468	static void hmR0VmxLazySaveHostMsrs(PVMCPU pVCpu)
1469	{
1470	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1471
1472	/*
1473	* Note: If you're adding MSRs here, make sure to update the MSR-bitmap permissions in hmR0VmxSetupProcCtls().
1474	*/
1475	if (!(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST))
1476	{
1477	Assert(!(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)); /* Guest MSRs better not be loaded now. */
1478	#if HC_ARCH_BITS == 64
1479	if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1480	{
1481	pVCpu->hm.s.vmx.u64HostLStarMsr = ASMRdMsr(MSR_K8_LSTAR);
1482	pVCpu->hm.s.vmx.u64HostStarMsr = ASMRdMsr(MSR_K6_STAR);
1483	pVCpu->hm.s.vmx.u64HostSFMaskMsr = ASMRdMsr(MSR_K8_SF_MASK);
1484	pVCpu->hm.s.vmx.u64HostKernelGSBaseMsr = ASMRdMsr(MSR_K8_KERNEL_GS_BASE);
1485	}
1486	#endif
1487	pVCpu->hm.s.vmx.fLazyMsrs \|= VMX_LAZY_MSRS_SAVED_HOST;
1488	}
1489	}
1490
1491
1492	/**
1493	* Checks whether the MSR belongs to the set of guest MSRs that we restore
1494	* lazily while leaving VT-x.
1495	*
1496	* @returns true if it does, false otherwise.
1497	* @param pVCpu The cross context virtual CPU structure.
1498	* @param uMsr The MSR to check.
1499	*/
1500	static bool hmR0VmxIsLazyGuestMsr(PVMCPU pVCpu, uint32_t uMsr)
1501	{
1502	NOREF(pVCpu);
1503	#if HC_ARCH_BITS == 64
1504	if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1505	{
1506	switch (uMsr)
1507	{
1508	case MSR_K8_LSTAR:
1509	case MSR_K6_STAR:
1510	case MSR_K8_SF_MASK:
1511	case MSR_K8_KERNEL_GS_BASE:
1512	return true;
1513	}
1514	}
1515	#else
1516	RT_NOREF(pVCpu, uMsr);
1517	#endif
1518	return false;
1519	}
1520
1521
1522	/**
1523	* Saves a set of guest MSRs back into the guest-CPU context.
1524	*
1525	* @param pVCpu The cross context virtual CPU structure.
1526	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
1527	* out-of-sync. Make sure to update the required fields
1528	* before using them.
1529	*
1530	* @remarks No-long-jump zone!!!
1531	*/
1532	static void hmR0VmxLazySaveGuestMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1533	{
1534	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1535	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1536
1537	if (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
1538	{
1539	Assert(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST);
1540	#if HC_ARCH_BITS == 64
1541	if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1542	{
1543	pMixedCtx->msrLSTAR = ASMRdMsr(MSR_K8_LSTAR);
1544	pMixedCtx->msrSTAR = ASMRdMsr(MSR_K6_STAR);
1545	pMixedCtx->msrSFMASK = ASMRdMsr(MSR_K8_SF_MASK);
1546	pMixedCtx->msrKERNELGSBASE = ASMRdMsr(MSR_K8_KERNEL_GS_BASE);
1547	}
1548	#else
1549	NOREF(pMixedCtx);
1550	#endif
1551	}
1552	}
1553
1554
1555	/**
1556	* Loads a set of guests MSRs to allow read/passthru to the guest.
1557	*
1558	* The name of this function is slightly confusing. This function does NOT
1559	* postpone loading, but loads the MSR right now. "hmR0VmxLazy" is simply a
1560	* common prefix for functions dealing with "lazy restoration" of the shared
1561	* MSRs.
1562	*
1563	* @param pVCpu The cross context virtual CPU structure.
1564	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
1565	* out-of-sync. Make sure to update the required fields
1566	* before using them.
1567	*
1568	* @remarks No-long-jump zone!!!
1569	*/
1570	static void hmR0VmxLazyLoadGuestMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1571	{
1572	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1573	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1574
1575	Assert(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST);
1576	#if HC_ARCH_BITS == 64
1577	if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1578	{
1579	/*
1580	* If the guest MSRs are not loaded -and- if all the guest MSRs are identical
1581	* to the MSRs on the CPU (which are the saved host MSRs, see assertion above) then
1582	* we can skip a few MSR writes.
1583	*
1584	* Otherwise, it implies either 1. they're not loaded, or 2. they're loaded but the
1585	* guest MSR values in the guest-CPU context might be different to what's currently
1586	* loaded in the CPU. In either case, we need to write the new guest MSR values to the
1587	* CPU, see @bugref{8728}.
1588	*/
1589	if ( !(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
1590	&& pMixedCtx->msrKERNELGSBASE == pVCpu->hm.s.vmx.u64HostKernelGSBaseMsr
1591	&& pMixedCtx->msrLSTAR == pVCpu->hm.s.vmx.u64HostLStarMsr
1592	&& pMixedCtx->msrSTAR == pVCpu->hm.s.vmx.u64HostStarMsr
1593	&& pMixedCtx->msrSFMASK == pVCpu->hm.s.vmx.u64HostSFMaskMsr)
1594	{
1595	#ifdef VBOX_STRICT
1596	Assert(ASMRdMsr(MSR_K8_KERNEL_GS_BASE) == pMixedCtx->msrKERNELGSBASE);
1597	Assert(ASMRdMsr(MSR_K8_LSTAR) == pMixedCtx->msrLSTAR);
1598	Assert(ASMRdMsr(MSR_K6_STAR) == pMixedCtx->msrSTAR);
1599	Assert(ASMRdMsr(MSR_K8_SF_MASK) == pMixedCtx->msrSFMASK);
1600	#endif
1601	}
1602	else
1603	{
1604	ASMWrMsr(MSR_K8_KERNEL_GS_BASE, pMixedCtx->msrKERNELGSBASE);
1605	ASMWrMsr(MSR_K8_LSTAR, pMixedCtx->msrLSTAR);
1606	ASMWrMsr(MSR_K6_STAR, pMixedCtx->msrSTAR);
1607	ASMWrMsr(MSR_K8_SF_MASK, pMixedCtx->msrSFMASK);
1608	}
1609	}
1610	#else
1611	RT_NOREF(pMixedCtx);
1612	#endif
1613	pVCpu->hm.s.vmx.fLazyMsrs \|= VMX_LAZY_MSRS_LOADED_GUEST;
1614	}
1615
1616
1617	/**
1618	* Performs lazy restoration of the set of host MSRs if they were previously
1619	* loaded with guest MSR values.
1620	*
1621	* @param pVCpu The cross context virtual CPU structure.
1622	*
1623	* @remarks No-long-jump zone!!!
1624	* @remarks The guest MSRs should have been saved back into the guest-CPU
1625	* context by hmR0VmxSaveGuestLazyMsrs()!!!
1626	*/
1627	static void hmR0VmxLazyRestoreHostMsrs(PVMCPU pVCpu)
1628	{
1629	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1630	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1631
1632	if (pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_LOADED_GUEST)
1633	{
1634	Assert(pVCpu->hm.s.vmx.fLazyMsrs & VMX_LAZY_MSRS_SAVED_HOST);
1635	#if HC_ARCH_BITS == 64
1636	if (pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests)
1637	{
1638	ASMWrMsr(MSR_K8_LSTAR, pVCpu->hm.s.vmx.u64HostLStarMsr);
1639	ASMWrMsr(MSR_K6_STAR, pVCpu->hm.s.vmx.u64HostStarMsr);
1640	ASMWrMsr(MSR_K8_SF_MASK, pVCpu->hm.s.vmx.u64HostSFMaskMsr);
1641	ASMWrMsr(MSR_K8_KERNEL_GS_BASE, pVCpu->hm.s.vmx.u64HostKernelGSBaseMsr);
1642	}
1643	#endif
1644	}
1645	pVCpu->hm.s.vmx.fLazyMsrs &= ~(VMX_LAZY_MSRS_LOADED_GUEST \| VMX_LAZY_MSRS_SAVED_HOST);
1646	}
1647
1648
1649	/**
1650	* Verifies that our cached values of the VMCS controls are all
1651	* consistent with what's actually present in the VMCS.
1652	*
1653	* @returns VBox status code.
1654	* @param pVCpu The cross context virtual CPU structure.
1655	*/
1656	static int hmR0VmxCheckVmcsCtls(PVMCPU pVCpu)
1657	{
1658	uint32_t u32Val;
1659	int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val);
1660	AssertRCReturn(rc, rc);
1661	AssertMsgReturn(pVCpu->hm.s.vmx.u32EntryCtls == u32Val, ("Cache=%#RX32 VMCS=%#RX32", pVCpu->hm.s.vmx.u32EntryCtls, u32Val),
1662	VERR_VMX_ENTRY_CTLS_CACHE_INVALID);
1663
1664	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT, &u32Val);
1665	AssertRCReturn(rc, rc);
1666	AssertMsgReturn(pVCpu->hm.s.vmx.u32ExitCtls == u32Val, ("Cache=%#RX32 VMCS=%#RX32", pVCpu->hm.s.vmx.u32ExitCtls, u32Val),
1667	VERR_VMX_EXIT_CTLS_CACHE_INVALID);
1668
1669	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, &u32Val);
1670	AssertRCReturn(rc, rc);
1671	AssertMsgReturn(pVCpu->hm.s.vmx.u32PinCtls == u32Val, ("Cache=%#RX32 VMCS=%#RX32", pVCpu->hm.s.vmx.u32PinCtls, u32Val),
1672	VERR_VMX_PIN_EXEC_CTLS_CACHE_INVALID);
1673
1674	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, &u32Val);
1675	AssertRCReturn(rc, rc);
1676	AssertMsgReturn(pVCpu->hm.s.vmx.u32ProcCtls == u32Val, ("Cache=%#RX32 VMCS=%#RX32", pVCpu->hm.s.vmx.u32ProcCtls, u32Val),
1677	VERR_VMX_PROC_EXEC_CTLS_CACHE_INVALID);
1678
1679	if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1680	{
1681	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val);
1682	AssertRCReturn(rc, rc);
1683	AssertMsgReturn(pVCpu->hm.s.vmx.u32ProcCtls2 == u32Val,
1684	("Cache=%#RX32 VMCS=%#RX32", pVCpu->hm.s.vmx.u32ProcCtls2, u32Val),
1685	VERR_VMX_PROC_EXEC2_CTLS_CACHE_INVALID);
1686	}
1687
1688	return VINF_SUCCESS;
1689	}
1690
1691
1692	#ifdef VBOX_STRICT
1693	/**
1694	* Verifies that our cached host EFER value has not changed
1695	* since we cached it.
1696	*
1697	* @param pVCpu The cross context virtual CPU structure.
1698	*/
1699	static void hmR0VmxCheckHostEferMsr(PVMCPU pVCpu)
1700	{
1701	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1702
1703	if (pVCpu->hm.s.vmx.u32ExitCtls & VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR)
1704	{
1705	uint64_t u64Val;
1706	int rc = VMXReadVmcs64(VMX_VMCS64_HOST_EFER_FULL, &u64Val);
1707	AssertRC(rc);
1708
1709	uint64_t u64HostEferMsr = ASMRdMsr(MSR_K6_EFER);
1710	AssertMsgReturnVoid(u64HostEferMsr == u64Val, ("u64HostEferMsr=%#RX64 u64Val=%#RX64\n", u64HostEferMsr, u64Val));
1711	}
1712	}
1713
1714
1715	/**
1716	* Verifies whether the guest/host MSR pairs in the auto-load/store area in the
1717	* VMCS are correct.
1718	*
1719	* @param pVCpu The cross context virtual CPU structure.
1720	*/
1721	static void hmR0VmxCheckAutoLoadStoreMsrs(PVMCPU pVCpu)
1722	{
1723	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1724
1725	/* Verify MSR counts in the VMCS are what we think it should be. */
1726	uint32_t cMsrs;
1727	int rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, &cMsrs); AssertRC(rc);
1728	Assert(cMsrs == pVCpu->hm.s.vmx.cMsrs);
1729
1730	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, &cMsrs); AssertRC(rc);
1731	Assert(cMsrs == pVCpu->hm.s.vmx.cMsrs);
1732
1733	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, &cMsrs); AssertRC(rc);
1734	Assert(cMsrs == pVCpu->hm.s.vmx.cMsrs);
1735
1736	PVMXAUTOMSR pHostMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvHostMsr;
1737	PVMXAUTOMSR pGuestMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
1738	for (uint32_t i = 0; i < cMsrs; i++, pHostMsr++, pGuestMsr++)
1739	{
1740	/* Verify that the MSRs are paired properly and that the host MSR has the correct value. */
1741	AssertMsgReturnVoid(pHostMsr->u32Msr == pGuestMsr->u32Msr, ("HostMsr=%#RX32 GuestMsr=%#RX32 cMsrs=%u\n", pHostMsr->u32Msr,
1742	pGuestMsr->u32Msr, cMsrs));
1743
1744	uint64_t u64Msr = ASMRdMsr(pHostMsr->u32Msr);
1745	AssertMsgReturnVoid(pHostMsr->u64Value == u64Msr, ("u32Msr=%#RX32 VMCS Value=%#RX64 ASMRdMsr=%#RX64 cMsrs=%u\n",
1746	pHostMsr->u32Msr, pHostMsr->u64Value, u64Msr, cMsrs));
1747
1748	/* Verify that the permissions are as expected in the MSR bitmap. */
1749	if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
1750	{
1751	VMXMSREXITREAD enmRead;
1752	VMXMSREXITWRITE enmWrite;
1753	rc = hmR0VmxGetMsrPermission(pVCpu, pGuestMsr->u32Msr, &enmRead, &enmWrite);
1754	AssertMsgReturnVoid(rc == VINF_SUCCESS, ("hmR0VmxGetMsrPermission! failed. rc=%Rrc\n", rc));
1755	if (pGuestMsr->u32Msr == MSR_K6_EFER)
1756	{
1757	AssertMsgReturnVoid(enmRead == VMXMSREXIT_INTERCEPT_READ, ("Passthru read for EFER!?\n"));
1758	AssertMsgReturnVoid(enmWrite == VMXMSREXIT_INTERCEPT_WRITE, ("Passthru write for EFER!?\n"));
1759	}
1760	else
1761	{
1762	AssertMsgReturnVoid(enmRead == VMXMSREXIT_PASSTHRU_READ, ("u32Msr=%#RX32 cMsrs=%u No passthru read!\n",
1763	pGuestMsr->u32Msr, cMsrs));
1764	AssertMsgReturnVoid(enmWrite == VMXMSREXIT_PASSTHRU_WRITE, ("u32Msr=%#RX32 cMsrs=%u No passthru write!\n",
1765	pGuestMsr->u32Msr, cMsrs));
1766	}
1767	}
1768	}
1769	}
1770	#endif /* VBOX_STRICT */
1771
1772
1773	/**
1774	* Flushes the TLB using EPT.
1775	*
1776	* @returns VBox status code.
1777	* @param pVCpu The cross context virtual CPU structure of the calling
1778	* EMT. Can be NULL depending on @a enmFlush.
1779	* @param enmFlush Type of flush.
1780	*
1781	* @remarks Caller is responsible for making sure this function is called only
1782	* when NestedPaging is supported and providing @a enmFlush that is
1783	* supported by the CPU.
1784	* @remarks Can be called with interrupts disabled.
1785	*/
1786	static void hmR0VmxFlushEpt(PVMCPU pVCpu, VMXFLUSHEPT enmFlush)
1787	{
1788	uint64_t au64Descriptor[2];
1789	if (enmFlush == VMXFLUSHEPT_ALL_CONTEXTS)
1790	au64Descriptor[0] = 0;
1791	else
1792	{
1793	Assert(pVCpu);
1794	au64Descriptor[0] = pVCpu->hm.s.vmx.HCPhysEPTP;
1795	}
1796	au64Descriptor[1] = 0; /* MBZ. Intel spec. 33.3 "VMX Instructions" */
1797
1798	int rc = VMXR0InvEPT(enmFlush, &au64Descriptor[0]);
1799	AssertMsg(rc == VINF_SUCCESS, ("VMXR0InvEPT %#x %RGv failed with %Rrc\n", enmFlush, pVCpu ? pVCpu->hm.s.vmx.HCPhysEPTP : 0,
1800	rc));
1801	if ( RT_SUCCESS(rc)
1802	&& pVCpu)
1803	{
1804	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushNestedPaging);
1805	}
1806	}
1807
1808
1809	/**
1810	* Flushes the TLB using VPID.
1811	*
1812	* @returns VBox status code.
1813	* @param pVM The cross context VM structure.
1814	* @param pVCpu The cross context virtual CPU structure of the calling
1815	* EMT. Can be NULL depending on @a enmFlush.
1816	* @param enmFlush Type of flush.
1817	* @param GCPtr Virtual address of the page to flush (can be 0 depending
1818	* on @a enmFlush).
1819	*
1820	* @remarks Can be called with interrupts disabled.
1821	*/
1822	static void hmR0VmxFlushVpid(PVM pVM, PVMCPU pVCpu, VMXFLUSHVPID enmFlush, RTGCPTR GCPtr)
1823	{
1824	NOREF(pVM);
1825	AssertPtr(pVM);
1826	Assert(pVM->hm.s.vmx.fVpid);
1827
1828	uint64_t au64Descriptor[2];
1829	if (enmFlush == VMXFLUSHVPID_ALL_CONTEXTS)
1830	{
1831	au64Descriptor[0] = 0;
1832	au64Descriptor[1] = 0;
1833	}
1834	else
1835	{
1836	AssertPtr(pVCpu);
1837	AssertMsg(pVCpu->hm.s.uCurrentAsid != 0, ("VMXR0InvVPID: invalid ASID %lu\n", pVCpu->hm.s.uCurrentAsid));
1838	AssertMsg(pVCpu->hm.s.uCurrentAsid <= UINT16_MAX, ("VMXR0InvVPID: invalid ASID %lu\n", pVCpu->hm.s.uCurrentAsid));
1839	au64Descriptor[0] = pVCpu->hm.s.uCurrentAsid;
1840	au64Descriptor[1] = GCPtr;
1841	}
1842
1843	int rc = VMXR0InvVPID(enmFlush, &au64Descriptor[0]); NOREF(rc);
1844	AssertMsg(rc == VINF_SUCCESS,
1845	("VMXR0InvVPID %#x %u %RGv failed with %d\n", enmFlush, pVCpu ? pVCpu->hm.s.uCurrentAsid : 0, GCPtr, rc));
1846	if ( RT_SUCCESS(rc)
1847	&& pVCpu)
1848	{
1849	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1850	}
1851	}
1852
1853
1854	/**
1855	* Invalidates a guest page by guest virtual address. Only relevant for
1856	* EPT/VPID, otherwise there is nothing really to invalidate.
1857	*
1858	* @returns VBox status code.
1859	* @param pVM The cross context VM structure.
1860	* @param pVCpu The cross context virtual CPU structure.
1861	* @param GCVirt Guest virtual address of the page to invalidate.
1862	*/
1863	VMMR0DECL(int) VMXR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
1864	{
1865	AssertPtr(pVM);
1866	AssertPtr(pVCpu);
1867	LogFlowFunc(("pVM=%p pVCpu=%p GCVirt=%RGv\n", pVM, pVCpu, GCVirt));
1868
1869	bool fFlushPending = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
1870	if (!fFlushPending)
1871	{
1872	/*
1873	* We must invalidate the guest TLB entry in either case, we cannot ignore it even for the EPT case
1874	* See @bugref{6043} and @bugref{6177}.
1875	*
1876	* Set the VMCPU_FF_TLB_FLUSH force flag and flush before VM-entry in hmR0VmxFlushTLB*() as this
1877	* function maybe called in a loop with individual addresses.
1878	*/
1879	if (pVM->hm.s.vmx.fVpid)
1880	{
1881	if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
1882	{
1883	hmR0VmxFlushVpid(pVM, pVCpu, VMXFLUSHVPID_INDIV_ADDR, GCVirt);
1884	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1885	}
1886	else
1887	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1888	}
1889	else if (pVM->hm.s.fNestedPaging)
1890	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1891	}
1892
1893	return VINF_SUCCESS;
1894	}
1895
1896
1897	/**
1898	* Invalidates a guest page by physical address. Only relevant for EPT/VPID,
1899	* otherwise there is nothing really to invalidate.
1900	*
1901	* @returns VBox status code.
1902	* @param pVM The cross context VM structure.
1903	* @param pVCpu The cross context virtual CPU structure.
1904	* @param GCPhys Guest physical address of the page to invalidate.
1905	*/
1906	VMMR0DECL(int) VMXR0InvalidatePhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys)
1907	{
1908	NOREF(pVM); NOREF(GCPhys);
1909	LogFlowFunc(("%RGp\n", GCPhys));
1910
1911	/*
1912	* We cannot flush a page by guest-physical address. invvpid takes only a linear address while invept only flushes
1913	* by EPT not individual addresses. We update the force flag here and flush before the next VM-entry in hmR0VmxFlushTLB*().
1914	* This function might be called in a loop. This should cause a flush-by-EPT if EPT is in use. See @bugref{6568}.
1915	*/
1916	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1917	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgPhys);
1918	return VINF_SUCCESS;
1919	}
1920
1921
1922	/**
1923	* Dummy placeholder for tagged-TLB flush handling before VM-entry. Used in the
1924	* case where neither EPT nor VPID is supported by the CPU.
1925	*
1926	* @param pVM The cross context VM structure.
1927	* @param pVCpu The cross context virtual CPU structure.
1928	* @param pCpu Pointer to the global HM struct.
1929	*
1930	* @remarks Called with interrupts disabled.
1931	*/
1932	static void hmR0VmxFlushTaggedTlbNone(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1933	{
1934	AssertPtr(pVCpu);
1935	AssertPtr(pCpu);
1936	NOREF(pVM);
1937
1938	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH);
1939
1940	Assert(pCpu->idCpu != NIL_RTCPUID);
1941	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1942	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1943	pVCpu->hm.s.fForceTLBFlush = false;
1944	return;
1945	}
1946
1947
1948	/**
1949	* Flushes the tagged-TLB entries for EPT+VPID CPUs as necessary.
1950	*
1951	* @param pVM The cross context VM structure.
1952	* @param pVCpu The cross context virtual CPU structure.
1953	* @param pCpu Pointer to the global HM CPU struct.
1954	* @remarks All references to "ASID" in this function pertains to "VPID" in
1955	* Intel's nomenclature. The reason is, to avoid confusion in compare
1956	* statements since the host-CPU copies are named "ASID".
1957	*
1958	* @remarks Called with interrupts disabled.
1959	*/
1960	static void hmR0VmxFlushTaggedTlbBoth(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1961	{
1962	#ifdef VBOX_WITH_STATISTICS
1963	bool fTlbFlushed = false;
1964	# define HMVMX_SET_TAGGED_TLB_FLUSHED() do { fTlbFlushed = true; } while (0)
1965	# define HMVMX_UPDATE_FLUSH_SKIPPED_STAT() do { \
1966	if (!fTlbFlushed) \
1967	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch); \
1968	} while (0)
1969	#else
1970	# define HMVMX_SET_TAGGED_TLB_FLUSHED() do { } while (0)
1971	# define HMVMX_UPDATE_FLUSH_SKIPPED_STAT() do { } while (0)
1972	#endif
1973
1974	AssertPtr(pVM);
1975	AssertPtr(pCpu);
1976	AssertPtr(pVCpu);
1977	Assert(pCpu->idCpu != NIL_RTCPUID);
1978
1979	AssertMsg(pVM->hm.s.fNestedPaging && pVM->hm.s.vmx.fVpid,
1980	("hmR0VmxFlushTaggedTlbBoth cannot be invoked unless NestedPaging & VPID are enabled."
1981	"fNestedPaging=%RTbool fVpid=%RTbool", pVM->hm.s.fNestedPaging, pVM->hm.s.vmx.fVpid));
1982
1983	/*
1984	* Force a TLB flush for the first world-switch if the current CPU differs from the one we ran on last.
1985	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB
1986	* or the host CPU is online after a suspend/resume, so we cannot reuse the current ASID anymore.
1987	*/
1988	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
1989	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
1990	{
1991	++pCpu->uCurrentAsid;
1992	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1993	{
1994	pCpu->uCurrentAsid = 1; /* Wraparound to 1; host uses 0. */
1995	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
1996	pCpu->fFlushAsidBeforeUse = true; /* All VCPUs that run on this host CPU must flush their new VPID before use. */
1997	}
1998
1999	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
2000	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
2001	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
2002
2003	/*
2004	* Flush by EPT when we get rescheduled to a new host CPU to ensure EPT-only tagged mappings are also
2005	* invalidated. We don't need to flush-by-VPID here as flushing by EPT covers it. See @bugref{6568}.
2006	*/
2007	hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmFlushEpt);
2008	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
2009	HMVMX_SET_TAGGED_TLB_FLUSHED();
2010	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH); /* Already flushed-by-EPT, skip doing it again below. */
2011	}
2012
2013	/* Check for explicit TLB flushes. */
2014	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
2015	{
2016	/*
2017	* Changes to the EPT paging structure by VMM requires flushing by EPT as the CPU creates
2018	* guest-physical (only EPT-tagged) mappings while traversing the EPT tables when EPT is in use.
2019	* Flushing by VPID will only flush linear (only VPID-tagged) and combined (EPT+VPID tagged) mappings
2020	* but not guest-physical mappings.
2021	* See Intel spec. 28.3.2 "Creating and Using Cached Translation Information". See @bugref{6568}.
2022	*/
2023	hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmFlushEpt);
2024	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
2025	HMVMX_SET_TAGGED_TLB_FLUSHED();
2026	}
2027
2028	pVCpu->hm.s.fForceTLBFlush = false;
2029	HMVMX_UPDATE_FLUSH_SKIPPED_STAT();
2030
2031	Assert(pVCpu->hm.s.idLastCpu == pCpu->idCpu);
2032	Assert(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes);
2033	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
2034	("Flush count mismatch for cpu %d (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
2035	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
2036	("Cpu[%u] uCurrentAsid=%u cTlbFlushes=%u pVCpu->idLastCpu=%u pVCpu->cTlbFlushes=%u\n", pCpu->idCpu,
2037	pCpu->uCurrentAsid, pCpu->cTlbFlushes, pVCpu->hm.s.idLastCpu, pVCpu->hm.s.cTlbFlushes));
2038	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
2039	("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
2040
2041	/* Update VMCS with the VPID. */
2042	int rc = VMXWriteVmcs32(VMX_VMCS16_VPID, pVCpu->hm.s.uCurrentAsid);
2043	AssertRC(rc);
2044
2045	#undef HMVMX_SET_TAGGED_TLB_FLUSHED
2046	}
2047
2048
2049	/**
2050	* Flushes the tagged-TLB entries for EPT CPUs as necessary.
2051	*
2052	* @returns VBox status code.
2053	* @param pVM The cross context VM structure.
2054	* @param pVCpu The cross context virtual CPU structure.
2055	* @param pCpu Pointer to the global HM CPU struct.
2056	*
2057	* @remarks Called with interrupts disabled.
2058	*/
2059	static void hmR0VmxFlushTaggedTlbEpt(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
2060	{
2061	AssertPtr(pVM);
2062	AssertPtr(pVCpu);
2063	AssertPtr(pCpu);
2064	Assert(pCpu->idCpu != NIL_RTCPUID);
2065	AssertMsg(pVM->hm.s.fNestedPaging, ("hmR0VmxFlushTaggedTlbEpt cannot be invoked with NestedPaging disabled."));
2066	AssertMsg(!pVM->hm.s.vmx.fVpid, ("hmR0VmxFlushTaggedTlbEpt cannot be invoked with VPID enabled."));
2067
2068	/*
2069	* Force a TLB flush for the first world-switch if the current CPU differs from the one we ran on last.
2070	* A change in the TLB flush count implies the host CPU is online after a suspend/resume.
2071	*/
2072	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
2073	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
2074	{
2075	pVCpu->hm.s.fForceTLBFlush = true;
2076	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
2077	}
2078
2079	/* Check for explicit TLB flushes. */
2080	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
2081	{
2082	pVCpu->hm.s.fForceTLBFlush = true;
2083	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
2084	}
2085
2086	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
2087	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
2088
2089	if (pVCpu->hm.s.fForceTLBFlush)
2090	{
2091	hmR0VmxFlushEpt(pVCpu, pVM->hm.s.vmx.enmFlushEpt);
2092	pVCpu->hm.s.fForceTLBFlush = false;
2093	}
2094	}
2095
2096
2097	/**
2098	* Flushes the tagged-TLB entries for VPID CPUs as necessary.
2099	*
2100	* @returns VBox status code.
2101	* @param pVM The cross context VM structure.
2102	* @param pVCpu The cross context virtual CPU structure.
2103	* @param pCpu Pointer to the global HM CPU struct.
2104	*
2105	* @remarks Called with interrupts disabled.
2106	*/
2107	static void hmR0VmxFlushTaggedTlbVpid(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
2108	{
2109	AssertPtr(pVM);
2110	AssertPtr(pVCpu);
2111	AssertPtr(pCpu);
2112	Assert(pCpu->idCpu != NIL_RTCPUID);
2113	AssertMsg(pVM->hm.s.vmx.fVpid, ("hmR0VmxFlushTlbVpid cannot be invoked with VPID disabled."));
2114	AssertMsg(!pVM->hm.s.fNestedPaging, ("hmR0VmxFlushTlbVpid cannot be invoked with NestedPaging enabled"));
2115
2116	/*
2117	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
2118	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB
2119	* or the host CPU is online after a suspend/resume, so we cannot reuse the current ASID anymore.
2120	*/
2121	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
2122	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
2123	{
2124	pVCpu->hm.s.fForceTLBFlush = true;
2125	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
2126	}
2127
2128	/* Check for explicit TLB flushes. */
2129	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
2130	{
2131	/*
2132	* If we ever support VPID flush combinations other than ALL or SINGLE-context (see hmR0VmxSetupTaggedTlb())
2133	* we would need to explicitly flush in this case (add an fExplicitFlush = true here and change the
2134	* pCpu->fFlushAsidBeforeUse check below to include fExplicitFlush's too) - an obscure corner case.
2135	*/
2136	pVCpu->hm.s.fForceTLBFlush = true;
2137	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
2138	}
2139
2140	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
2141	if (pVCpu->hm.s.fForceTLBFlush)
2142	{
2143	++pCpu->uCurrentAsid;
2144	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
2145	{
2146	pCpu->uCurrentAsid = 1; /* Wraparound to 1; host uses 0 */
2147	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
2148	pCpu->fFlushAsidBeforeUse = true; /* All VCPUs that run on this host CPU must flush their new VPID before use. */
2149	}
2150
2151	pVCpu->hm.s.fForceTLBFlush = false;
2152	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
2153	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
2154	if (pCpu->fFlushAsidBeforeUse)
2155	{
2156	if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT)
2157	hmR0VmxFlushVpid(pVM, pVCpu, VMXFLUSHVPID_SINGLE_CONTEXT, 0 /* GCPtr */);
2158	else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_ALL_CONTEXTS)
2159	{
2160	hmR0VmxFlushVpid(pVM, pVCpu, VMXFLUSHVPID_ALL_CONTEXTS, 0 /* GCPtr */);
2161	pCpu->fFlushAsidBeforeUse = false;
2162	}
2163	else
2164	{
2165	/* hmR0VmxSetupTaggedTlb() ensures we never get here. Paranoia. */
2166	AssertMsgFailed(("Unsupported VPID-flush context type.\n"));
2167	}
2168	}
2169	}
2170
2171	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
2172	("Flush count mismatch for cpu %d (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
2173	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
2174	("Cpu[%u] uCurrentAsid=%u cTlbFlushes=%u pVCpu->idLastCpu=%u pVCpu->cTlbFlushes=%u\n", pCpu->idCpu,
2175	pCpu->uCurrentAsid, pCpu->cTlbFlushes, pVCpu->hm.s.idLastCpu, pVCpu->hm.s.cTlbFlushes));
2176	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
2177	("Cpu[%u] pVCpu->uCurrentAsid=%u\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
2178
2179	int rc = VMXWriteVmcs32(VMX_VMCS16_VPID, pVCpu->hm.s.uCurrentAsid);
2180	AssertRC(rc);
2181	}
2182
2183
2184	/**
2185	* Flushes the guest TLB entry based on CPU capabilities.
2186	*
2187	* @param pVCpu The cross context virtual CPU structure.
2188	* @param pCpu Pointer to the global HM CPU struct.
2189	*/
2190	DECLINLINE(void) hmR0VmxFlushTaggedTlb(PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
2191	{
2192	#ifdef HMVMX_ALWAYS_FLUSH_TLB
2193	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
2194	#endif
2195	PVM pVM = pVCpu->CTX_SUFF(pVM);
2196	switch (pVM->hm.s.vmx.uFlushTaggedTlb)
2197	{
2198	case HMVMX_FLUSH_TAGGED_TLB_EPT_VPID: hmR0VmxFlushTaggedTlbBoth(pVM, pVCpu, pCpu); break;
2199	case HMVMX_FLUSH_TAGGED_TLB_EPT: hmR0VmxFlushTaggedTlbEpt(pVM, pVCpu, pCpu); break;
2200	case HMVMX_FLUSH_TAGGED_TLB_VPID: hmR0VmxFlushTaggedTlbVpid(pVM, pVCpu, pCpu); break;
2201	case HMVMX_FLUSH_TAGGED_TLB_NONE: hmR0VmxFlushTaggedTlbNone(pVM, pVCpu, pCpu); break;
2202	default:
2203	AssertMsgFailed(("Invalid flush-tag function identifier\n"));
2204	break;
2205	}
2206
2207	/* Don't assert that VMCPU_FF_TLB_FLUSH should no longer be pending. It can be set by other EMTs. */
2208	}
2209
2210
2211	/**
2212	* Sets up the appropriate tagged TLB-flush level and handler for flushing guest
2213	* TLB entries from the host TLB before VM-entry.
2214	*
2215	* @returns VBox status code.
2216	* @param pVM The cross context VM structure.
2217	*/
2218	static int hmR0VmxSetupTaggedTlb(PVM pVM)
2219	{
2220	/*
2221	* Determine optimal flush type for Nested Paging.
2222	* We cannot ignore EPT if no suitable flush-types is supported by the CPU as we've already setup unrestricted
2223	* guest execution (see hmR3InitFinalizeR0()).
2224	*/
2225	if (pVM->hm.s.fNestedPaging)
2226	{
2227	if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT)
2228	{
2229	if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT)
2230	pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_SINGLE_CONTEXT;
2231	else if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
2232	pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_ALL_CONTEXTS;
2233	else
2234	{
2235	/* Shouldn't happen. EPT is supported but no suitable flush-types supported. */
2236	pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_NOT_SUPPORTED;
2237	pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED;
2238	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2239	}
2240
2241	/* Make sure the write-back cacheable memory type for EPT is supported. */
2242	if (RT_UNLIKELY(!(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB)))
2243	{
2244	pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_NOT_SUPPORTED;
2245	pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_MEM_TYPE_NOT_WB;
2246	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2247	}
2248
2249	/* EPT requires a page-walk length of 4. */
2250	if (RT_UNLIKELY(!(pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4)))
2251	{
2252	pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_NOT_SUPPORTED;
2253	pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED;
2254	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2255	}
2256	}
2257	else
2258	{
2259	/* Shouldn't happen. EPT is supported but INVEPT instruction is not supported. */
2260	pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_NOT_SUPPORTED;
2261	pVM->aCpus[0].hm.s.u32HMError = VMX_UFC_EPT_INVEPT_UNAVAILABLE;
2262	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2263	}
2264	}
2265
2266	/*
2267	* Determine optimal flush type for VPID.
2268	*/
2269	if (pVM->hm.s.vmx.fVpid)
2270	{
2271	if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID)
2272	{
2273	if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT)
2274	pVM->hm.s.vmx.enmFlushVpid = VMXFLUSHVPID_SINGLE_CONTEXT;
2275	else if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS)
2276	pVM->hm.s.vmx.enmFlushVpid = VMXFLUSHVPID_ALL_CONTEXTS;
2277	else
2278	{
2279	/* Neither SINGLE nor ALL-context flush types for VPID is supported by the CPU. Ignore VPID capability. */
2280	if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
2281	LogRel(("hmR0VmxSetupTaggedTlb: Only INDIV_ADDR supported. Ignoring VPID.\n"));
2282	if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
2283	LogRel(("hmR0VmxSetupTaggedTlb: Only SINGLE_CONTEXT_RETAIN_GLOBALS supported. Ignoring VPID.\n"));
2284	pVM->hm.s.vmx.enmFlushVpid = VMXFLUSHVPID_NOT_SUPPORTED;
2285	pVM->hm.s.vmx.fVpid = false;
2286	}
2287	}
2288	else
2289	{
2290	/* Shouldn't happen. VPID is supported but INVVPID is not supported by the CPU. Ignore VPID capability. */
2291	Log4(("hmR0VmxSetupTaggedTlb: VPID supported without INVEPT support. Ignoring VPID.\n"));
2292	pVM->hm.s.vmx.enmFlushVpid = VMXFLUSHVPID_NOT_SUPPORTED;
2293	pVM->hm.s.vmx.fVpid = false;
2294	}
2295	}
2296
2297	/*
2298	* Setup the handler for flushing tagged-TLBs.
2299	*/
2300	if (pVM->hm.s.fNestedPaging && pVM->hm.s.vmx.fVpid)
2301	pVM->hm.s.vmx.uFlushTaggedTlb = HMVMX_FLUSH_TAGGED_TLB_EPT_VPID;
2302	else if (pVM->hm.s.fNestedPaging)
2303	pVM->hm.s.vmx.uFlushTaggedTlb = HMVMX_FLUSH_TAGGED_TLB_EPT;
2304	else if (pVM->hm.s.vmx.fVpid)
2305	pVM->hm.s.vmx.uFlushTaggedTlb = HMVMX_FLUSH_TAGGED_TLB_VPID;
2306	else
2307	pVM->hm.s.vmx.uFlushTaggedTlb = HMVMX_FLUSH_TAGGED_TLB_NONE;
2308	return VINF_SUCCESS;
2309	}
2310
2311
2312	/**
2313	* Sets up pin-based VM-execution controls in the VMCS.
2314	*
2315	* @returns VBox status code.
2316	* @param pVM The cross context VM structure.
2317	* @param pVCpu The cross context virtual CPU structure.
2318	*/
2319	static int hmR0VmxSetupPinCtls(PVM pVM, PVMCPU pVCpu)
2320	{
2321	AssertPtr(pVM);
2322	AssertPtr(pVCpu);
2323
2324	uint32_t val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0; /* Bits set here must always be set. */
2325	uint32_t zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1; /* Bits cleared here must always be cleared. */
2326
2327	val \|= VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT /* External interrupts cause a VM-exit. */
2328	\| VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT; /* Non-maskable interrupts (NMIs) cause a VM-exit. */
2329
2330	if (pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI)
2331	val \|= VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI; /* Use virtual NMIs and virtual-NMI blocking features. */
2332
2333	/* Enable the VMX preemption timer. */
2334	if (pVM->hm.s.vmx.fUsePreemptTimer)
2335	{
2336	Assert(pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
2337	val \|= VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER;
2338	}
2339
2340	#if 0
2341	/* Enable posted-interrupt processing. */
2342	if (pVM->hm.s.fPostedIntrs)
2343	{
2344	Assert(pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR);
2345	Assert(pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
2346	val \|= VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR;
2347	}
2348	#endif
2349
2350	if ((val & zap) != val)
2351	{
2352	LogRel(("hmR0VmxSetupPinCtls: Invalid pin-based VM-execution controls combo! cpu=%#RX64 val=%#RX64 zap=%#RX64\n",
2353	pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0, val, zap));
2354	pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PIN_EXEC;
2355	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2356	}
2357
2358	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, val);
2359	AssertRCReturn(rc, rc);
2360
2361	pVCpu->hm.s.vmx.u32PinCtls = val;
2362	return rc;
2363	}
2364
2365
2366	/**
2367	* Sets up processor-based VM-execution controls in the VMCS.
2368	*
2369	* @returns VBox status code.
2370	* @param pVM The cross context VM structure.
2371	* @param pVCpu The cross context virtual CPU structure.
2372	*/
2373	static int hmR0VmxSetupProcCtls(PVM pVM, PVMCPU pVCpu)
2374	{
2375	AssertPtr(pVM);
2376	AssertPtr(pVCpu);
2377
2378	int rc = VERR_INTERNAL_ERROR_5;
2379	uint32_t val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0; /* Bits set here must be set in the VMCS. */
2380	uint32_t zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
2381
2382	val \|= VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT /* HLT causes a VM-exit. */
2383	\| VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING /* Use TSC-offsetting. */
2384	\| VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT /* MOV DRx causes a VM-exit. */
2385	\| VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT /* All IO instructions cause a VM-exit. */
2386	\| VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT /* RDPMC causes a VM-exit. */
2387	\| VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT /* MONITOR causes a VM-exit. */
2388	\| VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT; /* MWAIT causes a VM-exit. */
2389
2390	/* We toggle VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT later, check if it's not -always- needed to be set or clear. */
2391	if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT)
2392	\|\| (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0 & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT))
2393	{
2394	LogRel(("hmR0VmxSetupProcCtls: Unsupported VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT combo!"));
2395	pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_MOV_DRX_EXIT;
2396	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2397	}
2398
2399	/* Without Nested Paging, INVLPG (also affects INVPCID) and MOV CR3 instructions should cause VM-exits. */
2400	if (!pVM->hm.s.fNestedPaging)
2401	{
2402	Assert(!pVM->hm.s.vmx.fUnrestrictedGuest); /* Paranoia. */
2403	val \|= VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT
2404	\| VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT
2405	\| VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT;
2406	}
2407
2408	/* Use TPR shadowing if supported by the CPU. */
2409	if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
2410	{
2411	Assert(pVCpu->hm.s.vmx.HCPhysVirtApic);
2412	Assert(!(pVCpu->hm.s.vmx.HCPhysVirtApic & 0xfff)); /* Bits 11:0 MBZ. */
2413	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, 0);
2414	rc \|= VMXWriteVmcs64(VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hm.s.vmx.HCPhysVirtApic);
2415	AssertRCReturn(rc, rc);
2416
2417	val \|= VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW; /* CR8 reads from the Virtual-APIC page. */
2418	/* CR8 writes cause a VM-exit based on TPR threshold. */
2419	Assert(!(val & VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT));
2420	Assert(!(val & VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT));
2421	}
2422	else
2423	{
2424	/*
2425	* Some 32-bit CPUs do not support CR8 load/store exiting as MOV CR8 is invalid on 32-bit Intel CPUs.
2426	* Set this control only for 64-bit guests.
2427	*/
2428	if (pVM->hm.s.fAllow64BitGuests)
2429	{
2430	val \|= VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT /* CR8 reads cause a VM-exit. */
2431	\| VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT; /* CR8 writes cause a VM-exit. */
2432	}
2433	}
2434
2435	/* Use MSR-bitmaps if supported by the CPU. */
2436	if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
2437	{
2438	val \|= VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS;
2439
2440	Assert(pVCpu->hm.s.vmx.HCPhysMsrBitmap);
2441	Assert(!(pVCpu->hm.s.vmx.HCPhysMsrBitmap & 0xfff)); /* Bits 11:0 MBZ. */
2442	rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_MSR_BITMAP_FULL, pVCpu->hm.s.vmx.HCPhysMsrBitmap);
2443	AssertRCReturn(rc, rc);
2444
2445	/*
2446	* The guest can access the following MSRs (read, write) without causing VM-exits; they are loaded/stored
2447	* automatically using dedicated fields in the VMCS.
2448	*/
2449	hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2450	hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2451	hmR0VmxSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2452	hmR0VmxSetMsrPermission(pVCpu, MSR_K8_GS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2453	hmR0VmxSetMsrPermission(pVCpu, MSR_K8_FS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2454
2455	#if HC_ARCH_BITS == 64
2456	/*
2457	* Set passthru permissions for the following MSRs (mandatory for VT-x) required for 64-bit guests.
2458	*/
2459	if (pVM->hm.s.fAllow64BitGuests)
2460	{
2461	hmR0VmxSetMsrPermission(pVCpu, MSR_K8_LSTAR, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2462	hmR0VmxSetMsrPermission(pVCpu, MSR_K6_STAR, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2463	hmR0VmxSetMsrPermission(pVCpu, MSR_K8_SF_MASK, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2464	hmR0VmxSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
2465	}
2466	#endif
2467	/* Though MSR_IA32_PERF_GLOBAL_CTRL is saved/restored lazily, we want intercept reads/write to it for now. */
2468	}
2469
2470	/* Use the secondary processor-based VM-execution controls if supported by the CPU. */
2471	if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
2472	val \|= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
2473
2474	if ((val & zap) != val)
2475	{
2476	LogRel(("hmR0VmxSetupProcCtls: Invalid processor-based VM-execution controls combo! cpu=%#RX64 val=%#RX64 zap=%#RX64\n",
2477	pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0, val, zap));
2478	pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC;
2479	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2480	}
2481
2482	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, val);
2483	AssertRCReturn(rc, rc);
2484
2485	pVCpu->hm.s.vmx.u32ProcCtls = val;
2486
2487	/*
2488	* Secondary processor-based VM-execution controls.
2489	*/
2490	if (RT_LIKELY(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL))
2491	{
2492	val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0; /* Bits set here must be set in the VMCS. */
2493	zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
2494
2495	if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
2496	val \|= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT; /* WBINVD causes a VM-exit. */
2497
2498	if (pVM->hm.s.fNestedPaging)
2499	val \|= VMX_VMCS_CTRL_PROC_EXEC2_EPT; /* Enable EPT. */
2500	else
2501	{
2502	/*
2503	* Without Nested Paging, INVPCID should cause a VM-exit. Enabling this bit causes the CPU to refer to
2504	* VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT when INVPCID is executed by the guest.
2505	* See Intel spec. 25.4 "Changes to instruction behaviour in VMX non-root operation".
2506	*/
2507	if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_INVPCID)
2508	val \|= VMX_VMCS_CTRL_PROC_EXEC2_INVPCID;
2509	}
2510
2511	if (pVM->hm.s.vmx.fVpid)
2512	val \|= VMX_VMCS_CTRL_PROC_EXEC2_VPID; /* Enable VPID. */
2513
2514	if (pVM->hm.s.vmx.fUnrestrictedGuest)
2515	val \|= VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST; /* Enable Unrestricted Execution. */
2516
2517	#if 0
2518	if (pVM->hm.s.fVirtApicRegs)
2519	{
2520	Assert(pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT);
2521	val \|= VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT; /* Enable APIC-register virtualization. */
2522
2523	Assert(pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY);
2524	val \|= VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY; /* Enable virtual-interrupt delivery. */
2525	}
2526	#endif
2527
2528	/* Enable Virtual-APIC page accesses if supported by the CPU. This is essentially where the TPR shadow resides. */
2529	/** @todo VIRT_X2APIC support, it's mutually exclusive with this. So must be
2530	* done dynamically. */
2531	if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
2532	{
2533	Assert(pVM->hm.s.vmx.HCPhysApicAccess);
2534	Assert(!(pVM->hm.s.vmx.HCPhysApicAccess & 0xfff)); /* Bits 11:0 MBZ. */
2535	val \|= VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC; /* Virtualize APIC accesses. */
2536	rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL, pVM->hm.s.vmx.HCPhysApicAccess);
2537	AssertRCReturn(rc, rc);
2538	}
2539
2540	if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
2541	val \|= VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP; /* Enable RDTSCP support. */
2542
2543	if ( pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT
2544	&& pVM->hm.s.vmx.cPleGapTicks
2545	&& pVM->hm.s.vmx.cPleWindowTicks)
2546	{
2547	val \|= VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT; /* Enable pause-loop exiting. */
2548
2549	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_GAP, pVM->hm.s.vmx.cPleGapTicks);
2550	rc \|= VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_WINDOW, pVM->hm.s.vmx.cPleWindowTicks);
2551	AssertRCReturn(rc, rc);
2552	}
2553
2554	if ((val & zap) != val)
2555	{
2556	LogRel(("hmR0VmxSetupProcCtls: Invalid secondary processor-based VM-execution controls combo! "
2557	"cpu=%#RX64 val=%#RX64 zap=%#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0, val, zap));
2558	pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC2;
2559	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2560	}
2561
2562	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, val);
2563	AssertRCReturn(rc, rc);
2564
2565	pVCpu->hm.s.vmx.u32ProcCtls2 = val;
2566	}
2567	else if (RT_UNLIKELY(pVM->hm.s.vmx.fUnrestrictedGuest))
2568	{
2569	LogRel(("hmR0VmxSetupProcCtls: Unrestricted Guest set as true when secondary processor-based VM-execution controls not "
2570	"available\n"));
2571	pVCpu->hm.s.u32HMError = VMX_UFC_INVALID_UX_COMBO;
2572	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2573	}
2574
2575	return VINF_SUCCESS;
2576	}
2577
2578
2579	/**
2580	* Sets up miscellaneous (everything other than Pin & Processor-based
2581	* VM-execution) control fields in the VMCS.
2582	*
2583	* @returns VBox status code.
2584	* @param pVM The cross context VM structure.
2585	* @param pVCpu The cross context virtual CPU structure.
2586	*/
2587	static int hmR0VmxSetupMiscCtls(PVM pVM, PVMCPU pVCpu)
2588	{
2589	NOREF(pVM);
2590	AssertPtr(pVM);
2591	AssertPtr(pVCpu);
2592
2593	int rc = VERR_GENERAL_FAILURE;
2594
2595	/* All fields are zero-initialized during allocation; but don't remove the commented block below. */
2596	#if 0
2597	/* All CR3 accesses cause VM-exits. Later we optimize CR3 accesses (see hmR0VmxLoadGuestCR3AndCR4())*/
2598	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, 0);
2599	rc \|= VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, 0);
2600
2601	/*
2602	* Set MASK & MATCH to 0. VMX checks if GuestPFErrCode & MASK == MATCH. If equal (in our case it always is)
2603	* and if the X86_XCPT_PF bit in the exception bitmap is set it causes a VM-exit, if clear doesn't cause an exit.
2604	* We thus use the exception bitmap to control it rather than use both.
2605	*/
2606	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, 0);
2607	rc \|= VMXWriteVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, 0);
2608
2609	/** @todo Explore possibility of using IO-bitmaps. */
2610	/* All IO & IOIO instructions cause VM-exits. */
2611	rc \|= VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_A_FULL, 0);
2612	rc \|= VMXWriteVmcs64(VMX_VMCS64_CTRL_IO_BITMAP_B_FULL, 0);
2613
2614	/* Initialize the MSR-bitmap area. */
2615	rc \|= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, 0);
2616	rc \|= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, 0);
2617	rc \|= VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, 0);
2618	AssertRCReturn(rc, rc);
2619	#endif
2620
2621	/* Setup MSR auto-load/store area. */
2622	Assert(pVCpu->hm.s.vmx.HCPhysGuestMsr);
2623	Assert(!(pVCpu->hm.s.vmx.HCPhysGuestMsr & 0xf)); /* Lower 4 bits MBZ. */
2624	rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
2625	rc \|= VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL, pVCpu->hm.s.vmx.HCPhysGuestMsr);
2626	AssertRCReturn(rc, rc);
2627
2628	Assert(pVCpu->hm.s.vmx.HCPhysHostMsr);
2629	Assert(!(pVCpu->hm.s.vmx.HCPhysHostMsr & 0xf)); /* Lower 4 bits MBZ. */
2630	rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL, pVCpu->hm.s.vmx.HCPhysHostMsr);
2631	AssertRCReturn(rc, rc);
2632
2633	/* Set VMCS link pointer. Reserved for future use, must be -1. Intel spec. 24.4 "Guest-State Area". */
2634	rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, UINT64_C(0xffffffffffffffff));
2635	AssertRCReturn(rc, rc);
2636
2637	/* All fields are zero-initialized during allocation; but don't remove the commented block below. */
2638	#if 0
2639	/* Setup debug controls */
2640	rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, 0); /** @todo We don't support IA32_DEBUGCTL MSR. Should we? */
2641	rc \|= VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, 0);
2642	AssertRCReturn(rc, rc);
2643	#endif
2644
2645	return rc;
2646	}
2647
2648
2649	/**
2650	* Sets up the initial exception bitmap in the VMCS based on static conditions.
2651	*
2652	* We shall setup those exception intercepts that don't change during the
2653	* lifetime of the VM here. The rest are done dynamically while loading the
2654	* guest state.
2655	*
2656	* @returns VBox status code.
2657	* @param pVM The cross context VM structure.
2658	* @param pVCpu The cross context virtual CPU structure.
2659	*/
2660	static int hmR0VmxInitXcptBitmap(PVM pVM, PVMCPU pVCpu)
2661	{
2662	AssertPtr(pVM);
2663	AssertPtr(pVCpu);
2664
2665	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
2666
2667	uint32_t u32XcptBitmap = 0;
2668
2669	/* Must always intercept #AC to prevent the guest from hanging the CPU. */
2670	u32XcptBitmap \|= RT_BIT_32(X86_XCPT_AC);
2671
2672	/* Because we need to maintain the DR6 state even when intercepting DRx reads
2673	and writes, and because recursive #DBs can cause the CPU hang, we must always
2674	intercept #DB. */
2675	u32XcptBitmap \|= RT_BIT_32(X86_XCPT_DB);
2676
2677	/* Without Nested Paging, #PF must cause a VM-exit so we can sync our shadow page tables. */
2678	if (!pVM->hm.s.fNestedPaging)
2679	u32XcptBitmap \|= RT_BIT(X86_XCPT_PF);
2680
2681	pVCpu->hm.s.vmx.u32XcptBitmap = u32XcptBitmap;
2682	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, u32XcptBitmap);
2683	AssertRCReturn(rc, rc);
2684	return rc;
2685	}
2686
2687
2688	/**
2689	* Sets up the initial guest-state mask. The guest-state mask is consulted
2690	* before reading guest-state fields from the VMCS as VMREADs can be expensive
2691	* for the nested virtualization case (as it would cause a VM-exit).
2692	*
2693	* @param pVCpu The cross context virtual CPU structure.
2694	*/
2695	static int hmR0VmxInitUpdatedGuestStateMask(PVMCPU pVCpu)
2696	{
2697	/* Initially the guest-state is up-to-date as there is nothing in the VMCS. */
2698	HMVMXCPU_GST_RESET_TO(pVCpu, HMVMX_UPDATED_GUEST_ALL);
2699	return VINF_SUCCESS;
2700	}
2701
2702
2703	/**
2704	* Does per-VM VT-x initialization.
2705	*
2706	* @returns VBox status code.
2707	* @param pVM The cross context VM structure.
2708	*/
2709	VMMR0DECL(int) VMXR0InitVM(PVM pVM)
2710	{
2711	LogFlowFunc(("pVM=%p\n", pVM));
2712
2713	int rc = hmR0VmxStructsAlloc(pVM);
2714	if (RT_FAILURE(rc))
2715	{
2716	LogRel(("VMXR0InitVM: hmR0VmxStructsAlloc failed! rc=%Rrc\n", rc));
2717	return rc;
2718	}
2719
2720	return VINF_SUCCESS;
2721	}
2722
2723
2724	/**
2725	* Does per-VM VT-x termination.
2726	*
2727	* @returns VBox status code.
2728	* @param pVM The cross context VM structure.
2729	*/
2730	VMMR0DECL(int) VMXR0TermVM(PVM pVM)
2731	{
2732	LogFlowFunc(("pVM=%p\n", pVM));
2733
2734	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2735	if (pVM->hm.s.vmx.hMemObjScratch != NIL_RTR0MEMOBJ)
2736	ASMMemZero32(pVM->hm.s.vmx.pvScratch, PAGE_SIZE);
2737	#endif
2738	hmR0VmxStructsFree(pVM);
2739	return VINF_SUCCESS;
2740	}
2741
2742
2743	/**
2744	* Sets up the VM for execution under VT-x.
2745	* This function is only called once per-VM during initialization.
2746	*
2747	* @returns VBox status code.
2748	* @param pVM The cross context VM structure.
2749	*/
2750	VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
2751	{
2752	AssertPtrReturn(pVM, VERR_INVALID_PARAMETER);
2753	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2754
2755	LogFlowFunc(("pVM=%p\n", pVM));
2756
2757	/*
2758	* Without UnrestrictedGuest, pRealModeTSS and pNonPagingModeEPTPageTable must always be allocated.
2759	* We no longer support the highly unlikely case of UnrestrictedGuest without pRealModeTSS. See hmR3InitFinalizeR0Intel().
2760	*/
2761	if ( !pVM->hm.s.vmx.fUnrestrictedGuest
2762	&& ( !pVM->hm.s.vmx.pNonPagingModeEPTPageTable
2763	\|\| !pVM->hm.s.vmx.pRealModeTSS))
2764	{
2765	LogRel(("VMXR0SetupVM: Invalid real-on-v86 state.\n"));
2766	return VERR_INTERNAL_ERROR;
2767	}
2768
2769	/* Initialize these always, see hmR3InitFinalizeR0().*/
2770	pVM->hm.s.vmx.enmFlushEpt = VMXFLUSHEPT_NONE;
2771	pVM->hm.s.vmx.enmFlushVpid = VMXFLUSHVPID_NONE;
2772
2773	/* Setup the tagged-TLB flush handlers. */
2774	int rc = hmR0VmxSetupTaggedTlb(pVM);
2775	if (RT_FAILURE(rc))
2776	{
2777	LogRel(("VMXR0SetupVM: hmR0VmxSetupTaggedTlb failed! rc=%Rrc\n", rc));
2778	return rc;
2779	}
2780
2781	/* Check if we can use the VMCS controls for swapping the EFER MSR. */
2782	Assert(!pVM->hm.s.vmx.fSupportsVmcsEfer);
2783	#if HC_ARCH_BITS == 64
2784	if ( (pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1 & VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR)
2785	&& (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR)
2786	&& (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR))
2787	{
2788	pVM->hm.s.vmx.fSupportsVmcsEfer = true;
2789	}
2790	#endif
2791
2792	/* At least verify VMX is enabled, since we can't check if we're in VMX root mode without #GP'ing. */
2793	RTCCUINTREG uHostCR4 = ASMGetCR4();
2794	if (RT_UNLIKELY(!(uHostCR4 & X86_CR4_VMXE)))
2795	return VERR_VMX_NOT_IN_VMX_ROOT_MODE;
2796
2797	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2798	{
2799	PVMCPU pVCpu = &pVM->aCpus[i];
2800	AssertPtr(pVCpu);
2801	AssertPtr(pVCpu->hm.s.vmx.pvVmcs);
2802
2803	/* Log the VCPU pointers, useful for debugging SMP VMs. */
2804	Log4(("VMXR0SetupVM: pVCpu=%p idCpu=%RU32\n", pVCpu, pVCpu->idCpu));
2805
2806	/* Initialize the VM-exit history array with end-of-array markers (UINT16_MAX). */
2807	Assert(!pVCpu->hm.s.idxExitHistoryFree);
2808	HMCPU_EXIT_HISTORY_RESET(pVCpu);
2809
2810	/* Set revision dword at the beginning of the VMCS structure. */
2811	(uint32_t )pVCpu->hm.s.vmx.pvVmcs = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo);
2812
2813	/* Initialize our VMCS region in memory, set the VMCS launch state to "clear". */
2814	rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2815	AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXClearVmcs failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2816	hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2817
2818	/* Load this VMCS as the current VMCS. */
2819	rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2820	AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXActivateVmcs failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2821	hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2822
2823	rc = hmR0VmxSetupPinCtls(pVM, pVCpu);
2824	AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupPinCtls failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2825	hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2826
2827	rc = hmR0VmxSetupProcCtls(pVM, pVCpu);
2828	AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupProcCtls failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2829	hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2830
2831	rc = hmR0VmxSetupMiscCtls(pVM, pVCpu);
2832	AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxSetupMiscCtls failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2833	hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2834
2835	rc = hmR0VmxInitXcptBitmap(pVM, pVCpu);
2836	AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitXcptBitmap failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2837	hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2838
2839	rc = hmR0VmxInitUpdatedGuestStateMask(pVCpu);
2840	AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitUpdatedGuestStateMask failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2841	hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2842
2843	#if HC_ARCH_BITS == 32
2844	rc = hmR0VmxInitVmcsReadCache(pVM, pVCpu);
2845	AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: hmR0VmxInitVmcsReadCache failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2846	hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2847	#endif
2848
2849	/* Re-sync the CPU's internal data into our VMCS memory region & reset the launch state to "clear". */
2850	rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
2851	AssertLogRelMsgRCReturnStmt(rc, ("VMXR0SetupVM: VMXClearVmcs(2) failed! rc=%Rrc (pVM=%p)\n", rc, pVM),
2852	hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc), rc);
2853
2854	pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
2855
2856	hmR0VmxUpdateErrorRecord(pVM, pVCpu, rc);
2857	}
2858
2859	return VINF_SUCCESS;
2860	}
2861
2862
2863	/**
2864	* Saves the host control registers (CR0, CR3, CR4) into the host-state area in
2865	* the VMCS.
2866	*
2867	* @returns VBox status code.
2868	* @param pVM The cross context VM structure.
2869	* @param pVCpu The cross context virtual CPU structure.
2870	*/
2871	DECLINLINE(int) hmR0VmxSaveHostControlRegs(PVM pVM, PVMCPU pVCpu)
2872	{
2873	NOREF(pVM); NOREF(pVCpu);
2874
2875	RTCCUINTREG uReg = ASMGetCR0();
2876	int rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR0, uReg);
2877	AssertRCReturn(rc, rc);
2878
2879	uReg = ASMGetCR3();
2880	rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR3, uReg);
2881	AssertRCReturn(rc, rc);
2882
2883	uReg = ASMGetCR4();
2884	rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_CR4, uReg);
2885	AssertRCReturn(rc, rc);
2886	return rc;
2887	}
2888
2889
2890	#if HC_ARCH_BITS == 64
2891	/**
2892	* Macro for adjusting host segment selectors to satisfy VT-x's VM-entry
2893	* requirements. See hmR0VmxSaveHostSegmentRegs().
2894	*/
2895	# define VMXLOCAL_ADJUST_HOST_SEG(seg, selValue) \
2896	if ((selValue) & (X86_SEL_RPL \| X86_SEL_LDT)) \
2897	{ \
2898	bool fValidSelector = true; \
2899	if ((selValue) & X86_SEL_LDT) \
2900	{ \
2901	uint32_t uAttr = ASMGetSegAttr((selValue)); \
2902	fValidSelector = RT_BOOL(uAttr != UINT32_MAX && (uAttr & X86_DESC_P)); \
2903	} \
2904	if (fValidSelector) \
2905	{ \
2906	pVCpu->hm.s.vmx.fRestoreHostFlags \|= VMX_RESTORE_HOST_SEL_##seg; \
2907	pVCpu->hm.s.vmx.RestoreHost.uHostSel##seg = (selValue); \
2908	} \
2909	(selValue) = 0; \
2910	}
2911	#endif
2912
2913
2914	/**
2915	* Saves the host segment registers and GDTR, IDTR, (TR, GS and FS bases) into
2916	* the host-state area in the VMCS.
2917	*
2918	* @returns VBox status code.
2919	* @param pVM The cross context VM structure.
2920	* @param pVCpu The cross context virtual CPU structure.
2921	*/
2922	DECLINLINE(int) hmR0VmxSaveHostSegmentRegs(PVM pVM, PVMCPU pVCpu)
2923	{
2924	int rc = VERR_INTERNAL_ERROR_5;
2925
2926	#if HC_ARCH_BITS == 64
2927	/*
2928	* If we've executed guest code using VT-x, the host-state bits will be messed up. We
2929	* should -not- save the messed up state without restoring the original host-state. See @bugref{7240}.
2930	*
2931	* This apparently can happen (most likely the FPU changes), deal with it rather than asserting.
2932	* Was observed booting Solaris10u10 32-bit guest.
2933	*/
2934	if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
2935	&& (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
2936	{
2937	Log4Func(("Restoring Host State: fRestoreHostFlags=%#RX32 HostCpuId=%u\n", pVCpu->hm.s.vmx.fRestoreHostFlags,
2938	pVCpu->idCpu));
2939	VMXRestoreHostState(pVCpu->hm.s.vmx.fRestoreHostFlags, &pVCpu->hm.s.vmx.RestoreHost);
2940	}
2941	pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
2942	#else
2943	RT_NOREF(pVCpu);
2944	#endif
2945
2946	/*
2947	* Host DS, ES, FS and GS segment registers.
2948	*/
2949	#if HC_ARCH_BITS == 64
2950	RTSEL uSelDS = ASMGetDS();
2951	RTSEL uSelES = ASMGetES();
2952	RTSEL uSelFS = ASMGetFS();
2953	RTSEL uSelGS = ASMGetGS();
2954	#else
2955	RTSEL uSelDS = 0;
2956	RTSEL uSelES = 0;
2957	RTSEL uSelFS = 0;
2958	RTSEL uSelGS = 0;
2959	#endif
2960
2961	/*
2962	* Host CS and SS segment registers.
2963	*/
2964	RTSEL uSelCS = ASMGetCS();
2965	RTSEL uSelSS = ASMGetSS();
2966
2967	/*
2968	* Host TR segment register.
2969	*/
2970	RTSEL uSelTR = ASMGetTR();
2971
2972	#if HC_ARCH_BITS == 64
2973	/*
2974	* Determine if the host segment registers are suitable for VT-x. Otherwise use zero to gain VM-entry and restore them
2975	* before we get preempted. See Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers".
2976	*/
2977	VMXLOCAL_ADJUST_HOST_SEG(DS, uSelDS);
2978	VMXLOCAL_ADJUST_HOST_SEG(ES, uSelES);
2979	VMXLOCAL_ADJUST_HOST_SEG(FS, uSelFS);
2980	VMXLOCAL_ADJUST_HOST_SEG(GS, uSelGS);
2981	# undef VMXLOCAL_ADJUST_HOST_SEG
2982	#endif
2983
2984	/* Verification based on Intel spec. 26.2.3 "Checks on Host Segment and Descriptor-Table Registers" */
2985	Assert(!(uSelCS & X86_SEL_RPL)); Assert(!(uSelCS & X86_SEL_LDT));
2986	Assert(!(uSelSS & X86_SEL_RPL)); Assert(!(uSelSS & X86_SEL_LDT));
2987	Assert(!(uSelDS & X86_SEL_RPL)); Assert(!(uSelDS & X86_SEL_LDT));
2988	Assert(!(uSelES & X86_SEL_RPL)); Assert(!(uSelES & X86_SEL_LDT));
2989	Assert(!(uSelFS & X86_SEL_RPL)); Assert(!(uSelFS & X86_SEL_LDT));
2990	Assert(!(uSelGS & X86_SEL_RPL)); Assert(!(uSelGS & X86_SEL_LDT));
2991	Assert(!(uSelTR & X86_SEL_RPL)); Assert(!(uSelTR & X86_SEL_LDT));
2992	Assert(uSelCS);
2993	Assert(uSelTR);
2994
2995	/* Assertion is right but we would not have updated u32ExitCtls yet. */
2996	#if 0
2997	if (!(pVCpu->hm.s.vmx.u32ExitCtls & VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE))
2998	Assert(uSelSS != 0);
2999	#endif
3000
3001	/* Write these host selector fields into the host-state area in the VMCS. */
3002	rc = VMXWriteVmcs32(VMX_VMCS16_HOST_CS_SEL, uSelCS);
3003	rc \|= VMXWriteVmcs32(VMX_VMCS16_HOST_SS_SEL, uSelSS);
3004	#if HC_ARCH_BITS == 64
3005	rc \|= VMXWriteVmcs32(VMX_VMCS16_HOST_DS_SEL, uSelDS);
3006	rc \|= VMXWriteVmcs32(VMX_VMCS16_HOST_ES_SEL, uSelES);
3007	rc \|= VMXWriteVmcs32(VMX_VMCS16_HOST_FS_SEL, uSelFS);
3008	rc \|= VMXWriteVmcs32(VMX_VMCS16_HOST_GS_SEL, uSelGS);
3009	#else
3010	NOREF(uSelDS);
3011	NOREF(uSelES);
3012	NOREF(uSelFS);
3013	NOREF(uSelGS);
3014	#endif
3015	rc \|= VMXWriteVmcs32(VMX_VMCS16_HOST_TR_SEL, uSelTR);
3016	AssertRCReturn(rc, rc);
3017
3018	/*
3019	* Host GDTR and IDTR.
3020	*/
3021	RTGDTR Gdtr;
3022	RTIDTR Idtr;
3023	RT_ZERO(Gdtr);
3024	RT_ZERO(Idtr);
3025	ASMGetGDTR(&Gdtr);
3026	ASMGetIDTR(&Idtr);
3027	rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, Gdtr.pGdt);
3028	rc \|= VMXWriteVmcsHstN(VMX_VMCS_HOST_IDTR_BASE, Idtr.pIdt);
3029	AssertRCReturn(rc, rc);
3030
3031	#if HC_ARCH_BITS == 64
3032	/*
3033	* Determine if we need to manually need to restore the GDTR and IDTR limits as VT-x zaps them to the
3034	* maximum limit (0xffff) on every VM-exit.
3035	*/
3036	if (Gdtr.cbGdt != 0xffff)
3037	{
3038	pVCpu->hm.s.vmx.fRestoreHostFlags \|= VMX_RESTORE_HOST_GDTR;
3039	AssertCompile(sizeof(Gdtr) == sizeof(X86XDTR64));
3040	memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostGdtr, &Gdtr, sizeof(X86XDTR64));
3041	}
3042
3043	/*
3044	* IDT limit is effectively capped at 0xfff. (See Intel spec. 6.14.1 "64-Bit Mode IDT"
3045	* and Intel spec. 6.2 "Exception and Interrupt Vectors".) Therefore if the host has the limit as 0xfff, VT-x
3046	* bloating the limit to 0xffff shouldn't cause any different CPU behavior. However, several hosts either insists
3047	* on 0xfff being the limit (Windows Patch Guard) or uses the limit for other purposes (darwin puts the CPU ID in there
3048	* but botches sidt alignment in at least one consumer). So, we're only allowing IDTR.LIMIT to be left at 0xffff on
3049	* hosts where we are pretty sure it won't cause trouble.
3050	*/
3051	# if defined(RT_OS_LINUX) \|\| defined(RT_OS_SOLARIS)
3052	if (Idtr.cbIdt < 0x0fff)
3053	# else
3054	if (Idtr.cbIdt != 0xffff)
3055	# endif
3056	{
3057	pVCpu->hm.s.vmx.fRestoreHostFlags \|= VMX_RESTORE_HOST_IDTR;
3058	AssertCompile(sizeof(Idtr) == sizeof(X86XDTR64));
3059	memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostIdtr, &Idtr, sizeof(X86XDTR64));
3060	}
3061	#endif
3062
3063	/*
3064	* Host TR base. Verify that TR selector doesn't point past the GDT. Masking off the TI and RPL bits
3065	* is effectively what the CPU does for "scaling by 8". TI is always 0 and RPL should be too in most cases.
3066	*/
3067	AssertMsgReturn((uSelTR \| X86_SEL_RPL_LDT) <= Gdtr.cbGdt,
3068	("hmR0VmxSaveHostSegmentRegs: TR selector exceeds limit. TR=%RTsel cbGdt=%#x\n", uSelTR, Gdtr.cbGdt),
3069	VERR_VMX_INVALID_HOST_STATE);
3070
3071	PCX86DESCHC pDesc = (PCX86DESCHC)(Gdtr.pGdt + (uSelTR & X86_SEL_MASK));
3072	#if HC_ARCH_BITS == 64
3073	uintptr_t uTRBase = X86DESC64_BASE(pDesc);
3074
3075	/*
3076	* VT-x unconditionally restores the TR limit to 0x67 and type to 11 (32-bit busy TSS) on all VM-exits.
3077	* The type is the same for 64-bit busy TSS[1]. The limit needs manual restoration if the host has something else.
3078	* Task switching is not supported in 64-bit mode[2], but the limit still matters as IOPM is supported in 64-bit mode.
3079	* Restoring the limit lazily while returning to ring-3 is safe because IOPM is not applicable in ring-0.
3080	*
3081	* [1] See Intel spec. 3.5 "System Descriptor Types".
3082	* [2] See Intel spec. 7.2.3 "TSS Descriptor in 64-bit mode".
3083	*/
3084	Assert(pDesc->System.u4Type == 11);
3085	if ( pDesc->System.u16LimitLow != 0x67
3086	\|\| pDesc->System.u4LimitHigh)
3087	{
3088	pVCpu->hm.s.vmx.fRestoreHostFlags \|= VMX_RESTORE_HOST_SEL_TR;
3089	/* If the host has made GDT read-only, we would need to temporarily toggle CR0.WP before writing the GDT. */
3090	if (pVM->hm.s.fHostKernelFeatures & SUPKERNELFEATURES_GDT_READ_ONLY)
3091	pVCpu->hm.s.vmx.fRestoreHostFlags \|= VMX_RESTORE_HOST_GDT_READ_ONLY;
3092	pVCpu->hm.s.vmx.RestoreHost.uHostSelTR = uSelTR;
3093
3094	/* Store the GDTR here as we need it while restoring TR. */
3095	memcpy(&pVCpu->hm.s.vmx.RestoreHost.HostGdtr, &Gdtr, sizeof(X86XDTR64));
3096	}
3097	#else
3098	NOREF(pVM);
3099	uintptr_t uTRBase = X86DESC_BASE(pDesc);
3100	#endif
3101	rc = VMXWriteVmcsHstN(VMX_VMCS_HOST_TR_BASE, uTRBase);
3102	AssertRCReturn(rc, rc);
3103
3104	/*
3105	* Host FS base and GS base.
3106	*/
3107	#if HC_ARCH_BITS == 64
3108	uint64_t u64FSBase = ASMRdMsr(MSR_K8_FS_BASE);
3109	uint64_t u64GSBase = ASMRdMsr(MSR_K8_GS_BASE);
3110	rc = VMXWriteVmcs64(VMX_VMCS_HOST_FS_BASE, u64FSBase);
3111	rc \|= VMXWriteVmcs64(VMX_VMCS_HOST_GS_BASE, u64GSBase);
3112	AssertRCReturn(rc, rc);
3113
3114	/* Store the base if we have to restore FS or GS manually as we need to restore the base as well. */
3115	if (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_SEL_FS)
3116	pVCpu->hm.s.vmx.RestoreHost.uHostFSBase = u64FSBase;
3117	if (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_SEL_GS)
3118	pVCpu->hm.s.vmx.RestoreHost.uHostGSBase = u64GSBase;
3119	#endif
3120	return rc;
3121	}
3122
3123
3124	/**
3125	* Saves certain host MSRs in the VM-exit MSR-load area and some in the
3126	* host-state area of the VMCS. Theses MSRs will be automatically restored on
3127	* the host after every successful VM-exit.
3128	*
3129	* @returns VBox status code.
3130	* @param pVM The cross context VM structure.
3131	* @param pVCpu The cross context virtual CPU structure.
3132	*
3133	* @remarks No-long-jump zone!!!
3134	*/
3135	DECLINLINE(int) hmR0VmxSaveHostMsrs(PVM pVM, PVMCPU pVCpu)
3136	{
3137	NOREF(pVM);
3138
3139	AssertPtr(pVCpu);
3140	AssertPtr(pVCpu->hm.s.vmx.pvHostMsr);
3141
3142	/*
3143	* Save MSRs that we restore lazily (due to preemption or transition to ring-3)
3144	* rather than swapping them on every VM-entry.
3145	*/
3146	hmR0VmxLazySaveHostMsrs(pVCpu);
3147
3148	/*
3149	* Host Sysenter MSRs.
3150	*/
3151	int rc = VMXWriteVmcs32(VMX_VMCS32_HOST_SYSENTER_CS, ASMRdMsr_Low(MSR_IA32_SYSENTER_CS));
3152	#if HC_ARCH_BITS == 32
3153	rc \|= VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr_Low(MSR_IA32_SYSENTER_ESP));
3154	rc \|= VMXWriteVmcs32(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr_Low(MSR_IA32_SYSENTER_EIP));
3155	#else
3156	rc \|= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_ESP, ASMRdMsr(MSR_IA32_SYSENTER_ESP));
3157	rc \|= VMXWriteVmcs64(VMX_VMCS_HOST_SYSENTER_EIP, ASMRdMsr(MSR_IA32_SYSENTER_EIP));
3158	#endif
3159	AssertRCReturn(rc, rc);
3160
3161	/*
3162	* Host EFER MSR.
3163	* If the CPU supports the newer VMCS controls for managing EFER, use it.
3164	* Otherwise it's done as part of auto-load/store MSR area in the VMCS, see hmR0VmxLoadGuestMsrs().
3165	*/
3166	if (pVM->hm.s.vmx.fSupportsVmcsEfer)
3167	{
3168	rc = VMXWriteVmcs64(VMX_VMCS64_HOST_EFER_FULL, pVM->hm.s.vmx.u64HostEfer);
3169	AssertRCReturn(rc, rc);
3170	}
3171
3172	/** @todo IA32_PERF_GLOBALCTRL, IA32_PAT also see
3173	* hmR0VmxLoadGuestExitCtls() !! */
3174
3175	return rc;
3176	}
3177
3178
3179	/**
3180	* Figures out if we need to swap the EFER MSR which is particularly expensive.
3181	*
3182	* We check all relevant bits. For now, that's everything besides LMA/LME, as
3183	* these two bits are handled by VM-entry, see hmR0VmxLoadGuestExitCtls() and
3184	* hmR0VMxLoadGuestEntryCtls().
3185	*
3186	* @returns true if we need to load guest EFER, false otherwise.
3187	* @param pVCpu The cross context virtual CPU structure.
3188	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
3189	* out-of-sync. Make sure to update the required fields
3190	* before using them.
3191	*
3192	* @remarks Requires EFER, CR4.
3193	* @remarks No-long-jump zone!!!
3194	*/
3195	static bool hmR0VmxShouldSwapEferMsr(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3196	{
3197	#ifdef HMVMX_ALWAYS_SWAP_EFER
3198	return true;
3199	#endif
3200
3201	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
3202	/* For 32-bit hosts running 64-bit guests, we always swap EFER in the world-switcher. Nothing to do here. */
3203	if (CPUMIsGuestInLongMode(pVCpu))
3204	return false;
3205	#endif
3206
3207	PVM pVM = pVCpu->CTX_SUFF(pVM);
3208	uint64_t u64HostEfer = pVM->hm.s.vmx.u64HostEfer;
3209	uint64_t u64GuestEfer = pMixedCtx->msrEFER;
3210
3211	/*
3212	* For 64-bit guests, if EFER.SCE bit differs, we need to swap to ensure that the
3213	* guest's SYSCALL behaviour isn't screwed. See @bugref{7386}.
3214	*/
3215	if ( CPUMIsGuestInLongMode(pVCpu)
3216	&& (u64GuestEfer & MSR_K6_EFER_SCE) != (u64HostEfer & MSR_K6_EFER_SCE))
3217	{
3218	return true;
3219	}
3220
3221	/*
3222	* If the guest uses PAE and EFER.NXE bit differs, we need to swap EFER as it
3223	* affects guest paging. 64-bit paging implies CR4.PAE as well.
3224	* See Intel spec. 4.5 "IA-32e Paging" and Intel spec. 4.1.1 "Three Paging Modes".
3225	*/
3226	if ( (pMixedCtx->cr4 & X86_CR4_PAE)
3227	&& (pMixedCtx->cr0 & X86_CR0_PG)
3228	&& (u64GuestEfer & MSR_K6_EFER_NXE) != (u64HostEfer & MSR_K6_EFER_NXE))
3229	{
3230	/* Assert that host is PAE capable. */
3231	Assert(pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_NX);
3232	return true;
3233	}
3234
3235	/** @todo Check the latest Intel spec. for any other bits,
3236	* like SMEP/SMAP? */
3237	return false;
3238	}
3239
3240
3241	/**
3242	* Sets up VM-entry controls in the VMCS. These controls can affect things done
3243	* on VM-exit; e.g. "load debug controls", see Intel spec. 24.8.1 "VM-entry
3244	* controls".
3245	*
3246	* @returns VBox status code.
3247	* @param pVCpu The cross context virtual CPU structure.
3248	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
3249	* out-of-sync. Make sure to update the required fields
3250	* before using them.
3251	*
3252	* @remarks Requires EFER.
3253	* @remarks No-long-jump zone!!!
3254	*/
3255	DECLINLINE(int) hmR0VmxLoadGuestEntryCtls(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3256	{
3257	int rc = VINF_SUCCESS;
3258	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_ENTRY_CTLS))
3259	{
3260	PVM pVM = pVCpu->CTX_SUFF(pVM);
3261	uint32_t val = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0; /* Bits set here must be set in the VMCS. */
3262	uint32_t zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
3263
3264	/* Load debug controls (DR7 & IA32_DEBUGCTL_MSR). The first VT-x capable CPUs only supports the 1-setting of this bit. */
3265	val \|= VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG;
3266
3267	/* Set if the guest is in long mode. This will set/clear the EFER.LMA bit on VM-entry. */
3268	if (CPUMIsGuestInLongModeEx(pMixedCtx))
3269	{
3270	val \|= VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST;
3271	Log4(("Load[%RU32]: VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST\n", pVCpu->idCpu));
3272	}
3273	else
3274	Assert(!(val & VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST));
3275
3276	/* If the CPU supports the newer VMCS controls for managing guest/host EFER, use it. */
3277	if ( pVM->hm.s.vmx.fSupportsVmcsEfer
3278	&& hmR0VmxShouldSwapEferMsr(pVCpu, pMixedCtx))
3279	{
3280	val \|= VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR;
3281	Log4(("Load[%RU32]: VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR\n", pVCpu->idCpu));
3282	}
3283
3284	/*
3285	* The following should -not- be set (since we're not in SMM mode):
3286	* - VMX_VMCS_CTRL_ENTRY_ENTRY_SMM
3287	* - VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON
3288	*/
3289
3290	/** @todo VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR,
3291	* VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR. */
3292
3293	if ((val & zap) != val)
3294	{
3295	LogRel(("hmR0VmxLoadGuestEntryCtls: Invalid VM-entry controls combo! cpu=%RX64 val=%RX64 zap=%RX64\n",
3296	pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0, val, zap));
3297	pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_ENTRY;
3298	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3299	}
3300
3301	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY, val);
3302	AssertRCReturn(rc, rc);
3303
3304	pVCpu->hm.s.vmx.u32EntryCtls = val;
3305	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMX_ENTRY_CTLS);
3306	}
3307	return rc;
3308	}
3309
3310
3311	/**
3312	* Sets up the VM-exit controls in the VMCS.
3313	*
3314	* @returns VBox status code.
3315	* @param pVCpu The cross context virtual CPU structure.
3316	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
3317	* out-of-sync. Make sure to update the required fields
3318	* before using them.
3319	*
3320	* @remarks Requires EFER.
3321	*/
3322	DECLINLINE(int) hmR0VmxLoadGuestExitCtls(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3323	{
3324	NOREF(pMixedCtx);
3325
3326	int rc = VINF_SUCCESS;
3327	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_EXIT_CTLS))
3328	{
3329	PVM pVM = pVCpu->CTX_SUFF(pVM);
3330	uint32_t val = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0; /* Bits set here must be set in the VMCS. */
3331	uint32_t zap = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
3332
3333	/* Save debug controls (DR7 & IA32_DEBUGCTL_MSR). The first VT-x CPUs only supported the 1-setting of this bit. */
3334	val \|= VMX_VMCS_CTRL_EXIT_SAVE_DEBUG;
3335
3336	/*
3337	* Set the host long mode active (EFER.LMA) bit (which Intel calls "Host address-space size") if necessary.
3338	* On VM-exit, VT-x sets both the host EFER.LMA and EFER.LME bit to this value. See assertion in hmR0VmxSaveHostMsrs().
3339	*/
3340	#if HC_ARCH_BITS == 64
3341	val \|= VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE;
3342	Log4(("Load[%RU32]: VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE\n", pVCpu->idCpu));
3343	#else
3344	Assert( pVCpu->hm.s.vmx.pfnStartVM == VMXR0SwitcherStartVM64
3345	\|\| pVCpu->hm.s.vmx.pfnStartVM == VMXR0StartVM32);
3346	/* Set the host address-space size based on the switcher, not guest state. See @bugref{8432}. */
3347	if (pVCpu->hm.s.vmx.pfnStartVM == VMXR0SwitcherStartVM64)
3348	{
3349	/* The switcher returns to long mode, EFER is managed by the switcher. */
3350	val \|= VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE;
3351	Log4(("Load[%RU32]: VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE\n", pVCpu->idCpu));
3352	}
3353	else
3354	Assert(!(val & VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE));
3355	#endif
3356
3357	/* If the newer VMCS fields for managing EFER exists, use it. */
3358	if ( pVM->hm.s.vmx.fSupportsVmcsEfer
3359	&& hmR0VmxShouldSwapEferMsr(pVCpu, pMixedCtx))
3360	{
3361	val \|= VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR
3362	\| VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR;
3363	Log4(("Load[%RU32]: VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR, VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR\n", pVCpu->idCpu));
3364	}
3365
3366	/* Don't acknowledge external interrupts on VM-exit. We want to let the host do that. */
3367	Assert(!(val & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT));
3368
3369	/** @todo VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR,
3370	* VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR,
3371	* VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR. */
3372
3373	if ( pVM->hm.s.vmx.fUsePreemptTimer
3374	&& (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER))
3375	val \|= VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER;
3376
3377	if ((val & zap) != val)
3378	{
3379	LogRel(("hmR0VmxSetupProcCtls: Invalid VM-exit controls combo! cpu=%RX64 val=%RX64 zap=%RX64\n",
3380	pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0, val, zap));
3381	pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_EXIT;
3382	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
3383	}
3384
3385	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXIT, val);
3386	AssertRCReturn(rc, rc);
3387
3388	pVCpu->hm.s.vmx.u32ExitCtls = val;
3389	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMX_EXIT_CTLS);
3390	}
3391	return rc;
3392	}
3393
3394
3395	/**
3396	* Sets the TPR threshold in the VMCS.
3397	*
3398	* @returns VBox status code.
3399	* @param pVCpu The cross context virtual CPU structure.
3400	* @param u32TprThreshold The TPR threshold (task-priority class only).
3401	*/
3402	DECLINLINE(int) hmR0VmxApicSetTprThreshold(PVMCPU pVCpu, uint32_t u32TprThreshold)
3403	{
3404	Assert(!(u32TprThreshold & 0xfffffff0)); /* Bits 31:4 MBZ. */
3405	Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW); RT_NOREF_PV(pVCpu);
3406	return VMXWriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, u32TprThreshold);
3407	}
3408
3409
3410	/**
3411	* Loads the guest APIC and related state.
3412	*
3413	* @returns VBox status code.
3414	* @param pVCpu The cross context virtual CPU structure.
3415	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
3416	* out-of-sync. Make sure to update the required fields
3417	* before using them.
3418	*
3419	* @remarks No-long-jump zone!!!
3420	*/
3421	DECLINLINE(int) hmR0VmxLoadGuestApicState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3422	{
3423	NOREF(pMixedCtx);
3424
3425	int rc = VINF_SUCCESS;
3426	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE))
3427	{
3428	if ( PDMHasApic(pVCpu->CTX_SUFF(pVM))
3429	&& APICIsEnabled(pVCpu))
3430	{
3431	/*
3432	* Setup TPR shadowing.
3433	*/
3434	if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
3435	{
3436	Assert(pVCpu->hm.s.vmx.HCPhysVirtApic);
3437
3438	bool fPendingIntr = false;
3439	uint8_t u8Tpr = 0;
3440	uint8_t u8PendingIntr = 0;
3441	rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, &u8PendingIntr);
3442	AssertRCReturn(rc, rc);
3443
3444	/*
3445	* If there are interrupts pending but masked by the TPR, instruct VT-x to cause a TPR-below-threshold VM-exit
3446	* when the guest lowers its TPR below the priority of the pending interrupt so we can deliver the interrupt.
3447	* If there are no interrupts pending, set threshold to 0 to not cause any TPR-below-threshold VM-exits.
3448	*/
3449	pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR] = u8Tpr;
3450	uint32_t u32TprThreshold = 0;
3451	if (fPendingIntr)
3452	{
3453	/* Bits 3:0 of the TPR threshold field correspond to bits 7:4 of the TPR (which is the Task-Priority Class). */
3454	const uint8_t u8PendingPriority = u8PendingIntr >> 4;
3455	const uint8_t u8TprPriority = u8Tpr >> 4;
3456	if (u8PendingPriority <= u8TprPriority)
3457	u32TprThreshold = u8PendingPriority;
3458	}
3459
3460	rc = hmR0VmxApicSetTprThreshold(pVCpu, u32TprThreshold);
3461	AssertRCReturn(rc, rc);
3462	}
3463	}
3464	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
3465	}
3466
3467	return rc;
3468	}
3469
3470
3471	/**
3472	* Gets the guest's interruptibility-state ("interrupt shadow" as AMD calls it).
3473	*
3474	* @returns Guest's interruptibility-state.
3475	* @param pVCpu The cross context virtual CPU structure.
3476	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
3477	* out-of-sync. Make sure to update the required fields
3478	* before using them.
3479	*
3480	* @remarks No-long-jump zone!!!
3481	*/
3482	DECLINLINE(uint32_t) hmR0VmxGetGuestIntrState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3483	{
3484	/*
3485	* Check if we should inhibit interrupt delivery due to instructions like STI and MOV SS.
3486	*/
3487	uint32_t uIntrState = 0;
3488	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3489	{
3490	/* If inhibition is active, RIP & RFLAGS should've been accessed (i.e. read previously from the VMCS or from ring-3). */
3491	AssertMsg(HMVMXCPU_GST_IS_SET(pVCpu, HMVMX_UPDATED_GUEST_RIP \| HMVMX_UPDATED_GUEST_RFLAGS),
3492	("%#x\n", HMVMXCPU_GST_VALUE(pVCpu)));
3493	if (pMixedCtx->rip == EMGetInhibitInterruptsPC(pVCpu))
3494	{
3495	if (pMixedCtx->eflags.Bits.u1IF)
3496	uIntrState = VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI;
3497	else
3498	uIntrState = VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS;
3499	}
3500	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3501	{
3502	/*
3503	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
3504	* VT-x, the flag's condition to be cleared is met and thus the cleared state is correct.
3505	*/
3506	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3507	}
3508	}
3509
3510	/*
3511	* NMIs to the guest are blocked after an NMI is injected until the guest executes an IRET. We only
3512	* bother with virtual-NMI blocking when we have support for virtual NMIs in the CPU, otherwise
3513	* setting this would block host-NMIs and IRET will not clear the blocking.
3514	*
3515	* See Intel spec. 26.6.1 "Interruptibility state". See @bugref{7445}.
3516	*/
3517	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS)
3518	&& (pVCpu->hm.s.vmx.u32PinCtls & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI))
3519	{
3520	uIntrState \|= VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI;
3521	}
3522
3523	return uIntrState;
3524	}
3525
3526
3527	/**
3528	* Loads the guest's interruptibility-state into the guest-state area in the
3529	* VMCS.
3530	*
3531	* @returns VBox status code.
3532	* @param pVCpu The cross context virtual CPU structure.
3533	* @param uIntrState The interruptibility-state to set.
3534	*/
3535	static int hmR0VmxLoadGuestIntrState(PVMCPU pVCpu, uint32_t uIntrState)
3536	{
3537	NOREF(pVCpu);
3538	AssertMsg(!(uIntrState & 0xfffffff0), ("%#x\n", uIntrState)); /* Bits 31:4 MBZ. */
3539	Assert((uIntrState & 0x3) != 0x3); /* Block-by-STI and MOV SS cannot be simultaneously set. */
3540	int rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, uIntrState);
3541	AssertRC(rc);
3542	return rc;
3543	}
3544
3545
3546	/**
3547	* Loads the exception intercepts required for guest execution in the VMCS.
3548	*
3549	* @returns VBox status code.
3550	* @param pVCpu The cross context virtual CPU structure.
3551	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
3552	* out-of-sync. Make sure to update the required fields
3553	* before using them.
3554	*/
3555	static int hmR0VmxLoadGuestXcptIntercepts(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3556	{
3557	NOREF(pMixedCtx);
3558	int rc = VINF_SUCCESS;
3559	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
3560	{
3561	/* The remaining exception intercepts are handled elsewhere, e.g. in hmR0VmxLoadSharedCR0(). */
3562	if (pVCpu->hm.s.fGIMTrapXcptUD)
3563	pVCpu->hm.s.vmx.u32XcptBitmap \|= RT_BIT(X86_XCPT_UD);
3564	#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
3565	else
3566	pVCpu->hm.s.vmx.u32XcptBitmap &= ~RT_BIT(X86_XCPT_UD);
3567	#endif
3568
3569	Assert(pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT_32(X86_XCPT_AC));
3570	Assert(pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT_32(X86_XCPT_DB));
3571
3572	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap);
3573	AssertRCReturn(rc, rc);
3574
3575	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
3576	Log4(("Load[%RU32]: VMX_VMCS32_CTRL_EXCEPTION_BITMAP=%#RX64 fContextUseFlags=%#RX32\n", pVCpu->idCpu,
3577	pVCpu->hm.s.vmx.u32XcptBitmap, HMCPU_CF_VALUE(pVCpu)));
3578	}
3579	return rc;
3580	}
3581
3582
3583	/**
3584	* Loads the guest's RIP into the guest-state area in the VMCS.
3585	*
3586	* @returns VBox status code.
3587	* @param pVCpu The cross context virtual CPU structure.
3588	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
3589	* out-of-sync. Make sure to update the required fields
3590	* before using them.
3591	*
3592	* @remarks No-long-jump zone!!!
3593	*/
3594	static int hmR0VmxLoadGuestRip(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3595	{
3596	int rc = VINF_SUCCESS;
3597	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RIP))
3598	{
3599	rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_RIP, pMixedCtx->rip);
3600	AssertRCReturn(rc, rc);
3601
3602	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP);
3603	Log4(("Load[%RU32]: VMX_VMCS_GUEST_RIP=%#RX64 fContextUseFlags=%#RX32\n", pVCpu->idCpu, pMixedCtx->rip,
3604	HMCPU_CF_VALUE(pVCpu)));
3605	}
3606	return rc;
3607	}
3608
3609
3610	/**
3611	* Loads the guest's RSP into the guest-state area in the VMCS.
3612	*
3613	* @returns VBox status code.
3614	* @param pVCpu The cross context virtual CPU structure.
3615	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
3616	* out-of-sync. Make sure to update the required fields
3617	* before using them.
3618	*
3619	* @remarks No-long-jump zone!!!
3620	*/
3621	static int hmR0VmxLoadGuestRsp(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3622	{
3623	int rc = VINF_SUCCESS;
3624	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RSP))
3625	{
3626	rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_RSP, pMixedCtx->rsp);
3627	AssertRCReturn(rc, rc);
3628
3629	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RSP);
3630	Log4(("Load[%RU32]: VMX_VMCS_GUEST_RSP=%#RX64\n", pVCpu->idCpu, pMixedCtx->rsp));
3631	}
3632	return rc;
3633	}
3634
3635
3636	/**
3637	* Loads the guest's RFLAGS into the guest-state area in the VMCS.
3638	*
3639	* @returns VBox status code.
3640	* @param pVCpu The cross context virtual CPU structure.
3641	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
3642	* out-of-sync. Make sure to update the required fields
3643	* before using them.
3644	*
3645	* @remarks No-long-jump zone!!!
3646	*/
3647	static int hmR0VmxLoadGuestRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3648	{
3649	int rc = VINF_SUCCESS;
3650	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RFLAGS))
3651	{
3652	/* Intel spec. 2.3.1 "System Flags and Fields in IA-32e Mode" claims the upper 32-bits of RFLAGS are reserved (MBZ).
3653	Let us assert it as such and use 32-bit VMWRITE. */
3654	Assert(!(pMixedCtx->rflags.u64 >> 32));
3655	X86EFLAGS Eflags = pMixedCtx->eflags;
3656	/** @todo r=bird: There shall be no need to OR in X86_EFL_1 here, nor
3657	* shall there be any reason for clearing bits 63:22, 15, 5 and 3.
3658	* These will never be cleared/set, unless some other part of the VMM
3659	* code is buggy - in which case we're better of finding and fixing
3660	* those bugs than hiding them. */
3661	Assert(Eflags.u32 & X86_EFL_RA1_MASK);
3662	Assert(!(Eflags.u32 & ~(X86_EFL_1 \| X86_EFL_LIVE_MASK)));
3663	Eflags.u32 &= VMX_EFLAGS_RESERVED_0; /* Bits 22-31, 15, 5 & 3 MBZ. */
3664	Eflags.u32 \|= VMX_EFLAGS_RESERVED_1; /* Bit 1 MB1. */
3665
3666	/*
3667	* If we're emulating real-mode using Virtual 8086 mode, save the real-mode eflags so we can restore them on VM-exit.
3668	* Modify the real-mode guest's eflags so that VT-x can run the real-mode guest code under Virtual 8086 mode.
3669	*/
3670	if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3671	{
3672	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
3673	Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
3674	pVCpu->hm.s.vmx.RealMode.Eflags.u32 = Eflags.u32; /* Save the original eflags of the real-mode guest. */
3675	Eflags.Bits.u1VM = 1; /* Set the Virtual 8086 mode bit. */
3676	Eflags.Bits.u2IOPL = 0; /* Change IOPL to 0, otherwise certain instructions won't fault. */
3677	}
3678
3679	rc = VMXWriteVmcs32(VMX_VMCS_GUEST_RFLAGS, Eflags.u32);
3680	AssertRCReturn(rc, rc);
3681
3682	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RFLAGS);
3683	Log4(("Load[%RU32]: VMX_VMCS_GUEST_RFLAGS=%#RX32\n", pVCpu->idCpu, Eflags.u32));
3684	}
3685	return rc;
3686	}
3687
3688
3689	/**
3690	* Loads the guest RIP, RSP and RFLAGS into the guest-state area in the VMCS.
3691	*
3692	* @returns VBox status code.
3693	* @param pVCpu The cross context virtual CPU structure.
3694	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
3695	* out-of-sync. Make sure to update the required fields
3696	* before using them.
3697	*
3698	* @remarks No-long-jump zone!!!
3699	*/
3700	DECLINLINE(int) hmR0VmxLoadGuestRipRspRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3701	{
3702	int rc = hmR0VmxLoadGuestRip(pVCpu, pMixedCtx);
3703	rc \|= hmR0VmxLoadGuestRsp(pVCpu, pMixedCtx);
3704	rc \|= hmR0VmxLoadGuestRflags(pVCpu, pMixedCtx);
3705	AssertRCReturn(rc, rc);
3706	return rc;
3707	}
3708
3709
3710	/**
3711	* Loads the guest CR0 control register into the guest-state area in the VMCS.
3712	* CR0 is partially shared with the host and we have to consider the FPU bits.
3713	*
3714	* @returns VBox status code.
3715	* @param pVCpu The cross context virtual CPU structure.
3716	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
3717	* out-of-sync. Make sure to update the required fields
3718	* before using them.
3719	*
3720	* @remarks No-long-jump zone!!!
3721	*/
3722	static int hmR0VmxLoadSharedCR0(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3723	{
3724	/*
3725	* Guest CR0.
3726	* Guest FPU.
3727	*/
3728	int rc = VINF_SUCCESS;
3729	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
3730	{
3731	Assert(!(pMixedCtx->cr0 >> 32));
3732	uint32_t u32GuestCR0 = pMixedCtx->cr0;
3733	PVM pVM = pVCpu->CTX_SUFF(pVM);
3734
3735	/* The guest's view (read access) of its CR0 is unblemished. */
3736	rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_READ_SHADOW, u32GuestCR0);
3737	AssertRCReturn(rc, rc);
3738	Log4(("Load[%RU32]: VMX_VMCS_CTRL_CR0_READ_SHADOW=%#RX32\n", pVCpu->idCpu, u32GuestCR0));
3739
3740	/* Setup VT-x's view of the guest CR0. */
3741	/* Minimize VM-exits due to CR3 changes when we have NestedPaging. */
3742	if (pVM->hm.s.fNestedPaging)
3743	{
3744	if (CPUMIsGuestPagingEnabledEx(pMixedCtx))
3745	{
3746	/* The guest has paging enabled, let it access CR3 without causing a VM-exit if supported. */
3747	pVCpu->hm.s.vmx.u32ProcCtls &= ~( VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT
3748	\| VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
3749	}
3750	else
3751	{
3752	/* The guest doesn't have paging enabled, make CR3 access cause a VM-exit to update our shadow. */
3753	pVCpu->hm.s.vmx.u32ProcCtls \|= VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT
3754	\| VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT;
3755	}
3756
3757	/* If we have unrestricted guest execution, we never have to intercept CR3 reads. */
3758	if (pVM->hm.s.vmx.fUnrestrictedGuest)
3759	pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT;
3760
3761	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
3762	AssertRCReturn(rc, rc);
3763	}
3764	else
3765	u32GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF VM-exit. */
3766
3767	/*
3768	* Guest FPU bits.
3769	* Intel spec. 23.8 "Restrictions on VMX operation" mentions that CR0.NE bit must always be set on the first
3770	* CPUs to support VT-x and no mention of with regards to UX in VM-entry checks.
3771	*/
3772	u32GuestCR0 \|= X86_CR0_NE;
3773	bool fInterceptNM = false;
3774	if (CPUMIsGuestFPUStateActive(pVCpu))
3775	{
3776	fInterceptNM = false; /* Guest FPU active, no need to VM-exit on #NM. */
3777	/* The guest should still get #NM exceptions when it expects it to, so we should not clear TS & MP bits here.
3778	We're only concerned about -us- not intercepting #NMs when the guest-FPU is active. Not the guest itself! */
3779	}
3780	else
3781	{
3782	fInterceptNM = true; /* Guest FPU inactive, VM-exit on #NM for lazy FPU loading. */
3783	u32GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
3784	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
3785	}
3786
3787	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
3788	bool fInterceptMF = false;
3789	if (!(pMixedCtx->cr0 & X86_CR0_NE))
3790	fInterceptMF = true;
3791
3792	/* Finally, intercept all exceptions as we cannot directly inject them in real-mode, see hmR0VmxInjectEventVmcs(). */
3793	if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
3794	{
3795	Assert(PDMVmmDevHeapIsEnabled(pVM));
3796	Assert(pVM->hm.s.vmx.pRealModeTSS);
3797	pVCpu->hm.s.vmx.u32XcptBitmap \|= HMVMX_REAL_MODE_XCPT_MASK;
3798	fInterceptNM = true;
3799	fInterceptMF = true;
3800	}
3801	else
3802	{
3803	/* For now, cleared here as mode-switches can happen outside HM/VT-x. See @bugref{7626#c11}. */
3804	pVCpu->hm.s.vmx.u32XcptBitmap &= ~HMVMX_REAL_MODE_XCPT_MASK;
3805	}
3806	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
3807
3808	if (fInterceptNM)
3809	pVCpu->hm.s.vmx.u32XcptBitmap \|= RT_BIT(X86_XCPT_NM);
3810	else
3811	pVCpu->hm.s.vmx.u32XcptBitmap &= ~RT_BIT(X86_XCPT_NM);
3812
3813	if (fInterceptMF)
3814	pVCpu->hm.s.vmx.u32XcptBitmap \|= RT_BIT(X86_XCPT_MF);
3815	else
3816	pVCpu->hm.s.vmx.u32XcptBitmap &= ~RT_BIT(X86_XCPT_MF);
3817
3818	/* Additional intercepts for debugging, define these yourself explicitly. */
3819	#ifdef HMVMX_ALWAYS_TRAP_ALL_XCPTS
3820	pVCpu->hm.s.vmx.u32XcptBitmap \|= 0
3821	\| RT_BIT(X86_XCPT_BP)
3822	\| RT_BIT(X86_XCPT_DE)
3823	\| RT_BIT(X86_XCPT_NM)
3824	\| RT_BIT(X86_XCPT_TS)
3825	\| RT_BIT(X86_XCPT_UD)
3826	\| RT_BIT(X86_XCPT_NP)
3827	\| RT_BIT(X86_XCPT_SS)
3828	\| RT_BIT(X86_XCPT_GP)
3829	\| RT_BIT(X86_XCPT_PF)
3830	\| RT_BIT(X86_XCPT_MF)
3831	;
3832	#elif defined(HMVMX_ALWAYS_TRAP_PF)
3833	pVCpu->hm.s.vmx.u32XcptBitmap \|= RT_BIT(X86_XCPT_PF);
3834	#endif
3835
3836	Assert(pVM->hm.s.fNestedPaging \|\| (pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT(X86_XCPT_PF)));
3837
3838	/* Set/clear the CR0 specific bits along with their exceptions (PE, PG, CD, NW). */
3839	uint32_t uSetCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
3840	uint32_t uZapCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 \| pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
3841	if (pVM->hm.s.vmx.fUnrestrictedGuest) /* Exceptions for unrestricted-guests for fixed CR0 bits (PE, PG). */
3842	uSetCR0 &= ~(X86_CR0_PE \| X86_CR0_PG);
3843	else
3844	Assert((uSetCR0 & (X86_CR0_PE \| X86_CR0_PG)) == (X86_CR0_PE \| X86_CR0_PG));
3845
3846	u32GuestCR0 \|= uSetCR0;
3847	u32GuestCR0 &= uZapCR0;
3848	u32GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW); /* Always enable caching. */
3849
3850	/* Write VT-x's view of the guest CR0 into the VMCS. */
3851	rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR0, u32GuestCR0);
3852	AssertRCReturn(rc, rc);
3853	Log4(("Load[%RU32]: VMX_VMCS_GUEST_CR0=%#RX32 (uSetCR0=%#RX32 uZapCR0=%#RX32)\n", pVCpu->idCpu, u32GuestCR0, uSetCR0,
3854	uZapCR0));
3855
3856	/*
3857	* CR0 is shared between host and guest along with a CR0 read shadow. Therefore, certain bits must not be changed
3858	* by the guest because VT-x ignores saving/restoring them (namely CD, ET, NW) and for certain other bits
3859	* we want to be notified immediately of guest CR0 changes (e.g. PG to update our shadow page tables).
3860	*/
3861	uint32_t u32CR0Mask = 0;
3862	u32CR0Mask = X86_CR0_PE
3863	\| X86_CR0_NE
3864	\| X86_CR0_WP
3865	\| X86_CR0_PG
3866	\| X86_CR0_ET /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.ET */
3867	\| X86_CR0_CD /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.CD */
3868	\| X86_CR0_NW; /* Bit ignored on VM-entry and VM-exit. Don't let the guest modify the host CR0.NW */
3869
3870	/** @todo Avoid intercepting CR0.PE with unrestricted guests. Fix PGM
3871	* enmGuestMode to be in-sync with the current mode. See @bugref{6398}
3872	* and @bugref{6944}. */
3873	#if 0
3874	if (pVM->hm.s.vmx.fUnrestrictedGuest)
3875	u32CR0Mask &= ~X86_CR0_PE;
3876	#endif
3877	if (pVM->hm.s.fNestedPaging)
3878	u32CR0Mask &= ~X86_CR0_WP;
3879
3880	/* If the guest FPU state is active, don't need to VM-exit on writes to FPU related bits in CR0. */
3881	if (fInterceptNM)
3882	{
3883	u32CR0Mask \|= X86_CR0_TS
3884	\| X86_CR0_MP;
3885	}
3886
3887	/* Write the CR0 mask into the VMCS and update the VCPU's copy of the current CR0 mask. */
3888	pVCpu->hm.s.vmx.u32CR0Mask = u32CR0Mask;
3889	rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_MASK, u32CR0Mask);
3890	AssertRCReturn(rc, rc);
3891	Log4(("Load[%RU32]: VMX_VMCS_CTRL_CR0_MASK=%#RX32\n", pVCpu->idCpu, u32CR0Mask));
3892
3893	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
3894	}
3895	return rc;
3896	}
3897
3898
3899	/**
3900	* Loads the guest control registers (CR3, CR4) into the guest-state area
3901	* in the VMCS.
3902	*
3903	* @returns VBox strict status code.
3904	* @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
3905	* without unrestricted guest access and the VMMDev is not presently
3906	* mapped (e.g. EFI32).
3907	*
3908	* @param pVCpu The cross context virtual CPU structure.
3909	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
3910	* out-of-sync. Make sure to update the required fields
3911	* before using them.
3912	*
3913	* @remarks No-long-jump zone!!!
3914	*/
3915	static VBOXSTRICTRC hmR0VmxLoadGuestCR3AndCR4(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
3916	{
3917	int rc = VINF_SUCCESS;
3918	PVM pVM = pVCpu->CTX_SUFF(pVM);
3919
3920	/*
3921	* Guest CR2.
3922	* It's always loaded in the assembler code. Nothing to do here.
3923	*/
3924
3925	/*
3926	* Guest CR3.
3927	*/
3928	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
3929	{
3930	RTGCPHYS GCPhysGuestCR3 = NIL_RTGCPHYS;
3931	if (pVM->hm.s.fNestedPaging)
3932	{
3933	pVCpu->hm.s.vmx.HCPhysEPTP = PGMGetHyperCR3(pVCpu);
3934
3935	/* Validate. See Intel spec. 28.2.2 "EPT Translation Mechanism" and 24.6.11 "Extended-Page-Table Pointer (EPTP)" */
3936	Assert(pVCpu->hm.s.vmx.HCPhysEPTP);
3937	Assert(!(pVCpu->hm.s.vmx.HCPhysEPTP & UINT64_C(0xfff0000000000000)));
3938	Assert(!(pVCpu->hm.s.vmx.HCPhysEPTP & 0xfff));
3939
3940	/* VMX_EPT_MEMTYPE_WB support is already checked in hmR0VmxSetupTaggedTlb(). */
3941	pVCpu->hm.s.vmx.HCPhysEPTP \|= VMX_EPT_MEMTYPE_WB
3942	\| (VMX_EPT_PAGE_WALK_LENGTH_DEFAULT << VMX_EPT_PAGE_WALK_LENGTH_SHIFT);
3943
3944	/* Validate. See Intel spec. 26.2.1 "Checks on VMX Controls" */
3945	AssertMsg( ((pVCpu->hm.s.vmx.HCPhysEPTP >> 3) & 0x07) == 3 /* Bits 3:5 (EPT page walk length - 1) must be 3. */
3946	&& ((pVCpu->hm.s.vmx.HCPhysEPTP >> 7) & 0x1f) == 0, /* Bits 7:11 MBZ. */
3947	("EPTP %#RX64\n", pVCpu->hm.s.vmx.HCPhysEPTP));
3948	AssertMsg( !((pVCpu->hm.s.vmx.HCPhysEPTP >> 6) & 0x01) /* Bit 6 (EPT accessed & dirty bit). */
3949	\|\| (pVM->hm.s.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY),
3950	("EPTP accessed/dirty bit not supported by CPU but set %#RX64\n", pVCpu->hm.s.vmx.HCPhysEPTP));
3951
3952	rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, pVCpu->hm.s.vmx.HCPhysEPTP);
3953	AssertRCReturn(rc, rc);
3954	Log4(("Load[%RU32]: VMX_VMCS64_CTRL_EPTP_FULL=%#RX64\n", pVCpu->idCpu, pVCpu->hm.s.vmx.HCPhysEPTP));
3955
3956	if ( pVM->hm.s.vmx.fUnrestrictedGuest
3957	\|\| CPUMIsGuestPagingEnabledEx(pMixedCtx))
3958	{
3959	/* If the guest is in PAE mode, pass the PDPEs to VT-x using the VMCS fields. */
3960	if (CPUMIsGuestInPAEModeEx(pMixedCtx))
3961	{
3962	rc = PGMGstGetPaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
3963	AssertRCReturn(rc, rc);
3964	rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, pVCpu->hm.s.aPdpes[0].u);
3965	rc \|= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, pVCpu->hm.s.aPdpes[1].u);
3966	rc \|= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, pVCpu->hm.s.aPdpes[2].u);
3967	rc \|= VMXWriteVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, pVCpu->hm.s.aPdpes[3].u);
3968	AssertRCReturn(rc, rc);
3969	}
3970
3971	/* The guest's view of its CR3 is unblemished with Nested Paging when the guest is using paging or we
3972	have Unrestricted Execution to handle the guest when it's not using paging. */
3973	GCPhysGuestCR3 = pMixedCtx->cr3;
3974	}
3975	else
3976	{
3977	/*
3978	* The guest is not using paging, but the CPU (VT-x) has to. While the guest thinks it accesses physical memory
3979	* directly, we use our identity-mapped page table to map guest-linear to guest-physical addresses.
3980	* EPT takes care of translating it to host-physical addresses.
3981	*/
3982	RTGCPHYS GCPhys;
3983	Assert(pVM->hm.s.vmx.pNonPagingModeEPTPageTable);
3984
3985	/* We obtain it here every time as the guest could have relocated this PCI region. */
3986	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
3987	if (RT_SUCCESS(rc))
3988	{ /* likely */ }
3989	else if (rc == VERR_PDM_DEV_HEAP_R3_TO_GCPHYS)
3990	{
3991	Log4(("Load[%RU32]: VERR_PDM_DEV_HEAP_R3_TO_GCPHYS -> VINF_EM_RESCHEDULE_REM\n", pVCpu->idCpu));
3992	return VINF_EM_RESCHEDULE_REM; /* We cannot execute now, switch to REM/IEM till the guest maps in VMMDev. */
3993	}
3994	else
3995	AssertMsgFailedReturn(("%Rrc\n", rc), rc);
3996
3997	GCPhysGuestCR3 = GCPhys;
3998	}
3999
4000	Log4(("Load[%RU32]: VMX_VMCS_GUEST_CR3=%#RGp (GstN)\n", pVCpu->idCpu, GCPhysGuestCR3));
4001	rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_CR3, GCPhysGuestCR3);
4002	}
4003	else
4004	{
4005	/* Non-nested paging case, just use the hypervisor's CR3. */
4006	RTHCPHYS HCPhysGuestCR3 = PGMGetHyperCR3(pVCpu);
4007
4008	Log4(("Load[%RU32]: VMX_VMCS_GUEST_CR3=%#RHv (HstN)\n", pVCpu->idCpu, HCPhysGuestCR3));
4009	rc = VMXWriteVmcsHstN(VMX_VMCS_GUEST_CR3, HCPhysGuestCR3);
4010	}
4011	AssertRCReturn(rc, rc);
4012
4013	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
4014	}
4015
4016	/*
4017	* Guest CR4.
4018	* ASSUMES this is done everytime we get in from ring-3! (XCR0)
4019	*/
4020	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
4021	{
4022	Assert(!(pMixedCtx->cr4 >> 32));
4023	uint32_t u32GuestCR4 = pMixedCtx->cr4;
4024
4025	/* The guest's view of its CR4 is unblemished. */
4026	rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_READ_SHADOW, u32GuestCR4);
4027	AssertRCReturn(rc, rc);
4028	Log4(("Load[%RU32]: VMX_VMCS_CTRL_CR4_READ_SHADOW=%#RX32\n", pVCpu->idCpu, u32GuestCR4));
4029
4030	/* Setup VT-x's view of the guest CR4. */
4031	/*
4032	* If we're emulating real-mode using virtual-8086 mode, we want to redirect software interrupts to the 8086 program
4033	* interrupt handler. Clear the VME bit (the interrupt redirection bitmap is already all 0, see hmR3InitFinalizeR0())
4034	* See Intel spec. 20.2 "Software Interrupt Handling Methods While in Virtual-8086 Mode".
4035	*/
4036	if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4037	{
4038	Assert(pVM->hm.s.vmx.pRealModeTSS);
4039	Assert(PDMVmmDevHeapIsEnabled(pVM));
4040	u32GuestCR4 &= ~X86_CR4_VME;
4041	}
4042
4043	if (pVM->hm.s.fNestedPaging)
4044	{
4045	if ( !CPUMIsGuestPagingEnabledEx(pMixedCtx)
4046	&& !pVM->hm.s.vmx.fUnrestrictedGuest)
4047	{
4048	/* We use 4 MB pages in our identity mapping page table when the guest doesn't have paging. */
4049	u32GuestCR4 \|= X86_CR4_PSE;
4050	/* Our identity mapping is a 32-bit page directory. */
4051	u32GuestCR4 &= ~X86_CR4_PAE;
4052	}
4053	/* else use guest CR4.*/
4054	}
4055	else
4056	{
4057	/*
4058	* The shadow paging modes and guest paging modes are different, the shadow is in accordance with the host
4059	* paging mode and thus we need to adjust VT-x's view of CR4 depending on our shadow page tables.
4060	*/
4061	switch (pVCpu->hm.s.enmShadowMode)
4062	{
4063	case PGMMODE_REAL: /* Real-mode. */
4064	case PGMMODE_PROTECTED: /* Protected mode without paging. */
4065	case PGMMODE_32_BIT: /* 32-bit paging. */
4066	{
4067	u32GuestCR4 &= ~X86_CR4_PAE;
4068	break;
4069	}
4070
4071	case PGMMODE_PAE: /* PAE paging. */
4072	case PGMMODE_PAE_NX: /* PAE paging with NX. */
4073	{
4074	u32GuestCR4 \|= X86_CR4_PAE;
4075	break;
4076	}
4077
4078	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
4079	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
4080	#ifdef VBOX_ENABLE_64_BITS_GUESTS
4081	break;
4082	#endif
4083	default:
4084	AssertFailed();
4085	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
4086	}
4087	}
4088
4089	/* We need to set and clear the CR4 specific bits here (mainly the X86_CR4_VMXE bit). */
4090	uint64_t uSetCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
4091	uint64_t uZapCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 \| pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
4092	u32GuestCR4 \|= uSetCR4;
4093	u32GuestCR4 &= uZapCR4;
4094
4095	/* Write VT-x's view of the guest CR4 into the VMCS. */
4096	Log4(("Load[%RU32]: VMX_VMCS_GUEST_CR4=%#RX32 (Set=%#RX32 Zap=%#RX32)\n", pVCpu->idCpu, u32GuestCR4, uSetCR4, uZapCR4));
4097	rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR4, u32GuestCR4);
4098	AssertRCReturn(rc, rc);
4099
4100	/* Setup CR4 mask. CR4 flags owned by the host, if the guest attempts to change them, that would cause a VM-exit. */
4101	uint32_t u32CR4Mask = X86_CR4_VME
4102	\| X86_CR4_PAE
4103	\| X86_CR4_PGE
4104	\| X86_CR4_PSE
4105	\| X86_CR4_VMXE;
4106	if (pVM->cpum.ro.HostFeatures.fXSaveRstor)
4107	u32CR4Mask \|= X86_CR4_OSXSAVE;
4108	pVCpu->hm.s.vmx.u32CR4Mask = u32CR4Mask;
4109	rc = VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_MASK, u32CR4Mask);
4110	AssertRCReturn(rc, rc);
4111
4112	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
4113	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pMixedCtx->cr4 & X86_CR4_OSXSAVE) && pMixedCtx->aXcr[0] != ASMGetXcr0();
4114
4115	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
4116	}
4117	return rc;
4118	}
4119
4120
4121	/**
4122	* Loads the guest debug registers into the guest-state area in the VMCS.
4123	*
4124	* This also sets up whether \#DB and MOV DRx accesses cause VM-exits.
4125	*
4126	* The guest debug bits are partially shared with the host (e.g. DR6, DR0-3).
4127	*
4128	* @returns VBox status code.
4129	* @param pVCpu The cross context virtual CPU structure.
4130	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
4131	* out-of-sync. Make sure to update the required fields
4132	* before using them.
4133	*
4134	* @remarks No-long-jump zone!!!
4135	*/
4136	static int hmR0VmxLoadSharedDebugState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
4137	{
4138	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
4139	return VINF_SUCCESS;
4140
4141	#ifdef VBOX_STRICT
4142	/* Validate. Intel spec. 26.3.1.1 "Checks on Guest Controls Registers, Debug Registers, MSRs" */
4143	if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG)
4144	{
4145	/* Validate. Intel spec. 17.2 "Debug Registers", recompiler paranoia checks. */
4146	Assert((pMixedCtx->dr[7] & (X86_DR7_MBZ_MASK \| X86_DR7_RAZ_MASK)) == 0); /* Bits 63:32, 15, 14, 12, 11 are reserved. */
4147	Assert((pMixedCtx->dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK); /* Bit 10 is reserved (RA1). */
4148	}
4149	#endif
4150
4151	int rc;
4152	PVM pVM = pVCpu->CTX_SUFF(pVM);
4153	bool fSteppingDB = false;
4154	bool fInterceptMovDRx = false;
4155	if (pVCpu->hm.s.fSingleInstruction)
4156	{
4157	/* If the CPU supports the monitor trap flag, use it for single stepping in DBGF and avoid intercepting #DB. */
4158	if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG)
4159	{
4160	pVCpu->hm.s.vmx.u32ProcCtls \|= VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG;
4161	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
4162	AssertRCReturn(rc, rc);
4163	Assert(fSteppingDB == false);
4164	}
4165	else
4166	{
4167	pMixedCtx->eflags.u32 \|= X86_EFL_TF;
4168	pVCpu->hm.s.fClearTrapFlag = true;
4169	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RFLAGS);
4170	fSteppingDB = true;
4171	}
4172	}
4173
4174	if ( fSteppingDB
4175	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
4176	{
4177	/*
4178	* Use the combined guest and host DRx values found in the hypervisor
4179	* register set because the debugger has breakpoints active or someone
4180	* is single stepping on the host side without a monitor trap flag.
4181	*
4182	* Note! DBGF expects a clean DR6 state before executing guest code.
4183	*/
4184	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4185	if ( CPUMIsGuestInLongModeEx(pMixedCtx)
4186	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
4187	{
4188	CPUMR0LoadHyperDebugState(pVCpu, true /* include DR6 */);
4189	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
4190	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
4191	}
4192	else
4193	#endif
4194	if (!CPUMIsHyperDebugStateActive(pVCpu))
4195	{
4196	CPUMR0LoadHyperDebugState(pVCpu, true /* include DR6 */);
4197	Assert(CPUMIsHyperDebugStateActive(pVCpu));
4198	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
4199	}
4200
4201	/* Update DR7. (The other DRx values are handled by CPUM one way or the other.) */
4202	rc = VMXWriteVmcs32(VMX_VMCS_GUEST_DR7, (uint32_t)CPUMGetHyperDR7(pVCpu));
4203	AssertRCReturn(rc, rc);
4204
4205	pVCpu->hm.s.fUsingHyperDR7 = true;
4206	fInterceptMovDRx = true;
4207	}
4208	else
4209	{
4210	/*
4211	* If the guest has enabled debug registers, we need to load them prior to
4212	* executing guest code so they'll trigger at the right time.
4213	*/
4214	if (pMixedCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
4215	{
4216	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4217	if ( CPUMIsGuestInLongModeEx(pMixedCtx)
4218	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
4219	{
4220	CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
4221	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
4222	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
4223	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
4224	}
4225	else
4226	#endif
4227	if (!CPUMIsGuestDebugStateActive(pVCpu))
4228	{
4229	CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
4230	Assert(CPUMIsGuestDebugStateActive(pVCpu));
4231	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
4232	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
4233	}
4234	Assert(!fInterceptMovDRx);
4235	}
4236	/*
4237	* If no debugging enabled, we'll lazy load DR0-3. Unlike on AMD-V, we
4238	* must intercept #DB in order to maintain a correct DR6 guest value, and
4239	* because we need to intercept it to prevent nested #DBs from hanging the
4240	* CPU, we end up always having to intercept it. See hmR0VmxInitXcptBitmap.
4241	*/
4242	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4243	else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
4244	&& !CPUMIsGuestDebugStateActive(pVCpu))
4245	#else
4246	else if (!CPUMIsGuestDebugStateActive(pVCpu))
4247	#endif
4248	{
4249	fInterceptMovDRx = true;
4250	}
4251
4252	/* Update guest DR7. */
4253	rc = VMXWriteVmcs32(VMX_VMCS_GUEST_DR7, pMixedCtx->dr[7]);
4254	AssertRCReturn(rc, rc);
4255
4256	pVCpu->hm.s.fUsingHyperDR7 = false;
4257	}
4258
4259	/*
4260	* Update the processor-based VM-execution controls regarding intercepting MOV DRx instructions.
4261	*/
4262	if (fInterceptMovDRx)
4263	pVCpu->hm.s.vmx.u32ProcCtls \|= VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT;
4264	else
4265	pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT;
4266	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
4267	AssertRCReturn(rc, rc);
4268
4269	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
4270	return VINF_SUCCESS;
4271	}
4272
4273
4274	#ifdef VBOX_STRICT
4275	/**
4276	* Strict function to validate segment registers.
4277	*
4278	* @remarks ASSUMES CR0 is up to date.
4279	*/
4280	static void hmR0VmxValidateSegmentRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4281	{
4282	/* Validate segment registers. See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers". */
4283	/* NOTE: The reason we check for attribute value 0 and not just the unusable bit here is because hmR0VmxWriteSegmentReg()
4284	* only updates the VMCS' copy of the value with the unusable bit and doesn't change the guest-context value. */
4285	if ( !pVM->hm.s.vmx.fUnrestrictedGuest
4286	&& ( !CPUMIsGuestInRealModeEx(pCtx)
4287	&& !CPUMIsGuestInV86ModeEx(pCtx)))
4288	{
4289	/* Protected mode checks */
4290	/* CS */
4291	Assert(pCtx->cs.Attr.n.u1Present);
4292	Assert(!(pCtx->cs.Attr.u & 0xf00));
4293	Assert(!(pCtx->cs.Attr.u & 0xfffe0000));
4294	Assert( (pCtx->cs.u32Limit & 0xfff) == 0xfff
4295	\|\| !(pCtx->cs.Attr.n.u1Granularity));
4296	Assert( !(pCtx->cs.u32Limit & 0xfff00000)
4297	\|\| (pCtx->cs.Attr.n.u1Granularity));
4298	/* CS cannot be loaded with NULL in protected mode. */
4299	Assert(pCtx->cs.Attr.u && !(pCtx->cs.Attr.u & X86DESCATTR_UNUSABLE)); /** @todo is this really true even for 64-bit CS? */
4300	if (pCtx->cs.Attr.n.u4Type == 9 \|\| pCtx->cs.Attr.n.u4Type == 11)
4301	Assert(pCtx->cs.Attr.n.u2Dpl == pCtx->ss.Attr.n.u2Dpl);
4302	else if (pCtx->cs.Attr.n.u4Type == 13 \|\| pCtx->cs.Attr.n.u4Type == 15)
4303	Assert(pCtx->cs.Attr.n.u2Dpl <= pCtx->ss.Attr.n.u2Dpl);
4304	else
4305	AssertMsgFailed(("Invalid CS Type %#x\n", pCtx->cs.Attr.n.u2Dpl));
4306	/* SS */
4307	Assert((pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL));
4308	Assert(pCtx->ss.Attr.n.u2Dpl == (pCtx->ss.Sel & X86_SEL_RPL));
4309	if ( !(pCtx->cr0 & X86_CR0_PE)
4310	\|\| pCtx->cs.Attr.n.u4Type == 3)
4311	{
4312	Assert(!pCtx->ss.Attr.n.u2Dpl);
4313	}
4314	if (pCtx->ss.Attr.u && !(pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE))
4315	{
4316	Assert((pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL));
4317	Assert(pCtx->ss.Attr.n.u4Type == 3 \|\| pCtx->ss.Attr.n.u4Type == 7);
4318	Assert(pCtx->ss.Attr.n.u1Present);
4319	Assert(!(pCtx->ss.Attr.u & 0xf00));
4320	Assert(!(pCtx->ss.Attr.u & 0xfffe0000));
4321	Assert( (pCtx->ss.u32Limit & 0xfff) == 0xfff
4322	\|\| !(pCtx->ss.Attr.n.u1Granularity));
4323	Assert( !(pCtx->ss.u32Limit & 0xfff00000)
4324	\|\| (pCtx->ss.Attr.n.u1Granularity));
4325	}
4326	/* DS, ES, FS, GS - only check for usable selectors, see hmR0VmxWriteSegmentReg(). */
4327	if (pCtx->ds.Attr.u && !(pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE))
4328	{
4329	Assert(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4330	Assert(pCtx->ds.Attr.n.u1Present);
4331	Assert(pCtx->ds.Attr.n.u4Type > 11 \|\| pCtx->ds.Attr.n.u2Dpl >= (pCtx->ds.Sel & X86_SEL_RPL));
4332	Assert(!(pCtx->ds.Attr.u & 0xf00));
4333	Assert(!(pCtx->ds.Attr.u & 0xfffe0000));
4334	Assert( (pCtx->ds.u32Limit & 0xfff) == 0xfff
4335	\|\| !(pCtx->ds.Attr.n.u1Granularity));
4336	Assert( !(pCtx->ds.u32Limit & 0xfff00000)
4337	\|\| (pCtx->ds.Attr.n.u1Granularity));
4338	Assert( !(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4339	\|\| (pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_READ));
4340	}
4341	if (pCtx->es.Attr.u && !(pCtx->es.Attr.u & X86DESCATTR_UNUSABLE))
4342	{
4343	Assert(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4344	Assert(pCtx->es.Attr.n.u1Present);
4345	Assert(pCtx->es.Attr.n.u4Type > 11 \|\| pCtx->es.Attr.n.u2Dpl >= (pCtx->es.Sel & X86_SEL_RPL));
4346	Assert(!(pCtx->es.Attr.u & 0xf00));
4347	Assert(!(pCtx->es.Attr.u & 0xfffe0000));
4348	Assert( (pCtx->es.u32Limit & 0xfff) == 0xfff
4349	\|\| !(pCtx->es.Attr.n.u1Granularity));
4350	Assert( !(pCtx->es.u32Limit & 0xfff00000)
4351	\|\| (pCtx->es.Attr.n.u1Granularity));
4352	Assert( !(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4353	\|\| (pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_READ));
4354	}
4355	if (pCtx->fs.Attr.u && !(pCtx->fs.Attr.u & X86DESCATTR_UNUSABLE))
4356	{
4357	Assert(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4358	Assert(pCtx->fs.Attr.n.u1Present);
4359	Assert(pCtx->fs.Attr.n.u4Type > 11 \|\| pCtx->fs.Attr.n.u2Dpl >= (pCtx->fs.Sel & X86_SEL_RPL));
4360	Assert(!(pCtx->fs.Attr.u & 0xf00));
4361	Assert(!(pCtx->fs.Attr.u & 0xfffe0000));
4362	Assert( (pCtx->fs.u32Limit & 0xfff) == 0xfff
4363	\|\| !(pCtx->fs.Attr.n.u1Granularity));
4364	Assert( !(pCtx->fs.u32Limit & 0xfff00000)
4365	\|\| (pCtx->fs.Attr.n.u1Granularity));
4366	Assert( !(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4367	\|\| (pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_READ));
4368	}
4369	if (pCtx->gs.Attr.u && !(pCtx->gs.Attr.u & X86DESCATTR_UNUSABLE))
4370	{
4371	Assert(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED);
4372	Assert(pCtx->gs.Attr.n.u1Present);
4373	Assert(pCtx->gs.Attr.n.u4Type > 11 \|\| pCtx->gs.Attr.n.u2Dpl >= (pCtx->gs.Sel & X86_SEL_RPL));
4374	Assert(!(pCtx->gs.Attr.u & 0xf00));
4375	Assert(!(pCtx->gs.Attr.u & 0xfffe0000));
4376	Assert( (pCtx->gs.u32Limit & 0xfff) == 0xfff
4377	\|\| !(pCtx->gs.Attr.n.u1Granularity));
4378	Assert( !(pCtx->gs.u32Limit & 0xfff00000)
4379	\|\| (pCtx->gs.Attr.n.u1Granularity));
4380	Assert( !(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
4381	\|\| (pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_READ));
4382	}
4383	/* 64-bit capable CPUs. */
4384	# if HC_ARCH_BITS == 64
4385	Assert(!(pCtx->cs.u64Base >> 32));
4386	Assert(!pCtx->ss.Attr.u \|\| !(pCtx->ss.u64Base >> 32));
4387	Assert(!pCtx->ds.Attr.u \|\| !(pCtx->ds.u64Base >> 32));
4388	Assert(!pCtx->es.Attr.u \|\| !(pCtx->es.u64Base >> 32));
4389	# endif
4390	}
4391	else if ( CPUMIsGuestInV86ModeEx(pCtx)
4392	\|\| ( CPUMIsGuestInRealModeEx(pCtx)
4393	&& !pVM->hm.s.vmx.fUnrestrictedGuest))
4394	{
4395	/* Real and v86 mode checks. */
4396	/* hmR0VmxWriteSegmentReg() writes the modified in VMCS. We want what we're feeding to VT-x. */
4397	uint32_t u32CSAttr, u32SSAttr, u32DSAttr, u32ESAttr, u32FSAttr, u32GSAttr;
4398	if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4399	{
4400	u32CSAttr = 0xf3; u32SSAttr = 0xf3; u32DSAttr = 0xf3; u32ESAttr = 0xf3; u32FSAttr = 0xf3; u32GSAttr = 0xf3;
4401	}
4402	else
4403	{
4404	u32CSAttr = pCtx->cs.Attr.u; u32SSAttr = pCtx->ss.Attr.u; u32DSAttr = pCtx->ds.Attr.u;
4405	u32ESAttr = pCtx->es.Attr.u; u32FSAttr = pCtx->fs.Attr.u; u32GSAttr = pCtx->gs.Attr.u;
4406	}
4407
4408	/* CS */
4409	AssertMsg((pCtx->cs.u64Base == (uint64_t)pCtx->cs.Sel << 4), ("CS base %#x %#x\n", pCtx->cs.u64Base, pCtx->cs.Sel));
4410	Assert(pCtx->cs.u32Limit == 0xffff);
4411	Assert(u32CSAttr == 0xf3);
4412	/* SS */
4413	Assert(pCtx->ss.u64Base == (uint64_t)pCtx->ss.Sel << 4);
4414	Assert(pCtx->ss.u32Limit == 0xffff);
4415	Assert(u32SSAttr == 0xf3);
4416	/* DS */
4417	Assert(pCtx->ds.u64Base == (uint64_t)pCtx->ds.Sel << 4);
4418	Assert(pCtx->ds.u32Limit == 0xffff);
4419	Assert(u32DSAttr == 0xf3);
4420	/* ES */
4421	Assert(pCtx->es.u64Base == (uint64_t)pCtx->es.Sel << 4);
4422	Assert(pCtx->es.u32Limit == 0xffff);
4423	Assert(u32ESAttr == 0xf3);
4424	/* FS */
4425	Assert(pCtx->fs.u64Base == (uint64_t)pCtx->fs.Sel << 4);
4426	Assert(pCtx->fs.u32Limit == 0xffff);
4427	Assert(u32FSAttr == 0xf3);
4428	/* GS */
4429	Assert(pCtx->gs.u64Base == (uint64_t)pCtx->gs.Sel << 4);
4430	Assert(pCtx->gs.u32Limit == 0xffff);
4431	Assert(u32GSAttr == 0xf3);
4432	/* 64-bit capable CPUs. */
4433	# if HC_ARCH_BITS == 64
4434	Assert(!(pCtx->cs.u64Base >> 32));
4435	Assert(!u32SSAttr \|\| !(pCtx->ss.u64Base >> 32));
4436	Assert(!u32DSAttr \|\| !(pCtx->ds.u64Base >> 32));
4437	Assert(!u32ESAttr \|\| !(pCtx->es.u64Base >> 32));
4438	# endif
4439	}
4440	}
4441	#endif /* VBOX_STRICT */
4442
4443
4444	/**
4445	* Writes a guest segment register into the guest-state area in the VMCS.
4446	*
4447	* @returns VBox status code.
4448	* @param pVCpu The cross context virtual CPU structure.
4449	* @param idxSel Index of the selector in the VMCS.
4450	* @param idxLimit Index of the segment limit in the VMCS.
4451	* @param idxBase Index of the segment base in the VMCS.
4452	* @param idxAccess Index of the access rights of the segment in the VMCS.
4453	* @param pSelReg Pointer to the segment selector.
4454	*
4455	* @remarks No-long-jump zone!!!
4456	*/
4457	static int hmR0VmxWriteSegmentReg(PVMCPU pVCpu, uint32_t idxSel, uint32_t idxLimit, uint32_t idxBase,
4458	uint32_t idxAccess, PCPUMSELREG pSelReg)
4459	{
4460	int rc = VMXWriteVmcs32(idxSel, pSelReg->Sel); /* 16-bit guest selector field. */
4461	rc \|= VMXWriteVmcs32(idxLimit, pSelReg->u32Limit); /* 32-bit guest segment limit field. */
4462	rc \|= VMXWriteVmcsGstN(idxBase, pSelReg->u64Base); /* Natural width guest segment base field.*/
4463	AssertRCReturn(rc, rc);
4464
4465	uint32_t u32Access = pSelReg->Attr.u;
4466	if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4467	{
4468	/* VT-x requires our real-using-v86 mode hack to override the segment access-right bits. */
4469	u32Access = 0xf3;
4470	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
4471	Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
4472	}
4473	else
4474	{
4475	/*
4476	* The way to differentiate between whether this is really a null selector or was just a selector loaded with 0 in
4477	* real-mode is using the segment attributes. A selector loaded in real-mode with the value 0 is valid and usable in
4478	* protected-mode and we should -not- mark it as an unusable segment. Both the recompiler & VT-x ensures NULL selectors
4479	* loaded in protected-mode have their attribute as 0.
4480	*/
4481	if (!u32Access)
4482	u32Access = X86DESCATTR_UNUSABLE;
4483	}
4484
4485	/* Validate segment access rights. Refer to Intel spec. "26.3.1.2 Checks on Guest Segment Registers". */
4486	AssertMsg((u32Access & X86DESCATTR_UNUSABLE) \|\| (u32Access & X86_SEL_TYPE_ACCESSED),
4487	("Access bit not set for usable segment. idx=%#x sel=%#x attr %#x\n", idxBase, pSelReg, pSelReg->Attr.u));
4488
4489	rc = VMXWriteVmcs32(idxAccess, u32Access); /* 32-bit guest segment access-rights field. */
4490	AssertRCReturn(rc, rc);
4491	return rc;
4492	}
4493
4494
4495	/**
4496	* Loads the guest segment registers, GDTR, IDTR, LDTR, (TR, FS and GS bases)
4497	* into the guest-state area in the VMCS.
4498	*
4499	* @returns VBox status code.
4500	* @param pVCpu The cross context virtual CPU structure.
4501	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
4502	* out-of-sync. Make sure to update the required fields
4503	* before using them.
4504	*
4505	* @remarks ASSUMES pMixedCtx->cr0 is up to date (strict builds validation).
4506	* @remarks No-long-jump zone!!!
4507	*/
4508	static int hmR0VmxLoadGuestSegmentRegs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
4509	{
4510	int rc = VERR_INTERNAL_ERROR_5;
4511	PVM pVM = pVCpu->CTX_SUFF(pVM);
4512
4513	/*
4514	* Guest Segment registers: CS, SS, DS, ES, FS, GS.
4515	*/
4516	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
4517	{
4518	/* Save the segment attributes for real-on-v86 mode hack, so we can restore them on VM-exit. */
4519	if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4520	{
4521	pVCpu->hm.s.vmx.RealMode.AttrCS.u = pMixedCtx->cs.Attr.u;
4522	pVCpu->hm.s.vmx.RealMode.AttrSS.u = pMixedCtx->ss.Attr.u;
4523	pVCpu->hm.s.vmx.RealMode.AttrDS.u = pMixedCtx->ds.Attr.u;
4524	pVCpu->hm.s.vmx.RealMode.AttrES.u = pMixedCtx->es.Attr.u;
4525	pVCpu->hm.s.vmx.RealMode.AttrFS.u = pMixedCtx->fs.Attr.u;
4526	pVCpu->hm.s.vmx.RealMode.AttrGS.u = pMixedCtx->gs.Attr.u;
4527	}
4528
4529	#ifdef VBOX_WITH_REM
4530	if (!pVM->hm.s.vmx.fUnrestrictedGuest)
4531	{
4532	Assert(pVM->hm.s.vmx.pRealModeTSS);
4533	AssertCompile(PGMMODE_REAL < PGMMODE_PROTECTED);
4534	if ( pVCpu->hm.s.vmx.fWasInRealMode
4535	&& PGMGetGuestMode(pVCpu) >= PGMMODE_PROTECTED)
4536	{
4537	/* Signal that the recompiler must flush its code-cache as the guest -may- rewrite code it will later execute
4538	in real-mode (e.g. OpenBSD 4.0) */
4539	REMFlushTBs(pVM);
4540	Log4(("Load[%RU32]: Switch to protected mode detected!\n", pVCpu->idCpu));
4541	pVCpu->hm.s.vmx.fWasInRealMode = false;
4542	}
4543	}
4544	#endif
4545	rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_CS_SEL, VMX_VMCS32_GUEST_CS_LIMIT, VMX_VMCS_GUEST_CS_BASE,
4546	VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS, &pMixedCtx->cs);
4547	AssertRCReturn(rc, rc);
4548	rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_SS_SEL, VMX_VMCS32_GUEST_SS_LIMIT, VMX_VMCS_GUEST_SS_BASE,
4549	VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS, &pMixedCtx->ss);
4550	AssertRCReturn(rc, rc);
4551	rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_DS_SEL, VMX_VMCS32_GUEST_DS_LIMIT, VMX_VMCS_GUEST_DS_BASE,
4552	VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS, &pMixedCtx->ds);
4553	AssertRCReturn(rc, rc);
4554	rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_ES_SEL, VMX_VMCS32_GUEST_ES_LIMIT, VMX_VMCS_GUEST_ES_BASE,
4555	VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS, &pMixedCtx->es);
4556	AssertRCReturn(rc, rc);
4557	rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_FS_SEL, VMX_VMCS32_GUEST_FS_LIMIT, VMX_VMCS_GUEST_FS_BASE,
4558	VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS, &pMixedCtx->fs);
4559	AssertRCReturn(rc, rc);
4560	rc = hmR0VmxWriteSegmentReg(pVCpu, VMX_VMCS16_GUEST_GS_SEL, VMX_VMCS32_GUEST_GS_LIMIT, VMX_VMCS_GUEST_GS_BASE,
4561	VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS, &pMixedCtx->gs);
4562	AssertRCReturn(rc, rc);
4563
4564	#ifdef VBOX_STRICT
4565	/* Validate. */
4566	hmR0VmxValidateSegmentRegs(pVM, pVCpu, pMixedCtx);
4567	#endif
4568
4569	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
4570	Log4(("Load[%RU32]: CS=%#RX16 Base=%#RX64 Limit=%#RX32 Attr=%#RX32\n", pVCpu->idCpu, pMixedCtx->cs.Sel,
4571	pMixedCtx->cs.u64Base, pMixedCtx->cs.u32Limit, pMixedCtx->cs.Attr.u));
4572	}
4573
4574	/*
4575	* Guest TR.
4576	*/
4577	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
4578	{
4579	/*
4580	* Real-mode emulation using virtual-8086 mode with CR4.VME. Interrupt redirection is achieved
4581	* using the interrupt redirection bitmap (all bits cleared to let the guest handle INT-n's) in the TSS.
4582	* See hmR3InitFinalizeR0() to see how pRealModeTSS is setup.
4583	*/
4584	uint16_t u16Sel = 0;
4585	uint32_t u32Limit = 0;
4586	uint64_t u64Base = 0;
4587	uint32_t u32AccessRights = 0;
4588
4589	if (!pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
4590	{
4591	u16Sel = pMixedCtx->tr.Sel;
4592	u32Limit = pMixedCtx->tr.u32Limit;
4593	u64Base = pMixedCtx->tr.u64Base;
4594	u32AccessRights = pMixedCtx->tr.Attr.u;
4595	}
4596	else
4597	{
4598	Assert(pVM->hm.s.vmx.pRealModeTSS);
4599	Assert(PDMVmmDevHeapIsEnabled(pVM)); /* Guaranteed by HMR3CanExecuteGuest() -XXX- what about inner loop changes? */
4600
4601	/* We obtain it here every time as PCI regions could be reconfigured in the guest, changing the VMMDev base. */
4602	RTGCPHYS GCPhys;
4603	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
4604	AssertRCReturn(rc, rc);
4605
4606	X86DESCATTR DescAttr;
4607	DescAttr.u = 0;
4608	DescAttr.n.u1Present = 1;
4609	DescAttr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
4610
4611	u16Sel = 0;
4612	u32Limit = HM_VTX_TSS_SIZE;
4613	u64Base = GCPhys; /* in real-mode phys = virt. */
4614	u32AccessRights = DescAttr.u;
4615	}
4616
4617	/* Validate. */
4618	Assert(!(u16Sel & RT_BIT(2)));
4619	AssertMsg( (u32AccessRights & 0xf) == X86_SEL_TYPE_SYS_386_TSS_BUSY
4620	\|\| (u32AccessRights & 0xf) == X86_SEL_TYPE_SYS_286_TSS_BUSY, ("TSS is not busy!? %#x\n", u32AccessRights));
4621	AssertMsg(!(u32AccessRights & X86DESCATTR_UNUSABLE), ("TR unusable bit is not clear!? %#x\n", u32AccessRights));
4622	Assert(!(u32AccessRights & RT_BIT(4))); /* System MBZ.*/
4623	Assert(u32AccessRights & RT_BIT(7)); /* Present MB1.*/
4624	Assert(!(u32AccessRights & 0xf00)); /* 11:8 MBZ. */
4625	Assert(!(u32AccessRights & 0xfffe0000)); /* 31:17 MBZ. */
4626	Assert( (u32Limit & 0xfff) == 0xfff
4627	\|\| !(u32AccessRights & RT_BIT(15))); /* Granularity MBZ. */
4628	Assert( !(pMixedCtx->tr.u32Limit & 0xfff00000)
4629	\|\| (u32AccessRights & RT_BIT(15))); /* Granularity MB1. */
4630
4631	rc = VMXWriteVmcs32(VMX_VMCS16_GUEST_TR_SEL, u16Sel);
4632	rc \|= VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_LIMIT, u32Limit);
4633	rc \|= VMXWriteVmcsGstN(VMX_VMCS_GUEST_TR_BASE, u64Base);
4634	rc \|= VMXWriteVmcs32(VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS, u32AccessRights);
4635	AssertRCReturn(rc, rc);
4636
4637	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
4638	Log4(("Load[%RU32]: VMX_VMCS_GUEST_TR_BASE=%#RX64\n", pVCpu->idCpu, u64Base));
4639	}
4640
4641	/*
4642	* Guest GDTR.
4643	*/
4644	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
4645	{
4646	rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, pMixedCtx->gdtr.cbGdt);
4647	rc \|= VMXWriteVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE, pMixedCtx->gdtr.pGdt);
4648	AssertRCReturn(rc, rc);
4649
4650	/* Validate. */
4651	Assert(!(pMixedCtx->gdtr.cbGdt & 0xffff0000)); /* Bits 31:16 MBZ. */
4652
4653	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
4654	Log4(("Load[%RU32]: VMX_VMCS_GUEST_GDTR_BASE=%#RX64\n", pVCpu->idCpu, pMixedCtx->gdtr.pGdt));
4655	}
4656
4657	/*
4658	* Guest LDTR.
4659	*/
4660	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
4661	{
4662	/* The unusable bit is specific to VT-x, if it's a null selector mark it as an unusable segment. */
4663	uint32_t u32Access = 0;
4664	if (!pMixedCtx->ldtr.Attr.u)
4665	u32Access = X86DESCATTR_UNUSABLE;
4666	else
4667	u32Access = pMixedCtx->ldtr.Attr.u;
4668
4669	rc = VMXWriteVmcs32(VMX_VMCS16_GUEST_LDTR_SEL, pMixedCtx->ldtr.Sel);
4670	rc \|= VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_LIMIT, pMixedCtx->ldtr.u32Limit);
4671	rc \|= VMXWriteVmcsGstN(VMX_VMCS_GUEST_LDTR_BASE, pMixedCtx->ldtr.u64Base);
4672	rc \|= VMXWriteVmcs32(VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS, u32Access);
4673	AssertRCReturn(rc, rc);
4674
4675	/* Validate. */
4676	if (!(u32Access & X86DESCATTR_UNUSABLE))
4677	{
4678	Assert(!(pMixedCtx->ldtr.Sel & RT_BIT(2))); /* TI MBZ. */
4679	Assert(pMixedCtx->ldtr.Attr.n.u4Type == 2); /* Type MB2 (LDT). */
4680	Assert(!pMixedCtx->ldtr.Attr.n.u1DescType); /* System MBZ. */
4681	Assert(pMixedCtx->ldtr.Attr.n.u1Present == 1); /* Present MB1. */
4682	Assert(!pMixedCtx->ldtr.Attr.n.u4LimitHigh); /* 11:8 MBZ. */
4683	Assert(!(pMixedCtx->ldtr.Attr.u & 0xfffe0000)); /* 31:17 MBZ. */
4684	Assert( (pMixedCtx->ldtr.u32Limit & 0xfff) == 0xfff
4685	\|\| !pMixedCtx->ldtr.Attr.n.u1Granularity); /* Granularity MBZ. */
4686	Assert( !(pMixedCtx->ldtr.u32Limit & 0xfff00000)
4687	\|\| pMixedCtx->ldtr.Attr.n.u1Granularity); /* Granularity MB1. */
4688	}
4689
4690	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
4691	Log4(("Load[%RU32]: VMX_VMCS_GUEST_LDTR_BASE=%#RX64\n", pVCpu->idCpu, pMixedCtx->ldtr.u64Base));
4692	}
4693
4694	/*
4695	* Guest IDTR.
4696	*/
4697	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
4698	{
4699	rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, pMixedCtx->idtr.cbIdt);
4700	rc \|= VMXWriteVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE, pMixedCtx->idtr.pIdt);
4701	AssertRCReturn(rc, rc);
4702
4703	/* Validate. */
4704	Assert(!(pMixedCtx->idtr.cbIdt & 0xffff0000)); /* Bits 31:16 MBZ. */
4705
4706	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
4707	Log4(("Load[%RU32]: VMX_VMCS_GUEST_IDTR_BASE=%#RX64\n", pVCpu->idCpu, pMixedCtx->idtr.pIdt));
4708	}
4709
4710	return VINF_SUCCESS;
4711	}
4712
4713
4714	/**
4715	* Loads certain guest MSRs into the VM-entry MSR-load and VM-exit MSR-store
4716	* areas.
4717	*
4718	* These MSRs will automatically be loaded to the host CPU on every successful
4719	* VM-entry and stored from the host CPU on every successful VM-exit. This also
4720	* creates/updates MSR slots for the host MSRs. The actual host MSR values are
4721	* -not- updated here for performance reasons. See hmR0VmxSaveHostMsrs().
4722	*
4723	* Also loads the sysenter MSRs into the guest-state area in the VMCS.
4724	*
4725	* @returns VBox status code.
4726	* @param pVCpu The cross context virtual CPU structure.
4727	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
4728	* out-of-sync. Make sure to update the required fields
4729	* before using them.
4730	*
4731	* @remarks No-long-jump zone!!!
4732	*/
4733	static int hmR0VmxLoadGuestMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
4734	{
4735	AssertPtr(pVCpu);
4736	AssertPtr(pVCpu->hm.s.vmx.pvGuestMsr);
4737
4738	/*
4739	* MSRs that we use the auto-load/store MSR area in the VMCS.
4740	*/
4741	PVM pVM = pVCpu->CTX_SUFF(pVM);
4742	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS))
4743	{
4744	/* For 64-bit hosts, we load/restore them lazily, see hmR0VmxLazyLoadGuestMsrs(). */
4745	#if HC_ARCH_BITS == 32
4746	if (pVM->hm.s.fAllow64BitGuests)
4747	{
4748	int rc = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_LSTAR, pMixedCtx->msrLSTAR, false, NULL);
4749	rc \|= hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K6_STAR, pMixedCtx->msrSTAR, false, NULL);
4750	rc \|= hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_SF_MASK, pMixedCtx->msrSFMASK, false, NULL);
4751	rc \|= hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_KERNEL_GS_BASE, pMixedCtx->msrKERNELGSBASE, false, NULL);
4752	AssertRCReturn(rc, rc);
4753	# ifdef LOG_ENABLED
4754	PVMXAUTOMSR pMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
4755	for (uint32_t i = 0; i < pVCpu->hm.s.vmx.cMsrs; i++, pMsr++)
4756	{
4757	Log4(("Load[%RU32]: MSR[%RU32]: u32Msr=%#RX32 u64Value=%#RX64\n", pVCpu->idCpu, i, pMsr->u32Msr,
4758	pMsr->u64Value));
4759	}
4760	# endif
4761	}
4762	#endif
4763	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS);
4764	}
4765
4766	/*
4767	* Guest Sysenter MSRs.
4768	* These flags are only set when MSR-bitmaps are not supported by the CPU and we cause
4769	* VM-exits on WRMSRs for these MSRs.
4770	*/
4771	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR))
4772	{
4773	int rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, pMixedCtx->SysEnter.cs); AssertRCReturn(rc, rc);
4774	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR);
4775	}
4776
4777	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR))
4778	{
4779	int rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_EIP, pMixedCtx->SysEnter.eip); AssertRCReturn(rc, rc);
4780	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR);
4781	}
4782
4783	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR))
4784	{
4785	int rc = VMXWriteVmcsGstN(VMX_VMCS_GUEST_SYSENTER_ESP, pMixedCtx->SysEnter.esp); AssertRCReturn(rc, rc);
4786	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR);
4787	}
4788
4789	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_EFER_MSR))
4790	{
4791	if (hmR0VmxShouldSwapEferMsr(pVCpu, pMixedCtx))
4792	{
4793	/*
4794	* If the CPU supports VMCS controls for swapping EFER, use it. Otherwise, we have no option
4795	* but to use the auto-load store MSR area in the VMCS for swapping EFER. See @bugref{7368}.
4796	*/
4797	if (pVM->hm.s.vmx.fSupportsVmcsEfer)
4798	{
4799	int rc = VMXWriteVmcs64(VMX_VMCS64_GUEST_EFER_FULL, pMixedCtx->msrEFER);
4800	AssertRCReturn(rc,rc);
4801	Log4(("Load[%RU32]: VMX_VMCS64_GUEST_EFER_FULL=%#RX64\n", pVCpu->idCpu, pMixedCtx->msrEFER));
4802	}
4803	else
4804	{
4805	int rc = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K6_EFER, pMixedCtx->msrEFER, false /* fUpdateHostMsr */,
4806	NULL /* pfAddedAndUpdated */);
4807	AssertRCReturn(rc, rc);
4808
4809	/* We need to intercept reads too, see @bugref{7386#c16}. */
4810	if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
4811	hmR0VmxSetMsrPermission(pVCpu, MSR_K6_EFER, VMXMSREXIT_INTERCEPT_READ, VMXMSREXIT_INTERCEPT_WRITE);
4812	Log4(("Load[%RU32]: MSR[--]: u32Msr=%#RX32 u64Value=%#RX64 cMsrs=%u\n", pVCpu->idCpu, MSR_K6_EFER,
4813	pMixedCtx->msrEFER, pVCpu->hm.s.vmx.cMsrs));
4814	}
4815	}
4816	else if (!pVM->hm.s.vmx.fSupportsVmcsEfer)
4817	hmR0VmxRemoveAutoLoadStoreMsr(pVCpu, MSR_K6_EFER);
4818	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
4819	}
4820
4821	return VINF_SUCCESS;
4822	}
4823
4824
4825	/**
4826	* Loads the guest activity state into the guest-state area in the VMCS.
4827	*
4828	* @returns VBox status code.
4829	* @param pVCpu The cross context virtual CPU structure.
4830	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
4831	* out-of-sync. Make sure to update the required fields
4832	* before using them.
4833	*
4834	* @remarks No-long-jump zone!!!
4835	*/
4836	static int hmR0VmxLoadGuestActivityState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
4837	{
4838	NOREF(pMixedCtx);
4839	/** @todo See if we can make use of other states, e.g.
4840	* VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN or HLT. */
4841	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_GUEST_ACTIVITY_STATE))
4842	{
4843	int rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_ACTIVITY_STATE, VMX_VMCS_GUEST_ACTIVITY_ACTIVE);
4844	AssertRCReturn(rc, rc);
4845
4846	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_VMX_GUEST_ACTIVITY_STATE);
4847	}
4848	return VINF_SUCCESS;
4849	}
4850
4851
4852	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
4853	/**
4854	* Check if guest state allows safe use of 32-bit switcher again.
4855	*
4856	* Segment bases and protected mode structures must be 32-bit addressable
4857	* because the 32-bit switcher will ignore high dword when writing these VMCS
4858	* fields. See @bugref{8432} for details.
4859	*
4860	* @returns true if safe, false if must continue to use the 64-bit switcher.
4861	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
4862	* out-of-sync. Make sure to update the required fields
4863	* before using them.
4864	*
4865	* @remarks No-long-jump zone!!!
4866	*/
4867	static bool hmR0VmxIs32BitSwitcherSafe(PCPUMCTX pMixedCtx)
4868	{
4869	if (pMixedCtx->gdtr.pGdt & UINT64_C(0xffffffff00000000))
4870	return false;
4871	if (pMixedCtx->idtr.pIdt & UINT64_C(0xffffffff00000000))
4872	return false;
4873	if (pMixedCtx->ldtr.u64Base & UINT64_C(0xffffffff00000000))
4874	return false;
4875	if (pMixedCtx->tr.u64Base & UINT64_C(0xffffffff00000000))
4876	return false;
4877	if (pMixedCtx->es.u64Base & UINT64_C(0xffffffff00000000))
4878	return false;
4879	if (pMixedCtx->cs.u64Base & UINT64_C(0xffffffff00000000))
4880	return false;
4881	if (pMixedCtx->ss.u64Base & UINT64_C(0xffffffff00000000))
4882	return false;
4883	if (pMixedCtx->ds.u64Base & UINT64_C(0xffffffff00000000))
4884	return false;
4885	if (pMixedCtx->fs.u64Base & UINT64_C(0xffffffff00000000))
4886	return false;
4887	if (pMixedCtx->gs.u64Base & UINT64_C(0xffffffff00000000))
4888	return false;
4889	/* All good, bases are 32-bit. */
4890	return true;
4891	}
4892	#endif
4893
4894
4895	/**
4896	* Sets up the appropriate function to run guest code.
4897	*
4898	* @returns VBox status code.
4899	* @param pVCpu The cross context virtual CPU structure.
4900	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
4901	* out-of-sync. Make sure to update the required fields
4902	* before using them.
4903	*
4904	* @remarks No-long-jump zone!!!
4905	*/
4906	static int hmR0VmxSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
4907	{
4908	if (CPUMIsGuestInLongModeEx(pMixedCtx))
4909	{
4910	#ifndef VBOX_ENABLE_64_BITS_GUESTS
4911	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
4912	#endif
4913	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
4914	#if HC_ARCH_BITS == 32
4915	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
4916	if (pVCpu->hm.s.vmx.pfnStartVM != VMXR0SwitcherStartVM64)
4917	{
4918	if (pVCpu->hm.s.vmx.pfnStartVM != NULL) /* Very first entry would have saved host-state already, ignore it. */
4919	{
4920	/* Currently, all mode changes sends us back to ring-3, so these should be set. See @bugref{6944}. */
4921	AssertMsg(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_VMX_EXIT_CTLS
4922	\| HM_CHANGED_VMX_ENTRY_CTLS
4923	\| HM_CHANGED_GUEST_EFER_MSR), ("flags=%#x\n", HMCPU_CF_VALUE(pVCpu)));
4924	}
4925	pVCpu->hm.s.vmx.pfnStartVM = VMXR0SwitcherStartVM64;
4926
4927	/* Mark that we've switched to 64-bit handler, we can't safely switch back to 32-bit for
4928	the rest of the VM run (until VM reset). See @bugref{8432#c7}. */
4929	pVCpu->hm.s.vmx.fSwitchedTo64on32 = true;
4930	Log4(("Load[%RU32]: hmR0VmxSetupVMRunHandler: selected 64-bit switcher\n", pVCpu->idCpu));
4931	}
4932	#else
4933	/* 64-bit host. */
4934	pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM64;
4935	#endif
4936	}
4937	else
4938	{
4939	/* Guest is not in long mode, use the 32-bit handler. */
4940	#if HC_ARCH_BITS == 32
4941	if ( pVCpu->hm.s.vmx.pfnStartVM != VMXR0StartVM32
4942	&& !pVCpu->hm.s.vmx.fSwitchedTo64on32 /* If set, guest mode change does not imply switcher change. */
4943	&& pVCpu->hm.s.vmx.pfnStartVM != NULL) /* Very first entry would have saved host-state already, ignore it. */
4944	{
4945	/* Currently, all mode changes sends us back to ring-3, so these should be set. See @bugref{6944}. */
4946	AssertMsg(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_VMX_EXIT_CTLS
4947	\| HM_CHANGED_VMX_ENTRY_CTLS
4948	\| HM_CHANGED_GUEST_EFER_MSR), ("flags=%#x\n", HMCPU_CF_VALUE(pVCpu)));
4949	}
4950	# ifdef VBOX_ENABLE_64_BITS_GUESTS
4951	/*
4952	* Keep using the 64-bit switcher even though we're in 32-bit because of bad Intel design, see @bugref{8432#c7}.
4953	* If real-on-v86 mode is active, clear the 64-bit switcher flag because now we know the guest is in a sane
4954	* state where it's safe to use the 32-bit switcher. Otherwise check the guest state if it's safe to use
4955	* the much faster 32-bit switcher again.
4956	*/
4957	if (!pVCpu->hm.s.vmx.fSwitchedTo64on32)
4958	{
4959	if (pVCpu->hm.s.vmx.pfnStartVM != VMXR0StartVM32)
4960	Log4(("Load[%RU32]: hmR0VmxSetupVMRunHandler: selected 32-bit switcher\n", pVCpu->idCpu));
4961	pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4962	}
4963	else
4964	{
4965	Assert(pVCpu->hm.s.vmx.pfnStartVM == VMXR0SwitcherStartVM64);
4966	if ( pVCpu->hm.s.vmx.RealMode.fRealOnV86Active
4967	\|\| hmR0VmxIs32BitSwitcherSafe(pMixedCtx))
4968	{
4969	pVCpu->hm.s.vmx.fSwitchedTo64on32 = false;
4970	pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4971	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR
4972	\| HM_CHANGED_VMX_ENTRY_CTLS
4973	\| HM_CHANGED_VMX_EXIT_CTLS
4974	\| HM_CHANGED_HOST_CONTEXT);
4975	Log4(("Load[%RU32]: hmR0VmxSetupVMRunHandler: selected 32-bit switcher (safe)\n", pVCpu->idCpu));
4976	}
4977	}
4978	# else
4979	pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4980	# endif
4981	#else
4982	pVCpu->hm.s.vmx.pfnStartVM = VMXR0StartVM32;
4983	#endif
4984	}
4985	Assert(pVCpu->hm.s.vmx.pfnStartVM);
4986	return VINF_SUCCESS;
4987	}
4988
4989
4990	/**
4991	* Wrapper for running the guest code in VT-x.
4992	*
4993	* @returns VBox status code, no informational status codes.
4994	* @param pVM The cross context VM structure.
4995	* @param pVCpu The cross context virtual CPU structure.
4996	* @param pCtx Pointer to the guest-CPU context.
4997	*
4998	* @remarks No-long-jump zone!!!
4999	*/
5000	DECLINLINE(int) hmR0VmxRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
5001	{
5002	/*
5003	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
5004	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
5005	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
5006	*/
5007	bool const fResumeVM = RT_BOOL(pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_LAUNCHED);
5008	/** @todo Add stats for resume vs launch. */
5009	#ifdef VBOX_WITH_KERNEL_USING_XMM
5010	int rc = hmR0VMXStartVMWrapXMM(fResumeVM, pCtx, &pVCpu->hm.s.vmx.VMCSCache, pVM, pVCpu, pVCpu->hm.s.vmx.pfnStartVM);
5011	#else
5012	int rc = pVCpu->hm.s.vmx.pfnStartVM(fResumeVM, pCtx, &pVCpu->hm.s.vmx.VMCSCache, pVM, pVCpu);
5013	#endif
5014	AssertMsg(rc <= VINF_SUCCESS, ("%Rrc\n", rc));
5015	return rc;
5016	}
5017
5018
5019	/**
5020	* Reports world-switch error and dumps some useful debug info.
5021	*
5022	* @param pVM The cross context VM structure.
5023	* @param pVCpu The cross context virtual CPU structure.
5024	* @param rcVMRun The return code from VMLAUNCH/VMRESUME.
5025	* @param pCtx Pointer to the guest-CPU context.
5026	* @param pVmxTransient Pointer to the VMX transient structure (only
5027	* exitReason updated).
5028	*/
5029	static void hmR0VmxReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx, PVMXTRANSIENT pVmxTransient)
5030	{
5031	Assert(pVM);
5032	Assert(pVCpu);
5033	Assert(pCtx);
5034	Assert(pVmxTransient);
5035	HMVMX_ASSERT_PREEMPT_SAFE();
5036
5037	Log4(("VM-entry failure: %Rrc\n", rcVMRun));
5038	switch (rcVMRun)
5039	{
5040	case VERR_VMX_INVALID_VMXON_PTR:
5041	AssertFailed();
5042	break;
5043	case VINF_SUCCESS: /* VMLAUNCH/VMRESUME succeeded but VM-entry failed... yeah, true story. */
5044	case VERR_VMX_UNABLE_TO_START_VM: /* VMLAUNCH/VMRESUME itself failed. */
5045	{
5046	int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_REASON, &pVCpu->hm.s.vmx.LastError.u32ExitReason);
5047	rc \|= VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &pVCpu->hm.s.vmx.LastError.u32InstrError);
5048	rc \|= hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
5049	AssertRC(rc);
5050
5051	pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hm.s.idEnteredCpu;
5052	/* LastError.idCurrentCpu was already updated in hmR0VmxPreRunGuestCommitted().
5053	Cannot do it here as we may have been long preempted. */
5054
5055	#ifdef VBOX_STRICT
5056	Log4(("uExitReason %#RX32 (VmxTransient %#RX16)\n", pVCpu->hm.s.vmx.LastError.u32ExitReason,
5057	pVmxTransient->uExitReason));
5058	Log4(("Exit Qualification %#RX64\n", pVmxTransient->uExitQualification));
5059	Log4(("InstrError %#RX32\n", pVCpu->hm.s.vmx.LastError.u32InstrError));
5060	if (pVCpu->hm.s.vmx.LastError.u32InstrError <= HMVMX_INSTR_ERROR_MAX)
5061	Log4(("InstrError Desc. \"%s\"\n", g_apszVmxInstrErrors[pVCpu->hm.s.vmx.LastError.u32InstrError]));
5062	else
5063	Log4(("InstrError Desc. Range exceeded %u\n", HMVMX_INSTR_ERROR_MAX));
5064	Log4(("Entered host CPU %u\n", pVCpu->hm.s.vmx.LastError.idEnteredCpu));
5065	Log4(("Current host CPU %u\n", pVCpu->hm.s.vmx.LastError.idCurrentCpu));
5066
5067	/* VMX control bits. */
5068	uint32_t u32Val;
5069	uint64_t u64Val;
5070	RTHCUINTREG uHCReg;
5071	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PIN_EXEC, &u32Val); AssertRC(rc);
5072	Log4(("VMX_VMCS32_CTRL_PIN_EXEC %#RX32\n", u32Val));
5073	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, &u32Val); AssertRC(rc);
5074	Log4(("VMX_VMCS32_CTRL_PROC_EXEC %#RX32\n", u32Val));
5075	if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
5076	{
5077	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val); AssertRC(rc);
5078	Log4(("VMX_VMCS32_CTRL_PROC_EXEC2 %#RX32\n", u32Val));
5079	}
5080	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val); AssertRC(rc);
5081	Log4(("VMX_VMCS32_CTRL_ENTRY %#RX32\n", u32Val));
5082	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT, &u32Val); AssertRC(rc);
5083	Log4(("VMX_VMCS32_CTRL_EXIT %#RX32\n", u32Val));
5084	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_CR3_TARGET_COUNT, &u32Val); AssertRC(rc);
5085	Log4(("VMX_VMCS32_CTRL_CR3_TARGET_COUNT %#RX32\n", u32Val));
5086	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &u32Val); AssertRC(rc);
5087	Log4(("VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO %#RX32\n", u32Val));
5088	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, &u32Val); AssertRC(rc);
5089	Log4(("VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE %#RX32\n", u32Val));
5090	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, &u32Val); AssertRC(rc);
5091	Log4(("VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH %u\n", u32Val));
5092	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, &u32Val); AssertRC(rc);
5093	Log4(("VMX_VMCS32_CTRL_TPR_THRESHOLD %u\n", u32Val));
5094	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT, &u32Val); AssertRC(rc);
5095	Log4(("VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT %u (guest MSRs)\n", u32Val));
5096	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT, &u32Val); AssertRC(rc);
5097	Log4(("VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT %u (host MSRs)\n", u32Val));
5098	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT, &u32Val); AssertRC(rc);
5099	Log4(("VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT %u (guest MSRs)\n", u32Val));
5100	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, &u32Val); AssertRC(rc);
5101	Log4(("VMX_VMCS32_CTRL_EXCEPTION_BITMAP %#RX32\n", u32Val));
5102	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK, &u32Val); AssertRC(rc);
5103	Log4(("VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK %#RX32\n", u32Val));
5104	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH, &u32Val); AssertRC(rc);
5105	Log4(("VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH %#RX32\n", u32Val));
5106	rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_MASK, &uHCReg); AssertRC(rc);
5107	Log4(("VMX_VMCS_CTRL_CR0_MASK %#RHr\n", uHCReg));
5108	rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_READ_SHADOW, &uHCReg); AssertRC(rc);
5109	Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
5110	rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_MASK, &uHCReg); AssertRC(rc);
5111	Log4(("VMX_VMCS_CTRL_CR4_MASK %#RHr\n", uHCReg));
5112	rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uHCReg); AssertRC(rc);
5113	Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
5114	if (pVM->hm.s.fNestedPaging)
5115	{
5116	rc = VMXReadVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, &u64Val); AssertRC(rc);
5117	Log4(("VMX_VMCS64_CTRL_EPTP_FULL %#RX64\n", u64Val));
5118	}
5119
5120	/* Guest bits. */
5121	rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &u64Val); AssertRC(rc);
5122	Log4(("Old Guest Rip %#RX64 New %#RX64\n", pCtx->rip, u64Val));
5123	rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &u64Val); AssertRC(rc);
5124	Log4(("Old Guest Rsp %#RX64 New %#RX64\n", pCtx->rsp, u64Val));
5125	rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Val); AssertRC(rc);
5126	Log4(("Old Guest Rflags %#RX32 New %#RX32\n", pCtx->eflags.u32, u32Val));
5127	if (pVM->hm.s.vmx.fVpid)
5128	{
5129	rc = VMXReadVmcs32(VMX_VMCS16_VPID, &u32Val); AssertRC(rc);
5130	Log4(("VMX_VMCS16_VPID %u\n", u32Val));
5131	}
5132
5133	/* Host bits. */
5134	rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR0, &uHCReg); AssertRC(rc);
5135	Log4(("Host CR0 %#RHr\n", uHCReg));
5136	rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR3, &uHCReg); AssertRC(rc);
5137	Log4(("Host CR3 %#RHr\n", uHCReg));
5138	rc = VMXReadVmcsHstN(VMX_VMCS_HOST_CR4, &uHCReg); AssertRC(rc);
5139	Log4(("Host CR4 %#RHr\n", uHCReg));
5140
5141	RTGDTR HostGdtr;
5142	PCX86DESCHC pDesc;
5143	ASMGetGDTR(&HostGdtr);
5144	rc = VMXReadVmcs32(VMX_VMCS16_HOST_CS_SEL, &u32Val); AssertRC(rc);
5145	Log4(("Host CS %#08x\n", u32Val));
5146	if (u32Val < HostGdtr.cbGdt)
5147	{
5148	pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5149	hmR0DumpDescriptor(pDesc, u32Val, "CS: ");
5150	}
5151
5152	rc = VMXReadVmcs32(VMX_VMCS16_HOST_DS_SEL, &u32Val); AssertRC(rc);
5153	Log4(("Host DS %#08x\n", u32Val));
5154	if (u32Val < HostGdtr.cbGdt)
5155	{
5156	pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5157	hmR0DumpDescriptor(pDesc, u32Val, "DS: ");
5158	}
5159
5160	rc = VMXReadVmcs32(VMX_VMCS16_HOST_ES_SEL, &u32Val); AssertRC(rc);
5161	Log4(("Host ES %#08x\n", u32Val));
5162	if (u32Val < HostGdtr.cbGdt)
5163	{
5164	pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5165	hmR0DumpDescriptor(pDesc, u32Val, "ES: ");
5166	}
5167
5168	rc = VMXReadVmcs32(VMX_VMCS16_HOST_FS_SEL, &u32Val); AssertRC(rc);
5169	Log4(("Host FS %#08x\n", u32Val));
5170	if (u32Val < HostGdtr.cbGdt)
5171	{
5172	pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5173	hmR0DumpDescriptor(pDesc, u32Val, "FS: ");
5174	}
5175
5176	rc = VMXReadVmcs32(VMX_VMCS16_HOST_GS_SEL, &u32Val); AssertRC(rc);
5177	Log4(("Host GS %#08x\n", u32Val));
5178	if (u32Val < HostGdtr.cbGdt)
5179	{
5180	pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5181	hmR0DumpDescriptor(pDesc, u32Val, "GS: ");
5182	}
5183
5184	rc = VMXReadVmcs32(VMX_VMCS16_HOST_SS_SEL, &u32Val); AssertRC(rc);
5185	Log4(("Host SS %#08x\n", u32Val));
5186	if (u32Val < HostGdtr.cbGdt)
5187	{
5188	pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5189	hmR0DumpDescriptor(pDesc, u32Val, "SS: ");
5190	}
5191
5192	rc = VMXReadVmcs32(VMX_VMCS16_HOST_TR_SEL, &u32Val); AssertRC(rc);
5193	Log4(("Host TR %#08x\n", u32Val));
5194	if (u32Val < HostGdtr.cbGdt)
5195	{
5196	pDesc = (PCX86DESCHC)(HostGdtr.pGdt + (u32Val & X86_SEL_MASK));
5197	hmR0DumpDescriptor(pDesc, u32Val, "TR: ");
5198	}
5199
5200	rc = VMXReadVmcsHstN(VMX_VMCS_HOST_TR_BASE, &uHCReg); AssertRC(rc);
5201	Log4(("Host TR Base %#RHv\n", uHCReg));
5202	rc = VMXReadVmcsHstN(VMX_VMCS_HOST_GDTR_BASE, &uHCReg); AssertRC(rc);
5203	Log4(("Host GDTR Base %#RHv\n", uHCReg));
5204	rc = VMXReadVmcsHstN(VMX_VMCS_HOST_IDTR_BASE, &uHCReg); AssertRC(rc);
5205	Log4(("Host IDTR Base %#RHv\n", uHCReg));
5206	rc = VMXReadVmcs32(VMX_VMCS32_HOST_SYSENTER_CS, &u32Val); AssertRC(rc);
5207	Log4(("Host SYSENTER CS %#08x\n", u32Val));
5208	rc = VMXReadVmcsHstN(VMX_VMCS_HOST_SYSENTER_EIP, &uHCReg); AssertRC(rc);
5209	Log4(("Host SYSENTER EIP %#RHv\n", uHCReg));
5210	rc = VMXReadVmcsHstN(VMX_VMCS_HOST_SYSENTER_ESP, &uHCReg); AssertRC(rc);
5211	Log4(("Host SYSENTER ESP %#RHv\n", uHCReg));
5212	rc = VMXReadVmcsHstN(VMX_VMCS_HOST_RSP, &uHCReg); AssertRC(rc);
5213	Log4(("Host RSP %#RHv\n", uHCReg));
5214	rc = VMXReadVmcsHstN(VMX_VMCS_HOST_RIP, &uHCReg); AssertRC(rc);
5215	Log4(("Host RIP %#RHv\n", uHCReg));
5216	# if HC_ARCH_BITS == 64
5217	Log4(("MSR_K6_EFER = %#RX64\n", ASMRdMsr(MSR_K6_EFER)));
5218	Log4(("MSR_K8_CSTAR = %#RX64\n", ASMRdMsr(MSR_K8_CSTAR)));
5219	Log4(("MSR_K8_LSTAR = %#RX64\n", ASMRdMsr(MSR_K8_LSTAR)));
5220	Log4(("MSR_K6_STAR = %#RX64\n", ASMRdMsr(MSR_K6_STAR)));
5221	Log4(("MSR_K8_SF_MASK = %#RX64\n", ASMRdMsr(MSR_K8_SF_MASK)));
5222	Log4(("MSR_K8_KERNEL_GS_BASE = %#RX64\n", ASMRdMsr(MSR_K8_KERNEL_GS_BASE)));
5223	# endif
5224	#endif /* VBOX_STRICT */
5225	break;
5226	}
5227
5228	default:
5229	/* Impossible */
5230	AssertMsgFailed(("hmR0VmxReportWorldSwitchError %Rrc (%#x)\n", rcVMRun, rcVMRun));
5231	break;
5232	}
5233	NOREF(pVM); NOREF(pCtx);
5234	}
5235
5236
5237	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
5238	#ifndef VMX_USE_CACHED_VMCS_ACCESSES
5239	# error "VMX_USE_CACHED_VMCS_ACCESSES not defined when it should be!"
5240	#endif
5241	#ifdef VBOX_STRICT
5242	static bool hmR0VmxIsValidWriteField(uint32_t idxField)
5243	{
5244	switch (idxField)
5245	{
5246	case VMX_VMCS_GUEST_RIP:
5247	case VMX_VMCS_GUEST_RSP:
5248	case VMX_VMCS_GUEST_SYSENTER_EIP:
5249	case VMX_VMCS_GUEST_SYSENTER_ESP:
5250	case VMX_VMCS_GUEST_GDTR_BASE:
5251	case VMX_VMCS_GUEST_IDTR_BASE:
5252	case VMX_VMCS_GUEST_CS_BASE:
5253	case VMX_VMCS_GUEST_DS_BASE:
5254	case VMX_VMCS_GUEST_ES_BASE:
5255	case VMX_VMCS_GUEST_FS_BASE:
5256	case VMX_VMCS_GUEST_GS_BASE:
5257	case VMX_VMCS_GUEST_SS_BASE:
5258	case VMX_VMCS_GUEST_LDTR_BASE:
5259	case VMX_VMCS_GUEST_TR_BASE:
5260	case VMX_VMCS_GUEST_CR3:
5261	return true;
5262	}
5263	return false;
5264	}
5265
5266	static bool hmR0VmxIsValidReadField(uint32_t idxField)
5267	{
5268	switch (idxField)
5269	{
5270	/* Read-only fields. */
5271	case VMX_VMCS_RO_EXIT_QUALIFICATION:
5272	return true;
5273	}
5274	/* Remaining readable fields should also be writable. */
5275	return hmR0VmxIsValidWriteField(idxField);
5276	}
5277	#endif /* VBOX_STRICT */
5278
5279
5280	/**
5281	* Executes the specified handler in 64-bit mode.
5282	*
5283	* @returns VBox status code (no informational status codes).
5284	* @param pVM The cross context VM structure.
5285	* @param pVCpu The cross context virtual CPU structure.
5286	* @param pCtx Pointer to the guest CPU context.
5287	* @param enmOp The operation to perform.
5288	* @param cParams Number of parameters.
5289	* @param paParam Array of 32-bit parameters.
5290	*/
5291	VMMR0DECL(int) VMXR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp,
5292	uint32_t cParams, uint32_t *paParam)
5293	{
5294	NOREF(pCtx);
5295
5296	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
5297	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
5298	Assert(pVCpu->hm.s.vmx.VMCSCache.Write.cValidEntries <= RT_ELEMENTS(pVCpu->hm.s.vmx.VMCSCache.Write.aField));
5299	Assert(pVCpu->hm.s.vmx.VMCSCache.Read.cValidEntries <= RT_ELEMENTS(pVCpu->hm.s.vmx.VMCSCache.Read.aField));
5300
5301	#ifdef VBOX_STRICT
5302	for (uint32_t i = 0; i < pVCpu->hm.s.vmx.VMCSCache.Write.cValidEntries; i++)
5303	Assert(hmR0VmxIsValidWriteField(pVCpu->hm.s.vmx.VMCSCache.Write.aField[i]));
5304
5305	for (uint32_t i = 0; i <pVCpu->hm.s.vmx.VMCSCache.Read.cValidEntries; i++)
5306	Assert(hmR0VmxIsValidReadField(pVCpu->hm.s.vmx.VMCSCache.Read.aField[i]));
5307	#endif
5308
5309	/* Disable interrupts. */
5310	RTCCUINTREG fOldEFlags = ASMIntDisableFlags();
5311
5312	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
5313	RTCPUID idHostCpu = RTMpCpuId();
5314	CPUMR0SetLApic(pVCpu, idHostCpu);
5315	#endif
5316
5317	PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
5318	RTHCPHYS HCPhysCpuPage = pCpu->HCPhysMemObj;
5319
5320	/* Clear VMCS. Marking it inactive, clearing implementation-specific data and writing VMCS data back to memory. */
5321	VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
5322	pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
5323
5324	/* Leave VMX Root Mode. */
5325	VMXDisable();
5326
5327	SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
5328
5329	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
5330	CPUMSetHyperEIP(pVCpu, enmOp);
5331	for (int i = (int)cParams - 1; i >= 0; i--)
5332	CPUMPushHyper(pVCpu, paParam[i]);
5333
5334	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
5335
5336	/* Call the switcher. */
5337	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
5338	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
5339
5340	/** @todo replace with hmR0VmxEnterRootMode() and hmR0VmxLeaveRootMode(). */
5341	/* Make sure the VMX instructions don't cause #UD faults. */
5342	SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
5343
5344	/* Re-enter VMX Root Mode */
5345	int rc2 = VMXEnable(HCPhysCpuPage);
5346	if (RT_FAILURE(rc2))
5347	{
5348	SUPR0ChangeCR4(0, ~X86_CR4_VMXE);
5349	ASMSetFlags(fOldEFlags);
5350	pVM->hm.s.vmx.HCPhysVmxEnableError = HCPhysCpuPage;
5351	return rc2;
5352	}
5353
5354	rc2 = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
5355	AssertRC(rc2);
5356	pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_ACTIVE;
5357	Assert(!(ASMGetFlags() & X86_EFL_IF));
5358	ASMSetFlags(fOldEFlags);
5359	return rc;
5360	}
5361
5362
5363	/**
5364	* Prepares for and executes VMLAUNCH (64-bit guests) for 32-bit hosts
5365	* supporting 64-bit guests.
5366	*
5367	* @returns VBox status code.
5368	* @param fResume Whether to VMLAUNCH or VMRESUME.
5369	* @param pCtx Pointer to the guest-CPU context.
5370	* @param pCache Pointer to the VMCS cache.
5371	* @param pVM The cross context VM structure.
5372	* @param pVCpu The cross context virtual CPU structure.
5373	*/
5374	DECLASM(int) VMXR0SwitcherStartVM64(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu)
5375	{
5376	NOREF(fResume);
5377
5378	PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
5379	RTHCPHYS HCPhysCpuPage = pCpu->HCPhysMemObj;
5380
5381	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
5382	pCache->uPos = 1;
5383	pCache->interPD = PGMGetInterPaeCR3(pVM);
5384	pCache->pSwitcher = (uint64_t)pVM->hm.s.pfnHost32ToGuest64R0;
5385	#endif
5386
5387	#if defined(DEBUG) && defined(VMX_USE_CACHED_VMCS_ACCESSES)
5388	pCache->TestIn.HCPhysCpuPage = 0;
5389	pCache->TestIn.HCPhysVmcs = 0;
5390	pCache->TestIn.pCache = 0;
5391	pCache->TestOut.HCPhysVmcs = 0;
5392	pCache->TestOut.pCache = 0;
5393	pCache->TestOut.pCtx = 0;
5394	pCache->TestOut.eflags = 0;
5395	#else
5396	NOREF(pCache);
5397	#endif
5398
5399	uint32_t aParam[10];
5400	aParam[0] = (uint32_t)(HCPhysCpuPage); /* Param 1: VMXON physical address - Lo. */
5401	aParam[1] = (uint32_t)(HCPhysCpuPage >> 32); /* Param 1: VMXON physical address - Hi. */
5402	aParam[2] = (uint32_t)(pVCpu->hm.s.vmx.HCPhysVmcs); /* Param 2: VMCS physical address - Lo. */
5403	aParam[3] = (uint32_t)(pVCpu->hm.s.vmx.HCPhysVmcs >> 32); /* Param 2: VMCS physical address - Hi. */
5404	aParam[4] = VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache);
5405	aParam[5] = 0;
5406	aParam[6] = VM_RC_ADDR(pVM, pVM);
5407	aParam[7] = 0;
5408	aParam[8] = VM_RC_ADDR(pVM, pVCpu);
5409	aParam[9] = 0;
5410
5411	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
5412	pCtx->dr[4] = pVM->hm.s.vmx.pScratchPhys + 16 + 8;
5413	(uint32_t )(pVM->hm.s.vmx.pScratch + 16 + 8) = 1;
5414	#endif
5415	int rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_VMXRCStartVM64, RT_ELEMENTS(aParam), &aParam[0]);
5416
5417	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
5418	Assert((uint32_t )(pVM->hm.s.vmx.pScratch + 16 + 8) == 5);
5419	Assert(pCtx->dr[4] == 10);
5420	(uint32_t )(pVM->hm.s.vmx.pScratch + 16 + 8) = 0xff;
5421	#endif
5422
5423	#if defined(DEBUG) && defined(VMX_USE_CACHED_VMCS_ACCESSES)
5424	AssertMsg(pCache->TestIn.HCPhysCpuPage == HCPhysCpuPage, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysCpuPage, HCPhysCpuPage));
5425	AssertMsg(pCache->TestIn.HCPhysVmcs == pVCpu->hm.s.vmx.HCPhysVmcs, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVmcs,
5426	pVCpu->hm.s.vmx.HCPhysVmcs));
5427	AssertMsg(pCache->TestIn.HCPhysVmcs == pCache->TestOut.HCPhysVmcs, ("%RHp vs %RHp\n", pCache->TestIn.HCPhysVmcs,
5428	pCache->TestOut.HCPhysVmcs));
5429	AssertMsg(pCache->TestIn.pCache == pCache->TestOut.pCache, ("%RGv vs %RGv\n", pCache->TestIn.pCache,
5430	pCache->TestOut.pCache));
5431	AssertMsg(pCache->TestIn.pCache == VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache),
5432	("%RGv vs %RGv\n", pCache->TestIn.pCache, VM_RC_ADDR(pVM, &pVM->aCpus[pVCpu->idCpu].hm.s.vmx.VMCSCache)));
5433	AssertMsg(pCache->TestIn.pCtx == pCache->TestOut.pCtx, ("%RGv vs %RGv\n", pCache->TestIn.pCtx,
5434	pCache->TestOut.pCtx));
5435	Assert(!(pCache->TestOut.eflags & X86_EFL_IF));
5436	#endif
5437	return rc;
5438	}
5439
5440
5441	/**
5442	* Initialize the VMCS-Read cache.
5443	*
5444	* The VMCS cache is used for 32-bit hosts running 64-bit guests (except 32-bit
5445	* Darwin which runs with 64-bit paging in 32-bit mode) for 64-bit fields that
5446	* cannot be accessed in 32-bit mode. Some 64-bit fields -can- be accessed
5447	* (those that have a 32-bit FULL & HIGH part).
5448	*
5449	* @returns VBox status code.
5450	* @param pVM The cross context VM structure.
5451	* @param pVCpu The cross context virtual CPU structure.
5452	*/
5453	static int hmR0VmxInitVmcsReadCache(PVM pVM, PVMCPU pVCpu)
5454	{
5455	#define VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, idxField) \
5456	{ \
5457	Assert(pCache->Read.aField[idxField##_CACHE_IDX] == 0); \
5458	pCache->Read.aField[idxField##_CACHE_IDX] = idxField; \
5459	pCache->Read.aFieldVal[idxField##_CACHE_IDX] = 0; \
5460	++cReadFields; \
5461	}
5462
5463	AssertPtr(pVM);
5464	AssertPtr(pVCpu);
5465	PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
5466	uint32_t cReadFields = 0;
5467
5468	/*
5469	* Don't remove the #if 0'd fields in this code. They're listed here for consistency
5470	* and serve to indicate exceptions to the rules.
5471	*/
5472
5473	/* Guest-natural selector base fields. */
5474	#if 0
5475	/* These are 32-bit in practice. See Intel spec. 2.5 "Control Registers". */
5476	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR0);
5477	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR4);
5478	#endif
5479	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_ES_BASE);
5480	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CS_BASE);
5481	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SS_BASE);
5482	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_DS_BASE);
5483	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_FS_BASE);
5484	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_GS_BASE);
5485	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_LDTR_BASE);
5486	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_TR_BASE);
5487	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_GDTR_BASE);
5488	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_IDTR_BASE);
5489	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_RSP);
5490	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_RIP);
5491	#if 0
5492	/* Unused natural width guest-state fields. */
5493	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS);
5494	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR3); /* Handled in Nested Paging case */
5495	#endif
5496	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SYSENTER_ESP);
5497	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_SYSENTER_EIP);
5498
5499	/* 64-bit guest-state fields; unused as we use two 32-bit VMREADs for these 64-bit fields (using "FULL" and "HIGH" fields). */
5500	#if 0
5501	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL);
5502	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_DEBUGCTL_FULL);
5503	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PAT_FULL);
5504	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_EFER_FULL);
5505	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL);
5506	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE0_FULL);
5507	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE1_FULL);
5508	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE2_FULL);
5509	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS64_GUEST_PDPTE3_FULL);
5510	#endif
5511
5512	/* Natural width guest-state fields. */
5513	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_RO_EXIT_QUALIFICATION);
5514	#if 0
5515	/* Currently unused field. */
5516	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR);
5517	#endif
5518
5519	if (pVM->hm.s.fNestedPaging)
5520	{
5521	VMXLOCAL_INIT_READ_CACHE_FIELD(pCache, VMX_VMCS_GUEST_CR3);
5522	AssertMsg(cReadFields == VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX, ("cReadFields=%u expected %u\n", cReadFields,
5523	VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX));
5524	pCache->Read.cValidEntries = VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX;
5525	}
5526	else
5527	{
5528	AssertMsg(cReadFields == VMX_VMCS_MAX_CACHE_IDX, ("cReadFields=%u expected %u\n", cReadFields, VMX_VMCS_MAX_CACHE_IDX));
5529	pCache->Read.cValidEntries = VMX_VMCS_MAX_CACHE_IDX;
5530	}
5531
5532	#undef VMXLOCAL_INIT_READ_CACHE_FIELD
5533	return VINF_SUCCESS;
5534	}
5535
5536
5537	/**
5538	* Writes a field into the VMCS. This can either directly invoke a VMWRITE or
5539	* queue up the VMWRITE by using the VMCS write cache (on 32-bit hosts, except
5540	* darwin, running 64-bit guests).
5541	*
5542	* @returns VBox status code.
5543	* @param pVCpu The cross context virtual CPU structure.
5544	* @param idxField The VMCS field encoding.
5545	* @param u64Val 16, 32 or 64-bit value.
5546	*/
5547	VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
5548	{
5549	int rc;
5550	switch (idxField)
5551	{
5552	/*
5553	* These fields consists of a "FULL" and a "HIGH" part which can be written to individually.
5554	*/
5555	/* 64-bit Control fields. */
5556	case VMX_VMCS64_CTRL_IO_BITMAP_A_FULL:
5557	case VMX_VMCS64_CTRL_IO_BITMAP_B_FULL:
5558	case VMX_VMCS64_CTRL_MSR_BITMAP_FULL:
5559	case VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL:
5560	case VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL:
5561	case VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL:
5562	case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
5563	case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
5564	case VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL:
5565	case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
5566	case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
5567	case VMX_VMCS64_CTRL_EPTP_FULL:
5568	case VMX_VMCS64_CTRL_EPTP_LIST_FULL:
5569	/* 64-bit Guest-state fields. */
5570	case VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL:
5571	case VMX_VMCS64_GUEST_DEBUGCTL_FULL:
5572	case VMX_VMCS64_GUEST_PAT_FULL:
5573	case VMX_VMCS64_GUEST_EFER_FULL:
5574	case VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL:
5575	case VMX_VMCS64_GUEST_PDPTE0_FULL:
5576	case VMX_VMCS64_GUEST_PDPTE1_FULL:
5577	case VMX_VMCS64_GUEST_PDPTE2_FULL:
5578	case VMX_VMCS64_GUEST_PDPTE3_FULL:
5579	/* 64-bit Host-state fields. */
5580	case VMX_VMCS64_HOST_PAT_FULL:
5581	case VMX_VMCS64_HOST_EFER_FULL:
5582	case VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL:
5583	{
5584	rc = VMXWriteVmcs32(idxField, u64Val);
5585	rc \|= VMXWriteVmcs32(idxField + 1, (uint32_t)(u64Val >> 32));
5586	break;
5587	}
5588
5589	/*
5590	* These fields do not have high and low parts. Queue up the VMWRITE by using the VMCS write-cache (for 64-bit
5591	* values). When we switch the host to 64-bit mode for running 64-bit guests, these VMWRITEs get executed then.
5592	*/
5593	/* Natural-width Guest-state fields. */
5594	case VMX_VMCS_GUEST_CR3:
5595	case VMX_VMCS_GUEST_ES_BASE:
5596	case VMX_VMCS_GUEST_CS_BASE:
5597	case VMX_VMCS_GUEST_SS_BASE:
5598	case VMX_VMCS_GUEST_DS_BASE:
5599	case VMX_VMCS_GUEST_FS_BASE:
5600	case VMX_VMCS_GUEST_GS_BASE:
5601	case VMX_VMCS_GUEST_LDTR_BASE:
5602	case VMX_VMCS_GUEST_TR_BASE:
5603	case VMX_VMCS_GUEST_GDTR_BASE:
5604	case VMX_VMCS_GUEST_IDTR_BASE:
5605	case VMX_VMCS_GUEST_RSP:
5606	case VMX_VMCS_GUEST_RIP:
5607	case VMX_VMCS_GUEST_SYSENTER_ESP:
5608	case VMX_VMCS_GUEST_SYSENTER_EIP:
5609	{
5610	if (!(u64Val >> 32))
5611	{
5612	/* If this field is 64-bit, VT-x will zero out the top bits. */
5613	rc = VMXWriteVmcs32(idxField, (uint32_t)u64Val);
5614	}
5615	else
5616	{
5617	/* Assert that only the 32->64 switcher case should ever come here. */
5618	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests);
5619	rc = VMXWriteCachedVmcsEx(pVCpu, idxField, u64Val);
5620	}
5621	break;
5622	}
5623
5624	default:
5625	{
5626	AssertMsgFailed(("VMXWriteVmcs64Ex: Invalid field %#RX32 (pVCpu=%p u64Val=%#RX64)\n", idxField, pVCpu, u64Val));
5627	rc = VERR_INVALID_PARAMETER;
5628	break;
5629	}
5630	}
5631	AssertRCReturn(rc, rc);
5632	return rc;
5633	}
5634
5635
5636	/**
5637	* Queue up a VMWRITE by using the VMCS write cache.
5638	* This is only used on 32-bit hosts (except darwin) for 64-bit guests.
5639	*
5640	* @param pVCpu The cross context virtual CPU structure.
5641	* @param idxField The VMCS field encoding.
5642	* @param u64Val 16, 32 or 64-bit value.
5643	*/
5644	VMMR0DECL(int) VMXWriteCachedVmcsEx(PVMCPU pVCpu, uint32_t idxField, uint64_t u64Val)
5645	{
5646	AssertPtr(pVCpu);
5647	PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
5648
5649	AssertMsgReturn(pCache->Write.cValidEntries < VMCSCACHE_MAX_ENTRY - 1,
5650	("entries=%u\n", pCache->Write.cValidEntries), VERR_ACCESS_DENIED);
5651
5652	/* Make sure there are no duplicates. */
5653	for (uint32_t i = 0; i < pCache->Write.cValidEntries; i++)
5654	{
5655	if (pCache->Write.aField[i] == idxField)
5656	{
5657	pCache->Write.aFieldVal[i] = u64Val;
5658	return VINF_SUCCESS;
5659	}
5660	}
5661
5662	pCache->Write.aField[pCache->Write.cValidEntries] = idxField;
5663	pCache->Write.aFieldVal[pCache->Write.cValidEntries] = u64Val;
5664	pCache->Write.cValidEntries++;
5665	return VINF_SUCCESS;
5666	}
5667	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
5668
5669
5670	/**
5671	* Sets up the usage of TSC-offsetting and updates the VMCS.
5672	*
5673	* If offsetting is not possible, cause VM-exits on RDTSC(P)s. Also sets up the
5674	* VMX preemption timer.
5675	*
5676	* @returns VBox status code.
5677	* @param pVM The cross context VM structure.
5678	* @param pVCpu The cross context virtual CPU structure.
5679	*
5680	* @remarks No-long-jump zone!!!
5681	*/
5682	static void hmR0VmxUpdateTscOffsettingAndPreemptTimer(PVM pVM, PVMCPU pVCpu)
5683	{
5684	int rc;
5685	bool fOffsettedTsc;
5686	bool fParavirtTsc;
5687	if (pVM->hm.s.vmx.fUsePreemptTimer)
5688	{
5689	uint64_t cTicksToDeadline = TMCpuTickGetDeadlineAndTscOffset(pVM, pVCpu, &pVCpu->hm.s.vmx.u64TSCOffset,
5690	&fOffsettedTsc, &fParavirtTsc);
5691
5692	/* Make sure the returned values have sane upper and lower boundaries. */
5693	uint64_t u64CpuHz = SUPGetCpuHzFromGipBySetIndex(g_pSUPGlobalInfoPage, pVCpu->iHostCpuSet);
5694	cTicksToDeadline = RT_MIN(cTicksToDeadline, u64CpuHz / 64); /* 1/64th of a second */
5695	cTicksToDeadline = RT_MAX(cTicksToDeadline, u64CpuHz / 2048); /* 1/2048th of a second */
5696	cTicksToDeadline >>= pVM->hm.s.vmx.cPreemptTimerShift;
5697
5698	uint32_t cPreemptionTickCount = (uint32_t)RT_MIN(cTicksToDeadline, UINT32_MAX - 16);
5699	rc = VMXWriteVmcs32(VMX_VMCS32_GUEST_PREEMPT_TIMER_VALUE, cPreemptionTickCount); AssertRC(rc);
5700	}
5701	else
5702	fOffsettedTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &pVCpu->hm.s.vmx.u64TSCOffset, &fParavirtTsc);
5703
5704	/** @todo later optimize this to be done elsewhere and not before every
5705	* VM-entry. */
5706	if (fParavirtTsc)
5707	{
5708	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
5709	information before every VM-entry, hence disable it for performance sake. */
5710	#if 0
5711	rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
5712	AssertRC(rc);
5713	#endif
5714	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
5715	}
5716
5717	if (fOffsettedTsc && RT_LIKELY(!pVCpu->hm.s.fDebugWantRdTscExit))
5718	{
5719	/* Note: VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT takes precedence over TSC_OFFSET, applies to RDTSCP too. */
5720	rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_TSC_OFFSET_FULL, pVCpu->hm.s.vmx.u64TSCOffset); AssertRC(rc);
5721
5722	pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT;
5723	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls); AssertRC(rc);
5724	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
5725	}
5726	else
5727	{
5728	/* We can't use TSC-offsetting (non-fixed TSC, warp drive active etc.), VM-exit on RDTSC(P). */
5729	pVCpu->hm.s.vmx.u32ProcCtls \|= VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT;
5730	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls); AssertRC(rc);
5731	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
5732	}
5733	}
5734
5735
5736	/**
5737	* Determines if an exception is a contributory exception.
5738	*
5739	* Contributory exceptions are ones which can cause double-faults unless the
5740	* original exception was a benign exception. Page-fault is intentionally not
5741	* included here as it's a conditional contributory exception.
5742	*
5743	* @returns true if the exception is contributory, false otherwise.
5744	* @param uVector The exception vector.
5745	*/
5746	DECLINLINE(bool) hmR0VmxIsContributoryXcpt(const uint32_t uVector)
5747	{
5748	switch (uVector)
5749	{
5750	case X86_XCPT_GP:
5751	case X86_XCPT_SS:
5752	case X86_XCPT_NP:
5753	case X86_XCPT_TS:
5754	case X86_XCPT_DE:
5755	return true;
5756	default:
5757	break;
5758	}
5759	return false;
5760	}
5761
5762
5763	/**
5764	* Sets an event as a pending event to be injected into the guest.
5765	*
5766	* @param pVCpu The cross context virtual CPU structure.
5767	* @param u32IntInfo The VM-entry interruption-information field.
5768	* @param cbInstr The VM-entry instruction length in bytes (for software
5769	* interrupts, exceptions and privileged software
5770	* exceptions).
5771	* @param u32ErrCode The VM-entry exception error code.
5772	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
5773	* page-fault.
5774	*
5775	* @remarks Statistics counter assumes this is a guest event being injected or
5776	* re-injected into the guest, i.e. 'StatInjectPendingReflect' is
5777	* always incremented.
5778	*/
5779	DECLINLINE(void) hmR0VmxSetPendingEvent(PVMCPU pVCpu, uint32_t u32IntInfo, uint32_t cbInstr, uint32_t u32ErrCode,
5780	RTGCUINTPTR GCPtrFaultAddress)
5781	{
5782	Assert(!pVCpu->hm.s.Event.fPending);
5783	pVCpu->hm.s.Event.fPending = true;
5784	pVCpu->hm.s.Event.u64IntInfo = u32IntInfo;
5785	pVCpu->hm.s.Event.u32ErrCode = u32ErrCode;
5786	pVCpu->hm.s.Event.cbInstr = cbInstr;
5787	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
5788	}
5789
5790
5791	/**
5792	* Sets a double-fault (\#DF) exception as pending-for-injection into the VM.
5793	*
5794	* @param pVCpu The cross context virtual CPU structure.
5795	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
5796	* out-of-sync. Make sure to update the required fields
5797	* before using them.
5798	*/
5799	DECLINLINE(void) hmR0VmxSetPendingXcptDF(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
5800	{
5801	NOREF(pMixedCtx);
5802	uint32_t u32IntInfo = X86_XCPT_DF \| VMX_EXIT_INTERRUPTION_INFO_VALID;
5803	u32IntInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
5804	u32IntInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
5805	hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr /, 0 / u32ErrCode /, 0 / GCPtrFaultAddress */);
5806	}
5807
5808
5809	/**
5810	* Handle a condition that occurred while delivering an event through the guest
5811	* IDT.
5812	*
5813	* @returns Strict VBox status code (i.e. informational status codes too).
5814	* @retval VINF_SUCCESS if we should continue handling the VM-exit.
5815	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought
5816	* to continue execution of the guest which will delivery the \#DF.
5817	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5818	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5819	*
5820	* @param pVCpu The cross context virtual CPU structure.
5821	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
5822	* out-of-sync. Make sure to update the required fields
5823	* before using them.
5824	* @param pVmxTransient Pointer to the VMX transient structure.
5825	*
5826	* @remarks No-long-jump zone!!!
5827	*/
5828	static VBOXSTRICTRC hmR0VmxCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
5829	{
5830	uint32_t uExitVector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVmxTransient->uExitIntInfo);
5831
5832	int rc2 = hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient); AssertRCReturn(rc2, rc2);
5833	rc2 = hmR0VmxReadExitIntInfoVmcs(pVmxTransient); AssertRCReturn(rc2, rc2);
5834
5835	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
5836	if (VMX_IDT_VECTORING_INFO_VALID(pVmxTransient->uIdtVectoringInfo))
5837	{
5838	uint32_t uIdtVectorType = VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uIdtVectoringInfo);
5839	uint32_t uIdtVector = VMX_IDT_VECTORING_INFO_VECTOR(pVmxTransient->uIdtVectoringInfo);
5840
5841	typedef enum
5842	{
5843	VMXREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
5844	VMXREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
5845	VMXREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
5846	VMXREFLECTXCPT_HANG, /* Indicate bad VM trying to deadlock the CPU. */
5847	VMXREFLECTXCPT_NONE /* Nothing to reflect. */
5848	} VMXREFLECTXCPT;
5849
5850	/* See Intel spec. 30.7.1.1 "Reflecting Exceptions to Guest Software". */
5851	VMXREFLECTXCPT enmReflect = VMXREFLECTXCPT_NONE;
5852	if (VMX_EXIT_INTERRUPTION_INFO_IS_VALID(pVmxTransient->uExitIntInfo))
5853	{
5854	if (uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT)
5855	{
5856	enmReflect = VMXREFLECTXCPT_XCPT;
5857	#ifdef VBOX_STRICT
5858	if ( hmR0VmxIsContributoryXcpt(uIdtVector)
5859	&& uExitVector == X86_XCPT_PF)
5860	{
5861	Log4(("IDT: vcpu[%RU32] Contributory #PF uCR2=%#RX64\n", pVCpu->idCpu, pMixedCtx->cr2));
5862	}
5863	#endif
5864	if ( uExitVector == X86_XCPT_PF
5865	&& uIdtVector == X86_XCPT_PF)
5866	{
5867	pVmxTransient->fVectoringDoublePF = true;
5868	Log4(("IDT: vcpu[%RU32] Vectoring Double #PF uCR2=%#RX64\n", pVCpu->idCpu, pMixedCtx->cr2));
5869	}
5870	else if ( uExitVector == X86_XCPT_AC
5871	&& uIdtVector == X86_XCPT_AC)
5872	{
5873	enmReflect = VMXREFLECTXCPT_HANG;
5874	Log4(("IDT: Nested #AC - Bad guest\n"));
5875	}
5876	else if ( (pVCpu->hm.s.vmx.u32XcptBitmap & HMVMX_CONTRIBUTORY_XCPT_MASK)
5877	&& hmR0VmxIsContributoryXcpt(uExitVector)
5878	&& ( hmR0VmxIsContributoryXcpt(uIdtVector)
5879	\|\| uIdtVector == X86_XCPT_PF))
5880	{
5881	enmReflect = VMXREFLECTXCPT_DF;
5882	}
5883	else if (uIdtVector == X86_XCPT_DF)
5884	enmReflect = VMXREFLECTXCPT_TF;
5885	}
5886	else if ( uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT
5887	\|\| uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_NMI)
5888	{
5889	/*
5890	* Ignore software interrupts (INT n), software exceptions (#BP, #OF) and
5891	* privileged software exception (#DB from ICEBP) as they reoccur when restarting the instruction.
5892	*/
5893	enmReflect = VMXREFLECTXCPT_XCPT;
5894
5895	if (uExitVector == X86_XCPT_PF)
5896	{
5897	pVmxTransient->fVectoringPF = true;
5898	Log4(("IDT: vcpu[%RU32] Vectoring #PF due to Ext-Int/NMI. uCR2=%#RX64\n", pVCpu->idCpu, pMixedCtx->cr2));
5899	}
5900	}
5901	}
5902	else if ( uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
5903	\|\| uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_EXT_INT
5904	\|\| uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_NMI)
5905	{
5906	/*
5907	* If event delivery caused an EPT violation/misconfig or APIC access VM-exit, then the VM-exit
5908	* interruption-information will not be valid as it's not an exception and we end up here. In such cases,
5909	* it is sufficient to reflect the original exception to the guest after handling the VM-exit.
5910	*/
5911	enmReflect = VMXREFLECTXCPT_XCPT;
5912	}
5913
5914	/*
5915	* On CPUs that support Virtual NMIs, if this VM-exit (be it an exception or EPT violation/misconfig etc.) occurred
5916	* while delivering the NMI, we need to clear the block-by-NMI field in the guest interruptibility-state before
5917	* re-delivering the NMI after handling the VM-exit. Otherwise the subsequent VM-entry would fail.
5918	*
5919	* See Intel spec. 30.7.1.2 "Resuming Guest Software after Handling an Exception". See @bugref{7445}.
5920	*/
5921	if ( uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_NMI
5922	&& enmReflect == VMXREFLECTXCPT_XCPT
5923	&& (pVCpu->hm.s.vmx.u32PinCtls & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI)
5924	&& VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
5925	{
5926	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5927	}
5928
5929	switch (enmReflect)
5930	{
5931	case VMXREFLECTXCPT_XCPT:
5932	{
5933	Assert( uIdtVectorType != VMX_IDT_VECTORING_INFO_TYPE_SW_INT
5934	&& uIdtVectorType != VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT
5935	&& uIdtVectorType != VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT);
5936
5937	uint32_t u32ErrCode = 0;
5938	if (VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(pVmxTransient->uIdtVectoringInfo))
5939	{
5940	rc2 = hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
5941	AssertRCReturn(rc2, rc2);
5942	u32ErrCode = pVmxTransient->uIdtVectoringErrorCode;
5943	}
5944
5945	/* If uExitVector is #PF, CR2 value will be updated from the VMCS if it's a guest #PF. See hmR0VmxExitXcptPF(). */
5946	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5947	hmR0VmxSetPendingEvent(pVCpu, VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(pVmxTransient->uIdtVectoringInfo),
5948	0 /* cbInstr */, u32ErrCode, pMixedCtx->cr2);
5949	rcStrict = VINF_SUCCESS;
5950	Log4(("IDT: vcpu[%RU32] Pending vectoring event %#RX64 Err=%#RX32\n", pVCpu->idCpu,
5951	pVCpu->hm.s.Event.u64IntInfo, pVCpu->hm.s.Event.u32ErrCode));
5952
5953	break;
5954	}
5955
5956	case VMXREFLECTXCPT_DF:
5957	{
5958	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5959	hmR0VmxSetPendingXcptDF(pVCpu, pMixedCtx);
5960	rcStrict = VINF_HM_DOUBLE_FAULT;
5961	Log4(("IDT: vcpu[%RU32] Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->idCpu,
5962	pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
5963
5964	break;
5965	}
5966
5967	case VMXREFLECTXCPT_TF:
5968	{
5969	rcStrict = VINF_EM_RESET;
5970	Log4(("IDT: vcpu[%RU32] Pending vectoring triple-fault uIdt=%#x uExit=%#x\n", pVCpu->idCpu, uIdtVector,
5971	uExitVector));
5972	break;
5973	}
5974
5975	case VMXREFLECTXCPT_HANG:
5976	{
5977	rcStrict = VERR_EM_GUEST_CPU_HANG;
5978	break;
5979	}
5980
5981	default:
5982	Assert(rcStrict == VINF_SUCCESS);
5983	break;
5984	}
5985	}
5986	else if ( VMX_EXIT_INTERRUPTION_INFO_IS_VALID(pVmxTransient->uExitIntInfo)
5987	&& VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK_IRET(pVmxTransient->uExitIntInfo)
5988	&& uExitVector != X86_XCPT_DF
5989	&& (pVCpu->hm.s.vmx.u32PinCtls & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI))
5990	{
5991	/*
5992	* Execution of IRET caused this fault when NMI blocking was in effect (i.e we're in the guest NMI handler).
5993	* We need to set the block-by-NMI field so that NMIs remain blocked until the IRET execution is restarted.
5994	* See Intel spec. 30.7.1.2 "Resuming guest software after handling an exception".
5995	*/
5996	if (!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
5997	{
5998	Log4(("hmR0VmxCheckExitDueToEventDelivery: vcpu[%RU32] Setting VMCPU_FF_BLOCK_NMIS. Valid=%RTbool uExitReason=%u\n",
5999	pVCpu->idCpu, VMX_EXIT_INTERRUPTION_INFO_IS_VALID(pVmxTransient->uExitIntInfo), pVmxTransient->uExitReason));
6000	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6001	}
6002	}
6003
6004	Assert( rcStrict == VINF_SUCCESS \|\| rcStrict == VINF_HM_DOUBLE_FAULT
6005	\|\| rcStrict == VINF_EM_RESET \|\| rcStrict == VERR_EM_GUEST_CPU_HANG);
6006	return rcStrict;
6007	}
6008
6009
6010	/**
6011	* Saves the guest's CR0 register from the VMCS into the guest-CPU context.
6012	*
6013	* @returns VBox status code.
6014	* @param pVCpu The cross context virtual CPU structure.
6015	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6016	* out-of-sync. Make sure to update the required fields
6017	* before using them.
6018	*
6019	* @remarks No-long-jump zone!!!
6020	*/
6021	static int hmR0VmxSaveGuestCR0(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6022	{
6023	NOREF(pMixedCtx);
6024
6025	/*
6026	* While in the middle of saving guest-CR0, we could get preempted and re-invoked from the preemption hook,
6027	* see hmR0VmxLeave(). Safer to just make this code non-preemptible.
6028	*/
6029	VMMRZCallRing3Disable(pVCpu);
6030	HM_DISABLE_PREEMPT();
6031
6032	if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR0))
6033	{
6034	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
6035	uint32_t uVal = 0;
6036	uint32_t uShadow = 0;
6037	int rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &uVal);
6038	rc \|= VMXReadVmcs32(VMX_VMCS_CTRL_CR0_READ_SHADOW, &uShadow);
6039	AssertRCReturn(rc, rc);
6040
6041	uVal = (uShadow & pVCpu->hm.s.vmx.u32CR0Mask) \| (uVal & ~pVCpu->hm.s.vmx.u32CR0Mask);
6042	CPUMSetGuestCR0(pVCpu, uVal);
6043	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR0);
6044	}
6045
6046	HM_RESTORE_PREEMPT();
6047	VMMRZCallRing3Enable(pVCpu);
6048	return VINF_SUCCESS;
6049	}
6050
6051
6052	/**
6053	* Saves the guest's CR4 register from the VMCS into the guest-CPU context.
6054	*
6055	* @returns VBox status code.
6056	* @param pVCpu The cross context virtual CPU structure.
6057	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6058	* out-of-sync. Make sure to update the required fields
6059	* before using them.
6060	*
6061	* @remarks No-long-jump zone!!!
6062	*/
6063	static int hmR0VmxSaveGuestCR4(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6064	{
6065	NOREF(pMixedCtx);
6066
6067	int rc = VINF_SUCCESS;
6068	if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR4))
6069	{
6070	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4));
6071	uint32_t uVal = 0;
6072	uint32_t uShadow = 0;
6073	rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR4, &uVal);
6074	rc \|= VMXReadVmcs32(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uShadow);
6075	AssertRCReturn(rc, rc);
6076
6077	uVal = (uShadow & pVCpu->hm.s.vmx.u32CR4Mask) \| (uVal & ~pVCpu->hm.s.vmx.u32CR4Mask);
6078	CPUMSetGuestCR4(pVCpu, uVal);
6079	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR4);
6080	}
6081	return rc;
6082	}
6083
6084
6085	/**
6086	* Saves the guest's RIP register from the VMCS into the guest-CPU context.
6087	*
6088	* @returns VBox status code.
6089	* @param pVCpu The cross context virtual CPU structure.
6090	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6091	* out-of-sync. Make sure to update the required fields
6092	* before using them.
6093	*
6094	* @remarks No-long-jump zone!!!
6095	*/
6096	static int hmR0VmxSaveGuestRip(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6097	{
6098	int rc = VINF_SUCCESS;
6099	if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RIP))
6100	{
6101	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RIP));
6102	uint64_t u64Val = 0;
6103	rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RIP, &u64Val);
6104	AssertRCReturn(rc, rc);
6105
6106	pMixedCtx->rip = u64Val;
6107	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RIP);
6108	}
6109	return rc;
6110	}
6111
6112
6113	/**
6114	* Saves the guest's RSP register from the VMCS into the guest-CPU context.
6115	*
6116	* @returns VBox status code.
6117	* @param pVCpu The cross context virtual CPU structure.
6118	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6119	* out-of-sync. Make sure to update the required fields
6120	* before using them.
6121	*
6122	* @remarks No-long-jump zone!!!
6123	*/
6124	static int hmR0VmxSaveGuestRsp(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6125	{
6126	int rc = VINF_SUCCESS;
6127	if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RSP))
6128	{
6129	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RSP));
6130	uint64_t u64Val = 0;
6131	rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_RSP, &u64Val);
6132	AssertRCReturn(rc, rc);
6133
6134	pMixedCtx->rsp = u64Val;
6135	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RSP);
6136	}
6137	return rc;
6138	}
6139
6140
6141	/**
6142	* Saves the guest's RFLAGS from the VMCS into the guest-CPU context.
6143	*
6144	* @returns VBox status code.
6145	* @param pVCpu The cross context virtual CPU structure.
6146	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6147	* out-of-sync. Make sure to update the required fields
6148	* before using them.
6149	*
6150	* @remarks No-long-jump zone!!!
6151	*/
6152	static int hmR0VmxSaveGuestRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6153	{
6154	if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RFLAGS))
6155	{
6156	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RFLAGS));
6157	uint32_t uVal = 0;
6158	int rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &uVal);
6159	AssertRCReturn(rc, rc);
6160
6161	pMixedCtx->eflags.u32 = uVal;
6162	if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active) /* Undo our real-on-v86-mode changes to eflags if necessary. */
6163	{
6164	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
6165	Log4(("Saving real-mode EFLAGS VT-x view=%#RX32\n", pMixedCtx->eflags.u32));
6166
6167	pMixedCtx->eflags.Bits.u1VM = 0;
6168	pMixedCtx->eflags.Bits.u2IOPL = pVCpu->hm.s.vmx.RealMode.Eflags.Bits.u2IOPL;
6169	}
6170
6171	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RFLAGS);
6172	}
6173	return VINF_SUCCESS;
6174	}
6175
6176
6177	/**
6178	* Wrapper for saving the guest's RIP, RSP and RFLAGS from the VMCS into the
6179	* guest-CPU context.
6180	*/
6181	DECLINLINE(int) hmR0VmxSaveGuestRipRspRflags(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6182	{
6183	int rc = hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
6184	rc \|= hmR0VmxSaveGuestRsp(pVCpu, pMixedCtx);
6185	rc \|= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
6186	return rc;
6187	}
6188
6189
6190	/**
6191	* Saves the guest's interruptibility-state ("interrupt shadow" as AMD calls it)
6192	* from the guest-state area in the VMCS.
6193	*
6194	* @param pVCpu The cross context virtual CPU structure.
6195	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6196	* out-of-sync. Make sure to update the required fields
6197	* before using them.
6198	*
6199	* @remarks No-long-jump zone!!!
6200	*/
6201	static void hmR0VmxSaveGuestIntrState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6202	{
6203	if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_INTR_STATE))
6204	{
6205	uint32_t uIntrState = 0;
6206	int rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &uIntrState);
6207	AssertRC(rc);
6208
6209	if (!uIntrState)
6210	{
6211	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6212	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6213
6214	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
6215	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6216	}
6217	else
6218	{
6219	if (uIntrState & ( VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS
6220	\| VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI))
6221	{
6222	rc = hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
6223	AssertRC(rc);
6224	rc = hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx); /* for hmR0VmxGetGuestIntrState(). */
6225	AssertRC(rc);
6226
6227	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
6228	Assert(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
6229	}
6230	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
6231	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6232
6233	if (uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI)
6234	{
6235	if (!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
6236	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
6237	}
6238	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
6239	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6240	}
6241
6242	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_INTR_STATE);
6243	}
6244	}
6245
6246
6247	/**
6248	* Saves the guest's activity state.
6249	*
6250	* @returns VBox status code.
6251	* @param pVCpu The cross context virtual CPU structure.
6252	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6253	* out-of-sync. Make sure to update the required fields
6254	* before using them.
6255	*
6256	* @remarks No-long-jump zone!!!
6257	*/
6258	static int hmR0VmxSaveGuestActivityState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6259	{
6260	NOREF(pMixedCtx);
6261	/* Nothing to do for now until we make use of different guest-CPU activity state. Just update the flag. */
6262	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_ACTIVITY_STATE);
6263	return VINF_SUCCESS;
6264	}
6265
6266
6267	/**
6268	* Saves the guest SYSENTER MSRs (SYSENTER_CS, SYSENTER_EIP, SYSENTER_ESP) from
6269	* the current VMCS into the guest-CPU context.
6270	*
6271	* @returns VBox status code.
6272	* @param pVCpu The cross context virtual CPU structure.
6273	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6274	* out-of-sync. Make sure to update the required fields
6275	* before using them.
6276	*
6277	* @remarks No-long-jump zone!!!
6278	*/
6279	static int hmR0VmxSaveGuestSysenterMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6280	{
6281	if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR))
6282	{
6283	Assert(!HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR));
6284	uint32_t u32Val = 0;
6285	int rc = VMXReadVmcs32(VMX_VMCS32_GUEST_SYSENTER_CS, &u32Val); AssertRCReturn(rc, rc);
6286	pMixedCtx->SysEnter.cs = u32Val;
6287	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR);
6288	}
6289
6290	if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR))
6291	{
6292	Assert(!HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR));
6293	uint64_t u64Val = 0;
6294	int rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_SYSENTER_EIP, &u64Val); AssertRCReturn(rc, rc);
6295	pMixedCtx->SysEnter.eip = u64Val;
6296	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR);
6297	}
6298	if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR))
6299	{
6300	Assert(!HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR));
6301	uint64_t u64Val = 0;
6302	int rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_SYSENTER_ESP, &u64Val); AssertRCReturn(rc, rc);
6303	pMixedCtx->SysEnter.esp = u64Val;
6304	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR);
6305	}
6306	return VINF_SUCCESS;
6307	}
6308
6309
6310	/**
6311	* Saves the set of guest MSRs (that we restore lazily while leaving VT-x) from
6312	* the CPU back into the guest-CPU context.
6313	*
6314	* @returns VBox status code.
6315	* @param pVCpu The cross context virtual CPU structure.
6316	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6317	* out-of-sync. Make sure to update the required fields
6318	* before using them.
6319	*
6320	* @remarks No-long-jump zone!!!
6321	*/
6322	static int hmR0VmxSaveGuestLazyMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6323	{
6324	/* Since this can be called from our preemption hook it's safer to make the guest-MSRs update non-preemptible. */
6325	VMMRZCallRing3Disable(pVCpu);
6326	HM_DISABLE_PREEMPT();
6327
6328	/* Doing the check here ensures we don't overwrite already-saved guest MSRs from a preemption hook. */
6329	if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_LAZY_MSRS))
6330	{
6331	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS));
6332	hmR0VmxLazySaveGuestMsrs(pVCpu, pMixedCtx);
6333	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_LAZY_MSRS);
6334	}
6335
6336	HM_RESTORE_PREEMPT();
6337	VMMRZCallRing3Enable(pVCpu);
6338
6339	return VINF_SUCCESS;
6340	}
6341
6342
6343	/**
6344	* Saves the auto load/store'd guest MSRs from the current VMCS into
6345	* the guest-CPU context.
6346	*
6347	* @returns VBox status code.
6348	* @param pVCpu The cross context virtual CPU structure.
6349	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6350	* out-of-sync. Make sure to update the required fields
6351	* before using them.
6352	*
6353	* @remarks No-long-jump zone!!!
6354	*/
6355	static int hmR0VmxSaveGuestAutoLoadStoreMsrs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6356	{
6357	if (HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS))
6358	return VINF_SUCCESS;
6359
6360	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS));
6361	PVMXAUTOMSR pMsr = (PVMXAUTOMSR)pVCpu->hm.s.vmx.pvGuestMsr;
6362	uint32_t cMsrs = pVCpu->hm.s.vmx.cMsrs;
6363	Log4(("hmR0VmxSaveGuestAutoLoadStoreMsrs: cMsrs=%u\n", cMsrs));
6364	for (uint32_t i = 0; i < cMsrs; i++, pMsr++)
6365	{
6366	switch (pMsr->u32Msr)
6367	{
6368	case MSR_K8_TSC_AUX: CPUMR0SetGuestTscAux(pVCpu, pMsr->u64Value); break;
6369	case MSR_K8_LSTAR: pMixedCtx->msrLSTAR = pMsr->u64Value; break;
6370	case MSR_K6_STAR: pMixedCtx->msrSTAR = pMsr->u64Value; break;
6371	case MSR_K8_SF_MASK: pMixedCtx->msrSFMASK = pMsr->u64Value; break;
6372	case MSR_K8_KERNEL_GS_BASE: pMixedCtx->msrKERNELGSBASE = pMsr->u64Value; break;
6373	case MSR_K6_EFER: /* Nothing to do here since we intercept writes, see hmR0VmxLoadGuestMsrs(). */
6374	break;
6375
6376	default:
6377	{
6378	AssertMsgFailed(("Unexpected MSR in auto-load/store area. uMsr=%#RX32 cMsrs=%u\n", pMsr->u32Msr, cMsrs));
6379	pVCpu->hm.s.u32HMError = pMsr->u32Msr;
6380	return VERR_HM_UNEXPECTED_LD_ST_MSR;
6381	}
6382	}
6383	}
6384
6385	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS);
6386	return VINF_SUCCESS;
6387	}
6388
6389
6390	/**
6391	* Saves the guest control registers from the current VMCS into the guest-CPU
6392	* context.
6393	*
6394	* @returns VBox status code.
6395	* @param pVCpu The cross context virtual CPU structure.
6396	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6397	* out-of-sync. Make sure to update the required fields
6398	* before using them.
6399	*
6400	* @remarks No-long-jump zone!!!
6401	*/
6402	static int hmR0VmxSaveGuestControlRegs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6403	{
6404	/* Guest CR0. Guest FPU. */
6405	int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
6406	AssertRCReturn(rc, rc);
6407
6408	/* Guest CR4. */
6409	rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
6410	AssertRCReturn(rc, rc);
6411
6412	/* Guest CR2 - updated always during the world-switch or in #PF. */
6413	/* Guest CR3. Only changes with Nested Paging. This must be done -after- saving CR0 and CR4 from the guest! */
6414	if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR3))
6415	{
6416	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3));
6417	Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR0));
6418	Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR4));
6419
6420	PVM pVM = pVCpu->CTX_SUFF(pVM);
6421	if ( pVM->hm.s.vmx.fUnrestrictedGuest
6422	\|\| ( pVM->hm.s.fNestedPaging
6423	&& CPUMIsGuestPagingEnabledEx(pMixedCtx)))
6424	{
6425	uint64_t u64Val = 0;
6426	rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_CR3, &u64Val);
6427	if (pMixedCtx->cr3 != u64Val)
6428	{
6429	CPUMSetGuestCR3(pVCpu, u64Val);
6430	if (VMMRZCallRing3IsEnabled(pVCpu))
6431	{
6432	PGMUpdateCR3(pVCpu, u64Val);
6433	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
6434	}
6435	else
6436	{
6437	/* Set the force flag to inform PGM about it when necessary. It is cleared by PGMUpdateCR3().*/
6438	VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
6439	}
6440	}
6441
6442	/* If the guest is in PAE mode, sync back the PDPE's into the guest state. */
6443	if (CPUMIsGuestInPAEModeEx(pMixedCtx)) /* Reads CR0, CR4 and EFER MSR (EFER is always up-to-date). */
6444	{
6445	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &pVCpu->hm.s.aPdpes[0].u);
6446	rc \|= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &pVCpu->hm.s.aPdpes[1].u);
6447	rc \|= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &pVCpu->hm.s.aPdpes[2].u);
6448	rc \|= VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &pVCpu->hm.s.aPdpes[3].u);
6449	AssertRCReturn(rc, rc);
6450
6451	if (VMMRZCallRing3IsEnabled(pVCpu))
6452	{
6453	PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
6454	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
6455	}
6456	else
6457	{
6458	/* Set the force flag to inform PGM about it when necessary. It is cleared by PGMGstUpdatePaePdpes(). */
6459	VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
6460	}
6461	}
6462	}
6463
6464	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR3);
6465	}
6466
6467	/*
6468	* Consider this scenario: VM-exit -> VMMRZCallRing3Enable() -> do stuff that causes a longjmp -> hmR0VmxCallRing3Callback()
6469	* -> VMMRZCallRing3Disable() -> hmR0VmxSaveGuestState() -> Set VMCPU_FF_HM_UPDATE_CR3 pending -> return from the longjmp
6470	* -> continue with VM-exit handling -> hmR0VmxSaveGuestControlRegs() and here we are.
6471	*
6472	* The reason for such complicated handling is because VM-exits that call into PGM expect CR3 to be up-to-date and thus
6473	* if any CR3-saves -before- the VM-exit (longjmp) postponed the CR3 update via the force-flag, any VM-exit handler that
6474	* calls into PGM when it re-saves CR3 will end up here and we call PGMUpdateCR3(). This is why the code below should
6475	* -NOT- check if HMVMX_UPDATED_GUEST_CR3 is already set or not!
6476	*
6477	* The longjmp exit path can't check these CR3 force-flags and call code that takes a lock again. We cover for it here.
6478	*/
6479	if (VMMRZCallRing3IsEnabled(pVCpu))
6480	{
6481	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
6482	PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
6483
6484	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
6485	PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
6486
6487	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
6488	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
6489	}
6490
6491	return rc;
6492	}
6493
6494
6495	/**
6496	* Reads a guest segment register from the current VMCS into the guest-CPU
6497	* context.
6498	*
6499	* @returns VBox status code.
6500	* @param pVCpu The cross context virtual CPU structure.
6501	* @param idxSel Index of the selector in the VMCS.
6502	* @param idxLimit Index of the segment limit in the VMCS.
6503	* @param idxBase Index of the segment base in the VMCS.
6504	* @param idxAccess Index of the access rights of the segment in the VMCS.
6505	* @param pSelReg Pointer to the segment selector.
6506	*
6507	* @remarks No-long-jump zone!!!
6508	* @remarks Never call this function directly!!! Use the VMXLOCAL_READ_SEG()
6509	* macro as that takes care of whether to read from the VMCS cache or
6510	* not.
6511	*/
6512	DECLINLINE(int) hmR0VmxReadSegmentReg(PVMCPU pVCpu, uint32_t idxSel, uint32_t idxLimit, uint32_t idxBase, uint32_t idxAccess,
6513	PCPUMSELREG pSelReg)
6514	{
6515	NOREF(pVCpu);
6516
6517	uint32_t u32Val = 0;
6518	int rc = VMXReadVmcs32(idxSel, &u32Val);
6519	AssertRCReturn(rc, rc);
6520	pSelReg->Sel = (uint16_t)u32Val;
6521	pSelReg->ValidSel = (uint16_t)u32Val;
6522	pSelReg->fFlags = CPUMSELREG_FLAGS_VALID;
6523
6524	rc = VMXReadVmcs32(idxLimit, &u32Val);
6525	AssertRCReturn(rc, rc);
6526	pSelReg->u32Limit = u32Val;
6527
6528	uint64_t u64Val = 0;
6529	rc = VMXReadVmcsGstNByIdxVal(idxBase, &u64Val);
6530	AssertRCReturn(rc, rc);
6531	pSelReg->u64Base = u64Val;
6532
6533	rc = VMXReadVmcs32(idxAccess, &u32Val);
6534	AssertRCReturn(rc, rc);
6535	pSelReg->Attr.u = u32Val;
6536
6537	/*
6538	* If VT-x marks the segment as unusable, most other bits remain undefined:
6539	* - For CS the L, D and G bits have meaning.
6540	* - For SS the DPL has meaning (it -is- the CPL for Intel and VBox).
6541	* - For the remaining data segments no bits are defined.
6542	*
6543	* The present bit and the unusable bit has been observed to be set at the
6544	* same time (the selector was supposed to be invalid as we started executing
6545	* a V8086 interrupt in ring-0).
6546	*
6547	* What should be important for the rest of the VBox code, is that the P bit is
6548	* cleared. Some of the other VBox code recognizes the unusable bit, but
6549	* AMD-V certainly don't, and REM doesn't really either. So, to be on the
6550	* safe side here, we'll strip off P and other bits we don't care about. If
6551	* any code breaks because Attr.u != 0 when Sel < 4, it should be fixed.
6552	*
6553	* See Intel spec. 27.3.2 "Saving Segment Registers and Descriptor-Table Registers".
6554	*/
6555	if (pSelReg->Attr.u & X86DESCATTR_UNUSABLE)
6556	{
6557	Assert(idxSel != VMX_VMCS16_GUEST_TR_SEL); /* TR is the only selector that can never be unusable. */
6558
6559	/* Masking off: X86DESCATTR_P, X86DESCATTR_LIMIT_HIGH, and X86DESCATTR_AVL. The latter two are really irrelevant. */
6560	pSelReg->Attr.u &= X86DESCATTR_UNUSABLE \| X86DESCATTR_L \| X86DESCATTR_D \| X86DESCATTR_G
6561	\| X86DESCATTR_DPL \| X86DESCATTR_TYPE \| X86DESCATTR_DT;
6562
6563	Log4(("hmR0VmxReadSegmentReg: Unusable idxSel=%#x attr=%#x -> %#x\n", idxSel, u32Val, pSelReg->Attr.u));
6564	#ifdef DEBUG_bird
6565	AssertMsg((u32Val & ~X86DESCATTR_P) == pSelReg->Attr.u,
6566	("%#x: %#x != %#x (sel=%#x base=%#llx limit=%#x)\n",
6567	idxSel, u32Val, pSelReg->Attr.u, pSelReg->Sel, pSelReg->u64Base, pSelReg->u32Limit));
6568	#endif
6569	}
6570	return VINF_SUCCESS;
6571	}
6572
6573
6574	#ifdef VMX_USE_CACHED_VMCS_ACCESSES
6575	# define VMXLOCAL_READ_SEG(Sel, CtxSel) \
6576	hmR0VmxReadSegmentReg(pVCpu, VMX_VMCS16_GUEST_##Sel##_SEL, VMX_VMCS32_GUEST_##Sel##_LIMIT, \
6577	VMX_VMCS_GUEST_##Sel##_BASE_CACHE_IDX, VMX_VMCS32_GUEST_##Sel##_ACCESS_RIGHTS, &pMixedCtx->CtxSel)
6578	#else
6579	# define VMXLOCAL_READ_SEG(Sel, CtxSel) \
6580	hmR0VmxReadSegmentReg(pVCpu, VMX_VMCS16_GUEST_##Sel##_SEL, VMX_VMCS32_GUEST_##Sel##_LIMIT, \
6581	VMX_VMCS_GUEST_##Sel##_BASE, VMX_VMCS32_GUEST_##Sel##_ACCESS_RIGHTS, &pMixedCtx->CtxSel)
6582	#endif
6583
6584
6585	/**
6586	* Saves the guest segment registers from the current VMCS into the guest-CPU
6587	* context.
6588	*
6589	* @returns VBox status code.
6590	* @param pVCpu The cross context virtual CPU structure.
6591	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6592	* out-of-sync. Make sure to update the required fields
6593	* before using them.
6594	*
6595	* @remarks No-long-jump zone!!!
6596	*/
6597	static int hmR0VmxSaveGuestSegmentRegs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6598	{
6599	/* Guest segment registers. */
6600	if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SEGMENT_REGS))
6601	{
6602	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS));
6603	int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
6604	AssertRCReturn(rc, rc);
6605
6606	rc = VMXLOCAL_READ_SEG(CS, cs);
6607	rc \|= VMXLOCAL_READ_SEG(SS, ss);
6608	rc \|= VMXLOCAL_READ_SEG(DS, ds);
6609	rc \|= VMXLOCAL_READ_SEG(ES, es);
6610	rc \|= VMXLOCAL_READ_SEG(FS, fs);
6611	rc \|= VMXLOCAL_READ_SEG(GS, gs);
6612	AssertRCReturn(rc, rc);
6613
6614	/* Restore segment attributes for real-on-v86 mode hack. */
6615	if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6616	{
6617	pMixedCtx->cs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrCS.u;
6618	pMixedCtx->ss.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrSS.u;
6619	pMixedCtx->ds.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrDS.u;
6620	pMixedCtx->es.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrES.u;
6621	pMixedCtx->fs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrFS.u;
6622	pMixedCtx->gs.Attr.u = pVCpu->hm.s.vmx.RealMode.AttrGS.u;
6623	}
6624	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SEGMENT_REGS);
6625	}
6626
6627	return VINF_SUCCESS;
6628	}
6629
6630
6631	/**
6632	* Saves the guest descriptor table registers and task register from the current
6633	* VMCS into the guest-CPU context.
6634	*
6635	* @returns VBox status code.
6636	* @param pVCpu The cross context virtual CPU structure.
6637	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6638	* out-of-sync. Make sure to update the required fields
6639	* before using them.
6640	*
6641	* @remarks No-long-jump zone!!!
6642	*/
6643	static int hmR0VmxSaveGuestTableRegs(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6644	{
6645	int rc = VINF_SUCCESS;
6646
6647	/* Guest LDTR. */
6648	if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_LDTR))
6649	{
6650	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR));
6651	rc = VMXLOCAL_READ_SEG(LDTR, ldtr);
6652	AssertRCReturn(rc, rc);
6653	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_LDTR);
6654	}
6655
6656	/* Guest GDTR. */
6657	uint64_t u64Val = 0;
6658	uint32_t u32Val = 0;
6659	if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_GDTR))
6660	{
6661	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR));
6662	rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_GDTR_BASE, &u64Val);
6663	rc \|= VMXReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val); AssertRCReturn(rc, rc);
6664	pMixedCtx->gdtr.pGdt = u64Val;
6665	pMixedCtx->gdtr.cbGdt = u32Val;
6666	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_GDTR);
6667	}
6668
6669	/* Guest IDTR. */
6670	if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_IDTR))
6671	{
6672	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR));
6673	rc = VMXReadVmcsGstN(VMX_VMCS_GUEST_IDTR_BASE, &u64Val);
6674	rc \|= VMXReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val); AssertRCReturn(rc, rc);
6675	pMixedCtx->idtr.pIdt = u64Val;
6676	pMixedCtx->idtr.cbIdt = u32Val;
6677	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_IDTR);
6678	}
6679
6680	/* Guest TR. */
6681	if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_TR))
6682	{
6683	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR));
6684	rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
6685	AssertRCReturn(rc, rc);
6686
6687	/* For real-mode emulation using virtual-8086 mode we have the fake TSS (pRealModeTSS) in TR, don't save the fake one. */
6688	if (!pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
6689	{
6690	rc = VMXLOCAL_READ_SEG(TR, tr);
6691	AssertRCReturn(rc, rc);
6692	}
6693	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_TR);
6694	}
6695	return rc;
6696	}
6697
6698	#undef VMXLOCAL_READ_SEG
6699
6700
6701	/**
6702	* Saves the guest debug-register DR7 from the current VMCS into the guest-CPU
6703	* context.
6704	*
6705	* @returns VBox status code.
6706	* @param pVCpu The cross context virtual CPU structure.
6707	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6708	* out-of-sync. Make sure to update the required fields
6709	* before using them.
6710	*
6711	* @remarks No-long-jump zone!!!
6712	*/
6713	static int hmR0VmxSaveGuestDR7(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6714	{
6715	if (!HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_DR7))
6716	{
6717	if (!pVCpu->hm.s.fUsingHyperDR7)
6718	{
6719	/* Upper 32-bits are always zero. See Intel spec. 2.7.3 "Loading and Storing Debug Registers". */
6720	uint32_t u32Val;
6721	int rc = VMXReadVmcs32(VMX_VMCS_GUEST_DR7, &u32Val); AssertRCReturn(rc, rc);
6722	pMixedCtx->dr[7] = u32Val;
6723	}
6724
6725	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_DR7);
6726	}
6727	return VINF_SUCCESS;
6728	}
6729
6730
6731	/**
6732	* Saves the guest APIC state from the current VMCS into the guest-CPU context.
6733	*
6734	* @returns VBox status code.
6735	* @param pVCpu The cross context virtual CPU structure.
6736	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
6737	* out-of-sync. Make sure to update the required fields
6738	* before using them.
6739	*
6740	* @remarks No-long-jump zone!!!
6741	*/
6742	static int hmR0VmxSaveGuestApicState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6743	{
6744	NOREF(pMixedCtx);
6745
6746	/* Updating TPR is already done in hmR0VmxPostRunGuest(). Just update the flag. */
6747	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_APIC_STATE);
6748	return VINF_SUCCESS;
6749	}
6750
6751
6752	/**
6753	* Saves the entire guest state from the currently active VMCS into the
6754	* guest-CPU context.
6755	*
6756	* This essentially VMREADs all guest-data.
6757	*
6758	* @returns VBox status code.
6759	* @param pVCpu The cross context virtual CPU structure.
6760	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
6761	* out-of-sync. Make sure to update the required fields
6762	* before using them.
6763	*/
6764	static int hmR0VmxSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6765	{
6766	Assert(pVCpu);
6767	Assert(pMixedCtx);
6768
6769	if (HMVMXCPU_GST_VALUE(pVCpu) == HMVMX_UPDATED_GUEST_ALL)
6770	return VINF_SUCCESS;
6771
6772	/* Though we can longjmp to ring-3 due to log-flushes here and get recalled
6773	again on the ring-3 callback path, there is no real need to. */
6774	if (VMMRZCallRing3IsEnabled(pVCpu))
6775	VMMR0LogFlushDisable(pVCpu);
6776	else
6777	Assert(VMMR0IsLogFlushDisabled(pVCpu));
6778	Log4Func(("vcpu[%RU32]\n", pVCpu->idCpu));
6779
6780	int rc = hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
6781	AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestRipRspRflags failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6782
6783	rc = hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
6784	AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestControlRegs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6785
6786	rc = hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
6787	AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestSegmentRegs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6788
6789	rc = hmR0VmxSaveGuestTableRegs(pVCpu, pMixedCtx);
6790	AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestTableRegs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6791
6792	rc = hmR0VmxSaveGuestDR7(pVCpu, pMixedCtx);
6793	AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestDR7 failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6794
6795	rc = hmR0VmxSaveGuestSysenterMsrs(pVCpu, pMixedCtx);
6796	AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestSysenterMsrs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6797
6798	rc = hmR0VmxSaveGuestLazyMsrs(pVCpu, pMixedCtx);
6799	AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestLazyMsrs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6800
6801	rc = hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx);
6802	AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestAutoLoadStoreMsrs failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6803
6804	rc = hmR0VmxSaveGuestActivityState(pVCpu, pMixedCtx);
6805	AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestActivityState failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6806
6807	rc = hmR0VmxSaveGuestApicState(pVCpu, pMixedCtx);
6808	AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveGuestApicState failed! rc=%Rrc (pVCpu=%p)\n", rc, pVCpu), rc);
6809
6810	AssertMsg(HMVMXCPU_GST_VALUE(pVCpu) == HMVMX_UPDATED_GUEST_ALL,
6811	("Missed guest state bits while saving state; missing %RX32 (got %RX32, want %RX32) - check log for any previous errors!\n",
6812	HMVMX_UPDATED_GUEST_ALL ^ HMVMXCPU_GST_VALUE(pVCpu), HMVMXCPU_GST_VALUE(pVCpu), HMVMX_UPDATED_GUEST_ALL));
6813
6814	if (VMMRZCallRing3IsEnabled(pVCpu))
6815	VMMR0LogFlushEnable(pVCpu);
6816
6817	return VINF_SUCCESS;
6818	}
6819
6820
6821	/**
6822	* Saves basic guest registers needed for IEM instruction execution.
6823	*
6824	* @returns VBox status code (OR-able).
6825	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
6826	* @param pMixedCtx Pointer to the CPU context of the guest.
6827	* @param fMemory Whether the instruction being executed operates on
6828	* memory or not. Only CR0 is synced up if clear.
6829	* @param fNeedRsp Need RSP (any instruction working on GPRs or stack).
6830	*/
6831	static int hmR0VmxSaveGuestRegsForIemExec(PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fMemory, bool fNeedRsp)
6832	{
6833	/*
6834	* We assume all general purpose registers other than RSP are available.
6835	*
6836	* - RIP is a must, as it will be incremented or otherwise changed.
6837	* - RFLAGS are always required to figure the CPL.
6838	* - RSP isn't always required, however it's a GPR, so frequently required.
6839	* - SS and CS are the only segment register needed if IEM doesn't do memory
6840	* access (CPL + 16/32/64-bit mode), but we can only get all segment registers.
6841	* - CR0 is always required by IEM for the CPL, while CR3 and CR4 will only
6842	* be required for memory accesses.
6843	*
6844	* Note! Before IEM dispatches an exception, it will call us to sync in everything.
6845	*/
6846	int rc = hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
6847	rc \|= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
6848	if (fNeedRsp)
6849	rc \|= hmR0VmxSaveGuestRsp(pVCpu, pMixedCtx);
6850	rc \|= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
6851	if (!fMemory)
6852	rc \|= hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
6853	else
6854	rc \|= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
6855	AssertRCReturn(rc, rc);
6856	return rc;
6857	}
6858
6859
6860	/**
6861	* Ensures that we've got a complete basic guest-context.
6862	*
6863	* This excludes the FPU, SSE, AVX, and similar extended state. The interface
6864	* is for the interpreter.
6865	*
6866	* @returns VBox status code.
6867	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
6868	* @param pMixedCtx Pointer to the guest-CPU context which may have data
6869	* needing to be synced in.
6870	* @thread EMT(pVCpu)
6871	*/
6872	VMMR0_INT_DECL(int) HMR0EnsureCompleteBasicContext(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
6873	{
6874	/* Note! Since this is only applicable to VT-x, the implementation is placed
6875	in the VT-x part of the sources instead of the generic stuff. */
6876	if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported)
6877	{
6878	int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
6879	/*
6880	* For now, imply that the caller might change everything too. Do this after
6881	* saving the guest state so as to not trigger assertions.
6882	*/
6883	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
6884	return rc;
6885	}
6886	return VINF_SUCCESS;
6887	}
6888
6889
6890	/**
6891	* Check per-VM and per-VCPU force flag actions that require us to go back to
6892	* ring-3 for one reason or another.
6893	*
6894	* @returns Strict VBox status code (i.e. informational status codes too)
6895	* @retval VINF_SUCCESS if we don't have any actions that require going back to
6896	* ring-3.
6897	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
6898	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
6899	* interrupts)
6900	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
6901	* all EMTs to be in ring-3.
6902	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
6903	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
6904	* to the EM loop.
6905	*
6906	* @param pVM The cross context VM structure.
6907	* @param pVCpu The cross context virtual CPU structure.
6908	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
6909	* out-of-sync. Make sure to update the required fields
6910	* before using them.
6911	* @param fStepping Running in hmR0VmxRunGuestCodeStep().
6912	*/
6913	static VBOXSTRICTRC hmR0VmxCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fStepping)
6914	{
6915	Assert(VMMRZCallRing3IsEnabled(pVCpu));
6916
6917	/*
6918	* Anything pending? Should be more likely than not if we're doing a good job.
6919	*/
6920	if ( !fStepping
6921	? !VM_FF_IS_PENDING(pVM, VM_FF_HP_R0_PRE_HM_MASK)
6922	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HP_R0_PRE_HM_MASK)
6923	: !VM_FF_IS_PENDING(pVM, VM_FF_HP_R0_PRE_HM_STEP_MASK)
6924	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
6925	return VINF_SUCCESS;
6926
6927	/* We need the control registers now, make sure the guest-CPU context is updated. */
6928	int rc3 = hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
6929	AssertRCReturn(rc3, rc3);
6930
6931	/* Pending HM CR3 sync. */
6932	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
6933	{
6934	int rc2 = PGMUpdateCR3(pVCpu, pMixedCtx->cr3);
6935	AssertMsgReturn(rc2 == VINF_SUCCESS \|\| rc2 == VINF_PGM_SYNC_CR3,
6936	("%Rrc\n", rc2), RT_FAILURE_NP(rc2) ? rc2 : VERR_IPE_UNEXPECTED_INFO_STATUS);
6937	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
6938	}
6939
6940	/* Pending HM PAE PDPEs. */
6941	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
6942	{
6943	PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
6944	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
6945	}
6946
6947	/* Pending PGM C3 sync. */
6948	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
6949	{
6950	VBOXSTRICTRC rcStrict2 = PGMSyncCR3(pVCpu, pMixedCtx->cr0, pMixedCtx->cr3, pMixedCtx->cr4,
6951	VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
6952	if (rcStrict2 != VINF_SUCCESS)
6953	{
6954	AssertRC(VBOXSTRICTRC_VAL(rcStrict2));
6955	Log4(("hmR0VmxCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc2=%d\n", VBOXSTRICTRC_VAL(rcStrict2)));
6956	return rcStrict2;
6957	}
6958	}
6959
6960	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
6961	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
6962	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
6963	{
6964	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
6965	int rc2 = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
6966	Log4(("hmR0VmxCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc2));
6967	return rc2;
6968	}
6969
6970	/* Pending VM request packets, such as hardware interrupts. */
6971	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
6972	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
6973	{
6974	Log4(("hmR0VmxCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
6975	return VINF_EM_PENDING_REQUEST;
6976	}
6977
6978	/* Pending PGM pool flushes. */
6979	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
6980	{
6981	Log4(("hmR0VmxCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
6982	return VINF_PGM_POOL_FLUSH_PENDING;
6983	}
6984
6985	/* Pending DMA requests. */
6986	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
6987	{
6988	Log4(("hmR0VmxCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
6989	return VINF_EM_RAW_TO_R3;
6990	}
6991
6992	return VINF_SUCCESS;
6993	}
6994
6995
6996	/**
6997	* Converts any TRPM trap into a pending HM event. This is typically used when
6998	* entering from ring-3 (not longjmp returns).
6999	*
7000	* @param pVCpu The cross context virtual CPU structure.
7001	*/
7002	static void hmR0VmxTrpmTrapToPendingEvent(PVMCPU pVCpu)
7003	{
7004	Assert(TRPMHasTrap(pVCpu));
7005	Assert(!pVCpu->hm.s.Event.fPending);
7006
7007	uint8_t uVector;
7008	TRPMEVENT enmTrpmEvent;
7009	RTGCUINT uErrCode;
7010	RTGCUINTPTR GCPtrFaultAddress;
7011	uint8_t cbInstr;
7012
7013	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
7014	AssertRC(rc);
7015
7016	/* Refer Intel spec. 24.8.3 "VM-entry Controls for Event Injection" for the format of u32IntInfo. */
7017	uint32_t u32IntInfo = uVector \| VMX_EXIT_INTERRUPTION_INFO_VALID;
7018	if (enmTrpmEvent == TRPM_TRAP)
7019	{
7020	switch (uVector)
7021	{
7022	case X86_XCPT_NMI:
7023	u32IntInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7024	break;
7025
7026	case X86_XCPT_BP:
7027	case X86_XCPT_OF:
7028	u32IntInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7029	break;
7030
7031	case X86_XCPT_PF:
7032	case X86_XCPT_DF:
7033	case X86_XCPT_TS:
7034	case X86_XCPT_NP:
7035	case X86_XCPT_SS:
7036	case X86_XCPT_GP:
7037	case X86_XCPT_AC:
7038	u32IntInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
7039	/* fall thru */
7040	default:
7041	u32IntInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7042	break;
7043	}
7044	}
7045	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
7046	u32IntInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7047	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
7048	u32IntInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7049	else
7050	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
7051
7052	rc = TRPMResetTrap(pVCpu);
7053	AssertRC(rc);
7054	Log4(("TRPM->HM event: u32IntInfo=%#RX32 enmTrpmEvent=%d cbInstr=%u uErrCode=%#RX32 GCPtrFaultAddress=%#RGv\n",
7055	u32IntInfo, enmTrpmEvent, cbInstr, uErrCode, GCPtrFaultAddress));
7056
7057	hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, cbInstr, uErrCode, GCPtrFaultAddress);
7058	}
7059
7060
7061	/**
7062	* Converts the pending HM event into a TRPM trap.
7063	*
7064	* @param pVCpu The cross context virtual CPU structure.
7065	*/
7066	static void hmR0VmxPendingEventToTrpmTrap(PVMCPU pVCpu)
7067	{
7068	Assert(pVCpu->hm.s.Event.fPending);
7069
7070	uint32_t uVectorType = VMX_IDT_VECTORING_INFO_TYPE(pVCpu->hm.s.Event.u64IntInfo);
7071	uint32_t uVector = VMX_IDT_VECTORING_INFO_VECTOR(pVCpu->hm.s.Event.u64IntInfo);
7072	bool fErrorCodeValid = VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(pVCpu->hm.s.Event.u64IntInfo);
7073	uint32_t uErrorCode = pVCpu->hm.s.Event.u32ErrCode;
7074
7075	/* If a trap was already pending, we did something wrong! */
7076	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
7077
7078	TRPMEVENT enmTrapType;
7079	switch (uVectorType)
7080	{
7081	case VMX_IDT_VECTORING_INFO_TYPE_EXT_INT:
7082	enmTrapType = TRPM_HARDWARE_INT;
7083	break;
7084
7085	case VMX_IDT_VECTORING_INFO_TYPE_SW_INT:
7086	enmTrapType = TRPM_SOFTWARE_INT;
7087	break;
7088
7089	case VMX_IDT_VECTORING_INFO_TYPE_NMI:
7090	case VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT:
7091	case VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT: /* #BP and #OF */
7092	case VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT:
7093	enmTrapType = TRPM_TRAP;
7094	break;
7095
7096	default:
7097	AssertMsgFailed(("Invalid trap type %#x\n", uVectorType));
7098	enmTrapType = TRPM_32BIT_HACK;
7099	break;
7100	}
7101
7102	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, enmTrapType));
7103
7104	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
7105	AssertRC(rc);
7106
7107	if (fErrorCodeValid)
7108	TRPMSetErrorCode(pVCpu, uErrorCode);
7109
7110	if ( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
7111	&& uVector == X86_XCPT_PF)
7112	{
7113	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
7114	}
7115	else if ( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
7116	\|\| uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT
7117	\|\| uVectorType == VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT)
7118	{
7119	AssertMsg( uVectorType == VMX_IDT_VECTORING_INFO_TYPE_SW_INT
7120	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
7121	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
7122	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
7123	}
7124
7125	/* Clear any pending events from the VMCS. */
7126	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, 0); AssertRC(rc);
7127	rc = VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, 0); AssertRC(rc);
7128
7129	/* We're now done converting the pending event. */
7130	pVCpu->hm.s.Event.fPending = false;
7131	}
7132
7133
7134	/**
7135	* Does the necessary state syncing before returning to ring-3 for any reason
7136	* (longjmp, preemption, voluntary exits to ring-3) from VT-x.
7137	*
7138	* @returns VBox status code.
7139	* @param pVCpu The cross context virtual CPU structure.
7140	* @param pMixedCtx Pointer to the guest-CPU context. The data may
7141	* be out-of-sync. Make sure to update the required
7142	* fields before using them.
7143	* @param fSaveGuestState Whether to save the guest state or not.
7144	*
7145	* @remarks No-long-jmp zone!!!
7146	*/
7147	static int hmR0VmxLeave(PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fSaveGuestState)
7148	{
7149	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
7150	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
7151
7152	RTCPUID idCpu = RTMpCpuId();
7153	Log4Func(("HostCpuId=%u\n", idCpu));
7154
7155	/*
7156	* !!! IMPORTANT !!!
7157	* If you modify code here, check whether hmR0VmxCallRing3Callback() needs to be updated too.
7158	*/
7159
7160	/* Save the guest state if necessary. */
7161	if ( fSaveGuestState
7162	&& HMVMXCPU_GST_VALUE(pVCpu) != HMVMX_UPDATED_GUEST_ALL)
7163	{
7164	int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
7165	AssertRCReturn(rc, rc);
7166	Assert(HMVMXCPU_GST_VALUE(pVCpu) == HMVMX_UPDATED_GUEST_ALL);
7167	}
7168
7169	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
7170	if (CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu))
7171	{
7172	/* We shouldn't reload CR0 without saving it first. */
7173	if (!fSaveGuestState)
7174	{
7175	int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
7176	AssertRCReturn(rc, rc);
7177	}
7178	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
7179	}
7180
7181	/* Restore host debug registers if necessary and resync on next R0 reentry. */
7182	#ifdef VBOX_STRICT
7183	if (CPUMIsHyperDebugStateActive(pVCpu))
7184	Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
7185	#endif
7186	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, true /* save DR6 */))
7187	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
7188	Assert(!CPUMIsGuestDebugStateActive(pVCpu) && !CPUMIsGuestDebugStateActivePending(pVCpu));
7189	Assert(!CPUMIsHyperDebugStateActive(pVCpu) && !CPUMIsHyperDebugStateActivePending(pVCpu));
7190
7191	#if HC_ARCH_BITS == 64
7192	/* Restore host-state bits that VT-x only restores partially. */
7193	if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
7194	&& (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
7195	{
7196	Log4Func(("Restoring Host State: fRestoreHostFlags=%#RX32 HostCpuId=%u\n", pVCpu->hm.s.vmx.fRestoreHostFlags, idCpu));
7197	VMXRestoreHostState(pVCpu->hm.s.vmx.fRestoreHostFlags, &pVCpu->hm.s.vmx.RestoreHost);
7198	}
7199	pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
7200	#endif
7201
7202	/* Restore the lazy host MSRs as we're leaving VT-x context. */
7203	if (pVCpu->hm.s.vmx.fLazyMsrs)
7204	{
7205	/* We shouldn't reload the guest MSRs without saving it first. */
7206	if (!fSaveGuestState)
7207	{
7208	int rc = hmR0VmxSaveGuestLazyMsrs(pVCpu, pMixedCtx);
7209	AssertRCReturn(rc, rc);
7210	}
7211	Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_LAZY_MSRS));
7212	hmR0VmxLazyRestoreHostMsrs(pVCpu);
7213	Assert(!pVCpu->hm.s.vmx.fLazyMsrs);
7214	}
7215
7216	/* Update auto-load/store host MSRs values when we re-enter VT-x (as we could be on a different CPU). */
7217	pVCpu->hm.s.vmx.fUpdatedHostMsrs = false;
7218
7219	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
7220	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
7221	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
7222	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
7223	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitIO);
7224	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitMovCRx);
7225	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitXcptNmi);
7226	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
7227
7228	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
7229
7230	/** @todo This partially defeats the purpose of having preemption hooks.
7231	* The problem is, deregistering the hooks should be moved to a place that
7232	* lasts until the EMT is about to be destroyed not everytime while leaving HM
7233	* context.
7234	*/
7235	if (pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_ACTIVE)
7236	{
7237	int rc = VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
7238	AssertRCReturn(rc, rc);
7239
7240	pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
7241	Log4Func(("Cleared Vmcs. HostCpuId=%u\n", idCpu));
7242	}
7243	Assert(!(pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_LAUNCHED));
7244	NOREF(idCpu);
7245
7246	return VINF_SUCCESS;
7247	}
7248
7249
7250	/**
7251	* Leaves the VT-x session.
7252	*
7253	* @returns VBox status code.
7254	* @param pVCpu The cross context virtual CPU structure.
7255	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
7256	* out-of-sync. Make sure to update the required fields
7257	* before using them.
7258	*
7259	* @remarks No-long-jmp zone!!!
7260	*/
7261	DECLINLINE(int) hmR0VmxLeaveSession(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
7262	{
7263	HM_DISABLE_PREEMPT();
7264	HMVMX_ASSERT_CPU_SAFE();
7265	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
7266	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
7267
7268	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
7269	and done this from the VMXR0ThreadCtxCallback(). */
7270	if (!pVCpu->hm.s.fLeaveDone)
7271	{
7272	int rc2 = hmR0VmxLeave(pVCpu, pMixedCtx, true /* fSaveGuestState */);
7273	AssertRCReturnStmt(rc2, HM_RESTORE_PREEMPT(), rc2);
7274	pVCpu->hm.s.fLeaveDone = true;
7275	}
7276	Assert(HMVMXCPU_GST_VALUE(pVCpu) == HMVMX_UPDATED_GUEST_ALL);
7277
7278	/*
7279	* !!! IMPORTANT !!!
7280	* If you modify code here, make sure to check whether hmR0VmxCallRing3Callback() needs to be updated too.
7281	*/
7282
7283	/* Deregister hook now that we've left HM context before re-enabling preemption. */
7284	/** @todo Deregistering here means we need to VMCLEAR always
7285	* (longjmp/exit-to-r3) in VT-x which is not efficient. */
7286	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
7287	VMMR0ThreadCtxHookDisable(pVCpu);
7288
7289	/* Leave HM context. This takes care of local init (term). */
7290	int rc = HMR0LeaveCpu(pVCpu);
7291
7292	HM_RESTORE_PREEMPT();
7293	return rc;
7294	}
7295
7296
7297	/**
7298	* Does the necessary state syncing before doing a longjmp to ring-3.
7299	*
7300	* @returns VBox status code.
7301	* @param pVCpu The cross context virtual CPU structure.
7302	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
7303	* out-of-sync. Make sure to update the required fields
7304	* before using them.
7305	*
7306	* @remarks No-long-jmp zone!!!
7307	*/
7308	DECLINLINE(int) hmR0VmxLongJmpToRing3(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
7309	{
7310	return hmR0VmxLeaveSession(pVCpu, pMixedCtx);
7311	}
7312
7313
7314	/**
7315	* Take necessary actions before going back to ring-3.
7316	*
7317	* An action requires us to go back to ring-3. This function does the necessary
7318	* steps before we can safely return to ring-3. This is not the same as longjmps
7319	* to ring-3, this is voluntary and prepares the guest so it may continue
7320	* executing outside HM (recompiler/IEM).
7321	*
7322	* @returns VBox status code.
7323	* @param pVM The cross context VM structure.
7324	* @param pVCpu The cross context virtual CPU structure.
7325	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
7326	* out-of-sync. Make sure to update the required fields
7327	* before using them.
7328	* @param rcExit The reason for exiting to ring-3. Can be
7329	* VINF_VMM_UNKNOWN_RING3_CALL.
7330	*/
7331	static int hmR0VmxExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, VBOXSTRICTRC rcExit)
7332	{
7333	Assert(pVM);
7334	Assert(pVCpu);
7335	Assert(pMixedCtx);
7336	HMVMX_ASSERT_PREEMPT_SAFE();
7337
7338	if (RT_UNLIKELY(rcExit == VERR_VMX_INVALID_VMCS_PTR))
7339	{
7340	VMXGetActivatedVmcs(&pVCpu->hm.s.vmx.LastError.u64VMCSPhys);
7341	pVCpu->hm.s.vmx.LastError.u32VMCSRevision = (uint32_t )pVCpu->hm.s.vmx.pvVmcs;
7342	pVCpu->hm.s.vmx.LastError.idEnteredCpu = pVCpu->hm.s.idEnteredCpu;
7343	/* LastError.idCurrentCpu was updated in hmR0VmxPreRunGuestCommitted(). */
7344	}
7345
7346	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
7347	VMMRZCallRing3Disable(pVCpu);
7348	Log4(("hmR0VmxExitToRing3: pVCpu=%p idCpu=%RU32 rcExit=%d\n", pVCpu, pVCpu->idCpu, VBOXSTRICTRC_VAL(rcExit)));
7349
7350	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
7351	if (pVCpu->hm.s.Event.fPending)
7352	{
7353	hmR0VmxPendingEventToTrpmTrap(pVCpu);
7354	Assert(!pVCpu->hm.s.Event.fPending);
7355	}
7356
7357	/* Clear interrupt-window and NMI-window controls as we re-evaluate it when we return from ring-3. */
7358	hmR0VmxClearIntNmiWindowsVmcs(pVCpu);
7359
7360	/* If we're emulating an instruction, we shouldn't have any TRPM traps pending
7361	and if we're injecting an event we should have a TRPM trap pending. */
7362	AssertMsg(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu), ("%Rrc\n", VBOXSTRICTRC_VAL(rcExit)));
7363	#ifndef DEBUG_bird /* Triggered after firing an NMI against NT4SP1, possibly a tripple fault in progress. */
7364	AssertMsg(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu), ("%Rrc\n", VBOXSTRICTRC_VAL(rcExit)));
7365	#endif
7366
7367	/* Save guest state and restore host state bits. */
7368	int rc = hmR0VmxLeaveSession(pVCpu, pMixedCtx);
7369	AssertRCReturn(rc, rc);
7370	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
7371	/* Thread-context hooks are unregistered at this point!!! */
7372
7373	/* Sync recompiler state. */
7374	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
7375	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
7376	\| CPUM_CHANGED_LDTR
7377	\| CPUM_CHANGED_GDTR
7378	\| CPUM_CHANGED_IDTR
7379	\| CPUM_CHANGED_TR
7380	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
7381	Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR0));
7382	if ( pVM->hm.s.fNestedPaging
7383	&& CPUMIsGuestPagingEnabledEx(pMixedCtx))
7384	{
7385	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
7386	}
7387
7388	Assert(!pVCpu->hm.s.fClearTrapFlag);
7389
7390	/* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
7391	if (rcExit != VINF_EM_RAW_INTERRUPT)
7392	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7393
7394	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
7395
7396	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
7397	VMMRZCallRing3RemoveNotification(pVCpu);
7398	VMMRZCallRing3Enable(pVCpu);
7399
7400	return rc;
7401	}
7402
7403
7404	/**
7405	* VMMRZCallRing3() callback wrapper which saves the guest state before we
7406	* longjump to ring-3 and possibly get preempted.
7407	*
7408	* @returns VBox status code.
7409	* @param pVCpu The cross context virtual CPU structure.
7410	* @param enmOperation The operation causing the ring-3 longjump.
7411	* @param pvUser Opaque pointer to the guest-CPU context. The data
7412	* may be out-of-sync. Make sure to update the required
7413	* fields before using them.
7414	*/
7415	static DECLCALLBACK(int) hmR0VmxCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
7416	{
7417	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
7418	{
7419	/*
7420	* !!! IMPORTANT !!!
7421	* If you modify code here, check whether hmR0VmxLeave() and hmR0VmxLeaveSession() needs to be updated too.
7422	* This is a stripped down version which gets out ASAP, trying to not trigger any further assertions.
7423	*/
7424	VMMRZCallRing3RemoveNotification(pVCpu);
7425	VMMRZCallRing3Disable(pVCpu);
7426	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
7427	RTThreadPreemptDisable(&PreemptState);
7428
7429	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
7430	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, true /* save DR6 */);
7431
7432	#if HC_ARCH_BITS == 64
7433	/* Restore host-state bits that VT-x only restores partially. */
7434	if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
7435	&& (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
7436	VMXRestoreHostState(pVCpu->hm.s.vmx.fRestoreHostFlags, &pVCpu->hm.s.vmx.RestoreHost);
7437	pVCpu->hm.s.vmx.fRestoreHostFlags = 0;
7438	#endif
7439	/* Restore the lazy host MSRs as we're leaving VT-x context. */
7440	if (pVCpu->hm.s.vmx.fLazyMsrs)
7441	hmR0VmxLazyRestoreHostMsrs(pVCpu);
7442
7443	/* Update auto-load/store host MSRs values when we re-enter VT-x (as we could be on a different CPU). */
7444	pVCpu->hm.s.vmx.fUpdatedHostMsrs = false;
7445	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
7446	if (pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_ACTIVE)
7447	{
7448	VMXClearVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
7449	pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_CLEAR;
7450	}
7451
7452	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
7453	VMMR0ThreadCtxHookDisable(pVCpu);
7454	HMR0LeaveCpu(pVCpu);
7455	RTThreadPreemptRestore(&PreemptState);
7456	return VINF_SUCCESS;
7457	}
7458
7459	Assert(pVCpu);
7460	Assert(pvUser);
7461	Assert(VMMRZCallRing3IsEnabled(pVCpu));
7462	HMVMX_ASSERT_PREEMPT_SAFE();
7463
7464	VMMRZCallRing3Disable(pVCpu);
7465	Assert(VMMR0IsLogFlushDisabled(pVCpu));
7466
7467	Log4(("hmR0VmxCallRing3Callback->hmR0VmxLongJmpToRing3 pVCpu=%p idCpu=%RU32 enmOperation=%d\n", pVCpu, pVCpu->idCpu,
7468	enmOperation));
7469
7470	int rc = hmR0VmxLongJmpToRing3(pVCpu, (PCPUMCTX)pvUser);
7471	AssertRCReturn(rc, rc);
7472
7473	VMMRZCallRing3Enable(pVCpu);
7474	return VINF_SUCCESS;
7475	}
7476
7477
7478	/**
7479	* Sets the interrupt-window exiting control in the VMCS which instructs VT-x to
7480	* cause a VM-exit as soon as the guest is in a state to receive interrupts.
7481	*
7482	* @param pVCpu The cross context virtual CPU structure.
7483	*/
7484	DECLINLINE(void) hmR0VmxSetIntWindowExitVmcs(PVMCPU pVCpu)
7485	{
7486	if (RT_LIKELY(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT))
7487	{
7488	if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT))
7489	{
7490	pVCpu->hm.s.vmx.u32ProcCtls \|= VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT;
7491	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
7492	AssertRC(rc);
7493	Log4(("Setup interrupt-window exiting\n"));
7494	}
7495	} /* else we will deliver interrupts whenever the guest exits next and is in a state to receive events. */
7496	}
7497
7498
7499	/**
7500	* Clears the interrupt-window exiting control in the VMCS.
7501	*
7502	* @param pVCpu The cross context virtual CPU structure.
7503	*/
7504	DECLINLINE(void) hmR0VmxClearIntWindowExitVmcs(PVMCPU pVCpu)
7505	{
7506	Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
7507	pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT;
7508	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
7509	AssertRC(rc);
7510	Log4(("Cleared interrupt-window exiting\n"));
7511	}
7512
7513
7514	/**
7515	* Sets the NMI-window exiting control in the VMCS which instructs VT-x to
7516	* cause a VM-exit as soon as the guest is in a state to receive NMIs.
7517	*
7518	* @param pVCpu The cross context virtual CPU structure.
7519	*/
7520	DECLINLINE(void) hmR0VmxSetNmiWindowExitVmcs(PVMCPU pVCpu)
7521	{
7522	if (RT_LIKELY(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT))
7523	{
7524	if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT))
7525	{
7526	pVCpu->hm.s.vmx.u32ProcCtls \|= VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT;
7527	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
7528	AssertRC(rc);
7529	Log4(("Setup NMI-window exiting\n"));
7530	}
7531	} /* else we will deliver NMIs whenever we VM-exit next, even possibly nesting NMIs. Can't be helped on ancient CPUs. */
7532	}
7533
7534
7535	/**
7536	* Clears the NMI-window exiting control in the VMCS.
7537	*
7538	* @param pVCpu The cross context virtual CPU structure.
7539	*/
7540	DECLINLINE(void) hmR0VmxClearNmiWindowExitVmcs(PVMCPU pVCpu)
7541	{
7542	Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
7543	pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT;
7544	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
7545	AssertRC(rc);
7546	Log4(("Cleared NMI-window exiting\n"));
7547	}
7548
7549
7550	/**
7551	* Evaluates the event to be delivered to the guest and sets it as the pending
7552	* event.
7553	*
7554	* @returns The VT-x guest-interruptibility state.
7555	* @param pVCpu The cross context virtual CPU structure.
7556	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
7557	* out-of-sync. Make sure to update the required fields
7558	* before using them.
7559	*/
7560	static uint32_t hmR0VmxEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
7561	{
7562	/* Get the current interruptibility-state of the guest and then figure out what can be injected. */
7563	uint32_t const uIntrState = hmR0VmxGetGuestIntrState(pVCpu, pMixedCtx);
7564	bool const fBlockMovSS = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS);
7565	bool const fBlockSti = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
7566	bool const fBlockNmi = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI);
7567
7568	Assert(!fBlockSti \|\| HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RFLAGS));
7569	Assert(!(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI)); /* We don't support block-by-SMI yet.*/
7570	Assert(!fBlockSti \|\| pMixedCtx->eflags.Bits.u1IF); /* Cannot set block-by-STI when interrupts are disabled. */
7571	Assert(!TRPMHasTrap(pVCpu));
7572
7573	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
7574	APICUpdatePendingInterrupts(pVCpu);
7575
7576	/*
7577	* Toggling of interrupt force-flags here is safe since we update TRPM on premature exits
7578	* to ring-3 before executing guest code, see hmR0VmxExitToRing3(). We must NOT restore these force-flags.
7579	*/
7580	/** @todo SMI. SMIs take priority over NMIs. */
7581	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts. */
7582	{
7583	/* On some CPUs block-by-STI also blocks NMIs. See Intel spec. 26.3.1.5 "Checks On Guest Non-Register State". */
7584	if ( !pVCpu->hm.s.Event.fPending
7585	&& !fBlockNmi
7586	&& !fBlockSti
7587	&& !fBlockMovSS)
7588	{
7589	Log4(("Pending NMI vcpu[%RU32]\n", pVCpu->idCpu));
7590	uint32_t u32IntInfo = X86_XCPT_NMI \| VMX_EXIT_INTERRUPTION_INFO_VALID;
7591	u32IntInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7592
7593	hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr /, 0 / u32ErrCode /, 0 / GCPtrFaultAddress */);
7594	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
7595	}
7596	else
7597	hmR0VmxSetNmiWindowExitVmcs(pVCpu);
7598	}
7599	/*
7600	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt() returns
7601	* a valid interrupt we must- deliver the interrupt. We can no longer re-request it from the APIC.
7602	*/
7603	else if ( VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC))
7604	&& !pVCpu->hm.s.fSingleInstruction)
7605	{
7606	Assert(!DBGFIsStepping(pVCpu));
7607	int rc = hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
7608	AssertRC(rc);
7609	bool const fBlockInt = !(pMixedCtx->eflags.u32 & X86_EFL_IF);
7610	if ( !pVCpu->hm.s.Event.fPending
7611	&& !fBlockInt
7612	&& !fBlockSti
7613	&& !fBlockMovSS)
7614	{
7615	uint8_t u8Interrupt;
7616	rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
7617	if (RT_SUCCESS(rc))
7618	{
7619	Log4(("Pending interrupt vcpu[%RU32] u8Interrupt=%#x \n", pVCpu->idCpu, u8Interrupt));
7620	uint32_t u32IntInfo = u8Interrupt \| VMX_EXIT_INTERRUPTION_INFO_VALID;
7621	u32IntInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7622
7623	hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr /, 0 / u32ErrCode /, 0 / GCPtrfaultAddress */);
7624	}
7625	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
7626	{
7627	if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
7628	hmR0VmxApicSetTprThreshold(pVCpu, u8Interrupt >> 4);
7629	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
7630
7631	/*
7632	* If the CPU doesn't have TPR shadowing, we will always get a VM-exit on TPR changes and
7633	* APICSetTpr() will end up setting the VMCPU_FF_INTERRUPT_APIC if required, so there is no
7634	* need to re-set this force-flag here.
7635	*/
7636	}
7637	else
7638	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
7639	}
7640	else
7641	hmR0VmxSetIntWindowExitVmcs(pVCpu);
7642	}
7643
7644	return uIntrState;
7645	}
7646
7647
7648	/**
7649	* Sets a pending-debug exception to be delivered to the guest if the guest is
7650	* single-stepping in the VMCS.
7651	*
7652	* @param pVCpu The cross context virtual CPU structure.
7653	*/
7654	DECLINLINE(void) hmR0VmxSetPendingDebugXcptVmcs(PVMCPU pVCpu)
7655	{
7656	Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RFLAGS)); NOREF(pVCpu);
7657	int rc = VMXWriteVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS);
7658	AssertRC(rc);
7659	}
7660
7661
7662	/**
7663	* Injects any pending events into the guest if the guest is in a state to
7664	* receive them.
7665	*
7666	* @returns Strict VBox status code (i.e. informational status codes too).
7667	* @param pVCpu The cross context virtual CPU structure.
7668	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
7669	* out-of-sync. Make sure to update the required fields
7670	* before using them.
7671	* @param uIntrState The VT-x guest-interruptibility state.
7672	* @param fStepping Running in hmR0VmxRunGuestCodeStep() and we should
7673	* return VINF_EM_DBG_STEPPED if the event was
7674	* dispatched directly.
7675	*/
7676	static VBOXSTRICTRC hmR0VmxInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint32_t uIntrState, bool fStepping)
7677	{
7678	HMVMX_ASSERT_PREEMPT_SAFE();
7679	Assert(VMMRZCallRing3IsEnabled(pVCpu));
7680
7681	bool fBlockMovSS = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS);
7682	bool fBlockSti = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
7683
7684	Assert(!fBlockSti \|\| HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RFLAGS));
7685	Assert(!(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI)); /* We don't support block-by-SMI yet.*/
7686	Assert(!fBlockSti \|\| pMixedCtx->eflags.Bits.u1IF); /* Cannot set block-by-STI when interrupts are disabled. */
7687	Assert(!TRPMHasTrap(pVCpu));
7688
7689	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
7690	if (pVCpu->hm.s.Event.fPending)
7691	{
7692	/*
7693	* Do -not- clear any interrupt-window exiting control here. We might have an interrupt
7694	* pending even while injecting an event and in this case, we want a VM-exit as soon as
7695	* the guest is ready for the next interrupt, see @bugref{6208#c45}.
7696	*
7697	* See Intel spec. 26.6.5 "Interrupt-Window Exiting and Virtual-Interrupt Delivery".
7698	*/
7699	uint32_t const uIntType = VMX_EXIT_INTERRUPTION_INFO_TYPE(pVCpu->hm.s.Event.u64IntInfo);
7700	#ifdef VBOX_STRICT
7701	if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT)
7702	{
7703	bool const fBlockInt = !(pMixedCtx->eflags.u32 & X86_EFL_IF);
7704	Assert(!fBlockInt);
7705	Assert(!fBlockSti);
7706	Assert(!fBlockMovSS);
7707	}
7708	else if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI)
7709	{
7710	bool const fBlockNmi = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI);
7711	Assert(!fBlockSti);
7712	Assert(!fBlockMovSS);
7713	Assert(!fBlockNmi);
7714	}
7715	#endif
7716	Log4(("Injecting pending event vcpu[%RU32] u64IntInfo=%#RX64 Type=%#x\n", pVCpu->idCpu, pVCpu->hm.s.Event.u64IntInfo,
7717	(uint8_t)uIntType));
7718	rcStrict = hmR0VmxInjectEventVmcs(pVCpu, pMixedCtx, pVCpu->hm.s.Event.u64IntInfo, pVCpu->hm.s.Event.cbInstr,
7719	pVCpu->hm.s.Event.u32ErrCode, pVCpu->hm.s.Event.GCPtrFaultAddress,
7720	fStepping, &uIntrState);
7721	AssertRCReturn(VBOXSTRICTRC_VAL(rcStrict), rcStrict);
7722
7723	/* Update the interruptibility-state as it could have been changed by
7724	hmR0VmxInjectEventVmcs() (e.g. real-on-v86 guest injecting software interrupts) */
7725	fBlockMovSS = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS);
7726	fBlockSti = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
7727
7728	if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT)
7729	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
7730	else
7731	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
7732	}
7733
7734	/* Deliver pending debug exception if the guest is single-stepping. Evaluate and set the BS bit. */
7735	if ( fBlockSti
7736	\|\| fBlockMovSS)
7737	{
7738	if (!pVCpu->hm.s.fSingleInstruction)
7739	{
7740	/*
7741	* The pending-debug exceptions field is cleared on all VM-exits except VMX_EXIT_TPR_BELOW_THRESHOLD,
7742	* VMX_EXIT_MTF, VMX_EXIT_APIC_WRITE and VMX_EXIT_VIRTUALIZED_EOI.
7743	* See Intel spec. 27.3.4 "Saving Non-Register State".
7744	*/
7745	Assert(!DBGFIsStepping(pVCpu));
7746	int rc2 = hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
7747	AssertRCReturn(rc2, rc2);
7748	if (pMixedCtx->eflags.Bits.u1TF)
7749	hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
7750	}
7751	else if (pMixedCtx->eflags.Bits.u1TF)
7752	{
7753	/*
7754	* We are single-stepping in the hypervisor debugger using EFLAGS.TF. Clear interrupt inhibition as setting the
7755	* BS bit would mean delivering a #DB to the guest upon VM-entry when it shouldn't be.
7756	*/
7757	Assert(!(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG));
7758	uIntrState = 0;
7759	}
7760	}
7761
7762	/*
7763	* There's no need to clear the VM-entry interruption-information field here if we're not injecting anything.
7764	* VT-x clears the valid bit on every VM-exit. See Intel spec. 24.8.3 "VM-Entry Controls for Event Injection".
7765	*/
7766	int rc2 = hmR0VmxLoadGuestIntrState(pVCpu, uIntrState);
7767	AssertRC(rc2);
7768
7769	Assert(rcStrict == VINF_SUCCESS \|\| rcStrict == VINF_EM_RESET \|\| (rcStrict == VINF_EM_DBG_STEPPED && fStepping));
7770	NOREF(fBlockMovSS); NOREF(fBlockSti);
7771	return rcStrict;
7772	}
7773
7774
7775	/**
7776	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
7777	*
7778	* @param pVCpu The cross context virtual CPU structure.
7779	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
7780	* out-of-sync. Make sure to update the required fields
7781	* before using them.
7782	*/
7783	DECLINLINE(void) hmR0VmxSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
7784	{
7785	NOREF(pMixedCtx);
7786	uint32_t u32IntInfo = X86_XCPT_UD \| VMX_EXIT_INTERRUPTION_INFO_VALID;
7787	hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr /, 0 / u32ErrCode /, 0 / GCPtrFaultAddress */);
7788	}
7789
7790
7791	/**
7792	* Injects a double-fault (\#DF) exception into the VM.
7793	*
7794	* @returns Strict VBox status code (i.e. informational status codes too).
7795	* @param pVCpu The cross context virtual CPU structure.
7796	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
7797	* out-of-sync. Make sure to update the required fields
7798	* before using them.
7799	* @param fStepping Whether we're running in hmR0VmxRunGuestCodeStep()
7800	* and should return VINF_EM_DBG_STEPPED if the event
7801	* is injected directly (register modified by us, not
7802	* by hardware on VM-entry).
7803	* @param puIntrState Pointer to the current guest interruptibility-state.
7804	* This interruptibility-state will be updated if
7805	* necessary. This cannot not be NULL.
7806	*/
7807	DECLINLINE(VBOXSTRICTRC) hmR0VmxInjectXcptDF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fStepping, uint32_t *puIntrState)
7808	{
7809	uint32_t u32IntInfo = X86_XCPT_DF \| VMX_EXIT_INTERRUPTION_INFO_VALID;
7810	u32IntInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7811	u32IntInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
7812	return hmR0VmxInjectEventVmcs(pVCpu, pMixedCtx, u32IntInfo, 0 /* cbInstr /, 0 / u32ErrCode /, 0 / GCPtrFaultAddress */,
7813	fStepping, puIntrState);
7814	}
7815
7816
7817	/**
7818	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
7819	*
7820	* @param pVCpu The cross context virtual CPU structure.
7821	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
7822	* out-of-sync. Make sure to update the required fields
7823	* before using them.
7824	*/
7825	DECLINLINE(void) hmR0VmxSetPendingXcptDB(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
7826	{
7827	NOREF(pMixedCtx);
7828	uint32_t u32IntInfo = X86_XCPT_DB \| VMX_EXIT_INTERRUPTION_INFO_VALID;
7829	u32IntInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7830	hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr /, 0 / u32ErrCode /, 0 / GCPtrFaultAddress */);
7831	}
7832
7833
7834	/**
7835	* Sets an overflow (\#OF) exception as pending-for-injection into the VM.
7836	*
7837	* @param pVCpu The cross context virtual CPU structure.
7838	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
7839	* out-of-sync. Make sure to update the required fields
7840	* before using them.
7841	* @param cbInstr The value of RIP that is to be pushed on the guest
7842	* stack.
7843	*/
7844	DECLINLINE(void) hmR0VmxSetPendingXcptOF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint32_t cbInstr)
7845	{
7846	NOREF(pMixedCtx);
7847	uint32_t u32IntInfo = X86_XCPT_OF \| VMX_EXIT_INTERRUPTION_INFO_VALID;
7848	u32IntInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7849	hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, cbInstr, 0 /* u32ErrCode /, 0 / GCPtrFaultAddress */);
7850	}
7851
7852
7853	/**
7854	* Injects a general-protection (\#GP) fault into the VM.
7855	*
7856	* @returns Strict VBox status code (i.e. informational status codes too).
7857	* @param pVCpu The cross context virtual CPU structure.
7858	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
7859	* out-of-sync. Make sure to update the required fields
7860	* before using them.
7861	* @param fErrorCodeValid Whether the error code is valid (depends on the CPU
7862	* mode, i.e. in real-mode it's not valid).
7863	* @param u32ErrorCode The error code associated with the \#GP.
7864	* @param fStepping Whether we're running in
7865	* hmR0VmxRunGuestCodeStep() and should return
7866	* VINF_EM_DBG_STEPPED if the event is injected
7867	* directly (register modified by us, not by
7868	* hardware on VM-entry).
7869	* @param puIntrState Pointer to the current guest interruptibility-state.
7870	* This interruptibility-state will be updated if
7871	* necessary. This cannot not be NULL.
7872	*/
7873	DECLINLINE(VBOXSTRICTRC) hmR0VmxInjectXcptGP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, bool fErrorCodeValid, uint32_t u32ErrorCode,
7874	bool fStepping, uint32_t *puIntrState)
7875	{
7876	uint32_t u32IntInfo = X86_XCPT_GP \| VMX_EXIT_INTERRUPTION_INFO_VALID;
7877	u32IntInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7878	if (fErrorCodeValid)
7879	u32IntInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
7880	return hmR0VmxInjectEventVmcs(pVCpu, pMixedCtx, u32IntInfo, 0 /* cbInstr /, u32ErrorCode, 0 / GCPtrFaultAddress */,
7881	fStepping, puIntrState);
7882	}
7883
7884
7885	#if 0 /* unused */
7886	/**
7887	* Sets a general-protection (\#GP) exception as pending-for-injection into the
7888	* VM.
7889	*
7890	* @param pVCpu The cross context virtual CPU structure.
7891	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
7892	* out-of-sync. Make sure to update the required fields
7893	* before using them.
7894	* @param u32ErrorCode The error code associated with the \#GP.
7895	*/
7896	DECLINLINE(void) hmR0VmxSetPendingXcptGP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint32_t u32ErrorCode)
7897	{
7898	NOREF(pMixedCtx);
7899	uint32_t u32IntInfo = X86_XCPT_GP \| VMX_EXIT_INTERRUPTION_INFO_VALID;
7900	u32IntInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7901	u32IntInfo \|= VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
7902	hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, 0 /* cbInstr /, u32ErrorCode, 0 / GCPtrFaultAddress */);
7903	}
7904	#endif /* unused */
7905
7906
7907	/**
7908	* Sets a software interrupt (INTn) as pending-for-injection into the VM.
7909	*
7910	* @param pVCpu The cross context virtual CPU structure.
7911	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
7912	* out-of-sync. Make sure to update the required fields
7913	* before using them.
7914	* @param uVector The software interrupt vector number.
7915	* @param cbInstr The value of RIP that is to be pushed on the guest
7916	* stack.
7917	*/
7918	DECLINLINE(void) hmR0VmxSetPendingIntN(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint16_t uVector, uint32_t cbInstr)
7919	{
7920	NOREF(pMixedCtx);
7921	uint32_t u32IntInfo = uVector \| VMX_EXIT_INTERRUPTION_INFO_VALID;
7922	if ( uVector == X86_XCPT_BP
7923	\|\| uVector == X86_XCPT_OF)
7924	u32IntInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7925	else
7926	u32IntInfo \|= (VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT << VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT);
7927	hmR0VmxSetPendingEvent(pVCpu, u32IntInfo, cbInstr, 0 /* u32ErrCode /, 0 / GCPtrFaultAddress */);
7928	}
7929
7930
7931	/**
7932	* Pushes a 2-byte value onto the real-mode (in virtual-8086 mode) guest's
7933	* stack.
7934	*
7935	* @returns Strict VBox status code (i.e. informational status codes too).
7936	* @retval VINF_EM_RESET if pushing a value to the stack caused a triple-fault.
7937	* @param pVM The cross context VM structure.
7938	* @param pMixedCtx Pointer to the guest-CPU context.
7939	* @param uValue The value to push to the guest stack.
7940	*/
7941	DECLINLINE(VBOXSTRICTRC) hmR0VmxRealModeGuestStackPush(PVM pVM, PCPUMCTX pMixedCtx, uint16_t uValue)
7942	{
7943	/*
7944	* The stack limit is 0xffff in real-on-virtual 8086 mode. Real-mode with weird stack limits cannot be run in
7945	* virtual 8086 mode in VT-x. See Intel spec. 26.3.1.2 "Checks on Guest Segment Registers".
7946	* See Intel Instruction reference for PUSH and Intel spec. 22.33.1 "Segment Wraparound".
7947	*/
7948	if (pMixedCtx->sp == 1)
7949	return VINF_EM_RESET;
7950	pMixedCtx->sp -= sizeof(uint16_t); /* May wrap around which is expected behaviour. */
7951	int rc = PGMPhysSimpleWriteGCPhys(pVM, pMixedCtx->ss.u64Base + pMixedCtx->sp, &uValue, sizeof(uint16_t));
7952	AssertRC(rc);
7953	return rc;
7954	}
7955
7956
7957	/**
7958	* Injects an event into the guest upon VM-entry by updating the relevant fields
7959	* in the VM-entry area in the VMCS.
7960	*
7961	* @returns Strict VBox status code (i.e. informational status codes too).
7962	* @retval VINF_SUCCESS if the event is successfully injected into the VMCS.
7963	* @retval VINF_EM_RESET if event injection resulted in a triple-fault.
7964	*
7965	* @param pVCpu The cross context virtual CPU structure.
7966	* @param pMixedCtx Pointer to the guest-CPU context. The data may
7967	* be out-of-sync. Make sure to update the required
7968	* fields before using them.
7969	* @param u64IntInfo The VM-entry interruption-information field.
7970	* @param cbInstr The VM-entry instruction length in bytes (for
7971	* software interrupts, exceptions and privileged
7972	* software exceptions).
7973	* @param u32ErrCode The VM-entry exception error code.
7974	* @param GCPtrFaultAddress The page-fault address for \#PF exceptions.
7975	* @param puIntrState Pointer to the current guest interruptibility-state.
7976	* This interruptibility-state will be updated if
7977	* necessary. This cannot not be NULL.
7978	* @param fStepping Whether we're running in
7979	* hmR0VmxRunGuestCodeStep() and should return
7980	* VINF_EM_DBG_STEPPED if the event is injected
7981	* directly (register modified by us, not by
7982	* hardware on VM-entry).
7983	*
7984	* @remarks Requires CR0!
7985	*/
7986	static VBOXSTRICTRC hmR0VmxInjectEventVmcs(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint64_t u64IntInfo, uint32_t cbInstr,
7987	uint32_t u32ErrCode, RTGCUINTREG GCPtrFaultAddress, bool fStepping,
7988	uint32_t *puIntrState)
7989	{
7990	/* Intel spec. 24.8.3 "VM-Entry Controls for Event Injection" specifies the interruption-information field to be 32-bits. */
7991	AssertMsg(u64IntInfo >> 32 == 0, ("%#RX64\n", u64IntInfo));
7992	Assert(puIntrState);
7993	uint32_t u32IntInfo = (uint32_t)u64IntInfo;
7994
7995	uint32_t const uVector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(u32IntInfo);
7996	uint32_t const uIntType = VMX_EXIT_INTERRUPTION_INFO_TYPE(u32IntInfo);
7997
7998	#ifdef VBOX_STRICT
7999	/* Validate the error-code-valid bit for hardware exceptions. */
8000	if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT)
8001	{
8002	switch (uVector)
8003	{
8004	case X86_XCPT_PF:
8005	case X86_XCPT_DF:
8006	case X86_XCPT_TS:
8007	case X86_XCPT_NP:
8008	case X86_XCPT_SS:
8009	case X86_XCPT_GP:
8010	case X86_XCPT_AC:
8011	AssertMsg(VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(u32IntInfo),
8012	("Error-code-valid bit not set for exception that has an error code uVector=%#x\n", uVector));
8013	/* fall thru */
8014	default:
8015	break;
8016	}
8017	}
8018	#endif
8019
8020	/* Cannot inject an NMI when block-by-MOV SS is in effect. */
8021	Assert( uIntType != VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI
8022	\|\| !(*puIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS));
8023
8024	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[uVector & MASK_INJECT_IRQ_STAT]);
8025
8026	/* We require CR0 to check if the guest is in real-mode. */
8027	int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
8028	AssertRCReturn(rc, rc);
8029
8030	/*
8031	* Hardware interrupts & exceptions cannot be delivered through the software interrupt redirection bitmap to the real
8032	* mode task in virtual-8086 mode. We must jump to the interrupt handler in the (real-mode) guest.
8033	* See Intel spec. 20.3 "Interrupt and Exception handling in Virtual-8086 Mode" for interrupt & exception classes.
8034	* See Intel spec. 20.1.4 "Interrupt and Exception Handling" for real-mode interrupt handling.
8035	*/
8036	if (CPUMIsGuestInRealModeEx(pMixedCtx))
8037	{
8038	PVM pVM = pVCpu->CTX_SUFF(pVM);
8039	if (!pVM->hm.s.vmx.fUnrestrictedGuest)
8040	{
8041	Assert(PDMVmmDevHeapIsEnabled(pVM));
8042	Assert(pVM->hm.s.vmx.pRealModeTSS);
8043
8044	/* We require RIP, RSP, RFLAGS, CS, IDTR. Save the required ones from the VMCS. */
8045	rc = hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
8046	rc \|= hmR0VmxSaveGuestTableRegs(pVCpu, pMixedCtx);
8047	rc \|= hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
8048	AssertRCReturn(rc, rc);
8049	Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_RIP));
8050
8051	/* Check if the interrupt handler is present in the IVT (real-mode IDT). IDT limit is (4N - 1). */
8052	size_t const cbIdtEntry = sizeof(X86IDTR16);
8053	if (uVector * cbIdtEntry + (cbIdtEntry - 1) > pMixedCtx->idtr.cbIdt)
8054	{
8055	/* If we are trying to inject a #DF with no valid IDT entry, return a triple-fault. */
8056	if (uVector == X86_XCPT_DF)
8057	return VINF_EM_RESET;
8058
8059	/* If we're injecting a #GP with no valid IDT entry, inject a double-fault. */
8060	if (uVector == X86_XCPT_GP)
8061	return hmR0VmxInjectXcptDF(pVCpu, pMixedCtx, fStepping, puIntrState);
8062
8063	/* If we're injecting an interrupt/exception with no valid IDT entry, inject a general-protection fault. */
8064	/* No error codes for exceptions in real-mode. See Intel spec. 20.1.4 "Interrupt and Exception Handling" */
8065	return hmR0VmxInjectXcptGP(pVCpu, pMixedCtx, false /* fErrCodeValid /, 0 / u32ErrCode */,
8066	fStepping, puIntrState);
8067	}
8068
8069	/* Software exceptions (#BP and #OF exceptions thrown as a result of INT3 or INTO) */
8070	uint16_t uGuestIp = pMixedCtx->ip;
8071	if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT)
8072	{
8073	Assert(uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF);
8074	/* #BP and #OF are both benign traps, we need to resume the next instruction. */
8075	uGuestIp = pMixedCtx->ip + (uint16_t)cbInstr;
8076	}
8077	else if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT)
8078	uGuestIp = pMixedCtx->ip + (uint16_t)cbInstr;
8079
8080	/* Get the code segment selector and offset from the IDT entry for the interrupt handler. */
8081	X86IDTR16 IdtEntry;
8082	RTGCPHYS GCPhysIdtEntry = (RTGCPHYS)pMixedCtx->idtr.pIdt + uVector * cbIdtEntry;
8083	rc = PGMPhysSimpleReadGCPhys(pVM, &IdtEntry, GCPhysIdtEntry, cbIdtEntry);
8084	AssertRCReturn(rc, rc);
8085
8086	/* Construct the stack frame for the interrupt/exception handler. */
8087	VBOXSTRICTRC rcStrict;
8088	rcStrict = hmR0VmxRealModeGuestStackPush(pVM, pMixedCtx, pMixedCtx->eflags.u32);
8089	if (rcStrict == VINF_SUCCESS)
8090	rcStrict = hmR0VmxRealModeGuestStackPush(pVM, pMixedCtx, pMixedCtx->cs.Sel);
8091	if (rcStrict == VINF_SUCCESS)
8092	rcStrict = hmR0VmxRealModeGuestStackPush(pVM, pMixedCtx, uGuestIp);
8093
8094	/* Clear the required eflag bits and jump to the interrupt/exception handler. */
8095	if (rcStrict == VINF_SUCCESS)
8096	{
8097	pMixedCtx->eflags.u32 &= ~(X86_EFL_IF \| X86_EFL_TF \| X86_EFL_RF \| X86_EFL_AC);
8098	pMixedCtx->rip = IdtEntry.offSel;
8099	pMixedCtx->cs.Sel = IdtEntry.uSel;
8100	pMixedCtx->cs.ValidSel = IdtEntry.uSel;
8101	pMixedCtx->cs.u64Base = IdtEntry.uSel << cbIdtEntry;
8102	if ( uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT
8103	&& uVector == X86_XCPT_PF)
8104	pMixedCtx->cr2 = GCPtrFaultAddress;
8105
8106	/* If any other guest-state bits are changed here, make sure to update
8107	hmR0VmxPreRunGuestCommitted() when thread-context hooks are used. */
8108	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS
8109	\| HM_CHANGED_GUEST_RIP
8110	\| HM_CHANGED_GUEST_RFLAGS
8111	\| HM_CHANGED_GUEST_RSP);
8112
8113	/* We're clearing interrupts, which means no block-by-STI interrupt-inhibition. */
8114	if (*puIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI)
8115	{
8116	Assert( uIntType != VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI
8117	&& uIntType != VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT);
8118	Log4(("Clearing inhibition due to STI.\n"));
8119	*puIntrState &= ~VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI;
8120	}
8121	Log4(("Injecting real-mode: u32IntInfo=%#x u32ErrCode=%#x cbInstr=%#x Eflags=%#x CS:EIP=%04x:%04x\n",
8122	u32IntInfo, u32ErrCode, cbInstr, pMixedCtx->eflags.u, pMixedCtx->cs.Sel, pMixedCtx->eip));
8123
8124	/* The event has been truly dispatched. Mark it as no longer pending so we don't attempt to 'undo'
8125	it, if we are returning to ring-3 before executing guest code. */
8126	pVCpu->hm.s.Event.fPending = false;
8127
8128	/* Make hmR0VmxPreRunGuest return if we're stepping since we've changed cs:rip. */
8129	if (fStepping)
8130	rcStrict = VINF_EM_DBG_STEPPED;
8131	}
8132	AssertMsg(rcStrict == VINF_SUCCESS \|\| rcStrict == VINF_EM_RESET \|\| (rcStrict == VINF_EM_DBG_STEPPED && fStepping),
8133	("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8134	return rcStrict;
8135	}
8136
8137	/*
8138	* For unrestricted execution enabled CPUs running real-mode guests, we must not set the deliver-error-code bit.
8139	* See Intel spec. 26.2.1.3 "VM-Entry Control Fields".
8140	*/
8141	u32IntInfo &= ~VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID;
8142	}
8143
8144	/* Validate. */
8145	Assert(VMX_EXIT_INTERRUPTION_INFO_IS_VALID(u32IntInfo)); /* Bit 31 (Valid bit) must be set by caller. */
8146	Assert(!VMX_EXIT_INTERRUPTION_INFO_NMI_UNBLOCK_IRET(u32IntInfo)); /* Bit 12 MBZ. */
8147	Assert(!(u32IntInfo & 0x7ffff000)); /* Bits 30:12 MBZ. */
8148
8149	/* Inject. */
8150	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, u32IntInfo);
8151	if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(u32IntInfo))
8152	rc \|= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE, u32ErrCode);
8153	rc \|= VMXWriteVmcs32(VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH, cbInstr);
8154
8155	if ( VMX_EXIT_INTERRUPTION_INFO_TYPE(u32IntInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT
8156	&& uVector == X86_XCPT_PF)
8157	pMixedCtx->cr2 = GCPtrFaultAddress;
8158
8159	Log4(("Injecting vcpu[%RU32] u32IntInfo=%#x u32ErrCode=%#x cbInstr=%#x pMixedCtx->uCR2=%#RX64\n", pVCpu->idCpu,
8160	u32IntInfo, u32ErrCode, cbInstr, pMixedCtx->cr2));
8161
8162	AssertRCReturn(rc, rc);
8163	return VINF_SUCCESS;
8164	}
8165
8166
8167	/**
8168	* Clears the interrupt-window exiting control in the VMCS and if necessary
8169	* clears the current event in the VMCS as well.
8170	*
8171	* @returns VBox status code.
8172	* @param pVCpu The cross context virtual CPU structure.
8173	*
8174	* @remarks Use this function only to clear events that have not yet been
8175	* delivered to the guest but are injected in the VMCS!
8176	* @remarks No-long-jump zone!!!
8177	*/
8178	static void hmR0VmxClearIntNmiWindowsVmcs(PVMCPU pVCpu)
8179	{
8180	Log4Func(("vcpu[%d]\n", pVCpu->idCpu));
8181
8182	if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT)
8183	hmR0VmxClearIntWindowExitVmcs(pVCpu);
8184
8185	if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT)
8186	hmR0VmxClearNmiWindowExitVmcs(pVCpu);
8187	}
8188
8189
8190	/**
8191	* Enters the VT-x session.
8192	*
8193	* @returns VBox status code.
8194	* @param pVM The cross context VM structure.
8195	* @param pVCpu The cross context virtual CPU structure.
8196	* @param pCpu Pointer to the CPU info struct.
8197	*/
8198	VMMR0DECL(int) VMXR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
8199	{
8200	AssertPtr(pVM);
8201	AssertPtr(pVCpu);
8202	Assert(pVM->hm.s.vmx.fSupported);
8203	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8204	NOREF(pCpu); NOREF(pVM);
8205
8206	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
8207	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
8208
8209	#ifdef VBOX_STRICT
8210	/* At least verify VMX is enabled, since we can't check if we're in VMX root mode without #GP'ing. */
8211	RTCCUINTREG uHostCR4 = ASMGetCR4();
8212	if (!(uHostCR4 & X86_CR4_VMXE))
8213	{
8214	LogRel(("VMXR0Enter: X86_CR4_VMXE bit in CR4 is not set!\n"));
8215	return VERR_VMX_X86_CR4_VMXE_CLEARED;
8216	}
8217	#endif
8218
8219	/*
8220	* Load the VCPU's VMCS as the current (and active) one.
8221	*/
8222	Assert(pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_CLEAR);
8223	int rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
8224	if (RT_FAILURE(rc))
8225	return rc;
8226
8227	pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_ACTIVE;
8228	pVCpu->hm.s.fLeaveDone = false;
8229	Log4Func(("Activated Vmcs. HostCpuId=%u\n", RTMpCpuId()));
8230
8231	return VINF_SUCCESS;
8232	}
8233
8234
8235	/**
8236	* The thread-context callback (only on platforms which support it).
8237	*
8238	* @param enmEvent The thread-context event.
8239	* @param pVCpu The cross context virtual CPU structure.
8240	* @param fGlobalInit Whether global VT-x/AMD-V init. was used.
8241	* @thread EMT(pVCpu)
8242	*/
8243	VMMR0DECL(void) VMXR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
8244	{
8245	NOREF(fGlobalInit);
8246
8247	switch (enmEvent)
8248	{
8249	case RTTHREADCTXEVENT_OUT:
8250	{
8251	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8252	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
8253	VMCPU_ASSERT_EMT(pVCpu);
8254
8255	PCPUMCTX pMixedCtx = CPUMQueryGuestCtxPtr(pVCpu);
8256
8257	/* No longjmps (logger flushes, locks) in this fragile context. */
8258	VMMRZCallRing3Disable(pVCpu);
8259	Log4Func(("Preempting: HostCpuId=%u\n", RTMpCpuId()));
8260
8261	/*
8262	* Restore host-state (FPU, debug etc.)
8263	*/
8264	if (!pVCpu->hm.s.fLeaveDone)
8265	{
8266	/* Do -not- save guest-state here as we might already be in the middle of saving it (esp. bad if we are
8267	holding the PGM lock while saving the guest state (see hmR0VmxSaveGuestControlRegs()). */
8268	hmR0VmxLeave(pVCpu, pMixedCtx, false /* fSaveGuestState */);
8269	pVCpu->hm.s.fLeaveDone = true;
8270	}
8271
8272	/* Leave HM context, takes care of local init (term). */
8273	int rc = HMR0LeaveCpu(pVCpu);
8274	AssertRC(rc); NOREF(rc);
8275
8276	/* Restore longjmp state. */
8277	VMMRZCallRing3Enable(pVCpu);
8278	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
8279	break;
8280	}
8281
8282	case RTTHREADCTXEVENT_IN:
8283	{
8284	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8285	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
8286	VMCPU_ASSERT_EMT(pVCpu);
8287
8288	/* No longjmps here, as we don't want to trigger preemption (& its hook) while resuming. */
8289	VMMRZCallRing3Disable(pVCpu);
8290	Log4Func(("Resumed: HostCpuId=%u\n", RTMpCpuId()));
8291
8292	/* Initialize the bare minimum state required for HM. This takes care of
8293	initializing VT-x if necessary (onlined CPUs, local init etc.) */
8294	int rc = HMR0EnterCpu(pVCpu);
8295	AssertRC(rc);
8296	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
8297
8298	/* Load the active VMCS as the current one. */
8299	if (pVCpu->hm.s.vmx.uVmcsState & HMVMX_VMCS_STATE_CLEAR)
8300	{
8301	rc = VMXActivateVmcs(pVCpu->hm.s.vmx.HCPhysVmcs);
8302	AssertRC(rc); NOREF(rc);
8303	pVCpu->hm.s.vmx.uVmcsState = HMVMX_VMCS_STATE_ACTIVE;
8304	Log4Func(("Resumed: Activated Vmcs. HostCpuId=%u\n", RTMpCpuId()));
8305	}
8306	pVCpu->hm.s.fLeaveDone = false;
8307
8308	/* Restore longjmp state. */
8309	VMMRZCallRing3Enable(pVCpu);
8310	break;
8311	}
8312
8313	default:
8314	break;
8315	}
8316	}
8317
8318
8319	/**
8320	* Saves the host state in the VMCS host-state.
8321	* Sets up the VM-exit MSR-load area.
8322	*
8323	* The CPU state will be loaded from these fields on every successful VM-exit.
8324	*
8325	* @returns VBox status code.
8326	* @param pVM The cross context VM structure.
8327	* @param pVCpu The cross context virtual CPU structure.
8328	*
8329	* @remarks No-long-jump zone!!!
8330	*/
8331	static int hmR0VmxSaveHostState(PVM pVM, PVMCPU pVCpu)
8332	{
8333	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8334
8335	int rc = VINF_SUCCESS;
8336	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_CONTEXT))
8337	{
8338	rc = hmR0VmxSaveHostControlRegs(pVM, pVCpu);
8339	AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveHostControlRegisters failed! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8340
8341	rc = hmR0VmxSaveHostSegmentRegs(pVM, pVCpu);
8342	AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveHostSegmentRegisters failed! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8343
8344	rc = hmR0VmxSaveHostMsrs(pVM, pVCpu);
8345	AssertLogRelMsgRCReturn(rc, ("hmR0VmxSaveHostMsrs failed! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8346
8347	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
8348	}
8349	return rc;
8350	}
8351
8352
8353	/**
8354	* Saves the host state in the VMCS host-state.
8355	*
8356	* @returns VBox status code.
8357	* @param pVM The cross context VM structure.
8358	* @param pVCpu The cross context virtual CPU structure.
8359	*
8360	* @remarks No-long-jump zone!!!
8361	*/
8362	VMMR0DECL(int) VMXR0SaveHostState(PVM pVM, PVMCPU pVCpu)
8363	{
8364	AssertPtr(pVM);
8365	AssertPtr(pVCpu);
8366
8367	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
8368
8369	/* Save the host state here while entering HM context. When thread-context hooks are used, we might get preempted
8370	and have to resave the host state but most of the time we won't be, so do it here before we disable interrupts. */
8371	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8372	return hmR0VmxSaveHostState(pVM, pVCpu);
8373	}
8374
8375
8376	/**
8377	* Loads the guest state into the VMCS guest-state area.
8378	*
8379	* The will typically be done before VM-entry when the guest-CPU state and the
8380	* VMCS state may potentially be out of sync.
8381	*
8382	* Sets up the VM-entry MSR-load and VM-exit MSR-store areas. Sets up the
8383	* VM-entry controls.
8384	* Sets up the appropriate VMX non-root function to execute guest code based on
8385	* the guest CPU mode.
8386	*
8387	* @returns VBox strict status code.
8388	* @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
8389	* without unrestricted guest access and the VMMDev is not presently
8390	* mapped (e.g. EFI32).
8391	*
8392	* @param pVM The cross context VM structure.
8393	* @param pVCpu The cross context virtual CPU structure.
8394	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
8395	* out-of-sync. Make sure to update the required fields
8396	* before using them.
8397	*
8398	* @remarks No-long-jump zone!!!
8399	*/
8400	static VBOXSTRICTRC hmR0VmxLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx)
8401	{
8402	AssertPtr(pVM);
8403	AssertPtr(pVCpu);
8404	AssertPtr(pMixedCtx);
8405	HMVMX_ASSERT_PREEMPT_SAFE();
8406
8407	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
8408
8409	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
8410
8411	/* Determine real-on-v86 mode. */
8412	pVCpu->hm.s.vmx.RealMode.fRealOnV86Active = false;
8413	if ( !pVM->hm.s.vmx.fUnrestrictedGuest
8414	&& CPUMIsGuestInRealModeEx(pMixedCtx))
8415	{
8416	pVCpu->hm.s.vmx.RealMode.fRealOnV86Active = true;
8417	}
8418
8419	/*
8420	* Load the guest-state into the VMCS.
8421	* Any ordering dependency among the sub-functions below must be explicitly stated using comments.
8422	* Ideally, assert that the cross-dependent bits are up-to-date at the point of using it.
8423	*/
8424	int rc = hmR0VmxSetupVMRunHandler(pVCpu, pMixedCtx);
8425	AssertLogRelMsgRCReturn(rc, ("hmR0VmxSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8426
8427	/* This needs to be done after hmR0VmxSetupVMRunHandler() as changing pfnStartVM may require VM-entry control updates. */
8428	rc = hmR0VmxLoadGuestEntryCtls(pVCpu, pMixedCtx);
8429	AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestEntryCtls! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8430
8431	/* This needs to be done after hmR0VmxSetupVMRunHandler() as changing pfnStartVM may require VM-exit control updates. */
8432	rc = hmR0VmxLoadGuestExitCtls(pVCpu, pMixedCtx);
8433	AssertLogRelMsgRCReturn(rc, ("hmR0VmxSetupExitCtls failed! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8434
8435	rc = hmR0VmxLoadGuestActivityState(pVCpu, pMixedCtx);
8436	AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestActivityState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8437
8438	VBOXSTRICTRC rcStrict = hmR0VmxLoadGuestCR3AndCR4(pVCpu, pMixedCtx);
8439	if (rcStrict == VINF_SUCCESS)
8440	{ /* likely */ }
8441	else
8442	{
8443	Assert(rcStrict == VINF_EM_RESCHEDULE_REM \|\| RT_FAILURE_NP(rcStrict));
8444	return rcStrict;
8445	}
8446
8447	/* Assumes pMixedCtx->cr0 is up-to-date (strict builds require CR0 for segment register validation checks). */
8448	rc = hmR0VmxLoadGuestSegmentRegs(pVCpu, pMixedCtx);
8449	AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestSegmentRegs: rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8450
8451	/* This needs to be done after hmR0VmxLoadGuestEntryCtls() and hmR0VmxLoadGuestExitCtls() as it may alter controls if we
8452	determine we don't have to swap EFER after all. */
8453	rc = hmR0VmxLoadGuestMsrs(pVCpu, pMixedCtx);
8454	AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestMsrs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8455
8456	rc = hmR0VmxLoadGuestApicState(pVCpu, pMixedCtx);
8457	AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8458
8459	rc = hmR0VmxLoadGuestXcptIntercepts(pVCpu, pMixedCtx);
8460	AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestXcptIntercepts! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8461
8462	/*
8463	* Loading Rflags here is fine, even though Rflags.TF might depend on guest debug state (which is not loaded here).
8464	* It is re-evaluated and updated if necessary in hmR0VmxLoadSharedState().
8465	*/
8466	rc = hmR0VmxLoadGuestRipRspRflags(pVCpu, pMixedCtx);
8467	AssertLogRelMsgRCReturn(rc, ("hmR0VmxLoadGuestRipRspRflags! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
8468
8469	/* Clear any unused and reserved bits. */
8470	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
8471
8472	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
8473	return rc;
8474	}
8475
8476
8477	/**
8478	* Loads the state shared between the host and guest into the VMCS.
8479	*
8480	* @param pVM The cross context VM structure.
8481	* @param pVCpu The cross context virtual CPU structure.
8482	* @param pCtx Pointer to the guest-CPU context.
8483	*
8484	* @remarks No-long-jump zone!!!
8485	*/
8486	static void hmR0VmxLoadSharedState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
8487	{
8488	NOREF(pVM);
8489
8490	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8491	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8492
8493	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
8494	{
8495	int rc = hmR0VmxLoadSharedCR0(pVCpu, pCtx);
8496	AssertRC(rc);
8497	}
8498
8499	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
8500	{
8501	int rc = hmR0VmxLoadSharedDebugState(pVCpu, pCtx);
8502	AssertRC(rc);
8503
8504	/* Loading shared debug bits might have changed eflags.TF bit for debugging purposes. */
8505	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RFLAGS))
8506	{
8507	rc = hmR0VmxLoadGuestRflags(pVCpu, pCtx);
8508	AssertRC(rc);
8509	}
8510	}
8511
8512	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS))
8513	{
8514	hmR0VmxLazyLoadGuestMsrs(pVCpu, pCtx);
8515	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
8516	}
8517
8518	/* Loading CR0, debug state might have changed intercepts, update VMCS. */
8519	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
8520	{
8521	Assert(pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT_32(X86_XCPT_AC));
8522	Assert(pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT_32(X86_XCPT_DB));
8523	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap);
8524	AssertRC(rc);
8525	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
8526	}
8527
8528	AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
8529	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
8530	}
8531
8532
8533	/**
8534	* Worker for loading the guest-state bits in the inner VT-x execution loop.
8535	*
8536	* @returns Strict VBox status code (i.e. informational status codes too).
8537	* @retval VINF_EM_RESCHEDULE_REM if we try to emulate non-paged guest code
8538	* without unrestricted guest access and the VMMDev is not presently
8539	* mapped (e.g. EFI32).
8540	*
8541	* @param pVM The cross context VM structure.
8542	* @param pVCpu The cross context virtual CPU structure.
8543	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
8544	* out-of-sync. Make sure to update the required fields
8545	* before using them.
8546	*
8547	* @remarks No-long-jump zone!!!
8548	*/
8549	static VBOXSTRICTRC hmR0VmxLoadGuestStateOptimal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx)
8550	{
8551	HMVMX_ASSERT_PREEMPT_SAFE();
8552	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8553	Assert(VMMR0IsLogFlushDisabled(pVCpu));
8554
8555	Log5(("LoadFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
8556	#ifdef HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE
8557	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
8558	#endif
8559
8560	/*
8561	* RIP is what changes the most often and hence if it's the only bit needing to be
8562	* updated, we shall handle it early for performance reasons.
8563	*/
8564	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
8565	if (HMCPU_CF_IS_SET_ONLY(pVCpu, HM_CHANGED_GUEST_RIP))
8566	{
8567	rcStrict = hmR0VmxLoadGuestRip(pVCpu, pMixedCtx);
8568	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8569	{ /* likely */}
8570	else
8571	{
8572	AssertMsgFailedReturn(("hmR0VmxLoadGuestStateOptimal: hmR0VmxLoadGuestRip failed! rc=%Rrc\n",
8573	VBOXSTRICTRC_VAL(rcStrict)), rcStrict);
8574	}
8575	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadMinimal);
8576	}
8577	else if (HMCPU_CF_VALUE(pVCpu))
8578	{
8579	rcStrict = hmR0VmxLoadGuestState(pVM, pVCpu, pMixedCtx);
8580	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8581	{ /* likely */}
8582	else
8583	{
8584	AssertMsg(rcStrict == VINF_EM_RESCHEDULE_REM,
8585	("hmR0VmxLoadGuestStateOptimal: hmR0VmxLoadGuestState failed! rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8586	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8587	return rcStrict;
8588	}
8589	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
8590	}
8591
8592	/* All the guest state bits should be loaded except maybe the host context and/or the shared host/guest bits. */
8593	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
8594	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
8595	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
8596	return rcStrict;
8597	}
8598
8599
8600	/**
8601	* Does the preparations before executing guest code in VT-x.
8602	*
8603	* This may cause longjmps to ring-3 and may even result in rescheduling to the
8604	* recompiler/IEM. We must be cautious what we do here regarding committing
8605	* guest-state information into the VMCS assuming we assuredly execute the
8606	* guest in VT-x mode.
8607	*
8608	* If we fall back to the recompiler/IEM after updating the VMCS and clearing
8609	* the common-state (TRPM/forceflags), we must undo those changes so that the
8610	* recompiler/IEM can (and should) use them when it resumes guest execution.
8611	* Otherwise such operations must be done when we can no longer exit to ring-3.
8612	*
8613	* @returns Strict VBox status code (i.e. informational status codes too).
8614	* @retval VINF_SUCCESS if we can proceed with running the guest, interrupts
8615	* have been disabled.
8616	* @retval VINF_EM_RESET if a triple-fault occurs while injecting a
8617	* double-fault into the guest.
8618	* @retval VINF_EM_DBG_STEPPED if @a fStepping is true and an event was
8619	* dispatched directly.
8620	* @retval VINF_* scheduling changes, we have to go back to ring-3.
8621	*
8622	* @param pVM The cross context VM structure.
8623	* @param pVCpu The cross context virtual CPU structure.
8624	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
8625	* out-of-sync. Make sure to update the required fields
8626	* before using them.
8627	* @param pVmxTransient Pointer to the VMX transient structure.
8628	* @param fStepping Set if called from hmR0VmxRunGuestCodeStep(). Makes
8629	* us ignore some of the reasons for returning to
8630	* ring-3, and return VINF_EM_DBG_STEPPED if event
8631	* dispatching took place.
8632	*/
8633	static VBOXSTRICTRC hmR0VmxPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, bool fStepping)
8634	{
8635	Assert(VMMRZCallRing3IsEnabled(pVCpu));
8636
8637	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0
8638	PGMRZDynMapFlushAutoSet(pVCpu);
8639	#endif
8640
8641	/* Check force flag actions that might require us to go back to ring-3. */
8642	VBOXSTRICTRC rcStrict = hmR0VmxCheckForceFlags(pVM, pVCpu, pMixedCtx, fStepping);
8643	if (rcStrict == VINF_SUCCESS)
8644	{ /* FFs doesn't get set all the time. */ }
8645	else
8646	return rcStrict;
8647
8648	#ifndef IEM_VERIFICATION_MODE_FULL
8649	/*
8650	* Setup the virtualized-APIC accesses.
8651	*
8652	* Note! This can cause a longjumps to R3 due to the acquisition of the PGM lock
8653	* in both PGMHandlerPhysicalReset() and IOMMMIOMapMMIOHCPage(), see @bugref{8721}.
8654	*
8655	* This is the reason we do it here and not in hmR0VmxLoadGuestState().
8656	*/
8657	if ( !pVCpu->hm.s.vmx.u64MsrApicBase
8658	&& (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
8659	&& PDMHasApic(pVM))
8660	{
8661	uint64_t const u64MsrApicBase = APICGetBaseMsrNoCheck(pVCpu);
8662	Assert(u64MsrApicBase);
8663	Assert(pVM->hm.s.vmx.HCPhysApicAccess);
8664
8665	RTGCPHYS const GCPhysApicBase = u64MsrApicBase & PAGE_BASE_GC_MASK;
8666
8667	/* Unalias any existing mapping. */
8668	int rc = PGMHandlerPhysicalReset(pVM, GCPhysApicBase);
8669	AssertRCReturn(rc, rc);
8670
8671	/* Map the HC APIC-access page in place of the MMIO page, also updates the shadow page tables if necessary. */
8672	LogRel(("hmR0VmxPreRunGuest: VCPU%u: Mapped HC APIC-access page at %#RGp\n", pVCpu->idCpu, GCPhysApicBase));
8673	rc = IOMMMIOMapMMIOHCPage(pVM, pVCpu, GCPhysApicBase, pVM->hm.s.vmx.HCPhysApicAccess, X86_PTE_RW \| X86_PTE_P);
8674	AssertRCReturn(rc, rc);
8675
8676	/* Update the per-VCPU cache of the APIC base MSR. */
8677	pVCpu->hm.s.vmx.u64MsrApicBase = u64MsrApicBase;
8678	}
8679	#endif /* !IEM_VERIFICATION_MODE_FULL */
8680
8681	if (TRPMHasTrap(pVCpu))
8682	hmR0VmxTrpmTrapToPendingEvent(pVCpu);
8683	uint32_t uIntrState = hmR0VmxEvaluatePendingEvent(pVCpu, pMixedCtx);
8684
8685	/*
8686	* Event injection may take locks (currently the PGM lock for real-on-v86 case) and thus needs to be done with
8687	* longjmps or interrupts + preemption enabled. Event injection might also result in triple-faulting the VM.
8688	*/
8689	rcStrict = hmR0VmxInjectPendingEvent(pVCpu, pMixedCtx, uIntrState, fStepping);
8690	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8691	{ /* likely */ }
8692	else
8693	{
8694	AssertMsg(rcStrict == VINF_EM_RESET \|\| (rcStrict == VINF_EM_DBG_STEPPED && fStepping),
8695	("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
8696	return rcStrict;
8697	}
8698
8699	/*
8700	* No longjmps to ring-3 from this point on!!!
8701	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
8702	* This also disables flushing of the R0-logger instance (if any).
8703	*/
8704	VMMRZCallRing3Disable(pVCpu);
8705
8706	/*
8707	* Load the guest state bits.
8708	*
8709	* We cannot perform longjmps while loading the guest state because we do not preserve the
8710	* host/guest state (although the VMCS will be preserved) across longjmps which can cause
8711	* CPU migration.
8712	*
8713	* If we are injecting events to a real-on-v86 mode guest, we will have to update
8714	* RIP and some segment registers, i.e. hmR0VmxInjectPendingEvent()->hmR0VmxInjectEventVmcs().
8715	* Hence, loading of the guest state needs to be done -after- injection of events.
8716	*/
8717	rcStrict = hmR0VmxLoadGuestStateOptimal(pVM, pVCpu, pMixedCtx);
8718	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
8719	{ /* likely */ }
8720	else
8721	{
8722	VMMRZCallRing3Enable(pVCpu);
8723	return rcStrict;
8724	}
8725
8726	/*
8727	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
8728	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
8729	*
8730	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
8731	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
8732	*
8733	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
8734	* executing guest code.
8735	*/
8736	pVmxTransient->fEFlags = ASMIntDisableFlags();
8737
8738	if ( ( !VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
8739	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
8740	\|\| ( fStepping /* Optimized for the non-stepping case, so a bit of unnecessary work when stepping. */
8741	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK & ~(VMCPU_FF_TIMER \| VMCPU_FF_PDM_CRITSECT))) )
8742	{
8743	if (!RTThreadPreemptIsPending(NIL_RTTHREAD))
8744	{
8745	pVCpu->hm.s.Event.fPending = false;
8746
8747	/*
8748	* We've injected any pending events. This is really the point of no return (to ring-3).
8749	*
8750	* Note! The caller expects to continue with interrupts & longjmps disabled on successful
8751	* returns from this function, so don't enable them here.
8752	*/
8753	return VINF_SUCCESS;
8754	}
8755
8756	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
8757	rcStrict = VINF_EM_RAW_INTERRUPT;
8758	}
8759	else
8760	{
8761	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
8762	rcStrict = VINF_EM_RAW_TO_R3;
8763	}
8764
8765	ASMSetFlags(pVmxTransient->fEFlags);
8766	VMMRZCallRing3Enable(pVCpu);
8767
8768	return rcStrict;
8769	}
8770
8771
8772	/**
8773	* Prepares to run guest code in VT-x and we've committed to doing so. This
8774	* means there is no backing out to ring-3 or anywhere else at this
8775	* point.
8776	*
8777	* @param pVM The cross context VM structure.
8778	* @param pVCpu The cross context virtual CPU structure.
8779	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
8780	* out-of-sync. Make sure to update the required fields
8781	* before using them.
8782	* @param pVmxTransient Pointer to the VMX transient structure.
8783	*
8784	* @remarks Called with preemption disabled.
8785	* @remarks No-long-jump zone!!!
8786	*/
8787	static void hmR0VmxPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
8788	{
8789	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8790	Assert(VMMR0IsLogFlushDisabled(pVCpu));
8791	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
8792
8793	/*
8794	* Indicate start of guest execution and where poking EMT out of guest-context is recognized.
8795	*/
8796	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
8797	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC);
8798
8799	#ifdef HMVMX_ALWAYS_SWAP_FPU_STATE
8800	if (!CPUMIsGuestFPUStateActive(pVCpu))
8801	if (CPUMR0LoadGuestFPU(pVM, pVCpu) == VINF_CPUM_HOST_CR0_MODIFIED)
8802	HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT);
8803	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
8804	#endif
8805
8806	if ( pVCpu->hm.s.fPreloadGuestFpu
8807	&& !CPUMIsGuestFPUStateActive(pVCpu))
8808	{
8809	if (CPUMR0LoadGuestFPU(pVM, pVCpu) == VINF_CPUM_HOST_CR0_MODIFIED)
8810	HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT);
8811	Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_CR0));
8812	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
8813	}
8814
8815	/*
8816	* Lazy-update of the host MSRs values in the auto-load/store MSR area.
8817	*/
8818	if ( !pVCpu->hm.s.vmx.fUpdatedHostMsrs
8819	&& pVCpu->hm.s.vmx.cMsrs > 0)
8820	{
8821	hmR0VmxUpdateAutoLoadStoreHostMsrs(pVCpu);
8822	}
8823
8824	/*
8825	* Load the host state bits as we may've been preempted (only happens when
8826	* thread-context hooks are used or when hmR0VmxSetupVMRunHandler() changes pfnStartVM).
8827	* Note that the 64-on-32 switcher saves the (64-bit) host state into the VMCS and
8828	* if we change the switcher back to 32-bit, we must save the 32-bit host state here.
8829	* See @bugref{8432}.
8830	*/
8831	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_CONTEXT))
8832	{
8833	int rc = hmR0VmxSaveHostState(pVM, pVCpu);
8834	AssertRC(rc);
8835	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreemptSaveHostState);
8836	}
8837	Assert(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_CONTEXT));
8838
8839	/*
8840	* Load the state shared between host and guest (FPU, debug, lazy MSRs).
8841	*/
8842	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
8843	hmR0VmxLoadSharedState(pVM, pVCpu, pMixedCtx);
8844	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
8845
8846	/* Store status of the shared guest-host state at the time of VM-entry. */
8847	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
8848	if (CPUMIsGuestInLongModeEx(pMixedCtx))
8849	{
8850	pVmxTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
8851	pVmxTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
8852	}
8853	else
8854	#endif
8855	{
8856	pVmxTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
8857	pVmxTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
8858	}
8859	pVmxTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
8860
8861	/*
8862	* Cache the TPR-shadow for checking on every VM-exit if it might have changed.
8863	*/
8864	if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
8865	pVmxTransient->u8GuestTpr = pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR];
8866
8867	PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
8868	RTCPUID idCurrentCpu = pCpu->idCpu;
8869	if ( pVmxTransient->fUpdateTscOffsettingAndPreemptTimer
8870	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
8871	{
8872	hmR0VmxUpdateTscOffsettingAndPreemptTimer(pVM, pVCpu);
8873	pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = false;
8874	}
8875
8876	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
8877	hmR0VmxFlushTaggedTlb(pVCpu, pCpu); /* Invalidate the appropriate guest entries from the TLB. */
8878	Assert(idCurrentCpu == pVCpu->hm.s.idLastCpu);
8879	pVCpu->hm.s.vmx.LastError.idCurrentCpu = idCurrentCpu; /* Update the error reporting info. with the current host CPU. */
8880
8881	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
8882
8883	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
8884	to start executing. */
8885
8886	/*
8887	* Load the TSC_AUX MSR when we are not intercepting RDTSCP.
8888	*/
8889	if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
8890	{
8891	if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT))
8892	{
8893	bool fMsrUpdated;
8894	int rc2 = hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx);
8895	AssertRC(rc2);
8896	Assert(HMVMXCPU_GST_IS_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_AUTO_LOAD_STORE_MSRS));
8897
8898	rc2 = hmR0VmxAddAutoLoadStoreMsr(pVCpu, MSR_K8_TSC_AUX, CPUMR0GetGuestTscAux(pVCpu), true /* fUpdateHostMsr */,
8899	&fMsrUpdated);
8900	AssertRC(rc2);
8901	Assert(fMsrUpdated \|\| pVCpu->hm.s.vmx.fUpdatedHostMsrs);
8902
8903	/* Finally, mark that all host MSR values are updated so we don't redo it without leaving VT-x. See @bugref{6956}. */
8904	pVCpu->hm.s.vmx.fUpdatedHostMsrs = true;
8905	}
8906	else
8907	{
8908	hmR0VmxRemoveAutoLoadStoreMsr(pVCpu, MSR_K8_TSC_AUX);
8909	Assert(!pVCpu->hm.s.vmx.cMsrs \|\| pVCpu->hm.s.vmx.fUpdatedHostMsrs);
8910	}
8911	}
8912
8913	#ifdef VBOX_STRICT
8914	hmR0VmxCheckAutoLoadStoreMsrs(pVCpu);
8915	hmR0VmxCheckHostEferMsr(pVCpu);
8916	AssertRC(hmR0VmxCheckVmcsCtls(pVCpu));
8917	#endif
8918	#ifdef HMVMX_ALWAYS_CHECK_GUEST_STATE
8919	uint32_t uInvalidReason = hmR0VmxCheckGuestState(pVM, pVCpu, pMixedCtx);
8920	if (uInvalidReason != VMX_IGS_REASON_NOT_FOUND)
8921	Log4(("hmR0VmxCheckGuestState returned %#x\n", uInvalidReason));
8922	#endif
8923	}
8924
8925
8926	/**
8927	* Performs some essential restoration of state after running guest code in
8928	* VT-x.
8929	*
8930	* @param pVM The cross context VM structure.
8931	* @param pVCpu The cross context virtual CPU structure.
8932	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
8933	* out-of-sync. Make sure to update the required fields
8934	* before using them.
8935	* @param pVmxTransient Pointer to the VMX transient structure.
8936	* @param rcVMRun Return code of VMLAUNCH/VMRESUME.
8937	*
8938	* @remarks Called with interrupts disabled, and returns with interrupts enabled!
8939	*
8940	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
8941	* unconditionally when it is safe to do so.
8942	*/
8943	static void hmR0VmxPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, int rcVMRun)
8944	{
8945	NOREF(pVM);
8946
8947	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
8948
8949	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
8950	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
8951	HMVMXCPU_GST_RESET_TO(pVCpu, 0); /* Exits/longjmps to ring-3 requires saving the guest state. */
8952	pVmxTransient->fVmcsFieldsRead = 0; /* Transient fields need to be read from the VMCS. */
8953	pVmxTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
8954	pVmxTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
8955
8956	if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT))
8957	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVCpu->hm.s.vmx.u64TSCOffset);
8958
8959	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
8960	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
8961	Assert(!ASMIntAreEnabled());
8962	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
8963
8964	#ifdef HMVMX_ALWAYS_SWAP_FPU_STATE
8965	if (CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVM, pVCpu))
8966	{
8967	hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
8968	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
8969	}
8970	#endif
8971
8972	#if HC_ARCH_BITS == 64
8973	pVCpu->hm.s.vmx.fRestoreHostFlags \|= VMX_RESTORE_HOST_REQUIRED; /* Host state messed up by VT-x, we must restore. */
8974	#endif
8975	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
8976	/* The 64-on-32 switcher maintains uVmcsState on its own and we need to leave it alone here. */
8977	if (pVCpu->hm.s.vmx.pfnStartVM != VMXR0SwitcherStartVM64)
8978	pVCpu->hm.s.vmx.uVmcsState \|= HMVMX_VMCS_STATE_LAUNCHED; /* Use VMRESUME instead of VMLAUNCH in the next run. */
8979	#else
8980	pVCpu->hm.s.vmx.uVmcsState \|= HMVMX_VMCS_STATE_LAUNCHED; /* Use VMRESUME instead of VMLAUNCH in the next run. */
8981	#endif
8982	#ifdef VBOX_STRICT
8983	hmR0VmxCheckHostEferMsr(pVCpu); /* Verify that VMRUN/VMLAUNCH didn't modify host EFER. */
8984	#endif
8985	ASMSetFlags(pVmxTransient->fEFlags); /* Enable interrupts. */
8986	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
8987
8988	/* Save the basic VM-exit reason. Refer Intel spec. 24.9.1 "Basic VM-exit Information". */
8989	uint32_t uExitReason;
8990	int rc = VMXReadVmcs32(VMX_VMCS32_RO_EXIT_REASON, &uExitReason);
8991	rc \|= hmR0VmxReadEntryIntInfoVmcs(pVmxTransient);
8992	AssertRC(rc);
8993	pVmxTransient->uExitReason = (uint16_t)VMX_EXIT_REASON_BASIC(uExitReason);
8994	pVmxTransient->fVMEntryFailed = VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(pVmxTransient->uEntryIntInfo);
8995
8996	/* If the VMLAUNCH/VMRESUME failed, we can bail out early. This does -not- cover VMX_EXIT_ERR_. /
8997	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
8998	{
8999	Log4(("VM-entry failure: pVCpu=%p idCpu=%RU32 rcVMRun=%Rrc fVMEntryFailed=%RTbool\n", pVCpu, pVCpu->idCpu, rcVMRun,
9000	pVmxTransient->fVMEntryFailed));
9001	return;
9002	}
9003
9004	/*
9005	* Update the VM-exit history array here even if the VM-entry failed due to:
9006	* - Invalid guest state.
9007	* - MSR loading.
9008	* - Machine-check event.
9009	*
9010	* In any of the above cases we will still have a "valid" VM-exit reason
9011	* despite @a fVMEntryFailed being false.
9012	*
9013	* See Intel spec. 26.7 "VM-Entry failures during or after loading guest state".
9014	*/
9015	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmxTransient->uExitReason);
9016
9017	if (RT_LIKELY(!pVmxTransient->fVMEntryFailed))
9018	{
9019	/** @todo We can optimize this by only syncing with our force-flags when
9020	* really needed and keeping the VMCS state as it is for most
9021	* VM-exits. */
9022	/* Update the guest interruptibility-state from the VMCS. */
9023	hmR0VmxSaveGuestIntrState(pVCpu, pMixedCtx);
9024
9025	#if defined(HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE) \|\| defined(HMVMX_ALWAYS_SAVE_FULL_GUEST_STATE)
9026	rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
9027	AssertRC(rc);
9028	#elif defined(HMVMX_ALWAYS_SAVE_GUEST_RFLAGS)
9029	rc = hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
9030	AssertRC(rc);
9031	#endif
9032
9033	/*
9034	* Sync the TPR shadow with our APIC state.
9035	*/
9036	if ( (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
9037	&& pVmxTransient->u8GuestTpr != pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR])
9038	{
9039	rc = APICSetTpr(pVCpu, pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR]);
9040	AssertRC(rc);
9041	HMCPU_CF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
9042	}
9043	}
9044	}
9045
9046
9047	/**
9048	* Runs the guest code using VT-x the normal way.
9049	*
9050	* @returns VBox status code.
9051	* @param pVM The cross context VM structure.
9052	* @param pVCpu The cross context virtual CPU structure.
9053	* @param pCtx Pointer to the guest-CPU context.
9054	*
9055	* @note Mostly the same as hmR0VmxRunGuestCodeStep().
9056	*/
9057	static VBOXSTRICTRC hmR0VmxRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
9058	{
9059	VMXTRANSIENT VmxTransient;
9060	VmxTransient.fUpdateTscOffsettingAndPreemptTimer = true;
9061	VBOXSTRICTRC rcStrict = VERR_INTERNAL_ERROR_5;
9062	uint32_t cLoops = 0;
9063
9064	for (;; cLoops++)
9065	{
9066	Assert(!HMR0SuspendPending());
9067	HMVMX_ASSERT_CPU_SAFE();
9068
9069	/* Preparatory work for running guest code, this may force us to return
9070	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
9071	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
9072	rcStrict = hmR0VmxPreRunGuest(pVM, pVCpu, pCtx, &VmxTransient, false /* fStepping */);
9073	if (rcStrict != VINF_SUCCESS)
9074	break;
9075
9076	hmR0VmxPreRunGuestCommitted(pVM, pVCpu, pCtx, &VmxTransient);
9077	int rcRun = hmR0VmxRunGuest(pVM, pVCpu, pCtx);
9078	/* The guest-CPU context is now outdated, 'pCtx' is to be treated as 'pMixedCtx' from this point on!!! */
9079
9080	/* Restore any residual host-state and save any bits shared between host
9081	and guest into the guest-CPU state. Re-enables interrupts! */
9082	hmR0VmxPostRunGuest(pVM, pVCpu, pCtx, &VmxTransient, rcRun);
9083
9084	/* Check for errors with running the VM (VMLAUNCH/VMRESUME). */
9085	if (RT_SUCCESS(rcRun))
9086	{ /* very likely */ }
9087	else
9088	{
9089	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
9090	hmR0VmxReportWorldSwitchError(pVM, pVCpu, rcRun, pCtx, &VmxTransient);
9091	return rcRun;
9092	}
9093
9094	/* Profile the VM-exit. */
9095	AssertMsg(VmxTransient.uExitReason <= VMX_EXIT_MAX, ("%#x\n", VmxTransient.uExitReason));
9096	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll);
9097	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);
9098	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
9099	HMVMX_START_EXIT_DISPATCH_PROF();
9100
9101	VBOXVMM_R0_HMVMX_VMEXIT_NOCTX(pVCpu, pCtx, VmxTransient.uExitReason);
9102
9103	/* Handle the VM-exit. */
9104	#ifdef HMVMX_USE_FUNCTION_TABLE
9105	rcStrict = g_apfnVMExitHandlers[VmxTransient.uExitReason](pVCpu, pCtx, &VmxTransient);
9106	#else
9107	rcStrict = hmR0VmxHandleExit(pVCpu, pCtx, &VmxTransient, VmxTransient.uExitReason);
9108	#endif
9109	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
9110	if (rcStrict == VINF_SUCCESS)
9111	{
9112	if (cLoops <= pVM->hm.s.cMaxResumeLoops)
9113	continue; /* likely */
9114	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
9115	rcStrict = VINF_EM_RAW_INTERRUPT;
9116	}
9117	break;
9118	}
9119
9120	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
9121	return rcStrict;
9122	}
9123
9124
9125
9126	/** @name Execution loop for single stepping, DBGF events and expensive Dtrace
9127	* probes.
9128	*
9129	* The following few functions and associated structure contains the bloat
9130	* necessary for providing detailed debug events and dtrace probes as well as
9131	* reliable host side single stepping. This works on the principle of
9132	* "subclassing" the normal execution loop and workers. We replace the loop
9133	* method completely and override selected helpers to add necessary adjustments
9134	* to their core operation.
9135	*
9136	* The goal is to keep the "parent" code lean and mean, so as not to sacrifice
9137	* any performance for debug and analysis features.
9138	*
9139	* @{
9140	*/
9141
9142	/**
9143	* Transient per-VCPU debug state of VMCS and related info. we save/restore in
9144	* the debug run loop.
9145	*/
9146	typedef struct VMXRUNDBGSTATE
9147	{
9148	/** The RIP we started executing at. This is for detecting that we stepped. */
9149	uint64_t uRipStart;
9150	/** The CS we started executing with. */
9151	uint16_t uCsStart;
9152
9153	/** Whether we've actually modified the 1st execution control field. */
9154	bool fModifiedProcCtls : 1;
9155	/** Whether we've actually modified the 2nd execution control field. */
9156	bool fModifiedProcCtls2 : 1;
9157	/** Whether we've actually modified the exception bitmap. */
9158	bool fModifiedXcptBitmap : 1;
9159
9160	/** We desire the modified the CR0 mask to be cleared. */
9161	bool fClearCr0Mask : 1;
9162	/** We desire the modified the CR4 mask to be cleared. */
9163	bool fClearCr4Mask : 1;
9164	/** Stuff we need in VMX_VMCS32_CTRL_PROC_EXEC. */
9165	uint32_t fCpe1Extra;
9166	/** Stuff we do not want in VMX_VMCS32_CTRL_PROC_EXEC. */
9167	uint32_t fCpe1Unwanted;
9168	/** Stuff we need in VMX_VMCS32_CTRL_PROC_EXEC2. */
9169	uint32_t fCpe2Extra;
9170	/** Extra stuff we need in VMX_VMCS32_CTRL_EXCEPTION_BITMAP. */
9171	uint32_t bmXcptExtra;
9172	/** The sequence number of the Dtrace provider settings the state was
9173	* configured against. */
9174	uint32_t uDtraceSettingsSeqNo;
9175	/** VM-exits to check (one bit per VM-exit). */
9176	uint32_t bmExitsToCheck[3];
9177
9178	/** The initial VMX_VMCS32_CTRL_PROC_EXEC value (helps with restore). */
9179	uint32_t fProcCtlsInitial;
9180	/** The initial VMX_VMCS32_CTRL_PROC_EXEC2 value (helps with restore). */
9181	uint32_t fProcCtls2Initial;
9182	/** The initial VMX_VMCS32_CTRL_EXCEPTION_BITMAP value (helps with restore). */
9183	uint32_t bmXcptInitial;
9184	} VMXRUNDBGSTATE;
9185	AssertCompileMemberSize(VMXRUNDBGSTATE, bmExitsToCheck, (VMX_EXIT_MAX + 1 + 31) / 32 * 4);
9186	typedef VMXRUNDBGSTATE *PVMXRUNDBGSTATE;
9187
9188
9189	/**
9190	* Initializes the VMXRUNDBGSTATE structure.
9191	*
9192	* @param pVCpu The cross context virtual CPU structure of the
9193	* calling EMT.
9194	* @param pCtx The CPU register context to go with @a pVCpu.
9195	* @param pDbgState The structure to initialize.
9196	*/
9197	DECLINLINE(void) hmR0VmxRunDebugStateInit(PVMCPU pVCpu, PCCPUMCTX pCtx, PVMXRUNDBGSTATE pDbgState)
9198	{
9199	pDbgState->uRipStart = pCtx->rip;
9200	pDbgState->uCsStart = pCtx->cs.Sel;
9201
9202	pDbgState->fModifiedProcCtls = false;
9203	pDbgState->fModifiedProcCtls2 = false;
9204	pDbgState->fModifiedXcptBitmap = false;
9205	pDbgState->fClearCr0Mask = false;
9206	pDbgState->fClearCr4Mask = false;
9207	pDbgState->fCpe1Extra = 0;
9208	pDbgState->fCpe1Unwanted = 0;
9209	pDbgState->fCpe2Extra = 0;
9210	pDbgState->bmXcptExtra = 0;
9211	pDbgState->fProcCtlsInitial = pVCpu->hm.s.vmx.u32ProcCtls;
9212	pDbgState->fProcCtls2Initial = pVCpu->hm.s.vmx.u32ProcCtls2;
9213	pDbgState->bmXcptInitial = pVCpu->hm.s.vmx.u32XcptBitmap;
9214	}
9215
9216
9217	/**
9218	* Updates the VMSC fields with changes requested by @a pDbgState.
9219	*
9220	* This is performed after hmR0VmxPreRunGuestDebugStateUpdate as well
9221	* immediately before executing guest code, i.e. when interrupts are disabled.
9222	* We don't check status codes here as we cannot easily assert or return in the
9223	* latter case.
9224	*
9225	* @param pVCpu The cross context virtual CPU structure.
9226	* @param pDbgState The debug state.
9227	*/
9228	DECLINLINE(void) hmR0VmxPreRunGuestDebugStateApply(PVMCPU pVCpu, PVMXRUNDBGSTATE pDbgState)
9229	{
9230	/*
9231	* Ensure desired flags in VMCS control fields are set.
9232	* (Ignoring write failure here, as we're committed and it's just debug extras.)
9233	*
9234	* Note! We load the shadow CR0 & CR4 bits when we flag the clearing, so
9235	* there should be no stale data in pCtx at this point.
9236	*/
9237	if ( (pVCpu->hm.s.vmx.u32ProcCtls & pDbgState->fCpe1Extra) != pDbgState->fCpe1Extra
9238	\|\| (pVCpu->hm.s.vmx.u32ProcCtls & pDbgState->fCpe1Unwanted))
9239	{
9240	pVCpu->hm.s.vmx.u32ProcCtls \|= pDbgState->fCpe1Extra;
9241	pVCpu->hm.s.vmx.u32ProcCtls &= ~pDbgState->fCpe1Unwanted;
9242	VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
9243	Log6(("hmR0VmxRunDebugStateRevert: VMX_VMCS32_CTRL_PROC_EXEC: %#RX32\n", pVCpu->hm.s.vmx.u32ProcCtls));
9244	pDbgState->fModifiedProcCtls = true;
9245	}
9246
9247	if ((pVCpu->hm.s.vmx.u32ProcCtls2 & pDbgState->fCpe2Extra) != pDbgState->fCpe2Extra)
9248	{
9249	pVCpu->hm.s.vmx.u32ProcCtls2 \|= pDbgState->fCpe2Extra;
9250	VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, pVCpu->hm.s.vmx.u32ProcCtls2);
9251	Log6(("hmR0VmxRunDebugStateRevert: VMX_VMCS32_CTRL_PROC_EXEC2: %#RX32\n", pVCpu->hm.s.vmx.u32ProcCtls2));
9252	pDbgState->fModifiedProcCtls2 = true;
9253	}
9254
9255	if ((pVCpu->hm.s.vmx.u32XcptBitmap & pDbgState->bmXcptExtra) != pDbgState->bmXcptExtra)
9256	{
9257	pVCpu->hm.s.vmx.u32XcptBitmap \|= pDbgState->bmXcptExtra;
9258	VMXWriteVmcs32(VMX_VMCS32_CTRL_EXCEPTION_BITMAP, pVCpu->hm.s.vmx.u32XcptBitmap);
9259	Log6(("hmR0VmxRunDebugStateRevert: VMX_VMCS32_CTRL_EXCEPTION_BITMAP: %#RX32\n", pVCpu->hm.s.vmx.u32XcptBitmap));
9260	pDbgState->fModifiedXcptBitmap = true;
9261	}
9262
9263	if (pDbgState->fClearCr0Mask && pVCpu->hm.s.vmx.u32CR0Mask != 0)
9264	{
9265	pVCpu->hm.s.vmx.u32CR0Mask = 0;
9266	VMXWriteVmcs32(VMX_VMCS_CTRL_CR0_MASK, 0);
9267	Log6(("hmR0VmxRunDebugStateRevert: VMX_VMCS_CTRL_CR0_MASK: 0\n"));
9268	}
9269
9270	if (pDbgState->fClearCr4Mask && pVCpu->hm.s.vmx.u32CR4Mask != 0)
9271	{
9272	pVCpu->hm.s.vmx.u32CR4Mask = 0;
9273	VMXWriteVmcs32(VMX_VMCS_CTRL_CR4_MASK, 0);
9274	Log6(("hmR0VmxRunDebugStateRevert: VMX_VMCS_CTRL_CR4_MASK: 0\n"));
9275	}
9276	}
9277
9278
9279	DECLINLINE(VBOXSTRICTRC) hmR0VmxRunDebugStateRevert(PVMCPU pVCpu, PVMXRUNDBGSTATE pDbgState, VBOXSTRICTRC rcStrict)
9280	{
9281	/*
9282	* Restore VM-exit control settings as we may not reenter this function the
9283	* next time around.
9284	*/
9285	/* We reload the initial value, trigger what we can of recalculations the
9286	next time around. From the looks of things, that's all that's required atm. */
9287	if (pDbgState->fModifiedProcCtls)
9288	{
9289	if (!(pDbgState->fProcCtlsInitial & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT) && CPUMIsHyperDebugStateActive(pVCpu))
9290	pDbgState->fProcCtlsInitial \|= VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT; /* Avoid assertion in hmR0VmxLeave */
9291	int rc2 = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pDbgState->fProcCtlsInitial);
9292	AssertRCReturn(rc2, rc2);
9293	pVCpu->hm.s.vmx.u32ProcCtls = pDbgState->fProcCtlsInitial;
9294	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0 \| HM_CHANGED_GUEST_DEBUG);
9295	}
9296
9297	/* We're currently the only ones messing with this one, so just restore the
9298	cached value and reload the field. */
9299	if ( pDbgState->fModifiedProcCtls2
9300	&& pVCpu->hm.s.vmx.u32ProcCtls2 != pDbgState->fProcCtls2Initial)
9301	{
9302	int rc2 = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, pDbgState->fProcCtls2Initial);
9303	AssertRCReturn(rc2, rc2);
9304	pVCpu->hm.s.vmx.u32ProcCtls2 = pDbgState->fProcCtls2Initial;
9305	}
9306
9307	/* If we've modified the exception bitmap, we restore it and trigger
9308	reloading and partial recalculation the next time around. */
9309	if (pDbgState->fModifiedXcptBitmap)
9310	{
9311	pVCpu->hm.s.vmx.u32XcptBitmap = pDbgState->bmXcptInitial;
9312	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS \| HM_CHANGED_GUEST_CR0);
9313	}
9314
9315	/* We assume hmR0VmxLoadSharedCR0 will recalculate and load the CR0 mask. */
9316	if (pDbgState->fClearCr0Mask)
9317	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
9318
9319	/* We assume hmR0VmxLoadGuestCR3AndCR4 will recalculate and load the CR4 mask. */
9320	if (pDbgState->fClearCr4Mask)
9321	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
9322
9323	return rcStrict;
9324	}
9325
9326
9327	/**
9328	* Configures VM-exit controls for current DBGF and DTrace settings.
9329	*
9330	* This updates @a pDbgState and the VMCS execution control fields to reflect
9331	* the necessary VM-exits demanded by DBGF and DTrace.
9332	*
9333	* @param pVM The cross context VM structure.
9334	* @param pVCpu The cross context virtual CPU structure.
9335	* @param pCtx Pointer to the guest-CPU context.
9336	* @param pDbgState The debug state.
9337	* @param pVmxTransient Pointer to the VMX transient structure. May update
9338	* fUpdateTscOffsettingAndPreemptTimer.
9339	*/
9340	static void hmR0VmxPreRunGuestDebugStateUpdate(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx,
9341	PVMXRUNDBGSTATE pDbgState, PVMXTRANSIENT pVmxTransient)
9342	{
9343	/*
9344	* Take down the dtrace serial number so we can spot changes.
9345	*/
9346	pDbgState->uDtraceSettingsSeqNo = VBOXVMM_GET_SETTINGS_SEQ_NO();
9347	ASMCompilerBarrier();
9348
9349	/*
9350	* We'll rebuild most of the middle block of data members (holding the
9351	* current settings) as we go along here, so start by clearing it all.
9352	*/
9353	pDbgState->bmXcptExtra = 0;
9354	pDbgState->fCpe1Extra = 0;
9355	pDbgState->fCpe1Unwanted = 0;
9356	pDbgState->fCpe2Extra = 0;
9357	for (unsigned i = 0; i < RT_ELEMENTS(pDbgState->bmExitsToCheck); i++)
9358	pDbgState->bmExitsToCheck[i] = 0;
9359
9360	/*
9361	* Software interrupts (INT XXh) - no idea how to trigger these...
9362	*/
9363	if ( DBGF_IS_EVENT_ENABLED(pVM, DBGFEVENT_INTERRUPT_SOFTWARE)
9364	\|\| VBOXVMM_INT_SOFTWARE_ENABLED())
9365	{
9366	ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_XCPT_OR_NMI);
9367	}
9368
9369	/*
9370	* INT3 breakpoints - triggered by #BP exceptions.
9371	*/
9372	if (pVM->dbgf.ro.cEnabledInt3Breakpoints > 0)
9373	pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_BP);
9374
9375	/*
9376	* Exception bitmap and XCPT events+probes.
9377	*/
9378	for (int iXcpt = 0; iXcpt < (DBGFEVENT_XCPT_LAST - DBGFEVENT_XCPT_FIRST + 1); iXcpt++)
9379	if (DBGF_IS_EVENT_ENABLED(pVM, (DBGFEVENTTYPE)(DBGFEVENT_XCPT_FIRST + iXcpt)))
9380	pDbgState->bmXcptExtra \|= RT_BIT_32(iXcpt);
9381
9382	if (VBOXVMM_XCPT_DE_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_DE);
9383	if (VBOXVMM_XCPT_DB_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_DB);
9384	if (VBOXVMM_XCPT_BP_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_BP);
9385	if (VBOXVMM_XCPT_OF_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_OF);
9386	if (VBOXVMM_XCPT_BR_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_BR);
9387	if (VBOXVMM_XCPT_UD_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_UD);
9388	if (VBOXVMM_XCPT_NM_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_NM);
9389	if (VBOXVMM_XCPT_DF_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_DF);
9390	if (VBOXVMM_XCPT_TS_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_TS);
9391	if (VBOXVMM_XCPT_NP_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_NP);
9392	if (VBOXVMM_XCPT_SS_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_SS);
9393	if (VBOXVMM_XCPT_GP_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_GP);
9394	if (VBOXVMM_XCPT_PF_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_PF);
9395	if (VBOXVMM_XCPT_MF_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_MF);
9396	if (VBOXVMM_XCPT_AC_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_AC);
9397	if (VBOXVMM_XCPT_XF_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_XF);
9398	if (VBOXVMM_XCPT_VE_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_VE);
9399	if (VBOXVMM_XCPT_SX_ENABLED()) pDbgState->bmXcptExtra \|= RT_BIT_32(X86_XCPT_SX);
9400
9401	if (pDbgState->bmXcptExtra)
9402	ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_XCPT_OR_NMI);
9403
9404	/*
9405	* Process events and probes for VM-exits, making sure we get the wanted VM-exits.
9406	*
9407	* Note! This is the reverse of waft hmR0VmxHandleExitDtraceEvents does.
9408	* So, when adding/changing/removing please don't forget to update it.
9409	*
9410	* Some of the macros are picking up local variables to save horizontal space,
9411	* (being able to see it in a table is the lesser evil here).
9412	*/
9413	#define IS_EITHER_ENABLED(a_pVM, a_EventSubName) \
9414	( DBGF_IS_EVENT_ENABLED(a_pVM, RT_CONCAT(DBGFEVENT_, a_EventSubName)) \
9415	\|\| RT_CONCAT3(VBOXVMM_, a_EventSubName, _ENABLED)() )
9416	#define SET_ONLY_XBM_IF_EITHER_EN(a_EventSubName, a_uExit) \
9417	if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9418	{ AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9419	ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9420	} else do { } while (0)
9421	#define SET_CPE1_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fCtrlProcExec) \
9422	if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9423	{ \
9424	(pDbgState)->fCpe1Extra \|= (a_fCtrlProcExec); \
9425	AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9426	ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9427	} else do { } while (0)
9428	#define SET_CPEU_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fUnwantedCtrlProcExec) \
9429	if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9430	{ \
9431	(pDbgState)->fCpe1Unwanted \|= (a_fUnwantedCtrlProcExec); \
9432	AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9433	ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9434	} else do { } while (0)
9435	#define SET_CPE2_XBM_IF_EITHER_EN(a_EventSubName, a_uExit, a_fCtrlProcExec2) \
9436	if (IS_EITHER_ENABLED(pVM, a_EventSubName)) \
9437	{ \
9438	(pDbgState)->fCpe2Extra \|= (a_fCtrlProcExec2); \
9439	AssertCompile((unsigned)(a_uExit) < sizeof(pDbgState->bmExitsToCheck) * 8); \
9440	ASMBitSet((pDbgState)->bmExitsToCheck, a_uExit); \
9441	} else do { } while (0)
9442
9443	SET_ONLY_XBM_IF_EITHER_EN(EXIT_TASK_SWITCH, VMX_EXIT_TASK_SWITCH); /* unconditional */
9444	SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_EPT_VIOLATION, VMX_EXIT_EPT_VIOLATION); /* unconditional */
9445	SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_EPT_MISCONFIG, VMX_EXIT_EPT_MISCONFIG); /* unconditional (unless #VE) */
9446	SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VAPIC_ACCESS, VMX_EXIT_APIC_ACCESS); /* feature dependent, nothing to enable here */
9447	SET_ONLY_XBM_IF_EITHER_EN(EXIT_VMX_VAPIC_WRITE, VMX_EXIT_APIC_WRITE); /* feature dependent, nothing to enable here */
9448
9449	SET_ONLY_XBM_IF_EITHER_EN(INSTR_CPUID, VMX_EXIT_CPUID); /* unconditional */
9450	SET_ONLY_XBM_IF_EITHER_EN( EXIT_CPUID, VMX_EXIT_CPUID);
9451	SET_ONLY_XBM_IF_EITHER_EN(INSTR_GETSEC, VMX_EXIT_GETSEC); /* unconditional */
9452	SET_ONLY_XBM_IF_EITHER_EN( EXIT_GETSEC, VMX_EXIT_GETSEC);
9453	SET_CPE1_XBM_IF_EITHER_EN(INSTR_HALT, VMX_EXIT_HLT, VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT); /* paranoia */
9454	SET_ONLY_XBM_IF_EITHER_EN( EXIT_HALT, VMX_EXIT_HLT);
9455	SET_ONLY_XBM_IF_EITHER_EN(INSTR_INVD, VMX_EXIT_INVD); /* unconditional */
9456	SET_ONLY_XBM_IF_EITHER_EN( EXIT_INVD, VMX_EXIT_INVD);
9457	SET_CPE1_XBM_IF_EITHER_EN(INSTR_INVLPG, VMX_EXIT_INVLPG, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
9458	SET_ONLY_XBM_IF_EITHER_EN( EXIT_INVLPG, VMX_EXIT_INVLPG);
9459	SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDPMC, VMX_EXIT_RDPMC, VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
9460	SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDPMC, VMX_EXIT_RDPMC);
9461	SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDTSC, VMX_EXIT_RDTSC, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
9462	SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDTSC, VMX_EXIT_RDTSC);
9463	SET_ONLY_XBM_IF_EITHER_EN(INSTR_RSM, VMX_EXIT_RSM); /* unconditional */
9464	SET_ONLY_XBM_IF_EITHER_EN( EXIT_RSM, VMX_EXIT_RSM);
9465	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMM_CALL, VMX_EXIT_VMCALL); /* unconditional */
9466	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMM_CALL, VMX_EXIT_VMCALL);
9467	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMCLEAR, VMX_EXIT_VMCLEAR); /* unconditional */
9468	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMCLEAR, VMX_EXIT_VMCLEAR);
9469	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMLAUNCH, VMX_EXIT_VMLAUNCH); /* unconditional */
9470	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMLAUNCH, VMX_EXIT_VMLAUNCH);
9471	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMPTRLD, VMX_EXIT_VMPTRLD); /* unconditional */
9472	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMPTRLD, VMX_EXIT_VMPTRLD);
9473	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMPTRST, VMX_EXIT_VMPTRST); /* unconditional */
9474	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMPTRST, VMX_EXIT_VMPTRST);
9475	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMREAD, VMX_EXIT_VMREAD); /* unconditional */
9476	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMREAD, VMX_EXIT_VMREAD);
9477	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMRESUME, VMX_EXIT_VMRESUME); /* unconditional */
9478	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMRESUME, VMX_EXIT_VMRESUME);
9479	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMWRITE, VMX_EXIT_VMWRITE); /* unconditional */
9480	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMWRITE, VMX_EXIT_VMWRITE);
9481	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMXOFF, VMX_EXIT_VMXOFF); /* unconditional */
9482	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMXOFF, VMX_EXIT_VMXOFF);
9483	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMXON, VMX_EXIT_VMXON); /* unconditional */
9484	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMXON, VMX_EXIT_VMXON);
9485
9486	if ( IS_EITHER_ENABLED(pVM, INSTR_CRX_READ)
9487	\|\| IS_EITHER_ENABLED(pVM, INSTR_CRX_WRITE))
9488	{
9489	int rc2 = hmR0VmxSaveGuestCR0(pVCpu, pCtx);
9490	rc2 \|= hmR0VmxSaveGuestCR4(pVCpu, pCtx);
9491	rc2 \|= hmR0VmxSaveGuestApicState(pVCpu, pCtx);
9492	AssertRC(rc2);
9493
9494	#if 0 /** @todo fix me */
9495	pDbgState->fClearCr0Mask = true;
9496	pDbgState->fClearCr4Mask = true;
9497	#endif
9498	if (IS_EITHER_ENABLED(pVM, INSTR_CRX_READ))
9499	pDbgState->fCpe1Extra \|= VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT \| VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT;
9500	if (IS_EITHER_ENABLED(pVM, INSTR_CRX_WRITE))
9501	pDbgState->fCpe1Extra \|= VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT \| VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT;
9502	pDbgState->fCpe1Unwanted \|= VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW; /* risky? */
9503	/* Note! We currently don't use VMX_VMCS32_CTRL_CR3_TARGET_COUNT. It would
9504	require clearing here and in the loop if we start using it. */
9505	ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_MOV_CRX);
9506	}
9507	else
9508	{
9509	if (pDbgState->fClearCr0Mask)
9510	{
9511	pDbgState->fClearCr0Mask = false;
9512	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
9513	}
9514	if (pDbgState->fClearCr4Mask)
9515	{
9516	pDbgState->fClearCr4Mask = false;
9517	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
9518	}
9519	}
9520	SET_ONLY_XBM_IF_EITHER_EN( EXIT_CRX_READ, VMX_EXIT_MOV_CRX);
9521	SET_ONLY_XBM_IF_EITHER_EN( EXIT_CRX_WRITE, VMX_EXIT_MOV_CRX);
9522
9523	if ( IS_EITHER_ENABLED(pVM, INSTR_DRX_READ)
9524	\|\| IS_EITHER_ENABLED(pVM, INSTR_DRX_WRITE))
9525	{
9526	/** @todo later, need to fix handler as it assumes this won't usually happen. */
9527	ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_MOV_DRX);
9528	}
9529	SET_ONLY_XBM_IF_EITHER_EN( EXIT_DRX_READ, VMX_EXIT_MOV_DRX);
9530	SET_ONLY_XBM_IF_EITHER_EN( EXIT_DRX_WRITE, VMX_EXIT_MOV_DRX);
9531
9532	SET_CPEU_XBM_IF_EITHER_EN(INSTR_RDMSR, VMX_EXIT_RDMSR, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS); /* risky clearing this? */
9533	SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDMSR, VMX_EXIT_RDMSR);
9534	SET_CPEU_XBM_IF_EITHER_EN(INSTR_WRMSR, VMX_EXIT_WRMSR, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
9535	SET_ONLY_XBM_IF_EITHER_EN( EXIT_WRMSR, VMX_EXIT_WRMSR);
9536	SET_CPE1_XBM_IF_EITHER_EN(INSTR_MWAIT, VMX_EXIT_MWAIT, VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT); /* paranoia */
9537	SET_ONLY_XBM_IF_EITHER_EN( EXIT_MWAIT, VMX_EXIT_MWAIT);
9538	SET_CPE1_XBM_IF_EITHER_EN(INSTR_MONITOR, VMX_EXIT_MONITOR, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT); /* paranoia */
9539	SET_ONLY_XBM_IF_EITHER_EN( EXIT_MONITOR, VMX_EXIT_MONITOR);
9540	#if 0 /** @todo too slow, fix handler. */
9541	SET_CPE1_XBM_IF_EITHER_EN(INSTR_PAUSE, VMX_EXIT_PAUSE, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
9542	#endif
9543	SET_ONLY_XBM_IF_EITHER_EN( EXIT_PAUSE, VMX_EXIT_PAUSE);
9544
9545	if ( IS_EITHER_ENABLED(pVM, INSTR_SGDT)
9546	\|\| IS_EITHER_ENABLED(pVM, INSTR_SIDT)
9547	\|\| IS_EITHER_ENABLED(pVM, INSTR_LGDT)
9548	\|\| IS_EITHER_ENABLED(pVM, INSTR_LIDT))
9549	{
9550	pDbgState->fCpe2Extra \|= VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT;
9551	ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_XDTR_ACCESS);
9552	}
9553	SET_ONLY_XBM_IF_EITHER_EN( EXIT_SGDT, VMX_EXIT_XDTR_ACCESS);
9554	SET_ONLY_XBM_IF_EITHER_EN( EXIT_SIDT, VMX_EXIT_XDTR_ACCESS);
9555	SET_ONLY_XBM_IF_EITHER_EN( EXIT_LGDT, VMX_EXIT_XDTR_ACCESS);
9556	SET_ONLY_XBM_IF_EITHER_EN( EXIT_LIDT, VMX_EXIT_XDTR_ACCESS);
9557
9558	if ( IS_EITHER_ENABLED(pVM, INSTR_SLDT)
9559	\|\| IS_EITHER_ENABLED(pVM, INSTR_STR)
9560	\|\| IS_EITHER_ENABLED(pVM, INSTR_LLDT)
9561	\|\| IS_EITHER_ENABLED(pVM, INSTR_LTR))
9562	{
9563	pDbgState->fCpe2Extra \|= VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT;
9564	ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_TR_ACCESS);
9565	}
9566	SET_ONLY_XBM_IF_EITHER_EN( EXIT_SLDT, VMX_EXIT_TR_ACCESS);
9567	SET_ONLY_XBM_IF_EITHER_EN( EXIT_STR, VMX_EXIT_TR_ACCESS);
9568	SET_ONLY_XBM_IF_EITHER_EN( EXIT_LLDT, VMX_EXIT_TR_ACCESS);
9569	SET_ONLY_XBM_IF_EITHER_EN( EXIT_LTR, VMX_EXIT_TR_ACCESS);
9570
9571	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_INVEPT, VMX_EXIT_INVEPT); /* unconditional */
9572	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVEPT, VMX_EXIT_INVEPT);
9573	SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDTSCP, VMX_EXIT_RDTSCP, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
9574	SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDTSCP, VMX_EXIT_RDTSCP);
9575	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_INVVPID, VMX_EXIT_INVVPID); /* unconditional */
9576	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVVPID, VMX_EXIT_INVVPID);
9577	SET_CPE2_XBM_IF_EITHER_EN(INSTR_WBINVD, VMX_EXIT_WBINVD, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
9578	SET_ONLY_XBM_IF_EITHER_EN( EXIT_WBINVD, VMX_EXIT_WBINVD);
9579	SET_ONLY_XBM_IF_EITHER_EN(INSTR_XSETBV, VMX_EXIT_XSETBV); /* unconditional */
9580	SET_ONLY_XBM_IF_EITHER_EN( EXIT_XSETBV, VMX_EXIT_XSETBV);
9581	SET_CPE2_XBM_IF_EITHER_EN(INSTR_RDRAND, VMX_EXIT_RDRAND, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
9582	SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDRAND, VMX_EXIT_RDRAND);
9583	SET_CPE1_XBM_IF_EITHER_EN(INSTR_VMX_INVPCID, VMX_EXIT_INVPCID, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
9584	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVPCID, VMX_EXIT_INVPCID);
9585	SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMFUNC, VMX_EXIT_VMFUNC); /* unconditional for the current setup */
9586	SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMFUNC, VMX_EXIT_VMFUNC);
9587	SET_CPE2_XBM_IF_EITHER_EN(INSTR_RDSEED, VMX_EXIT_RDSEED, VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT);
9588	SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDSEED, VMX_EXIT_RDSEED);
9589	SET_ONLY_XBM_IF_EITHER_EN(INSTR_XSAVES, VMX_EXIT_XSAVES); /* unconditional (enabled by host, guest cfg) */
9590	SET_ONLY_XBM_IF_EITHER_EN(EXIT_XSAVES, VMX_EXIT_XSAVES);
9591	SET_ONLY_XBM_IF_EITHER_EN(INSTR_XRSTORS, VMX_EXIT_XRSTORS); /* unconditional (enabled by host, guest cfg) */
9592	SET_ONLY_XBM_IF_EITHER_EN( EXIT_XRSTORS, VMX_EXIT_XRSTORS);
9593
9594	#undef IS_EITHER_ENABLED
9595	#undef SET_ONLY_XBM_IF_EITHER_EN
9596	#undef SET_CPE1_XBM_IF_EITHER_EN
9597	#undef SET_CPEU_XBM_IF_EITHER_EN
9598	#undef SET_CPE2_XBM_IF_EITHER_EN
9599
9600	/*
9601	* Sanitize the control stuff.
9602	*/
9603	pDbgState->fCpe2Extra &= pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1;
9604	if (pDbgState->fCpe2Extra)
9605	pDbgState->fCpe1Extra \|= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
9606	pDbgState->fCpe1Extra &= pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1;
9607	pDbgState->fCpe1Unwanted &= ~pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0;
9608	if (pVCpu->hm.s.fDebugWantRdTscExit != RT_BOOL(pDbgState->fCpe1Extra & VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT))
9609	{
9610	pVCpu->hm.s.fDebugWantRdTscExit ^= true;
9611	pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
9612	}
9613
9614	Log6(("HM: debug state: cpe1=%#RX32 cpeu=%#RX32 cpe2=%#RX32%s%s\n",
9615	pDbgState->fCpe1Extra, pDbgState->fCpe1Unwanted, pDbgState->fCpe2Extra,
9616	pDbgState->fClearCr0Mask ? " clr-cr0" : "",
9617	pDbgState->fClearCr4Mask ? " clr-cr4" : ""));
9618	}
9619
9620
9621	/**
9622	* Fires off DBGF events and dtrace probes for a VM-exit, when it's
9623	* appropriate.
9624	*
9625	* The caller has checked the VM-exit against the
9626	* VMXRUNDBGSTATE::bmExitsToCheck bitmap. The caller has checked for NMIs
9627	* already, so we don't have to do that either.
9628	*
9629	* @returns Strict VBox status code (i.e. informational status codes too).
9630	* @param pVM The cross context VM structure.
9631	* @param pVCpu The cross context virtual CPU structure.
9632	* @param pMixedCtx Pointer to the guest-CPU context.
9633	* @param pVmxTransient Pointer to the VMX-transient structure.
9634	* @param uExitReason The VM-exit reason.
9635	*
9636	* @remarks The name of this function is displayed by dtrace, so keep it short
9637	* and to the point. No longer than 33 chars long, please.
9638	*/
9639	static VBOXSTRICTRC hmR0VmxHandleExitDtraceEvents(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx,
9640	PVMXTRANSIENT pVmxTransient, uint32_t uExitReason)
9641	{
9642	/*
9643	* Translate the event into a DBGF event (enmEvent + uEventArg) and at the
9644	* same time check whether any corresponding Dtrace event is enabled (fDtrace).
9645	*
9646	* Note! This is the reverse operation of what hmR0VmxPreRunGuestDebugStateUpdate
9647	* does. Must add/change/remove both places. Same ordering, please.
9648	*
9649	* Added/removed events must also be reflected in the next section
9650	* where we dispatch dtrace events.
9651	*/
9652	bool fDtrace1 = false;
9653	bool fDtrace2 = false;
9654	DBGFEVENTTYPE enmEvent1 = DBGFEVENT_END;
9655	DBGFEVENTTYPE enmEvent2 = DBGFEVENT_END;
9656	uint32_t uEventArg = 0;
9657	#define SET_EXIT(a_EventSubName) \
9658	do { \
9659	enmEvent2 = RT_CONCAT(DBGFEVENT_EXIT_, a_EventSubName); \
9660	fDtrace2 = RT_CONCAT3(VBOXVMM_EXIT_, a_EventSubName, _ENABLED)(); \
9661	} while (0)
9662	#define SET_BOTH(a_EventSubName) \
9663	do { \
9664	enmEvent1 = RT_CONCAT(DBGFEVENT_INSTR_, a_EventSubName); \
9665	enmEvent2 = RT_CONCAT(DBGFEVENT_EXIT_, a_EventSubName); \
9666	fDtrace1 = RT_CONCAT3(VBOXVMM_INSTR_, a_EventSubName, _ENABLED)(); \
9667	fDtrace2 = RT_CONCAT3(VBOXVMM_EXIT_, a_EventSubName, _ENABLED)(); \
9668	} while (0)
9669	switch (uExitReason)
9670	{
9671	case VMX_EXIT_MTF:
9672	return hmR0VmxExitMtf(pVCpu, pMixedCtx, pVmxTransient);
9673
9674	case VMX_EXIT_XCPT_OR_NMI:
9675	{
9676	uint8_t const idxVector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVmxTransient->uExitIntInfo);
9677	switch (VMX_EXIT_INTERRUPTION_INFO_TYPE(pVmxTransient->uExitIntInfo))
9678	{
9679	case VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT:
9680	case VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT:
9681	case VMX_EXIT_INTERRUPTION_INFO_TYPE_PRIV_SW_XCPT:
9682	if (idxVector <= (unsigned)(DBGFEVENT_XCPT_LAST - DBGFEVENT_XCPT_FIRST))
9683	{
9684	if (VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_IS_VALID(pVmxTransient->uExitIntInfo))
9685	{
9686	hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
9687	uEventArg = pVmxTransient->uExitIntErrorCode;
9688	}
9689	enmEvent1 = (DBGFEVENTTYPE)(DBGFEVENT_XCPT_FIRST + idxVector);
9690	switch (enmEvent1)
9691	{
9692	case DBGFEVENT_XCPT_DE: fDtrace1 = VBOXVMM_XCPT_DE_ENABLED(); break;
9693	case DBGFEVENT_XCPT_DB: fDtrace1 = VBOXVMM_XCPT_DB_ENABLED(); break;
9694	case DBGFEVENT_XCPT_BP: fDtrace1 = VBOXVMM_XCPT_BP_ENABLED(); break;
9695	case DBGFEVENT_XCPT_OF: fDtrace1 = VBOXVMM_XCPT_OF_ENABLED(); break;
9696	case DBGFEVENT_XCPT_BR: fDtrace1 = VBOXVMM_XCPT_BR_ENABLED(); break;
9697	case DBGFEVENT_XCPT_UD: fDtrace1 = VBOXVMM_XCPT_UD_ENABLED(); break;
9698	case DBGFEVENT_XCPT_NM: fDtrace1 = VBOXVMM_XCPT_NM_ENABLED(); break;
9699	case DBGFEVENT_XCPT_DF: fDtrace1 = VBOXVMM_XCPT_DF_ENABLED(); break;
9700	case DBGFEVENT_XCPT_TS: fDtrace1 = VBOXVMM_XCPT_TS_ENABLED(); break;
9701	case DBGFEVENT_XCPT_NP: fDtrace1 = VBOXVMM_XCPT_NP_ENABLED(); break;
9702	case DBGFEVENT_XCPT_SS: fDtrace1 = VBOXVMM_XCPT_SS_ENABLED(); break;
9703	case DBGFEVENT_XCPT_GP: fDtrace1 = VBOXVMM_XCPT_GP_ENABLED(); break;
9704	case DBGFEVENT_XCPT_PF: fDtrace1 = VBOXVMM_XCPT_PF_ENABLED(); break;
9705	case DBGFEVENT_XCPT_MF: fDtrace1 = VBOXVMM_XCPT_MF_ENABLED(); break;
9706	case DBGFEVENT_XCPT_AC: fDtrace1 = VBOXVMM_XCPT_AC_ENABLED(); break;
9707	case DBGFEVENT_XCPT_XF: fDtrace1 = VBOXVMM_XCPT_XF_ENABLED(); break;
9708	case DBGFEVENT_XCPT_VE: fDtrace1 = VBOXVMM_XCPT_VE_ENABLED(); break;
9709	case DBGFEVENT_XCPT_SX: fDtrace1 = VBOXVMM_XCPT_SX_ENABLED(); break;
9710	default: break;
9711	}
9712	}
9713	else
9714	AssertFailed();
9715	break;
9716
9717	case VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_INT:
9718	uEventArg = idxVector;
9719	enmEvent1 = DBGFEVENT_INTERRUPT_SOFTWARE;
9720	fDtrace1 = VBOXVMM_INT_SOFTWARE_ENABLED();
9721	break;
9722	}
9723	break;
9724	}
9725
9726	case VMX_EXIT_TRIPLE_FAULT:
9727	enmEvent1 = DBGFEVENT_TRIPLE_FAULT;
9728	//fDtrace1 = VBOXVMM_EXIT_TRIPLE_FAULT_ENABLED();
9729	break;
9730	case VMX_EXIT_TASK_SWITCH: SET_EXIT(TASK_SWITCH); break;
9731	case VMX_EXIT_EPT_VIOLATION: SET_EXIT(VMX_EPT_VIOLATION); break;
9732	case VMX_EXIT_EPT_MISCONFIG: SET_EXIT(VMX_EPT_MISCONFIG); break;
9733	case VMX_EXIT_APIC_ACCESS: SET_EXIT(VMX_VAPIC_ACCESS); break;
9734	case VMX_EXIT_APIC_WRITE: SET_EXIT(VMX_VAPIC_WRITE); break;
9735
9736	/* Instruction specific VM-exits: */
9737	case VMX_EXIT_CPUID: SET_BOTH(CPUID); break;
9738	case VMX_EXIT_GETSEC: SET_BOTH(GETSEC); break;
9739	case VMX_EXIT_HLT: SET_BOTH(HALT); break;
9740	case VMX_EXIT_INVD: SET_BOTH(INVD); break;
9741	case VMX_EXIT_INVLPG: SET_BOTH(INVLPG); break;
9742	case VMX_EXIT_RDPMC: SET_BOTH(RDPMC); break;
9743	case VMX_EXIT_RDTSC: SET_BOTH(RDTSC); break;
9744	case VMX_EXIT_RSM: SET_BOTH(RSM); break;
9745	case VMX_EXIT_VMCALL: SET_BOTH(VMM_CALL); break;
9746	case VMX_EXIT_VMCLEAR: SET_BOTH(VMX_VMCLEAR); break;
9747	case VMX_EXIT_VMLAUNCH: SET_BOTH(VMX_VMLAUNCH); break;
9748	case VMX_EXIT_VMPTRLD: SET_BOTH(VMX_VMPTRLD); break;
9749	case VMX_EXIT_VMPTRST: SET_BOTH(VMX_VMPTRST); break;
9750	case VMX_EXIT_VMREAD: SET_BOTH(VMX_VMREAD); break;
9751	case VMX_EXIT_VMRESUME: SET_BOTH(VMX_VMRESUME); break;
9752	case VMX_EXIT_VMWRITE: SET_BOTH(VMX_VMWRITE); break;
9753	case VMX_EXIT_VMXOFF: SET_BOTH(VMX_VMXOFF); break;
9754	case VMX_EXIT_VMXON: SET_BOTH(VMX_VMXON); break;
9755	case VMX_EXIT_MOV_CRX:
9756	hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
9757	/** @todo r=bird: I feel these macros aren't very descriptive and needs to be at least 30 chars longer! ;-)
9758	* Sensible abbreviations strongly recommended here because even with 130 columns this stuff get too wide! */
9759	if ( VMX_EXIT_QUALIFICATION_CRX_ACCESS(pVmxTransient->uExitQualification)
9760	== VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ)
9761	SET_BOTH(CRX_READ);
9762	else
9763	SET_BOTH(CRX_WRITE);
9764	uEventArg = VMX_EXIT_QUALIFICATION_CRX_REGISTER(pVmxTransient->uExitQualification);
9765	break;
9766	case VMX_EXIT_MOV_DRX:
9767	hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
9768	if ( VMX_EXIT_QUALIFICATION_DRX_DIRECTION(pVmxTransient->uExitQualification)
9769	== VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ)
9770	SET_BOTH(DRX_READ);
9771	else
9772	SET_BOTH(DRX_WRITE);
9773	uEventArg = VMX_EXIT_QUALIFICATION_DRX_REGISTER(pVmxTransient->uExitQualification);
9774	break;
9775	case VMX_EXIT_RDMSR: SET_BOTH(RDMSR); break;
9776	case VMX_EXIT_WRMSR: SET_BOTH(WRMSR); break;
9777	case VMX_EXIT_MWAIT: SET_BOTH(MWAIT); break;
9778	case VMX_EXIT_MONITOR: SET_BOTH(MONITOR); break;
9779	case VMX_EXIT_PAUSE: SET_BOTH(PAUSE); break;
9780	case VMX_EXIT_XDTR_ACCESS:
9781	hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
9782	switch (RT_BF_GET(pVmxTransient->ExitInstrInfo.u, VMX_XDTR_INSINFO_INSTR_ID))
9783	{
9784	case VMX_XDTR_INSINFO_II_SGDT: SET_BOTH(SGDT); break;
9785	case VMX_XDTR_INSINFO_II_SIDT: SET_BOTH(SIDT); break;
9786	case VMX_XDTR_INSINFO_II_LGDT: SET_BOTH(LGDT); break;
9787	case VMX_XDTR_INSINFO_II_LIDT: SET_BOTH(LIDT); break;
9788	}
9789	break;
9790
9791	case VMX_EXIT_TR_ACCESS:
9792	hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
9793	switch (RT_BF_GET(pVmxTransient->ExitInstrInfo.u, VMX_YYTR_INSINFO_INSTR_ID))
9794	{
9795	case VMX_YYTR_INSINFO_II_SLDT: SET_BOTH(SLDT); break;
9796	case VMX_YYTR_INSINFO_II_STR: SET_BOTH(STR); break;
9797	case VMX_YYTR_INSINFO_II_LLDT: SET_BOTH(LLDT); break;
9798	case VMX_YYTR_INSINFO_II_LTR: SET_BOTH(LTR); break;
9799	}
9800	break;
9801
9802	case VMX_EXIT_INVEPT: SET_BOTH(VMX_INVEPT); break;
9803	case VMX_EXIT_RDTSCP: SET_BOTH(RDTSCP); break;
9804	case VMX_EXIT_INVVPID: SET_BOTH(VMX_INVVPID); break;
9805	case VMX_EXIT_WBINVD: SET_BOTH(WBINVD); break;
9806	case VMX_EXIT_XSETBV: SET_BOTH(XSETBV); break;
9807	case VMX_EXIT_RDRAND: SET_BOTH(RDRAND); break;
9808	case VMX_EXIT_INVPCID: SET_BOTH(VMX_INVPCID); break;
9809	case VMX_EXIT_VMFUNC: SET_BOTH(VMX_VMFUNC); break;
9810	case VMX_EXIT_RDSEED: SET_BOTH(RDSEED); break;
9811	case VMX_EXIT_XSAVES: SET_BOTH(XSAVES); break;
9812	case VMX_EXIT_XRSTORS: SET_BOTH(XRSTORS); break;
9813
9814	/* Events that aren't relevant at this point. */
9815	case VMX_EXIT_EXT_INT:
9816	case VMX_EXIT_INT_WINDOW:
9817	case VMX_EXIT_NMI_WINDOW:
9818	case VMX_EXIT_TPR_BELOW_THRESHOLD:
9819	case VMX_EXIT_PREEMPT_TIMER:
9820	case VMX_EXIT_IO_INSTR:
9821	break;
9822
9823	/* Errors and unexpected events. */
9824	case VMX_EXIT_INIT_SIGNAL:
9825	case VMX_EXIT_SIPI:
9826	case VMX_EXIT_IO_SMI:
9827	case VMX_EXIT_SMI:
9828	case VMX_EXIT_ERR_INVALID_GUEST_STATE:
9829	case VMX_EXIT_ERR_MSR_LOAD:
9830	case VMX_EXIT_ERR_MACHINE_CHECK:
9831	break;
9832
9833	default:
9834	AssertMsgFailed(("Unexpected VM-exit=%#x\n", uExitReason));
9835	break;
9836	}
9837	#undef SET_BOTH
9838	#undef SET_EXIT
9839
9840	/*
9841	* Dtrace tracepoints go first. We do them here at once so we don't
9842	* have to copy the guest state saving and stuff a few dozen times.
9843	* Down side is that we've got to repeat the switch, though this time
9844	* we use enmEvent since the probes are a subset of what DBGF does.
9845	*/
9846	if (fDtrace1 \|\| fDtrace2)
9847	{
9848	hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
9849	hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
9850	switch (enmEvent1)
9851	{
9852	/** @todo consider which extra parameters would be helpful for each probe. */
9853	case DBGFEVENT_END: break;
9854	case DBGFEVENT_XCPT_DE: VBOXVMM_XCPT_DE(pVCpu, pMixedCtx); break;
9855	case DBGFEVENT_XCPT_DB: VBOXVMM_XCPT_DB(pVCpu, pMixedCtx, pMixedCtx->dr[6]); break;
9856	case DBGFEVENT_XCPT_BP: VBOXVMM_XCPT_BP(pVCpu, pMixedCtx); break;
9857	case DBGFEVENT_XCPT_OF: VBOXVMM_XCPT_OF(pVCpu, pMixedCtx); break;
9858	case DBGFEVENT_XCPT_BR: VBOXVMM_XCPT_BR(pVCpu, pMixedCtx); break;
9859	case DBGFEVENT_XCPT_UD: VBOXVMM_XCPT_UD(pVCpu, pMixedCtx); break;
9860	case DBGFEVENT_XCPT_NM: VBOXVMM_XCPT_NM(pVCpu, pMixedCtx); break;
9861	case DBGFEVENT_XCPT_DF: VBOXVMM_XCPT_DF(pVCpu, pMixedCtx); break;
9862	case DBGFEVENT_XCPT_TS: VBOXVMM_XCPT_TS(pVCpu, pMixedCtx, uEventArg); break;
9863	case DBGFEVENT_XCPT_NP: VBOXVMM_XCPT_NP(pVCpu, pMixedCtx, uEventArg); break;
9864	case DBGFEVENT_XCPT_SS: VBOXVMM_XCPT_SS(pVCpu, pMixedCtx, uEventArg); break;
9865	case DBGFEVENT_XCPT_GP: VBOXVMM_XCPT_GP(pVCpu, pMixedCtx, uEventArg); break;
9866	case DBGFEVENT_XCPT_PF: VBOXVMM_XCPT_PF(pVCpu, pMixedCtx, uEventArg, pMixedCtx->cr2); break;
9867	case DBGFEVENT_XCPT_MF: VBOXVMM_XCPT_MF(pVCpu, pMixedCtx); break;
9868	case DBGFEVENT_XCPT_AC: VBOXVMM_XCPT_AC(pVCpu, pMixedCtx); break;
9869	case DBGFEVENT_XCPT_XF: VBOXVMM_XCPT_XF(pVCpu, pMixedCtx); break;
9870	case DBGFEVENT_XCPT_VE: VBOXVMM_XCPT_VE(pVCpu, pMixedCtx); break;
9871	case DBGFEVENT_XCPT_SX: VBOXVMM_XCPT_SX(pVCpu, pMixedCtx, uEventArg); break;
9872	case DBGFEVENT_INTERRUPT_SOFTWARE: VBOXVMM_INT_SOFTWARE(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
9873	case DBGFEVENT_INSTR_CPUID: VBOXVMM_INSTR_CPUID(pVCpu, pMixedCtx, pMixedCtx->eax, pMixedCtx->ecx); break;
9874	case DBGFEVENT_INSTR_GETSEC: VBOXVMM_INSTR_GETSEC(pVCpu, pMixedCtx); break;
9875	case DBGFEVENT_INSTR_HALT: VBOXVMM_INSTR_HALT(pVCpu, pMixedCtx); break;
9876	case DBGFEVENT_INSTR_INVD: VBOXVMM_INSTR_INVD(pVCpu, pMixedCtx); break;
9877	case DBGFEVENT_INSTR_INVLPG: VBOXVMM_INSTR_INVLPG(pVCpu, pMixedCtx); break;
9878	case DBGFEVENT_INSTR_RDPMC: VBOXVMM_INSTR_RDPMC(pVCpu, pMixedCtx); break;
9879	case DBGFEVENT_INSTR_RDTSC: VBOXVMM_INSTR_RDTSC(pVCpu, pMixedCtx); break;
9880	case DBGFEVENT_INSTR_RSM: VBOXVMM_INSTR_RSM(pVCpu, pMixedCtx); break;
9881	case DBGFEVENT_INSTR_CRX_READ: VBOXVMM_INSTR_CRX_READ(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
9882	case DBGFEVENT_INSTR_CRX_WRITE: VBOXVMM_INSTR_CRX_WRITE(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
9883	case DBGFEVENT_INSTR_DRX_READ: VBOXVMM_INSTR_DRX_READ(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
9884	case DBGFEVENT_INSTR_DRX_WRITE: VBOXVMM_INSTR_DRX_WRITE(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
9885	case DBGFEVENT_INSTR_RDMSR: VBOXVMM_INSTR_RDMSR(pVCpu, pMixedCtx, pMixedCtx->ecx); break;
9886	case DBGFEVENT_INSTR_WRMSR: VBOXVMM_INSTR_WRMSR(pVCpu, pMixedCtx, pMixedCtx->ecx,
9887	RT_MAKE_U64(pMixedCtx->eax, pMixedCtx->edx)); break;
9888	case DBGFEVENT_INSTR_MWAIT: VBOXVMM_INSTR_MWAIT(pVCpu, pMixedCtx); break;
9889	case DBGFEVENT_INSTR_MONITOR: VBOXVMM_INSTR_MONITOR(pVCpu, pMixedCtx); break;
9890	case DBGFEVENT_INSTR_PAUSE: VBOXVMM_INSTR_PAUSE(pVCpu, pMixedCtx); break;
9891	case DBGFEVENT_INSTR_SGDT: VBOXVMM_INSTR_SGDT(pVCpu, pMixedCtx); break;
9892	case DBGFEVENT_INSTR_SIDT: VBOXVMM_INSTR_SIDT(pVCpu, pMixedCtx); break;
9893	case DBGFEVENT_INSTR_LGDT: VBOXVMM_INSTR_LGDT(pVCpu, pMixedCtx); break;
9894	case DBGFEVENT_INSTR_LIDT: VBOXVMM_INSTR_LIDT(pVCpu, pMixedCtx); break;
9895	case DBGFEVENT_INSTR_SLDT: VBOXVMM_INSTR_SLDT(pVCpu, pMixedCtx); break;
9896	case DBGFEVENT_INSTR_STR: VBOXVMM_INSTR_STR(pVCpu, pMixedCtx); break;
9897	case DBGFEVENT_INSTR_LLDT: VBOXVMM_INSTR_LLDT(pVCpu, pMixedCtx); break;
9898	case DBGFEVENT_INSTR_LTR: VBOXVMM_INSTR_LTR(pVCpu, pMixedCtx); break;
9899	case DBGFEVENT_INSTR_RDTSCP: VBOXVMM_INSTR_RDTSCP(pVCpu, pMixedCtx); break;
9900	case DBGFEVENT_INSTR_WBINVD: VBOXVMM_INSTR_WBINVD(pVCpu, pMixedCtx); break;
9901	case DBGFEVENT_INSTR_XSETBV: VBOXVMM_INSTR_XSETBV(pVCpu, pMixedCtx); break;
9902	case DBGFEVENT_INSTR_RDRAND: VBOXVMM_INSTR_RDRAND(pVCpu, pMixedCtx); break;
9903	case DBGFEVENT_INSTR_RDSEED: VBOXVMM_INSTR_RDSEED(pVCpu, pMixedCtx); break;
9904	case DBGFEVENT_INSTR_XSAVES: VBOXVMM_INSTR_XSAVES(pVCpu, pMixedCtx); break;
9905	case DBGFEVENT_INSTR_XRSTORS: VBOXVMM_INSTR_XRSTORS(pVCpu, pMixedCtx); break;
9906	case DBGFEVENT_INSTR_VMM_CALL: VBOXVMM_INSTR_VMM_CALL(pVCpu, pMixedCtx); break;
9907	case DBGFEVENT_INSTR_VMX_VMCLEAR: VBOXVMM_INSTR_VMX_VMCLEAR(pVCpu, pMixedCtx); break;
9908	case DBGFEVENT_INSTR_VMX_VMLAUNCH: VBOXVMM_INSTR_VMX_VMLAUNCH(pVCpu, pMixedCtx); break;
9909	case DBGFEVENT_INSTR_VMX_VMPTRLD: VBOXVMM_INSTR_VMX_VMPTRLD(pVCpu, pMixedCtx); break;
9910	case DBGFEVENT_INSTR_VMX_VMPTRST: VBOXVMM_INSTR_VMX_VMPTRST(pVCpu, pMixedCtx); break;
9911	case DBGFEVENT_INSTR_VMX_VMREAD: VBOXVMM_INSTR_VMX_VMREAD(pVCpu, pMixedCtx); break;
9912	case DBGFEVENT_INSTR_VMX_VMRESUME: VBOXVMM_INSTR_VMX_VMRESUME(pVCpu, pMixedCtx); break;
9913	case DBGFEVENT_INSTR_VMX_VMWRITE: VBOXVMM_INSTR_VMX_VMWRITE(pVCpu, pMixedCtx); break;
9914	case DBGFEVENT_INSTR_VMX_VMXOFF: VBOXVMM_INSTR_VMX_VMXOFF(pVCpu, pMixedCtx); break;
9915	case DBGFEVENT_INSTR_VMX_VMXON: VBOXVMM_INSTR_VMX_VMXON(pVCpu, pMixedCtx); break;
9916	case DBGFEVENT_INSTR_VMX_INVEPT: VBOXVMM_INSTR_VMX_INVEPT(pVCpu, pMixedCtx); break;
9917	case DBGFEVENT_INSTR_VMX_INVVPID: VBOXVMM_INSTR_VMX_INVVPID(pVCpu, pMixedCtx); break;
9918	case DBGFEVENT_INSTR_VMX_INVPCID: VBOXVMM_INSTR_VMX_INVPCID(pVCpu, pMixedCtx); break;
9919	case DBGFEVENT_INSTR_VMX_VMFUNC: VBOXVMM_INSTR_VMX_VMFUNC(pVCpu, pMixedCtx); break;
9920	default: AssertMsgFailed(("enmEvent1=%d uExitReason=%d\n", enmEvent1, uExitReason)); break;
9921	}
9922	switch (enmEvent2)
9923	{
9924	/** @todo consider which extra parameters would be helpful for each probe. */
9925	case DBGFEVENT_END: break;
9926	case DBGFEVENT_EXIT_TASK_SWITCH: VBOXVMM_EXIT_TASK_SWITCH(pVCpu, pMixedCtx); break;
9927	case DBGFEVENT_EXIT_CPUID: VBOXVMM_EXIT_CPUID(pVCpu, pMixedCtx, pMixedCtx->eax, pMixedCtx->ecx); break;
9928	case DBGFEVENT_EXIT_GETSEC: VBOXVMM_EXIT_GETSEC(pVCpu, pMixedCtx); break;
9929	case DBGFEVENT_EXIT_HALT: VBOXVMM_EXIT_HALT(pVCpu, pMixedCtx); break;
9930	case DBGFEVENT_EXIT_INVD: VBOXVMM_EXIT_INVD(pVCpu, pMixedCtx); break;
9931	case DBGFEVENT_EXIT_INVLPG: VBOXVMM_EXIT_INVLPG(pVCpu, pMixedCtx); break;
9932	case DBGFEVENT_EXIT_RDPMC: VBOXVMM_EXIT_RDPMC(pVCpu, pMixedCtx); break;
9933	case DBGFEVENT_EXIT_RDTSC: VBOXVMM_EXIT_RDTSC(pVCpu, pMixedCtx); break;
9934	case DBGFEVENT_EXIT_RSM: VBOXVMM_EXIT_RSM(pVCpu, pMixedCtx); break;
9935	case DBGFEVENT_EXIT_CRX_READ: VBOXVMM_EXIT_CRX_READ(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
9936	case DBGFEVENT_EXIT_CRX_WRITE: VBOXVMM_EXIT_CRX_WRITE(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
9937	case DBGFEVENT_EXIT_DRX_READ: VBOXVMM_EXIT_DRX_READ(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
9938	case DBGFEVENT_EXIT_DRX_WRITE: VBOXVMM_EXIT_DRX_WRITE(pVCpu, pMixedCtx, (uint8_t)uEventArg); break;
9939	case DBGFEVENT_EXIT_RDMSR: VBOXVMM_EXIT_RDMSR(pVCpu, pMixedCtx, pMixedCtx->ecx); break;
9940	case DBGFEVENT_EXIT_WRMSR: VBOXVMM_EXIT_WRMSR(pVCpu, pMixedCtx, pMixedCtx->ecx,
9941	RT_MAKE_U64(pMixedCtx->eax, pMixedCtx->edx)); break;
9942	case DBGFEVENT_EXIT_MWAIT: VBOXVMM_EXIT_MWAIT(pVCpu, pMixedCtx); break;
9943	case DBGFEVENT_EXIT_MONITOR: VBOXVMM_EXIT_MONITOR(pVCpu, pMixedCtx); break;
9944	case DBGFEVENT_EXIT_PAUSE: VBOXVMM_EXIT_PAUSE(pVCpu, pMixedCtx); break;
9945	case DBGFEVENT_EXIT_SGDT: VBOXVMM_EXIT_SGDT(pVCpu, pMixedCtx); break;
9946	case DBGFEVENT_EXIT_SIDT: VBOXVMM_EXIT_SIDT(pVCpu, pMixedCtx); break;
9947	case DBGFEVENT_EXIT_LGDT: VBOXVMM_EXIT_LGDT(pVCpu, pMixedCtx); break;
9948	case DBGFEVENT_EXIT_LIDT: VBOXVMM_EXIT_LIDT(pVCpu, pMixedCtx); break;
9949	case DBGFEVENT_EXIT_SLDT: VBOXVMM_EXIT_SLDT(pVCpu, pMixedCtx); break;
9950	case DBGFEVENT_EXIT_STR: VBOXVMM_EXIT_STR(pVCpu, pMixedCtx); break;
9951	case DBGFEVENT_EXIT_LLDT: VBOXVMM_EXIT_LLDT(pVCpu, pMixedCtx); break;
9952	case DBGFEVENT_EXIT_LTR: VBOXVMM_EXIT_LTR(pVCpu, pMixedCtx); break;
9953	case DBGFEVENT_EXIT_RDTSCP: VBOXVMM_EXIT_RDTSCP(pVCpu, pMixedCtx); break;
9954	case DBGFEVENT_EXIT_WBINVD: VBOXVMM_EXIT_WBINVD(pVCpu, pMixedCtx); break;
9955	case DBGFEVENT_EXIT_XSETBV: VBOXVMM_EXIT_XSETBV(pVCpu, pMixedCtx); break;
9956	case DBGFEVENT_EXIT_RDRAND: VBOXVMM_EXIT_RDRAND(pVCpu, pMixedCtx); break;
9957	case DBGFEVENT_EXIT_RDSEED: VBOXVMM_EXIT_RDSEED(pVCpu, pMixedCtx); break;
9958	case DBGFEVENT_EXIT_XSAVES: VBOXVMM_EXIT_XSAVES(pVCpu, pMixedCtx); break;
9959	case DBGFEVENT_EXIT_XRSTORS: VBOXVMM_EXIT_XRSTORS(pVCpu, pMixedCtx); break;
9960	case DBGFEVENT_EXIT_VMM_CALL: VBOXVMM_EXIT_VMM_CALL(pVCpu, pMixedCtx); break;
9961	case DBGFEVENT_EXIT_VMX_VMCLEAR: VBOXVMM_EXIT_VMX_VMCLEAR(pVCpu, pMixedCtx); break;
9962	case DBGFEVENT_EXIT_VMX_VMLAUNCH: VBOXVMM_EXIT_VMX_VMLAUNCH(pVCpu, pMixedCtx); break;
9963	case DBGFEVENT_EXIT_VMX_VMPTRLD: VBOXVMM_EXIT_VMX_VMPTRLD(pVCpu, pMixedCtx); break;
9964	case DBGFEVENT_EXIT_VMX_VMPTRST: VBOXVMM_EXIT_VMX_VMPTRST(pVCpu, pMixedCtx); break;
9965	case DBGFEVENT_EXIT_VMX_VMREAD: VBOXVMM_EXIT_VMX_VMREAD(pVCpu, pMixedCtx); break;
9966	case DBGFEVENT_EXIT_VMX_VMRESUME: VBOXVMM_EXIT_VMX_VMRESUME(pVCpu, pMixedCtx); break;
9967	case DBGFEVENT_EXIT_VMX_VMWRITE: VBOXVMM_EXIT_VMX_VMWRITE(pVCpu, pMixedCtx); break;
9968	case DBGFEVENT_EXIT_VMX_VMXOFF: VBOXVMM_EXIT_VMX_VMXOFF(pVCpu, pMixedCtx); break;
9969	case DBGFEVENT_EXIT_VMX_VMXON: VBOXVMM_EXIT_VMX_VMXON(pVCpu, pMixedCtx); break;
9970	case DBGFEVENT_EXIT_VMX_INVEPT: VBOXVMM_EXIT_VMX_INVEPT(pVCpu, pMixedCtx); break;
9971	case DBGFEVENT_EXIT_VMX_INVVPID: VBOXVMM_EXIT_VMX_INVVPID(pVCpu, pMixedCtx); break;
9972	case DBGFEVENT_EXIT_VMX_INVPCID: VBOXVMM_EXIT_VMX_INVPCID(pVCpu, pMixedCtx); break;
9973	case DBGFEVENT_EXIT_VMX_VMFUNC: VBOXVMM_EXIT_VMX_VMFUNC(pVCpu, pMixedCtx); break;
9974	case DBGFEVENT_EXIT_VMX_EPT_MISCONFIG: VBOXVMM_EXIT_VMX_EPT_MISCONFIG(pVCpu, pMixedCtx); break;
9975	case DBGFEVENT_EXIT_VMX_EPT_VIOLATION: VBOXVMM_EXIT_VMX_EPT_VIOLATION(pVCpu, pMixedCtx); break;
9976	case DBGFEVENT_EXIT_VMX_VAPIC_ACCESS: VBOXVMM_EXIT_VMX_VAPIC_ACCESS(pVCpu, pMixedCtx); break;
9977	case DBGFEVENT_EXIT_VMX_VAPIC_WRITE: VBOXVMM_EXIT_VMX_VAPIC_WRITE(pVCpu, pMixedCtx); break;
9978	default: AssertMsgFailed(("enmEvent2=%d uExitReason=%d\n", enmEvent2, uExitReason)); break;
9979	}
9980	}
9981
9982	/*
9983	* Fire of the DBGF event, if enabled (our check here is just a quick one,
9984	* the DBGF call will do a full check).
9985	*
9986	* Note! DBGF sets DBGFEVENT_INTERRUPT_SOFTWARE in the bitmap.
9987	* Note! If we have to events, we prioritize the first, i.e. the instruction
9988	* one, in order to avoid event nesting.
9989	*/
9990	if ( enmEvent1 != DBGFEVENT_END
9991	&& DBGF_IS_EVENT_ENABLED(pVM, enmEvent1))
9992	{
9993	VBOXSTRICTRC rcStrict = DBGFEventGenericWithArg(pVM, pVCpu, enmEvent1, uEventArg, DBGFEVENTCTX_HM);
9994	if (rcStrict != VINF_SUCCESS)
9995	return rcStrict;
9996	}
9997	else if ( enmEvent2 != DBGFEVENT_END
9998	&& DBGF_IS_EVENT_ENABLED(pVM, enmEvent2))
9999	{
10000	VBOXSTRICTRC rcStrict = DBGFEventGenericWithArg(pVM, pVCpu, enmEvent2, uEventArg, DBGFEVENTCTX_HM);
10001	if (rcStrict != VINF_SUCCESS)
10002	return rcStrict;
10003	}
10004
10005	return VINF_SUCCESS;
10006	}
10007
10008
10009	/**
10010	* Single-stepping VM-exit filtering.
10011	*
10012	* This is preprocessing the VM-exits and deciding whether we've gotten far
10013	* enough to return VINF_EM_DBG_STEPPED already. If not, normal VM-exit
10014	* handling is performed.
10015	*
10016	* @returns Strict VBox status code (i.e. informational status codes too).
10017	* @param pVM The cross context VM structure.
10018	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
10019	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
10020	* out-of-sync. Make sure to update the required
10021	* fields before using them.
10022	* @param pVmxTransient Pointer to the VMX-transient structure.
10023	* @param uExitReason The VM-exit reason.
10024	* @param pDbgState The debug state.
10025	*/
10026	DECLINLINE(VBOXSTRICTRC) hmR0VmxRunDebugHandleExit(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient,
10027	uint32_t uExitReason, PVMXRUNDBGSTATE pDbgState)
10028	{
10029	/*
10030	* Expensive (saves context) generic dtrace VM-exit probe.
10031	*/
10032	if (!VBOXVMM_R0_HMVMX_VMEXIT_ENABLED())
10033	{ /* more likely */ }
10034	else
10035	{
10036	hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
10037	hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
10038	VBOXVMM_R0_HMVMX_VMEXIT(pVCpu, pMixedCtx, pVmxTransient->uExitReason, pVmxTransient->uExitQualification);
10039	}
10040
10041	/*
10042	* Check for host NMI, just to get that out of the way.
10043	*/
10044	if (uExitReason != VMX_EXIT_XCPT_OR_NMI)
10045	{ /* normally likely */ }
10046	else
10047	{
10048	int rc2 = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
10049	AssertRCReturn(rc2, rc2);
10050	uint32_t uIntType = VMX_EXIT_INTERRUPTION_INFO_TYPE(pVmxTransient->uExitIntInfo);
10051	if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI)
10052	return hmR0VmxExitXcptOrNmi(pVCpu, pMixedCtx, pVmxTransient);
10053	}
10054
10055	/*
10056	* Check for single stepping event if we're stepping.
10057	*/
10058	if (pVCpu->hm.s.fSingleInstruction)
10059	{
10060	switch (uExitReason)
10061	{
10062	case VMX_EXIT_MTF:
10063	return hmR0VmxExitMtf(pVCpu, pMixedCtx, pVmxTransient);
10064
10065	/* Various events: */
10066	case VMX_EXIT_XCPT_OR_NMI:
10067	case VMX_EXIT_EXT_INT:
10068	case VMX_EXIT_TRIPLE_FAULT:
10069	case VMX_EXIT_INT_WINDOW:
10070	case VMX_EXIT_NMI_WINDOW:
10071	case VMX_EXIT_TASK_SWITCH:
10072	case VMX_EXIT_TPR_BELOW_THRESHOLD:
10073	case VMX_EXIT_APIC_ACCESS:
10074	case VMX_EXIT_EPT_VIOLATION:
10075	case VMX_EXIT_EPT_MISCONFIG:
10076	case VMX_EXIT_PREEMPT_TIMER:
10077
10078	/* Instruction specific VM-exits: */
10079	case VMX_EXIT_CPUID:
10080	case VMX_EXIT_GETSEC:
10081	case VMX_EXIT_HLT:
10082	case VMX_EXIT_INVD:
10083	case VMX_EXIT_INVLPG:
10084	case VMX_EXIT_RDPMC:
10085	case VMX_EXIT_RDTSC:
10086	case VMX_EXIT_RSM:
10087	case VMX_EXIT_VMCALL:
10088	case VMX_EXIT_VMCLEAR:
10089	case VMX_EXIT_VMLAUNCH:
10090	case VMX_EXIT_VMPTRLD:
10091	case VMX_EXIT_VMPTRST:
10092	case VMX_EXIT_VMREAD:
10093	case VMX_EXIT_VMRESUME:
10094	case VMX_EXIT_VMWRITE:
10095	case VMX_EXIT_VMXOFF:
10096	case VMX_EXIT_VMXON:
10097	case VMX_EXIT_MOV_CRX:
10098	case VMX_EXIT_MOV_DRX:
10099	case VMX_EXIT_IO_INSTR:
10100	case VMX_EXIT_RDMSR:
10101	case VMX_EXIT_WRMSR:
10102	case VMX_EXIT_MWAIT:
10103	case VMX_EXIT_MONITOR:
10104	case VMX_EXIT_PAUSE:
10105	case VMX_EXIT_XDTR_ACCESS:
10106	case VMX_EXIT_TR_ACCESS:
10107	case VMX_EXIT_INVEPT:
10108	case VMX_EXIT_RDTSCP:
10109	case VMX_EXIT_INVVPID:
10110	case VMX_EXIT_WBINVD:
10111	case VMX_EXIT_XSETBV:
10112	case VMX_EXIT_RDRAND:
10113	case VMX_EXIT_INVPCID:
10114	case VMX_EXIT_VMFUNC:
10115	case VMX_EXIT_RDSEED:
10116	case VMX_EXIT_XSAVES:
10117	case VMX_EXIT_XRSTORS:
10118	{
10119	int rc2 = hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
10120	rc2 \|= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
10121	AssertRCReturn(rc2, rc2);
10122	if ( pMixedCtx->rip != pDbgState->uRipStart
10123	\|\| pMixedCtx->cs.Sel != pDbgState->uCsStart)
10124	return VINF_EM_DBG_STEPPED;
10125	break;
10126	}
10127
10128	/* Errors and unexpected events: */
10129	case VMX_EXIT_INIT_SIGNAL:
10130	case VMX_EXIT_SIPI:
10131	case VMX_EXIT_IO_SMI:
10132	case VMX_EXIT_SMI:
10133	case VMX_EXIT_ERR_INVALID_GUEST_STATE:
10134	case VMX_EXIT_ERR_MSR_LOAD:
10135	case VMX_EXIT_ERR_MACHINE_CHECK:
10136	case VMX_EXIT_APIC_WRITE: /* Some talk about this being fault like, so I guess we must process it? */
10137	break;
10138
10139	default:
10140	AssertMsgFailed(("Unexpected VM-exit=%#x\n", uExitReason));
10141	break;
10142	}
10143	}
10144
10145	/*
10146	* Check for debugger event breakpoints and dtrace probes.
10147	*/
10148	if ( uExitReason < RT_ELEMENTS(pDbgState->bmExitsToCheck) * 32U
10149	&& ASMBitTest(pDbgState->bmExitsToCheck, uExitReason) )
10150	{
10151	VBOXSTRICTRC rcStrict = hmR0VmxHandleExitDtraceEvents(pVM, pVCpu, pMixedCtx, pVmxTransient, uExitReason);
10152	if (rcStrict != VINF_SUCCESS)
10153	return rcStrict;
10154	}
10155
10156	/*
10157	* Normal processing.
10158	*/
10159	#ifdef HMVMX_USE_FUNCTION_TABLE
10160	return g_apfnVMExitHandlers[uExitReason](pVCpu, pMixedCtx, pVmxTransient);
10161	#else
10162	return hmR0VmxHandleExit(pVCpu, pMixedCtx, pVmxTransient, uExitReason);
10163	#endif
10164	}
10165
10166
10167	/**
10168	* Single steps guest code using VT-x.
10169	*
10170	* @returns Strict VBox status code (i.e. informational status codes too).
10171	* @param pVM The cross context VM structure.
10172	* @param pVCpu The cross context virtual CPU structure.
10173	* @param pCtx Pointer to the guest-CPU context.
10174	*
10175	* @note Mostly the same as hmR0VmxRunGuestCodeNormal().
10176	*/
10177	static VBOXSTRICTRC hmR0VmxRunGuestCodeDebug(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
10178	{
10179	VMXTRANSIENT VmxTransient;
10180	VmxTransient.fUpdateTscOffsettingAndPreemptTimer = true;
10181
10182	/* Set HMCPU indicators. */
10183	bool const fSavedSingleInstruction = pVCpu->hm.s.fSingleInstruction;
10184	pVCpu->hm.s.fSingleInstruction = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
10185	pVCpu->hm.s.fDebugWantRdTscExit = false;
10186	pVCpu->hm.s.fUsingDebugLoop = true;
10187
10188	/* State we keep to help modify and later restore the VMCS fields we alter, and for detecting steps. */
10189	VMXRUNDBGSTATE DbgState;
10190	hmR0VmxRunDebugStateInit(pVCpu, pCtx, &DbgState);
10191	hmR0VmxPreRunGuestDebugStateUpdate(pVM, pVCpu, pCtx, &DbgState, &VmxTransient);
10192
10193	/*
10194	* The loop.
10195	*/
10196	VBOXSTRICTRC rcStrict = VERR_INTERNAL_ERROR_5;
10197	for (uint32_t cLoops = 0; ; cLoops++)
10198	{
10199	Assert(!HMR0SuspendPending());
10200	HMVMX_ASSERT_CPU_SAFE();
10201	bool fStepping = pVCpu->hm.s.fSingleInstruction;
10202
10203	/*
10204	* Preparatory work for running guest code, this may force us to return
10205	* to ring-3. This bugger disables interrupts on VINF_SUCCESS!
10206	*/
10207	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
10208	hmR0VmxPreRunGuestDebugStateApply(pVCpu, &DbgState); /* Set up execute controls the next to can respond to. */
10209	rcStrict = hmR0VmxPreRunGuest(pVM, pVCpu, pCtx, &VmxTransient, fStepping);
10210	if (rcStrict != VINF_SUCCESS)
10211	break;
10212
10213	hmR0VmxPreRunGuestCommitted(pVM, pVCpu, pCtx, &VmxTransient);
10214	hmR0VmxPreRunGuestDebugStateApply(pVCpu, &DbgState); /* Override any obnoxious code in the above two calls. */
10215
10216	/*
10217	* Now we can run the guest code.
10218	*/
10219	int rcRun = hmR0VmxRunGuest(pVM, pVCpu, pCtx);
10220
10221	/* The guest-CPU context is now outdated, 'pCtx' is to be treated as 'pMixedCtx' from this point on!!! */
10222
10223	/*
10224	* Restore any residual host-state and save any bits shared between host
10225	* and guest into the guest-CPU state. Re-enables interrupts!
10226	*/
10227	hmR0VmxPostRunGuest(pVM, pVCpu, pCtx, &VmxTransient, rcRun);
10228
10229	/* Check for errors with running the VM (VMLAUNCH/VMRESUME). */
10230	if (RT_SUCCESS(rcRun))
10231	{ /* very likely */ }
10232	else
10233	{
10234	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
10235	hmR0VmxReportWorldSwitchError(pVM, pVCpu, rcRun, pCtx, &VmxTransient);
10236	return rcRun;
10237	}
10238
10239	/* Profile the VM-exit. */
10240	AssertMsg(VmxTransient.uExitReason <= VMX_EXIT_MAX, ("%#x\n", VmxTransient.uExitReason));
10241	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll);
10242	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[VmxTransient.uExitReason & MASK_EXITREASON_STAT]);
10243	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
10244	HMVMX_START_EXIT_DISPATCH_PROF();
10245
10246	VBOXVMM_R0_HMVMX_VMEXIT_NOCTX(pVCpu, pCtx, VmxTransient.uExitReason);
10247
10248	/*
10249	* Handle the VM-exit - we quit earlier on certain VM-exits, see hmR0VmxHandleExitDebug().
10250	*/
10251	rcStrict = hmR0VmxRunDebugHandleExit(pVM, pVCpu, pCtx, &VmxTransient, VmxTransient.uExitReason, &DbgState);
10252	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
10253	if (rcStrict != VINF_SUCCESS)
10254	break;
10255	if (cLoops > pVM->hm.s.cMaxResumeLoops)
10256	{
10257	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
10258	rcStrict = VINF_EM_RAW_INTERRUPT;
10259	break;
10260	}
10261
10262	/*
10263	* Stepping: Did the RIP change, if so, consider it a single step.
10264	* Otherwise, make sure one of the TFs gets set.
10265	*/
10266	if (fStepping)
10267	{
10268	int rc2 = hmR0VmxSaveGuestRip(pVCpu, pCtx);
10269	rc2 \|= hmR0VmxSaveGuestSegmentRegs(pVCpu, pCtx);
10270	AssertRCReturn(rc2, rc2);
10271	if ( pCtx->rip != DbgState.uRipStart
10272	\|\| pCtx->cs.Sel != DbgState.uCsStart)
10273	{
10274	rcStrict = VINF_EM_DBG_STEPPED;
10275	break;
10276	}
10277	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
10278	}
10279
10280	/*
10281	* Update when dtrace settings changes (DBGF kicks us, so no need to check).
10282	*/
10283	if (VBOXVMM_GET_SETTINGS_SEQ_NO() != DbgState.uDtraceSettingsSeqNo)
10284	hmR0VmxPreRunGuestDebugStateUpdate(pVM, pVCpu, pCtx, &DbgState, &VmxTransient);
10285	}
10286
10287	/*
10288	* Clear the X86_EFL_TF if necessary.
10289	*/
10290	if (pVCpu->hm.s.fClearTrapFlag)
10291	{
10292	int rc2 = hmR0VmxSaveGuestRflags(pVCpu, pCtx);
10293	AssertRCReturn(rc2, rc2);
10294	pVCpu->hm.s.fClearTrapFlag = false;
10295	pCtx->eflags.Bits.u1TF = 0;
10296	}
10297	/** @todo there seems to be issues with the resume flag when the monitor trap
10298	* flag is pending without being used. Seen early in bios init when
10299	* accessing APIC page in protected mode. */
10300
10301	/*
10302	* Restore VM-exit control settings as we may not reenter this function the
10303	* next time around.
10304	*/
10305	rcStrict = hmR0VmxRunDebugStateRevert(pVCpu, &DbgState, rcStrict);
10306
10307	/* Restore HMCPU indicators. */
10308	pVCpu->hm.s.fUsingDebugLoop = false;
10309	pVCpu->hm.s.fDebugWantRdTscExit = false;
10310	pVCpu->hm.s.fSingleInstruction = fSavedSingleInstruction;
10311
10312	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
10313	return rcStrict;
10314	}
10315
10316
10317	/** @} */
10318
10319
10320	/**
10321	* Checks if any expensive dtrace probes are enabled and we should go to the
10322	* debug loop.
10323	*
10324	* @returns true if we should use debug loop, false if not.
10325	*/
10326	static bool hmR0VmxAnyExpensiveProbesEnabled(void)
10327	{
10328	/* It's probably faster to OR the raw 32-bit counter variables together.
10329	Since the variables are in an array and the probes are next to one
10330	another (more or less), we have good locality. So, better read
10331	eight-nine cache lines ever time and only have one conditional, than
10332	128+ conditionals, right? */
10333	return ( VBOXVMM_R0_HMVMX_VMEXIT_ENABLED_RAW() /* expensive too due to context */
10334	\| VBOXVMM_XCPT_DE_ENABLED_RAW()
10335	\| VBOXVMM_XCPT_DB_ENABLED_RAW()
10336	\| VBOXVMM_XCPT_BP_ENABLED_RAW()
10337	\| VBOXVMM_XCPT_OF_ENABLED_RAW()
10338	\| VBOXVMM_XCPT_BR_ENABLED_RAW()
10339	\| VBOXVMM_XCPT_UD_ENABLED_RAW()
10340	\| VBOXVMM_XCPT_NM_ENABLED_RAW()
10341	\| VBOXVMM_XCPT_DF_ENABLED_RAW()
10342	\| VBOXVMM_XCPT_TS_ENABLED_RAW()
10343	\| VBOXVMM_XCPT_NP_ENABLED_RAW()
10344	\| VBOXVMM_XCPT_SS_ENABLED_RAW()
10345	\| VBOXVMM_XCPT_GP_ENABLED_RAW()
10346	\| VBOXVMM_XCPT_PF_ENABLED_RAW()
10347	\| VBOXVMM_XCPT_MF_ENABLED_RAW()
10348	\| VBOXVMM_XCPT_AC_ENABLED_RAW()
10349	\| VBOXVMM_XCPT_XF_ENABLED_RAW()
10350	\| VBOXVMM_XCPT_VE_ENABLED_RAW()
10351	\| VBOXVMM_XCPT_SX_ENABLED_RAW()
10352	\| VBOXVMM_INT_SOFTWARE_ENABLED_RAW()
10353	\| VBOXVMM_INT_HARDWARE_ENABLED_RAW()
10354	) != 0
10355	\|\| ( VBOXVMM_INSTR_HALT_ENABLED_RAW()
10356	\| VBOXVMM_INSTR_MWAIT_ENABLED_RAW()
10357	\| VBOXVMM_INSTR_MONITOR_ENABLED_RAW()
10358	\| VBOXVMM_INSTR_CPUID_ENABLED_RAW()
10359	\| VBOXVMM_INSTR_INVD_ENABLED_RAW()
10360	\| VBOXVMM_INSTR_WBINVD_ENABLED_RAW()
10361	\| VBOXVMM_INSTR_INVLPG_ENABLED_RAW()
10362	\| VBOXVMM_INSTR_RDTSC_ENABLED_RAW()
10363	\| VBOXVMM_INSTR_RDTSCP_ENABLED_RAW()
10364	\| VBOXVMM_INSTR_RDPMC_ENABLED_RAW()
10365	\| VBOXVMM_INSTR_RDMSR_ENABLED_RAW()
10366	\| VBOXVMM_INSTR_WRMSR_ENABLED_RAW()
10367	\| VBOXVMM_INSTR_CRX_READ_ENABLED_RAW()
10368	\| VBOXVMM_INSTR_CRX_WRITE_ENABLED_RAW()
10369	\| VBOXVMM_INSTR_DRX_READ_ENABLED_RAW()
10370	\| VBOXVMM_INSTR_DRX_WRITE_ENABLED_RAW()
10371	\| VBOXVMM_INSTR_PAUSE_ENABLED_RAW()
10372	\| VBOXVMM_INSTR_XSETBV_ENABLED_RAW()
10373	\| VBOXVMM_INSTR_SIDT_ENABLED_RAW()
10374	\| VBOXVMM_INSTR_LIDT_ENABLED_RAW()
10375	\| VBOXVMM_INSTR_SGDT_ENABLED_RAW()
10376	\| VBOXVMM_INSTR_LGDT_ENABLED_RAW()
10377	\| VBOXVMM_INSTR_SLDT_ENABLED_RAW()
10378	\| VBOXVMM_INSTR_LLDT_ENABLED_RAW()
10379	\| VBOXVMM_INSTR_STR_ENABLED_RAW()
10380	\| VBOXVMM_INSTR_LTR_ENABLED_RAW()
10381	\| VBOXVMM_INSTR_GETSEC_ENABLED_RAW()
10382	\| VBOXVMM_INSTR_RSM_ENABLED_RAW()
10383	\| VBOXVMM_INSTR_RDRAND_ENABLED_RAW()
10384	\| VBOXVMM_INSTR_RDSEED_ENABLED_RAW()
10385	\| VBOXVMM_INSTR_XSAVES_ENABLED_RAW()
10386	\| VBOXVMM_INSTR_XRSTORS_ENABLED_RAW()
10387	\| VBOXVMM_INSTR_VMM_CALL_ENABLED_RAW()
10388	\| VBOXVMM_INSTR_VMX_VMCLEAR_ENABLED_RAW()
10389	\| VBOXVMM_INSTR_VMX_VMLAUNCH_ENABLED_RAW()
10390	\| VBOXVMM_INSTR_VMX_VMPTRLD_ENABLED_RAW()
10391	\| VBOXVMM_INSTR_VMX_VMPTRST_ENABLED_RAW()
10392	\| VBOXVMM_INSTR_VMX_VMREAD_ENABLED_RAW()
10393	\| VBOXVMM_INSTR_VMX_VMRESUME_ENABLED_RAW()
10394	\| VBOXVMM_INSTR_VMX_VMWRITE_ENABLED_RAW()
10395	\| VBOXVMM_INSTR_VMX_VMXOFF_ENABLED_RAW()
10396	\| VBOXVMM_INSTR_VMX_VMXON_ENABLED_RAW()
10397	\| VBOXVMM_INSTR_VMX_VMFUNC_ENABLED_RAW()
10398	\| VBOXVMM_INSTR_VMX_INVEPT_ENABLED_RAW()
10399	\| VBOXVMM_INSTR_VMX_INVVPID_ENABLED_RAW()
10400	\| VBOXVMM_INSTR_VMX_INVPCID_ENABLED_RAW()
10401	) != 0
10402	\|\| ( VBOXVMM_EXIT_TASK_SWITCH_ENABLED_RAW()
10403	\| VBOXVMM_EXIT_HALT_ENABLED_RAW()
10404	\| VBOXVMM_EXIT_MWAIT_ENABLED_RAW()
10405	\| VBOXVMM_EXIT_MONITOR_ENABLED_RAW()
10406	\| VBOXVMM_EXIT_CPUID_ENABLED_RAW()
10407	\| VBOXVMM_EXIT_INVD_ENABLED_RAW()
10408	\| VBOXVMM_EXIT_WBINVD_ENABLED_RAW()
10409	\| VBOXVMM_EXIT_INVLPG_ENABLED_RAW()
10410	\| VBOXVMM_EXIT_RDTSC_ENABLED_RAW()
10411	\| VBOXVMM_EXIT_RDTSCP_ENABLED_RAW()
10412	\| VBOXVMM_EXIT_RDPMC_ENABLED_RAW()
10413	\| VBOXVMM_EXIT_RDMSR_ENABLED_RAW()
10414	\| VBOXVMM_EXIT_WRMSR_ENABLED_RAW()
10415	\| VBOXVMM_EXIT_CRX_READ_ENABLED_RAW()
10416	\| VBOXVMM_EXIT_CRX_WRITE_ENABLED_RAW()
10417	\| VBOXVMM_EXIT_DRX_READ_ENABLED_RAW()
10418	\| VBOXVMM_EXIT_DRX_WRITE_ENABLED_RAW()
10419	\| VBOXVMM_EXIT_PAUSE_ENABLED_RAW()
10420	\| VBOXVMM_EXIT_XSETBV_ENABLED_RAW()
10421	\| VBOXVMM_EXIT_SIDT_ENABLED_RAW()
10422	\| VBOXVMM_EXIT_LIDT_ENABLED_RAW()
10423	\| VBOXVMM_EXIT_SGDT_ENABLED_RAW()
10424	\| VBOXVMM_EXIT_LGDT_ENABLED_RAW()
10425	\| VBOXVMM_EXIT_SLDT_ENABLED_RAW()
10426	\| VBOXVMM_EXIT_LLDT_ENABLED_RAW()
10427	\| VBOXVMM_EXIT_STR_ENABLED_RAW()
10428	\| VBOXVMM_EXIT_LTR_ENABLED_RAW()
10429	\| VBOXVMM_EXIT_GETSEC_ENABLED_RAW()
10430	\| VBOXVMM_EXIT_RSM_ENABLED_RAW()
10431	\| VBOXVMM_EXIT_RDRAND_ENABLED_RAW()
10432	\| VBOXVMM_EXIT_RDSEED_ENABLED_RAW()
10433	\| VBOXVMM_EXIT_XSAVES_ENABLED_RAW()
10434	\| VBOXVMM_EXIT_XRSTORS_ENABLED_RAW()
10435	\| VBOXVMM_EXIT_VMM_CALL_ENABLED_RAW()
10436	\| VBOXVMM_EXIT_VMX_VMCLEAR_ENABLED_RAW()
10437	\| VBOXVMM_EXIT_VMX_VMLAUNCH_ENABLED_RAW()
10438	\| VBOXVMM_EXIT_VMX_VMPTRLD_ENABLED_RAW()
10439	\| VBOXVMM_EXIT_VMX_VMPTRST_ENABLED_RAW()
10440	\| VBOXVMM_EXIT_VMX_VMREAD_ENABLED_RAW()
10441	\| VBOXVMM_EXIT_VMX_VMRESUME_ENABLED_RAW()
10442	\| VBOXVMM_EXIT_VMX_VMWRITE_ENABLED_RAW()
10443	\| VBOXVMM_EXIT_VMX_VMXOFF_ENABLED_RAW()
10444	\| VBOXVMM_EXIT_VMX_VMXON_ENABLED_RAW()
10445	\| VBOXVMM_EXIT_VMX_VMFUNC_ENABLED_RAW()
10446	\| VBOXVMM_EXIT_VMX_INVEPT_ENABLED_RAW()
10447	\| VBOXVMM_EXIT_VMX_INVVPID_ENABLED_RAW()
10448	\| VBOXVMM_EXIT_VMX_INVPCID_ENABLED_RAW()
10449	\| VBOXVMM_EXIT_VMX_EPT_VIOLATION_ENABLED_RAW()
10450	\| VBOXVMM_EXIT_VMX_EPT_MISCONFIG_ENABLED_RAW()
10451	\| VBOXVMM_EXIT_VMX_VAPIC_ACCESS_ENABLED_RAW()
10452	\| VBOXVMM_EXIT_VMX_VAPIC_WRITE_ENABLED_RAW()
10453	) != 0;
10454	}
10455
10456
10457	/**
10458	* Runs the guest code using VT-x.
10459	*
10460	* @returns Strict VBox status code (i.e. informational status codes too).
10461	* @param pVM The cross context VM structure.
10462	* @param pVCpu The cross context virtual CPU structure.
10463	* @param pCtx Pointer to the guest-CPU context.
10464	*/
10465	VMMR0DECL(VBOXSTRICTRC) VMXR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
10466	{
10467	Assert(VMMRZCallRing3IsEnabled(pVCpu));
10468	Assert(HMVMXCPU_GST_VALUE(pVCpu) == HMVMX_UPDATED_GUEST_ALL);
10469	HMVMX_ASSERT_PREEMPT_SAFE();
10470
10471	VMMRZCallRing3SetNotification(pVCpu, hmR0VmxCallRing3Callback, pCtx);
10472
10473	VBOXSTRICTRC rcStrict;
10474	if ( !pVCpu->hm.s.fUseDebugLoop
10475	&& (!VBOXVMM_ANY_PROBES_ENABLED() \|\| !hmR0VmxAnyExpensiveProbesEnabled())
10476	&& !DBGFIsStepping(pVCpu)
10477	&& !pVM->dbgf.ro.cEnabledInt3Breakpoints)
10478	rcStrict = hmR0VmxRunGuestCodeNormal(pVM, pVCpu, pCtx);
10479	else
10480	rcStrict = hmR0VmxRunGuestCodeDebug(pVM, pVCpu, pCtx);
10481
10482	if (rcStrict == VERR_EM_INTERPRETER)
10483	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
10484	else if (rcStrict == VINF_EM_RESET)
10485	rcStrict = VINF_EM_TRIPLE_FAULT;
10486
10487	int rc2 = hmR0VmxExitToRing3(pVM, pVCpu, pCtx, rcStrict);
10488	if (RT_FAILURE(rc2))
10489	{
10490	pVCpu->hm.s.u32HMError = (uint32_t)VBOXSTRICTRC_VAL(rcStrict);
10491	rcStrict = rc2;
10492	}
10493	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
10494	return rcStrict;
10495	}
10496
10497
10498	#ifndef HMVMX_USE_FUNCTION_TABLE
10499	DECLINLINE(VBOXSTRICTRC) hmR0VmxHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient, uint32_t rcReason)
10500	{
10501	# ifdef DEBUG_ramshankar
10502	# define RETURN_EXIT_CALL(a_CallExpr) \
10503	do { \
10504	int rc2 = hmR0VmxSaveGuestState(pVCpu, pMixedCtx); AssertRC(rc2); \
10505	VBOXSTRICTRC rcStrict = a_CallExpr; \
10506	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST); \
10507	return rcStrict; \
10508	} while (0)
10509	# else
10510	# define RETURN_EXIT_CALL(a_CallExpr) return a_CallExpr
10511	# endif
10512	switch (rcReason)
10513	{
10514	case VMX_EXIT_EPT_MISCONFIG: RETURN_EXIT_CALL(hmR0VmxExitEptMisconfig(pVCpu, pMixedCtx, pVmxTransient));
10515	case VMX_EXIT_EPT_VIOLATION: RETURN_EXIT_CALL(hmR0VmxExitEptViolation(pVCpu, pMixedCtx, pVmxTransient));
10516	case VMX_EXIT_IO_INSTR: RETURN_EXIT_CALL(hmR0VmxExitIoInstr(pVCpu, pMixedCtx, pVmxTransient));
10517	case VMX_EXIT_CPUID: RETURN_EXIT_CALL(hmR0VmxExitCpuid(pVCpu, pMixedCtx, pVmxTransient));
10518	case VMX_EXIT_RDTSC: RETURN_EXIT_CALL(hmR0VmxExitRdtsc(pVCpu, pMixedCtx, pVmxTransient));
10519	case VMX_EXIT_RDTSCP: RETURN_EXIT_CALL(hmR0VmxExitRdtscp(pVCpu, pMixedCtx, pVmxTransient));
10520	case VMX_EXIT_APIC_ACCESS: RETURN_EXIT_CALL(hmR0VmxExitApicAccess(pVCpu, pMixedCtx, pVmxTransient));
10521	case VMX_EXIT_XCPT_OR_NMI: RETURN_EXIT_CALL(hmR0VmxExitXcptOrNmi(pVCpu, pMixedCtx, pVmxTransient));
10522	case VMX_EXIT_MOV_CRX: RETURN_EXIT_CALL(hmR0VmxExitMovCRx(pVCpu, pMixedCtx, pVmxTransient));
10523	case VMX_EXIT_EXT_INT: RETURN_EXIT_CALL(hmR0VmxExitExtInt(pVCpu, pMixedCtx, pVmxTransient));
10524	case VMX_EXIT_INT_WINDOW: RETURN_EXIT_CALL(hmR0VmxExitIntWindow(pVCpu, pMixedCtx, pVmxTransient));
10525	case VMX_EXIT_MWAIT: RETURN_EXIT_CALL(hmR0VmxExitMwait(pVCpu, pMixedCtx, pVmxTransient));
10526	case VMX_EXIT_MONITOR: RETURN_EXIT_CALL(hmR0VmxExitMonitor(pVCpu, pMixedCtx, pVmxTransient));
10527	case VMX_EXIT_TASK_SWITCH: RETURN_EXIT_CALL(hmR0VmxExitTaskSwitch(pVCpu, pMixedCtx, pVmxTransient));
10528	case VMX_EXIT_PREEMPT_TIMER: RETURN_EXIT_CALL(hmR0VmxExitPreemptTimer(pVCpu, pMixedCtx, pVmxTransient));
10529	case VMX_EXIT_RDMSR: RETURN_EXIT_CALL(hmR0VmxExitRdmsr(pVCpu, pMixedCtx, pVmxTransient));
10530	case VMX_EXIT_WRMSR: RETURN_EXIT_CALL(hmR0VmxExitWrmsr(pVCpu, pMixedCtx, pVmxTransient));
10531	case VMX_EXIT_MOV_DRX: RETURN_EXIT_CALL(hmR0VmxExitMovDRx(pVCpu, pMixedCtx, pVmxTransient));
10532	case VMX_EXIT_TPR_BELOW_THRESHOLD: RETURN_EXIT_CALL(hmR0VmxExitTprBelowThreshold(pVCpu, pMixedCtx, pVmxTransient));
10533	case VMX_EXIT_HLT: RETURN_EXIT_CALL(hmR0VmxExitHlt(pVCpu, pMixedCtx, pVmxTransient));
10534	case VMX_EXIT_INVD: RETURN_EXIT_CALL(hmR0VmxExitInvd(pVCpu, pMixedCtx, pVmxTransient));
10535	case VMX_EXIT_INVLPG: RETURN_EXIT_CALL(hmR0VmxExitInvlpg(pVCpu, pMixedCtx, pVmxTransient));
10536	case VMX_EXIT_RSM: RETURN_EXIT_CALL(hmR0VmxExitRsm(pVCpu, pMixedCtx, pVmxTransient));
10537	case VMX_EXIT_MTF: RETURN_EXIT_CALL(hmR0VmxExitMtf(pVCpu, pMixedCtx, pVmxTransient));
10538	case VMX_EXIT_PAUSE: RETURN_EXIT_CALL(hmR0VmxExitPause(pVCpu, pMixedCtx, pVmxTransient));
10539	case VMX_EXIT_XDTR_ACCESS: RETURN_EXIT_CALL(hmR0VmxExitXdtrAccess(pVCpu, pMixedCtx, pVmxTransient));
10540	case VMX_EXIT_TR_ACCESS: RETURN_EXIT_CALL(hmR0VmxExitXdtrAccess(pVCpu, pMixedCtx, pVmxTransient));
10541	case VMX_EXIT_WBINVD: RETURN_EXIT_CALL(hmR0VmxExitWbinvd(pVCpu, pMixedCtx, pVmxTransient));
10542	case VMX_EXIT_XSETBV: RETURN_EXIT_CALL(hmR0VmxExitXsetbv(pVCpu, pMixedCtx, pVmxTransient));
10543	case VMX_EXIT_RDRAND: RETURN_EXIT_CALL(hmR0VmxExitRdrand(pVCpu, pMixedCtx, pVmxTransient));
10544	case VMX_EXIT_INVPCID: RETURN_EXIT_CALL(hmR0VmxExitInvpcid(pVCpu, pMixedCtx, pVmxTransient));
10545	case VMX_EXIT_GETSEC: RETURN_EXIT_CALL(hmR0VmxExitGetsec(pVCpu, pMixedCtx, pVmxTransient));
10546	case VMX_EXIT_RDPMC: RETURN_EXIT_CALL(hmR0VmxExitRdpmc(pVCpu, pMixedCtx, pVmxTransient));
10547	case VMX_EXIT_VMCALL: RETURN_EXIT_CALL(hmR0VmxExitVmcall(pVCpu, pMixedCtx, pVmxTransient));
10548
10549	case VMX_EXIT_TRIPLE_FAULT: return hmR0VmxExitTripleFault(pVCpu, pMixedCtx, pVmxTransient);
10550	case VMX_EXIT_NMI_WINDOW: return hmR0VmxExitNmiWindow(pVCpu, pMixedCtx, pVmxTransient);
10551	case VMX_EXIT_INIT_SIGNAL: return hmR0VmxExitInitSignal(pVCpu, pMixedCtx, pVmxTransient);
10552	case VMX_EXIT_SIPI: return hmR0VmxExitSipi(pVCpu, pMixedCtx, pVmxTransient);
10553	case VMX_EXIT_IO_SMI: return hmR0VmxExitIoSmi(pVCpu, pMixedCtx, pVmxTransient);
10554	case VMX_EXIT_SMI: return hmR0VmxExitSmi(pVCpu, pMixedCtx, pVmxTransient);
10555	case VMX_EXIT_ERR_MSR_LOAD: return hmR0VmxExitErrMsrLoad(pVCpu, pMixedCtx, pVmxTransient);
10556	case VMX_EXIT_ERR_INVALID_GUEST_STATE: return hmR0VmxExitErrInvalidGuestState(pVCpu, pMixedCtx, pVmxTransient);
10557	case VMX_EXIT_ERR_MACHINE_CHECK: return hmR0VmxExitErrMachineCheck(pVCpu, pMixedCtx, pVmxTransient);
10558
10559	case VMX_EXIT_VMCLEAR:
10560	case VMX_EXIT_VMLAUNCH:
10561	case VMX_EXIT_VMPTRLD:
10562	case VMX_EXIT_VMPTRST:
10563	case VMX_EXIT_VMREAD:
10564	case VMX_EXIT_VMRESUME:
10565	case VMX_EXIT_VMWRITE:
10566	case VMX_EXIT_VMXOFF:
10567	case VMX_EXIT_VMXON:
10568	case VMX_EXIT_INVEPT:
10569	case VMX_EXIT_INVVPID:
10570	case VMX_EXIT_VMFUNC:
10571	case VMX_EXIT_XSAVES:
10572	case VMX_EXIT_XRSTORS:
10573	return hmR0VmxExitSetPendingXcptUD(pVCpu, pMixedCtx, pVmxTransient);
10574	case VMX_EXIT_ENCLS:
10575	case VMX_EXIT_RDSEED: /* only spurious VM-exits, so undefined */
10576	case VMX_EXIT_PML_FULL:
10577	default:
10578	return hmR0VmxExitErrUndefined(pVCpu, pMixedCtx, pVmxTransient);
10579	}
10580	#undef RETURN_EXIT_CALL
10581	}
10582	#endif /* !HMVMX_USE_FUNCTION_TABLE */
10583
10584
10585	#ifdef VBOX_STRICT
10586	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
10587	# define HMVMX_ASSERT_PREEMPT_CPUID_VAR() \
10588	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
10589
10590	# define HMVMX_ASSERT_PREEMPT_CPUID() \
10591	do { \
10592	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
10593	AssertMsg(idAssertCpu == idAssertCpuNow, ("VMX %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
10594	} while (0)
10595
10596	# define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS() \
10597	do { \
10598	AssertPtr(pVCpu); \
10599	AssertPtr(pMixedCtx); \
10600	AssertPtr(pVmxTransient); \
10601	Assert(pVmxTransient->fVMEntryFailed == false); \
10602	Assert(ASMIntAreEnabled()); \
10603	HMVMX_ASSERT_PREEMPT_SAFE(); \
10604	HMVMX_ASSERT_PREEMPT_CPUID_VAR(); \
10605	Log4Func(("vcpu[%RU32] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v\n", pVCpu->idCpu)); \
10606	HMVMX_ASSERT_PREEMPT_SAFE(); \
10607	if (VMMR0IsLogFlushDisabled(pVCpu)) \
10608	HMVMX_ASSERT_PREEMPT_CPUID(); \
10609	HMVMX_STOP_EXIT_DISPATCH_PROF(); \
10610	} while (0)
10611
10612	# define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS() \
10613	do { \
10614	Log4Func(("\n")); \
10615	} while (0)
10616	#else /* nonstrict builds: */
10617	# define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS() \
10618	do { \
10619	HMVMX_STOP_EXIT_DISPATCH_PROF(); \
10620	NOREF(pVCpu); NOREF(pMixedCtx); NOREF(pVmxTransient); \
10621	} while (0)
10622	# define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS() do { } while (0)
10623	#endif
10624
10625
10626	/**
10627	* Advances the guest RIP by the specified number of bytes.
10628	*
10629	* @param pVCpu The cross context virtual CPU structure.
10630	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
10631	* out-of-sync. Make sure to update the required fields
10632	* before using them.
10633	* @param cbInstr Number of bytes to advance the RIP by.
10634	*
10635	* @remarks No-long-jump zone!!!
10636	*/
10637	DECLINLINE(void) hmR0VmxAdvanceGuestRipBy(PVMCPU pVCpu, PCPUMCTX pMixedCtx, uint32_t cbInstr)
10638	{
10639	/* Advance the RIP. */
10640	pMixedCtx->rip += cbInstr;
10641	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
10642
10643	/* Update interrupt inhibition. */
10644	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
10645	&& pMixedCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
10646	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
10647	}
10648
10649
10650	/**
10651	* Advances the guest RIP after reading it from the VMCS.
10652	*
10653	* @returns VBox status code, no informational status codes.
10654	* @param pVCpu The cross context virtual CPU structure.
10655	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
10656	* out-of-sync. Make sure to update the required fields
10657	* before using them.
10658	* @param pVmxTransient Pointer to the VMX transient structure.
10659	*
10660	* @remarks No-long-jump zone!!!
10661	*/
10662	static int hmR0VmxAdvanceGuestRip(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
10663	{
10664	int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
10665	rc \|= hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
10666	rc \|= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
10667	AssertRCReturn(rc, rc);
10668
10669	hmR0VmxAdvanceGuestRipBy(pVCpu, pMixedCtx, pVmxTransient->cbInstr);
10670
10671	/*
10672	* Deliver a debug exception to the guest if it is single-stepping. Don't directly inject a #DB but use the
10673	* pending debug exception field as it takes care of priority of events.
10674	*
10675	* See Intel spec. 32.2.1 "Debug Exceptions".
10676	*/
10677	if ( !pVCpu->hm.s.fSingleInstruction
10678	&& pMixedCtx->eflags.Bits.u1TF)
10679	hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
10680
10681	return VINF_SUCCESS;
10682	}
10683
10684
10685	/**
10686	* Tries to determine what part of the guest-state VT-x has deemed as invalid
10687	* and update error record fields accordingly.
10688	*
10689	* @return VMX_IGS_* return codes.
10690	* @retval VMX_IGS_REASON_NOT_FOUND if this function could not find anything
10691	* wrong with the guest state.
10692	*
10693	* @param pVM The cross context VM structure.
10694	* @param pVCpu The cross context virtual CPU structure.
10695	* @param pCtx Pointer to the guest-CPU state.
10696	*
10697	* @remarks This function assumes our cache of the VMCS controls
10698	* are valid, i.e. hmR0VmxCheckVmcsCtls() succeeded.
10699	*/
10700	static uint32_t hmR0VmxCheckGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
10701	{
10702	#define HMVMX_ERROR_BREAK(err) { uError = (err); break; }
10703	#define HMVMX_CHECK_BREAK(expr, err) if (!(expr)) { \
10704	uError = (err); \
10705	break; \
10706	} else do { } while (0)
10707
10708	int rc;
10709	uint32_t uError = VMX_IGS_ERROR;
10710	uint32_t u32Val;
10711	bool fUnrestrictedGuest = pVM->hm.s.vmx.fUnrestrictedGuest;
10712
10713	do
10714	{
10715	/*
10716	* CR0.
10717	*/
10718	uint32_t uSetCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
10719	uint32_t uZapCR0 = (uint32_t)(pVM->hm.s.vmx.Msrs.u64Cr0Fixed0 \| pVM->hm.s.vmx.Msrs.u64Cr0Fixed1);
10720	/* Exceptions for unrestricted-guests for fixed CR0 bits (PE, PG).
10721	See Intel spec. 26.3.1 "Checks on Guest Control Registers, Debug Registers and MSRs." */
10722	if (fUnrestrictedGuest)
10723	uSetCR0 &= ~(X86_CR0_PE \| X86_CR0_PG);
10724
10725	uint32_t u32GuestCR0;
10726	rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &u32GuestCR0);
10727	AssertRCBreak(rc);
10728	HMVMX_CHECK_BREAK((u32GuestCR0 & uSetCR0) == uSetCR0, VMX_IGS_CR0_FIXED1);
10729	HMVMX_CHECK_BREAK(!(u32GuestCR0 & ~uZapCR0), VMX_IGS_CR0_FIXED0);
10730	if ( !fUnrestrictedGuest
10731	&& (u32GuestCR0 & X86_CR0_PG)
10732	&& !(u32GuestCR0 & X86_CR0_PE))
10733	{
10734	HMVMX_ERROR_BREAK(VMX_IGS_CR0_PG_PE_COMBO);
10735	}
10736
10737	/*
10738	* CR4.
10739	*/
10740	uint64_t uSetCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 & pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
10741	uint64_t uZapCR4 = (pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 \| pVM->hm.s.vmx.Msrs.u64Cr4Fixed1);
10742
10743	uint32_t u32GuestCR4;
10744	rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR4, &u32GuestCR4);
10745	AssertRCBreak(rc);
10746	HMVMX_CHECK_BREAK((u32GuestCR4 & uSetCR4) == uSetCR4, VMX_IGS_CR4_FIXED1);
10747	HMVMX_CHECK_BREAK(!(u32GuestCR4 & ~uZapCR4), VMX_IGS_CR4_FIXED0);
10748
10749	/*
10750	* IA32_DEBUGCTL MSR.
10751	*/
10752	uint64_t u64Val;
10753	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, &u64Val);
10754	AssertRCBreak(rc);
10755	if ( (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG)
10756	&& (u64Val & 0xfffffe3c)) /* Bits 31:9, bits 5:2 MBZ. */
10757	{
10758	HMVMX_ERROR_BREAK(VMX_IGS_DEBUGCTL_MSR_RESERVED);
10759	}
10760	uint64_t u64DebugCtlMsr = u64Val;
10761
10762	#ifdef VBOX_STRICT
10763	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY, &u32Val);
10764	AssertRCBreak(rc);
10765	Assert(u32Val == pVCpu->hm.s.vmx.u32EntryCtls);
10766	#endif
10767	bool const fLongModeGuest = RT_BOOL(pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
10768
10769	/*
10770	* RIP and RFLAGS.
10771	*/
10772	uint32_t u32Eflags;
10773	#if HC_ARCH_BITS == 64
10774	rc = VMXReadVmcs64(VMX_VMCS_GUEST_RIP, &u64Val);
10775	AssertRCBreak(rc);
10776	/* pCtx->rip can be different than the one in the VMCS (e.g. run guest code and VM-exits that don't update it). */
10777	if ( !fLongModeGuest
10778	\|\| !pCtx->cs.Attr.n.u1Long)
10779	{
10780	HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffff00000000)), VMX_IGS_LONGMODE_RIP_INVALID);
10781	}
10782	/** @todo If the processor supports N < 64 linear-address bits, bits 63:N
10783	* must be identical if the "IA-32e mode guest" VM-entry
10784	* control is 1 and CS.L is 1. No check applies if the
10785	* CPU supports 64 linear-address bits. */
10786
10787	/* Flags in pCtx can be different (real-on-v86 for instance). We are only concerned about the VMCS contents here. */
10788	rc = VMXReadVmcs64(VMX_VMCS_GUEST_RFLAGS, &u64Val);
10789	AssertRCBreak(rc);
10790	HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffffffc08028)), /* Bit 63:22, Bit 15, 5, 3 MBZ. */
10791	VMX_IGS_RFLAGS_RESERVED);
10792	HMVMX_CHECK_BREAK((u64Val & X86_EFL_RA1_MASK), VMX_IGS_RFLAGS_RESERVED1); /* Bit 1 MB1. */
10793	u32Eflags = u64Val;
10794	#else
10795	rc = VMXReadVmcs32(VMX_VMCS_GUEST_RFLAGS, &u32Eflags);
10796	AssertRCBreak(rc);
10797	HMVMX_CHECK_BREAK(!(u32Eflags & 0xffc08028), VMX_IGS_RFLAGS_RESERVED); /* Bit 31:22, Bit 15, 5, 3 MBZ. */
10798	HMVMX_CHECK_BREAK((u32Eflags & X86_EFL_RA1_MASK), VMX_IGS_RFLAGS_RESERVED1); /* Bit 1 MB1. */
10799	#endif
10800
10801	if ( fLongModeGuest
10802	\|\| ( fUnrestrictedGuest
10803	&& !(u32GuestCR0 & X86_CR0_PE)))
10804	{
10805	HMVMX_CHECK_BREAK(!(u32Eflags & X86_EFL_VM), VMX_IGS_RFLAGS_VM_INVALID);
10806	}
10807
10808	uint32_t u32EntryInfo;
10809	rc = VMXReadVmcs32(VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, &u32EntryInfo);
10810	AssertRCBreak(rc);
10811	if ( VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(u32EntryInfo)
10812	&& VMX_ENTRY_INTERRUPTION_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT)
10813	{
10814	HMVMX_CHECK_BREAK(u32Eflags & X86_EFL_IF, VMX_IGS_RFLAGS_IF_INVALID);
10815	}
10816
10817	/*
10818	* 64-bit checks.
10819	*/
10820	#if HC_ARCH_BITS == 64
10821	if (fLongModeGuest)
10822	{
10823	HMVMX_CHECK_BREAK(u32GuestCR0 & X86_CR0_PG, VMX_IGS_CR0_PG_LONGMODE);
10824	HMVMX_CHECK_BREAK(u32GuestCR4 & X86_CR4_PAE, VMX_IGS_CR4_PAE_LONGMODE);
10825	}
10826
10827	if ( !fLongModeGuest
10828	&& (u32GuestCR4 & X86_CR4_PCIDE))
10829	{
10830	HMVMX_ERROR_BREAK(VMX_IGS_CR4_PCIDE);
10831	}
10832
10833	/** @todo CR3 field must be such that bits 63:52 and bits in the range
10834	* 51:32 beyond the processor's physical-address width are 0. */
10835
10836	if ( (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG)
10837	&& (pCtx->dr[7] & X86_DR7_MBZ_MASK))
10838	{
10839	HMVMX_ERROR_BREAK(VMX_IGS_DR7_RESERVED);
10840	}
10841
10842	rc = VMXReadVmcs64(VMX_VMCS_HOST_SYSENTER_ESP, &u64Val);
10843	AssertRCBreak(rc);
10844	HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_SYSENTER_ESP_NOT_CANONICAL);
10845
10846	rc = VMXReadVmcs64(VMX_VMCS_HOST_SYSENTER_EIP, &u64Val);
10847	AssertRCBreak(rc);
10848	HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_SYSENTER_EIP_NOT_CANONICAL);
10849	#endif
10850
10851	/*
10852	* PERF_GLOBAL MSR.
10853	*/
10854	if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR)
10855	{
10856	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL, &u64Val);
10857	AssertRCBreak(rc);
10858	HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xfffffff8fffffffc)),
10859	VMX_IGS_PERF_GLOBAL_MSR_RESERVED); /* Bits 63:35, bits 31:2 MBZ. */
10860	}
10861
10862	/*
10863	* PAT MSR.
10864	*/
10865	if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR)
10866	{
10867	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PAT_FULL, &u64Val);
10868	AssertRCBreak(rc);
10869	HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0x707070707070707)), VMX_IGS_PAT_MSR_RESERVED);
10870	for (unsigned i = 0; i < 8; i++)
10871	{
10872	uint8_t u8Val = (u64Val & 0xff);
10873	if ( u8Val != 0 /* UC */
10874	&& u8Val != 1 /* WC */
10875	&& u8Val != 4 /* WT */
10876	&& u8Val != 5 /* WP */
10877	&& u8Val != 6 /* WB */
10878	&& u8Val != 7 /* UC- */)
10879	{
10880	HMVMX_ERROR_BREAK(VMX_IGS_PAT_MSR_INVALID);
10881	}
10882	u64Val >>= 8;
10883	}
10884	}
10885
10886	/*
10887	* EFER MSR.
10888	*/
10889	if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR)
10890	{
10891	Assert(pVM->hm.s.vmx.fSupportsVmcsEfer);
10892	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_EFER_FULL, &u64Val);
10893	AssertRCBreak(rc);
10894	HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xfffffffffffff2fe)),
10895	VMX_IGS_EFER_MSR_RESERVED); /* Bits 63:12, bit 9, bits 7:1 MBZ. */
10896	HMVMX_CHECK_BREAK(RT_BOOL(u64Val & MSR_K6_EFER_LMA) == RT_BOOL( pVCpu->hm.s.vmx.u32EntryCtls
10897	& VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST),
10898	VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH);
10899	HMVMX_CHECK_BREAK( fUnrestrictedGuest
10900	\|\| !(u32GuestCR0 & X86_CR0_PG)
10901	\|\| RT_BOOL(u64Val & MSR_K6_EFER_LMA) == RT_BOOL(u64Val & MSR_K6_EFER_LME),
10902	VMX_IGS_EFER_LMA_LME_MISMATCH);
10903	}
10904
10905	/*
10906	* Segment registers.
10907	*/
10908	HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
10909	\|\| !(pCtx->ldtr.Sel & X86_SEL_LDT), VMX_IGS_LDTR_TI_INVALID);
10910	if (!(u32Eflags & X86_EFL_VM))
10911	{
10912	/* CS */
10913	HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u1Present, VMX_IGS_CS_ATTR_P_INVALID);
10914	HMVMX_CHECK_BREAK(!(pCtx->cs.Attr.u & 0xf00), VMX_IGS_CS_ATTR_RESERVED);
10915	HMVMX_CHECK_BREAK(!(pCtx->cs.Attr.u & 0xfffe0000), VMX_IGS_CS_ATTR_RESERVED);
10916	HMVMX_CHECK_BREAK( (pCtx->cs.u32Limit & 0xfff) == 0xfff
10917	\|\| !(pCtx->cs.Attr.n.u1Granularity), VMX_IGS_CS_ATTR_G_INVALID);
10918	HMVMX_CHECK_BREAK( !(pCtx->cs.u32Limit & 0xfff00000)
10919	\|\| (pCtx->cs.Attr.n.u1Granularity), VMX_IGS_CS_ATTR_G_INVALID);
10920	/* CS cannot be loaded with NULL in protected mode. */
10921	HMVMX_CHECK_BREAK(pCtx->cs.Attr.u && !(pCtx->cs.Attr.u & X86DESCATTR_UNUSABLE), VMX_IGS_CS_ATTR_UNUSABLE);
10922	HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u1DescType, VMX_IGS_CS_ATTR_S_INVALID);
10923	if (pCtx->cs.Attr.n.u4Type == 9 \|\| pCtx->cs.Attr.n.u4Type == 11)
10924	HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl == pCtx->ss.Attr.n.u2Dpl, VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL);
10925	else if (pCtx->cs.Attr.n.u4Type == 13 \|\| pCtx->cs.Attr.n.u4Type == 15)
10926	HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl <= pCtx->ss.Attr.n.u2Dpl, VMX_IGS_CS_SS_ATTR_DPL_MISMATCH);
10927	else if (pVM->hm.s.vmx.fUnrestrictedGuest && pCtx->cs.Attr.n.u4Type == 3)
10928	HMVMX_CHECK_BREAK(pCtx->cs.Attr.n.u2Dpl == 0, VMX_IGS_CS_ATTR_DPL_INVALID);
10929	else
10930	HMVMX_ERROR_BREAK(VMX_IGS_CS_ATTR_TYPE_INVALID);
10931
10932	/* SS */
10933	HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10934	\|\| (pCtx->ss.Sel & X86_SEL_RPL) == (pCtx->cs.Sel & X86_SEL_RPL), VMX_IGS_SS_CS_RPL_UNEQUAL);
10935	HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u2Dpl == (pCtx->ss.Sel & X86_SEL_RPL), VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL);
10936	if ( !(pCtx->cr0 & X86_CR0_PE)
10937	\|\| pCtx->cs.Attr.n.u4Type == 3)
10938	{
10939	HMVMX_CHECK_BREAK(!pCtx->ss.Attr.n.u2Dpl, VMX_IGS_SS_ATTR_DPL_INVALID);
10940	}
10941	if (!(pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE))
10942	{
10943	HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u4Type == 3 \|\| pCtx->ss.Attr.n.u4Type == 7, VMX_IGS_SS_ATTR_TYPE_INVALID);
10944	HMVMX_CHECK_BREAK(pCtx->ss.Attr.n.u1Present, VMX_IGS_SS_ATTR_P_INVALID);
10945	HMVMX_CHECK_BREAK(!(pCtx->ss.Attr.u & 0xf00), VMX_IGS_SS_ATTR_RESERVED);
10946	HMVMX_CHECK_BREAK(!(pCtx->ss.Attr.u & 0xfffe0000), VMX_IGS_SS_ATTR_RESERVED);
10947	HMVMX_CHECK_BREAK( (pCtx->ss.u32Limit & 0xfff) == 0xfff
10948	\|\| !(pCtx->ss.Attr.n.u1Granularity), VMX_IGS_SS_ATTR_G_INVALID);
10949	HMVMX_CHECK_BREAK( !(pCtx->ss.u32Limit & 0xfff00000)
10950	\|\| (pCtx->ss.Attr.n.u1Granularity), VMX_IGS_SS_ATTR_G_INVALID);
10951	}
10952
10953	/* DS, ES, FS, GS - only check for usable selectors, see hmR0VmxWriteSegmentReg(). */
10954	if (!(pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE))
10955	{
10956	HMVMX_CHECK_BREAK(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_DS_ATTR_A_INVALID);
10957	HMVMX_CHECK_BREAK(pCtx->ds.Attr.n.u1Present, VMX_IGS_DS_ATTR_P_INVALID);
10958	HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10959	\|\| pCtx->ds.Attr.n.u4Type > 11
10960	\|\| pCtx->ds.Attr.n.u2Dpl >= (pCtx->ds.Sel & X86_SEL_RPL), VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL);
10961	HMVMX_CHECK_BREAK(!(pCtx->ds.Attr.u & 0xf00), VMX_IGS_DS_ATTR_RESERVED);
10962	HMVMX_CHECK_BREAK(!(pCtx->ds.Attr.u & 0xfffe0000), VMX_IGS_DS_ATTR_RESERVED);
10963	HMVMX_CHECK_BREAK( (pCtx->ds.u32Limit & 0xfff) == 0xfff
10964	\|\| !(pCtx->ds.Attr.n.u1Granularity), VMX_IGS_DS_ATTR_G_INVALID);
10965	HMVMX_CHECK_BREAK( !(pCtx->ds.u32Limit & 0xfff00000)
10966	\|\| (pCtx->ds.Attr.n.u1Granularity), VMX_IGS_DS_ATTR_G_INVALID);
10967	HMVMX_CHECK_BREAK( !(pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_CODE)
10968	\|\| (pCtx->ds.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_DS_ATTR_TYPE_INVALID);
10969	}
10970	if (!(pCtx->es.Attr.u & X86DESCATTR_UNUSABLE))
10971	{
10972	HMVMX_CHECK_BREAK(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_ES_ATTR_A_INVALID);
10973	HMVMX_CHECK_BREAK(pCtx->es.Attr.n.u1Present, VMX_IGS_ES_ATTR_P_INVALID);
10974	HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10975	\|\| pCtx->es.Attr.n.u4Type > 11
10976	\|\| pCtx->es.Attr.n.u2Dpl >= (pCtx->es.Sel & X86_SEL_RPL), VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL);
10977	HMVMX_CHECK_BREAK(!(pCtx->es.Attr.u & 0xf00), VMX_IGS_ES_ATTR_RESERVED);
10978	HMVMX_CHECK_BREAK(!(pCtx->es.Attr.u & 0xfffe0000), VMX_IGS_ES_ATTR_RESERVED);
10979	HMVMX_CHECK_BREAK( (pCtx->es.u32Limit & 0xfff) == 0xfff
10980	\|\| !(pCtx->es.Attr.n.u1Granularity), VMX_IGS_ES_ATTR_G_INVALID);
10981	HMVMX_CHECK_BREAK( !(pCtx->es.u32Limit & 0xfff00000)
10982	\|\| (pCtx->es.Attr.n.u1Granularity), VMX_IGS_ES_ATTR_G_INVALID);
10983	HMVMX_CHECK_BREAK( !(pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_CODE)
10984	\|\| (pCtx->es.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_ES_ATTR_TYPE_INVALID);
10985	}
10986	if (!(pCtx->fs.Attr.u & X86DESCATTR_UNUSABLE))
10987	{
10988	HMVMX_CHECK_BREAK(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_FS_ATTR_A_INVALID);
10989	HMVMX_CHECK_BREAK(pCtx->fs.Attr.n.u1Present, VMX_IGS_FS_ATTR_P_INVALID);
10990	HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
10991	\|\| pCtx->fs.Attr.n.u4Type > 11
10992	\|\| pCtx->fs.Attr.n.u2Dpl >= (pCtx->fs.Sel & X86_SEL_RPL), VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL);
10993	HMVMX_CHECK_BREAK(!(pCtx->fs.Attr.u & 0xf00), VMX_IGS_FS_ATTR_RESERVED);
10994	HMVMX_CHECK_BREAK(!(pCtx->fs.Attr.u & 0xfffe0000), VMX_IGS_FS_ATTR_RESERVED);
10995	HMVMX_CHECK_BREAK( (pCtx->fs.u32Limit & 0xfff) == 0xfff
10996	\|\| !(pCtx->fs.Attr.n.u1Granularity), VMX_IGS_FS_ATTR_G_INVALID);
10997	HMVMX_CHECK_BREAK( !(pCtx->fs.u32Limit & 0xfff00000)
10998	\|\| (pCtx->fs.Attr.n.u1Granularity), VMX_IGS_FS_ATTR_G_INVALID);
10999	HMVMX_CHECK_BREAK( !(pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
11000	\|\| (pCtx->fs.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_FS_ATTR_TYPE_INVALID);
11001	}
11002	if (!(pCtx->gs.Attr.u & X86DESCATTR_UNUSABLE))
11003	{
11004	HMVMX_CHECK_BREAK(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_ACCESSED, VMX_IGS_GS_ATTR_A_INVALID);
11005	HMVMX_CHECK_BREAK(pCtx->gs.Attr.n.u1Present, VMX_IGS_GS_ATTR_P_INVALID);
11006	HMVMX_CHECK_BREAK( pVM->hm.s.vmx.fUnrestrictedGuest
11007	\|\| pCtx->gs.Attr.n.u4Type > 11
11008	\|\| pCtx->gs.Attr.n.u2Dpl >= (pCtx->gs.Sel & X86_SEL_RPL), VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL);
11009	HMVMX_CHECK_BREAK(!(pCtx->gs.Attr.u & 0xf00), VMX_IGS_GS_ATTR_RESERVED);
11010	HMVMX_CHECK_BREAK(!(pCtx->gs.Attr.u & 0xfffe0000), VMX_IGS_GS_ATTR_RESERVED);
11011	HMVMX_CHECK_BREAK( (pCtx->gs.u32Limit & 0xfff) == 0xfff
11012	\|\| !(pCtx->gs.Attr.n.u1Granularity), VMX_IGS_GS_ATTR_G_INVALID);
11013	HMVMX_CHECK_BREAK( !(pCtx->gs.u32Limit & 0xfff00000)
11014	\|\| (pCtx->gs.Attr.n.u1Granularity), VMX_IGS_GS_ATTR_G_INVALID);
11015	HMVMX_CHECK_BREAK( !(pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_CODE)
11016	\|\| (pCtx->gs.Attr.n.u4Type & X86_SEL_TYPE_READ), VMX_IGS_GS_ATTR_TYPE_INVALID);
11017	}
11018	/* 64-bit capable CPUs. */
11019	#if HC_ARCH_BITS == 64
11020	HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->fs.u64Base), VMX_IGS_FS_BASE_NOT_CANONICAL);
11021	HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->gs.u64Base), VMX_IGS_GS_BASE_NOT_CANONICAL);
11022	HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
11023	\|\| X86_IS_CANONICAL(pCtx->ldtr.u64Base), VMX_IGS_LDTR_BASE_NOT_CANONICAL);
11024	HMVMX_CHECK_BREAK(!(pCtx->cs.u64Base >> 32), VMX_IGS_LONGMODE_CS_BASE_INVALID);
11025	HMVMX_CHECK_BREAK((pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE) \|\| !(pCtx->ss.u64Base >> 32),
11026	VMX_IGS_LONGMODE_SS_BASE_INVALID);
11027	HMVMX_CHECK_BREAK((pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE) \|\| !(pCtx->ds.u64Base >> 32),
11028	VMX_IGS_LONGMODE_DS_BASE_INVALID);
11029	HMVMX_CHECK_BREAK((pCtx->es.Attr.u & X86DESCATTR_UNUSABLE) \|\| !(pCtx->es.u64Base >> 32),
11030	VMX_IGS_LONGMODE_ES_BASE_INVALID);
11031	#endif
11032	}
11033	else
11034	{
11035	/* V86 mode checks. */
11036	uint32_t u32CSAttr, u32SSAttr, u32DSAttr, u32ESAttr, u32FSAttr, u32GSAttr;
11037	if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
11038	{
11039	u32CSAttr = 0xf3; u32SSAttr = 0xf3;
11040	u32DSAttr = 0xf3; u32ESAttr = 0xf3;
11041	u32FSAttr = 0xf3; u32GSAttr = 0xf3;
11042	}
11043	else
11044	{
11045	u32CSAttr = pCtx->cs.Attr.u; u32SSAttr = pCtx->ss.Attr.u;
11046	u32DSAttr = pCtx->ds.Attr.u; u32ESAttr = pCtx->es.Attr.u;
11047	u32FSAttr = pCtx->fs.Attr.u; u32GSAttr = pCtx->gs.Attr.u;
11048	}
11049
11050	/* CS */
11051	HMVMX_CHECK_BREAK((pCtx->cs.u64Base == (uint64_t)pCtx->cs.Sel << 4), VMX_IGS_V86_CS_BASE_INVALID);
11052	HMVMX_CHECK_BREAK(pCtx->cs.u32Limit == 0xffff, VMX_IGS_V86_CS_LIMIT_INVALID);
11053	HMVMX_CHECK_BREAK(u32CSAttr == 0xf3, VMX_IGS_V86_CS_ATTR_INVALID);
11054	/* SS */
11055	HMVMX_CHECK_BREAK((pCtx->ss.u64Base == (uint64_t)pCtx->ss.Sel << 4), VMX_IGS_V86_SS_BASE_INVALID);
11056	HMVMX_CHECK_BREAK(pCtx->ss.u32Limit == 0xffff, VMX_IGS_V86_SS_LIMIT_INVALID);
11057	HMVMX_CHECK_BREAK(u32SSAttr == 0xf3, VMX_IGS_V86_SS_ATTR_INVALID);
11058	/* DS */
11059	HMVMX_CHECK_BREAK((pCtx->ds.u64Base == (uint64_t)pCtx->ds.Sel << 4), VMX_IGS_V86_DS_BASE_INVALID);
11060	HMVMX_CHECK_BREAK(pCtx->ds.u32Limit == 0xffff, VMX_IGS_V86_DS_LIMIT_INVALID);
11061	HMVMX_CHECK_BREAK(u32DSAttr == 0xf3, VMX_IGS_V86_DS_ATTR_INVALID);
11062	/* ES */
11063	HMVMX_CHECK_BREAK((pCtx->es.u64Base == (uint64_t)pCtx->es.Sel << 4), VMX_IGS_V86_ES_BASE_INVALID);
11064	HMVMX_CHECK_BREAK(pCtx->es.u32Limit == 0xffff, VMX_IGS_V86_ES_LIMIT_INVALID);
11065	HMVMX_CHECK_BREAK(u32ESAttr == 0xf3, VMX_IGS_V86_ES_ATTR_INVALID);
11066	/* FS */
11067	HMVMX_CHECK_BREAK((pCtx->fs.u64Base == (uint64_t)pCtx->fs.Sel << 4), VMX_IGS_V86_FS_BASE_INVALID);
11068	HMVMX_CHECK_BREAK(pCtx->fs.u32Limit == 0xffff, VMX_IGS_V86_FS_LIMIT_INVALID);
11069	HMVMX_CHECK_BREAK(u32FSAttr == 0xf3, VMX_IGS_V86_FS_ATTR_INVALID);
11070	/* GS */
11071	HMVMX_CHECK_BREAK((pCtx->gs.u64Base == (uint64_t)pCtx->gs.Sel << 4), VMX_IGS_V86_GS_BASE_INVALID);
11072	HMVMX_CHECK_BREAK(pCtx->gs.u32Limit == 0xffff, VMX_IGS_V86_GS_LIMIT_INVALID);
11073	HMVMX_CHECK_BREAK(u32GSAttr == 0xf3, VMX_IGS_V86_GS_ATTR_INVALID);
11074	/* 64-bit capable CPUs. */
11075	#if HC_ARCH_BITS == 64
11076	HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->fs.u64Base), VMX_IGS_FS_BASE_NOT_CANONICAL);
11077	HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->gs.u64Base), VMX_IGS_GS_BASE_NOT_CANONICAL);
11078	HMVMX_CHECK_BREAK( (pCtx->ldtr.Attr.u & X86DESCATTR_UNUSABLE)
11079	\|\| X86_IS_CANONICAL(pCtx->ldtr.u64Base), VMX_IGS_LDTR_BASE_NOT_CANONICAL);
11080	HMVMX_CHECK_BREAK(!(pCtx->cs.u64Base >> 32), VMX_IGS_LONGMODE_CS_BASE_INVALID);
11081	HMVMX_CHECK_BREAK((pCtx->ss.Attr.u & X86DESCATTR_UNUSABLE) \|\| !(pCtx->ss.u64Base >> 32),
11082	VMX_IGS_LONGMODE_SS_BASE_INVALID);
11083	HMVMX_CHECK_BREAK((pCtx->ds.Attr.u & X86DESCATTR_UNUSABLE) \|\| !(pCtx->ds.u64Base >> 32),
11084	VMX_IGS_LONGMODE_DS_BASE_INVALID);
11085	HMVMX_CHECK_BREAK((pCtx->es.Attr.u & X86DESCATTR_UNUSABLE) \|\| !(pCtx->es.u64Base >> 32),
11086	VMX_IGS_LONGMODE_ES_BASE_INVALID);
11087	#endif
11088	}
11089
11090	/*
11091	* TR.
11092	*/
11093	HMVMX_CHECK_BREAK(!(pCtx->tr.Sel & X86_SEL_LDT), VMX_IGS_TR_TI_INVALID);
11094	/* 64-bit capable CPUs. */
11095	#if HC_ARCH_BITS == 64
11096	HMVMX_CHECK_BREAK(X86_IS_CANONICAL(pCtx->tr.u64Base), VMX_IGS_TR_BASE_NOT_CANONICAL);
11097	#endif
11098	if (fLongModeGuest)
11099	{
11100	HMVMX_CHECK_BREAK(pCtx->tr.Attr.n.u4Type == 11, /* 64-bit busy TSS. */
11101	VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID);
11102	}
11103	else
11104	{
11105	HMVMX_CHECK_BREAK( pCtx->tr.Attr.n.u4Type == 3 /* 16-bit busy TSS. */
11106	\|\| pCtx->tr.Attr.n.u4Type == 11, /* 32-bit busy TSS.*/
11107	VMX_IGS_TR_ATTR_TYPE_INVALID);
11108	}
11109	HMVMX_CHECK_BREAK(!pCtx->tr.Attr.n.u1DescType, VMX_IGS_TR_ATTR_S_INVALID);
11110	HMVMX_CHECK_BREAK(pCtx->tr.Attr.n.u1Present, VMX_IGS_TR_ATTR_P_INVALID);
11111	HMVMX_CHECK_BREAK(!(pCtx->tr.Attr.u & 0xf00), VMX_IGS_TR_ATTR_RESERVED); /* Bits 11:8 MBZ. */
11112	HMVMX_CHECK_BREAK( (pCtx->tr.u32Limit & 0xfff) == 0xfff
11113	\|\| !(pCtx->tr.Attr.n.u1Granularity), VMX_IGS_TR_ATTR_G_INVALID);
11114	HMVMX_CHECK_BREAK( !(pCtx->tr.u32Limit & 0xfff00000)
11115	\|\| (pCtx->tr.Attr.n.u1Granularity), VMX_IGS_TR_ATTR_G_INVALID);
11116	HMVMX_CHECK_BREAK(!(pCtx->tr.Attr.u & X86DESCATTR_UNUSABLE), VMX_IGS_TR_ATTR_UNUSABLE);
11117
11118	/*
11119	* GDTR and IDTR.
11120	*/
11121	#if HC_ARCH_BITS == 64
11122	rc = VMXReadVmcs64(VMX_VMCS_GUEST_GDTR_BASE, &u64Val);
11123	AssertRCBreak(rc);
11124	HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_GDTR_BASE_NOT_CANONICAL);
11125
11126	rc = VMXReadVmcs64(VMX_VMCS_GUEST_IDTR_BASE, &u64Val);
11127	AssertRCBreak(rc);
11128	HMVMX_CHECK_BREAK(X86_IS_CANONICAL(u64Val), VMX_IGS_IDTR_BASE_NOT_CANONICAL);
11129	#endif
11130
11131	rc = VMXReadVmcs32(VMX_VMCS32_GUEST_GDTR_LIMIT, &u32Val);
11132	AssertRCBreak(rc);
11133	HMVMX_CHECK_BREAK(!(u32Val & 0xffff0000), VMX_IGS_GDTR_LIMIT_INVALID); /* Bits 31:16 MBZ. */
11134
11135	rc = VMXReadVmcs32(VMX_VMCS32_GUEST_IDTR_LIMIT, &u32Val);
11136	AssertRCBreak(rc);
11137	HMVMX_CHECK_BREAK(!(u32Val & 0xffff0000), VMX_IGS_IDTR_LIMIT_INVALID); /* Bits 31:16 MBZ. */
11138
11139	/*
11140	* Guest Non-Register State.
11141	*/
11142	/* Activity State. */
11143	uint32_t u32ActivityState;
11144	rc = VMXReadVmcs32(VMX_VMCS32_GUEST_ACTIVITY_STATE, &u32ActivityState);
11145	AssertRCBreak(rc);
11146	HMVMX_CHECK_BREAK( !u32ActivityState
11147	\|\| (u32ActivityState & MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.Msrs.u64Misc)),
11148	VMX_IGS_ACTIVITY_STATE_INVALID);
11149	HMVMX_CHECK_BREAK( !(pCtx->ss.Attr.n.u2Dpl)
11150	\|\| u32ActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT, VMX_IGS_ACTIVITY_STATE_HLT_INVALID);
11151	uint32_t u32IntrState;
11152	rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &u32IntrState);
11153	AssertRCBreak(rc);
11154	if ( u32IntrState == VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS
11155	\|\| u32IntrState == VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI)
11156	{
11157	HMVMX_CHECK_BREAK(u32ActivityState == VMX_VMCS_GUEST_ACTIVITY_ACTIVE, VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID);
11158	}
11159
11160	/** @todo Activity state and injecting interrupts. Left as a todo since we
11161	* currently don't use activity states but ACTIVE. */
11162
11163	HMVMX_CHECK_BREAK( !(pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_ENTRY_SMM)
11164	\|\| u32ActivityState != VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT, VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID);
11165
11166	/* Guest interruptibility-state. */
11167	HMVMX_CHECK_BREAK(!(u32IntrState & 0xfffffff0), VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED);
11168	HMVMX_CHECK_BREAK((u32IntrState & ( VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI
11169	\| VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS))
11170	!= ( VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI
11171	\| VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS),
11172	VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID);
11173	HMVMX_CHECK_BREAK( (u32Eflags & X86_EFL_IF)
11174	\|\| !(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI),
11175	VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID);
11176	if (VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(u32EntryInfo))
11177	{
11178	if (VMX_ENTRY_INTERRUPTION_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT)
11179	{
11180	HMVMX_CHECK_BREAK( !(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI)
11181	&& !(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS),
11182	VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID);
11183	}
11184	else if (VMX_ENTRY_INTERRUPTION_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI)
11185	{
11186	HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS),
11187	VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID);
11188	HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI),
11189	VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID);
11190	}
11191	}
11192	/** @todo Assumes the processor is not in SMM. */
11193	HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI),
11194	VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID);
11195	HMVMX_CHECK_BREAK( !(pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_ENTRY_SMM)
11196	\|\| (u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI),
11197	VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID);
11198	if ( (pVCpu->hm.s.vmx.u32PinCtls & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI)
11199	&& VMX_ENTRY_INTERRUPTION_INFO_IS_VALID(u32EntryInfo)
11200	&& VMX_ENTRY_INTERRUPTION_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI)
11201	{
11202	HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI),
11203	VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID);
11204	}
11205
11206	/* Pending debug exceptions. */
11207	#if HC_ARCH_BITS == 64
11208	rc = VMXReadVmcs64(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, &u64Val);
11209	AssertRCBreak(rc);
11210	/* Bits 63:15, Bit 13, Bits 11:4 MBZ. */
11211	HMVMX_CHECK_BREAK(!(u64Val & UINT64_C(0xffffffffffffaff0)), VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED);
11212	u32Val = u64Val; /* For pending debug exceptions checks below. */
11213	#else
11214	rc = VMXReadVmcs32(VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS, &u32Val);
11215	AssertRCBreak(rc);
11216	/* Bits 31:15, Bit 13, Bits 11:4 MBZ. */
11217	HMVMX_CHECK_BREAK(!(u32Val & 0xffffaff0), VMX_IGS_PENDING_DEBUG_RESERVED);
11218	#endif
11219
11220	if ( (u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI)
11221	\|\| (u32IntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS)
11222	\|\| u32ActivityState == VMX_VMCS_GUEST_ACTIVITY_HLT)
11223	{
11224	if ( (u32Eflags & X86_EFL_TF)
11225	&& !(u64DebugCtlMsr & RT_BIT_64(1))) /* Bit 1 is IA32_DEBUGCTL.BTF. */
11226	{
11227	/* Bit 14 is PendingDebug.BS. */
11228	HMVMX_CHECK_BREAK(u32Val & RT_BIT(14), VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET);
11229	}
11230	if ( !(u32Eflags & X86_EFL_TF)
11231	\|\| (u64DebugCtlMsr & RT_BIT_64(1))) /* Bit 1 is IA32_DEBUGCTL.BTF. */
11232	{
11233	/* Bit 14 is PendingDebug.BS. */
11234	HMVMX_CHECK_BREAK(!(u32Val & RT_BIT(14)), VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR);
11235	}
11236	}
11237
11238	/* VMCS link pointer. */
11239	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL, &u64Val);
11240	AssertRCBreak(rc);
11241	if (u64Val != UINT64_C(0xffffffffffffffff))
11242	{
11243	HMVMX_CHECK_BREAK(!(u64Val & 0xfff), VMX_IGS_VMCS_LINK_PTR_RESERVED);
11244	/** @todo Bits beyond the processor's physical-address width MBZ. */
11245	/** @todo 32-bit located in memory referenced by value of this field (as a
11246	* physical address) must contain the processor's VMCS revision ID. */
11247	/** @todo SMM checks. */
11248	}
11249
11250	/** @todo Checks on Guest Page-Directory-Pointer-Table Entries when guest is
11251	* not using Nested Paging? */
11252	if ( pVM->hm.s.fNestedPaging
11253	&& !fLongModeGuest
11254	&& CPUMIsGuestInPAEModeEx(pCtx))
11255	{
11256	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE0_FULL, &u64Val);
11257	AssertRCBreak(rc);
11258	HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11259
11260	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE1_FULL, &u64Val);
11261	AssertRCBreak(rc);
11262	HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11263
11264	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE2_FULL, &u64Val);
11265	AssertRCBreak(rc);
11266	HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11267
11268	rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PDPTE3_FULL, &u64Val);
11269	AssertRCBreak(rc);
11270	HMVMX_CHECK_BREAK(!(u64Val & X86_PDPE_PAE_MBZ_MASK), VMX_IGS_PAE_PDPTE_RESERVED);
11271	}
11272
11273	/* Shouldn't happen but distinguish it from AssertRCBreak() errors. */
11274	if (uError == VMX_IGS_ERROR)
11275	uError = VMX_IGS_REASON_NOT_FOUND;
11276	} while (0);
11277
11278	pVCpu->hm.s.u32HMError = uError;
11279	return uError;
11280
11281	#undef HMVMX_ERROR_BREAK
11282	#undef HMVMX_CHECK_BREAK
11283	}
11284
11285	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
11286	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- VM-exit handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
11287	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
11288
11289	/** @name VM-exit handlers.
11290	* @{
11291	*/
11292
11293	/**
11294	* VM-exit handler for external interrupts (VMX_EXIT_EXT_INT).
11295	*/
11296	HMVMX_EXIT_DECL hmR0VmxExitExtInt(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11297	{
11298	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11299	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
11300	/* Windows hosts (32-bit and 64-bit) have DPC latency issues. See @bugref{6853}. */
11301	if (VMMR0ThreadCtxHookIsEnabled(pVCpu))
11302	return VINF_SUCCESS;
11303	return VINF_EM_RAW_INTERRUPT;
11304	}
11305
11306
11307	/**
11308	* VM-exit handler for exceptions or NMIs (VMX_EXIT_XCPT_OR_NMI).
11309	*/
11310	HMVMX_EXIT_DECL hmR0VmxExitXcptOrNmi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11311	{
11312	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11313	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitXcptNmi, y3);
11314
11315	int rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
11316	AssertRCReturn(rc, rc);
11317
11318	uint32_t uIntType = VMX_EXIT_INTERRUPTION_INFO_TYPE(pVmxTransient->uExitIntInfo);
11319	Assert( !(pVCpu->hm.s.vmx.u32ExitCtls & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT)
11320	&& uIntType != VMX_EXIT_INTERRUPTION_INFO_TYPE_EXT_INT);
11321	Assert(VMX_EXIT_INTERRUPTION_INFO_IS_VALID(pVmxTransient->uExitIntInfo));
11322
11323	if (uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_NMI)
11324	{
11325	/*
11326	* This cannot be a guest NMI as the only way for the guest to receive an NMI is if we injected it ourselves and
11327	* anything we inject is not going to cause a VM-exit directly for the event being injected.
11328	* See Intel spec. 27.2.3 "Information for VM Exits During Event Delivery".
11329	*
11330	* Dispatch the NMI to the host. See Intel spec. 27.5.5 "Updating Non-Register State".
11331	*/
11332	VMXDispatchHostNmi();
11333	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
11334	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
11335	return VINF_SUCCESS;
11336	}
11337
11338	/* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
11339	VBOXSTRICTRC rcStrictRc1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pMixedCtx, pVmxTransient);
11340	if (RT_UNLIKELY(rcStrictRc1 == VINF_SUCCESS))
11341	{ /* likely */ }
11342	else
11343	{
11344	if (rcStrictRc1 == VINF_HM_DOUBLE_FAULT)
11345	rcStrictRc1 = VINF_SUCCESS;
11346	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
11347	return rcStrictRc1;
11348	}
11349
11350	uint32_t uExitIntInfo = pVmxTransient->uExitIntInfo;
11351	uint32_t uVector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(uExitIntInfo);
11352	switch (uIntType)
11353	{
11354	case VMX_EXIT_INTERRUPTION_INFO_TYPE_PRIV_SW_XCPT: /* Privileged software exception. (#DB from ICEBP) */
11355	Assert(uVector == X86_XCPT_DB);
11356	/* fall thru */
11357	case VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT: /* Software exception. (#BP or #OF) */
11358	Assert(uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF \|\| uIntType == VMX_EXIT_INTERRUPTION_INFO_TYPE_PRIV_SW_XCPT);
11359	/* fall thru */
11360	case VMX_EXIT_INTERRUPTION_INFO_TYPE_HW_XCPT:
11361	{
11362	/*
11363	* If there's any exception caused as a result of event injection, go back to
11364	* the interpreter. The page-fault case is complicated and we manually handle
11365	* any currently pending event in hmR0VmxExitXcptPF. Nested #ACs are already
11366	* handled in hmR0VmxCheckExitDueToEventDelivery.
11367	*/
11368	if (!pVCpu->hm.s.Event.fPending)
11369	{ /* likely */ }
11370	else if ( uVector != X86_XCPT_PF
11371	&& uVector != X86_XCPT_AC)
11372	{
11373	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
11374	rc = VERR_EM_INTERPRETER;
11375	break;
11376	}
11377
11378	switch (uVector)
11379	{
11380	case X86_XCPT_PF: rc = hmR0VmxExitXcptPF(pVCpu, pMixedCtx, pVmxTransient); break;
11381	case X86_XCPT_GP: rc = hmR0VmxExitXcptGP(pVCpu, pMixedCtx, pVmxTransient); break;
11382	case X86_XCPT_NM: rc = hmR0VmxExitXcptNM(pVCpu, pMixedCtx, pVmxTransient); break;
11383	case X86_XCPT_MF: rc = hmR0VmxExitXcptMF(pVCpu, pMixedCtx, pVmxTransient); break;
11384	case X86_XCPT_DB: rc = hmR0VmxExitXcptDB(pVCpu, pMixedCtx, pVmxTransient); break;
11385	case X86_XCPT_BP: rc = hmR0VmxExitXcptBP(pVCpu, pMixedCtx, pVmxTransient); break;
11386	case X86_XCPT_AC: rc = hmR0VmxExitXcptAC(pVCpu, pMixedCtx, pVmxTransient); break;
11387
11388	case X86_XCPT_XF: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXF);
11389	rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
11390	case X86_XCPT_DE: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
11391	rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
11392	case X86_XCPT_UD: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
11393	rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
11394	case X86_XCPT_SS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
11395	rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
11396	case X86_XCPT_NP: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
11397	rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
11398	case X86_XCPT_TS: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestTS);
11399	rc = hmR0VmxExitXcptGeneric(pVCpu, pMixedCtx, pVmxTransient); break;
11400	default:
11401	{
11402	rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
11403	AssertRCReturn(rc, rc);
11404
11405	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestXcpUnk);
11406	if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
11407	{
11408	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.pRealModeTSS);
11409	Assert(PDMVmmDevHeapIsEnabled(pVCpu->CTX_SUFF(pVM)));
11410	Assert(CPUMIsGuestInRealModeEx(pMixedCtx));
11411
11412	rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11413	rc \|= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
11414	AssertRCReturn(rc, rc);
11415	hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(uExitIntInfo),
11416	pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode,
11417	0 /* GCPtrFaultAddress */);
11418	AssertRCReturn(rc, rc);
11419	}
11420	else
11421	{
11422	AssertMsgFailed(("Unexpected VM-exit caused by exception %#x\n", uVector));
11423	pVCpu->hm.s.u32HMError = uVector;
11424	rc = VERR_VMX_UNEXPECTED_EXCEPTION;
11425	}
11426	break;
11427	}
11428	}
11429	break;
11430	}
11431
11432	default:
11433	{
11434	pVCpu->hm.s.u32HMError = uExitIntInfo;
11435	rc = VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE;
11436	AssertMsgFailed(("Unexpected interruption info %#x\n", VMX_EXIT_INTERRUPTION_INFO_TYPE(uExitIntInfo)));
11437	break;
11438	}
11439	}
11440	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitXcptNmi, y3);
11441	return rc;
11442	}
11443
11444
11445	/**
11446	* VM-exit handler for interrupt-window exiting (VMX_EXIT_INT_WINDOW).
11447	*/
11448	HMVMX_EXIT_NSRC_DECL hmR0VmxExitIntWindow(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11449	{
11450	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11451
11452	/* Indicate that we no longer need to VM-exit when the guest is ready to receive interrupts, it is now ready. */
11453	hmR0VmxClearIntWindowExitVmcs(pVCpu);
11454
11455	/* Deliver the pending interrupts via hmR0VmxEvaluatePendingEvent() and resume guest execution. */
11456	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
11457	return VINF_SUCCESS;
11458	}
11459
11460
11461	/**
11462	* VM-exit handler for NMI-window exiting (VMX_EXIT_NMI_WINDOW).
11463	*/
11464	HMVMX_EXIT_NSRC_DECL hmR0VmxExitNmiWindow(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11465	{
11466	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11467	if (RT_UNLIKELY(!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT)))
11468	{
11469	AssertMsgFailed(("Unexpected NMI-window exit.\n"));
11470	HMVMX_RETURN_UNEXPECTED_EXIT();
11471	}
11472
11473	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS));
11474
11475	/*
11476	* If block-by-STI is set when we get this VM-exit, it means the CPU doesn't block NMIs following STI.
11477	* It is therefore safe to unblock STI and deliver the NMI ourselves. See @bugref{7445}.
11478	*/
11479	uint32_t uIntrState = 0;
11480	int rc = VMXReadVmcs32(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &uIntrState);
11481	AssertRCReturn(rc, rc);
11482
11483	bool const fBlockSti = RT_BOOL(uIntrState & VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI);
11484	if ( fBlockSti
11485	&& VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
11486	{
11487	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
11488	}
11489
11490	/* Indicate that we no longer need to VM-exit when the guest is ready to receive NMIs, it is now ready */
11491	hmR0VmxClearNmiWindowExitVmcs(pVCpu);
11492
11493	/* Deliver the pending NMI via hmR0VmxEvaluatePendingEvent() and resume guest execution. */
11494	return VINF_SUCCESS;
11495	}
11496
11497
11498	/**
11499	* VM-exit handler for WBINVD (VMX_EXIT_WBINVD). Conditional VM-exit.
11500	*/
11501	HMVMX_EXIT_NSRC_DECL hmR0VmxExitWbinvd(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11502	{
11503	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11504	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
11505	return hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11506	}
11507
11508
11509	/**
11510	* VM-exit handler for INVD (VMX_EXIT_INVD). Unconditional VM-exit.
11511	*/
11512	HMVMX_EXIT_NSRC_DECL hmR0VmxExitInvd(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11513	{
11514	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11515	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
11516	return hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11517	}
11518
11519
11520	/**
11521	* VM-exit handler for CPUID (VMX_EXIT_CPUID). Unconditional VM-exit.
11522	*/
11523	HMVMX_EXIT_DECL hmR0VmxExitCpuid(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11524	{
11525	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11526	PVM pVM = pVCpu->CTX_SUFF(pVM);
11527	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
11528	if (RT_LIKELY(rc == VINF_SUCCESS))
11529	{
11530	rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11531	Assert(pVmxTransient->cbInstr == 2);
11532	}
11533	else
11534	{
11535	AssertMsgFailed(("hmR0VmxExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
11536	rc = VERR_EM_INTERPRETER;
11537	}
11538	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
11539	return rc;
11540	}
11541
11542
11543	/**
11544	* VM-exit handler for GETSEC (VMX_EXIT_GETSEC). Unconditional VM-exit.
11545	*/
11546	HMVMX_EXIT_DECL hmR0VmxExitGetsec(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11547	{
11548	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11549	int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
11550	AssertRCReturn(rc, rc);
11551
11552	if (pMixedCtx->cr4 & X86_CR4_SMXE)
11553	return VINF_EM_RAW_EMULATE_INSTR;
11554
11555	AssertMsgFailed(("hmR0VmxExitGetsec: unexpected VM-exit when CR4.SMXE is 0.\n"));
11556	HMVMX_RETURN_UNEXPECTED_EXIT();
11557	}
11558
11559
11560	/**
11561	* VM-exit handler for RDTSC (VMX_EXIT_RDTSC). Conditional VM-exit.
11562	*/
11563	HMVMX_EXIT_DECL hmR0VmxExitRdtsc(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11564	{
11565	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11566	int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
11567	AssertRCReturn(rc, rc);
11568
11569	PVM pVM = pVCpu->CTX_SUFF(pVM);
11570	rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
11571	if (RT_LIKELY(rc == VINF_SUCCESS))
11572	{
11573	rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11574	Assert(pVmxTransient->cbInstr == 2);
11575	/* If we get a spurious VM-exit when offsetting is enabled, we must reset offsetting on VM-reentry. See @bugref{6634}. */
11576	if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING)
11577	pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
11578	}
11579	else
11580	rc = VERR_EM_INTERPRETER;
11581	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
11582	return rc;
11583	}
11584
11585
11586	/**
11587	* VM-exit handler for RDTSCP (VMX_EXIT_RDTSCP). Conditional VM-exit.
11588	*/
11589	HMVMX_EXIT_DECL hmR0VmxExitRdtscp(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11590	{
11591	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11592	int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
11593	rc \|= hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx); /* For MSR_K8_TSC_AUX */
11594	AssertRCReturn(rc, rc);
11595
11596	PVM pVM = pVCpu->CTX_SUFF(pVM);
11597	rc = EMInterpretRdtscp(pVM, pVCpu, pMixedCtx);
11598	if (RT_SUCCESS(rc))
11599	{
11600	rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11601	Assert(pVmxTransient->cbInstr == 3);
11602	/* If we get a spurious VM-exit when offsetting is enabled, we must reset offsetting on VM-reentry. See @bugref{6634}. */
11603	if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING)
11604	pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
11605	}
11606	else
11607	{
11608	AssertMsgFailed(("hmR0VmxExitRdtscp: EMInterpretRdtscp failed with %Rrc\n", rc));
11609	rc = VERR_EM_INTERPRETER;
11610	}
11611	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
11612	return rc;
11613	}
11614
11615
11616	/**
11617	* VM-exit handler for RDPMC (VMX_EXIT_RDPMC). Conditional VM-exit.
11618	*/
11619	HMVMX_EXIT_DECL hmR0VmxExitRdpmc(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11620	{
11621	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11622	int rc = hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
11623	rc \|= hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
11624	AssertRCReturn(rc, rc);
11625
11626	PVM pVM = pVCpu->CTX_SUFF(pVM);
11627	rc = EMInterpretRdpmc(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
11628	if (RT_LIKELY(rc == VINF_SUCCESS))
11629	{
11630	rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11631	Assert(pVmxTransient->cbInstr == 2);
11632	}
11633	else
11634	{
11635	AssertMsgFailed(("hmR0VmxExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
11636	rc = VERR_EM_INTERPRETER;
11637	}
11638	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
11639	return rc;
11640	}
11641
11642
11643	/**
11644	* VM-exit handler for VMCALL (VMX_EXIT_VMCALL). Unconditional VM-exit.
11645	*/
11646	HMVMX_EXIT_DECL hmR0VmxExitVmcall(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11647	{
11648	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11649	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmcall);
11650
11651	VBOXSTRICTRC rcStrict = VERR_VMX_IPE_3;
11652	if (pVCpu->hm.s.fHypercallsEnabled)
11653	{
11654	#if 0
11655	int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
11656	#else
11657	/* Aggressive state sync. for now. */
11658	int rc = hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
11659	rc \|= hmR0VmxSaveGuestRflags(pVCpu,pMixedCtx); /* For CPL checks in gimHvHypercall() & gimKvmHypercall() */
11660	rc \|= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx); /* For long-mode checks in gimKvmHypercall(). */
11661	AssertRCReturn(rc, rc);
11662	#endif
11663
11664	/* Perform the hypercall. */
11665	rcStrict = GIMHypercall(pVCpu, pMixedCtx);
11666	if (rcStrict == VINF_SUCCESS)
11667	{
11668	rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11669	AssertRCReturn(rc, rc);
11670	}
11671	else
11672	Assert( rcStrict == VINF_GIM_R3_HYPERCALL
11673	\|\| rcStrict == VINF_GIM_HYPERCALL_CONTINUING
11674	\|\| RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
11675
11676	/* If the hypercall changes anything other than guest's general-purpose registers,
11677	we would need to reload the guest changed bits here before VM-entry. */
11678	}
11679	else
11680	Log4(("hmR0VmxExitVmcall: Hypercalls not enabled\n"));
11681
11682	/* If hypercalls are disabled or the hypercall failed for some reason, raise #UD and continue. */
11683	if (RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)))
11684	{
11685	hmR0VmxSetPendingXcptUD(pVCpu, pMixedCtx);
11686	rcStrict = VINF_SUCCESS;
11687	}
11688
11689	return rcStrict;
11690	}
11691
11692
11693	/**
11694	* VM-exit handler for INVLPG (VMX_EXIT_INVLPG). Conditional VM-exit.
11695	*/
11696	HMVMX_EXIT_DECL hmR0VmxExitInvlpg(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11697	{
11698	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11699	PVM pVM = pVCpu->CTX_SUFF(pVM);
11700	Assert(!pVM->hm.s.fNestedPaging \|\| pVCpu->hm.s.fUsingDebugLoop);
11701
11702	int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
11703	rc \|= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
11704	AssertRCReturn(rc, rc);
11705
11706	VBOXSTRICTRC rcStrict = EMInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx), pVmxTransient->uExitQualification);
11707	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
11708	rcStrict = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11709	else
11710	AssertMsg(rcStrict == VERR_EM_INTERPRETER, ("hmR0VmxExitInvlpg: EMInterpretInvlpg %#RX64 failed with %Rrc\n",
11711	pVmxTransient->uExitQualification, VBOXSTRICTRC_VAL(rcStrict)));
11712	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
11713	return rcStrict;
11714	}
11715
11716
11717	/**
11718	* VM-exit handler for MONITOR (VMX_EXIT_MONITOR). Conditional VM-exit.
11719	*/
11720	HMVMX_EXIT_DECL hmR0VmxExitMonitor(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11721	{
11722	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11723	int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
11724	rc \|= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
11725	rc \|= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
11726	AssertRCReturn(rc, rc);
11727
11728	PVM pVM = pVCpu->CTX_SUFF(pVM);
11729	rc = EMInterpretMonitor(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
11730	if (RT_LIKELY(rc == VINF_SUCCESS))
11731	rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11732	else
11733	{
11734	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0VmxExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
11735	rc = VERR_EM_INTERPRETER;
11736	}
11737	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
11738	return rc;
11739	}
11740
11741
11742	/**
11743	* VM-exit handler for MWAIT (VMX_EXIT_MWAIT). Conditional VM-exit.
11744	*/
11745	HMVMX_EXIT_DECL hmR0VmxExitMwait(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11746	{
11747	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11748	int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
11749	rc \|= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
11750	rc \|= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
11751	AssertRCReturn(rc, rc);
11752
11753	PVM pVM = pVCpu->CTX_SUFF(pVM);
11754	VBOXSTRICTRC rc2 = EMInterpretMWait(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
11755	rc = VBOXSTRICTRC_VAL(rc2);
11756	if (RT_LIKELY( rc == VINF_SUCCESS
11757	\|\| rc == VINF_EM_HALT))
11758	{
11759	int rc3 = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11760	AssertRCReturn(rc3, rc3);
11761
11762	if ( rc == VINF_EM_HALT
11763	&& EMMonitorWaitShouldContinue(pVCpu, pMixedCtx))
11764	{
11765	rc = VINF_SUCCESS;
11766	}
11767	}
11768	else
11769	{
11770	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0VmxExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
11771	rc = VERR_EM_INTERPRETER;
11772	}
11773	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
11774	("hmR0VmxExitMwait: failed, invalid error code %Rrc\n", rc));
11775	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
11776	return rc;
11777	}
11778
11779
11780	/**
11781	* VM-exit handler for RSM (VMX_EXIT_RSM). Unconditional VM-exit.
11782	*/
11783	HMVMX_EXIT_NSRC_DECL hmR0VmxExitRsm(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11784	{
11785	/*
11786	* Execution of RSM outside of SMM mode causes #UD regardless of VMX root or VMX non-root mode. In theory, we should never
11787	* get this VM-exit. This can happen only if dual-monitor treatment of SMI and VMX is enabled, which can (only?) be done by
11788	* executing VMCALL in VMX root operation. If we get here, something funny is going on.
11789	* See Intel spec. "33.15.5 Enabling the Dual-Monitor Treatment".
11790	*/
11791	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11792	AssertMsgFailed(("Unexpected RSM VM-exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
11793	HMVMX_RETURN_UNEXPECTED_EXIT();
11794	}
11795
11796
11797	/**
11798	* VM-exit handler for SMI (VMX_EXIT_SMI). Unconditional VM-exit.
11799	*/
11800	HMVMX_EXIT_NSRC_DECL hmR0VmxExitSmi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11801	{
11802	/*
11803	* This can only happen if we support dual-monitor treatment of SMI, which can be activated by executing VMCALL in VMX
11804	* root operation. Only an STM (SMM transfer monitor) would get this VM-exit when we (the executive monitor) execute a VMCALL
11805	* in VMX root mode or receive an SMI. If we get here, something funny is going on.
11806	* See Intel spec. "33.15.6 Activating the Dual-Monitor Treatment" and Intel spec. 25.3 "Other Causes of VM-Exits"
11807	*/
11808	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11809	AssertMsgFailed(("Unexpected SMI VM-exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
11810	HMVMX_RETURN_UNEXPECTED_EXIT();
11811	}
11812
11813
11814	/**
11815	* VM-exit handler for IO SMI (VMX_EXIT_IO_SMI). Unconditional VM-exit.
11816	*/
11817	HMVMX_EXIT_NSRC_DECL hmR0VmxExitIoSmi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11818	{
11819	/* Same treatment as VMX_EXIT_SMI. See comment in hmR0VmxExitSmi(). */
11820	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11821	AssertMsgFailed(("Unexpected IO SMI VM-exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
11822	HMVMX_RETURN_UNEXPECTED_EXIT();
11823	}
11824
11825
11826	/**
11827	* VM-exit handler for SIPI (VMX_EXIT_SIPI). Conditional VM-exit.
11828	*/
11829	HMVMX_EXIT_NSRC_DECL hmR0VmxExitSipi(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11830	{
11831	/*
11832	* SIPI exits can only occur in VMX non-root operation when the "wait-for-SIPI" guest activity state is used. We currently
11833	* don't make use of it (see hmR0VmxLoadGuestActivityState()) as our guests don't have direct access to the host LAPIC.
11834	* See Intel spec. 25.3 "Other Causes of VM-exits".
11835	*/
11836	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11837	AssertMsgFailed(("Unexpected SIPI VM-exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
11838	HMVMX_RETURN_UNEXPECTED_EXIT();
11839	}
11840
11841
11842	/**
11843	* VM-exit handler for INIT signal (VMX_EXIT_INIT_SIGNAL). Unconditional
11844	* VM-exit.
11845	*/
11846	HMVMX_EXIT_NSRC_DECL hmR0VmxExitInitSignal(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11847	{
11848	/*
11849	* INIT signals are blocked in VMX root operation by VMXON and by SMI in SMM.
11850	* See Intel spec. 33.14.1 Default Treatment of SMI Delivery" and Intel spec. 29.3 "VMX Instructions" for "VMXON".
11851	*
11852	* It is -NOT- blocked in VMX non-root operation so we can, in theory, still get these VM-exits.
11853	* See Intel spec. "23.8 Restrictions on VMX operation".
11854	*/
11855	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11856	return VINF_SUCCESS;
11857	}
11858
11859
11860	/**
11861	* VM-exit handler for triple faults (VMX_EXIT_TRIPLE_FAULT). Unconditional
11862	* VM-exit.
11863	*/
11864	HMVMX_EXIT_DECL hmR0VmxExitTripleFault(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11865	{
11866	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11867	return VINF_EM_RESET;
11868	}
11869
11870
11871	/**
11872	* VM-exit handler for HLT (VMX_EXIT_HLT). Conditional VM-exit.
11873	*/
11874	HMVMX_EXIT_DECL hmR0VmxExitHlt(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11875	{
11876	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11877	Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
11878
11879	int rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
11880	AssertRCReturn(rc, rc);
11881
11882	if (EMShouldContinueAfterHalt(pVCpu, pMixedCtx)) /* Requires eflags. */
11883	rc = VINF_SUCCESS;
11884	else
11885	rc = VINF_EM_HALT;
11886
11887	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
11888	if (rc != VINF_SUCCESS)
11889	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
11890	return rc;
11891	}
11892
11893
11894	/**
11895	* VM-exit handler for instructions that result in a \#UD exception delivered to
11896	* the guest.
11897	*/
11898	HMVMX_EXIT_NSRC_DECL hmR0VmxExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11899	{
11900	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11901	hmR0VmxSetPendingXcptUD(pVCpu, pMixedCtx);
11902	return VINF_SUCCESS;
11903	}
11904
11905
11906	/**
11907	* VM-exit handler for expiry of the VMX preemption timer.
11908	*/
11909	HMVMX_EXIT_DECL hmR0VmxExitPreemptTimer(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11910	{
11911	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11912
11913	/* If the preemption-timer has expired, reinitialize the preemption timer on next VM-entry. */
11914	pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
11915
11916	/* If there are any timer events pending, fall back to ring-3, otherwise resume guest execution. */
11917	PVM pVM = pVCpu->CTX_SUFF(pVM);
11918	bool fTimersPending = TMTimerPollBool(pVM, pVCpu);
11919	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPreemptTimer);
11920	return fTimersPending ? VINF_EM_RAW_TIMER_PENDING : VINF_SUCCESS;
11921	}
11922
11923
11924	/**
11925	* VM-exit handler for XSETBV (VMX_EXIT_XSETBV). Unconditional VM-exit.
11926	*/
11927	HMVMX_EXIT_DECL hmR0VmxExitXsetbv(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11928	{
11929	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11930
11931	int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
11932	rc \|= hmR0VmxSaveGuestRegsForIemExec(pVCpu, pMixedCtx, false /fMemory/, false /fNeedRsp/);
11933	rc \|= hmR0VmxSaveGuestCR4(pVCpu, pMixedCtx);
11934	AssertRCReturn(rc, rc);
11935
11936	VBOXSTRICTRC rcStrict = IEMExecDecodedXsetbv(pVCpu, pVmxTransient->cbInstr);
11937	HMCPU_CF_SET(pVCpu, rcStrict != VINF_IEM_RAISED_XCPT ? HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS : HM_CHANGED_ALL_GUEST);
11938
11939	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pMixedCtx->cr4 & X86_CR4_OSXSAVE) && pMixedCtx->aXcr[0] != ASMGetXcr0();
11940
11941	return rcStrict;
11942	}
11943
11944
11945	/**
11946	* VM-exit handler for INVPCID (VMX_EXIT_INVPCID). Conditional VM-exit.
11947	*/
11948	HMVMX_EXIT_DECL hmR0VmxExitInvpcid(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11949	{
11950	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
11951
11952	/* The guest should not invalidate the host CPU's TLBs, fallback to interpreter. */
11953	/** @todo implement EMInterpretInvpcid() */
11954	return VERR_EM_INTERPRETER;
11955	}
11956
11957
11958	/**
11959	* VM-exit handler for invalid-guest-state (VMX_EXIT_ERR_INVALID_GUEST_STATE).
11960	* Error VM-exit.
11961	*/
11962	HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrInvalidGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
11963	{
11964	int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
11965	AssertRCReturn(rc, rc);
11966
11967	rc = hmR0VmxCheckVmcsCtls(pVCpu);
11968	AssertRCReturn(rc, rc);
11969
11970	uint32_t uInvalidReason = hmR0VmxCheckGuestState(pVCpu->CTX_SUFF(pVM), pVCpu, pMixedCtx);
11971	NOREF(uInvalidReason);
11972
11973	#ifdef VBOX_STRICT
11974	uint32_t uIntrState;
11975	RTHCUINTREG uHCReg;
11976	uint64_t u64Val;
11977	uint32_t u32Val;
11978
11979	rc = hmR0VmxReadEntryIntInfoVmcs(pVmxTransient);
11980	rc \|= hmR0VmxReadEntryXcptErrorCodeVmcs(pVmxTransient);
11981	rc \|= hmR0VmxReadEntryInstrLenVmcs(pVmxTransient);
11982	rc \|= VMXReadVmcs32(VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE, &uIntrState);
11983	AssertRCReturn(rc, rc);
11984
11985	Log4(("uInvalidReason %u\n", uInvalidReason));
11986	Log4(("VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO %#RX32\n", pVmxTransient->uEntryIntInfo));
11987	Log4(("VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE %#RX32\n", pVmxTransient->uEntryXcptErrorCode));
11988	Log4(("VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH %#RX32\n", pVmxTransient->cbEntryInstr));
11989	Log4(("VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE %#RX32\n", uIntrState));
11990
11991	rc = VMXReadVmcs32(VMX_VMCS_GUEST_CR0, &u32Val); AssertRC(rc);
11992	Log4(("VMX_VMCS_GUEST_CR0 %#RX32\n", u32Val));
11993	rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_MASK, &uHCReg); AssertRC(rc);
11994	Log4(("VMX_VMCS_CTRL_CR0_MASK %#RHr\n", uHCReg));
11995	rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR0_READ_SHADOW, &uHCReg); AssertRC(rc);
11996	Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
11997	rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_MASK, &uHCReg); AssertRC(rc);
11998	Log4(("VMX_VMCS_CTRL_CR4_MASK %#RHr\n", uHCReg));
11999	rc = VMXReadVmcsHstN(VMX_VMCS_CTRL_CR4_READ_SHADOW, &uHCReg); AssertRC(rc);
12000	Log4(("VMX_VMCS_CTRL_CR4_READ_SHADOW %#RHr\n", uHCReg));
12001	rc = VMXReadVmcs64(VMX_VMCS64_CTRL_EPTP_FULL, &u64Val); AssertRC(rc);
12002	Log4(("VMX_VMCS64_CTRL_EPTP_FULL %#RX64\n", u64Val));
12003	#else
12004	NOREF(pVmxTransient);
12005	#endif
12006
12007	hmDumpRegs(pVCpu->CTX_SUFF(pVM), pVCpu, pMixedCtx);
12008	return VERR_VMX_INVALID_GUEST_STATE;
12009	}
12010
12011
12012	/**
12013	* VM-exit handler for VM-entry failure due to an MSR-load
12014	* (VMX_EXIT_ERR_MSR_LOAD). Error VM-exit.
12015	*/
12016	HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrMsrLoad(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12017	{
12018	NOREF(pVmxTransient);
12019	AssertMsgFailed(("Unexpected MSR-load exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx)); NOREF(pMixedCtx);
12020	HMVMX_RETURN_UNEXPECTED_EXIT();
12021	}
12022
12023
12024	/**
12025	* VM-exit handler for VM-entry failure due to a machine-check event
12026	* (VMX_EXIT_ERR_MACHINE_CHECK). Error VM-exit.
12027	*/
12028	HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrMachineCheck(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12029	{
12030	NOREF(pVmxTransient);
12031	AssertMsgFailed(("Unexpected machine-check event exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx)); NOREF(pMixedCtx);
12032	HMVMX_RETURN_UNEXPECTED_EXIT();
12033	}
12034
12035
12036	/**
12037	* VM-exit handler for all undefined reasons. Should never ever happen.. in
12038	* theory.
12039	*/
12040	HMVMX_EXIT_NSRC_DECL hmR0VmxExitErrUndefined(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12041	{
12042	AssertMsgFailed(("Huh!? Undefined VM-exit reason %d. pVCpu=%p pMixedCtx=%p\n", pVmxTransient->uExitReason, pVCpu, pMixedCtx));
12043	NOREF(pVCpu); NOREF(pMixedCtx); NOREF(pVmxTransient);
12044	return VERR_VMX_UNDEFINED_EXIT_CODE;
12045	}
12046
12047
12048	/**
12049	* VM-exit handler for XDTR (LGDT, SGDT, LIDT, SIDT) accesses
12050	* (VMX_EXIT_XDTR_ACCESS) and LDT and TR access (LLDT, LTR, SLDT, STR).
12051	* Conditional VM-exit.
12052	*/
12053	HMVMX_EXIT_DECL hmR0VmxExitXdtrAccess(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12054	{
12055	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12056
12057	/* By default, we don't enable VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT. */
12058	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitXdtrAccess);
12059	if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT)
12060	return VERR_EM_INTERPRETER;
12061	AssertMsgFailed(("Unexpected XDTR access. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
12062	HMVMX_RETURN_UNEXPECTED_EXIT();
12063	}
12064
12065
12066	/**
12067	* VM-exit handler for RDRAND (VMX_EXIT_RDRAND). Conditional VM-exit.
12068	*/
12069	HMVMX_EXIT_DECL hmR0VmxExitRdrand(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12070	{
12071	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12072
12073	/* By default, we don't enable VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT. */
12074	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdrand);
12075	if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT)
12076	return VERR_EM_INTERPRETER;
12077	AssertMsgFailed(("Unexpected RDRAND exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
12078	HMVMX_RETURN_UNEXPECTED_EXIT();
12079	}
12080
12081
12082	/**
12083	* VM-exit handler for RDMSR (VMX_EXIT_RDMSR).
12084	*/
12085	HMVMX_EXIT_DECL hmR0VmxExitRdmsr(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12086	{
12087	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12088
12089	/* EMInterpretRdmsr() requires CR0, Eflags and SS segment register. */
12090	int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
12091	rc \|= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
12092	rc \|= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
12093	if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS))
12094	{
12095	rc \|= hmR0VmxSaveGuestLazyMsrs(pVCpu, pMixedCtx);
12096	rc \|= hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx);
12097	}
12098	AssertRCReturn(rc, rc);
12099	Log4(("ecx=%#RX32\n", pMixedCtx->ecx));
12100
12101	#ifdef VBOX_STRICT
12102	if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
12103	{
12104	if ( hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, pMixedCtx->ecx)
12105	&& pMixedCtx->ecx != MSR_K6_EFER)
12106	{
12107	AssertMsgFailed(("Unexpected RDMSR for an MSR in the auto-load/store area in the VMCS. ecx=%#RX32\n",
12108	pMixedCtx->ecx));
12109	HMVMX_RETURN_UNEXPECTED_EXIT();
12110	}
12111	if (hmR0VmxIsLazyGuestMsr(pVCpu, pMixedCtx->ecx))
12112	{
12113	VMXMSREXITREAD enmRead;
12114	VMXMSREXITWRITE enmWrite;
12115	int rc2 = hmR0VmxGetMsrPermission(pVCpu, pMixedCtx->ecx, &enmRead, &enmWrite);
12116	AssertRCReturn(rc2, rc2);
12117	if (enmRead == VMXMSREXIT_PASSTHRU_READ)
12118	{
12119	AssertMsgFailed(("Unexpected RDMSR for a passthru lazy-restore MSR. ecx=%#RX32\n", pMixedCtx->ecx));
12120	HMVMX_RETURN_UNEXPECTED_EXIT();
12121	}
12122	}
12123	}
12124	#endif
12125
12126	PVM pVM = pVCpu->CTX_SUFF(pVM);
12127	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
12128	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER,
12129	("hmR0VmxExitRdmsr: failed, invalid error code %Rrc\n", rc));
12130	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
12131	if (RT_SUCCESS(rc))
12132	{
12133	rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
12134	Assert(pVmxTransient->cbInstr == 2);
12135	}
12136	return rc;
12137	}
12138
12139
12140	/**
12141	* VM-exit handler for WRMSR (VMX_EXIT_WRMSR).
12142	*/
12143	HMVMX_EXIT_DECL hmR0VmxExitWrmsr(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12144	{
12145	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12146	PVM pVM = pVCpu->CTX_SUFF(pVM);
12147	int rc = VINF_SUCCESS;
12148
12149	/* EMInterpretWrmsr() requires CR0, EFLAGS and SS segment register. */
12150	rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
12151	rc \|= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx);
12152	rc \|= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
12153	if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS))
12154	{
12155	rc \|= hmR0VmxSaveGuestLazyMsrs(pVCpu, pMixedCtx);
12156	rc \|= hmR0VmxSaveGuestAutoLoadStoreMsrs(pVCpu, pMixedCtx);
12157	}
12158	AssertRCReturn(rc, rc);
12159	Log4(("ecx=%#RX32 edx:eax=%#RX32:%#RX32\n", pMixedCtx->ecx, pMixedCtx->edx, pMixedCtx->eax));
12160
12161	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
12162	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER, ("hmR0VmxExitWrmsr: failed, invalid error code %Rrc\n", rc));
12163	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
12164
12165	if (RT_SUCCESS(rc))
12166	{
12167	rc = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
12168
12169	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
12170	if ( pMixedCtx->ecx == MSR_IA32_APICBASE
12171	\|\| ( pMixedCtx->ecx >= MSR_IA32_X2APIC_START
12172	&& pMixedCtx->ecx <= MSR_IA32_X2APIC_END))
12173	{
12174	/*
12175	* We've already saved the APIC related guest-state (TPR) in hmR0VmxPostRunGuest(). When full APIC register
12176	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCS before
12177	* EMInterpretWrmsr() changes it.
12178	*/
12179	HMCPU_CF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
12180	}
12181	else if (pMixedCtx->ecx == MSR_IA32_TSC) /* Windows 7 does this during bootup. See @bugref{6398}. */
12182	pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
12183	else if (pMixedCtx->ecx == MSR_K6_EFER)
12184	{
12185	/*
12186	* If the guest touches EFER we need to update the VM-Entry and VM-Exit controls as well,
12187	* even if it is -not- touching bits that cause paging mode changes (LMA/LME). We care about
12188	* the other bits as well, SCE and NXE. See @bugref{7368}.
12189	*/
12190	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR \| HM_CHANGED_VMX_ENTRY_CTLS \| HM_CHANGED_VMX_EXIT_CTLS);
12191	}
12192
12193	/* Update MSRs that are part of the VMCS and auto-load/store area when MSR-bitmaps are not supported. */
12194	if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS))
12195	{
12196	switch (pMixedCtx->ecx)
12197	{
12198	/*
12199	* For SYSENTER CS, EIP, ESP MSRs, we set both the flags here so we don't accidentally
12200	* overwrite the changed guest-CPU context value while going to ring-3, see @bufref{8745}.
12201	*/
12202	case MSR_IA32_SYSENTER_CS:
12203	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR);
12204	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_CS_MSR);
12205	break;
12206	case MSR_IA32_SYSENTER_EIP:
12207	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR);
12208	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_EIP_MSR);
12209	break;
12210	case MSR_IA32_SYSENTER_ESP:
12211	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR);
12212	HMVMXCPU_GST_SET_UPDATED(pVCpu, HMVMX_UPDATED_GUEST_SYSENTER_ESP_MSR);
12213	break;
12214	case MSR_K8_FS_BASE: /* fall thru */
12215	case MSR_K8_GS_BASE: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS); break;
12216	case MSR_K6_EFER: /* already handled above */ break;
12217	default:
12218	{
12219	if (hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, pMixedCtx->ecx))
12220	HMCPU_CF_SET(pVCpu, HM_CHANGED_VMX_GUEST_AUTO_MSRS);
12221	else if (hmR0VmxIsLazyGuestMsr(pVCpu, pMixedCtx->ecx))
12222	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
12223	break;
12224	}
12225	}
12226	}
12227	#ifdef VBOX_STRICT
12228	else
12229	{
12230	/* Paranoia. Validate that MSRs in the MSR-bitmaps with write-passthru are not intercepted. */
12231	switch (pMixedCtx->ecx)
12232	{
12233	case MSR_IA32_SYSENTER_CS:
12234	case MSR_IA32_SYSENTER_EIP:
12235	case MSR_IA32_SYSENTER_ESP:
12236	case MSR_K8_FS_BASE:
12237	case MSR_K8_GS_BASE:
12238	{
12239	AssertMsgFailed(("Unexpected WRMSR for an MSR in the VMCS. ecx=%#RX32\n", pMixedCtx->ecx));
12240	HMVMX_RETURN_UNEXPECTED_EXIT();
12241	}
12242
12243	/* Writes to MSRs in auto-load/store area/swapped MSRs, shouldn't cause VM-exits with MSR-bitmaps. */
12244	default:
12245	{
12246	if (hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, pMixedCtx->ecx))
12247	{
12248	/* EFER writes are always intercepted, see hmR0VmxLoadGuestMsrs(). */
12249	if (pMixedCtx->ecx != MSR_K6_EFER)
12250	{
12251	AssertMsgFailed(("Unexpected WRMSR for an MSR in the auto-load/store area in the VMCS. ecx=%#RX32\n",
12252	pMixedCtx->ecx));
12253	HMVMX_RETURN_UNEXPECTED_EXIT();
12254	}
12255	}
12256
12257	if (hmR0VmxIsLazyGuestMsr(pVCpu, pMixedCtx->ecx))
12258	{
12259	VMXMSREXITREAD enmRead;
12260	VMXMSREXITWRITE enmWrite;
12261	int rc2 = hmR0VmxGetMsrPermission(pVCpu, pMixedCtx->ecx, &enmRead, &enmWrite);
12262	AssertRCReturn(rc2, rc2);
12263	if (enmWrite == VMXMSREXIT_PASSTHRU_WRITE)
12264	{
12265	AssertMsgFailed(("Unexpected WRMSR for passthru, lazy-restore MSR. ecx=%#RX32\n", pMixedCtx->ecx));
12266	HMVMX_RETURN_UNEXPECTED_EXIT();
12267	}
12268	}
12269	break;
12270	}
12271	}
12272	}
12273	#endif /* VBOX_STRICT */
12274	}
12275	return rc;
12276	}
12277
12278
12279	/**
12280	* VM-exit handler for PAUSE (VMX_EXIT_PAUSE). Conditional VM-exit.
12281	*/
12282	HMVMX_EXIT_DECL hmR0VmxExitPause(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12283	{
12284	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12285
12286	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPause);
12287	return VINF_EM_RAW_INTERRUPT;
12288	}
12289
12290
12291	/**
12292	* VM-exit handler for when the TPR value is lowered below the specified
12293	* threshold (VMX_EXIT_TPR_BELOW_THRESHOLD). Conditional VM-exit.
12294	*/
12295	HMVMX_EXIT_NSRC_DECL hmR0VmxExitTprBelowThreshold(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12296	{
12297	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12298	Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
12299
12300	/*
12301	* The TPR shadow would've been synced with the APIC TPR in hmR0VmxPostRunGuest(). We'll re-evaluate
12302	* pending interrupts and inject them before the next VM-entry so we can just continue execution here.
12303	*/
12304	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTprBelowThreshold);
12305	return VINF_SUCCESS;
12306	}
12307
12308
12309	/**
12310	* VM-exit handler for control-register accesses (VMX_EXIT_MOV_CRX). Conditional
12311	* VM-exit.
12312	*
12313	* @retval VINF_SUCCESS when guest execution can continue.
12314	* @retval VINF_PGM_CHANGE_MODE when shadow paging mode changed, back to ring-3.
12315	* @retval VINF_PGM_SYNC_CR3 CR3 sync is required, back to ring-3.
12316	* @retval VERR_EM_INTERPRETER when something unexpected happened, fallback to
12317	* interpreter.
12318	*/
12319	HMVMX_EXIT_DECL hmR0VmxExitMovCRx(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12320	{
12321	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12322	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitMovCRx, y2);
12323	int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
12324	rc \|= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
12325	AssertRCReturn(rc, rc);
12326
12327	RTGCUINTPTR const uExitQualification = pVmxTransient->uExitQualification;
12328	uint32_t const uAccessType = VMX_EXIT_QUALIFICATION_CRX_ACCESS(uExitQualification);
12329	PVM pVM = pVCpu->CTX_SUFF(pVM);
12330	VBOXSTRICTRC rcStrict;
12331	rc = hmR0VmxSaveGuestRegsForIemExec(pVCpu, pMixedCtx, false /fMemory/, true /fNeedRsp/);
12332	switch (uAccessType)
12333	{
12334	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE: /* MOV to CRx */
12335	{
12336	rc \|= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
12337	AssertRCReturn(rc, rc);
12338
12339	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, pVmxTransient->cbInstr,
12340	VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification),
12341	VMX_EXIT_QUALIFICATION_CRX_GENREG(uExitQualification));
12342	AssertMsg( rcStrict == VINF_SUCCESS \|\| rcStrict == VINF_IEM_RAISED_XCPT \|\| rcStrict == VINF_PGM_CHANGE_MODE
12343	\|\| rcStrict == VINF_PGM_SYNC_CR3, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12344	switch (VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification))
12345	{
12346	case 0: /* CR0 */
12347	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
12348	Log4(("CRX CR0 write rcStrict=%Rrc CR0=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), pMixedCtx->cr0));
12349	break;
12350	case 2: /* CR2 */
12351	/* Nothing to do here, CR2 it's not part of the VMCS. */
12352	break;
12353	case 3: /* CR3 */
12354	Assert(!pVM->hm.s.fNestedPaging \|\| !CPUMIsGuestPagingEnabledEx(pMixedCtx) \|\| pVCpu->hm.s.fUsingDebugLoop);
12355	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
12356	Log4(("CRX CR3 write rcStrict=%Rrc CR3=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict), pMixedCtx->cr3));
12357	break;
12358	case 4: /* CR4 */
12359	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
12360	Log4(("CRX CR4 write rc=%Rrc CR4=%#RX64 fLoadSaveGuestXcr0=%u\n",
12361	VBOXSTRICTRC_VAL(rcStrict), pMixedCtx->cr4, pVCpu->hm.s.fLoadSaveGuestXcr0));
12362	break;
12363	case 8: /* CR8 */
12364	Assert(!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW));
12365	/* CR8 contains the APIC TPR. Was updated by IEMExecDecodedMovCRxWrite(). */
12366	HMCPU_CF_SET(pVCpu, HM_CHANGED_VMX_GUEST_APIC_STATE);
12367	break;
12368	default:
12369	AssertMsgFailed(("Invalid CRx register %#x\n", VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification)));
12370	break;
12371	}
12372
12373	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxWrite[VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification)]);
12374	break;
12375	}
12376
12377	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ: /* MOV from CRx */
12378	{
12379	rc \|= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
12380	AssertRCReturn(rc, rc);
12381
12382	Assert( !pVM->hm.s.fNestedPaging
12383	\|\| !CPUMIsGuestPagingEnabledEx(pMixedCtx)
12384	\|\| pVCpu->hm.s.fUsingDebugLoop
12385	\|\| VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification) != 3);
12386
12387	/* CR8 reads only cause a VM-exit when the TPR shadow feature isn't enabled. */
12388	Assert( VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification) != 8
12389	\|\| !(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW));
12390
12391	rcStrict = IEMExecDecodedMovCRxRead(pVCpu, pVmxTransient->cbInstr,
12392	VMX_EXIT_QUALIFICATION_CRX_GENREG(uExitQualification),
12393	VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification));
12394	AssertMsg(rcStrict == VINF_SUCCESS \|\| rcStrict == VINF_IEM_RAISED_XCPT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12395	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification)]);
12396	Log4(("CRX CR%d Read access rcStrict=%Rrc\n", VMX_EXIT_QUALIFICATION_CRX_REGISTER(uExitQualification),
12397	VBOXSTRICTRC_VAL(rcStrict)));
12398	break;
12399	}
12400
12401	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS: /* CLTS (Clear Task-Switch Flag in CR0) */
12402	{
12403	AssertRCReturn(rc, rc);
12404	rcStrict = IEMExecDecodedClts(pVCpu, pVmxTransient->cbInstr);
12405	AssertMsg(rcStrict == VINF_SUCCESS \|\| rcStrict == VINF_IEM_RAISED_XCPT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12406	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
12407	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClts);
12408	Log4(("CRX CLTS rcStrict=%d\n", VBOXSTRICTRC_VAL(rcStrict)));
12409	break;
12410	}
12411
12412	case VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW: /* LMSW (Load Machine-Status Word into CR0) */
12413	{
12414	AssertRCReturn(rc, rc);
12415	rcStrict = IEMExecDecodedLmsw(pVCpu, pVmxTransient->cbInstr,
12416	VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(uExitQualification));
12417	AssertMsg(rcStrict == VINF_SUCCESS \|\| rcStrict == VINF_IEM_RAISED_XCPT \|\| rcStrict == VINF_PGM_CHANGE_MODE,
12418	("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12419	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
12420	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitLmsw);
12421	Log4(("CRX LMSW rcStrict=%d\n", VBOXSTRICTRC_VAL(rcStrict)));
12422	break;
12423	}
12424
12425	default:
12426	AssertMsgFailedReturn(("Invalid access-type in Mov CRx VM-exit qualification %#x\n", uAccessType),
12427	VERR_VMX_UNEXPECTED_EXCEPTION);
12428	}
12429
12430	HMCPU_CF_SET(pVCpu, rcStrict != VINF_IEM_RAISED_XCPT ? HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS : HM_CHANGED_ALL_GUEST);
12431	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitMovCRx, y2);
12432	NOREF(pVM);
12433	return rcStrict;
12434	}
12435
12436
12437	/**
12438	* VM-exit handler for I/O instructions (VMX_EXIT_IO_INSTR). Conditional
12439	* VM-exit.
12440	*/
12441	HMVMX_EXIT_DECL hmR0VmxExitIoInstr(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12442	{
12443	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12444	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitIO, y1);
12445
12446	int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
12447	rc \|= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
12448	rc \|= hmR0VmxSaveGuestRip(pVCpu, pMixedCtx);
12449	rc \|= hmR0VmxSaveGuestRflags(pVCpu, pMixedCtx); /* Eflag checks in EMInterpretDisasCurrent(). */
12450	rc \|= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx); /* CR0 checks & PGM* in EMInterpretDisasCurrent(). */
12451	rc \|= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx); /* SELM checks in EMInterpretDisasCurrent(). */
12452	/* EFER also required for longmode checks in EMInterpretDisasCurrent(), but it's always up-to-date. */
12453	AssertRCReturn(rc, rc);
12454
12455	/* Refer Intel spec. 27-5. "Exit Qualifications for I/O Instructions" for the format. */
12456	uint32_t uIOPort = VMX_EXIT_QUALIFICATION_IO_PORT(pVmxTransient->uExitQualification);
12457	uint8_t uIOWidth = VMX_EXIT_QUALIFICATION_IO_WIDTH(pVmxTransient->uExitQualification);
12458	bool fIOWrite = ( VMX_EXIT_QUALIFICATION_IO_DIRECTION(pVmxTransient->uExitQualification)
12459	== VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT);
12460	bool fIOString = VMX_EXIT_QUALIFICATION_IO_IS_STRING(pVmxTransient->uExitQualification);
12461	bool fGstStepping = RT_BOOL(pMixedCtx->eflags.Bits.u1TF);
12462	bool fDbgStepping = pVCpu->hm.s.fSingleInstruction;
12463	AssertReturn(uIOWidth <= 3 && uIOWidth != 2, VERR_VMX_IPE_1);
12464
12465	/* I/O operation lookup arrays. */
12466	static uint32_t const s_aIOSizes[4] = { 1, 2, 0, 4 }; /* Size of the I/O accesses. */
12467	static uint32_t const s_aIOOpAnd[4] = { 0xff, 0xffff, 0, 0xffffffff }; /* AND masks for saving the result (in AL/AX/EAX). */
12468
12469	VBOXSTRICTRC rcStrict;
12470	uint32_t const cbValue = s_aIOSizes[uIOWidth];
12471	uint32_t const cbInstr = pVmxTransient->cbInstr;
12472	bool fUpdateRipAlready = false; /* ugly hack, should be temporary. */
12473	PVM pVM = pVCpu->CTX_SUFF(pVM);
12474	if (fIOString)
12475	{
12476	#ifdef VBOX_WITH_2ND_IEM_STEP /* This used to gurus with debian 32-bit guest without NP (on ATA reads).
12477	See @bugref{5752#c158}. Should work now. */
12478	/*
12479	* INS/OUTS - I/O String instruction.
12480	*
12481	* Use instruction-information if available, otherwise fall back on
12482	* interpreting the instruction.
12483	*/
12484	Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pMixedCtx->cs.Sel, pMixedCtx->rip, uIOPort, cbValue,
12485	fIOWrite ? 'w' : 'r'));
12486	AssertReturn(pMixedCtx->dx == uIOPort, VERR_VMX_IPE_2);
12487	if (MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo))
12488	{
12489	int rc2 = hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
12490	/** @todo optimize this, IEM should request the additional state if it needs it (GP, PF, ++). */
12491	rc2 \|= hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
12492	AssertRCReturn(rc2, rc2);
12493	AssertReturn(pVmxTransient->ExitInstrInfo.StrIo.u3AddrSize <= 2, VERR_VMX_IPE_3);
12494	AssertCompile(IEMMODE_16BIT == 0 && IEMMODE_32BIT == 1 && IEMMODE_64BIT == 2);
12495	IEMMODE enmAddrMode = (IEMMODE)pVmxTransient->ExitInstrInfo.StrIo.u3AddrSize;
12496	bool fRep = VMX_EXIT_QUALIFICATION_IO_IS_REP(pVmxTransient->uExitQualification);
12497	if (fIOWrite)
12498	{
12499	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, fRep, cbInstr,
12500	pVmxTransient->ExitInstrInfo.StrIo.iSegReg, true /fIoChecked/);
12501	}
12502	else
12503	{
12504	/*
12505	* The segment prefix for INS cannot be overridden and is always ES. We can safely assume X86_SREG_ES.
12506	* Hence "iSegReg" field is undefined in the instruction-information field in VT-x for INS.
12507	* See Intel Instruction spec. for "INS".
12508	* See Intel spec. Table 27-8 "Format of the VM-Exit Instruction-Information Field as Used for INS and OUTS".
12509	*/
12510	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, fRep, cbInstr, true /fIoChecked/);
12511	}
12512	}
12513	else
12514	{
12515	/** @todo optimize this, IEM should request the additional state if it needs it (GP, PF, ++). */
12516	int rc2 = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
12517	AssertRCReturn(rc2, rc2);
12518	rcStrict = IEMExecOne(pVCpu);
12519	}
12520	/** @todo IEM needs to be setting these flags somehow. */
12521	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
12522	fUpdateRipAlready = true;
12523	#else
12524	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
12525	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
12526	if (RT_SUCCESS(rcStrict))
12527	{
12528	if (fIOWrite)
12529	{
12530	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx), uIOPort, pDis->fPrefix,
12531	(DISCPUMODE)pDis->uAddrMode, cbValue);
12532	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
12533	}
12534	else
12535	{
12536	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx), uIOPort, pDis->fPrefix,
12537	(DISCPUMODE)pDis->uAddrMode, cbValue);
12538	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
12539	}
12540	}
12541	else
12542	{
12543	AssertMsg(rcStrict == VERR_EM_INTERPRETER, ("rcStrict=%Rrc RIP=%#RX64\n", VBOXSTRICTRC_VAL(rcStrict),
12544	pMixedCtx->rip));
12545	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
12546	}
12547	#endif
12548	}
12549	else
12550	{
12551	/*
12552	* IN/OUT - I/O instruction.
12553	*/
12554	Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c\n", pMixedCtx->cs.Sel, pMixedCtx->rip, uIOPort, cbValue, fIOWrite ? 'w' : 'r'));
12555	uint32_t const uAndVal = s_aIOOpAnd[uIOWidth];
12556	Assert(!VMX_EXIT_QUALIFICATION_IO_IS_REP(pVmxTransient->uExitQualification));
12557	if (fIOWrite)
12558	{
12559	rcStrict = IOMIOPortWrite(pVM, pVCpu, uIOPort, pMixedCtx->eax & uAndVal, cbValue);
12560	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
12561	}
12562	else
12563	{
12564	uint32_t u32Result = 0;
12565	rcStrict = IOMIOPortRead(pVM, pVCpu, uIOPort, &u32Result, cbValue);
12566	if (IOM_SUCCESS(rcStrict))
12567	{
12568	/* Save result of I/O IN instr. in AL/AX/EAX. */
12569	pMixedCtx->eax = (pMixedCtx->eax & ~uAndVal) \| (u32Result & uAndVal);
12570	}
12571	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
12572	HMR0SavePendingIOPortRead(pVCpu, pMixedCtx->rip, pMixedCtx->rip + cbInstr, uIOPort, uAndVal, cbValue);
12573	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
12574	}
12575	}
12576
12577	if (IOM_SUCCESS(rcStrict))
12578	{
12579	if (!fUpdateRipAlready)
12580	{
12581	hmR0VmxAdvanceGuestRipBy(pVCpu, pMixedCtx, cbInstr);
12582	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP);
12583	}
12584
12585	/*
12586	* INS/OUTS with REP prefix updates RFLAGS, can be observed with triple-fault guru while booting Fedora 17 64-bit guest.
12587	* See Intel Instruction reference for REP/REPE/REPZ/REPNE/REPNZ.
12588	*/
12589	if (fIOString)
12590	{
12591	/** @todo Single-step for INS/OUTS with REP prefix? */
12592	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RFLAGS);
12593	}
12594	else if ( !fDbgStepping
12595	&& fGstStepping)
12596	{
12597	hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
12598	}
12599
12600	/*
12601	* If any I/O breakpoints are armed, we need to check if one triggered
12602	* and take appropriate action.
12603	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
12604	*/
12605	int rc2 = hmR0VmxSaveGuestDR7(pVCpu, pMixedCtx);
12606	AssertRCReturn(rc2, rc2);
12607
12608	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
12609	* execution engines about whether hyper BPs and such are pending. */
12610	uint32_t const uDr7 = pMixedCtx->dr[7];
12611	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
12612	&& X86_DR7_ANY_RW_IO(uDr7)
12613	&& (pMixedCtx->cr4 & X86_CR4_DE))
12614	\|\| DBGFBpIsHwIoArmed(pVM)))
12615	{
12616	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
12617
12618	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
12619	VMMRZCallRing3Disable(pVCpu);
12620	HM_DISABLE_PREEMPT();
12621
12622	bool fIsGuestDbgActive = CPUMR0DebugStateMaybeSaveGuest(pVCpu, true /* fDr6 */);
12623
12624	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pMixedCtx, uIOPort, cbValue);
12625	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
12626	{
12627	/* Raise #DB. */
12628	if (fIsGuestDbgActive)
12629	ASMSetDR6(pMixedCtx->dr[6]);
12630	if (pMixedCtx->dr[7] != uDr7)
12631	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
12632
12633	hmR0VmxSetPendingXcptDB(pVCpu, pMixedCtx);
12634	}
12635	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
12636	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
12637	else if ( rcStrict2 != VINF_SUCCESS
12638	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
12639	rcStrict = rcStrict2;
12640	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
12641
12642	HM_RESTORE_PREEMPT();
12643	VMMRZCallRing3Enable(pVCpu);
12644	}
12645	}
12646
12647	#ifdef VBOX_STRICT
12648	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
12649	Assert(!fIOWrite);
12650	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE \|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE)
12651	Assert(fIOWrite);
12652	else
12653	{
12654	#if 0 /** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
12655	* statuses, that the VMM device and some others may return. See
12656	* IOM_SUCCESS() for guidance. */
12657	AssertMsg( RT_FAILURE(rcStrict)
12658	\|\| rcStrict == VINF_SUCCESS
12659	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
12660	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
12661	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
12662	\|\| rcStrict == VINF_EM_RAW_TO_R3
12663	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
12664	#endif
12665	}
12666	#endif
12667
12668	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitIO, y1);
12669	return rcStrict;
12670	}
12671
12672
12673	/**
12674	* VM-exit handler for task switches (VMX_EXIT_TASK_SWITCH). Unconditional
12675	* VM-exit.
12676	*/
12677	HMVMX_EXIT_DECL hmR0VmxExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12678	{
12679	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12680
12681	/* Check if this task-switch occurred while delivery an event through the guest IDT. */
12682	int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
12683	AssertRCReturn(rc, rc);
12684	if (VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(pVmxTransient->uExitQualification) == VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT)
12685	{
12686	rc = hmR0VmxReadIdtVectoringInfoVmcs(pVmxTransient);
12687	AssertRCReturn(rc, rc);
12688	if (VMX_IDT_VECTORING_INFO_VALID(pVmxTransient->uIdtVectoringInfo))
12689	{
12690	uint32_t uIntType = VMX_IDT_VECTORING_INFO_TYPE(pVmxTransient->uIdtVectoringInfo);
12691
12692	uint32_t uVector = VMX_IDT_VECTORING_INFO_VECTOR(pVmxTransient->uIdtVectoringInfo);
12693	bool fErrorCodeValid = VMX_IDT_VECTORING_INFO_ERROR_CODE_IS_VALID(pVmxTransient->uIdtVectoringInfo);
12694
12695	/* Save it as a pending event and it'll be converted to a TRPM event on the way out to ring-3. */
12696	Assert(!pVCpu->hm.s.Event.fPending);
12697	pVCpu->hm.s.Event.fPending = true;
12698	pVCpu->hm.s.Event.u64IntInfo = pVmxTransient->uIdtVectoringInfo;
12699	rc = hmR0VmxReadIdtVectoringErrorCodeVmcs(pVmxTransient);
12700	AssertRCReturn(rc, rc);
12701	if (fErrorCodeValid)
12702	pVCpu->hm.s.Event.u32ErrCode = pVmxTransient->uIdtVectoringErrorCode;
12703	else
12704	pVCpu->hm.s.Event.u32ErrCode = 0;
12705	if ( uIntType == VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT
12706	&& uVector == X86_XCPT_PF)
12707	{
12708	pVCpu->hm.s.Event.GCPtrFaultAddress = pMixedCtx->cr2;
12709	}
12710
12711	Log4(("Pending event on TaskSwitch uIntType=%#x uVector=%#x\n", uIntType, uVector));
12712	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
12713	return VINF_EM_RAW_INJECT_TRPM_EVENT;
12714	}
12715	}
12716
12717	/* Fall back to the interpreter to emulate the task-switch. */
12718	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
12719	return VERR_EM_INTERPRETER;
12720	}
12721
12722
12723	/**
12724	* VM-exit handler for monitor-trap-flag (VMX_EXIT_MTF). Conditional VM-exit.
12725	*/
12726	HMVMX_EXIT_DECL hmR0VmxExitMtf(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12727	{
12728	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12729	Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
12730	pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG;
12731	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
12732	AssertRCReturn(rc, rc);
12733	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMtf);
12734	return VINF_EM_DBG_STEPPED;
12735	}
12736
12737
12738	/**
12739	* VM-exit handler for APIC access (VMX_EXIT_APIC_ACCESS). Conditional VM-exit.
12740	*/
12741	HMVMX_EXIT_DECL hmR0VmxExitApicAccess(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12742	{
12743	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12744
12745	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitApicAccess);
12746
12747	/* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
12748	VBOXSTRICTRC rcStrict1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pMixedCtx, pVmxTransient);
12749	if (RT_LIKELY(rcStrict1 == VINF_SUCCESS))
12750	{
12751	/* For some crazy guest, if an event delivery causes an APIC-access VM-exit, go to instruction emulation. */
12752	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
12753	{
12754	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
12755	return VERR_EM_INTERPRETER;
12756	}
12757	}
12758	else
12759	{
12760	if (rcStrict1 == VINF_HM_DOUBLE_FAULT)
12761	rcStrict1 = VINF_SUCCESS;
12762	return rcStrict1;
12763	}
12764
12765	#if 0
12766	/** @todo Investigate if IOMMMIOPhysHandler() requires a lot of state, for now
12767	* just sync the whole thing. */
12768	int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
12769	#else
12770	/* Aggressive state sync. for now. */
12771	int rc = hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
12772	rc \|= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
12773	rc \|= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
12774	#endif
12775	rc \|= hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
12776	AssertRCReturn(rc, rc);
12777
12778	/* See Intel spec. 27-6 "Exit Qualifications for APIC-access VM-exits from Linear Accesses & Guest-Phyiscal Addresses" */
12779	uint32_t uAccessType = VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(pVmxTransient->uExitQualification);
12780	VBOXSTRICTRC rcStrict2;
12781	switch (uAccessType)
12782	{
12783	case VMX_APIC_ACCESS_TYPE_LINEAR_WRITE:
12784	case VMX_APIC_ACCESS_TYPE_LINEAR_READ:
12785	{
12786	AssertMsg( !(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
12787	\|\| VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification) != XAPIC_OFF_TPR,
12788	("hmR0VmxExitApicAccess: can't access TPR offset while using TPR shadowing.\n"));
12789
12790	RTGCPHYS GCPhys = pVCpu->hm.s.vmx.u64MsrApicBase; /* Always up-to-date, u64MsrApicBase is not part of the VMCS. */
12791	GCPhys &= PAGE_BASE_GC_MASK;
12792	GCPhys += VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification);
12793	PVM pVM = pVCpu->CTX_SUFF(pVM);
12794	Log4(("ApicAccess uAccessType=%#x GCPhys=%#RGp Off=%#x\n", uAccessType, GCPhys,
12795	VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification)));
12796
12797	rcStrict2 = IOMMMIOPhysHandler(pVM, pVCpu,
12798	uAccessType == VMX_APIC_ACCESS_TYPE_LINEAR_READ ? 0 : X86_TRAP_PF_RW,
12799	CPUMCTX2CORE(pMixedCtx), GCPhys);
12800	Log4(("ApicAccess rcStrict2=%d\n", VBOXSTRICTRC_VAL(rcStrict2)));
12801	if ( rcStrict2 == VINF_SUCCESS
12802	\|\| rcStrict2 == VERR_PAGE_TABLE_NOT_PRESENT
12803	\|\| rcStrict2 == VERR_PAGE_NOT_PRESENT)
12804	{
12805	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
12806	\| HM_CHANGED_GUEST_RSP
12807	\| HM_CHANGED_GUEST_RFLAGS
12808	\| HM_CHANGED_VMX_GUEST_APIC_STATE);
12809	rcStrict2 = VINF_SUCCESS;
12810	}
12811	break;
12812	}
12813
12814	default:
12815	Log4(("ApicAccess uAccessType=%#x\n", uAccessType));
12816	rcStrict2 = VINF_EM_RAW_EMULATE_INSTR;
12817	break;
12818	}
12819
12820	if (rcStrict2 != VINF_SUCCESS)
12821	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchApicAccessToR3);
12822	return rcStrict2;
12823	}
12824
12825
12826	/**
12827	* VM-exit handler for debug-register accesses (VMX_EXIT_MOV_DRX). Conditional
12828	* VM-exit.
12829	*/
12830	HMVMX_EXIT_DECL hmR0VmxExitMovDRx(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12831	{
12832	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12833
12834	/* We should -not- get this VM-exit if the guest's debug registers were active. */
12835	if (pVmxTransient->fWasGuestDebugStateActive)
12836	{
12837	AssertMsgFailed(("Unexpected MOV DRx exit. pVCpu=%p pMixedCtx=%p\n", pVCpu, pMixedCtx));
12838	HMVMX_RETURN_UNEXPECTED_EXIT();
12839	}
12840
12841	if ( !pVCpu->hm.s.fSingleInstruction
12842	&& !pVmxTransient->fWasHyperDebugStateActive)
12843	{
12844	Assert(!DBGFIsStepping(pVCpu));
12845	Assert(pVCpu->hm.s.vmx.u32XcptBitmap & RT_BIT_32(X86_XCPT_DB));
12846
12847	/* Don't intercept MOV DRx any more. */
12848	pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT;
12849	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
12850	AssertRCReturn(rc, rc);
12851
12852	/* We're playing with the host CPU state here, make sure we can't preempt or longjmp. */
12853	VMMRZCallRing3Disable(pVCpu);
12854	HM_DISABLE_PREEMPT();
12855
12856	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
12857	CPUMR0LoadGuestDebugState(pVCpu, true /* include DR6 */);
12858	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
12859
12860	HM_RESTORE_PREEMPT();
12861	VMMRZCallRing3Enable(pVCpu);
12862
12863	#ifdef VBOX_WITH_STATISTICS
12864	rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
12865	AssertRCReturn(rc, rc);
12866	if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(pVmxTransient->uExitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
12867	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
12868	else
12869	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
12870	#endif
12871	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
12872	return VINF_SUCCESS;
12873	}
12874
12875	/*
12876	* EMInterpretDRx[Write\|Read]() calls CPUMIsGuestIn64BitCode() which requires EFER, CS. EFER is always up-to-date.
12877	* Update the segment registers and DR7 from the CPU.
12878	*/
12879	int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
12880	rc \|= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
12881	rc \|= hmR0VmxSaveGuestDR7(pVCpu, pMixedCtx);
12882	AssertRCReturn(rc, rc);
12883	Log4(("CS:RIP=%04x:%08RX64\n", pMixedCtx->cs.Sel, pMixedCtx->rip));
12884
12885	PVM pVM = pVCpu->CTX_SUFF(pVM);
12886	if (VMX_EXIT_QUALIFICATION_DRX_DIRECTION(pVmxTransient->uExitQualification) == VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE)
12887	{
12888	rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx),
12889	VMX_EXIT_QUALIFICATION_DRX_REGISTER(pVmxTransient->uExitQualification),
12890	VMX_EXIT_QUALIFICATION_DRX_GENREG(pVmxTransient->uExitQualification));
12891	if (RT_SUCCESS(rc))
12892	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
12893	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
12894	}
12895	else
12896	{
12897	rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx),
12898	VMX_EXIT_QUALIFICATION_DRX_GENREG(pVmxTransient->uExitQualification),
12899	VMX_EXIT_QUALIFICATION_DRX_REGISTER(pVmxTransient->uExitQualification));
12900	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
12901	}
12902
12903	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
12904	if (RT_SUCCESS(rc))
12905	{
12906	int rc2 = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
12907	AssertRCReturn(rc2, rc2);
12908	return VINF_SUCCESS;
12909	}
12910	return rc;
12911	}
12912
12913
12914	/**
12915	* VM-exit handler for EPT misconfiguration (VMX_EXIT_EPT_MISCONFIG).
12916	* Conditional VM-exit.
12917	*/
12918	HMVMX_EXIT_DECL hmR0VmxExitEptMisconfig(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12919	{
12920	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12921	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
12922
12923	/* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
12924	VBOXSTRICTRC rcStrict1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pMixedCtx, pVmxTransient);
12925	if (RT_LIKELY(rcStrict1 == VINF_SUCCESS))
12926	{
12927	/* If event delivery causes an EPT misconfig (MMIO), go back to instruction emulation as otherwise
12928	injecting the original pending event would most likely cause the same EPT misconfig VM-exit. */
12929	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
12930	{
12931	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
12932	return VERR_EM_INTERPRETER;
12933	}
12934	}
12935	else
12936	{
12937	if (rcStrict1 == VINF_HM_DOUBLE_FAULT)
12938	rcStrict1 = VINF_SUCCESS;
12939	return rcStrict1;
12940	}
12941
12942	RTGCPHYS GCPhys = 0;
12943	int rc = VMXReadVmcs64(VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL, &GCPhys);
12944
12945	#if 0
12946	rc \|= hmR0VmxSaveGuestState(pVCpu, pMixedCtx); /** @todo Can we do better? */
12947	#else
12948	/* Aggressive state sync. for now. */
12949	rc \|= hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
12950	rc \|= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
12951	rc \|= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
12952	#endif
12953	AssertRCReturn(rc, rc);
12954
12955	/*
12956	* If we succeed, resume guest execution.
12957	* If we fail in interpreting the instruction because we couldn't get the guest physical address
12958	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
12959	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
12960	* weird case. See @bugref{6043}.
12961	*/
12962	PVM pVM = pVCpu->CTX_SUFF(pVM);
12963	VBOXSTRICTRC rcStrict2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, PGMMODE_EPT, CPUMCTX2CORE(pMixedCtx), GCPhys, UINT32_MAX);
12964	Log4(("EPT misconfig at %#RGp RIP=%#RX64 rc=%Rrc\n", GCPhys, pMixedCtx->rip, VBOXSTRICTRC_VAL(rcStrict2)));
12965	if ( rcStrict2 == VINF_SUCCESS
12966	\|\| rcStrict2 == VERR_PAGE_TABLE_NOT_PRESENT
12967	\|\| rcStrict2 == VERR_PAGE_NOT_PRESENT)
12968	{
12969	/* Successfully handled MMIO operation. */
12970	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
12971	\| HM_CHANGED_GUEST_RSP
12972	\| HM_CHANGED_GUEST_RFLAGS
12973	\| HM_CHANGED_VMX_GUEST_APIC_STATE);
12974	return VINF_SUCCESS;
12975	}
12976	return rcStrict2;
12977	}
12978
12979
12980	/**
12981	* VM-exit handler for EPT violation (VMX_EXIT_EPT_VIOLATION). Conditional
12982	* VM-exit.
12983	*/
12984	HMVMX_EXIT_DECL hmR0VmxExitEptViolation(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
12985	{
12986	HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
12987	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
12988
12989	/* If this VM-exit occurred while delivering an event through the guest IDT, handle it accordingly. */
12990	VBOXSTRICTRC rcStrict1 = hmR0VmxCheckExitDueToEventDelivery(pVCpu, pMixedCtx, pVmxTransient);
12991	if (RT_LIKELY(rcStrict1 == VINF_SUCCESS))
12992	{
12993	/* In the unlikely case that the EPT violation happened as a result of delivering an event, log it. */
12994	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
12995	Log4(("EPT violation with an event pending u64IntInfo=%#RX64\n", pVCpu->hm.s.Event.u64IntInfo));
12996	}
12997	else
12998	{
12999	if (rcStrict1 == VINF_HM_DOUBLE_FAULT)
13000	rcStrict1 = VINF_SUCCESS;
13001	return rcStrict1;
13002	}
13003
13004	RTGCPHYS GCPhys = 0;
13005	int rc = VMXReadVmcs64(VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL, &GCPhys);
13006	rc \|= hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
13007	#if 0
13008	rc \|= hmR0VmxSaveGuestState(pVCpu, pMixedCtx); /** @todo Can we do better? */
13009	#else
13010	/* Aggressive state sync. for now. */
13011	rc \|= hmR0VmxSaveGuestRipRspRflags(pVCpu, pMixedCtx);
13012	rc \|= hmR0VmxSaveGuestControlRegs(pVCpu, pMixedCtx);
13013	rc \|= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
13014	#endif
13015	AssertRCReturn(rc, rc);
13016
13017	/* Intel spec. Table 27-7 "Exit Qualifications for EPT violations". */
13018	AssertMsg(((pVmxTransient->uExitQualification >> 7) & 3) != 2, ("%#RX64", pVmxTransient->uExitQualification));
13019
13020	RTGCUINT uErrorCode = 0;
13021	if (pVmxTransient->uExitQualification & VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH)
13022	uErrorCode \|= X86_TRAP_PF_ID;
13023	if (pVmxTransient->uExitQualification & VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE)
13024	uErrorCode \|= X86_TRAP_PF_RW;
13025	if (pVmxTransient->uExitQualification & VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT)
13026	uErrorCode \|= X86_TRAP_PF_P;
13027
13028	TRPMAssertXcptPF(pVCpu, GCPhys, uErrorCode);
13029
13030	Log4(("EPT violation %#x at %#RX64 ErrorCode %#x CS:RIP=%04x:%08RX64\n", pVmxTransient->uExitQualification, GCPhys,
13031	uErrorCode, pMixedCtx->cs.Sel, pMixedCtx->rip));
13032
13033	/* Handle the pagefault trap for the nested shadow table. */
13034	PVM pVM = pVCpu->CTX_SUFF(pVM);
13035	VBOXSTRICTRC rcStrict2 = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, PGMMODE_EPT, uErrorCode, CPUMCTX2CORE(pMixedCtx), GCPhys);
13036	TRPMResetTrap(pVCpu);
13037
13038	/* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}. */
13039	if ( rcStrict2 == VINF_SUCCESS
13040	\|\| rcStrict2 == VERR_PAGE_TABLE_NOT_PRESENT
13041	\|\| rcStrict2 == VERR_PAGE_NOT_PRESENT)
13042	{
13043	/* Successfully synced our nested page tables. */
13044	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf);
13045	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
13046	\| HM_CHANGED_GUEST_RSP
13047	\| HM_CHANGED_GUEST_RFLAGS);
13048	return VINF_SUCCESS;
13049	}
13050
13051	Log4(("EPT return to ring-3 rcStrict2=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict2)));
13052	return rcStrict2;
13053	}
13054
13055	/** @} */
13056
13057	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-= */
13058	/* -=-=-=-=-=-=-=-=-=- VM-exit Exception Handlers -=-=-=-=-=-=-=-=-=-=- */
13059	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-= */
13060
13061	/** @name VM-exit exception handlers.
13062	* @{
13063	*/
13064
13065	/**
13066	* VM-exit exception handler for \#MF (Math Fault: floating point exception).
13067	*/
13068	static int hmR0VmxExitXcptMF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13069	{
13070	HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13071	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
13072
13073	int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
13074	AssertRCReturn(rc, rc);
13075
13076	if (!(pMixedCtx->cr0 & X86_CR0_NE))
13077	{
13078	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
13079	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
13080
13081	/** @todo r=ramshankar: The Intel spec. does -not- specify that this VM-exit
13082	* provides VM-exit instruction length. If this causes problem later,
13083	* disassemble the instruction like it's done on AMD-V. */
13084	int rc2 = hmR0VmxAdvanceGuestRip(pVCpu, pMixedCtx, pVmxTransient);
13085	AssertRCReturn(rc2, rc2);
13086	return rc;
13087	}
13088
13089	hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13090	pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13091	return rc;
13092	}
13093
13094
13095	/**
13096	* VM-exit exception handler for \#BP (Breakpoint exception).
13097	*/
13098	static int hmR0VmxExitXcptBP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13099	{
13100	HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13101	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
13102
13103	/** @todo Try optimize this by not saving the entire guest state unless
13104	* really needed. */
13105	int rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
13106	AssertRCReturn(rc, rc);
13107
13108	PVM pVM = pVCpu->CTX_SUFF(pVM);
13109	rc = DBGFRZTrap03Handler(pVM, pVCpu, CPUMCTX2CORE(pMixedCtx));
13110	if (rc == VINF_EM_RAW_GUEST_TRAP)
13111	{
13112	rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13113	rc \|= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13114	rc \|= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13115	AssertRCReturn(rc, rc);
13116
13117	hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13118	pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13119	}
13120
13121	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_EM_DBG_BREAKPOINT);
13122	return rc;
13123	}
13124
13125
13126	/**
13127	* VM-exit exception handler for \#AC (alignment check exception).
13128	*/
13129	static int hmR0VmxExitXcptAC(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13130	{
13131	RT_NOREF_PV(pMixedCtx);
13132	HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13133
13134	/*
13135	* Re-inject it. We'll detect any nesting before getting here.
13136	*/
13137	int rc = hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13138	rc \|= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13139	AssertRCReturn(rc, rc);
13140	Assert(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO);
13141
13142	hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13143	pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13144	return VINF_SUCCESS;
13145	}
13146
13147
13148	/**
13149	* VM-exit exception handler for \#DB (Debug exception).
13150	*/
13151	static int hmR0VmxExitXcptDB(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13152	{
13153	HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13154	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
13155	Log6(("XcptDB\n"));
13156
13157	/*
13158	* Get the DR6-like values from the VM-exit qualification and pass it to DBGF
13159	* for processing.
13160	*/
13161	int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
13162	AssertRCReturn(rc, rc);
13163
13164	/* Refer Intel spec. Table 27-1. "Exit Qualifications for debug exceptions" for the format. */
13165	uint64_t uDR6 = X86_DR6_INIT_VAL;
13166	uDR6 \|= ( pVmxTransient->uExitQualification
13167	& (X86_DR6_B0 \| X86_DR6_B1 \| X86_DR6_B2 \| X86_DR6_B3 \| X86_DR6_BD \| X86_DR6_BS));
13168
13169	rc = DBGFRZTrap01Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pMixedCtx), uDR6, pVCpu->hm.s.fSingleInstruction);
13170	if (rc == VINF_EM_RAW_GUEST_TRAP)
13171	{
13172	/*
13173	* The exception was for the guest. Update DR6, DR7.GD and
13174	* IA32_DEBUGCTL.LBR before forwarding it.
13175	* (See Intel spec. 27.1 "Architectural State before a VM-Exit".)
13176	*/
13177	VMMRZCallRing3Disable(pVCpu);
13178	HM_DISABLE_PREEMPT();
13179
13180	pMixedCtx->dr[6] &= ~X86_DR6_B_MASK;
13181	pMixedCtx->dr[6] \|= uDR6;
13182	if (CPUMIsGuestDebugStateActive(pVCpu))
13183	ASMSetDR6(pMixedCtx->dr[6]);
13184
13185	HM_RESTORE_PREEMPT();
13186	VMMRZCallRing3Enable(pVCpu);
13187
13188	rc = hmR0VmxSaveGuestDR7(pVCpu, pMixedCtx);
13189	AssertRCReturn(rc, rc);
13190
13191	/* X86_DR7_GD will be cleared if DRx accesses should be trapped inside the guest. */
13192	pMixedCtx->dr[7] &= ~X86_DR7_GD;
13193
13194	/* Paranoia. */
13195	pMixedCtx->dr[7] &= ~X86_DR7_RAZ_MASK;
13196	pMixedCtx->dr[7] \|= X86_DR7_RA1_MASK;
13197
13198	rc = VMXWriteVmcs32(VMX_VMCS_GUEST_DR7, (uint32_t)pMixedCtx->dr[7]);
13199	AssertRCReturn(rc, rc);
13200
13201	/*
13202	* Raise #DB in the guest.
13203	*
13204	* It is important to reflect what the VM-exit gave us (preserving the interruption-type) rather than use
13205	* hmR0VmxSetPendingXcptDB() as the #DB could've been raised while executing ICEBP and not the 'normal' #DB.
13206	* Thus it -may- trigger different handling in the CPU (like skipped DPL checks). See @bugref{6398}.
13207	*
13208	* Since ICEBP isn't documented on Intel, see AMD spec. 15.20 "Event Injection".
13209	*/
13210	rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13211	rc \|= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13212	rc \|= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13213	AssertRCReturn(rc, rc);
13214	hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13215	pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13216	return VINF_SUCCESS;
13217	}
13218
13219	/*
13220	* Not a guest trap, must be a hypervisor related debug event then.
13221	* Update DR6 in case someone is interested in it.
13222	*/
13223	AssertMsg(rc == VINF_EM_DBG_STEPPED \|\| rc == VINF_EM_DBG_BREAKPOINT, ("%Rrc\n", rc));
13224	AssertReturn(pVmxTransient->fWasHyperDebugStateActive, VERR_HM_IPE_5);
13225	CPUMSetHyperDR6(pVCpu, uDR6);
13226
13227	return rc;
13228	}
13229
13230
13231	/**
13232	* VM-exit exception handler for \#NM (Device-not-available exception: floating
13233	* point exception).
13234	*/
13235	static int hmR0VmxExitXcptNM(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13236	{
13237	HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13238
13239	/* We require CR0 and EFER. EFER is always up-to-date. */
13240	int rc = hmR0VmxSaveGuestCR0(pVCpu, pMixedCtx);
13241	AssertRCReturn(rc, rc);
13242
13243	/* We're playing with the host CPU state here, have to disable preemption or longjmp. */
13244	VMMRZCallRing3Disable(pVCpu);
13245	HM_DISABLE_PREEMPT();
13246
13247	/* If the guest FPU was active at the time of the #NM VM-exit, then it's a guest fault. */
13248	if (pVmxTransient->fWasGuestFPUStateActive)
13249	{
13250	rc = VINF_EM_RAW_GUEST_TRAP;
13251	Assert(CPUMIsGuestFPUStateActive(pVCpu) \|\| HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
13252	}
13253	else
13254	{
13255	#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
13256	Assert(!pVmxTransient->fWasGuestFPUStateActive \|\| pVCpu->hm.s.fUsingDebugLoop);
13257	#endif
13258	rc = CPUMR0Trap07Handler(pVCpu->CTX_SUFF(pVM), pVCpu);
13259	Assert( rc == VINF_EM_RAW_GUEST_TRAP
13260	\|\| ((rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED) && CPUMIsGuestFPUStateActive(pVCpu)));
13261	if (rc == VINF_CPUM_HOST_CR0_MODIFIED)
13262	HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT);
13263	}
13264
13265	HM_RESTORE_PREEMPT();
13266	VMMRZCallRing3Enable(pVCpu);
13267
13268	if (rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED)
13269	{
13270	/* Guest FPU state was activated, we'll want to change CR0 FPU intercepts before the next VM-reentry. */
13271	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
13272	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
13273	pVCpu->hm.s.fPreloadGuestFpu = true;
13274	}
13275	else
13276	{
13277	/* Forward #NM to the guest. */
13278	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
13279	rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13280	AssertRCReturn(rc, rc);
13281	hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13282	pVmxTransient->cbInstr, 0 /* error code /, 0 / GCPtrFaultAddress */);
13283	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
13284	}
13285
13286	return VINF_SUCCESS;
13287	}
13288
13289
13290	/**
13291	* VM-exit exception handler for \#GP (General-protection exception).
13292	*
13293	* @remarks Requires pVmxTransient->uExitIntInfo to be up-to-date.
13294	*/
13295	static int hmR0VmxExitXcptGP(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13296	{
13297	HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13298	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
13299
13300	int rc;
13301	if (pVCpu->hm.s.vmx.RealMode.fRealOnV86Active)
13302	{ /* likely */ }
13303	else
13304	{
13305	#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
13306	Assert(pVCpu->hm.s.fUsingDebugLoop);
13307	#endif
13308	/* If the guest is not in real-mode or we have unrestricted execution support, reflect #GP to the guest. */
13309	rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13310	rc \|= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13311	rc \|= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13312	rc \|= hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
13313	AssertRCReturn(rc, rc);
13314	Log4(("#GP Gst: CS:RIP %04x:%08RX64 ErrorCode=%#x CR0=%#RX64 CPL=%u TR=%#04x\n", pMixedCtx->cs.Sel, pMixedCtx->rip,
13315	pVmxTransient->uExitIntErrorCode, pMixedCtx->cr0, CPUMGetGuestCPL(pVCpu), pMixedCtx->tr.Sel));
13316	hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13317	pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13318	return rc;
13319	}
13320
13321	Assert(CPUMIsGuestInRealModeEx(pMixedCtx));
13322	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fUnrestrictedGuest);
13323
13324	/* EMInterpretDisasCurrent() requires a lot of the state, save the entire state. */
13325	rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
13326	AssertRCReturn(rc, rc);
13327
13328	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
13329	uint32_t cbOp = 0;
13330	PVM pVM = pVCpu->CTX_SUFF(pVM);
13331	bool fDbgStepping = pVCpu->hm.s.fSingleInstruction;
13332	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
13333	if (RT_SUCCESS(rc))
13334	{
13335	rc = VINF_SUCCESS;
13336	Assert(cbOp == pDis->cbInstr);
13337	Log4(("#GP Disas OpCode=%u CS:EIP %04x:%04RX64\n", pDis->pCurInstr->uOpcode, pMixedCtx->cs.Sel, pMixedCtx->rip));
13338	switch (pDis->pCurInstr->uOpcode)
13339	{
13340	case OP_CLI:
13341	{
13342	pMixedCtx->eflags.Bits.u1IF = 0;
13343	pMixedCtx->eflags.Bits.u1RF = 0;
13344	pMixedCtx->rip += pDis->cbInstr;
13345	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS);
13346	if ( !fDbgStepping
13347	&& pMixedCtx->eflags.Bits.u1TF)
13348	hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
13349	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCli);
13350	break;
13351	}
13352
13353	case OP_STI:
13354	{
13355	bool fOldIF = pMixedCtx->eflags.Bits.u1IF;
13356	pMixedCtx->eflags.Bits.u1IF = 1;
13357	pMixedCtx->eflags.Bits.u1RF = 0;
13358	pMixedCtx->rip += pDis->cbInstr;
13359	if (!fOldIF)
13360	{
13361	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
13362	Assert(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
13363	}
13364	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS);
13365	if ( !fDbgStepping
13366	&& pMixedCtx->eflags.Bits.u1TF)
13367	hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
13368	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitSti);
13369	break;
13370	}
13371
13372	case OP_HLT:
13373	{
13374	rc = VINF_EM_HALT;
13375	pMixedCtx->rip += pDis->cbInstr;
13376	pMixedCtx->eflags.Bits.u1RF = 0;
13377	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP \| HM_CHANGED_GUEST_RFLAGS);
13378	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
13379	break;
13380	}
13381
13382	case OP_POPF:
13383	{
13384	Log4(("POPF CS:EIP %04x:%04RX64\n", pMixedCtx->cs.Sel, pMixedCtx->rip));
13385	uint32_t cbParm;
13386	uint32_t uMask;
13387	bool fGstStepping = RT_BOOL(pMixedCtx->eflags.Bits.u1TF);
13388	if (pDis->fPrefix & DISPREFIX_OPSIZE)
13389	{
13390	cbParm = 4;
13391	uMask = 0xffffffff;
13392	}
13393	else
13394	{
13395	cbParm = 2;
13396	uMask = 0xffff;
13397	}
13398
13399	/* Get the stack pointer & pop the contents of the stack onto Eflags. */
13400	RTGCPTR GCPtrStack = 0;
13401	X86EFLAGS Eflags;
13402	Eflags.u32 = 0;
13403	rc = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pMixedCtx), pMixedCtx->esp & uMask, SELMTOFLAT_FLAGS_CPL0,
13404	&GCPtrStack);
13405	if (RT_SUCCESS(rc))
13406	{
13407	Assert(sizeof(Eflags.u32) >= cbParm);
13408	rc = VBOXSTRICTRC_TODO(PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &Eflags.u32, cbParm, PGMACCESSORIGIN_HM));
13409	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc)); /** @todo allow strict return codes here */
13410	}
13411	if (RT_FAILURE(rc))
13412	{
13413	rc = VERR_EM_INTERPRETER;
13414	break;
13415	}
13416	Log4(("POPF %#x -> %#RX64 mask=%#x RIP=%#RX64\n", Eflags.u, pMixedCtx->rsp, uMask, pMixedCtx->rip));
13417	pMixedCtx->eflags.u32 = (pMixedCtx->eflags.u32 & ~((X86_EFL_POPF_BITS & uMask) \| X86_EFL_RF))
13418	\| (Eflags.u32 & X86_EFL_POPF_BITS & uMask);
13419	pMixedCtx->esp += cbParm;
13420	pMixedCtx->esp &= uMask;
13421	pMixedCtx->rip += pDis->cbInstr;
13422	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
13423	\| HM_CHANGED_GUEST_RSP
13424	\| HM_CHANGED_GUEST_RFLAGS);
13425	/* Generate a pending-debug exception when the guest stepping over POPF regardless of how
13426	POPF restores EFLAGS.TF. */
13427	if ( !fDbgStepping
13428	&& fGstStepping)
13429	hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
13430	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPopf);
13431	break;
13432	}
13433
13434	case OP_PUSHF:
13435	{
13436	uint32_t cbParm;
13437	uint32_t uMask;
13438	if (pDis->fPrefix & DISPREFIX_OPSIZE)
13439	{
13440	cbParm = 4;
13441	uMask = 0xffffffff;
13442	}
13443	else
13444	{
13445	cbParm = 2;
13446	uMask = 0xffff;
13447	}
13448
13449	/* Get the stack pointer & push the contents of eflags onto the stack. */
13450	RTGCPTR GCPtrStack = 0;
13451	rc = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pMixedCtx), (pMixedCtx->esp - cbParm) & uMask,
13452	SELMTOFLAT_FLAGS_CPL0, &GCPtrStack);
13453	if (RT_FAILURE(rc))
13454	{
13455	rc = VERR_EM_INTERPRETER;
13456	break;
13457	}
13458	X86EFLAGS Eflags = pMixedCtx->eflags;
13459	/* The RF & VM bits are cleared on image stored on stack; see Intel Instruction reference for PUSHF. */
13460	Eflags.Bits.u1RF = 0;
13461	Eflags.Bits.u1VM = 0;
13462
13463	rc = VBOXSTRICTRC_TODO(PGMPhysWrite(pVM, (RTGCPHYS)GCPtrStack, &Eflags.u, cbParm, PGMACCESSORIGIN_HM));
13464	if (RT_UNLIKELY(rc != VINF_SUCCESS))
13465	{
13466	AssertMsgFailed(("%Rrc\n", rc)); /** @todo allow strict return codes here */
13467	rc = VERR_EM_INTERPRETER;
13468	break;
13469	}
13470	Log4(("PUSHF %#x -> %#RGv\n", Eflags.u, GCPtrStack));
13471	pMixedCtx->esp -= cbParm;
13472	pMixedCtx->esp &= uMask;
13473	pMixedCtx->rip += pDis->cbInstr;
13474	pMixedCtx->eflags.Bits.u1RF = 0;
13475	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
13476	\| HM_CHANGED_GUEST_RSP
13477	\| HM_CHANGED_GUEST_RFLAGS);
13478	if ( !fDbgStepping
13479	&& pMixedCtx->eflags.Bits.u1TF)
13480	hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
13481	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPushf);
13482	break;
13483	}
13484
13485	case OP_IRET:
13486	{
13487	/** @todo Handle 32-bit operand sizes and check stack limits. See Intel
13488	* instruction reference. */
13489	RTGCPTR GCPtrStack = 0;
13490	uint32_t uMask = 0xffff;
13491	bool fGstStepping = RT_BOOL(pMixedCtx->eflags.Bits.u1TF);
13492	uint16_t aIretFrame[3];
13493	if (pDis->fPrefix & (DISPREFIX_OPSIZE \| DISPREFIX_ADDRSIZE))
13494	{
13495	rc = VERR_EM_INTERPRETER;
13496	break;
13497	}
13498	rc = SELMToFlatEx(pVCpu, DISSELREG_SS, CPUMCTX2CORE(pMixedCtx), pMixedCtx->esp & uMask, SELMTOFLAT_FLAGS_CPL0,
13499	&GCPtrStack);
13500	if (RT_SUCCESS(rc))
13501	{
13502	rc = VBOXSTRICTRC_TODO(PGMPhysRead(pVM, (RTGCPHYS)GCPtrStack, &aIretFrame[0], sizeof(aIretFrame),
13503	PGMACCESSORIGIN_HM));
13504	AssertMsg(rc == VINF_SUCCESS, ("%Rrc\n", rc)); /** @todo allow strict return codes here */
13505	}
13506	if (RT_FAILURE(rc))
13507	{
13508	rc = VERR_EM_INTERPRETER;
13509	break;
13510	}
13511	pMixedCtx->eip = 0;
13512	pMixedCtx->ip = aIretFrame[0];
13513	pMixedCtx->cs.Sel = aIretFrame[1];
13514	pMixedCtx->cs.ValidSel = aIretFrame[1];
13515	pMixedCtx->cs.u64Base = (uint64_t)pMixedCtx->cs.Sel << 4;
13516	pMixedCtx->eflags.u32 = (pMixedCtx->eflags.u32 & ((UINT32_C(0xffff0000) \| X86_EFL_1) & ~X86_EFL_RF))
13517	\| (aIretFrame[2] & X86_EFL_POPF_BITS & uMask);
13518	pMixedCtx->sp += sizeof(aIretFrame);
13519	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
13520	\| HM_CHANGED_GUEST_SEGMENT_REGS
13521	\| HM_CHANGED_GUEST_RSP
13522	\| HM_CHANGED_GUEST_RFLAGS);
13523	/* Generate a pending-debug exception when stepping over IRET regardless of how IRET modifies EFLAGS.TF. */
13524	if ( !fDbgStepping
13525	&& fGstStepping)
13526	hmR0VmxSetPendingDebugXcptVmcs(pVCpu);
13527	Log4(("IRET %#RX32 to %04x:%04x\n", GCPtrStack, pMixedCtx->cs.Sel, pMixedCtx->ip));
13528	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIret);
13529	break;
13530	}
13531
13532	case OP_INT:
13533	{
13534	uint16_t uVector = pDis->Param1.uValue & 0xff;
13535	hmR0VmxSetPendingIntN(pVCpu, pMixedCtx, uVector, pDis->cbInstr);
13536	/* INT clears EFLAGS.TF, we must not set any pending debug exceptions here. */
13537	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInt);
13538	break;
13539	}
13540
13541	case OP_INTO:
13542	{
13543	if (pMixedCtx->eflags.Bits.u1OF)
13544	{
13545	hmR0VmxSetPendingXcptOF(pVCpu, pMixedCtx, pDis->cbInstr);
13546	/* INTO clears EFLAGS.TF, we must not set any pending debug exceptions here. */
13547	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInt);
13548	}
13549	else
13550	{
13551	pMixedCtx->eflags.Bits.u1RF = 0;
13552	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RFLAGS);
13553	}
13554	break;
13555	}
13556
13557	default:
13558	{
13559	pMixedCtx->eflags.Bits.u1RF = 0; /* This is correct most of the time... */
13560	VBOXSTRICTRC rc2 = EMInterpretInstructionDisasState(pVCpu, pDis, CPUMCTX2CORE(pMixedCtx), 0 /* pvFault */,
13561	EMCODETYPE_SUPERVISOR);
13562	rc = VBOXSTRICTRC_VAL(rc2);
13563	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
13564	/** @todo We have to set pending-debug exceptions here when the guest is
13565	* single-stepping depending on the instruction that was interpreted. */
13566	Log4(("#GP rc=%Rrc\n", rc));
13567	break;
13568	}
13569	}
13570	}
13571	else
13572	rc = VERR_EM_INTERPRETER;
13573
13574	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_EM_HALT,
13575	("#GP Unexpected rc=%Rrc\n", rc));
13576	return rc;
13577	}
13578
13579
13580	/**
13581	* VM-exit exception handler wrapper for generic exceptions. Simply re-injects
13582	* the exception reported in the VMX transient structure back into the VM.
13583	*
13584	* @remarks Requires uExitIntInfo in the VMX transient structure to be
13585	* up-to-date.
13586	*/
13587	static int hmR0VmxExitXcptGeneric(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13588	{
13589	RT_NOREF_PV(pMixedCtx);
13590	HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13591	#ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
13592	Assert(pVCpu->hm.s.fUsingDebugLoop);
13593	#endif
13594
13595	/* Re-inject the exception into the guest. This cannot be a double-fault condition which would have been handled in
13596	hmR0VmxCheckExitDueToEventDelivery(). */
13597	int rc = hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13598	rc \|= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
13599	AssertRCReturn(rc, rc);
13600	Assert(pVmxTransient->fVmcsFieldsRead & HMVMX_UPDATED_TRANSIENT_EXIT_INTERRUPTION_INFO);
13601
13602	#ifdef DEBUG_ramshankar
13603	rc \|= hmR0VmxSaveGuestSegmentRegs(pVCpu, pMixedCtx);
13604	uint8_t uVector = VMX_EXIT_INTERRUPTION_INFO_VECTOR(pVmxTransient->uExitIntInfo);
13605	Log(("hmR0VmxExitXcptGeneric: Reinjecting Xcpt. uVector=%#x cs:rip=%#04x:%#RX64\n", uVector, pCtx->cs.Sel, pCtx->rip));
13606	#endif
13607
13608	hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13609	pVmxTransient->cbInstr, pVmxTransient->uExitIntErrorCode, 0 /* GCPtrFaultAddress */);
13610	return VINF_SUCCESS;
13611	}
13612
13613
13614	/**
13615	* VM-exit exception handler for \#PF (Page-fault exception).
13616	*/
13617	static int hmR0VmxExitXcptPF(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PVMXTRANSIENT pVmxTransient)
13618	{
13619	HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
13620	PVM pVM = pVCpu->CTX_SUFF(pVM);
13621	int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);
13622	rc \|= hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
13623	rc \|= hmR0VmxReadExitIntErrorCodeVmcs(pVmxTransient);
13624	AssertRCReturn(rc, rc);
13625
13626	if (!pVM->hm.s.fNestedPaging)
13627	{ /* likely */ }
13628	else
13629	{
13630	#if !defined(HMVMX_ALWAYS_TRAP_ALL_XCPTS) && !defined(HMVMX_ALWAYS_TRAP_PF)
13631	Assert(pVCpu->hm.s.fUsingDebugLoop);
13632	#endif
13633	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
13634	if (RT_LIKELY(!pVmxTransient->fVectoringDoublePF))
13635	{
13636	pMixedCtx->cr2 = pVmxTransient->uExitQualification; /* Update here in case we go back to ring-3 before injection. */
13637	hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13638	0 /* cbInstr */, pVmxTransient->uExitIntErrorCode, pVmxTransient->uExitQualification);
13639	}
13640	else
13641	{
13642	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
13643	hmR0VmxSetPendingXcptDF(pVCpu, pMixedCtx);
13644	Log4(("Pending #DF due to vectoring #PF. NP\n"));
13645	}
13646	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
13647	return rc;
13648	}
13649
13650	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
13651	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
13652	if (pVmxTransient->fVectoringPF)
13653	{
13654	Assert(pVCpu->hm.s.Event.fPending);
13655	return VINF_EM_RAW_INJECT_TRPM_EVENT;
13656	}
13657
13658	rc = hmR0VmxSaveGuestState(pVCpu, pMixedCtx);
13659	AssertRCReturn(rc, rc);
13660
13661	Log4(("#PF: cr2=%#RX64 cs:rip=%#04x:%#RX64 uErrCode %#RX32 cr3=%#RX64\n", pVmxTransient->uExitQualification,
13662	pMixedCtx->cs.Sel, pMixedCtx->rip, pVmxTransient->uExitIntErrorCode, pMixedCtx->cr3));
13663
13664	TRPMAssertXcptPF(pVCpu, pVmxTransient->uExitQualification, (RTGCUINT)pVmxTransient->uExitIntErrorCode);
13665	rc = PGMTrap0eHandler(pVCpu, pVmxTransient->uExitIntErrorCode, CPUMCTX2CORE(pMixedCtx),
13666	(RTGCPTR)pVmxTransient->uExitQualification);
13667
13668	Log4(("#PF: rc=%Rrc\n", rc));
13669	if (rc == VINF_SUCCESS)
13670	{
13671	#if 0
13672	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
13673	/** @todo this isn't quite right, what if guest does lgdt with some MMIO
13674	* memory? We don't update the whole state here... */
13675	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_RIP
13676	\| HM_CHANGED_GUEST_RSP
13677	\| HM_CHANGED_GUEST_RFLAGS
13678	\| HM_CHANGED_VMX_GUEST_APIC_STATE);
13679	#else
13680	/*
13681	* This is typically a shadow page table sync or a MMIO instruction. But we may have
13682	* emulated something like LTR or a far jump. Any part of the CPU context may have changed.
13683	*/
13684	/** @todo take advantage of CPUM changed flags instead of brute forcing. */
13685	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
13686	#endif
13687	TRPMResetTrap(pVCpu);
13688	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
13689	return rc;
13690	}
13691
13692	if (rc == VINF_EM_RAW_GUEST_TRAP)
13693	{
13694	if (!pVmxTransient->fVectoringDoublePF)
13695	{
13696	/* It's a guest page fault and needs to be reflected to the guest. */
13697	uint32_t uGstErrorCode = TRPMGetErrorCode(pVCpu);
13698	TRPMResetTrap(pVCpu);
13699	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory #PF. */
13700	pMixedCtx->cr2 = pVmxTransient->uExitQualification; /* Update here in case we go back to ring-3 before injection. */
13701	hmR0VmxSetPendingEvent(pVCpu, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(pVmxTransient->uExitIntInfo),
13702	0 /* cbInstr */, uGstErrorCode, pVmxTransient->uExitQualification);
13703	}
13704	else
13705	{
13706	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
13707	TRPMResetTrap(pVCpu);
13708	pVCpu->hm.s.Event.fPending = false; /* Clear pending #PF to replace it with #DF. */
13709	hmR0VmxSetPendingXcptDF(pVCpu, pMixedCtx);
13710	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
13711	}
13712
13713	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
13714	return VINF_SUCCESS;
13715	}
13716
13717	TRPMResetTrap(pVCpu);
13718	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
13719	return rc;
13720	}
13721
13722	/** @} */
13723

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp@ 65697

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