HMSVMR0.cpp@ 71312

Last change on this file since 71312 was 71312, checked in by vboxsync, 7 years ago
VMM/HMSVMR0: Nested Hw.virt: Explicitly skip intercepting #UD and #BP while executing the nested-guest just because the outer guest might happen to intercept them for purposes that are currently irrelevant for the nested-guest.
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1	/* $Id: HMSVMR0.cpp 71312 2018-03-13 10:55:27Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <iprt/asm-amd64-x86.h>
25	#include <iprt/thread.h>
26
27	#include <VBox/vmm/pdmapi.h>
28	#include <VBox/vmm/dbgf.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32	#include <VBox/vmm/gim.h>
33	#include <VBox/vmm/apic.h>
34	#include "HMInternal.h"
35	#include <VBox/vmm/vm.h>
36	#include "HMSVMR0.h"
37	#include "dtrace/VBoxVMM.h"
38
39	#define HMSVM_USE_IEM_EVENT_REFLECTION
40	#ifdef DEBUG_ramshankar
41	# define HMSVM_SYNC_FULL_GUEST_STATE
42	# define HMSVM_SYNC_FULL_NESTED_GUEST_STATE
43	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
44	# define HMSVM_ALWAYS_TRAP_PF
45	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
46	#endif
47
48
49	/*********************************************************************************************************************************
50	* Defined Constants And Macros *
51	*********************************************************************************************************************************/
52	#ifdef VBOX_WITH_STATISTICS
53	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
54	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
55	if ((u64ExitCode) == SVM_EXIT_NPF) \
56	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
57	else \
58	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
59	} while (0)
60	#else
61	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
62	#endif
63
64	/** If we decide to use a function table approach this can be useful to
65	* switch to a "static DECLCALLBACK(int)". */
66	#define HMSVM_EXIT_DECL static int
67
68	/** Macro for checking and returning from the using function for
69	* \#VMEXIT intercepts that maybe caused during delivering of another
70	* event in the guest. */
71	#ifdef VBOX_WITH_NESTED_HWVIRT
72	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
73	do \
74	{ \
75	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
76	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
77	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
78	else if ( rc == VINF_EM_RESET \
79	&& HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN)) \
80	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_SHUTDOWN, 0, 0)); \
81	else \
82	return rc; \
83	} while (0)
84	#else
85	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
86	do \
87	{ \
88	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
89	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
90	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
91	else \
92	return rc; \
93	} while (0)
94	#endif
95
96	/**
97	* Updates interrupt shadow for the current RIP.
98	*/
99	#define HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx) \
100	do { \
101	/* Update interrupt shadow. */ \
102	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS) \
103	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu)) \
104	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS); \
105	} while (0)
106
107	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
108	* instruction that exited. */
109	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
110	do { \
111	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
112	(a_rc) = VINF_EM_DBG_STEPPED; \
113	} while (0)
114
115	/** Assert that preemption is disabled or covered by thread-context hooks. */
116	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
117	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
118
119	/** Assert that we haven't migrated CPUs when thread-context hooks are not
120	* used. */
121	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
122	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
123	("Illegal migration! Entered on CPU %u Current %u\n", \
124	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
125
126	/** Assert that we're not executing a nested-guest. */
127	#ifdef VBOX_WITH_NESTED_HWVIRT
128	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) Assert(!CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
129	#else
130	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
131	#endif
132
133	/** Assert that we're executing a nested-guest. */
134	#ifdef VBOX_WITH_NESTED_HWVIRT
135	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) Assert(CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
136	#else
137	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
138	#endif
139
140	/** Validate segment descriptor granularity bit. */
141	#ifdef VBOX_STRICT
142	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
143	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
144	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
145	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
146	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
147	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
148	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
149	#else
150	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) do { } while (0)
151	#endif
152
153	/**
154	* Exception bitmap mask for all contributory exceptions.
155	*
156	* Page fault is deliberately excluded here as it's conditional as to whether
157	* it's contributory or benign. Page faults are handled separately.
158	*/
159	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
160	\| RT_BIT(X86_XCPT_DE))
161
162	/**
163	* Mandatory/unconditional guest control intercepts.
164	*
165	* SMIs can and do happen in normal operation. We need not intercept them
166	* while executing the guest or nested-guest.
167	*/
168	#define HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS ( SVM_CTRL_INTERCEPT_INTR \
169	\| SVM_CTRL_INTERCEPT_NMI \
170	\| SVM_CTRL_INTERCEPT_INIT \
171	\| SVM_CTRL_INTERCEPT_RDPMC \
172	\| SVM_CTRL_INTERCEPT_CPUID \
173	\| SVM_CTRL_INTERCEPT_RSM \
174	\| SVM_CTRL_INTERCEPT_HLT \
175	\| SVM_CTRL_INTERCEPT_IOIO_PROT \
176	\| SVM_CTRL_INTERCEPT_MSR_PROT \
177	\| SVM_CTRL_INTERCEPT_INVLPGA \
178	\| SVM_CTRL_INTERCEPT_SHUTDOWN \
179	\| SVM_CTRL_INTERCEPT_FERR_FREEZE \
180	\| SVM_CTRL_INTERCEPT_VMRUN \
181	\| SVM_CTRL_INTERCEPT_SKINIT \
182	\| SVM_CTRL_INTERCEPT_WBINVD \
183	\| SVM_CTRL_INTERCEPT_MONITOR \
184	\| SVM_CTRL_INTERCEPT_MWAIT \
185	\| SVM_CTRL_INTERCEPT_XSETBV)
186
187	/** @name VMCB Clean Bits.
188	*
189	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
190	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
191	* memory.
192	*
193	* @{ */
194	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
195	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
196	/** I/O permission bitmap, MSR permission bitmap. */
197	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
198	/** ASID. */
199	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
200	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
201	V_INTR_VECTOR. */
202	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
203	/** Nested Paging: Nested CR3 (nCR3), PAT. */
204	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
205	/** Control registers (CR0, CR3, CR4, EFER). */
206	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
207	/** Debug registers (DR6, DR7). */
208	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
209	/** GDT, IDT limit and base. */
210	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
211	/** Segment register: CS, SS, DS, ES limit and base. */
212	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
213	/** CR2.*/
214	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
215	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
216	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
217	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
218	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
219	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
220	/** Mask of all valid VMCB Clean bits. */
221	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
222	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
223	\| HMSVM_VMCB_CLEAN_ASID \
224	\| HMSVM_VMCB_CLEAN_TPR \
225	\| HMSVM_VMCB_CLEAN_NP \
226	\| HMSVM_VMCB_CLEAN_CRX_EFER \
227	\| HMSVM_VMCB_CLEAN_DRX \
228	\| HMSVM_VMCB_CLEAN_DT \
229	\| HMSVM_VMCB_CLEAN_SEG \
230	\| HMSVM_VMCB_CLEAN_CR2 \
231	\| HMSVM_VMCB_CLEAN_LBR \
232	\| HMSVM_VMCB_CLEAN_AVIC)
233	/** @} */
234
235	/** @name SVM transient.
236	*
237	* A state structure for holding miscellaneous information across AMD-V
238	* VMRUN/\#VMEXIT operation, restored after the transition.
239	*
240	* @{ */
241	typedef struct SVMTRANSIENT
242	{
243	/** The host's rflags/eflags. */
244	RTCCUINTREG fEFlags;
245	#if HC_ARCH_BITS == 32
246	uint32_t u32Alignment0;
247	#endif
248
249	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
250	uint64_t u64ExitCode;
251	/** The guest's TPR value used for TPR shadowing. */
252	uint8_t u8GuestTpr;
253	/** Alignment. */
254	uint8_t abAlignment0[7];
255
256	/** Whether the guest FPU state was active at the time of \#VMEXIT. */
257	bool fWasGuestFPUStateActive;
258	/** Whether the guest debug state was active at the time of \#VMEXIT. */
259	bool fWasGuestDebugStateActive;
260	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
261	bool fWasHyperDebugStateActive;
262	/** Whether the TSC offset mode needs to be updated. */
263	bool fUpdateTscOffsetting;
264	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
265	bool fRestoreTscAuxMsr;
266	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
267	* contributary exception or a page-fault. */
268	bool fVectoringDoublePF;
269	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
270	* external interrupt or NMI. */
271	bool fVectoringPF;
272	} SVMTRANSIENT, *PSVMTRANSIENT;
273	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
274	AssertCompileMemberAlignment(SVMTRANSIENT, fWasGuestFPUStateActive, sizeof(uint64_t));
275	/** @} */
276
277	/**
278	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
279	*/
280	typedef enum SVMMSREXITREAD
281	{
282	/** Reading this MSR causes a \#VMEXIT. */
283	SVMMSREXIT_INTERCEPT_READ = 0xb,
284	/** Reading this MSR does not cause a \#VMEXIT. */
285	SVMMSREXIT_PASSTHRU_READ
286	} SVMMSREXITREAD;
287
288	/**
289	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
290	*/
291	typedef enum SVMMSREXITWRITE
292	{
293	/** Writing to this MSR causes a \#VMEXIT. */
294	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
295	/** Writing to this MSR does not cause a \#VMEXIT. */
296	SVMMSREXIT_PASSTHRU_WRITE
297	} SVMMSREXITWRITE;
298
299	/**
300	* SVM \#VMEXIT handler.
301	*
302	* @returns VBox status code.
303	* @param pVCpu The cross context virtual CPU structure.
304	* @param pMixedCtx Pointer to the guest-CPU context.
305	* @param pSvmTransient Pointer to the SVM-transient structure.
306	*/
307	typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
308
309
310	/*********************************************************************************************************************************
311	* Internal Functions *
312	*********************************************************************************************************************************/
313	static void hmR0SvmSetMsrPermission(PSVMVMCB pVmcb, uint8_t *pbMsrBitmap, unsigned uMsr, SVMMSREXITREAD enmRead,
314	SVMMSREXITWRITE enmWrite);
315	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
316	static void hmR0SvmLeave(PVMCPU pVCpu);
317
318	/** @name \#VMEXIT handlers.
319	* @{
320	*/
321	static FNSVMEXITHANDLER hmR0SvmExitIntr;
322	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
323	static FNSVMEXITHANDLER hmR0SvmExitInvd;
324	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
325	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
326	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
327	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
328	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
329	static FNSVMEXITHANDLER hmR0SvmExitHlt;
330	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
331	static FNSVMEXITHANDLER hmR0SvmExitMwait;
332	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
333	static FNSVMEXITHANDLER hmR0SvmExitUnexpected;
334	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
335	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
336	static FNSVMEXITHANDLER hmR0SvmExitMsr;
337	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
338	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
339	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
340	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
341	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
342	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
343	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
344	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
345	static FNSVMEXITHANDLER hmR0SvmExitPause;
346	static FNSVMEXITHANDLER hmR0SvmExitIret;
347	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
348	static FNSVMEXITHANDLER hmR0SvmExitXcptNM;
349	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
350	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
351	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
352	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
353	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
354	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT)
355	static FNSVMEXITHANDLER hmR0SvmExitXcptGeneric;
356	#endif
357	#ifdef VBOX_WITH_NESTED_HWVIRT
358	static FNSVMEXITHANDLER hmR0SvmExitXcptPFNested;
359	static FNSVMEXITHANDLER hmR0SvmExitClgi;
360	static FNSVMEXITHANDLER hmR0SvmExitStgi;
361	static FNSVMEXITHANDLER hmR0SvmExitVmload;
362	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
363	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
364	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
365	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptDB;
366	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptBP;
367	#endif
368	/** @} */
369
370	static int hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
371	#ifdef VBOX_WITH_NESTED_HWVIRT
372	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
373	#endif
374
375
376	/*********************************************************************************************************************************
377	* Global Variables *
378	*********************************************************************************************************************************/
379	/** Ring-0 memory object for the IO bitmap. */
380	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
381	/** Physical address of the IO bitmap. */
382	RTHCPHYS g_HCPhysIOBitmap = 0;
383	/** Pointer to the IO bitmap. */
384	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
385
386	#ifdef VBOX_WITH_NESTED_HWVIRT
387	/** Ring-0 memory object for the nested-guest MSRPM bitmap. */
388	RTR0MEMOBJ g_hMemObjNstGstMsrBitmap = NIL_RTR0MEMOBJ;
389	/** Physical address of the nested-guest MSRPM bitmap. */
390	RTHCPHYS g_HCPhysNstGstMsrBitmap = 0;
391	/** Pointer to the nested-guest MSRPM bitmap. */
392	R0PTRTYPE(void *) g_pvNstGstMsrBitmap = NULL;
393	#endif
394
395
396	#ifdef VBOX_STRICT
397	# define HMSVM_LOG_CS RT_BIT_32(0)
398	# define HMSVM_LOG_SS RT_BIT_32(1)
399	# define HMSVM_LOG_FS RT_BIT_32(2)
400	# define HMSVM_LOG_GS RT_BIT_32(3)
401	# define HMSVM_LOG_LBR RT_BIT_32(4)
402	# define HMSVM_LOG_ALL ( HMSVM_LOG_CS \
403	\| HMSVM_LOG_SS \
404	\| HMSVM_LOG_FS \
405	\| HMSVM_LOG_GS \
406	\| HMSVM_LOG_LBR)
407
408	/**
409	* Dumps CPU state and additional info. to the logger for diagnostics.
410	*
411	* @param pVCpu The cross context virtual CPU structure.
412	* @param pVmcb Pointer to the VM control block.
413	* @param pCtx Pointer to the guest-CPU context.
414	* @param pszPrefix Log prefix.
415	* @param fFlags Log flags, see HMSVM_LOG_XXX.
416	* @param uVerbose The verbosity level, currently unused.
417	*/
418	static void hmR0SvmLogState(PVMCPU pVCpu, PCSVMVMCB pVmcb, PCPUMCTX pCtx, const char *pszPrefix, uint32_t fFlags,
419	uint8_t uVerbose)
420	{
421	RT_NOREF2(pVCpu, uVerbose);
422
423	Log4(("%s: cs:rip=%04x:%RX64 efl=%#RX64 cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", pszPrefix, pCtx->cs.Sel, pCtx->rip,
424	pCtx->rflags.u, pCtx->cr0, pCtx->cr3, pCtx->cr4));
425	Log4(("%s: rsp=%#RX64 rbp=%#RX64 rdi=%#RX64\n", pszPrefix, pCtx->rsp, pCtx->rbp, pCtx->rdi));
426	if (fFlags & HMSVM_LOG_CS)
427	{
428	Log4(("%s: cs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base,
429	pCtx->cs.u32Limit, pCtx->cs.Attr.u));
430	}
431	if (fFlags & HMSVM_LOG_SS)
432	{
433	Log4(("%s: ss={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base,
434	pCtx->ss.u32Limit, pCtx->ss.Attr.u));
435	}
436	if (fFlags & HMSVM_LOG_FS)
437	{
438	Log4(("%s: fs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base,
439	pCtx->fs.u32Limit, pCtx->fs.Attr.u));
440	}
441	if (fFlags & HMSVM_LOG_GS)
442	{
443	Log4(("%s: gs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base,
444	pCtx->gs.u32Limit, pCtx->gs.Attr.u));
445	}
446
447	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
448	if (fFlags & HMSVM_LOG_LBR)
449	{
450	Log4(("%s: br_from=%#RX64 br_to=%#RX64 lastxcpt_from=%#RX64 lastxcpt_to=%#RX64\n", pszPrefix, pVmcbGuest->u64BR_FROM,
451	pVmcbGuest->u64BR_TO, pVmcbGuest->u64LASTEXCPFROM, pVmcbGuest->u64LASTEXCPTO));
452	}
453	NOREF(pVmcbGuest);
454	}
455	#endif
456
457
458	/**
459	* Sets up and activates AMD-V on the current CPU.
460	*
461	* @returns VBox status code.
462	* @param pCpu Pointer to the CPU info struct.
463	* @param pVM The cross context VM structure. Can be
464	* NULL after a resume!
465	* @param pvCpuPage Pointer to the global CPU page.
466	* @param HCPhysCpuPage Physical address of the global CPU page.
467	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
468	* @param pvArg Unused on AMD-V.
469	*/
470	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
471	void *pvArg)
472	{
473	Assert(!fEnabledByHost);
474	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
475	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
476	Assert(pvCpuPage); NOREF(pvCpuPage);
477	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
478
479	NOREF(pvArg);
480	NOREF(fEnabledByHost);
481
482	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
483	RTCCUINTREG fEFlags = ASMIntDisableFlags();
484
485	/*
486	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
487	*/
488	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
489	if (u64HostEfer & MSR_K6_EFER_SVME)
490	{
491	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
492	if ( pVM
493	&& pVM->hm.s.svm.fIgnoreInUseError)
494	{
495	pCpu->fIgnoreAMDVInUseError = true;
496	}
497
498	if (!pCpu->fIgnoreAMDVInUseError)
499	{
500	ASMSetFlags(fEFlags);
501	return VERR_SVM_IN_USE;
502	}
503	}
504
505	/* Turn on AMD-V in the EFER MSR. */
506	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
507
508	/* Write the physical page address where the CPU will store the host state while executing the VM. */
509	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
510
511	/* Restore interrupts. */
512	ASMSetFlags(fEFlags);
513
514	/*
515	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
516	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
517	* upon VMRUN). Therefore, flag that we need to flush the TLB entirely with before executing any
518	* guest code.
519	*/
520	pCpu->fFlushAsidBeforeUse = true;
521
522	/*
523	* Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
524	*/
525	++pCpu->cTlbFlushes;
526
527	return VINF_SUCCESS;
528	}
529
530
531	/**
532	* Deactivates AMD-V on the current CPU.
533	*
534	* @returns VBox status code.
535	* @param pCpu Pointer to the CPU info struct.
536	* @param pvCpuPage Pointer to the global CPU page.
537	* @param HCPhysCpuPage Physical address of the global CPU page.
538	*/
539	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
540	{
541	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
542	AssertReturn( HCPhysCpuPage
543	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
544	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
545	NOREF(pCpu);
546
547	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
548	RTCCUINTREG fEFlags = ASMIntDisableFlags();
549
550	/* Turn off AMD-V in the EFER MSR. */
551	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
552	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
553
554	/* Invalidate host state physical address. */
555	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
556
557	/* Restore interrupts. */
558	ASMSetFlags(fEFlags);
559
560	return VINF_SUCCESS;
561	}
562
563
564	/**
565	* Does global AMD-V initialization (called during module initialization).
566	*
567	* @returns VBox status code.
568	*/
569	VMMR0DECL(int) SVMR0GlobalInit(void)
570	{
571	/*
572	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
573	* once globally here instead of per-VM.
574	*/
575	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
576	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
577	if (RT_FAILURE(rc))
578	return rc;
579
580	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
581	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
582
583	/* Set all bits to intercept all IO accesses. */
584	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
585
586	#ifdef VBOX_WITH_NESTED_HWVIRT
587	/*
588	* Allocate 8 KB for the MSR permission bitmap for the nested-guest.
589	*/
590	Assert(g_hMemObjNstGstMsrBitmap == NIL_RTR0MEMOBJ);
591	rc = RTR0MemObjAllocCont(&g_hMemObjNstGstMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
592	if (RT_FAILURE(rc))
593	return rc;
594
595	g_pvNstGstMsrBitmap = RTR0MemObjAddress(g_hMemObjNstGstMsrBitmap);
596	g_HCPhysNstGstMsrBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjNstGstMsrBitmap, 0 /* iPage */);
597
598	/* Set all bits to intercept all MSR accesses. */
599	ASMMemFill32(g_pvNstGstMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
600	#endif
601
602	return VINF_SUCCESS;
603	}
604
605
606	/**
607	* Does global AMD-V termination (called during module termination).
608	*/
609	VMMR0DECL(void) SVMR0GlobalTerm(void)
610	{
611	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
612	{
613	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
614	g_pvIOBitmap = NULL;
615	g_HCPhysIOBitmap = 0;
616	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
617	}
618
619	#ifdef VBOX_WITH_NESTED_HWVIRT
620	if (g_hMemObjNstGstMsrBitmap != NIL_RTR0MEMOBJ)
621	{
622	RTR0MemObjFree(g_hMemObjNstGstMsrBitmap, true /* fFreeMappings */);
623	g_pvNstGstMsrBitmap = NULL;
624	g_HCPhysNstGstMsrBitmap = 0;
625	g_hMemObjNstGstMsrBitmap = NIL_RTR0MEMOBJ;
626	}
627	#endif
628	}
629
630
631	/**
632	* Frees any allocated per-VCPU structures for a VM.
633	*
634	* @param pVM The cross context VM structure.
635	*/
636	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
637	{
638	for (uint32_t i = 0; i < pVM->cCpus; i++)
639	{
640	PVMCPU pVCpu = &pVM->aCpus[i];
641	AssertPtr(pVCpu);
642
643	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
644	{
645	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
646	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
647	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
648	}
649
650	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
651	{
652	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
653	pVCpu->hm.s.svm.pVmcb = NULL;
654	pVCpu->hm.s.svm.HCPhysVmcb = 0;
655	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
656	}
657
658	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
659	{
660	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
661	pVCpu->hm.s.svm.pvMsrBitmap = NULL;
662	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
663	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
664	}
665	}
666	}
667
668
669	/**
670	* Does per-VM AMD-V initialization.
671	*
672	* @returns VBox status code.
673	* @param pVM The cross context VM structure.
674	*/
675	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
676	{
677	int rc = VERR_INTERNAL_ERROR_5;
678
679	/*
680	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
681	*/
682	uint32_t u32Family;
683	uint32_t u32Model;
684	uint32_t u32Stepping;
685	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
686	{
687	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
688	pVM->hm.s.svm.fAlwaysFlushTLB = true;
689	}
690
691	/*
692	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
693	*/
694	for (VMCPUID i = 0; i < pVM->cCpus; i++)
695	{
696	PVMCPU pVCpu = &pVM->aCpus[i];
697	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
698	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
699	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
700	}
701
702	for (VMCPUID i = 0; i < pVM->cCpus; i++)
703	{
704	PVMCPU pVCpu = &pVM->aCpus[i];
705
706	/*
707	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
708	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
709	*/
710	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
711	if (RT_FAILURE(rc))
712	goto failure_cleanup;
713
714	void *pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
715	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
716	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
717	ASMMemZeroPage(pvVmcbHost);
718
719	/*
720	* Allocate one page for the guest-state VMCB.
721	*/
722	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
723	if (RT_FAILURE(rc))
724	goto failure_cleanup;
725
726	pVCpu->hm.s.svm.pVmcb = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
727	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
728	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
729	ASMMemZeroPage(pVCpu->hm.s.svm.pVmcb);
730
731	/*
732	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
733	* SVM to not require one.
734	*/
735	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
736	false /* fExecutable */);
737	if (RT_FAILURE(rc))
738	goto failure_cleanup;
739
740	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
741	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
742	/* Set all bits to intercept all MSR accesses (changed later on). */
743	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
744	}
745
746	return VINF_SUCCESS;
747
748	failure_cleanup:
749	hmR0SvmFreeStructs(pVM);
750	return rc;
751	}
752
753
754	/**
755	* Does per-VM AMD-V termination.
756	*
757	* @returns VBox status code.
758	* @param pVM The cross context VM structure.
759	*/
760	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
761	{
762	hmR0SvmFreeStructs(pVM);
763	return VINF_SUCCESS;
764	}
765
766
767	/**
768	* Returns whether the VMCB Clean Bits feature is supported.
769	*
770	* @return @c true if supported, @c false otherwise.
771	* @param pVCpu The cross context virtual CPU structure.
772	* @param pCtx Pointer to the guest-CPU context.
773	*/
774	DECLINLINE(bool) hmR0SvmSupportsVmcbCleanBits(PVMCPU pVCpu, PCPUMCTX pCtx)
775	{
776	PVM pVM = pVCpu->CTX_SUFF(pVM);
777	#ifdef VBOX_WITH_NESTED_HWVIRT
778	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
779	{
780	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN)
781	&& pVM->cpum.ro.GuestFeatures.fSvmVmcbClean;
782	}
783	#else
784	RT_NOREF(pCtx);
785	#endif
786	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
787	}
788
789
790	/**
791	* Returns whether the decode assists feature is supported.
792	*
793	* @return @c true if supported, @c false otherwise.
794	* @param pVCpu The cross context virtual CPU structure.
795	* @param pCtx Pointer to the guest-CPU context.
796	*/
797	DECLINLINE(bool) hmR0SvmSupportsDecodeAssists(PVMCPU pVCpu, PCPUMCTX pCtx)
798	{
799	PVM pVM = pVCpu->CTX_SUFF(pVM);
800	#ifdef VBOX_WITH_NESTED_HWVIRT
801	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
802	{
803	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS)
804	&& pVM->cpum.ro.GuestFeatures.fSvmDecodeAssists;
805	}
806	#else
807	RT_NOREF(pCtx);
808	#endif
809	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
810	}
811
812
813	/**
814	* Returns whether the NRIP_SAVE feature is supported.
815	*
816	* @return @c true if supported, @c false otherwise.
817	* @param pVCpu The cross context virtual CPU structure.
818	* @param pCtx Pointer to the guest-CPU context.
819	*/
820	DECLINLINE(bool) hmR0SvmSupportsNextRipSave(PVMCPU pVCpu, PCPUMCTX pCtx)
821	{
822	PVM pVM = pVCpu->CTX_SUFF(pVM);
823	#ifdef VBOX_WITH_NESTED_HWVIRT
824	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
825	{
826	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
827	&& pVM->cpum.ro.GuestFeatures.fSvmNextRipSave;
828	}
829	#else
830	RT_NOREF(pCtx);
831	#endif
832	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
833	}
834
835
836	/**
837	* Sets the permission bits for the specified MSR in the MSRPM.
838	*
839	* @param pVmcb Pointer to the VM control block.
840	* @param pbMsrBitmap Pointer to the MSR bitmap.
841	* @param uMsr The MSR for which the access permissions are being set.
842	* @param enmRead MSR read permissions.
843	* @param enmWrite MSR write permissions.
844	*/
845	static void hmR0SvmSetMsrPermission(PSVMVMCB pVmcb, uint8_t *pbMsrBitmap, unsigned uMsr, SVMMSREXITREAD enmRead,
846	SVMMSREXITWRITE enmWrite)
847	{
848	uint16_t offMsrpm;
849	uint32_t uMsrpmBit;
850	int rc = HMSvmGetMsrpmOffsetAndBit(uMsr, &offMsrpm, &uMsrpmBit);
851	AssertRC(rc);
852
853	Assert(uMsrpmBit < 0x3fff);
854	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
855
856	pbMsrBitmap += offMsrpm;
857	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
858	ASMBitSet(pbMsrBitmap, uMsrpmBit);
859	else
860	ASMBitClear(pbMsrBitmap, uMsrpmBit);
861
862	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
863	ASMBitSet(pbMsrBitmap, uMsrpmBit + 1);
864	else
865	ASMBitClear(pbMsrBitmap, uMsrpmBit + 1);
866
867	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
868	}
869
870
871	/**
872	* Sets up AMD-V for the specified VM.
873	* This function is only called once per-VM during initalization.
874	*
875	* @returns VBox status code.
876	* @param pVM The cross context VM structure.
877	*/
878	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
879	{
880	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
881	AssertReturn(pVM, VERR_INVALID_PARAMETER);
882	Assert(pVM->hm.s.svm.fSupported);
883
884	bool const fPauseFilter = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
885	bool const fPauseFilterThreshold = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
886	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter && pVM->hm.s.svm.cPauseFilterThresholdTicks;
887
888	bool const fLbrVirt = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
889	bool const fUseLbrVirt = fLbrVirt; /** @todo CFGM, IEM implementation etc. */
890
891	#ifdef VBOX_WITH_NESTED_HWVIRT
892	bool const fVirtVmsaveVmload = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
893	bool const fUseVirtVmsaveVmload = fVirtVmsaveVmload && pVM->hm.s.svm.fVirtVmsaveVmload && pVM->hm.s.fNestedPaging;
894
895	bool const fVGif = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF);
896	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
897	#endif
898
899	for (VMCPUID i = 0; i < pVM->cCpus; i++)
900	{
901	PVMCPU pVCpu = &pVM->aCpus[i];
902	PSVMVMCB pVmcb = pVM->aCpus[i].hm.s.svm.pVmcb;
903
904	AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
905
906	/* Initialize the #VMEXIT history array with end-of-array markers (UINT16_MAX). */
907	Assert(!pVCpu->hm.s.idxExitHistoryFree);
908	HMCPU_EXIT_HISTORY_RESET(pVCpu);
909
910	/* Always trap #AC for reasons of security. */
911	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
912
913	/* Always trap #DB for reasons of security. */
914	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
915
916	/* Trap exceptions unconditionally (debug purposes). */
917	#ifdef HMSVM_ALWAYS_TRAP_PF
918	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
919	#endif
920	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
921	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
922	pVmcb->ctrl.u32InterceptXcpt \|= 0
923	\| RT_BIT(X86_XCPT_BP)
924	\| RT_BIT(X86_XCPT_DE)
925	\| RT_BIT(X86_XCPT_NM)
926	\| RT_BIT(X86_XCPT_UD)
927	\| RT_BIT(X86_XCPT_NP)
928	\| RT_BIT(X86_XCPT_SS)
929	\| RT_BIT(X86_XCPT_GP)
930	\| RT_BIT(X86_XCPT_PF)
931	\| RT_BIT(X86_XCPT_MF)
932	;
933	#endif
934
935	/* Set up unconditional intercepts and conditions. */
936	pVmcb->ctrl.u64InterceptCtrl = HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS
937	\| SVM_CTRL_INTERCEPT_VMMCALL;
938
939	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
940	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
941
942	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
943	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
944
945	/* Intercept all DRx reads and writes by default. Changed later on. */
946	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
947	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
948
949	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
950	pVmcb->ctrl.IntCtrl.n.u1VIntrMasking = 1;
951
952	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
953	and we currently deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
954	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
955
956	/* Set IO and MSR bitmap permission bitmap physical addresses. */
957	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
958	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
959
960	/* LBR virtualization. */
961	if (fUseLbrVirt)
962	{
963	pVmcb->ctrl.LbrVirt.n.u1LbrVirt = fUseLbrVirt;
964	pVmcb->guest.u64DBGCTL = MSR_IA32_DEBUGCTL_LBR;
965	}
966	else
967	Assert(pVmcb->ctrl.LbrVirt.n.u1LbrVirt == 0);
968
969	#ifdef VBOX_WITH_NESTED_HWVIRT
970	/* Virtualized VMSAVE/VMLOAD. */
971	pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload = fUseVirtVmsaveVmload;
972	if (!fUseVirtVmsaveVmload)
973	{
974	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
975	\| SVM_CTRL_INTERCEPT_VMLOAD;
976	}
977
978	/* Virtual GIF. */
979	pVmcb->ctrl.IntCtrl.n.u1VGifEnable = fUseVGif;
980	if (!fUseVGif)
981	{
982	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
983	\| SVM_CTRL_INTERCEPT_STGI;
984	}
985	#endif
986
987	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
988	Assert(pVmcb->ctrl.u32VmcbCleanBits == 0);
989
990	/* The host ASID MBZ, for the guest start with 1. */
991	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
992
993	/*
994	* Setup the PAT MSR (applicable for Nested Paging only).
995	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
996	* so choose type 6 for all PAT slots.
997	*/
998	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
999
1000	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
1001	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
1002
1003	/* Without Nested Paging, we need additionally intercepts. */
1004	if (!pVM->hm.s.fNestedPaging)
1005	{
1006	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
1007	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
1008	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
1009
1010	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
1011	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
1012	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
1013
1014	/* Page faults must be intercepted to implement shadow paging. */
1015	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
1016	}
1017
1018	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
1019	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
1020	#endif
1021
1022	/* Apply the exceptions intercepts needed by the GIM provider. */
1023	if (pVCpu->hm.s.fGIMTrapXcptUD)
1024	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
1025
1026	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
1027	if (fUsePauseFilter)
1028	{
1029	pVmcb->ctrl.u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
1030	if (fPauseFilterThreshold)
1031	pVmcb->ctrl.u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
1032	}
1033
1034	/*
1035	* The following MSRs are saved/restored automatically during the world-switch.
1036	* Don't intercept guest read/write accesses to these MSRs.
1037	*/
1038	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
1039	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1040	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1041	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1042	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1043	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1044	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1045	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1046	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1047	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1048	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1049	}
1050
1051	return VINF_SUCCESS;
1052	}
1053
1054
1055	/**
1056	* Gets a pointer to the currently active guest or nested-guest VMCB.
1057	*
1058	* @returns Pointer to the current context VMCB.
1059	* @param pVCpu The cross context virtual CPU structure.
1060	* @param pCtx Pointer to the guest-CPU context.
1061	*/
1062	DECLINLINE(PSVMVMCB) hmR0SvmGetCurrentVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
1063	{
1064	#ifdef VBOX_WITH_NESTED_HWVIRT
1065	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1066	return pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
1067	#else
1068	RT_NOREF(pCtx);
1069	#endif
1070	return pVCpu->hm.s.svm.pVmcb;
1071	}
1072
1073
1074	/**
1075	* Invalidates a guest page by guest virtual address.
1076	*
1077	* @returns VBox status code.
1078	* @param pVM The cross context VM structure.
1079	* @param pVCpu The cross context virtual CPU structure.
1080	* @param GCVirt Guest virtual address of the page to invalidate.
1081	*/
1082	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
1083	{
1084	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1085	Assert(pVM->hm.s.svm.fSupported);
1086
1087	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
1088
1089	/* Skip it if a TLB flush is already pending. */
1090	if (!fFlushPending)
1091	{
1092	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
1093
1094	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1095	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
1096	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
1097
1098	#if HC_ARCH_BITS == 32
1099	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
1100	if (CPUMIsGuestInLongMode(pVCpu))
1101	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1102	else
1103	#endif
1104	{
1105	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
1106	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1107	}
1108	}
1109	return VINF_SUCCESS;
1110	}
1111
1112
1113	/**
1114	* Flushes the appropriate tagged-TLB entries.
1115	*
1116	* @param pVCpu The cross context virtual CPU structure.
1117	* @param pCtx Pointer to the guest-CPU or nested-guest-CPU context.
1118	* @param pVmcb Pointer to the VM control block.
1119	*/
1120	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb)
1121	{
1122	#ifndef VBOX_WITH_NESTED_HWVIRT
1123	RT_NOREF(pCtx);
1124	#endif
1125
1126	PVM pVM = pVCpu->CTX_SUFF(pVM);
1127	PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
1128
1129	/*
1130	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
1131	* This can happen both for start & resume due to long jumps back to ring-3.
1132	*
1133	* We also force a TLB flush every time when executing a nested-guest VCPU as there is no correlation
1134	* between it and the physical CPU.
1135	*
1136	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
1137	* so we cannot reuse the ASIDs without flushing.
1138	*/
1139	bool fNewAsid = false;
1140	Assert(pCpu->idCpu != NIL_RTCPUID);
1141	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
1142	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes
1143	#ifdef VBOX_WITH_NESTED_HWVIRT
1144	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
1145	#endif
1146	)
1147	{
1148	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1149	pVCpu->hm.s.fForceTLBFlush = true;
1150	fNewAsid = true;
1151	}
1152
1153	/* Set TLB flush state as checked until we return from the world switch. */
1154	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
1155
1156	/* Check for explicit TLB flushes. */
1157	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1158	{
1159	pVCpu->hm.s.fForceTLBFlush = true;
1160	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1161	}
1162
1163	/*
1164	* If the AMD CPU erratum 170, We need to flush the entire TLB for each world switch. Sad.
1165	* This Host CPU requirement takes precedence.
1166	*/
1167	if (pVM->hm.s.svm.fAlwaysFlushTLB)
1168	{
1169	pCpu->uCurrentAsid = 1;
1170	pVCpu->hm.s.uCurrentAsid = 1;
1171	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1172	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1173
1174	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1175	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1176
1177	/* Keep track of last CPU ID even when flushing all the time. */
1178	if (fNewAsid)
1179	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1180	}
1181	else
1182	{
1183	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
1184	if (pVCpu->hm.s.fForceTLBFlush)
1185	{
1186	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1187	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1188
1189	if (fNewAsid)
1190	{
1191	++pCpu->uCurrentAsid;
1192
1193	bool fHitASIDLimit = false;
1194	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1195	{
1196	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
1197	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new ASID. */
1198	fHitASIDLimit = true;
1199	}
1200
1201	if ( fHitASIDLimit
1202	\|\| pCpu->fFlushAsidBeforeUse)
1203	{
1204	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1205	pCpu->fFlushAsidBeforeUse = false;
1206	}
1207
1208	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
1209	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
1210	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
1211	}
1212	else
1213	{
1214	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1215	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1216	else
1217	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1218	}
1219
1220	pVCpu->hm.s.fForceTLBFlush = false;
1221	}
1222	}
1223
1224	/* Update VMCB with the ASID. */
1225	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
1226	{
1227	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
1228	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
1229	}
1230
1231	AssertMsg(pVCpu->hm.s.idLastCpu == pCpu->idCpu,
1232	("vcpu idLastCpu=%u pcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pCpu->idCpu));
1233	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
1234	("Flush count mismatch for cpu %u (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
1235	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
1236	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
1237	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
1238	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1239
1240	#ifdef VBOX_WITH_STATISTICS
1241	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1242	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1243	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1244	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1245	{
1246	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1247	}
1248	else
1249	{
1250	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1251	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1252	}
1253	#endif
1254	}
1255
1256
1257	/** @name 64-bit guest on 32-bit host OS helper functions.
1258	*
1259	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
1260	* mode (code segment, paging). These wrappers/helpers perform the necessary
1261	* bits for the 32->64 switcher.
1262	*
1263	* @{ */
1264	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1265	/**
1266	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
1267	*
1268	* @returns VBox status code.
1269	* @param HCPhysVmcbHost Physical address of host VMCB.
1270	* @param HCPhysVmcb Physical address of the VMCB.
1271	* @param pCtx Pointer to the guest-CPU context.
1272	* @param pVM The cross context VM structure.
1273	* @param pVCpu The cross context virtual CPU structure.
1274	*/
1275	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
1276	{
1277	uint32_t aParam[8];
1278	aParam[0] = RT_LO_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
1279	aParam[1] = RT_HI_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Hi. */
1280	aParam[2] = RT_LO_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
1281	aParam[3] = RT_HI_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Hi. */
1282	aParam[4] = VM_RC_ADDR(pVM, pVM);
1283	aParam[5] = 0;
1284	aParam[6] = VM_RC_ADDR(pVM, pVCpu);
1285	aParam[7] = 0;
1286
1287	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, RT_ELEMENTS(aParam), &aParam[0]);
1288	}
1289
1290
1291	/**
1292	* Executes the specified VMRUN handler in 64-bit mode.
1293	*
1294	* @returns VBox status code.
1295	* @param pVM The cross context VM structure.
1296	* @param pVCpu The cross context virtual CPU structure.
1297	* @param pCtx Pointer to the guest-CPU context.
1298	* @param enmOp The operation to perform.
1299	* @param cParams Number of parameters.
1300	* @param paParam Array of 32-bit parameters.
1301	*/
1302	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp,
1303	uint32_t cParams, uint32_t *paParam)
1304	{
1305	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1306	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1307
1308	NOREF(pCtx);
1309
1310	/* Disable interrupts. */
1311	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
1312
1313	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1314	RTCPUID idHostCpu = RTMpCpuId();
1315	CPUMR0SetLApic(pVCpu, idHostCpu);
1316	#endif
1317
1318	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1319	CPUMSetHyperEIP(pVCpu, enmOp);
1320	for (int i = (int)cParams - 1; i >= 0; i--)
1321	CPUMPushHyper(pVCpu, paParam[i]);
1322
1323	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1324	/* Call the switcher. */
1325	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1326	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1327
1328	/* Restore interrupts. */
1329	ASMSetFlags(uOldEFlags);
1330	return rc;
1331	}
1332
1333	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1334	/** @} */
1335
1336
1337	/**
1338	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1339	* the corresponding VMCB Clean bit.
1340	*
1341	* @param pVmcb Pointer to the VM control block.
1342	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1343	*/
1344	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1345	{
1346	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt)))
1347	{
1348	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(u32Xcpt);
1349	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1350	}
1351	}
1352
1353
1354	/**
1355	* Removes an exception from the intercept-exception bitmap in the VMCB and
1356	* updates the corresponding VMCB Clean bit.
1357	*
1358	* @param pVCpu The cross context virtual CPU structure.
1359	* @param pCtx Pointer to the guest-CPU context.
1360	* @param pVmcb Pointer to the VM control block.
1361	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1362	*
1363	* @remarks This takes into account if we're executing a nested-guest and only
1364	* removes the exception intercept if both the guest -and- nested-guest
1365	* are not intercepting it.
1366	*/
1367	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb, uint32_t u32Xcpt)
1368	{
1369	Assert(u32Xcpt != X86_XCPT_DB);
1370	Assert(u32Xcpt != X86_XCPT_AC);
1371	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1372	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt))
1373	{
1374	bool fRemoveXcpt = true;
1375	#ifdef VBOX_WITH_NESTED_HWVIRT
1376	/* Only remove the intercept if the nested-guest is also not intercepting it! */
1377	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1378	{
1379	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); NOREF(pCtx);
1380	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
1381	fRemoveXcpt = !(pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(u32Xcpt));
1382	}
1383	#else
1384	RT_NOREF2(pVCpu, pCtx);
1385	#endif
1386	if (fRemoveXcpt)
1387	{
1388	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(u32Xcpt);
1389	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1390	}
1391	}
1392	#else
1393	RT_NOREF3(pVCpu, pCtx, pVmcb);
1394	#endif
1395	}
1396
1397
1398	/**
1399	* Loads the guest (or nested-guest) CR0 control register into the guest-state
1400	* area in the VMCB.
1401	*
1402	* Although the guest CR0 is a separate field in the VMCB we have to consider
1403	* the FPU state itself which is shared between the host and the guest.
1404	*
1405	* @returns VBox status code.
1406	* @param pVCpu The cross context virtual CPU structure.
1407	* @param pVmcb Pointer to the VM control block.
1408	* @param pCtx Pointer to the guest-CPU context.
1409	*
1410	* @remarks No-long-jump zone!!!
1411	*/
1412	static void hmR0SvmLoadSharedCR0(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1413	{
1414	uint64_t u64GuestCR0 = pCtx->cr0;
1415
1416	/* Always enable caching. */
1417	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1418
1419	/*
1420	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1421	*/
1422	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1423	{
1424	u64GuestCR0 \|= X86_CR0_PG /* When Nested Paging is not available, use shadow page tables. */
1425	\| X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1426	}
1427
1428	/*
1429	* Guest FPU bits.
1430	*/
1431	bool fInterceptNM = false;
1432	bool fInterceptMF = false;
1433	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1434	if (CPUMIsGuestFPUStateActive(pVCpu))
1435	{
1436	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1437	if (!(pCtx->cr0 & X86_CR0_NE))
1438	{
1439	Log4(("hmR0SvmLoadSharedCR0: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1440	fInterceptMF = true;
1441	}
1442	}
1443	else
1444	{
1445	fInterceptNM = true; /* Guest FPU inactive, #VMEXIT on #NM for lazy FPU loading. */
1446	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1447	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1448	}
1449
1450	/*
1451	* Update the exception intercept bitmap.
1452	*/
1453	if (fInterceptNM)
1454	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1455	else
1456	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_NM);
1457
1458	if (fInterceptMF)
1459	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1460	else
1461	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_MF);
1462
1463	pVmcb->guest.u64CR0 = u64GuestCR0;
1464	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1465	}
1466
1467
1468	/**
1469	* Loads the guest/nested-guest control registers (CR2, CR3, CR4) into the VMCB.
1470	*
1471	* @returns VBox status code.
1472	* @param pVCpu The cross context virtual CPU structure.
1473	* @param pVmcb Pointer to the VM control block.
1474	* @param pCtx Pointer to the guest-CPU context.
1475	*
1476	* @remarks No-long-jump zone!!!
1477	*/
1478	static int hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1479	{
1480	PVM pVM = pVCpu->CTX_SUFF(pVM);
1481
1482	/*
1483	* Guest CR2.
1484	*/
1485	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR2))
1486	{
1487	pVmcb->guest.u64CR2 = pCtx->cr2;
1488	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1489	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
1490	}
1491
1492	/*
1493	* Guest CR3.
1494	*/
1495	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
1496	{
1497	if (pVM->hm.s.fNestedPaging)
1498	{
1499	PGMMODE enmShwPagingMode;
1500	#if HC_ARCH_BITS == 32
1501	if (CPUMIsGuestInLongModeEx(pCtx))
1502	enmShwPagingMode = PGMMODE_AMD64_NX;
1503	else
1504	#endif
1505	enmShwPagingMode = PGMGetHostMode(pVM);
1506
1507	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1508	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1509	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1510	pVmcb->guest.u64CR3 = pCtx->cr3;
1511	}
1512	else
1513	{
1514	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1515	Log4(("hmR0SvmLoadGuestControlRegs: CR3=%#RX64 (HyperCR3=%#RX64)\n", pCtx->cr3, pVmcb->guest.u64CR3));
1516	}
1517
1518	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1519	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
1520	}
1521
1522	/*
1523	* Guest CR4.
1524	* ASSUMES this is done everytime we get in from ring-3! (XCR0)
1525	*/
1526	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
1527	{
1528	uint64_t u64GuestCR4 = pCtx->cr4;
1529	Assert(RT_HI_U32(u64GuestCR4) == 0);
1530	if (!pVM->hm.s.fNestedPaging)
1531	{
1532	switch (pVCpu->hm.s.enmShadowMode)
1533	{
1534	case PGMMODE_REAL:
1535	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1536	AssertFailed();
1537	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1538
1539	case PGMMODE_32_BIT: /* 32-bit paging. */
1540	u64GuestCR4 &= ~X86_CR4_PAE;
1541	break;
1542
1543	case PGMMODE_PAE: /* PAE paging. */
1544	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1545	/** Must use PAE paging as we could use physical memory > 4 GB */
1546	u64GuestCR4 \|= X86_CR4_PAE;
1547	break;
1548
1549	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1550	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1551	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1552	break;
1553	#else
1554	AssertFailed();
1555	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1556	#endif
1557
1558	default: /* shut up gcc */
1559	AssertFailed();
1560	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1561	}
1562	}
1563
1564	pVmcb->guest.u64CR4 = u64GuestCR4;
1565	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1566
1567	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1568	pVCpu->hm.s.fLoadSaveGuestXcr0 = (u64GuestCR4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1569
1570	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
1571	}
1572
1573	return VINF_SUCCESS;
1574	}
1575
1576
1577	/**
1578	* Loads the guest (or nested-guest) segment registers into the VMCB.
1579	*
1580	* @returns VBox status code.
1581	* @param pVCpu The cross context virtual CPU structure.
1582	* @param pVmcb Pointer to the VM control block.
1583	* @param pCtx Pointer to the guest-CPU context.
1584	*
1585	* @remarks No-long-jump zone!!!
1586	*/
1587	static void hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1588	{
1589	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1590	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
1591	{
1592	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1593	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1594	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1595	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1596	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1597	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1598
1599	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1600	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1601	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
1602	}
1603
1604	/* Guest TR. */
1605	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
1606	{
1607	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1608	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
1609	}
1610
1611	/* Guest LDTR. */
1612	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
1613	{
1614	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1615	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
1616	}
1617
1618	/* Guest GDTR. */
1619	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
1620	{
1621	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1622	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1623	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1624	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
1625	}
1626
1627	/* Guest IDTR. */
1628	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
1629	{
1630	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1631	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1632	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1633	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
1634	}
1635	}
1636
1637
1638	/**
1639	* Loads the guest (or nested-guest) MSRs into the VMCB.
1640	*
1641	* @param pVCpu The cross context virtual CPU structure.
1642	* @param pVmcb Pointer to the VM control block.
1643	* @param pCtx Pointer to the guest-CPU context.
1644	*
1645	* @remarks No-long-jump zone!!!
1646	*/
1647	static void hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1648	{
1649	/* Guest Sysenter MSRs. */
1650	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1651	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1652	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1653
1654	/*
1655	* Guest EFER MSR.
1656	* AMD-V requires guest EFER.SVME to be set. Weird.
1657	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1658	*/
1659	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_EFER_MSR))
1660	{
1661	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1662	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1663	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
1664	}
1665
1666	/* 64-bit MSRs. */
1667	if (CPUMIsGuestInLongModeEx(pCtx))
1668	{
1669	/* Load these always as the guest may modify FS/GS base using MSRs in 64-bit mode which we don't intercept. */
1670	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1671	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1672	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1673	}
1674	else
1675	{
1676	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1677	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1678	{
1679	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1680	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1681	}
1682	}
1683
1684	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1685	* be writable in 32-bit mode. Clarify with AMD spec. */
1686	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1687	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1688	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1689	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1690	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1691	}
1692
1693
1694	/**
1695	* Loads the guest (or nested-guest) debug state into the VMCB and programs the
1696	* necessary intercepts accordingly.
1697	*
1698	* @param pVCpu The cross context virtual CPU structure.
1699	* @param pVmcb Pointer to the VM control block.
1700	* @param pCtx Pointer to the guest-CPU context.
1701	*
1702	* @remarks No-long-jump zone!!!
1703	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1704	*/
1705	static void hmR0SvmLoadSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1706	{
1707	bool fInterceptMovDRx = false;
1708
1709	/*
1710	* Anyone single stepping on the host side? If so, we'll have to use the
1711	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1712	* the VMM level like the VT-x implementations does.
1713	*/
1714	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1715	if (fStepping)
1716	{
1717	pVCpu->hm.s.fClearTrapFlag = true;
1718	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1719	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1720	}
1721
1722	if ( fStepping
1723	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1724	{
1725	/*
1726	* Use the combined guest and host DRx values found in the hypervisor
1727	* register set because the debugger has breakpoints active or someone
1728	* is single stepping on the host side.
1729	*
1730	* Note! DBGF expects a clean DR6 state before executing guest code.
1731	*/
1732	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1733	if ( CPUMIsGuestInLongModeEx(pCtx)
1734	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
1735	{
1736	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1737	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1738	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1739	}
1740	else
1741	#endif
1742	if (!CPUMIsHyperDebugStateActive(pVCpu))
1743	{
1744	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1745	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1746	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1747	}
1748
1749	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1750	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1751	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1752	{
1753	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1754	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1755	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1756	pVCpu->hm.s.fUsingHyperDR7 = true;
1757	}
1758
1759	/** @todo If we cared, we could optimize to allow the guest to read registers
1760	* with the same values. */
1761	fInterceptMovDRx = true;
1762	Log5(("hmR0SvmLoadSharedDebugState: Loaded hyper DRx\n"));
1763	}
1764	else
1765	{
1766	/*
1767	* Update DR6, DR7 with the guest values if necessary.
1768	*/
1769	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1770	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1771	{
1772	pVmcb->guest.u64DR7 = pCtx->dr[7];
1773	pVmcb->guest.u64DR6 = pCtx->dr[6];
1774	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1775	pVCpu->hm.s.fUsingHyperDR7 = false;
1776	}
1777
1778	/*
1779	* If the guest has enabled debug registers, we need to load them prior to
1780	* executing guest code so they'll trigger at the right time.
1781	*/
1782	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1783	{
1784	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1785	if ( CPUMIsGuestInLongModeEx(pCtx)
1786	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1787	{
1788	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1789	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1790	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1791	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1792	}
1793	else
1794	#endif
1795	if (!CPUMIsGuestDebugStateActive(pVCpu))
1796	{
1797	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1798	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1799	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1800	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1801	}
1802	Log5(("hmR0SvmLoadSharedDebugState: Loaded guest DRx\n"));
1803	}
1804	/*
1805	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1806	* intercept #DB as DR6 is updated in the VMCB.
1807	*
1808	* Note! If we cared and dared, we could skip intercepting \#DB here.
1809	* However, \#DB shouldn't be performance critical, so we'll play safe
1810	* and keep the code similar to the VT-x code and always intercept it.
1811	*/
1812	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1813	else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
1814	&& !CPUMIsGuestDebugStateActive(pVCpu))
1815	#else
1816	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1817	#endif
1818	{
1819	fInterceptMovDRx = true;
1820	}
1821	}
1822
1823	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
1824	if (fInterceptMovDRx)
1825	{
1826	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1827	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1828	{
1829	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1830	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1831	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1832	}
1833	}
1834	else
1835	{
1836	if ( pVmcb->ctrl.u16InterceptRdDRx
1837	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1838	{
1839	pVmcb->ctrl.u16InterceptRdDRx = 0;
1840	pVmcb->ctrl.u16InterceptWrDRx = 0;
1841	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1842	}
1843	}
1844	Log4(("hmR0SvmLoadSharedDebugState: DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
1845	}
1846
1847
1848	#ifdef VBOX_WITH_NESTED_HWVIRT
1849	/**
1850	* Loads the nested-guest APIC state (currently just the TPR).
1851	*
1852	* @param pVCpu The cross context virtual CPU structure.
1853	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1854	*/
1855	static void hmR0SvmLoadGuestApicStateNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst)
1856	{
1857	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1858	{
1859	/* Always enable V_INTR_MASKING as we do not want to allow access to the physical APIC TPR. */
1860	pVmcbNstGst->ctrl.IntCtrl.n.u1VIntrMasking = 1;
1861	pVCpu->hm.s.svm.fSyncVTpr = false;
1862	pVmcbNstGst->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_TPR;
1863
1864	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1865	}
1866	}
1867	#endif
1868
1869	/**
1870	* Loads the guest APIC state (currently just the TPR).
1871	*
1872	* @returns VBox status code.
1873	* @param pVCpu The cross context virtual CPU structure.
1874	* @param pVmcb Pointer to the VM control block.
1875	* @param pCtx Pointer to the guest-CPU context.
1876	*/
1877	static int hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1878	{
1879	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1880	return VINF_SUCCESS;
1881
1882	int rc = VINF_SUCCESS;
1883	PVM pVM = pVCpu->CTX_SUFF(pVM);
1884	if ( PDMHasApic(pVM)
1885	&& APICIsEnabled(pVCpu))
1886	{
1887	bool fPendingIntr;
1888	uint8_t u8Tpr;
1889	rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1890	AssertRCReturn(rc, rc);
1891
1892	/* Assume that we need to trap all TPR accesses and thus need not check on
1893	every #VMEXIT if we should update the TPR. */
1894	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
1895	pVCpu->hm.s.svm.fSyncVTpr = false;
1896
1897	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1898	if (pVM->hm.s.fTPRPatchingActive)
1899	{
1900	pCtx->msrLSTAR = u8Tpr;
1901	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
1902
1903	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1904	if (fPendingIntr)
1905	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1906	else
1907	{
1908	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1909	pVCpu->hm.s.svm.fSyncVTpr = true;
1910	}
1911	}
1912	else
1913	{
1914	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1915	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1916
1917	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1918	if (fPendingIntr)
1919	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1920	else
1921	{
1922	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1923	pVCpu->hm.s.svm.fSyncVTpr = true;
1924	}
1925
1926	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1927	}
1928	}
1929
1930	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1931	return rc;
1932	}
1933
1934
1935	/**
1936	* Loads the exception interrupts required for guest (or nested-guest) execution in
1937	* the VMCB.
1938	*
1939	* @param pVCpu The cross context virtual CPU structure.
1940	* @param pVmcb Pointer to the VM control block.
1941	* @param pCtx Pointer to the guest-CPU context.
1942	*/
1943	static void hmR0SvmLoadGuestXcptIntercepts(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1944	{
1945	/* If we modify intercepts from here, please check & adjust hmR0SvmLoadGuestXcptInterceptsNested()
1946	if required. */
1947	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1948	{
1949	/* Trap #UD for GIM provider (e.g. for hypercalls). */
1950	if (pVCpu->hm.s.fGIMTrapXcptUD)
1951	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_UD);
1952	else
1953	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_UD);
1954
1955	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
1956	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
1957	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_BP);
1958	else
1959	hmR0SvmRemoveXcptIntercept(pVCpu, pCtx, pVmcb, X86_XCPT_BP);
1960
1961	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmLoadSharedCR0(). */
1962	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
1963	}
1964	}
1965
1966
1967	#ifdef VBOX_WITH_NESTED_HWVIRT
1968	/**
1969	* Loads the intercepts required for nested-guest execution in the VMCB.
1970	*
1971	* This merges the guest and nested-guest intercepts in a way that if the outer
1972	* guest intercepts an exception we need to intercept it in the nested-guest as
1973	* well and handle it accordingly.
1974	*
1975	* @param pVCpu The cross context virtual CPU structure.
1976	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
1977	* @param pCtx Pointer to the guest-CPU context.
1978	*/
1979	static void hmR0SvmLoadGuestXcptInterceptsNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst, PCPUMCTX pCtx)
1980	{
1981	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1982	{
1983	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
1984
1985	/* Merge the guest's CR intercepts into the nested-guest VMCB. */
1986	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= pVmcb->ctrl.u16InterceptRdCRx;
1987	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= pVmcb->ctrl.u16InterceptWrCRx;
1988
1989	/* Always intercept CR0, CR4 reads and writes as we alter them. */
1990	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= RT_BIT(0) \| RT_BIT(4);
1991	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= RT_BIT(0) \| RT_BIT(4);
1992
1993	/* Without nested paging, intercept CR3 reads and writes as we load shadow page tables. */
1994	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1995	{
1996	pVmcbNstGst->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
1997	pVmcbNstGst->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
1998	}
1999
2000	/** @todo Figure out debugging with nested-guests, till then just intercept
2001	* all DR[0-15] accesses. */
2002	pVmcbNstGst->ctrl.u16InterceptRdDRx \|= 0xffff;
2003	pVmcbNstGst->ctrl.u16InterceptWrDRx \|= 0xffff;
2004
2005	/*
2006	* Merge the guest's exception intercepts into the nested-guest VMCB.
2007	*
2008	* - \#UD: Exclude these as the outer guest's GIM hypercalls are not applicable
2009	* while executing the nested-guest.
2010	*
2011	* - \#BP: Exclude breakpoints set by the VM debugger for the outer guest. This can
2012	* be tweaked later depending on how we wish to implement breakpoints.
2013	*
2014	* Warning!! This ASSUMES we only intercept \#UD for hypercall purposes and \#BP
2015	* for VM debugger breakpoints, see hmR0SvmLoadGuestXcptIntercepts.
2016	*/
2017	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
2018	pVmcbNstGst->ctrl.u32InterceptXcpt \|= (pVmcb->ctrl.u32InterceptXcpt & ~( RT_BIT(X86_XCPT_UD)
2019	\| RT_BIT(X86_XCPT_BP)));
2020	#else
2021	pVmcbNstGst->ctrl.u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt;
2022	#endif
2023
2024	/*
2025	* Adjust intercepts while executing the nested-guest that differ from the
2026	* outer guest intercepts.
2027	*
2028	* - VINTR: Exclude the outer guest intercept as we don't need to cause VINTR #VMEXITs
2029	* that belong to the nested-guest to the outer guest.
2030	*
2031	* - VMMCALL: Exclude the outer guest intercept as when it's also not intercepted by
2032	* the nested-guest, the physical CPU raises a \#UD exception as expected.
2033	*/
2034	pVmcbNstGst->ctrl.u64InterceptCtrl \|= (pVmcb->ctrl.u64InterceptCtrl & ~( SVM_CTRL_INTERCEPT_VINTR
2035	\| SVM_CTRL_INTERCEPT_VMMCALL))
2036	\| HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
2037
2038	Assert( (pVmcbNstGst->ctrl.u64InterceptCtrl & HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS)
2039	== HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
2040
2041	/*
2042	* If we don't expose Virtualized-VMSAVE/VMLOAD feature to the outer guest, we
2043	* need to intercept VMSAVE/VMLOAD instructions executed by the nested-guest.
2044	*/
2045	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVirtVmsaveVmload)
2046	{
2047	pVmcbNstGst->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
2048	\| SVM_CTRL_INTERCEPT_VMLOAD;
2049	}
2050
2051	/*
2052	* If we don't expose Virtual GIF feature to the outer guest, we need to intercept
2053	* CLGI/STGI instructions executed by the nested-guest.
2054	*/
2055	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVGif)
2056	{
2057	pVmcbNstGst->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
2058	\| SVM_CTRL_INTERCEPT_STGI;
2059	}
2060
2061	/* Finally, update the VMCB clean bits. */
2062	pVmcbNstGst->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2063	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
2064	}
2065	}
2066	#endif
2067
2068
2069	/**
2070	* Sets up the appropriate function to run guest code.
2071	*
2072	* @returns VBox status code.
2073	* @param pVCpu The cross context virtual CPU structure.
2074	*
2075	* @remarks No-long-jump zone!!!
2076	*/
2077	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu)
2078	{
2079	if (CPUMIsGuestInLongMode(pVCpu))
2080	{
2081	#ifndef VBOX_ENABLE_64_BITS_GUESTS
2082	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
2083	#endif
2084	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
2085	#if HC_ARCH_BITS == 32
2086	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
2087	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
2088	#else
2089	/* 64-bit host or hybrid host. */
2090	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
2091	#endif
2092	}
2093	else
2094	{
2095	/* Guest is not in long mode, use the 32-bit handler. */
2096	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
2097	}
2098	return VINF_SUCCESS;
2099	}
2100
2101
2102	/**
2103	* Enters the AMD-V session.
2104	*
2105	* @returns VBox status code.
2106	* @param pVM The cross context VM structure.
2107	* @param pVCpu The cross context virtual CPU structure.
2108	* @param pCpu Pointer to the CPU info struct.
2109	*/
2110	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
2111	{
2112	AssertPtr(pVM);
2113	AssertPtr(pVCpu);
2114	Assert(pVM->hm.s.svm.fSupported);
2115	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2116	NOREF(pVM); NOREF(pCpu);
2117
2118	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
2119	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
2120
2121	pVCpu->hm.s.fLeaveDone = false;
2122	return VINF_SUCCESS;
2123	}
2124
2125
2126	/**
2127	* Thread-context callback for AMD-V.
2128	*
2129	* @param enmEvent The thread-context event.
2130	* @param pVCpu The cross context virtual CPU structure.
2131	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
2132	* @thread EMT(pVCpu)
2133	*/
2134	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
2135	{
2136	NOREF(fGlobalInit);
2137
2138	switch (enmEvent)
2139	{
2140	case RTTHREADCTXEVENT_OUT:
2141	{
2142	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2143	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2144	VMCPU_ASSERT_EMT(pVCpu);
2145
2146	/* No longjmps (log-flush, locks) in this fragile context. */
2147	VMMRZCallRing3Disable(pVCpu);
2148
2149	if (!pVCpu->hm.s.fLeaveDone)
2150	{
2151	hmR0SvmLeave(pVCpu);
2152	pVCpu->hm.s.fLeaveDone = true;
2153	}
2154
2155	/* Leave HM context, takes care of local init (term). */
2156	int rc = HMR0LeaveCpu(pVCpu);
2157	AssertRC(rc); NOREF(rc);
2158
2159	/* Restore longjmp state. */
2160	VMMRZCallRing3Enable(pVCpu);
2161	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
2162	break;
2163	}
2164
2165	case RTTHREADCTXEVENT_IN:
2166	{
2167	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2168	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2169	VMCPU_ASSERT_EMT(pVCpu);
2170
2171	/* No longjmps (log-flush, locks) in this fragile context. */
2172	VMMRZCallRing3Disable(pVCpu);
2173
2174	/*
2175	* Initialize the bare minimum state required for HM. This takes care of
2176	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
2177	*/
2178	int rc = HMR0EnterCpu(pVCpu);
2179	AssertRC(rc); NOREF(rc);
2180	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
2181
2182	pVCpu->hm.s.fLeaveDone = false;
2183
2184	/* Restore longjmp state. */
2185	VMMRZCallRing3Enable(pVCpu);
2186	break;
2187	}
2188
2189	default:
2190	break;
2191	}
2192	}
2193
2194
2195	/**
2196	* Saves the host state.
2197	*
2198	* @returns VBox status code.
2199	* @param pVM The cross context VM structure.
2200	* @param pVCpu The cross context virtual CPU structure.
2201	*
2202	* @remarks No-long-jump zone!!!
2203	*/
2204	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
2205	{
2206	NOREF(pVM);
2207	NOREF(pVCpu);
2208	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
2209	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
2210	return VINF_SUCCESS;
2211	}
2212
2213
2214	/**
2215	* Loads the guest state into the VMCB.
2216	*
2217	* The CPU state will be loaded from these fields on every successful VM-entry.
2218	* Also sets up the appropriate VMRUN function to execute guest code based on
2219	* the guest CPU mode.
2220	*
2221	* @returns VBox status code.
2222	* @param pVM The cross context VM structure.
2223	* @param pVCpu The cross context virtual CPU structure.
2224	* @param pCtx Pointer to the guest-CPU context.
2225	*
2226	* @remarks No-long-jump zone!!!
2227	*/
2228	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2229	{
2230	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
2231
2232	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2233	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
2234
2235	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
2236
2237	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
2238	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2239
2240	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
2241	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
2242
2243	pVmcb->guest.u64RIP = pCtx->rip;
2244	pVmcb->guest.u64RSP = pCtx->rsp;
2245	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
2246	pVmcb->guest.u64RAX = pCtx->rax;
2247
2248	#ifdef VBOX_WITH_NESTED_HWVIRT
2249	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable == 1)
2250	{
2251	Assert(pVM->hm.s.svm.fVGif);
2252	pVmcb->ctrl.IntCtrl.n.u1VGif = pCtx->hwvirt.fGif;
2253	}
2254	#endif
2255
2256	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
2257	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2258
2259	hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb, pCtx);
2260
2261	rc = hmR0SvmSetupVMRunHandler(pVCpu);
2262	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
2263
2264	/* Clear any unused and reserved bits. */
2265	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
2266	\| HM_CHANGED_GUEST_RSP
2267	\| HM_CHANGED_GUEST_RFLAGS
2268	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
2269	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
2270	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
2271	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
2272	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
2273	\| HM_CHANGED_SVM_RESERVED2
2274	\| HM_CHANGED_SVM_RESERVED3
2275	\| HM_CHANGED_SVM_RESERVED4);
2276
2277	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
2278	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
2279	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
2280	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2281
2282	#ifdef VBOX_STRICT
2283	hmR0SvmLogState(pVCpu, pVmcb, pCtx, "hmR0SvmLoadGuestState", 0 /* fFlags /, 0 / uVerbose */);
2284	#endif
2285	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
2286	return rc;
2287	}
2288
2289
2290	#ifdef VBOX_WITH_NESTED_HWVIRT
2291	/**
2292	* Caches the nested-guest VMCB fields before we modify them for execution using
2293	* hardware-assisted SVM.
2294	*
2295	* @returns true if the VMCB was previously already cached, false otherwise.
2296	* @param pCtx Pointer to the guest-CPU context.
2297	*
2298	* @sa HMSvmNstGstVmExitNotify.
2299	*/
2300	static bool hmR0SvmVmRunCacheVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
2301	{
2302	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2303	PCSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2304	PCSVMVMCBSTATESAVE pVmcbNstGstState = &pVmcbNstGst->guest;
2305	PSVMNESTEDVMCBCACHE pNstGstVmcbCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2306
2307	/*
2308	* Cache the nested-guest programmed VMCB fields if we have not cached it yet.
2309	* Otherwise we risk re-caching the values we may have modified, see @bugref{7243#c44}.
2310	*
2311	* Nested-paging CR3 is not saved back into the VMCB on #VMEXIT, hence no need to
2312	* cache and restore it, see AMD spec. 15.25.4 "Nested Paging and VMRUN/#VMEXIT".
2313	*/
2314	bool const fWasCached = pCtx->hwvirt.svm.fHMCachedVmcb;
2315	if (!fWasCached)
2316	{
2317	pNstGstVmcbCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
2318	pNstGstVmcbCache->u16InterceptWrCRx = pVmcbNstGstCtrl->u16InterceptWrCRx;
2319	pNstGstVmcbCache->u16InterceptRdDRx = pVmcbNstGstCtrl->u16InterceptRdDRx;
2320	pNstGstVmcbCache->u16InterceptWrDRx = pVmcbNstGstCtrl->u16InterceptWrDRx;
2321	pNstGstVmcbCache->u32InterceptXcpt = pVmcbNstGstCtrl->u32InterceptXcpt;
2322	pNstGstVmcbCache->u64InterceptCtrl = pVmcbNstGstCtrl->u64InterceptCtrl;
2323	pNstGstVmcbCache->u64CR0 = pVmcbNstGstState->u64CR0;
2324	pNstGstVmcbCache->u64CR3 = pVmcbNstGstState->u64CR3;
2325	pNstGstVmcbCache->u64CR4 = pVmcbNstGstState->u64CR4;
2326	pNstGstVmcbCache->u64EFER = pVmcbNstGstState->u64EFER;
2327	pNstGstVmcbCache->u64DBGCTL = pVmcbNstGstState->u64DBGCTL;
2328	pNstGstVmcbCache->u64IOPMPhysAddr = pVmcbNstGstCtrl->u64IOPMPhysAddr;
2329	pNstGstVmcbCache->u64MSRPMPhysAddr = pVmcbNstGstCtrl->u64MSRPMPhysAddr;
2330	pNstGstVmcbCache->u64TSCOffset = pVmcbNstGstCtrl->u64TSCOffset;
2331	pNstGstVmcbCache->u32VmcbCleanBits = pVmcbNstGstCtrl->u32VmcbCleanBits;
2332	pNstGstVmcbCache->fVIntrMasking = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
2333	pNstGstVmcbCache->TLBCtrl = pVmcbNstGstCtrl->TLBCtrl;
2334	pNstGstVmcbCache->u1NestedPaging = pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging;
2335	pNstGstVmcbCache->u1LbrVirt = pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt;
2336	pCtx->hwvirt.svm.fHMCachedVmcb = true;
2337	Log4(("hmR0SvmVmRunCacheVmcb: Cached VMCB fields\n"));
2338	}
2339
2340	return fWasCached;
2341	}
2342
2343
2344	/**
2345	* Sets up the nested-guest VMCB for execution using hardware-assisted SVM.
2346	*
2347	* @param pVCpu The cross context virtual CPU structure.
2348	* @param pCtx Pointer to the guest-CPU context.
2349	*/
2350	static void hmR0SvmVmRunSetupVmcb(PVMCPU pVCpu, PCPUMCTX pCtx)
2351	{
2352	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2353	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2354
2355	/*
2356	* First cache the nested-guest VMCB fields we may potentially modify.
2357	*/
2358	bool const fVmcbCached = hmR0SvmVmRunCacheVmcb(pVCpu, pCtx);
2359	if (!fVmcbCached)
2360	{
2361	/*
2362	* The IOPM of the nested-guest can be ignored because the the guest always
2363	* intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
2364	* into the nested-guest one and swap it back on the #VMEXIT.
2365	*/
2366	pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
2367
2368	/*
2369	* Load the host-physical address into the MSRPM rather than the nested-guest
2370	* physical address (currently we trap all MSRs in the nested-guest).
2371	*/
2372	pVmcbNstGstCtrl->u64MSRPMPhysAddr = g_HCPhysNstGstMsrBitmap;
2373
2374	/*
2375	* Use the same nested-paging as the "outer" guest. We can't dynamically
2376	* switch off nested-paging suddenly while executing a VM (see assertion at the
2377	* end of Trap0eHandler in PGMAllBth.h).
2378	*/
2379	pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging;
2380
2381	/* For now copy the LBR info. from outer guest VMCB. */
2382	/** @todo fix this later. */
2383	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2384	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcb->ctrl.LbrVirt.n.u1LbrVirt;
2385	pVmcbNstGst->guest.u64DBGCTL = pVmcb->guest.u64DBGCTL;
2386	}
2387	else
2388	{
2389	Assert(pVmcbNstGstCtrl->u64IOPMPhysAddr == g_HCPhysIOBitmap);
2390	Assert(pVmcbNstGstCtrl->u64MSRPMPhysAddr = g_HCPhysNstGstMsrBitmap);
2391	Assert(RT_BOOL(pVmcbNstGstCtrl->NestedPaging.n.u1NestedPaging) == pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
2392	}
2393	}
2394
2395
2396	/**
2397	* Loads the nested-guest state into the VMCB.
2398	*
2399	* @returns VBox status code.
2400	* @param pVCpu The cross context virtual CPU structure.
2401	* @param pCtx Pointer to the guest-CPU context.
2402	*
2403	* @remarks No-long-jump zone!!!
2404	*/
2405	static int hmR0SvmLoadGuestStateNested(PVMCPU pVCpu, PCPUMCTX pCtx)
2406	{
2407	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
2408
2409	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2410	Assert(pVmcbNstGst);
2411
2412	hmR0SvmVmRunSetupVmcb(pVCpu, pCtx);
2413
2414	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcbNstGst, pCtx);
2415	AssertRCReturn(rc, rc);
2416
2417	/*
2418	* We need to load the entire state (including FS, GS etc.) as we could be continuing
2419	* to execute the nested-guest at any point (not just immediately after VMRUN) and thus
2420	* the VMCB can possibly be out-of-sync with the actual nested-guest state if it was
2421	* executed in IEM.
2422	*/
2423	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcbNstGst, pCtx);
2424	hmR0SvmLoadGuestMsrs(pVCpu, pVmcbNstGst, pCtx);
2425	hmR0SvmLoadGuestApicStateNested(pVCpu, pVmcbNstGst);
2426
2427	pVmcbNstGst->guest.u64RIP = pCtx->rip;
2428	pVmcbNstGst->guest.u64RSP = pCtx->rsp;
2429	pVmcbNstGst->guest.u64RFlags = pCtx->eflags.u32;
2430	pVmcbNstGst->guest.u64RAX = pCtx->rax;
2431
2432	#ifdef VBOX_WITH_NESTED_HWVIRT
2433	Assert(pVmcbNstGst->ctrl.IntCtrl.n.u1VGifEnable == 0); /* Nested VGIF not supported yet. */
2434	#endif
2435
2436	hmR0SvmLoadGuestXcptInterceptsNested(pVCpu, pVmcbNstGst, pCtx);
2437
2438	rc = hmR0SvmSetupVMRunHandler(pVCpu);
2439	AssertRCReturn(rc, rc);
2440
2441	/* Clear any unused and reserved bits. */
2442	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
2443	\| HM_CHANGED_GUEST_RSP
2444	\| HM_CHANGED_GUEST_RFLAGS
2445	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
2446	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
2447	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
2448	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
2449	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
2450	\| HM_CHANGED_SVM_RESERVED2
2451	\| HM_CHANGED_SVM_RESERVED3
2452	\| HM_CHANGED_SVM_RESERVED4);
2453
2454	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
2455	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
2456	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
2457	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2458
2459	#ifdef VBOX_STRICT
2460	hmR0SvmLogState(pVCpu, pVmcbNstGst, pCtx, "hmR0SvmLoadGuestStateNested", HMSVM_LOG_ALL, 0 /* uVerbose */);
2461	#endif
2462	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
2463	return rc;
2464	}
2465	#endif
2466
2467
2468	/**
2469	* Loads the state shared between the host and guest or nested-guest into the
2470	* VMCB.
2471	*
2472	* @param pVCpu The cross context virtual CPU structure.
2473	* @param pVmcb Pointer to the VM control block.
2474	* @param pCtx Pointer to the guest-CPU context.
2475	*
2476	* @remarks No-long-jump zone!!!
2477	*/
2478	static void hmR0SvmLoadSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
2479	{
2480	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2481	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2482
2483	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
2484	{
2485	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
2486	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
2487	}
2488
2489	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
2490	{
2491	/** @todo Figure out stepping with nested-guest. */
2492	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2493	hmR0SvmLoadSharedDebugState(pVCpu, pVmcb, pCtx);
2494	else
2495	{
2496	pVmcb->guest.u64DR6 = pCtx->dr[6];
2497	pVmcb->guest.u64DR7 = pCtx->dr[7];
2498	Log4(("hmR0SvmLoadSharedState: DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
2499	}
2500
2501	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
2502	}
2503
2504	/* Unused on AMD-V. */
2505	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
2506
2507	AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
2508	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
2509	}
2510
2511
2512	/**
2513	* Saves the guest (or nested-guest) state from the VMCB into the guest-CPU
2514	* context.
2515	*
2516	* Currently there is no residual state left in the CPU that is not updated in the
2517	* VMCB.
2518	*
2519	* @returns VBox status code.
2520	* @param pVCpu The cross context virtual CPU structure.
2521	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
2522	* out-of-sync. Make sure to update the required fields
2523	* before using them.
2524	* @param pVmcb Pointer to the VM control block.
2525	*/
2526	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PCSVMVMCB pVmcb)
2527	{
2528	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2529
2530	pMixedCtx->rip = pVmcb->guest.u64RIP;
2531	pMixedCtx->rsp = pVmcb->guest.u64RSP;
2532	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
2533	pMixedCtx->rax = pVmcb->guest.u64RAX;
2534
2535	#ifdef VBOX_WITH_NESTED_HWVIRT
2536	/*
2537	* Guest Virtual GIF (Global Interrupt Flag).
2538	*/
2539	if ( pVmcb->ctrl.IntCtrl.n.u1VGifEnable == 1
2540	&& !CPUMIsGuestInSvmNestedHwVirtMode(pMixedCtx))
2541	{
2542	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fVGif);
2543	pMixedCtx->hwvirt.fGif = pVmcb->ctrl.IntCtrl.n.u1VGif;
2544	}
2545	#endif
2546
2547	/*
2548	* Guest interrupt shadow.
2549	*/
2550	if (pVmcb->ctrl.IntShadow.n.u1IntShadow)
2551	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
2552	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2553	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2554
2555	/*
2556	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
2557	*/
2558	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
2559
2560	/*
2561	* Guest MSRs.
2562	*/
2563	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
2564	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
2565	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
2566	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
2567	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
2568	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
2569	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
2570	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
2571
2572	/*
2573	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
2574	*/
2575	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, CS, cs);
2576	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, SS, ss);
2577	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, DS, ds);
2578	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, ES, es);
2579	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, FS, fs);
2580	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, GS, gs);
2581
2582	/*
2583	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
2584	* register (yet).
2585	*/
2586	/** @todo SELM might need to be fixed as it too should not care about the
2587	* granularity bit. See @bugref{6785}. */
2588	if ( !pMixedCtx->cs.Attr.n.u1Granularity
2589	&& pMixedCtx->cs.Attr.n.u1Present
2590	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
2591	{
2592	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
2593	pMixedCtx->cs.Attr.n.u1Granularity = 1;
2594	}
2595
2596	HMSVM_ASSERT_SEG_GRANULARITY(cs);
2597	HMSVM_ASSERT_SEG_GRANULARITY(ss);
2598	HMSVM_ASSERT_SEG_GRANULARITY(ds);
2599	HMSVM_ASSERT_SEG_GRANULARITY(es);
2600	HMSVM_ASSERT_SEG_GRANULARITY(fs);
2601	HMSVM_ASSERT_SEG_GRANULARITY(gs);
2602
2603	/*
2604	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
2605	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
2606	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
2607	* See AMD spec. 15.5.1 "Basic operation".
2608	*/
2609	Assert(!(pVmcb->guest.u8CPL & ~0x3));
2610	uint8_t const uCpl = pVmcb->guest.u8CPL;
2611	if (pMixedCtx->ss.Attr.n.u2Dpl != uCpl)
2612	{
2613	Log4(("hmR0SvmSaveGuestState: CPL differs. SS.DPL=%u, CPL=%u, overwriting SS.DPL!\n", pMixedCtx->ss.Attr.n.u2Dpl, uCpl));
2614	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
2615	}
2616
2617	/*
2618	* Guest TR.
2619	* Fixup TR attributes so it's compatible with Intel. Important when saved-states are used
2620	* between Intel and AMD. See @bugref{6208#c39}.
2621	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2622	*/
2623	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, TR, tr);
2624	if (pMixedCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2625	{
2626	if ( pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2627	\|\| CPUMIsGuestInLongModeEx(pMixedCtx))
2628	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2629	else if (pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2630	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2631	}
2632
2633	/*
2634	* Guest Descriptor-Table registers (GDTR, IDTR, LDTR).
2635	*/
2636	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, LDTR, ldtr);
2637	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
2638	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
2639
2640	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
2641	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
2642
2643	/*
2644	* Guest Debug registers.
2645	*/
2646	if (!pVCpu->hm.s.fUsingHyperDR7)
2647	{
2648	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
2649	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
2650	}
2651	else
2652	{
2653	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
2654	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
2655	}
2656
2657	/*
2658	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
2659	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
2660	*/
2661	if ( pVmcb->ctrl.NestedPaging.n.u1NestedPaging
2662	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
2663	{
2664	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
2665	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
2666	}
2667
2668	#ifdef VBOX_STRICT
2669	if (CPUMIsGuestInSvmNestedHwVirtMode(pMixedCtx))
2670	hmR0SvmLogState(pVCpu, pVmcb, pMixedCtx, "hmR0SvmSaveGuestStateNested", HMSVM_LOG_ALL & ~HMSVM_LOG_LBR, 0 /* uVerbose */);
2671	#endif
2672	}
2673
2674
2675	/**
2676	* Does the necessary state syncing before returning to ring-3 for any reason
2677	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2678	*
2679	* @param pVCpu The cross context virtual CPU structure.
2680	*
2681	* @remarks No-long-jmp zone!!!
2682	*/
2683	static void hmR0SvmLeave(PVMCPU pVCpu)
2684	{
2685	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2686	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2687	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2688
2689	/*
2690	* !!! IMPORTANT !!!
2691	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2692	*/
2693
2694	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
2695	if (CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu))
2696	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0); /** @todo r=ramshankar: This shouldn't be necessary, it's set in HMR0EnterCpu. */
2697
2698	/*
2699	* Restore host debug registers if necessary and resync on next R0 reentry.
2700	*/
2701	#ifdef VBOX_STRICT
2702	if (CPUMIsHyperDebugStateActive(pVCpu))
2703	{
2704	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb; /** @todo nested-guest. */
2705	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2706	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2707	}
2708	#endif
2709	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
2710	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);/** @todo r=ramshankar: This shouldn't be necessary, it's set in HMR0EnterCpu. */
2711
2712	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2713	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2714
2715	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2716	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
2717	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
2718	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
2719	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2720
2721	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2722	}
2723
2724
2725	/**
2726	* Leaves the AMD-V session.
2727	*
2728	* @returns VBox status code.
2729	* @param pVCpu The cross context virtual CPU structure.
2730	*/
2731	static int hmR0SvmLeaveSession(PVMCPU pVCpu)
2732	{
2733	HM_DISABLE_PREEMPT();
2734	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2735	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2736
2737	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
2738	and done this from the SVMR0ThreadCtxCallback(). */
2739	if (!pVCpu->hm.s.fLeaveDone)
2740	{
2741	hmR0SvmLeave(pVCpu);
2742	pVCpu->hm.s.fLeaveDone = true;
2743	}
2744
2745	/*
2746	* !!! IMPORTANT !!!
2747	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2748	*/
2749
2750	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2751	/* Deregister hook now that we've left HM context before re-enabling preemption. */
2752	VMMR0ThreadCtxHookDisable(pVCpu);
2753
2754	/* Leave HM context. This takes care of local init (term). */
2755	int rc = HMR0LeaveCpu(pVCpu);
2756
2757	HM_RESTORE_PREEMPT();
2758	return rc;
2759	}
2760
2761
2762	/**
2763	* Does the necessary state syncing before doing a longjmp to ring-3.
2764	*
2765	* @returns VBox status code.
2766	* @param pVCpu The cross context virtual CPU structure.
2767	*
2768	* @remarks No-long-jmp zone!!!
2769	*/
2770	static int hmR0SvmLongJmpToRing3(PVMCPU pVCpu)
2771	{
2772	return hmR0SvmLeaveSession(pVCpu);
2773	}
2774
2775
2776	/**
2777	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2778	* any remaining host state) before we longjump to ring-3 and possibly get
2779	* preempted.
2780	*
2781	* @param pVCpu The cross context virtual CPU structure.
2782	* @param enmOperation The operation causing the ring-3 longjump.
2783	* @param pvUser The user argument (pointer to the possibly
2784	* out-of-date guest-CPU context).
2785	*/
2786	static DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
2787	{
2788	RT_NOREF_PV(pvUser);
2789
2790	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
2791	{
2792	/*
2793	* !!! IMPORTANT !!!
2794	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
2795	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
2796	*/
2797	VMMRZCallRing3RemoveNotification(pVCpu);
2798	VMMRZCallRing3Disable(pVCpu);
2799	HM_DISABLE_PREEMPT();
2800
2801	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2802	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2803
2804	/* Restore host debug registers if necessary and resync on next R0 reentry. */
2805	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2806
2807	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
2808	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2809	VMMR0ThreadCtxHookDisable(pVCpu);
2810
2811	/* Leave HM context. This takes care of local init (term). */
2812	HMR0LeaveCpu(pVCpu);
2813
2814	HM_RESTORE_PREEMPT();
2815	return VINF_SUCCESS;
2816	}
2817
2818	Assert(pVCpu);
2819	Assert(pvUser);
2820	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2821	HMSVM_ASSERT_PREEMPT_SAFE();
2822
2823	VMMRZCallRing3Disable(pVCpu);
2824	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2825
2826	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
2827	int rc = hmR0SvmLongJmpToRing3(pVCpu);
2828	AssertRCReturn(rc, rc);
2829
2830	VMMRZCallRing3Enable(pVCpu);
2831	return VINF_SUCCESS;
2832	}
2833
2834
2835	/**
2836	* Take necessary actions before going back to ring-3.
2837	*
2838	* An action requires us to go back to ring-3. This function does the necessary
2839	* steps before we can safely return to ring-3. This is not the same as longjmps
2840	* to ring-3, this is voluntary.
2841	*
2842	* @returns VBox status code.
2843	* @param pVM The cross context VM structure.
2844	* @param pVCpu The cross context virtual CPU structure.
2845	* @param pCtx Pointer to the guest-CPU context.
2846	* @param rcExit The reason for exiting to ring-3. Can be
2847	* VINF_VMM_UNKNOWN_RING3_CALL.
2848	*/
2849	static int hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2850	{
2851	Assert(pVM);
2852	Assert(pVCpu);
2853	Assert(pCtx);
2854	HMSVM_ASSERT_PREEMPT_SAFE();
2855
2856	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2857	VMMRZCallRing3Disable(pVCpu);
2858	Log4(("hmR0SvmExitToRing3: VCPU[%u]: rcExit=%d LocalFF=%#RX32 GlobalFF=%#RX32\n", pVCpu->idCpu, rcExit,
2859	pVCpu->fLocalForcedActions, pVM->fGlobalForcedActions));
2860
2861	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2862	if (pVCpu->hm.s.Event.fPending)
2863	{
2864	hmR0SvmPendingEventToTrpmTrap(pVCpu);
2865	Assert(!pVCpu->hm.s.Event.fPending);
2866	}
2867
2868	/* Sync. the necessary state for going back to ring-3. */
2869	hmR0SvmLeaveSession(pVCpu);
2870	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2871
2872	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2873	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2874	\| CPUM_CHANGED_LDTR
2875	\| CPUM_CHANGED_GDTR
2876	\| CPUM_CHANGED_IDTR
2877	\| CPUM_CHANGED_TR
2878	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2879	if ( pVM->hm.s.fNestedPaging
2880	&& CPUMIsGuestPagingEnabledEx(pCtx))
2881	{
2882	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
2883	}
2884
2885	/* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
2886	if (rcExit != VINF_EM_RAW_INTERRUPT)
2887	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2888
2889	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
2890
2891	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
2892	VMMRZCallRing3RemoveNotification(pVCpu);
2893	VMMRZCallRing3Enable(pVCpu);
2894
2895	/*
2896	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
2897	* and if we're injecting an event we should have a TRPM trap pending.
2898	*/
2899	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
2900	pVCpu->hm.s.u32HMError = rcExit,
2901	VERR_SVM_IPE_5);
2902	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
2903	pVCpu->hm.s.u32HMError = rcExit,
2904	VERR_SVM_IPE_4);
2905
2906	return rcExit;
2907	}
2908
2909
2910	#ifdef VBOX_WITH_NESTED_HWVIRT
2911	/**
2912	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2913	* intercepts for the nested-guest.
2914	*
2915	* @param pVM The cross context VM structure.
2916	* @param pVCpu The cross context virtual CPU structure.
2917	* @param pCtx Pointer to the nested guest-CPU context.
2918	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
2919	*
2920	* @remarks No-long-jump zone!!!
2921	*/
2922	static void hmR0SvmUpdateTscOffsettingNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcbNstGst)
2923	{
2924	Assert(CPUMIsGuestInSvmNestedHwVirtMode(pCtx));
2925
2926	bool fParavirtTsc;
2927	uint64_t uTscOffset;
2928	bool const fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &uTscOffset, &fParavirtTsc);
2929
2930	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2931	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2932	Assert(pCtx->hwvirt.svm.fHMCachedVmcb); RT_NOREF(pCtx);
2933
2934	/*
2935	* Only avoid intercepting if we determined the host TSC (++) is stable enough
2936	* to not intercept -and- the nested-hypervisor itself does not want to intercept it.
2937	*/
2938	if ( fCanUseRealTsc
2939	&& !(pVmcbNstGstCache->u64InterceptCtrl & (SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP)))
2940	{
2941	pVmcbNstGstCtrl->u64InterceptCtrl &= ~(SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
2942	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2943	}
2944	else
2945	{
2946	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP;
2947	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2948	}
2949
2950	/* Apply the nested-guest VMCB's TSC offset over the guest one. */
2951	uTscOffset = HMSvmNstGstApplyTscOffset(pVCpu, uTscOffset);
2952
2953	/* Update the nested-guest VMCB with the combined TSC offset (of guest and nested-guest). */
2954	pVmcbNstGstCtrl->u64TSCOffset = uTscOffset;
2955
2956	/* Finally update the VMCB clean bits since we touched the intercepts as well as the TSC offset. */
2957	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2958
2959	if (fParavirtTsc)
2960	{
2961	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
2962	information before every VM-entry, hence disable it for performance sake. */
2963	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
2964	}
2965	}
2966	#endif
2967
2968
2969	/**
2970	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2971	* intercepts.
2972	*
2973	* @param pVM The cross context VM structure.
2974	* @param pVCpu The cross context virtual CPU structure.
2975	* @param pVmcb Pointer to the VM control block.
2976	*
2977	* @remarks No-long-jump zone!!!
2978	*/
2979	static void hmR0SvmUpdateTscOffsetting(PVM pVM, PVMCPU pVCpu, PSVMVMCB pVmcb)
2980	{
2981	bool fParavirtTsc;
2982	bool fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &pVmcb->ctrl.u64TSCOffset, &fParavirtTsc);
2983	if (fCanUseRealTsc)
2984	{
2985	pVmcb->ctrl.u64InterceptCtrl &= ~(SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
2986	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2987	}
2988	else
2989	{
2990	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP;
2991	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2992	}
2993	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2994
2995	/** @todo later optimize this to be done elsewhere and not before every
2996	* VM-entry. */
2997	if (fParavirtTsc)
2998	{
2999	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
3000	information before every VM-entry, hence disable it for performance sake. */
3001	#if 0
3002	int rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
3003	AssertRC(rc);
3004	#endif
3005	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
3006	}
3007	}
3008
3009
3010	/**
3011	* Sets an event as a pending event to be injected into the guest.
3012	*
3013	* @param pVCpu The cross context virtual CPU structure.
3014	* @param pEvent Pointer to the SVM event.
3015	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
3016	* page-fault.
3017	*
3018	* @remarks Statistics counter assumes this is a guest event being reflected to
3019	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
3020	*/
3021	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
3022	{
3023	Assert(!pVCpu->hm.s.Event.fPending);
3024	Assert(pEvent->n.u1Valid);
3025
3026	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
3027	pVCpu->hm.s.Event.fPending = true;
3028	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
3029
3030	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
3031	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3032	}
3033
3034
3035	/**
3036	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
3037	*
3038	* @param pVCpu The cross context virtual CPU structure.
3039	*/
3040	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3041	{
3042	SVMEVENT Event;
3043	Event.u = 0;
3044	Event.n.u1Valid = 1;
3045	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3046	Event.n.u8Vector = X86_XCPT_UD;
3047	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3048	}
3049
3050
3051	/**
3052	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
3053	*
3054	* @param pVCpu The cross context virtual CPU structure.
3055	*/
3056	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3057	{
3058	SVMEVENT Event;
3059	Event.u = 0;
3060	Event.n.u1Valid = 1;
3061	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3062	Event.n.u8Vector = X86_XCPT_DB;
3063	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3064	}
3065
3066
3067	/**
3068	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
3069	*
3070	* @param pVCpu The cross context virtual CPU structure.
3071	* @param pCtx Pointer to the guest-CPU context.
3072	* @param u32ErrCode The error-code for the page-fault.
3073	* @param uFaultAddress The page fault address (CR2).
3074	*
3075	* @remarks This updates the guest CR2 with @a uFaultAddress!
3076	*/
3077	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3078	{
3079	SVMEVENT Event;
3080	Event.u = 0;
3081	Event.n.u1Valid = 1;
3082	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3083	Event.n.u8Vector = X86_XCPT_PF;
3084	Event.n.u1ErrorCodeValid = 1;
3085	Event.n.u32ErrorCode = u32ErrCode;
3086
3087	/* Update CR2 of the guest. */
3088	if (pCtx->cr2 != uFaultAddress)
3089	{
3090	pCtx->cr2 = uFaultAddress;
3091	/* The VMCB clean bit for CR2 will be updated while re-loading the guest state. */
3092	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR2);
3093	}
3094
3095	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3096	}
3097
3098
3099	/**
3100	* Sets a device-not-available (\#NM) exception as pending-for-injection into
3101	* the VM.
3102	*
3103	* @param pVCpu The cross context virtual CPU structure.
3104	*/
3105	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
3106	{
3107	SVMEVENT Event;
3108	Event.u = 0;
3109	Event.n.u1Valid = 1;
3110	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3111	Event.n.u8Vector = X86_XCPT_NM;
3112	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3113	}
3114
3115
3116	/**
3117	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
3118	*
3119	* @param pVCpu The cross context virtual CPU structure.
3120	*/
3121	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3122	{
3123	SVMEVENT Event;
3124	Event.u = 0;
3125	Event.n.u1Valid = 1;
3126	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3127	Event.n.u8Vector = X86_XCPT_MF;
3128	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3129	}
3130
3131
3132	/**
3133	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
3134	*
3135	* @param pVCpu The cross context virtual CPU structure.
3136	*/
3137	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3138	{
3139	SVMEVENT Event;
3140	Event.u = 0;
3141	Event.n.u1Valid = 1;
3142	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3143	Event.n.u8Vector = X86_XCPT_DF;
3144	Event.n.u1ErrorCodeValid = 1;
3145	Event.n.u32ErrorCode = 0;
3146	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3147	}
3148
3149
3150	/**
3151	* Injects an event into the guest upon VMRUN by updating the relevant field
3152	* in the VMCB.
3153	*
3154	* @param pVCpu The cross context virtual CPU structure.
3155	* @param pVmcb Pointer to the guest VM control block.
3156	* @param pCtx Pointer to the guest-CPU context.
3157	* @param pEvent Pointer to the event.
3158	*
3159	* @remarks No-long-jump zone!!!
3160	* @remarks Requires CR0!
3161	*/
3162	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
3163	{
3164	NOREF(pVCpu); NOREF(pCtx);
3165
3166	Assert(!pVmcb->ctrl.EventInject.n.u1Valid);
3167	pVmcb->ctrl.EventInject.u = pEvent->u;
3168	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
3169
3170	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
3171	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3172	}
3173
3174
3175
3176	/**
3177	* Converts any TRPM trap into a pending HM event. This is typically used when
3178	* entering from ring-3 (not longjmp returns).
3179	*
3180	* @param pVCpu The cross context virtual CPU structure.
3181	*/
3182	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
3183	{
3184	Assert(TRPMHasTrap(pVCpu));
3185	Assert(!pVCpu->hm.s.Event.fPending);
3186
3187	uint8_t uVector;
3188	TRPMEVENT enmTrpmEvent;
3189	RTGCUINT uErrCode;
3190	RTGCUINTPTR GCPtrFaultAddress;
3191	uint8_t cbInstr;
3192
3193	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
3194	AssertRC(rc);
3195
3196	SVMEVENT Event;
3197	Event.u = 0;
3198	Event.n.u1Valid = 1;
3199	Event.n.u8Vector = uVector;
3200
3201	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
3202	if (enmTrpmEvent == TRPM_TRAP)
3203	{
3204	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3205	switch (uVector)
3206	{
3207	case X86_XCPT_NMI:
3208	{
3209	Event.n.u3Type = SVM_EVENT_NMI;
3210	break;
3211	}
3212
3213	case X86_XCPT_PF:
3214	case X86_XCPT_DF:
3215	case X86_XCPT_TS:
3216	case X86_XCPT_NP:
3217	case X86_XCPT_SS:
3218	case X86_XCPT_GP:
3219	case X86_XCPT_AC:
3220	{
3221	Event.n.u1ErrorCodeValid = 1;
3222	Event.n.u32ErrorCode = uErrCode;
3223	break;
3224	}
3225	}
3226	}
3227	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
3228	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3229	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
3230	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
3231	else
3232	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
3233
3234	rc = TRPMResetTrap(pVCpu);
3235	AssertRC(rc);
3236
3237	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
3238	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
3239
3240	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
3241	}
3242
3243
3244	/**
3245	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
3246	* AMD-V to execute any instruction.
3247	*
3248	* @param pVCpu The cross context virtual CPU structure.
3249	*/
3250	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
3251	{
3252	Assert(pVCpu->hm.s.Event.fPending);
3253	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
3254
3255	SVMEVENT Event;
3256	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3257
3258	uint8_t uVector = Event.n.u8Vector;
3259	uint8_t uVectorType = Event.n.u3Type;
3260	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event);
3261
3262	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
3263
3264	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
3265	AssertRC(rc);
3266
3267	if (Event.n.u1ErrorCodeValid)
3268	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
3269
3270	if ( uVectorType == SVM_EVENT_EXCEPTION
3271	&& uVector == X86_XCPT_PF)
3272	{
3273	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
3274	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
3275	}
3276	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
3277	{
3278	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
3279	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
3280	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
3281	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
3282	}
3283	pVCpu->hm.s.Event.fPending = false;
3284	}
3285
3286
3287	/**
3288	* Checks if the guest (or nested-guest) has an interrupt shadow active right
3289	* now.
3290	*
3291	* @returns @c true if the interrupt shadow is active, @c false otherwise.
3292	* @param pVCpu The cross context virtual CPU structure.
3293	* @param pCtx Pointer to the guest-CPU context.
3294	*
3295	* @remarks No-long-jump zone!!!
3296	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
3297	*/
3298	DECLINLINE(bool) hmR0SvmIsIntrShadowActive(PVMCPU pVCpu, PCPUMCTX pCtx)
3299	{
3300	/*
3301	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
3302	* inhibit interrupts or clear any existing interrupt-inhibition.
3303	*/
3304	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3305	{
3306	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
3307	{
3308	/*
3309	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
3310	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
3311	*/
3312	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3313	return false;
3314	}
3315	return true;
3316	}
3317	return false;
3318	}
3319
3320
3321	/**
3322	* Sets the virtual interrupt intercept control in the VMCB.
3323	*
3324	* @param pVmcb Pointer to the VM control block.
3325	*/
3326	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
3327	{
3328	/*
3329	* When AVIC isn't supported, indicate that a virtual interrupt is pending and to
3330	* cause a #VMEXIT when the guest is ready to accept interrupts. At #VMEXIT, we
3331	* then get the interrupt from the APIC (updating ISR at the right time) and
3332	* inject the interrupt.
3333	*
3334	* With AVIC is supported, we could make use of the asynchronously delivery without
3335	* #VMEXIT and we would be passing the AVIC page to SVM.
3336	*/
3337	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
3338	{
3339	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqPending == 0);
3340	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1;
3341	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VINTR;
3342	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
3343	Log4(("Set VINTR intercept\n"));
3344	}
3345	}
3346
3347
3348	/**
3349	* Clears the virtual interrupt intercept control in the VMCB as
3350	* we are figured the guest is unable process any interrupts
3351	* at this point of time.
3352	*
3353	* @param pVmcb Pointer to the VM control block.
3354	*/
3355	DECLINLINE(void) hmR0SvmClearVirtIntrIntercept(PSVMVMCB pVmcb)
3356	{
3357	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
3358	{
3359	Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqPending == 1);
3360	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 0;
3361	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
3362	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
3363	Log4(("Cleared VINTR intercept\n"));
3364	}
3365	}
3366
3367
3368	/**
3369	* Sets the IRET intercept control in the VMCB which instructs AMD-V to cause a
3370	* \#VMEXIT as soon as a guest starts executing an IRET. This is used to unblock
3371	* virtual NMIs.
3372	*
3373	* @param pVmcb Pointer to the VM control block.
3374	*/
3375	DECLINLINE(void) hmR0SvmSetIretIntercept(PSVMVMCB pVmcb)
3376	{
3377	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET))
3378	{
3379	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_IRET;
3380	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3381
3382	Log4(("Setting IRET intercept\n"));
3383	}
3384	}
3385
3386
3387	/**
3388	* Clears the IRET intercept control in the VMCB.
3389	*
3390	* @param pVmcb Pointer to the VM control block.
3391	*/
3392	DECLINLINE(void) hmR0SvmClearIretIntercept(PSVMVMCB pVmcb)
3393	{
3394	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET)
3395	{
3396	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_IRET;
3397	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
3398
3399	Log4(("Clearing IRET intercept\n"));
3400	}
3401	}
3402
3403	#ifdef VBOX_WITH_NESTED_HWVIRT
3404
3405
3406	/**
3407	* Evaluates the event to be delivered to the nested-guest and sets it as the
3408	* pending event.
3409	*
3410	* @returns VBox strict status code.
3411	* @param pVCpu The cross context virtual CPU structure.
3412	* @param pCtx Pointer to the guest-CPU context.
3413	*/
3414	static VBOXSTRICTRC hmR0SvmEvaluatePendingEventNested(PVMCPU pVCpu, PCPUMCTX pCtx)
3415	{
3416	Log4Func(("\n"));
3417
3418	Assert(!pVCpu->hm.s.Event.fPending);
3419
3420	bool const fGif = pCtx->hwvirt.fGif;
3421	if (fGif)
3422	{
3423	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
3424
3425	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3426
3427	/*
3428	* Check if the nested-guest can receive NMIs.
3429	* NMIs are higher priority than regular interrupts.
3430	*/
3431	/** @todo SMI. SMIs take priority over NMIs. */
3432	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI))
3433	{
3434	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3435	if (fBlockNmi)
3436	hmR0SvmSetIretIntercept(pVmcbNstGst);
3437	else if (fIntShadow)
3438	{
3439	/** @todo Figure this out, how we shall manage virt. intercept if the
3440	* nested-guest already has one set and/or if we really need it? */
3441	//hmR0SvmSetVirtIntrIntercept(pVmcbNstGst);
3442	}
3443	else
3444	{
3445	Log4(("Pending NMI\n"));
3446
3447	SVMEVENT Event;
3448	Event.u = 0;
3449	Event.n.u1Valid = 1;
3450	Event.n.u8Vector = X86_XCPT_NMI;
3451	Event.n.u3Type = SVM_EVENT_NMI;
3452
3453	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3454	hmR0SvmSetIretIntercept(pVmcbNstGst);
3455	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3456	return VINF_SUCCESS;
3457	}
3458	}
3459
3460	/*
3461	* Check if the nested-guest can receive external interrupts (generated by
3462	* the guest's PIC/APIC).
3463	*
3464	* External intercepts, NMI, SMI etc. from the physical CPU are -always- intercepted
3465	* when executing using hardware-assisted SVM, see HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS.
3466	*
3467	* External interrupts that are generated for the outer guest may be intercepted
3468	* depending on how the nested-guest VMCB was programmed by guest software.
3469	*
3470	* Physical interrupts always take priority over virtual interrupts,
3471	* see AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
3472	*/
3473	if (!fIntShadow)
3474	{
3475	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3476	&& !pVCpu->hm.s.fSingleInstruction
3477	&& CPUMCanSvmNstGstTakePhysIntr(pVCpu, pCtx))
3478	{
3479	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INTR))
3480	{
3481	Log4(("Intercepting external interrupt -> #VMEXIT\n"));
3482	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
3483	}
3484
3485	uint8_t u8Interrupt;
3486	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3487	if (RT_SUCCESS(rc))
3488	{
3489	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
3490
3491	SVMEVENT Event;
3492	Event.u = 0;
3493	Event.n.u1Valid = 1;
3494	Event.n.u8Vector = u8Interrupt;
3495	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3496
3497	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3498	}
3499	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3500	{
3501	/*
3502	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3503	* updated eventually when the TPR is written by the guest.
3504	*/
3505	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3506	}
3507	else
3508	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3509	}
3510
3511	/*
3512	* Check if the nested-guest is intercepting virtual (using V_IRQ and related fields)
3513	* interrupt injection. The virtual interrupt injection itself, if any, will be done
3514	* by the physical CPU.
3515	*/
3516	/** @todo later explore this for performance reasons. Right now the hardware
3517	* takes care of virtual interrupt injection for nested-guest. */
3518	#if 0
3519	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST)
3520	&& (pVmcbNstGstCache->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
3521	&& CPUMCanSvmNstGstTakeVirtIntr(pVCpu, pCtx))
3522	{
3523	Log4(("Intercepting virtual interrupt -> #VMEXIT\n"));
3524	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_VINTR, 0, 0);
3525	}
3526	#endif
3527	}
3528	}
3529
3530	return VINF_SUCCESS;
3531	}
3532	#endif
3533
3534
3535	/**
3536	* Evaluates the event to be delivered to the guest and sets it as the pending
3537	* event.
3538	*
3539	* @param pVCpu The cross context virtual CPU structure.
3540	* @param pCtx Pointer to the guest-CPU context.
3541	*
3542	* @remarks Don't use this function when we are actively executing a
3543	* nested-guest, use hmR0SvmEvaluatePendingEventNested instead.
3544	*/
3545	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
3546	{
3547	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
3548	Assert(!pVCpu->hm.s.Event.fPending);
3549
3550	#ifdef VBOX_WITH_NESTED_HWVIRT
3551	bool const fGif = pCtx->hwvirt.fGif;
3552	#else
3553	bool const fGif = true;
3554	#endif
3555	Log4Func(("fGif=%RTbool\n", fGif));
3556
3557	/*
3558	* If the global interrupt flag (GIF) isn't set, even NMIs and other events are blocked.
3559	* See AMD spec. Table 15-10. "Effect of the GIF on Interrupt Handling".
3560	*/
3561	if (fGif)
3562	{
3563	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3564	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
3565	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3566	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3567
3568	Log4Func(("fBlockInt=%RTbool fIntShadow=%RTbool APIC/PIC_Pending=%RTbool\n", fBlockInt, fIntShadow,
3569	VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)));
3570
3571	/** @todo SMI. SMIs take priority over NMIs. */
3572	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts. */
3573	{
3574	if (fBlockNmi)
3575	hmR0SvmSetIretIntercept(pVmcb);
3576	else if (fIntShadow)
3577	hmR0SvmSetVirtIntrIntercept(pVmcb);
3578	else
3579	{
3580	Log4(("Pending NMI\n"));
3581
3582	SVMEVENT Event;
3583	Event.u = 0;
3584	Event.n.u1Valid = 1;
3585	Event.n.u8Vector = X86_XCPT_NMI;
3586	Event.n.u3Type = SVM_EVENT_NMI;
3587
3588	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3589	hmR0SvmSetIretIntercept(pVmcb);
3590	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3591	return;
3592	}
3593	}
3594	else if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3595	&& !pVCpu->hm.s.fSingleInstruction)
3596	{
3597	/*
3598	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt() returns
3599	* a valid interrupt we -must- deliver the interrupt. We can no longer re-request it from the APIC.
3600	*/
3601	if ( !fBlockInt
3602	&& !fIntShadow)
3603	{
3604	uint8_t u8Interrupt;
3605	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3606	if (RT_SUCCESS(rc))
3607	{
3608	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
3609
3610	SVMEVENT Event;
3611	Event.u = 0;
3612	Event.n.u1Valid = 1;
3613	Event.n.u8Vector = u8Interrupt;
3614	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3615
3616	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3617	}
3618	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3619	{
3620	/*
3621	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3622	* updated eventually when the TPR is written by the guest.
3623	*/
3624	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3625	}
3626	else
3627	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3628	}
3629	else
3630	hmR0SvmSetVirtIntrIntercept(pVmcb);
3631	}
3632	}
3633	}
3634
3635
3636	/**
3637	* Injects any pending events into the guest or nested-guest.
3638	*
3639	* @param pVCpu The cross context virtual CPU structure.
3640	* @param pCtx Pointer to the guest-CPU context.
3641	* @param pVmcb Pointer to the VM control block.
3642	*/
3643	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMVMCB pVmcb)
3644	{
3645	Assert(!TRPMHasTrap(pVCpu));
3646	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3647
3648	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu, pCtx);
3649	#ifdef VBOX_STRICT
3650	bool const fGif = pCtx->hwvirt.fGif;
3651	bool fAllowInt = fGif;
3652	if (fGif)
3653	{
3654	/*
3655	* For nested-guests we have no way to determine if we're injecting a physical or virtual
3656	* interrupt at this point. Hence the partial verification below.
3657	*/
3658	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3659	fAllowInt = CPUMCanSvmNstGstTakePhysIntr(pVCpu, pCtx) \|\| CPUMCanSvmNstGstTakeVirtIntr(pVCpu, pCtx);
3660	else
3661	fAllowInt = RT_BOOL(pCtx->eflags.u32 & X86_EFL_IF);
3662	}
3663	#endif
3664
3665	if (pVCpu->hm.s.Event.fPending)
3666	{
3667	SVMEVENT Event;
3668	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3669	Assert(Event.n.u1Valid);
3670
3671	/*
3672	* Validate event injection pre-conditions.
3673	*/
3674	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3675	{
3676	Assert(fAllowInt);
3677	Assert(!fIntShadow);
3678	}
3679	else if (Event.n.u3Type == SVM_EVENT_NMI)
3680	{
3681	Assert(fGif);
3682	Assert(!fIntShadow);
3683	}
3684
3685	/*
3686	* Inject it (update VMCB for injection by the hardware).
3687	*/
3688	Log4(("Injecting pending HM event\n"));
3689	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
3690	pVCpu->hm.s.Event.fPending = false;
3691
3692	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3693	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
3694	else
3695	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
3696	}
3697	else
3698	Assert(pVmcb->ctrl.EventInject.n.u1Valid == 0);
3699
3700	/*
3701	* Update the guest interrupt shadow in the guest or nested-guest VMCB.
3702	*
3703	* For nested-guests: We need to update it too for the scenario where IEM executes
3704	* the nested-guest but execution later continues here with an interrupt shadow active.
3705	*/
3706	pVmcb->ctrl.IntShadow.n.u1IntShadow = fIntShadow;
3707	}
3708
3709
3710	/**
3711	* Reports world-switch error and dumps some useful debug info.
3712	*
3713	* @param pVM The cross context VM structure.
3714	* @param pVCpu The cross context virtual CPU structure.
3715	* @param rcVMRun The return code from VMRUN (or
3716	* VERR_SVM_INVALID_GUEST_STATE for invalid
3717	* guest-state).
3718	* @param pCtx Pointer to the guest-CPU context.
3719	*/
3720	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
3721	{
3722	NOREF(pCtx);
3723	HMSVM_ASSERT_PREEMPT_SAFE();
3724	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
3725	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
3726
3727	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
3728	{
3729	hmR0DumpRegs(pVM, pVCpu, pCtx); NOREF(pVM);
3730	#ifdef VBOX_STRICT
3731	Log4(("ctrl.u32VmcbCleanBits %#RX32\n", pVmcb->ctrl.u32VmcbCleanBits));
3732	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
3733	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
3734	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
3735	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
3736	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
3737	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
3738	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
3739	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
3740	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
3741
3742	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
3743	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
3744	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
3745
3746	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
3747	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
3748	Log4(("ctrl.IntCtrl.u1VGif %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGif));
3749	Log4(("ctrl.IntCtrl.u6Reserved0 %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved0));
3750	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
3751	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
3752	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
3753	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
3754	Log4(("ctrl.IntCtrl.u1VGifEnable %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGifEnable));
3755	Log4(("ctrl.IntCtrl.u5Reserved1 %#x\n", pVmcb->ctrl.IntCtrl.n.u5Reserved1));
3756	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
3757	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
3758
3759	Log4(("ctrl.IntShadow.u1IntShadow %#x\n", pVmcb->ctrl.IntShadow.n.u1IntShadow));
3760	Log4(("ctrl.IntShadow.u1GuestIntMask %#x\n", pVmcb->ctrl.IntShadow.n.u1GuestIntMask));
3761	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
3762	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
3763	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
3764	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
3765	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
3766	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
3767	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
3768	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
3769	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
3770	Log4(("ctrl.NestedPaging.u1NestedPaging %#x\n", pVmcb->ctrl.NestedPaging.n.u1NestedPaging));
3771	Log4(("ctrl.NestedPaging.u1Sev %#x\n", pVmcb->ctrl.NestedPaging.n.u1Sev));
3772	Log4(("ctrl.NestedPaging.u1SevEs %#x\n", pVmcb->ctrl.NestedPaging.n.u1SevEs));
3773	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
3774	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
3775	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
3776	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
3777	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
3778	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
3779
3780	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
3781
3782	Log4(("ctrl.LbrVirt.u1LbrVirt %#x\n", pVmcb->ctrl.LbrVirt.n.u1LbrVirt));
3783	Log4(("ctrl.LbrVirt.u1VirtVmsaveVmload %#x\n", pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload));
3784
3785	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
3786	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
3787	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
3788	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
3789	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
3790	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
3791	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
3792	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
3793	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
3794	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
3795	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
3796	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
3797	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
3798	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
3799	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
3800	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
3801	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
3802	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
3803	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
3804	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
3805
3806	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
3807	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
3808
3809	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
3810	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
3811	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
3812	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
3813
3814	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
3815	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
3816
3817	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
3818	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
3819	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
3820	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
3821
3822	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
3823	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
3824	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
3825	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
3826	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
3827	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
3828	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
3829
3830	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
3831	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
3832	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
3833	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
3834
3835	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
3836	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
3837	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
3838
3839	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
3840	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
3841	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
3842	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
3843	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
3844	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
3845	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
3846	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
3847	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
3848	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
3849	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
3850	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
3851	#endif /* VBOX_STRICT */
3852	}
3853	else
3854	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
3855
3856	NOREF(pVmcb);
3857	}
3858
3859
3860	/**
3861	* Check per-VM and per-VCPU force flag actions that require us to go back to
3862	* ring-3 for one reason or another.
3863	*
3864	* @returns VBox status code (information status code included).
3865	* @retval VINF_SUCCESS if we don't have any actions that require going back to
3866	* ring-3.
3867	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
3868	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
3869	* interrupts)
3870	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
3871	* all EMTs to be in ring-3.
3872	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
3873	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
3874	* to the EM loop.
3875	*
3876	* @param pVM The cross context VM structure.
3877	* @param pVCpu The cross context virtual CPU structure.
3878	* @param pCtx Pointer to the guest-CPU context.
3879	*/
3880	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3881	{
3882	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3883
3884	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
3885	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
3886	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
3887
3888	/* Update pending interrupts into the APIC's IRR. */
3889	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
3890	APICUpdatePendingInterrupts(pVCpu);
3891
3892	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
3893	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
3894	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
3895	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
3896	{
3897	/* Pending PGM C3 sync. */
3898	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
3899	{
3900	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3901	if (rc != VINF_SUCCESS)
3902	{
3903	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
3904	return rc;
3905	}
3906	}
3907
3908	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
3909	/* -XXX- what was that about single stepping? */
3910	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
3911	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3912	{
3913	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3914	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
3915	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
3916	return rc;
3917	}
3918
3919	/* Pending VM request packets, such as hardware interrupts. */
3920	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
3921	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
3922	{
3923	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
3924	return VINF_EM_PENDING_REQUEST;
3925	}
3926
3927	/* Pending PGM pool flushes. */
3928	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
3929	{
3930	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
3931	return VINF_PGM_POOL_FLUSH_PENDING;
3932	}
3933
3934	/* Pending DMA requests. */
3935	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
3936	{
3937	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
3938	return VINF_EM_RAW_TO_R3;
3939	}
3940	}
3941
3942	return VINF_SUCCESS;
3943	}
3944
3945
3946	#ifdef VBOX_WITH_NESTED_HWVIRT
3947	/**
3948	* Does the preparations before executing nested-guest code in AMD-V.
3949	*
3950	* @returns VBox status code (informational status codes included).
3951	* @retval VINF_SUCCESS if we can proceed with running the guest.
3952	* @retval VINF_* scheduling changes, we have to go back to ring-3.
3953	*
3954	* @param pVM The cross context VM structure.
3955	* @param pVCpu The cross context virtual CPU structure.
3956	* @param pCtx Pointer to the guest-CPU context.
3957	* @param pSvmTransient Pointer to the SVM transient structure.
3958	*
3959	* @remarks Same caveats regarding longjumps as hmR0SvmPreRunGuest applies.
3960	* @sa hmR0SvmPreRunGuest.
3961	*/
3962	static int hmR0SvmPreRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3963	{
3964	HMSVM_ASSERT_PREEMPT_SAFE();
3965
3966	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3967	{
3968	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
3969	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
3970	return VINF_EM_RESCHEDULE_REM;
3971	#endif
3972	}
3973	else
3974	return VINF_SVM_VMEXIT;
3975
3976	/* Check force flag actions that might require us to go back to ring-3. */
3977	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
3978	if (rc != VINF_SUCCESS)
3979	return rc;
3980
3981	if (TRPMHasTrap(pVCpu))
3982	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
3983	else if (!pVCpu->hm.s.Event.fPending)
3984	{
3985	VBOXSTRICTRC rcStrict = hmR0SvmEvaluatePendingEventNested(pVCpu, pCtx);
3986	if (rcStrict != VINF_SUCCESS)
3987	return VBOXSTRICTRC_VAL(rcStrict);
3988	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3989	return VINF_SVM_VMEXIT;
3990	}
3991
3992	/*
3993	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
3994	* Just do it in software, see @bugref{8411}.
3995	* NB: If we could continue a task switch exit we wouldn't need to do this.
3996	*/
3997	if (RT_UNLIKELY( !pVM->hm.s.svm.u32Features
3998	&& pVCpu->hm.s.Event.fPending
3999	&& SVM_EVENT_GET_TYPE(pVCpu->hm.s.Event.u64IntInfo) == SVM_EVENT_NMI))
4000	{
4001	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4002	}
4003
4004	#ifdef HMSVM_SYNC_FULL_NESTED_GUEST_STATE
4005	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
4006	#endif
4007
4008	/*
4009	* Load the nested-guest state.
4010	*/
4011	rc = hmR0SvmLoadGuestStateNested(pVCpu, pCtx);
4012	AssertRCReturn(rc, rc);
4013	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull); /** @todo Get new STAM counter for this? */
4014
4015	/* Ensure we've cached (and hopefully modified) the VMCB for execution using hardware SVM. */
4016	Assert(pCtx->hwvirt.svm.fHMCachedVmcb);
4017
4018	/*
4019	* No longjmps to ring-3 from this point on!!!
4020	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4021	* This also disables flushing of the R0-logger instance (if any).
4022	*/
4023	VMMRZCallRing3Disable(pVCpu);
4024
4025	/*
4026	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
4027	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
4028	*
4029	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
4030	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
4031	*
4032	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
4033	* executing guest code.
4034	*/
4035	pSvmTransient->fEFlags = ASMIntDisableFlags();
4036	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4037	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4038	{
4039	ASMSetFlags(pSvmTransient->fEFlags);
4040	VMMRZCallRing3Enable(pVCpu);
4041	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4042	return VINF_EM_RAW_TO_R3;
4043	}
4044	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4045	{
4046	ASMSetFlags(pSvmTransient->fEFlags);
4047	VMMRZCallRing3Enable(pVCpu);
4048	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
4049	return VINF_EM_RAW_INTERRUPT;
4050	}
4051
4052	/*
4053	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
4054	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
4055	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
4056	*
4057	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
4058	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
4059	*/
4060	if (pVCpu->hm.s.Event.fPending)
4061	{
4062	SVMEVENT Event;
4063	Event.u = pVCpu->hm.s.Event.u64IntInfo;
4064	if ( Event.n.u1Valid
4065	&& Event.n.u3Type == SVM_EVENT_NMI
4066	&& Event.n.u8Vector == X86_XCPT_NMI
4067	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
4068	{
4069	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
4070	}
4071	}
4072
4073	return VINF_SUCCESS;
4074	}
4075	#endif
4076
4077
4078	/**
4079	* Does the preparations before executing guest code in AMD-V.
4080	*
4081	* This may cause longjmps to ring-3 and may even result in rescheduling to the
4082	* recompiler. We must be cautious what we do here regarding committing
4083	* guest-state information into the VMCB assuming we assuredly execute the guest
4084	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
4085	* clearing the common-state (TRPM/forceflags), we must undo those changes so
4086	* that the recompiler can (and should) use them when it resumes guest
4087	* execution. Otherwise such operations must be done when we can no longer
4088	* exit to ring-3.
4089	*
4090	* @returns VBox status code (informational status codes included).
4091	* @retval VINF_SUCCESS if we can proceed with running the guest.
4092	* @retval VINF_* scheduling changes, we have to go back to ring-3.
4093	*
4094	* @param pVM The cross context VM structure.
4095	* @param pVCpu The cross context virtual CPU structure.
4096	* @param pCtx Pointer to the guest-CPU context.
4097	* @param pSvmTransient Pointer to the SVM transient structure.
4098	*/
4099	static int hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4100	{
4101	HMSVM_ASSERT_PREEMPT_SAFE();
4102	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
4103
4104	/* Check force flag actions that might require us to go back to ring-3. */
4105	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
4106	if (rc != VINF_SUCCESS)
4107	return rc;
4108
4109	if (TRPMHasTrap(pVCpu))
4110	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4111	else if (!pVCpu->hm.s.Event.fPending)
4112	hmR0SvmEvaluatePendingEvent(pVCpu, pCtx);
4113
4114	/*
4115	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4116	* Just do it in software, see @bugref{8411}.
4117	* NB: If we could continue a task switch exit we wouldn't need to do this.
4118	*/
4119	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending && (((pVCpu->hm.s.Event.u64IntInfo >> 8) & 7) == SVM_EVENT_NMI)))
4120	if (RT_UNLIKELY(!pVM->hm.s.svm.u32Features))
4121	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4122
4123	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4124	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
4125	#endif
4126
4127	/* Load the guest bits that are not shared with the host in any way since we can longjmp or get preempted. */
4128	rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
4129	AssertRCReturn(rc, rc);
4130	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
4131
4132	/*
4133	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
4134	* so we can update it on the way back if the guest changed the TPR.
4135	*/
4136	if (pVCpu->hm.s.svm.fSyncVTpr)
4137	{
4138	if (pVM->hm.s.fTPRPatchingActive)
4139	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
4140	else
4141	{
4142	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4143	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
4144	}
4145	}
4146
4147	/*
4148	* No longjmps to ring-3 from this point on!!!
4149	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4150	* This also disables flushing of the R0-logger instance (if any).
4151	*/
4152	VMMRZCallRing3Disable(pVCpu);
4153
4154	/*
4155	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
4156	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
4157	*
4158	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
4159	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
4160	*
4161	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
4162	* executing guest code.
4163	*/
4164	pSvmTransient->fEFlags = ASMIntDisableFlags();
4165	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4166	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4167	{
4168	ASMSetFlags(pSvmTransient->fEFlags);
4169	VMMRZCallRing3Enable(pVCpu);
4170	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4171	return VINF_EM_RAW_TO_R3;
4172	}
4173	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4174	{
4175	ASMSetFlags(pSvmTransient->fEFlags);
4176	VMMRZCallRing3Enable(pVCpu);
4177	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
4178	return VINF_EM_RAW_INTERRUPT;
4179	}
4180
4181	/*
4182	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
4183	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
4184	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
4185	*
4186	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
4187	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
4188	*/
4189	if (pVCpu->hm.s.Event.fPending)
4190	{
4191	SVMEVENT Event;
4192	Event.u = pVCpu->hm.s.Event.u64IntInfo;
4193	if ( Event.n.u1Valid
4194	&& Event.n.u3Type == SVM_EVENT_NMI
4195	&& Event.n.u8Vector == X86_XCPT_NMI
4196	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
4197	{
4198	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
4199	}
4200	}
4201
4202	return VINF_SUCCESS;
4203	}
4204
4205
4206	#ifdef VBOX_WITH_NESTED_HWVIRT
4207	/**
4208	* Prepares to run nested-guest code in AMD-V and we've committed to doing so. This
4209	* means there is no backing out to ring-3 or anywhere else at this point.
4210	*
4211	* @param pVM The cross context VM structure.
4212	* @param pVCpu The cross context virtual CPU structure.
4213	* @param pCtx Pointer to the guest-CPU context.
4214	* @param pSvmTransient Pointer to the SVM transient structure.
4215	*
4216	* @remarks Called with preemption disabled.
4217	* @remarks No-long-jump zone!!!
4218	*/
4219	static void hmR0SvmPreRunGuestCommittedNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4220	{
4221	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4222	Assert(VMMR0IsLogFlushDisabled(pVCpu));
4223	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4224	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4225
4226	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4227	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4228
4229	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4230	hmR0SvmInjectPendingEvent(pVCpu, pCtx, pVmcbNstGst);
4231
4232	if ( pVCpu->hm.s.fPreloadGuestFpu
4233	&& !CPUMIsGuestFPUStateActive(pVCpu))
4234	{
4235	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4236	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
4237	}
4238
4239	/* Load the state shared between host and nested-guest (FPU, debug). */
4240	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
4241	hmR0SvmLoadSharedState(pVCpu, pVmcbNstGst, pCtx);
4242
4243	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
4244	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
4245
4246	/* Setup TSC offsetting. */
4247	RTCPUID idCurrentCpu = hmR0GetCurrentCpu()->idCpu;
4248	if ( pSvmTransient->fUpdateTscOffsetting
4249	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
4250	{
4251	hmR0SvmUpdateTscOffsettingNested(pVM, pVCpu, pCtx, pVmcbNstGst);
4252	pSvmTransient->fUpdateTscOffsetting = false;
4253	}
4254
4255	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4256	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
4257	pVmcbNstGst->ctrl.u32VmcbCleanBits = 0;
4258
4259	/* Store status of the shared guest-host state at the time of VMRUN. */
4260	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4261	if (CPUMIsGuestInLongModeEx(pCtx))
4262	{
4263	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
4264	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
4265	}
4266	else
4267	#endif
4268	{
4269	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4270	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4271	}
4272	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
4273
4274	/* The TLB flushing would've already been setup by the nested-hypervisor. */
4275	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4276	hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcbNstGst);
4277	Assert(hmR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
4278
4279	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4280
4281	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
4282	to start executing. */
4283
4284	/*
4285	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
4286	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
4287	*
4288	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4289	*/
4290	uint8_t pbMsrBitmap = (uint8_t )pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
4291	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
4292	&& !(pVmcbNstGst->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4293	{
4294	hmR0SvmSetMsrPermission(pVmcbNstGst, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4295	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4296	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
4297	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
4298	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
4299	pSvmTransient->fRestoreTscAuxMsr = true;
4300	}
4301	else
4302	{
4303	hmR0SvmSetMsrPermission(pVmcbNstGst, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4304	pSvmTransient->fRestoreTscAuxMsr = false;
4305	}
4306
4307	/*
4308	* If VMCB Clean bits isn't supported by the CPU or exposed by the guest,
4309	* mark all state-bits as dirty indicating to the CPU to re-load from VMCB.
4310	*/
4311	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu, pCtx);
4312	if (!fSupportsVmcbCleanBits)
4313	pVmcbNstGst->ctrl.u32VmcbCleanBits = 0;
4314	}
4315	#endif
4316
4317
4318	/**
4319	* Prepares to run guest code in AMD-V and we've committed to doing so. This
4320	* means there is no backing out to ring-3 or anywhere else at this
4321	* point.
4322	*
4323	* @param pVM The cross context VM structure.
4324	* @param pVCpu The cross context virtual CPU structure.
4325	* @param pCtx Pointer to the guest-CPU context.
4326	* @param pSvmTransient Pointer to the SVM transient structure.
4327	*
4328	* @remarks Called with preemption disabled.
4329	* @remarks No-long-jump zone!!!
4330	*/
4331	static void hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4332	{
4333	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4334	Assert(VMMR0IsLogFlushDisabled(pVCpu));
4335	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4336	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
4337
4338	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4339	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4340
4341	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4342	hmR0SvmInjectPendingEvent(pVCpu, pCtx, pVmcb);
4343
4344	if ( pVCpu->hm.s.fPreloadGuestFpu
4345	&& !CPUMIsGuestFPUStateActive(pVCpu))
4346	{
4347	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4348	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
4349	}
4350
4351	/* Load the state shared between host and guest (FPU, debug). */
4352	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
4353	hmR0SvmLoadSharedState(pVCpu, pVmcb, pCtx);
4354
4355	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
4356	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
4357
4358	/* Setup TSC offsetting. */
4359	RTCPUID idCurrentCpu = hmR0GetCurrentCpu()->idCpu;
4360	if ( pSvmTransient->fUpdateTscOffsetting
4361	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
4362	{
4363	hmR0SvmUpdateTscOffsetting(pVM, pVCpu, pVmcb);
4364	pSvmTransient->fUpdateTscOffsetting = false;
4365	}
4366
4367	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4368	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
4369	pVmcb->ctrl.u32VmcbCleanBits = 0;
4370
4371	/* Store status of the shared guest-host state at the time of VMRUN. */
4372	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4373	if (CPUMIsGuestInLongModeEx(pCtx))
4374	{
4375	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
4376	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
4377	}
4378	else
4379	#endif
4380	{
4381	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4382	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4383	}
4384	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
4385
4386	/* Flush the appropriate tagged-TLB entries. */
4387	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4388	hmR0SvmFlushTaggedTlb(pVCpu, pCtx, pVmcb);
4389	Assert(hmR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
4390
4391	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4392
4393	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
4394	to start executing. */
4395
4396	/*
4397	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
4398	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
4399	*
4400	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4401	*/
4402	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
4403	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
4404	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4405	{
4406	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4407	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4408	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
4409	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
4410	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
4411	pSvmTransient->fRestoreTscAuxMsr = true;
4412	}
4413	else
4414	{
4415	hmR0SvmSetMsrPermission(pVmcb, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4416	pSvmTransient->fRestoreTscAuxMsr = false;
4417	}
4418
4419	/* If VMCB Clean bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
4420	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu, pCtx);
4421	if (!fSupportsVmcbCleanBits)
4422	pVmcb->ctrl.u32VmcbCleanBits = 0;
4423	}
4424
4425
4426	/**
4427	* Wrapper for running the guest code in AMD-V.
4428	*
4429	* @returns VBox strict status code.
4430	* @param pVM The cross context VM structure.
4431	* @param pVCpu The cross context virtual CPU structure.
4432	* @param pCtx Pointer to the guest-CPU context.
4433	*
4434	* @remarks No-long-jump zone!!!
4435	*/
4436	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4437	{
4438	/*
4439	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4440	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4441	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4442	*/
4443	#ifdef VBOX_WITH_KERNEL_USING_XMM
4444	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
4445	pVCpu->hm.s.svm.pfnVMRun);
4446	#else
4447	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
4448	#endif
4449	}
4450
4451
4452	#ifdef VBOX_WITH_NESTED_HWVIRT
4453	/**
4454	* Wrapper for running the nested-guest code in AMD-V.
4455	*
4456	* @returns VBox strict status code.
4457	* @param pVM The cross context VM structure.
4458	* @param pVCpu The cross context virtual CPU structure.
4459	* @param pCtx Pointer to the guest-CPU context.
4460	*
4461	* @remarks No-long-jump zone!!!
4462	*/
4463	DECLINLINE(int) hmR0SvmRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4464	{
4465	/*
4466	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
4467	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
4468	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
4469	*/
4470	#ifdef VBOX_WITH_KERNEL_USING_XMM
4471	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
4472	pVCpu->hm.s.svm.pfnVMRun);
4473	#else
4474	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pCtx->hwvirt.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
4475	#endif
4476	}
4477
4478
4479	/**
4480	* Performs some essential restoration of state after running nested-guest code in
4481	* AMD-V.
4482	*
4483	* @param pVM The cross context VM structure.
4484	* @param pVCpu The cross context virtual CPU structure.
4485	* @param pMixedCtx Pointer to the nested-guest-CPU context. The data maybe
4486	* out-of-sync. Make sure to update the required fields
4487	* before using them.
4488	* @param pSvmTransient Pointer to the SVM transient structure.
4489	* @param rcVMRun Return code of VMRUN.
4490	*
4491	* @remarks Called with interrupts disabled.
4492	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4493	* unconditionally when it is safe to do so.
4494	*/
4495	static void hmR0SvmPostRunGuestNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4496	{
4497	RT_NOREF(pVM);
4498	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4499
4500	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4501	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4502
4503	/* TSC read must be done early for maximum accuracy. */
4504	PSVMVMCB pVmcbNstGst = pMixedCtx->hwvirt.svm.CTX_SUFF(pVmcb);
4505	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
4506	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
4507	if (!(pVmcbNstGstCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4508	{
4509	/*
4510	* Undo what we did in hmR0SvmUpdateTscOffsettingNested() but don't restore the
4511	* nested-guest VMCB TSC offset here. It shall eventually be restored on #VMEXIT
4512	* later by HMSvmNstGstVmExitNotify().
4513	*/
4514	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcbNstGstCtrl->u64TSCOffset - pVmcbNstGstCache->u64TSCOffset);
4515	}
4516
4517	if (pSvmTransient->fRestoreTscAuxMsr)
4518	{
4519	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4520	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4521	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4522	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4523	}
4524
4525	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
4526	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4527	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4528
4529	Assert(!(ASMGetFlags() & X86_EFL_IF));
4530	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4531	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4532
4533	/* Mark the VMCB-state cache as unmodified by VMM. */
4534	pVmcbNstGstCtrl->u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL;
4535
4536	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4537	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4538	{
4539	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4540	return;
4541	}
4542
4543	pSvmTransient->u64ExitCode = pVmcbNstGstCtrl->u64ExitCode; /* Save the #VMEXIT reason. */
4544	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcbNstGstCtrl->u64ExitCode);/* Update the #VMEXIT history array. */
4545	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4546	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4547
4548	Assert(!pVCpu->hm.s.svm.fSyncVTpr);
4549	hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcbNstGst); /* Save the nested-guest state from the VMCB to the
4550	guest-CPU context. */
4551	}
4552	#endif
4553
4554	/**
4555	* Performs some essential restoration of state after running guest code in
4556	* AMD-V.
4557	*
4558	* @param pVM The cross context VM structure.
4559	* @param pVCpu The cross context virtual CPU structure.
4560	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
4561	* out-of-sync. Make sure to update the required fields
4562	* before using them.
4563	* @param pSvmTransient Pointer to the SVM transient structure.
4564	* @param rcVMRun Return code of VMRUN.
4565	*
4566	* @remarks Called with interrupts disabled.
4567	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4568	* unconditionally when it is safe to do so.
4569	*/
4570	static void hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4571	{
4572	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4573
4574	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4575	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4576
4577	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4578	pVmcb->ctrl.u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
4579
4580	/* TSC read must be done early for maximum accuracy. */
4581	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4582	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset);
4583
4584	if (pSvmTransient->fRestoreTscAuxMsr)
4585	{
4586	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4587	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4588	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4589	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4590	}
4591
4592	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
4593	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4594	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4595
4596	Assert(!(ASMGetFlags() & X86_EFL_IF));
4597	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4598	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4599
4600	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4601	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4602	{
4603	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4604	return;
4605	}
4606
4607	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
4608	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcb->ctrl.u64ExitCode); /* Update the #VMEXIT history array. */
4609	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4610	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4611
4612	hmR0SvmSaveGuestState(pVCpu, pMixedCtx, pVmcb); /* Save the guest state from the VMCB to the guest-CPU context. */
4613
4614	if (RT_LIKELY(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID))
4615	{
4616	if (pVCpu->hm.s.svm.fSyncVTpr)
4617	{
4618	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
4619	if ( pVM->hm.s.fTPRPatchingActive
4620	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
4621	{
4622	int rc = APICSetTpr(pVCpu, pMixedCtx->msrLSTAR & 0xff);
4623	AssertRC(rc);
4624	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4625	}
4626	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
4627	{
4628	int rc = APICSetTpr(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
4629	AssertRC(rc);
4630	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4631	}
4632	}
4633	}
4634	}
4635
4636
4637	/**
4638	* Runs the guest code using AMD-V.
4639	*
4640	* @returns VBox status code.
4641	* @param pVM The cross context VM structure.
4642	* @param pVCpu The cross context virtual CPU structure.
4643	* @param pCtx Pointer to the guest-CPU context.
4644	* @param pcLoops Pointer to the number of executed loops.
4645	*/
4646	static int hmR0SvmRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4647	{
4648	uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
4649	Assert(pcLoops);
4650	Assert(*pcLoops <= cMaxResumeLoops);
4651
4652	SVMTRANSIENT SvmTransient;
4653	SvmTransient.fUpdateTscOffsetting = true;
4654
4655	int rc = VERR_INTERNAL_ERROR_5;
4656	for (;;)
4657	{
4658	Assert(!HMR0SuspendPending());
4659	HMSVM_ASSERT_CPU_SAFE();
4660
4661	/* Preparatory work for running guest code, this may force us to return
4662	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4663	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4664	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
4665	if (rc != VINF_SUCCESS)
4666	break;
4667
4668	/*
4669	* No longjmps to ring-3 from this point on!!!
4670	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4671	* This also disables flushing of the R0-logger instance (if any).
4672	*/
4673	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
4674	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
4675
4676	/* Restore any residual host-state and save any bits shared between host
4677	and guest into the guest-CPU state. Re-enables interrupts! */
4678	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
4679
4680	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4681	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4682	{
4683	if (rc == VINF_SUCCESS)
4684	rc = VERR_SVM_INVALID_GUEST_STATE;
4685	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4686	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4687	break;
4688	}
4689
4690	/* Handle the #VMEXIT. */
4691	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4692	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4693	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4694	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
4695	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4696	if (rc != VINF_SUCCESS)
4697	break;
4698	if (++(*pcLoops) >= cMaxResumeLoops)
4699	{
4700	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4701	rc = VINF_EM_RAW_INTERRUPT;
4702	break;
4703	}
4704	}
4705
4706	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4707	return rc;
4708	}
4709
4710
4711	/**
4712	* Runs the guest code using AMD-V in single step mode.
4713	*
4714	* @returns VBox status code.
4715	* @param pVM The cross context VM structure.
4716	* @param pVCpu The cross context virtual CPU structure.
4717	* @param pCtx Pointer to the guest-CPU context.
4718	* @param pcLoops Pointer to the number of executed loops.
4719	*/
4720	static int hmR0SvmRunGuestCodeStep(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4721	{
4722	uint32_t const cMaxResumeLoops = pVM->hm.s.cMaxResumeLoops;
4723	Assert(pcLoops);
4724	Assert(*pcLoops <= cMaxResumeLoops);
4725
4726	SVMTRANSIENT SvmTransient;
4727	SvmTransient.fUpdateTscOffsetting = true;
4728
4729	uint16_t uCsStart = pCtx->cs.Sel;
4730	uint64_t uRipStart = pCtx->rip;
4731
4732	int rc = VERR_INTERNAL_ERROR_5;
4733	for (;;)
4734	{
4735	Assert(!HMR0SuspendPending());
4736	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
4737	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
4738	(unsigned)RTMpCpuId(), *pcLoops));
4739
4740	/* Preparatory work for running guest code, this may force us to return
4741	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4742	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4743	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
4744	if (rc != VINF_SUCCESS)
4745	break;
4746
4747	/*
4748	* No longjmps to ring-3 from this point on!!!
4749	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4750	* This also disables flushing of the R0-logger instance (if any).
4751	*/
4752	VMMRZCallRing3Disable(pVCpu);
4753	VMMRZCallRing3RemoveNotification(pVCpu);
4754	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
4755
4756	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
4757
4758	/*
4759	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
4760	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
4761	*/
4762	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
4763	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4764	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4765	{
4766	if (rc == VINF_SUCCESS)
4767	rc = VERR_SVM_INVALID_GUEST_STATE;
4768	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
4769	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
4770	return rc;
4771	}
4772
4773	/* Handle the #VMEXIT. */
4774	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4775	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4776	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4777	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
4778	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4779	if (rc != VINF_SUCCESS)
4780	break;
4781	if (++(*pcLoops) >= cMaxResumeLoops)
4782	{
4783	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4784	rc = VINF_EM_RAW_INTERRUPT;
4785	break;
4786	}
4787
4788	/*
4789	* Did the RIP change, if so, consider it a single step.
4790	* Otherwise, make sure one of the TFs gets set.
4791	*/
4792	if ( pCtx->rip != uRipStart
4793	\|\| pCtx->cs.Sel != uCsStart)
4794	{
4795	rc = VINF_EM_DBG_STEPPED;
4796	break;
4797	}
4798	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
4799	}
4800
4801	/*
4802	* Clear the X86_EFL_TF if necessary.
4803	*/
4804	if (pVCpu->hm.s.fClearTrapFlag)
4805	{
4806	pVCpu->hm.s.fClearTrapFlag = false;
4807	pCtx->eflags.Bits.u1TF = 0;
4808	}
4809
4810	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4811	return rc;
4812	}
4813
4814	#ifdef VBOX_WITH_NESTED_HWVIRT
4815	/**
4816	* Runs the nested-guest code using AMD-V.
4817	*
4818	* @returns VBox status code.
4819	* @param pVM The cross context VM structure.
4820	* @param pVCpu The cross context virtual CPU structure.
4821	* @param pCtx Pointer to the guest-CPU context.
4822	* @param pcLoops Pointer to the number of executed loops. If we're switching
4823	* from the guest-code execution loop to this nested-guest
4824	* execution loop pass the remainder value, else pass 0.
4825	*/
4826	static int hmR0SvmRunGuestCodeNested(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t *pcLoops)
4827	{
4828	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4829	Assert(pcLoops);
4830	Assert(*pcLoops <= pVM->hm.s.cMaxResumeLoops);
4831
4832	SVMTRANSIENT SvmTransient;
4833	SvmTransient.fUpdateTscOffsetting = true;
4834
4835	int rc = VERR_INTERNAL_ERROR_4;
4836	for (;;)
4837	{
4838	Assert(!HMR0SuspendPending());
4839	HMSVM_ASSERT_CPU_SAFE();
4840
4841	/* Preparatory work for running nested-guest code, this may force us to return
4842	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4843	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4844	rc = hmR0SvmPreRunGuestNested(pVM, pVCpu, pCtx, &SvmTransient);
4845	if ( rc != VINF_SUCCESS
4846	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4847	{
4848	break;
4849	}
4850
4851	/*
4852	* No longjmps to ring-3 from this point on!!!
4853	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
4854	* This also disables flushing of the R0-logger instance (if any).
4855	*/
4856	hmR0SvmPreRunGuestCommittedNested(pVM, pVCpu, pCtx, &SvmTransient);
4857
4858	rc = hmR0SvmRunGuestNested(pVM, pVCpu, pCtx);
4859
4860	/* Restore any residual host-state and save any bits shared between host
4861	and guest into the guest-CPU state. Re-enables interrupts! */
4862	hmR0SvmPostRunGuestNested(pVM, pVCpu, pCtx, &SvmTransient, rc);
4863
4864	if (RT_LIKELY( rc == VINF_SUCCESS
4865	&& SvmTransient.u64ExitCode != SVM_EXIT_INVALID))
4866	{ /* extremely likely */ }
4867	else
4868	{
4869	/* VMRUN failed, shouldn't really happen, Guru. */
4870	if (rc != VINF_SUCCESS)
4871	break;
4872
4873	/* Invalid nested-guest state. Cause a #VMEXIT but assert on strict builds. */
4874	AssertMsgFailed(("Invalid nested-guest state. rc=%Rrc u64ExitCode=%#RX64\n", rc, SvmTransient.u64ExitCode));
4875	rc = VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0, 0));
4876	break;
4877	}
4878
4879	/* Handle the #VMEXIT. */
4880	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4881	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
4882	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
4883	rc = hmR0SvmHandleExitNested(pVCpu, pCtx, &SvmTransient);
4884	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
4885	if (rc != VINF_SUCCESS)
4886	break;
4887	if (++(*pcLoops) >= pVM->hm.s.cMaxResumeLoops)
4888	{
4889	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4890	rc = VINF_EM_RAW_INTERRUPT;
4891	break;
4892	}
4893
4894	/** @todo handle single-stepping */
4895	}
4896
4897	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4898	return rc;
4899	}
4900	#endif
4901
4902
4903	/**
4904	* Runs the guest code using AMD-V.
4905	*
4906	* @returns Strict VBox status code.
4907	* @param pVM The cross context VM structure.
4908	* @param pVCpu The cross context virtual CPU structure.
4909	* @param pCtx Pointer to the guest-CPU context.
4910	*/
4911	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
4912	{
4913	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4914	HMSVM_ASSERT_PREEMPT_SAFE();
4915	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pCtx);
4916
4917	uint32_t cLoops = 0;
4918	int rc;
4919	#ifdef VBOX_WITH_NESTED_HWVIRT
4920	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4921	#endif
4922	{
4923	if (!pVCpu->hm.s.fSingleInstruction)
4924	rc = hmR0SvmRunGuestCodeNormal(pVM, pVCpu, pCtx, &cLoops);
4925	else
4926	rc = hmR0SvmRunGuestCodeStep(pVM, pVCpu, pCtx, &cLoops);
4927	}
4928	#ifdef VBOX_WITH_NESTED_HWVIRT
4929	else
4930	{
4931	rc = VINF_SVM_VMRUN;
4932	}
4933
4934	/* Re-check the nested-guest condition here as we may be transitioning from the normal
4935	execution loop into the nested-guest, hence this is not placed in the 'else' part above. */
4936	if (rc == VINF_SVM_VMRUN)
4937	{
4938	rc = hmR0SvmRunGuestCodeNested(pVM, pVCpu, pCtx, &cLoops);
4939	if (rc == VINF_SVM_VMEXIT)
4940	rc = VINF_SUCCESS;
4941	}
4942	#endif
4943
4944	/* Fixup error codes. */
4945	if (rc == VERR_EM_INTERPRETER)
4946	rc = VINF_EM_RAW_EMULATE_INSTR;
4947	else if (rc == VINF_EM_RESET)
4948	rc = VINF_EM_TRIPLE_FAULT;
4949
4950	/* Prepare to return to ring-3. This will remove longjmp notifications. */
4951	rc = hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
4952	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
4953	return rc;
4954	}
4955
4956
4957	#ifdef VBOX_WITH_NESTED_HWVIRT
4958	/**
4959	* Determines whether an IOIO intercept is active for the nested-guest or not.
4960	*
4961	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
4962	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO.
4963	*/
4964	static bool hmR0SvmIsIoInterceptActive(void *pvIoBitmap, PSVMIOIOEXITINFO pIoExitInfo)
4965	{
4966	const uint16_t u16Port = pIoExitInfo->n.u16Port;
4967	const SVMIOIOTYPE enmIoType = (SVMIOIOTYPE)pIoExitInfo->n.u1Type;
4968	const uint8_t cbReg = (pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7;
4969	const uint8_t cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
4970	const uint8_t iEffSeg = pIoExitInfo->n.u3SEG;
4971	const bool fRep = pIoExitInfo->n.u1REP;
4972	const bool fStrIo = pIoExitInfo->n.u1STR;
4973
4974	return HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
4975	NULL /* pIoExitInfo */);
4976	}
4977
4978
4979	/**
4980	* Handles a nested-guest \#VMEXIT (for all EXITCODE values except
4981	* SVM_EXIT_INVALID).
4982	*
4983	* @returns VBox status code (informational status codes included).
4984	* @param pVCpu The cross context virtual CPU structure.
4985	* @param pCtx Pointer to the guest-CPU context.
4986	* @param pSvmTransient Pointer to the SVM transient structure.
4987	*/
4988	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4989	{
4990	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4991	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
4992	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
4993
4994	#define HM_SVM_VMEXIT_NESTED(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
4995	VBOXSTRICTRC_TODO(IEMExecSvmVmexit(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2))
4996
4997	/*
4998	* For all the #VMEXITs here we primarily figure out if the #VMEXIT is expected
4999	* by the nested-guest. If it isn't, it should be handled by the (outer) guest.
5000	*/
5001	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
5002	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
5003	uint64_t const uExitCode = pVmcbNstGstCtrl->u64ExitCode;
5004	uint64_t const uExitInfo1 = pVmcbNstGstCtrl->u64ExitInfo1;
5005	uint64_t const uExitInfo2 = pVmcbNstGstCtrl->u64ExitInfo2;
5006
5007	Assert(uExitCode == pVmcbNstGstCtrl->u64ExitCode);
5008	switch (uExitCode)
5009	{
5010	case SVM_EXIT_CPUID:
5011	{
5012	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CPUID))
5013	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5014	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
5015	}
5016
5017	case SVM_EXIT_RDTSC:
5018	{
5019	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSC))
5020	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5021	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
5022	}
5023
5024	case SVM_EXIT_RDTSCP:
5025	{
5026	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDTSCP))
5027	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5028	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
5029	}
5030
5031
5032	case SVM_EXIT_MONITOR:
5033	{
5034	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MONITOR))
5035	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5036	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
5037	}
5038
5039	case SVM_EXIT_MWAIT:
5040	{
5041	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MWAIT))
5042	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5043	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
5044	}
5045
5046	case SVM_EXIT_HLT:
5047	{
5048	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_HLT))
5049	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5050	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
5051	}
5052
5053	case SVM_EXIT_MSR:
5054	{
5055	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_MSR_PROT))
5056	{
5057	uint32_t const idMsr = pCtx->ecx;
5058	uint16_t offMsrpm;
5059	uint32_t uMsrpmBit;
5060	int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
5061	if (RT_SUCCESS(rc))
5062	{
5063	void const *pvMsrBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvMsrBitmap);
5064	bool const fInterceptRead = ASMBitTest(pvMsrBitmap, (offMsrpm << 3) + uMsrpmBit);
5065	bool const fInterceptWrite = ASMBitTest(pvMsrBitmap, (offMsrpm << 3) + uMsrpmBit + 1);
5066
5067	if ( (fInterceptWrite && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
5068	\|\| (fInterceptRead && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_READ))
5069	{
5070	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5071	}
5072	}
5073	else
5074	{
5075	/*
5076	* MSRs not covered by the MSRPM automatically cause an #VMEXIT.
5077	* See AMD-V spec. "15.11 MSR Intercepts".
5078	*/
5079	Assert(rc == VERR_OUT_OF_RANGE);
5080	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5081	}
5082	}
5083	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
5084	}
5085
5086	case SVM_EXIT_IOIO:
5087	{
5088	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IOIO_PROT))
5089	{
5090	void *pvIoBitmap = pCtx->hwvirt.svm.CTX_SUFF(pvIoBitmap);
5091	SVMIOIOEXITINFO IoExitInfo;
5092	IoExitInfo.u = pVmcbNstGst->ctrl.u64ExitInfo1;
5093	bool const fIntercept = hmR0SvmIsIoInterceptActive(pvIoBitmap, &IoExitInfo);
5094	if (fIntercept)
5095	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5096	}
5097	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
5098	}
5099
5100	case SVM_EXIT_EXCEPTION_14: /* X86_XCPT_PF */
5101	{
5102	PVM pVM = pVCpu->CTX_SUFF(pVM);
5103	if (pVM->hm.s.fNestedPaging)
5104	{
5105	uint32_t const u32ErrCode = pVmcbNstGstCtrl->u64ExitInfo1;
5106	uint64_t const uFaultAddress = pVmcbNstGstCtrl->u64ExitInfo2;
5107
5108	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
5109	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
5110	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
5111
5112	/* If the nested-guest is not intercepting #PFs, forward the #PF to the nested-guest. */
5113	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
5114	return VINF_SUCCESS;
5115	}
5116	return hmR0SvmExitXcptPFNested(pVCpu, pCtx,pSvmTransient);
5117	}
5118
5119	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
5120	{
5121	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_NM))
5122	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5123	hmR0SvmSetPendingXcptNM(pVCpu);
5124	return VINF_SUCCESS;
5125	}
5126
5127	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
5128	{
5129	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_UD))
5130	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5131	hmR0SvmSetPendingXcptUD(pVCpu);
5132	return VINF_SUCCESS;
5133	}
5134
5135	case SVM_EXIT_EXCEPTION_16: /* X86_XCPT_MF */
5136	{
5137	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_MF))
5138	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5139	hmR0SvmSetPendingXcptMF(pVCpu);
5140	return VINF_SUCCESS;
5141	}
5142
5143	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
5144	{
5145	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_DB))
5146	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5147	return hmR0SvmNestedExitXcptDB(pVCpu, pCtx, pSvmTransient);
5148	}
5149
5150	case SVM_EXIT_EXCEPTION_17: /* X86_XCPT_AC */
5151	{
5152	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_AC))
5153	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5154	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
5155	}
5156
5157	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
5158	{
5159	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_BP))
5160	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5161	return hmR0SvmNestedExitXcptBP(pVCpu, pCtx, pSvmTransient);
5162	}
5163
5164	case SVM_EXIT_READ_CR0:
5165	case SVM_EXIT_READ_CR3:
5166	case SVM_EXIT_READ_CR4:
5167	{
5168	uint8_t const uCr = uExitCode - SVM_EXIT_READ_CR0;
5169	if (HMIsGuestSvmReadCRxInterceptSet(pVCpu, pCtx, uCr))
5170	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5171	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
5172	}
5173
5174	case SVM_EXIT_WRITE_CR0:
5175	case SVM_EXIT_WRITE_CR3:
5176	case SVM_EXIT_WRITE_CR4:
5177	case SVM_EXIT_WRITE_CR8: /** @todo Shouldn't writes to CR8 go to V_TPR instead since we run with V_INTR_MASKING set?? */
5178	{
5179	uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
5180	Log4(("hmR0SvmHandleExitNested: Write CR%u: uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uCr, uExitInfo1, uExitInfo2));
5181
5182	if (HMIsGuestSvmWriteCRxInterceptSet(pVCpu, pCtx, uCr))
5183	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5184	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
5185	}
5186
5187	case SVM_EXIT_PAUSE:
5188	{
5189	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_PAUSE))
5190	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5191	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
5192	}
5193
5194	case SVM_EXIT_VINTR:
5195	{
5196	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VINTR))
5197	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5198	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5199	}
5200
5201	case SVM_EXIT_INTR:
5202	case SVM_EXIT_NMI:
5203	case SVM_EXIT_SMI:
5204	{
5205	/*
5206	* We shouldn't direct physical interrupts, NMIs, SMIs to the nested-guest.
5207	*
5208	* Although we don't intercept SMIs, the nested-guest might. Therefore, we
5209	* might get an SMI #VMEXIT here so simply ignore rather than causing a
5210	* corresponding nested-guest #VMEXIT.
5211	*/
5212	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
5213	}
5214
5215	case SVM_EXIT_FERR_FREEZE:
5216	{
5217	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_FERR_FREEZE))
5218	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5219	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
5220	}
5221
5222	case SVM_EXIT_INVLPG:
5223	{
5224	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPG))
5225	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5226	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
5227	}
5228
5229	case SVM_EXIT_WBINVD:
5230	{
5231	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_WBINVD))
5232	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5233	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
5234	}
5235
5236	case SVM_EXIT_INVD:
5237	{
5238	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVD))
5239	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5240	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
5241	}
5242
5243	case SVM_EXIT_RDPMC:
5244	{
5245	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RDPMC))
5246	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5247	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
5248	}
5249
5250	default:
5251	{
5252	switch (uExitCode)
5253	{
5254	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5255	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5256	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5257	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5258	{
5259	uint8_t const uDr = uExitCode - SVM_EXIT_READ_DR0;
5260	if (HMIsGuestSvmReadDRxInterceptSet(pVCpu, pCtx, uDr))
5261	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5262	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
5263	}
5264
5265	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5266	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5267	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5268	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5269	{
5270	uint8_t const uDr = uExitCode - SVM_EXIT_WRITE_DR0;
5271	if (HMIsGuestSvmWriteDRxInterceptSet(pVCpu, pCtx, uDr))
5272	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5273	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
5274	}
5275
5276	/* The exceptions not handled here are already handled individually above (as they occur more frequently). */
5277	case SVM_EXIT_EXCEPTION_0: /case SVM_EXIT_EXCEPTION_1:/ case SVM_EXIT_EXCEPTION_2:
5278	/case SVM_EXIT_EXCEPTION_3:/ case SVM_EXIT_EXCEPTION_4: case SVM_EXIT_EXCEPTION_5:
5279	/case SVM_EXIT_EXCEPTION_6:/ /case SVM_EXIT_EXCEPTION_7:/ case SVM_EXIT_EXCEPTION_8:
5280	case SVM_EXIT_EXCEPTION_9: case SVM_EXIT_EXCEPTION_10: case SVM_EXIT_EXCEPTION_11:
5281	case SVM_EXIT_EXCEPTION_12: case SVM_EXIT_EXCEPTION_13: /case SVM_EXIT_EXCEPTION_14:/
5282	case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16: /case SVM_EXIT_EXCEPTION_17:/
5283	case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19: case SVM_EXIT_EXCEPTION_20:
5284	case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22: case SVM_EXIT_EXCEPTION_23:
5285	case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25: case SVM_EXIT_EXCEPTION_26:
5286	case SVM_EXIT_EXCEPTION_27: case SVM_EXIT_EXCEPTION_28: case SVM_EXIT_EXCEPTION_29:
5287	case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
5288	{
5289	uint8_t const uVector = uExitCode - SVM_EXIT_EXCEPTION_0;
5290	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, uVector))
5291	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5292	return hmR0SvmExitXcptGeneric(pVCpu, pCtx, pSvmTransient);
5293	}
5294
5295	case SVM_EXIT_XSETBV:
5296	{
5297	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_XSETBV))
5298	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5299	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
5300	}
5301
5302	case SVM_EXIT_TASK_SWITCH:
5303	{
5304	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_TASK_SWITCH))
5305	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5306	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
5307	}
5308
5309	case SVM_EXIT_IRET:
5310	{
5311	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_IRET))
5312	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5313	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
5314	}
5315
5316	case SVM_EXIT_SHUTDOWN:
5317	{
5318	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SHUTDOWN))
5319	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5320	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
5321	}
5322
5323	case SVM_EXIT_VMMCALL:
5324	{
5325	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMMCALL))
5326	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5327	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
5328	}
5329
5330	case SVM_EXIT_CLGI:
5331	{
5332	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_CLGI))
5333	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5334	return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
5335	}
5336
5337	case SVM_EXIT_STGI:
5338	{
5339	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_STGI))
5340	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5341	return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
5342	}
5343
5344	case SVM_EXIT_VMLOAD:
5345	{
5346	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMLOAD))
5347	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5348	return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
5349	}
5350
5351	case SVM_EXIT_VMSAVE:
5352	{
5353	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMSAVE))
5354	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5355	return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
5356	}
5357
5358	case SVM_EXIT_INVLPGA:
5359	{
5360	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INVLPGA))
5361	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5362	return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
5363	}
5364
5365	case SVM_EXIT_VMRUN:
5366	{
5367	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_VMRUN))
5368	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5369	return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
5370	}
5371
5372	case SVM_EXIT_RSM:
5373	{
5374	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_RSM))
5375	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5376	hmR0SvmSetPendingXcptUD(pVCpu);
5377	return VINF_SUCCESS;
5378	}
5379
5380	case SVM_EXIT_SKINIT:
5381	{
5382	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_SKINIT))
5383	return HM_SVM_VMEXIT_NESTED(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5384	hmR0SvmSetPendingXcptUD(pVCpu);
5385	return VINF_SUCCESS;
5386	}
5387
5388	/** @todo Needed when restoring saved-state when saved state support wasn't yet
5389	* added. Perhaps it won't be required later. */
5390	#if 0
5391	case SVM_EXIT_NPF:
5392	{
5393	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
5394	if (HMIsGuestSvmXcptInterceptSet(pVCpu, pCtx, X86_XCPT_PF))
5395	return HM_SVM_VMEXIT_NESTED(pVCpu, SVM_EXIT_EXCEPTION_14, RT_LO_U32(uExitInfo1), uExitInfo2);
5396	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, RT_LO_U32(uExitInfo1), uExitInfo2);
5397	return VINF_SUCCESS;
5398	}
5399	#else
5400	case SVM_EXIT_NPF:
5401	#endif
5402	case SVM_EXIT_INIT: /* We shouldn't get INIT signals while executing a nested-guest. */
5403	{
5404	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5405	}
5406
5407	default:
5408	{
5409	AssertMsgFailed(("hmR0SvmHandleExitNested: Unknown exit code %#x\n", pSvmTransient->u64ExitCode));
5410	pVCpu->hm.s.u32HMError = pSvmTransient->u64ExitCode;
5411	return VERR_SVM_UNKNOWN_EXIT;
5412	}
5413	}
5414	}
5415	}
5416	/* not reached */
5417
5418	#undef HM_SVM_VMEXIT_NESTED
5419	}
5420	#endif
5421
5422
5423	/**
5424	* Handles a guest \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
5425	*
5426	* @returns VBox status code (informational status codes included).
5427	* @param pVCpu The cross context virtual CPU structure.
5428	* @param pCtx Pointer to the guest-CPU context.
5429	* @param pSvmTransient Pointer to the SVM transient structure.
5430	*/
5431	static int hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5432	{
5433	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5434	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5435
5436	/*
5437	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs for most guests under
5438	* normal workloads (for some definition of "normal").
5439	*/
5440	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
5441	switch (uExitCode)
5442	{
5443	case SVM_EXIT_NPF:
5444	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
5445
5446	case SVM_EXIT_IOIO:
5447	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
5448
5449	case SVM_EXIT_RDTSC:
5450	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
5451
5452	case SVM_EXIT_RDTSCP:
5453	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
5454
5455	case SVM_EXIT_CPUID:
5456	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
5457
5458	case SVM_EXIT_EXCEPTION_14: /* X86_XCPT_PF */
5459	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
5460
5461	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
5462	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
5463
5464	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
5465	return hmR0SvmExitXcptUD(pVCpu, pCtx, pSvmTransient);
5466
5467	case SVM_EXIT_EXCEPTION_16: /* X86_XCPT_MF */
5468	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
5469
5470	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
5471	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
5472
5473	case SVM_EXIT_EXCEPTION_17: /* X86_XCPT_AC */
5474	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
5475
5476	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
5477	return hmR0SvmExitXcptBP(pVCpu, pCtx, pSvmTransient);
5478
5479	case SVM_EXIT_MONITOR:
5480	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
5481
5482	case SVM_EXIT_MWAIT:
5483	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
5484
5485	case SVM_EXIT_HLT:
5486	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
5487
5488	case SVM_EXIT_READ_CR0:
5489	case SVM_EXIT_READ_CR3:
5490	case SVM_EXIT_READ_CR4:
5491	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
5492
5493	case SVM_EXIT_WRITE_CR0:
5494	case SVM_EXIT_WRITE_CR3:
5495	case SVM_EXIT_WRITE_CR4:
5496	case SVM_EXIT_WRITE_CR8:
5497	{
5498	uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
5499	Log4(("hmR0SvmHandleExit: Write CR%u\n", uCr)); NOREF(uCr);
5500	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
5501	}
5502
5503	case SVM_EXIT_PAUSE:
5504	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
5505
5506	case SVM_EXIT_VMMCALL:
5507	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
5508
5509	case SVM_EXIT_VINTR:
5510	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
5511
5512	case SVM_EXIT_INTR:
5513	case SVM_EXIT_FERR_FREEZE:
5514	case SVM_EXIT_NMI:
5515	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
5516
5517	case SVM_EXIT_MSR:
5518	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
5519
5520	case SVM_EXIT_INVLPG:
5521	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
5522
5523	case SVM_EXIT_WBINVD:
5524	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
5525
5526	case SVM_EXIT_INVD:
5527	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
5528
5529	case SVM_EXIT_RDPMC:
5530	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
5531
5532	default:
5533	{
5534	switch (pSvmTransient->u64ExitCode)
5535	{
5536	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5537	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5538	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5539	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5540	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
5541
5542	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5543	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5544	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5545	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5546	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
5547
5548	case SVM_EXIT_XSETBV:
5549	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
5550
5551	case SVM_EXIT_TASK_SWITCH:
5552	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
5553
5554	case SVM_EXIT_IRET:
5555	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
5556
5557	case SVM_EXIT_SHUTDOWN:
5558	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
5559
5560	case SVM_EXIT_SMI:
5561	case SVM_EXIT_INIT:
5562	{
5563	/*
5564	* We don't intercept SMIs. As for INIT signals, it really shouldn't ever happen here.
5565	* If it ever does, we want to know about it so log the exit code and bail.
5566	*/
5567	return hmR0SvmExitUnexpected(pVCpu, pCtx, pSvmTransient);
5568	}
5569
5570	#ifdef VBOX_WITH_NESTED_HWVIRT
5571	case SVM_EXIT_CLGI: return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
5572	case SVM_EXIT_STGI: return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
5573	case SVM_EXIT_VMLOAD: return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
5574	case SVM_EXIT_VMSAVE: return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
5575	case SVM_EXIT_INVLPGA: return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
5576	case SVM_EXIT_VMRUN: return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
5577	#else
5578	case SVM_EXIT_CLGI:
5579	case SVM_EXIT_STGI:
5580	case SVM_EXIT_VMLOAD:
5581	case SVM_EXIT_VMSAVE:
5582	case SVM_EXIT_INVLPGA:
5583	case SVM_EXIT_VMRUN:
5584	#endif
5585	case SVM_EXIT_RSM:
5586	case SVM_EXIT_SKINIT:
5587	{
5588	hmR0SvmSetPendingXcptUD(pVCpu);
5589	return VINF_SUCCESS;
5590	}
5591
5592	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5593	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
5594	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
5595	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
5596	/* SVM_EXIT_EXCEPTION_3: / / X86_XCPT_BP - Handled above. */
5597	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
5598	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
5599	/* SVM_EXIT_EXCEPTION_6: / / X86_XCPT_UD - Handled above. */
5600	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
5601	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
5602	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
5603	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_TS */
5604	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_NP */
5605	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_SS */
5606	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_GP */
5607	/* SVM_EXIT_EXCEPTION_14: / / X86_XCPT_PF - Handled above. */
5608	case SVM_EXIT_EXCEPTION_15: /* Reserved. */
5609	/* SVM_EXIT_EXCEPTION_16: / / X86_XCPT_MF - Handled above. */
5610	/* SVM_EXIT_EXCEPTION_17: / / X86_XCPT_AC - Handled above. */
5611	case SVM_EXIT_EXCEPTION_18: /* X86_XCPT_MC */
5612	case SVM_EXIT_EXCEPTION_19: /* X86_XCPT_XF */
5613	case SVM_EXIT_EXCEPTION_20: case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22:
5614	case SVM_EXIT_EXCEPTION_23: case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25:
5615	case SVM_EXIT_EXCEPTION_26: case SVM_EXIT_EXCEPTION_27: case SVM_EXIT_EXCEPTION_28:
5616	case SVM_EXIT_EXCEPTION_29: case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
5617	return hmR0SvmExitXcptGeneric(pVCpu, pCtx, pSvmTransient);
5618	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
5619
5620	default:
5621	{
5622	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#RX64\n", uExitCode));
5623	pVCpu->hm.s.u32HMError = uExitCode;
5624	return VERR_SVM_UNKNOWN_EXIT;
5625	}
5626	}
5627	}
5628	}
5629	/* not reached */
5630	}
5631
5632
5633	#ifdef DEBUG
5634	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
5635	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
5636	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
5637
5638	# define HMSVM_ASSERT_PREEMPT_CPUID() \
5639	do \
5640	{ \
5641	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
5642	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
5643	} while (0)
5644
5645	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
5646	do { \
5647	AssertPtr(pVCpu); \
5648	AssertPtr(pCtx); \
5649	AssertPtr(pSvmTransient); \
5650	Assert(ASMIntAreEnabled()); \
5651	HMSVM_ASSERT_PREEMPT_SAFE(); \
5652	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
5653	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
5654	HMSVM_ASSERT_PREEMPT_SAFE(); \
5655	if (VMMR0IsLogFlushDisabled(pVCpu)) \
5656	HMSVM_ASSERT_PREEMPT_CPUID(); \
5657	} while (0)
5658	#else /* Release builds */
5659	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { NOREF(pVCpu); NOREF(pCtx); NOREF(pSvmTransient); } while (0)
5660	#endif
5661
5662
5663	/**
5664	* Worker for hmR0SvmInterpretInvlpg().
5665	*
5666	* @return VBox status code.
5667	* @param pVCpu The cross context virtual CPU structure.
5668	* @param pCpu Pointer to the disassembler state.
5669	* @param pCtx The guest CPU context.
5670	*/
5671	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTX pCtx)
5672	{
5673	DISQPVPARAMVAL Param1;
5674	RTGCPTR GCPtrPage;
5675
5676	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
5677	if (RT_FAILURE(rc))
5678	return VERR_EM_INTERPRETER;
5679
5680	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
5681	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
5682	{
5683	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
5684	return VERR_EM_INTERPRETER;
5685
5686	GCPtrPage = Param1.val.val64;
5687	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), GCPtrPage);
5688	rc = VBOXSTRICTRC_VAL(rc2);
5689	}
5690	else
5691	{
5692	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
5693	rc = VERR_EM_INTERPRETER;
5694	}
5695
5696	return rc;
5697	}
5698
5699
5700	/**
5701	* Interprets INVLPG.
5702	*
5703	* @returns VBox status code.
5704	* @retval VINF_* Scheduling instructions.
5705	* @retval VERR_EM_INTERPRETER Something we can't cope with.
5706	* @retval VERR_* Fatal errors.
5707	*
5708	* @param pVM The cross context VM structure.
5709	* @param pVCpu The cross context virtual CPU structure.
5710	* @param pCtx The guest CPU context.
5711	*
5712	* @remarks Updates the RIP if the instruction was executed successfully.
5713	*/
5714	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
5715	{
5716	/* Only allow 32 & 64 bit code. */
5717	if (CPUMGetGuestCodeBits(pVCpu) != 16)
5718	{
5719	PDISSTATE pDis = &pVCpu->hm.s.DisState;
5720	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
5721	if ( RT_SUCCESS(rc)
5722	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
5723	{
5724	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pCtx);
5725	if (RT_SUCCESS(rc))
5726	pCtx->rip += pDis->cbInstr;
5727	return rc;
5728	}
5729	else
5730	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
5731	}
5732	return VERR_EM_INTERPRETER;
5733	}
5734
5735
5736	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
5737	/**
5738	* Gets the IEM exception flags for the specified SVM event.
5739	*
5740	* @returns The IEM exception flags.
5741	* @param pEvent Pointer to the SVM event.
5742	*
5743	* @remarks This function currently only constructs flags required for
5744	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
5745	* and CR2 aspects of an exception are not included).
5746	*/
5747	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
5748	{
5749	uint8_t const uEventType = pEvent->n.u3Type;
5750	uint32_t fIemXcptFlags;
5751	switch (uEventType)
5752	{
5753	case SVM_EVENT_EXCEPTION:
5754	/*
5755	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
5756	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
5757	*/
5758	if (pEvent->n.u8Vector == X86_XCPT_BP)
5759	{
5760	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
5761	break;
5762	}
5763	if (pEvent->n.u8Vector == X86_XCPT_OF)
5764	{
5765	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
5766	break;
5767	}
5768	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
5769	RT_FALL_THRU();
5770	case SVM_EVENT_NMI:
5771	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5772	break;
5773
5774	case SVM_EVENT_EXTERNAL_IRQ:
5775	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5776	break;
5777
5778	case SVM_EVENT_SOFTWARE_INT:
5779	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5780	break;
5781
5782	default:
5783	fIemXcptFlags = 0;
5784	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
5785	break;
5786	}
5787	return fIemXcptFlags;
5788	}
5789
5790	#else
5791	/**
5792	* Determines if an exception is a contributory exception.
5793	*
5794	* Contributory exceptions are ones which can cause double-faults unless the
5795	* original exception was a benign exception. Page-fault is intentionally not
5796	* included here as it's a conditional contributory exception.
5797	*
5798	* @returns @c true if the exception is contributory, @c false otherwise.
5799	* @param uVector The exception vector.
5800	*/
5801	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
5802	{
5803	switch (uVector)
5804	{
5805	case X86_XCPT_GP:
5806	case X86_XCPT_SS:
5807	case X86_XCPT_NP:
5808	case X86_XCPT_TS:
5809	case X86_XCPT_DE:
5810	return true;
5811	default:
5812	break;
5813	}
5814	return false;
5815	}
5816	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
5817
5818
5819	/**
5820	* Handle a condition that occurred while delivering an event through the guest
5821	* IDT.
5822	*
5823	* @returns VBox status code (informational error codes included).
5824	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
5825	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
5826	* continue execution of the guest which will delivery the \#DF.
5827	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5828	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5829	*
5830	* @param pVCpu The cross context virtual CPU structure.
5831	* @param pCtx Pointer to the guest-CPU context.
5832	* @param pSvmTransient Pointer to the SVM transient structure.
5833	*
5834	* @remarks No-long-jump zone!!!
5835	*/
5836	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5837	{
5838	int rc = VINF_SUCCESS;
5839	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
5840
5841	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
5842	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
5843	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
5844
5845	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
5846	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
5847	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
5848	{
5849	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
5850	IEMXCPTRAISE enmRaise;
5851	IEMXCPTRAISEINFO fRaiseInfo;
5852	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31;
5853	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5854	if (fExitIsHwXcpt)
5855	{
5856	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
5857	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
5858	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5859	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
5860	}
5861	else
5862	{
5863	/*
5864	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF) then we
5865	* end up here.
5866	*
5867	* If the event was:
5868	* - a software interrupt, we can re-execute the instruction which will regenerate
5869	* the event.
5870	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
5871	* - a hardware exception or external interrupt, we re-inject it.
5872	*/
5873	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5874	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
5875	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5876	else
5877	enmRaise = IEMXCPTRAISE_PREV_EVENT;
5878	}
5879
5880	switch (enmRaise)
5881	{
5882	case IEMXCPTRAISE_CURRENT_XCPT:
5883	case IEMXCPTRAISE_PREV_EVENT:
5884	{
5885	/* For software interrupts, we shall re-execute the instruction. */
5886	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
5887	{
5888	RTGCUINTPTR GCPtrFaultAddress = 0;
5889
5890	/* If we are re-injecting an NMI, clear NMI blocking. */
5891	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5892	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5893
5894	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
5895	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
5896	pSvmTransient->fVectoringPF = true;
5897	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
5898	&& uIdtVector == X86_XCPT_PF)
5899	{
5900	/*
5901	* If the previous exception was a #PF, we need to recover the CR2 value.
5902	* This can't happen with shadow paging.
5903	*/
5904	GCPtrFaultAddress = pCtx->cr2;
5905	}
5906
5907	/*
5908	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
5909	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
5910	*/
5911	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5912	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5913	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
5914
5915	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
5916	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
5917	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
5918	}
5919	break;
5920	}
5921
5922	case IEMXCPTRAISE_REEXEC_INSTR:
5923	{
5924	Assert(rc == VINF_SUCCESS);
5925	break;
5926	}
5927
5928	case IEMXCPTRAISE_DOUBLE_FAULT:
5929	{
5930	/*
5931	* Determing a vectoring double #PF condition. Used later, when PGM evaluates the
5932	* second #PF as a guest #PF (and not a shadow #PF) and needs to be converted into a #DF.
5933	*/
5934	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
5935	{
5936	pSvmTransient->fVectoringDoublePF = true;
5937	Assert(rc == VINF_SUCCESS);
5938	}
5939	else
5940	{
5941	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5942	hmR0SvmSetPendingXcptDF(pVCpu);
5943	rc = VINF_HM_DOUBLE_FAULT;
5944	}
5945	break;
5946	}
5947
5948	case IEMXCPTRAISE_TRIPLE_FAULT:
5949	{
5950	rc = VINF_EM_RESET;
5951	break;
5952	}
5953
5954	case IEMXCPTRAISE_CPU_HANG:
5955	{
5956	rc = VERR_EM_GUEST_CPU_HANG;
5957	break;
5958	}
5959
5960	default:
5961	{
5962	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
5963	rc = VERR_SVM_IPE_2;
5964	break;
5965	}
5966	}
5967	#else
5968	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5969
5970	typedef enum
5971	{
5972	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
5973	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
5974	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
5975	SVMREFLECTXCPT_HANG, /* Indicate bad VM trying to deadlock the CPU. */
5976	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
5977	} SVMREFLECTXCPT;
5978
5979	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
5980	bool fReflectingNmi = false;
5981	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
5982	{
5983	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31)
5984	{
5985	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
5986
5987	#ifdef VBOX_STRICT
5988	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
5989	&& uExitVector == X86_XCPT_PF)
5990	{
5991	Log4(("IDT: Contributory #PF idCpu=%u uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
5992	}
5993	#endif
5994
5995	if ( uIdtVector == X86_XCPT_BP
5996	\|\| uIdtVector == X86_XCPT_OF)
5997	{
5998	/* Ignore INT3/INTO, just re-execute. See @bugref{8357}. */
5999	}
6000	else if ( uExitVector == X86_XCPT_PF
6001	&& uIdtVector == X86_XCPT_PF)
6002	{
6003	pSvmTransient->fVectoringDoublePF = true;
6004	Log4(("IDT: Vectoring double #PF uCR2=%#RX64\n", pCtx->cr2));
6005	}
6006	else if ( uExitVector == X86_XCPT_AC
6007	&& uIdtVector == X86_XCPT_AC)
6008	{
6009	enmReflect = SVMREFLECTXCPT_HANG;
6010	Log4(("IDT: Nested #AC - Bad guest\n"));
6011	}
6012	else if ( (pVmcb->ctrl.u32InterceptXcpt & HMSVM_CONTRIBUTORY_XCPT_MASK)
6013	&& hmR0SvmIsContributoryXcpt(uExitVector)
6014	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
6015	\|\| uIdtVector == X86_XCPT_PF))
6016	{
6017	enmReflect = SVMREFLECTXCPT_DF;
6018	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
6019	uIdtVector, uExitVector));
6020	}
6021	else if (uIdtVector == X86_XCPT_DF)
6022	{
6023	enmReflect = SVMREFLECTXCPT_TF;
6024	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n",
6025	pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
6026	}
6027	else
6028	enmReflect = SVMREFLECTXCPT_XCPT;
6029	}
6030	else
6031	{
6032	/*
6033	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
6034	* exception to the guest after handling the #VMEXIT.
6035	*/
6036	enmReflect = SVMREFLECTXCPT_XCPT;
6037	}
6038	}
6039	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
6040	\|\| pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
6041	{
6042	enmReflect = SVMREFLECTXCPT_XCPT;
6043	fReflectingNmi = RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI);
6044
6045	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31)
6046	{
6047	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
6048	if (uExitVector == X86_XCPT_PF)
6049	{
6050	pSvmTransient->fVectoringPF = true;
6051	Log4(("IDT: Vectoring #PF due to Ext-Int/NMI. uCR2=%#RX64\n", pCtx->cr2));
6052	}
6053	}
6054	}
6055	/* else: Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
6056
6057	switch (enmReflect)
6058	{
6059	case SVMREFLECTXCPT_XCPT:
6060	{
6061	/* If we are re-injecting the NMI, clear NMI blocking. */
6062	if (fReflectingNmi)
6063	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
6064
6065	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
6066	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6067	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
6068
6069	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
6070	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
6071	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
6072	break;
6073	}
6074
6075	case SVMREFLECTXCPT_DF:
6076	{
6077	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6078	hmR0SvmSetPendingXcptDF(pVCpu);
6079	rc = VINF_HM_DOUBLE_FAULT;
6080	break;
6081	}
6082
6083	case SVMREFLECTXCPT_TF:
6084	{
6085	rc = VINF_EM_RESET;
6086	break;
6087	}
6088
6089	case SVMREFLECTXCPT_HANG:
6090	{
6091	rc = VERR_EM_GUEST_CPU_HANG;
6092	break;
6093	}
6094
6095	default:
6096	Assert(rc == VINF_SUCCESS);
6097	break;
6098	}
6099	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
6100	}
6101	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
6102	NOREF(pCtx);
6103	return rc;
6104	}
6105
6106
6107	/**
6108	* Advances the guest RIP making use of the CPU's NRIP_SAVE feature if
6109	* supported, otherwise advances the RIP by the number of bytes specified in
6110	* @a cb.
6111	*
6112	* @param pVCpu The cross context virtual CPU structure.
6113	* @param pCtx Pointer to the guest-CPU context.
6114	* @param cb RIP increment value in bytes.
6115	*
6116	* @remarks Use this function only from \#VMEXIT's where the NRIP value is valid
6117	* when NRIP_SAVE is supported by the CPU, otherwise use
6118	* hmR0SvmAdvanceRipDumb!
6119	*/
6120	DECLINLINE(void) hmR0SvmAdvanceRipHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
6121	{
6122	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6123	if (fSupportsNextRipSave)
6124	{
6125	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6126	Assert(pVmcb->ctrl.u64NextRIP);
6127	AssertRelease(pVmcb->ctrl.u64NextRIP - pCtx->rip == cb); /* temporary, remove later */
6128	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6129	}
6130	else
6131	pCtx->rip += cb;
6132
6133	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
6134	}
6135
6136
6137	#ifdef VBOX_WITH_NESTED_HWVIRT
6138	/**
6139	* Gets the length of the current instruction if the CPU supports the NRIP_SAVE
6140	* feature. Otherwise, returns the value in @a cbLikely.
6141	*
6142	* @param pVCpu The cross context virtual CPU structure.
6143	* @param pCtx Pointer to the guest-CPU context.
6144	* @param cbLikely The likely instruction length.
6145	*/
6146	DECLINLINE(uint8_t) hmR0SvmGetInstrLengthHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbLikely)
6147	{
6148	Assert(cbLikely <= 15); /* See Intel spec. 2.3.11 "AVX Instruction Length" */
6149	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6150	if (fSupportsNextRipSave)
6151	{
6152	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6153	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6154	Assert(cbInstr == cbLikely);
6155	return cbInstr;
6156	}
6157	return cbLikely;
6158	}
6159	#endif
6160
6161
6162	/**
6163	* Advances the guest RIP by the number of bytes specified in @a cb. This does
6164	* not make use of any hardware features to determine the instruction length.
6165	*
6166	* @param pVCpu The cross context virtual CPU structure.
6167	* @param pCtx Pointer to the guest-CPU context.
6168	* @param cb RIP increment value in bytes.
6169	*/
6170	DECLINLINE(void) hmR0SvmAdvanceRipDumb(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
6171	{
6172	pCtx->rip += cb;
6173	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
6174	}
6175	#undef HMSVM_UPDATE_INTR_SHADOW
6176
6177
6178	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
6179	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
6180	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
6181
6182	/** @name \#VMEXIT handlers.
6183	* @{
6184	*/
6185
6186	/**
6187	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
6188	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
6189	*/
6190	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6191	{
6192	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6193
6194	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
6195	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
6196	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
6197	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
6198
6199	/*
6200	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
6201	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
6202	* interrupt it is until the host actually take the interrupt.
6203	*
6204	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
6205	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
6206	*/
6207	return VINF_EM_RAW_INTERRUPT;
6208	}
6209
6210
6211	/**
6212	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
6213	*/
6214	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6215	{
6216	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6217
6218	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6219	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
6220	int rc = VINF_SUCCESS;
6221	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6222	return rc;
6223	}
6224
6225
6226	/**
6227	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
6228	*/
6229	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6230	{
6231	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6232
6233	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6234	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
6235	int rc = VINF_SUCCESS;
6236	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6237	return rc;
6238	}
6239
6240
6241	/**
6242	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
6243	*/
6244	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6245	{
6246	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6247	PVM pVM = pVCpu->CTX_SUFF(pVM);
6248	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6249	if (RT_LIKELY(rc == VINF_SUCCESS))
6250	{
6251	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6252	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6253	}
6254	else
6255	{
6256	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
6257	rc = VERR_EM_INTERPRETER;
6258	}
6259	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
6260	return rc;
6261	}
6262
6263
6264	/**
6265	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
6266	*/
6267	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6268	{
6269	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6270	PVM pVM = pVCpu->CTX_SUFF(pVM);
6271	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6272	if (RT_LIKELY(rc == VINF_SUCCESS))
6273	{
6274	pSvmTransient->fUpdateTscOffsetting = true;
6275	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6276	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6277	}
6278	else
6279	{
6280	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
6281	rc = VERR_EM_INTERPRETER;
6282	}
6283	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
6284	return rc;
6285	}
6286
6287
6288	/**
6289	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
6290	*/
6291	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6292	{
6293	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6294	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
6295	if (RT_LIKELY(rc == VINF_SUCCESS))
6296	{
6297	pSvmTransient->fUpdateTscOffsetting = true;
6298	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6299	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6300	}
6301	else
6302	{
6303	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
6304	rc = VERR_EM_INTERPRETER;
6305	}
6306	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
6307	return rc;
6308	}
6309
6310
6311	/**
6312	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
6313	*/
6314	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6315	{
6316	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6317	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6318	if (RT_LIKELY(rc == VINF_SUCCESS))
6319	{
6320	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6321	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6322	}
6323	else
6324	{
6325	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
6326	rc = VERR_EM_INTERPRETER;
6327	}
6328	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
6329	return rc;
6330	}
6331
6332
6333	/**
6334	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
6335	*/
6336	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6337	{
6338	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6339	PVM pVM = pVCpu->CTX_SUFF(pVM);
6340	Assert(!pVM->hm.s.fNestedPaging);
6341	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
6342
6343	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu, pCtx);
6344	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6345	if ( fSupportsDecodeAssists
6346	&& fSupportsNextRipSave)
6347	{
6348	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6349	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6350	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
6351	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
6352	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6353	return VBOXSTRICTRC_VAL(rcStrict);
6354	}
6355
6356	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, pCtx); /* Updates RIP if successful. */
6357	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
6358	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6359	return rc;
6360	}
6361
6362
6363	/**
6364	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
6365	*/
6366	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6367	{
6368	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6369
6370	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 1);
6371	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
6372	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6373	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
6374	if (rc != VINF_SUCCESS)
6375	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
6376	return rc;
6377	}
6378
6379
6380	/**
6381	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
6382	*/
6383	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6384	{
6385	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6386	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6387	if (RT_LIKELY(rc == VINF_SUCCESS))
6388	{
6389	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6390	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6391	}
6392	else
6393	{
6394	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
6395	rc = VERR_EM_INTERPRETER;
6396	}
6397	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
6398	return rc;
6399	}
6400
6401
6402	/**
6403	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
6404	*/
6405	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6406	{
6407	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6408	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
6409	int rc = VBOXSTRICTRC_VAL(rc2);
6410	if ( rc == VINF_EM_HALT
6411	\|\| rc == VINF_SUCCESS)
6412	{
6413	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
6414
6415	if ( rc == VINF_EM_HALT
6416	&& EMMonitorWaitShouldContinue(pVCpu, pCtx))
6417	{
6418	rc = VINF_SUCCESS;
6419	}
6420	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6421	}
6422	else
6423	{
6424	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
6425	rc = VERR_EM_INTERPRETER;
6426	}
6427	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
6428	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
6429	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
6430	return rc;
6431	}
6432
6433
6434	/**
6435	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
6436	* \#VMEXIT.
6437	*/
6438	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6439	{
6440	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6441	return VINF_EM_RESET;
6442	}
6443
6444
6445	/**
6446	* \#VMEXIT handler for unexpected exits. Conditional \#VMEXIT.
6447	*/
6448	HMSVM_EXIT_DECL hmR0SvmExitUnexpected(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6449	{
6450	RT_NOREF(pCtx);
6451	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6452	AssertMsgFailed(("hmR0SvmExitUnexpected: ExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", pSvmTransient->u64ExitCode,
6453	pVmcb->ctrl.u64ExitInfo1, pVmcb->ctrl.u64ExitInfo2));
6454	RT_NOREF(pVmcb);
6455	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6456	return VERR_SVM_UNEXPECTED_EXIT;
6457	}
6458
6459
6460	/**
6461	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
6462	*/
6463	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6464	{
6465	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6466
6467	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6468	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
6469
6470	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu, pCtx);
6471	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6472	if ( fSupportsDecodeAssists
6473	&& fSupportsNextRipSave)
6474	{
6475	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6476	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6477	if (fMovCRx)
6478	{
6479	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6480	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
6481	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6482	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
6483	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6484	return VBOXSTRICTRC_VAL(rcStrict);
6485	}
6486	/* else: SMSW instruction, fall back below to IEM for this. */
6487	}
6488
6489	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6490	int rc = VBOXSTRICTRC_VAL(rc2);
6491	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
6492	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
6493	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
6494	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6495	return rc;
6496	}
6497
6498
6499	/**
6500	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
6501	*/
6502	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6503	{
6504	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6505
6506	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0;
6507	Assert(iCrReg <= 15);
6508
6509	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
6510	bool fDecodedInstr = false;
6511	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu, pCtx);
6512	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6513	if ( fSupportsDecodeAssists
6514	&& fSupportsNextRipSave)
6515	{
6516	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6517	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6518	if (fMovCRx)
6519	{
6520	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6521	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6522	Log4(("hmR0SvmExitWriteCRx: Mov CR%u w/ iGReg=%#x\n", iCrReg, iGReg));
6523	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
6524	fDecodedInstr = true;
6525	}
6526	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
6527	}
6528
6529	if (!fDecodedInstr)
6530	{
6531	Log4(("hmR0SvmExitWriteCRx: iCrReg=%#x\n", iCrReg));
6532	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(pCtx), NULL);
6533	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
6534	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
6535	rcStrict = VERR_EM_INTERPRETER;
6536	}
6537
6538	if (rcStrict == VINF_SUCCESS)
6539	{
6540	switch (iCrReg)
6541	{
6542	case 0: /* CR0. */
6543	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
6544	break;
6545
6546	case 3: /* CR3. */
6547	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
6548	break;
6549
6550	case 4: /* CR4. */
6551	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
6552	break;
6553
6554	case 8: /* CR8 (TPR). */
6555	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6556	break;
6557
6558	default:
6559	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
6560	pSvmTransient->u64ExitCode, iCrReg));
6561	break;
6562	}
6563	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6564	}
6565	else
6566	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_CHANGE_MODE \|\| rcStrict == VINF_PGM_SYNC_CR3);
6567	return VBOXSTRICTRC_TODO(rcStrict);
6568	}
6569
6570
6571	/**
6572	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
6573	* \#VMEXIT.
6574	*/
6575	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6576	{
6577	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6578	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6579	PVM pVM = pVCpu->CTX_SUFF(pVM);
6580
6581	int rc;
6582	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
6583	{
6584	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
6585	Log4(("MSR Write: idMsr=%#RX32\n", pCtx->ecx));
6586
6587	/* Handle TPR patching; intercepted LSTAR write. */
6588	if ( pVM->hm.s.fTPRPatchingActive
6589	&& pCtx->ecx == MSR_K8_LSTAR)
6590	{
6591	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
6592	{
6593	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
6594	int rc2 = APICSetTpr(pVCpu, pCtx->eax & 0xff);
6595	AssertRC(rc2);
6596	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6597	}
6598	rc = VINF_SUCCESS;
6599	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
6600	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6601	return rc;
6602	}
6603
6604	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6605	if (fSupportsNextRipSave)
6606	{
6607	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6608	if (RT_LIKELY(rc == VINF_SUCCESS))
6609	{
6610	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6611	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6612	}
6613	else
6614	AssertMsg( rc == VERR_EM_INTERPRETER
6615	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
6616	}
6617	else
6618	{
6619	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
6620	if (RT_LIKELY(rc == VINF_SUCCESS))
6621	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc); /* RIP updated by EMInterpretInstruction(). */
6622	else
6623	AssertMsg( rc == VERR_EM_INTERPRETER
6624	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
6625	}
6626
6627	if (rc == VINF_SUCCESS)
6628	{
6629	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
6630	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
6631	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
6632	{
6633	/*
6634	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
6635	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
6636	* EMInterpretWrmsr() changes it.
6637	*/
6638	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
6639	}
6640	else
6641	{
6642	switch (pCtx->ecx)
6643	{
6644	case MSR_K6_EFER: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR); break;
6645	case MSR_IA32_TSC: pSvmTransient->fUpdateTscOffsetting = true; break;
6646	case MSR_K8_FS_BASE:
6647	case MSR_K8_GS_BASE: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS); break;
6648	case MSR_IA32_SYSENTER_CS: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_CS_MSR); break;
6649	case MSR_IA32_SYSENTER_EIP: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
6650	case MSR_IA32_SYSENTER_ESP: HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
6651	}
6652	}
6653	}
6654	}
6655	else
6656	{
6657	/* MSR Read access. */
6658	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
6659	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
6660	Log4(("MSR Read: idMsr=%#RX32\n", pCtx->ecx));
6661
6662	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6663	if (fSupportsNextRipSave)
6664	{
6665	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
6666	if (RT_LIKELY(rc == VINF_SUCCESS))
6667	{
6668	pCtx->rip = pVmcb->ctrl.u64NextRIP;
6669	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6670	}
6671	else
6672	AssertMsg( rc == VERR_EM_INTERPRETER
6673	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
6674	}
6675	else
6676	{
6677	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
6678	if (RT_UNLIKELY(rc != VINF_SUCCESS))
6679	{
6680	AssertMsg( rc == VERR_EM_INTERPRETER
6681	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
6682	}
6683	/* RIP updated by EMInterpretInstruction(). */
6684	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6685	}
6686	}
6687
6688	/* RIP has been updated by EMInterpret[Rd\|Wr]msr() or EMInterpretInstruction(). */
6689	return rc;
6690	}
6691
6692
6693	/**
6694	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
6695	*/
6696	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6697	{
6698	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6699	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
6700
6701	/** @todo Stepping with nested-guest. */
6702	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
6703	{
6704	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
6705	if (pSvmTransient->fWasGuestDebugStateActive)
6706	{
6707	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
6708	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6709	return VERR_SVM_UNEXPECTED_EXIT;
6710	}
6711
6712	/*
6713	* Lazy DR0-3 loading.
6714	*/
6715	if (!pSvmTransient->fWasHyperDebugStateActive)
6716	{
6717	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
6718	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
6719
6720	/* Don't intercept DRx read and writes. */
6721	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6722	pVmcb->ctrl.u16InterceptRdDRx = 0;
6723	pVmcb->ctrl.u16InterceptWrDRx = 0;
6724	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
6725
6726	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6727	VMMRZCallRing3Disable(pVCpu);
6728	HM_DISABLE_PREEMPT();
6729
6730	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
6731	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
6732	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
6733
6734	HM_RESTORE_PREEMPT();
6735	VMMRZCallRing3Enable(pVCpu);
6736
6737	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
6738	return VINF_SUCCESS;
6739	}
6740	}
6741
6742	/*
6743	* Interpret the read/writing of DRx.
6744	*/
6745	/** @todo Decode assist. */
6746	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6747	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
6748	if (RT_LIKELY(rc == VINF_SUCCESS))
6749	{
6750	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
6751	/** @todo CPUM should set this flag! */
6752	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
6753	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6754	}
6755	else
6756	Assert(rc == VERR_EM_INTERPRETER);
6757	return VBOXSTRICTRC_TODO(rc);
6758	}
6759
6760
6761	/**
6762	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
6763	*/
6764	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6765	{
6766	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6767	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
6768	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
6769	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
6770	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
6771	return rc;
6772	}
6773
6774
6775	/**
6776	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
6777	*/
6778	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6779	{
6780	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6781
6782	/** @todo decode assists... */
6783	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6784	if (rcStrict == VINF_IEM_RAISED_XCPT)
6785	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
6786
6787	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6788	Log4(("hmR0SvmExitXsetbv: New XCR0=%#RX64 fLoadSaveGuestXcr0=%d (cr4=%RX64) rcStrict=%Rrc\n",
6789	pCtx->aXcr[0], pVCpu->hm.s.fLoadSaveGuestXcr0, pCtx->cr4, VBOXSTRICTRC_VAL(rcStrict)));
6790
6791	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6792	return VBOXSTRICTRC_TODO(rcStrict);
6793	}
6794
6795
6796	/**
6797	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
6798	*/
6799	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
6800	{
6801	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
6802
6803	/* I/O operation lookup arrays. */
6804	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
6805	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
6806	the result (in AL/AX/EAX). */
6807	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6808
6809	PVM pVM = pVCpu->CTX_SUFF(pVM);
6810	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
6811
6812	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
6813	SVMIOIOEXITINFO IoExitInfo;
6814	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
6815	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
6816	uint32_t cbValue = s_aIOSize[uIOWidth];
6817	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
6818
6819	if (RT_UNLIKELY(!cbValue))
6820	{
6821	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
6822	return VERR_EM_INTERPRETER;
6823	}
6824
6825	VBOXSTRICTRC rcStrict;
6826	bool fUpdateRipAlready = false;
6827	if (IoExitInfo.n.u1STR)
6828	{
6829	#ifdef VBOX_WITH_2ND_IEM_STEP
6830	/* INS/OUTS - I/O String instruction. */
6831	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6832	* in EXITINFO1? Investigate once this thing is up and running. */
6833	Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
6834	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
6835	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
6836	static IEMMODE const s_aenmAddrMode[8] =
6837	{
6838	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
6839	};
6840	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
6841	if (enmAddrMode != (IEMMODE)-1)
6842	{
6843	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6844	if (cbInstr <= 15 && cbInstr >= 1)
6845	{
6846	Assert(cbInstr >= 1U + IoExitInfo.n.u1REP);
6847	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6848	{
6849	/* Don't know exactly how to detect whether u3SEG is valid, currently
6850	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
6851	2384 Opterons when only checking NRIP. */
6852	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu, pCtx);
6853	if ( fSupportsNextRipSave
6854	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
6855	{
6856	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1REP,
6857	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3SEG, cbInstr, IoExitInfo.n.u1REP));
6858	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6859	IoExitInfo.n.u3SEG, true /fIoChecked/);
6860	}
6861	else if (cbInstr == 1U + IoExitInfo.n.u1REP)
6862	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6863	X86_SREG_DS, true /fIoChecked/);
6864	else
6865	rcStrict = IEMExecOne(pVCpu);
6866	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6867	}
6868	else
6869	{
6870	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3SEG));
6871	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
6872	true /fIoChecked/);
6873	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6874	}
6875	}
6876	else
6877	{
6878	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
6879	rcStrict = IEMExecOne(pVCpu);
6880	}
6881	}
6882	else
6883	{
6884	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
6885	rcStrict = IEMExecOne(pVCpu);
6886	}
6887	fUpdateRipAlready = true;
6888
6889	#else
6890	/* INS/OUTS - I/O String instruction. */
6891	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
6892
6893	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6894	* in EXITINFO1? Investigate once this thing is up and running. */
6895
6896	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
6897	if (rcStrict == VINF_SUCCESS)
6898	{
6899	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6900	{
6901	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
6902	(DISCPUMODE)pDis->uAddrMode, cbValue);
6903	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
6904	}
6905	else
6906	{
6907	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
6908	(DISCPUMODE)pDis->uAddrMode, cbValue);
6909	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
6910	}
6911	}
6912	else
6913	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
6914	#endif
6915	}
6916	else
6917	{
6918	/* IN/OUT - I/O instruction. */
6919	Assert(!IoExitInfo.n.u1REP);
6920
6921	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6922	{
6923	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
6924	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
6925	}
6926	else
6927	{
6928	uint32_t u32Val = 0;
6929	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
6930	if (IOM_SUCCESS(rcStrict))
6931	{
6932	/* Save result of I/O IN instr. in AL/AX/EAX. */
6933	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
6934	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
6935	}
6936	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
6937	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
6938
6939	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
6940	}
6941	}
6942
6943	if (IOM_SUCCESS(rcStrict))
6944	{
6945	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
6946	if (!fUpdateRipAlready)
6947	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
6948
6949	/*
6950	* If any I/O breakpoints are armed, we need to check if one triggered
6951	* and take appropriate action.
6952	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
6953	*/
6954	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
6955	* execution engines about whether hyper BPs and such are pending. */
6956	uint32_t const uDr7 = pCtx->dr[7];
6957	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
6958	&& X86_DR7_ANY_RW_IO(uDr7)
6959	&& (pCtx->cr4 & X86_CR4_DE))
6960	\|\| DBGFBpIsHwIoArmed(pVM)))
6961	{
6962	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6963	VMMRZCallRing3Disable(pVCpu);
6964	HM_DISABLE_PREEMPT();
6965
6966	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
6967	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
6968
6969	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
6970	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
6971	{
6972	/* Raise #DB. */
6973	pVmcb->guest.u64DR6 = pCtx->dr[6];
6974	pVmcb->guest.u64DR7 = pCtx->dr[7];
6975	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
6976	hmR0SvmSetPendingXcptDB(pVCpu);
6977	}
6978	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
6979	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
6980	else if ( rcStrict2 != VINF_SUCCESS
6981	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
6982	rcStrict = rcStrict2;
6983	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
6984
6985	HM_RESTORE_PREEMPT();
6986	VMMRZCallRing3Enable(pVCpu);
6987	}
6988
6989	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6990	}
6991
6992	#ifdef VBOX_STRICT
6993	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
6994	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
6995	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE \|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE)
6996	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
6997	else
6998	{
6999	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
7000	* statuses, that the VMM device and some others may return. See
7001	* IOM_SUCCESS() for guidance. */
7002	AssertMsg( RT_FAILURE(rcStrict)
7003	\|\| rcStrict == VINF_SUCCESS
7004	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
7005	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
7006	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
7007	\|\| rcStrict == VINF_EM_RAW_TO_R3
7008	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED
7009	\|\| rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7010	}
7011	#endif
7012	return VBOXSTRICTRC_TODO(rcStrict);
7013	}
7014
7015
7016	/**
7017	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
7018	*/
7019	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7020	{
7021	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7022	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
7023
7024	PVM pVM = pVCpu->CTX_SUFF(pVM);
7025	Assert(pVM->hm.s.fNestedPaging);
7026
7027	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7028
7029	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
7030	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7031	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1; /** @todo Make it more explicit that high bits can be non-zero. */
7032	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
7033
7034	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
7035
7036	#ifdef VBOX_HM_WITH_GUEST_PATCHING
7037	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
7038	if ( pVM->hm.s.fTprPatchingAllowed
7039	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
7040	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
7041	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
7042	&& !CPUMIsGuestInLongModeEx(pCtx)
7043	&& !CPUMGetGuestCPL(pVCpu)
7044	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7045	{
7046	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7047	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7048
7049	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
7050	{
7051	/* Only attempt to patch the instruction once. */
7052	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7053	if (!pPatch)
7054	return VINF_EM_HM_PATCH_TPR_INSTR;
7055	}
7056	}
7057	#endif
7058
7059	/*
7060	* Determine the nested paging mode.
7061	*/
7062	PGMMODE enmNestedPagingMode;
7063	#if HC_ARCH_BITS == 32
7064	if (CPUMIsGuestInLongModeEx(pCtx))
7065	enmNestedPagingMode = PGMMODE_AMD64_NX;
7066	else
7067	#endif
7068	enmNestedPagingMode = PGMGetHostMode(pVM);
7069
7070	/*
7071	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
7072	*/
7073	int rc;
7074	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
7075	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
7076	{
7077	/* If event delivery causes an MMIO #NPF, go back to instruction emulation as
7078	otherwise injecting the original pending event would most likely cause the same MMIO #NPF. */
7079	if (pVCpu->hm.s.Event.fPending)
7080	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7081
7082	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
7083	u32ErrCode);
7084	rc = VBOXSTRICTRC_VAL(rc2);
7085
7086	/*
7087	* If we succeed, resume guest execution.
7088	* If we fail in interpreting the instruction because we couldn't get the guest physical address
7089	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
7090	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
7091	* weird case. See @bugref{6043}.
7092	*/
7093	if ( rc == VINF_SUCCESS
7094	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
7095	\|\| rc == VERR_PAGE_NOT_PRESENT)
7096	{
7097	/* Successfully handled MMIO operation. */
7098	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
7099	rc = VINF_SUCCESS;
7100	}
7101	return rc;
7102	}
7103
7104	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
7105	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
7106	TRPMResetTrap(pVCpu);
7107
7108	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
7109
7110	/*
7111	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
7112	*/
7113	if ( rc == VINF_SUCCESS
7114	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
7115	\|\| rc == VERR_PAGE_NOT_PRESENT)
7116	{
7117	/* We've successfully synced our shadow page tables. */
7118	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7119	rc = VINF_SUCCESS;
7120	}
7121
7122	return rc;
7123	}
7124
7125
7126	/**
7127	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
7128	* \#VMEXIT.
7129	*/
7130	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7131	{
7132	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7133	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
7134
7135	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7136	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7137	hmR0SvmClearVirtIntrIntercept(pVmcb);
7138
7139	/* Deliver the pending interrupt via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7140	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
7141	return VINF_SUCCESS;
7142	}
7143
7144
7145	/**
7146	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
7147	* \#VMEXIT.
7148	*/
7149	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7150	{
7151	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7152
7153	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7154
7155	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
7156	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
7157	#endif
7158
7159	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
7160	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
7161	{
7162	/*
7163	* AMD-V provides us with the exception which caused the TS; we collect
7164	* the information in the call to hmR0SvmCheckExitDueToEventDelivery.
7165	*/
7166	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery.\n"));
7167	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7168	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7169	}
7170
7171	/** @todo Emulate task switch someday, currently just going back to ring-3 for
7172	* emulation. */
7173	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7174	return VERR_EM_INTERPRETER;
7175	}
7176
7177
7178	/**
7179	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7180	*/
7181	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7182	{
7183	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7184	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmcall);
7185
7186	bool fRipUpdated;
7187	VBOXSTRICTRC rcStrict = HMSvmVmmcall(pVCpu, pCtx, &fRipUpdated);
7188	if (RT_SUCCESS(rcStrict))
7189	{
7190	/* Only update the RIP if we're continuing guest execution and not
7191	in the case of say VINF_GIM_R3_HYPERCALL. */
7192	if ( rcStrict == VINF_SUCCESS
7193	&& !fRipUpdated)
7194	{
7195	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3 /* cbInstr */);
7196	}
7197
7198	/* If the hypercall or TPR patching changes anything other than guest's general-purpose registers,
7199	we would need to reload the guest changed bits here before VM-entry. */
7200	return VBOXSTRICTRC_VAL(rcStrict);
7201	}
7202
7203	hmR0SvmSetPendingXcptUD(pVCpu);
7204	return VINF_SUCCESS;
7205	}
7206
7207
7208	/**
7209	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7210	*/
7211	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7212	{
7213	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7214	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPause);
7215	return VINF_EM_RAW_INTERRUPT;
7216	}
7217
7218
7219	/**
7220	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
7221	*/
7222	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7223	{
7224	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7225
7226	/* Clear NMI blocking. */
7227	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
7228
7229	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7230	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7231	hmR0SvmClearIretIntercept(pVmcb);
7232
7233	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7234	return VINF_SUCCESS;
7235	}
7236
7237
7238	/**
7239	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_14).
7240	* Conditional \#VMEXIT.
7241	*/
7242	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7243	{
7244	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7245	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
7246
7247	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7248
7249	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7250	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7251	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
7252	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7253	PVM pVM = pVCpu->CTX_SUFF(pVM);
7254
7255	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
7256	if (pVM->hm.s.fNestedPaging)
7257	{
7258	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7259	if (!pSvmTransient->fVectoringDoublePF)
7260	{
7261	/* A genuine guest #PF, reflect it to the guest. */
7262	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7263	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
7264	uFaultAddress, u32ErrCode));
7265	}
7266	else
7267	{
7268	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7269	hmR0SvmSetPendingXcptDF(pVCpu);
7270	Log4(("Pending #DF due to vectoring #PF. NP\n"));
7271	}
7272	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7273	return VINF_SUCCESS;
7274	}
7275	#endif
7276
7277	Assert(!pVM->hm.s.fNestedPaging);
7278
7279	#ifdef VBOX_HM_WITH_GUEST_PATCHING
7280	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
7281	if ( pVM->hm.s.fTprPatchingAllowed
7282	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
7283	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
7284	&& !CPUMIsGuestInLongModeEx(pCtx)
7285	&& !CPUMGetGuestCPL(pVCpu)
7286	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7287	{
7288	RTGCPHYS GCPhysApicBase;
7289	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7290	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7291
7292	/* Check if the page at the fault-address is the APIC base. */
7293	RTGCPHYS GCPhysPage;
7294	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
7295	if ( rc2 == VINF_SUCCESS
7296	&& GCPhysPage == GCPhysApicBase)
7297	{
7298	/* Only attempt to patch the instruction once. */
7299	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7300	if (!pPatch)
7301	return VINF_EM_HM_PATCH_TPR_INSTR;
7302	}
7303	}
7304	#endif
7305
7306	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7307	pCtx->rip, u32ErrCode, pCtx->cr3));
7308
7309	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
7310	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
7311	if (pSvmTransient->fVectoringPF)
7312	{
7313	Assert(pVCpu->hm.s.Event.fPending);
7314	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7315	}
7316
7317	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
7318	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7319
7320	Log4(("#PF rc=%Rrc\n", rc));
7321
7322	if (rc == VINF_SUCCESS)
7323	{
7324	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7325	TRPMResetTrap(pVCpu);
7326	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7327	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7328	return rc;
7329	}
7330	else if (rc == VINF_EM_RAW_GUEST_TRAP)
7331	{
7332	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7333
7334	if (!pSvmTransient->fVectoringDoublePF)
7335	{
7336	/* It's a guest page fault and needs to be reflected to the guest. */
7337	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7338	TRPMResetTrap(pVCpu);
7339	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7340	}
7341	else
7342	{
7343	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7344	TRPMResetTrap(pVCpu);
7345	hmR0SvmSetPendingXcptDF(pVCpu);
7346	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
7347	}
7348
7349	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7350	return VINF_SUCCESS;
7351	}
7352
7353	TRPMResetTrap(pVCpu);
7354	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7355	return rc;
7356	}
7357
7358
7359	/**
7360	* \#VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
7361	* Conditional \#VMEXIT.
7362	*/
7363	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7364	{
7365	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7366
7367	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7368	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7369	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7370
7371	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
7372	VMMRZCallRing3Disable(pVCpu);
7373	HM_DISABLE_PREEMPT();
7374
7375	int rc;
7376	/* If the guest FPU was active at the time of the #NM exit, then it's a guest fault. */
7377	if (pSvmTransient->fWasGuestFPUStateActive)
7378	{
7379	rc = VINF_EM_RAW_GUEST_TRAP;
7380	Assert(CPUMIsGuestFPUStateActive(pVCpu) \|\| HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
7381	}
7382	else
7383	{
7384	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
7385	Assert(!pSvmTransient->fWasGuestFPUStateActive);
7386	#endif
7387	rc = CPUMR0Trap07Handler(pVCpu->CTX_SUFF(pVM), pVCpu); /* (No need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
7388	Assert( rc == VINF_EM_RAW_GUEST_TRAP
7389	\|\| ((rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED) && CPUMIsGuestFPUStateActive(pVCpu)));
7390	}
7391
7392	HM_RESTORE_PREEMPT();
7393	VMMRZCallRing3Enable(pVCpu);
7394
7395	if (rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED)
7396	{
7397	/* Guest FPU state was activated, we'll want to change CR0 FPU intercepts before the next VM-reentry. */
7398	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
7399	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
7400	pVCpu->hm.s.fPreloadGuestFpu = true;
7401	}
7402	else
7403	{
7404	/* Forward #NM to the guest. */
7405	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
7406	hmR0SvmSetPendingXcptNM(pVCpu);
7407	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
7408	}
7409	return VINF_SUCCESS;
7410	}
7411
7412
7413	/**
7414	* \#VMEXIT handler for undefined opcode (SVM_EXIT_EXCEPTION_6).
7415	* Conditional \#VMEXIT.
7416	*/
7417	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7418	{
7419	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7420
7421	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7422	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7423	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7424
7425	int rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7426	if (pVCpu->hm.s.fGIMTrapXcptUD)
7427	{
7428	uint8_t cbInstr = 0;
7429	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, pCtx, NULL /* pDis */, &cbInstr);
7430	if (rcStrict == VINF_SUCCESS)
7431	{
7432	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
7433	hmR0SvmAdvanceRipDumb(pVCpu, pCtx, cbInstr);
7434	rc = VINF_SUCCESS;
7435	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
7436	}
7437	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
7438	rc = VINF_SUCCESS;
7439	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
7440	rc = VINF_GIM_R3_HYPERCALL;
7441	else
7442	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
7443	}
7444
7445	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
7446	if (RT_FAILURE(rc))
7447	{
7448	hmR0SvmSetPendingXcptUD(pVCpu);
7449	rc = VINF_SUCCESS;
7450	}
7451
7452	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7453	return rc;
7454	}
7455
7456
7457	/**
7458	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_16).
7459	* Conditional \#VMEXIT.
7460	*/
7461	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7462	{
7463	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7464
7465	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7466	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7467	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7468
7469	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7470
7471	if (!(pCtx->cr0 & X86_CR0_NE))
7472	{
7473	PVM pVM = pVCpu->CTX_SUFF(pVM);
7474	PDISSTATE pDis = &pVCpu->hm.s.DisState;
7475	unsigned cbOp;
7476	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
7477	if (RT_SUCCESS(rc))
7478	{
7479	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
7480	/** @todo FERR intercept when in nested-guest mode? */
7481	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
7482	if (RT_SUCCESS(rc))
7483	pCtx->rip += cbOp;
7484	}
7485	else
7486	Log4(("hmR0SvmExitXcptMF: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
7487	return rc;
7488	}
7489
7490	hmR0SvmSetPendingXcptMF(pVCpu);
7491	return VINF_SUCCESS;
7492	}
7493
7494
7495	/**
7496	* \#VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
7497	* \#VMEXIT.
7498	*/
7499	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7500	{
7501	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7502
7503	/* If this #DB is the result of delivering an event, go back to the interpreter. */
7504	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7505	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7506	{
7507	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7508	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7509	}
7510
7511	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7512
7513	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
7514	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
7515	PVM pVM = pVCpu->CTX_SUFF(pVM);
7516	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7517	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
7518	if (rc == VINF_EM_RAW_GUEST_TRAP)
7519	{
7520	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
7521	if (CPUMIsHyperDebugStateActive(pVCpu))
7522	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
7523
7524	/* Reflect the exception back to the guest. */
7525	hmR0SvmSetPendingXcptDB(pVCpu);
7526	rc = VINF_SUCCESS;
7527	}
7528
7529	/*
7530	* Update DR6.
7531	*/
7532	if (CPUMIsHyperDebugStateActive(pVCpu))
7533	{
7534	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
7535	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
7536	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7537	}
7538	else
7539	{
7540	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
7541	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
7542	}
7543
7544	return rc;
7545	}
7546
7547
7548	/**
7549	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_EXCEPTION_17).
7550	* Conditional \#VMEXIT.
7551	*/
7552	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7553	{
7554	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7555
7556	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7557	* shutdown VMEXIT. */
7558	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7559
7560	SVMEVENT Event;
7561	Event.u = 0;
7562	Event.n.u1Valid = 1;
7563	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7564	Event.n.u8Vector = X86_XCPT_AC;
7565	Event.n.u1ErrorCodeValid = 1;
7566	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7567	return VINF_SUCCESS;
7568	}
7569
7570
7571	/**
7572	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_EXCEPTION_3).
7573	* Conditional \#VMEXIT.
7574	*/
7575	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7576	{
7577	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7578
7579	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7580
7581	int rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
7582	if (rc == VINF_EM_RAW_GUEST_TRAP)
7583	{
7584	SVMEVENT Event;
7585	Event.u = 0;
7586	Event.n.u1Valid = 1;
7587	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7588	Event.n.u8Vector = X86_XCPT_BP;
7589	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7590	}
7591
7592	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_EM_DBG_BREAKPOINT);
7593	return rc;
7594	}
7595
7596
7597	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT)
7598	/**
7599	* \#VMEXIT handler for generic exceptions. Conditional \#VMEXIT.
7600	*/
7601	HMSVM_EXIT_DECL hmR0SvmExitXcptGeneric(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7602	{
7603	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7604
7605	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7606
7607	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7608	uint8_t const uVector = pVmcb->ctrl.u64ExitCode - SVM_EXIT_EXCEPTION_0;
7609	uint32_t const uErrCode = pVmcb->ctrl.u64ExitInfo1;
7610	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7611	Assert(uVector <= X86_XCPT_LAST);
7612	Log4(("hmR0SvmExitXcptGeneric: uVector=%#x uErrCode=%u\n", uVector, uErrCode));
7613
7614	SVMEVENT Event;
7615	Event.u = 0;
7616	Event.n.u1Valid = 1;
7617	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7618	Event.n.u8Vector = uVector;
7619	switch (uVector)
7620	{
7621	/* Shouldn't be here for reflecting #PFs (among other things, the fault address isn't passed along). */
7622	case X86_XCPT_PF: AssertMsgFailed(("hmR0SvmExitXcptGeneric: Unexpected exception")); return VERR_SVM_IPE_5;
7623	case X86_XCPT_DF:
7624	case X86_XCPT_TS:
7625	case X86_XCPT_NP:
7626	case X86_XCPT_SS:
7627	case X86_XCPT_GP:
7628	case X86_XCPT_AC:
7629	{
7630	Event.n.u1ErrorCodeValid = 1;
7631	Event.n.u32ErrorCode = uErrCode;
7632	break;
7633	}
7634	}
7635
7636	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7637	return VINF_SUCCESS;
7638	}
7639	#endif
7640
7641	#ifdef VBOX_WITH_NESTED_HWVIRT
7642	/**
7643	* \#VMEXIT handler for #PF occuring while in nested-guest execution
7644	* (SVM_EXIT_EXCEPTION_14). Conditional \#VMEXIT.
7645	*/
7646	HMSVM_EXIT_DECL hmR0SvmExitXcptPFNested(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7647	{
7648	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7649
7650	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7651
7652	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7653	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7654	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
7655	uint64_t const uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7656
7657	Log4(("#PFNested: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode=%#RX32 CR3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7658	pCtx->rip, u32ErrCode, pCtx->cr3));
7659
7660	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
7661	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
7662	if (pSvmTransient->fVectoringPF)
7663	{
7664	Assert(pVCpu->hm.s.Event.fPending);
7665	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7666	}
7667
7668	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
7669
7670	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
7671	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7672
7673	Log4(("#PFNested: rc=%Rrc\n", rc));
7674
7675	if (rc == VINF_SUCCESS)
7676	{
7677	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7678	TRPMResetTrap(pVCpu);
7679	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7680	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7681	return rc;
7682	}
7683
7684	if (rc == VINF_EM_RAW_GUEST_TRAP)
7685	{
7686	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7687
7688	if (!pSvmTransient->fVectoringDoublePF)
7689	{
7690	/* It's a nested-guest page fault and needs to be reflected to the nested-guest. */
7691	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7692	TRPMResetTrap(pVCpu);
7693	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
7694	}
7695	else
7696	{
7697	/* A nested-guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7698	TRPMResetTrap(pVCpu);
7699	hmR0SvmSetPendingXcptDF(pVCpu);
7700	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
7701	}
7702
7703	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7704	return VINF_SUCCESS;
7705	}
7706
7707	TRPMResetTrap(pVCpu);
7708	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7709	return rc;
7710	}
7711
7712
7713	/**
7714	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
7715	*/
7716	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7717	{
7718	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7719
7720	#ifdef VBOX_STRICT
7721	PCSVMVMCB pVmcbTmp = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7722	Assert(pVmcbTmp);
7723	Assert(!pVmcbTmp->ctrl.IntCtrl.n.u1VGifEnable);
7724	RT_NOREF(pVmcbTmp);
7725	#endif
7726
7727	/** @todo Stat. */
7728	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClgi); */
7729	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7730	VBOXSTRICTRC rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
7731	return VBOXSTRICTRC_VAL(rcStrict);
7732	}
7733
7734
7735	/**
7736	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
7737	*/
7738	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7739	{
7740	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7741
7742	#ifdef VBOX_STRICT
7743	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7744	Assert(pVmcb);
7745	Assert(!pVmcb->ctrl.IntCtrl.n.u1VGifEnable);
7746	RT_NOREF(pVmcb);
7747	#endif
7748
7749	/** @todo Stat. */
7750	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitStgi); */
7751	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7752	VBOXSTRICTRC rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
7753	return VBOXSTRICTRC_VAL(rcStrict);
7754	}
7755
7756
7757	/**
7758	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
7759	*/
7760	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7761	{
7762	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7763
7764	#ifdef VBOX_STRICT
7765	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7766	Assert(pVmcb);
7767	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7768	RT_NOREF(pVmcb);
7769	#endif
7770
7771	/** @todo Stat. */
7772	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmload); */
7773	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7774	VBOXSTRICTRC rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
7775	if (rcStrict == VINF_SUCCESS)
7776	{
7777	/* We skip flagging changes made to LSTAR, STAR, SFMASK and other MSRs as they are always re-loaded. */
7778	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS
7779	\| HM_CHANGED_GUEST_TR
7780	\| HM_CHANGED_GUEST_LDTR);
7781	}
7782	return VBOXSTRICTRC_VAL(rcStrict);
7783	}
7784
7785
7786	/**
7787	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
7788	*/
7789	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7790	{
7791	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7792
7793	#ifdef VBOX_STRICT
7794	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu, pCtx);
7795	Assert(pVmcb);
7796	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7797	RT_NOREF(pVmcb);
7798	#endif
7799
7800	/** @todo Stat. */
7801	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmsave); */
7802	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7803	VBOXSTRICTRC rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
7804	return VBOXSTRICTRC_VAL(rcStrict);
7805	}
7806
7807
7808	/**
7809	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
7810	*/
7811	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7812	{
7813	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7814	/** @todo Stat. */
7815	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpga); */
7816	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7817	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
7818	return VBOXSTRICTRC_VAL(rcStrict);
7819	}
7820
7821
7822	/**
7823	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
7824	*/
7825	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7826	{
7827	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7828	/** @todo Stat. */
7829	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmrun); */
7830	#if 0
7831	VBOXSTRICTRC rcStrict;
7832	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
7833	rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
7834	Log4(("IEMExecDecodedVmrun: returned %d\n", VBOXSTRICTRC_VAL(rcStrict)));
7835	if (rcStrict == VINF_SUCCESS)
7836	{
7837	rcStrict = VINF_SVM_VMRUN;
7838	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
7839	}
7840	return VBOXSTRICTRC_VAL(rcStrict);
7841	#endif
7842	return VERR_EM_INTERPRETER;
7843	}
7844
7845
7846	/**
7847	* Nested-guest \#VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1).
7848	* Unconditional \#VMEXIT.
7849	*/
7850	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7851	{
7852	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7853
7854	/* If this #DB is the result of delivering an event, go back to the interpreter. */
7855	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7856	* shutdown VMEXIT. */
7857	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7858	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7859	{
7860	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7861	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7862	}
7863
7864	hmR0SvmSetPendingXcptDB(pVCpu);
7865	return VINF_SUCCESS;
7866	}
7867
7868
7869	/**
7870	* Nested-guest \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_EXCEPTION_3).
7871	* Conditional \#VMEXIT.
7872	*/
7873	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
7874	{
7875	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
7876
7877	/** @todo if triple-fault is returned in nested-guest scenario convert to a
7878	* shutdown VMEXIT. */
7879	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
7880
7881	SVMEVENT Event;
7882	Event.u = 0;
7883	Event.n.u1Valid = 1;
7884	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7885	Event.n.u8Vector = X86_XCPT_BP;
7886	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7887	return VINF_SUCCESS;
7888	}
7889
7890	#endif /* VBOX_WITH_NESTED_HWVIRT */
7891
7892
7893	/** @} */
7894

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 71312

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