HMSVMR0.cpp@ 67837

Last change on this file since 67837 was 67662, checked in by vboxsync, 7 years ago
VMM/HMSVMR0: msc warning.
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1	/* $Id: HMSVMR0.cpp 67662 2017-06-28 10:26:17Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <iprt/asm-amd64-x86.h>
24	#include <iprt/thread.h>
25
26	#include <VBox/vmm/pdmapi.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/iem.h>
29	#include <VBox/vmm/iom.h>
30	#include <VBox/vmm/tm.h>
31	#include <VBox/vmm/gim.h>
32	#include <VBox/vmm/apic.h>
33	#include "HMInternal.h"
34	#include <VBox/vmm/vm.h>
35	#include "HMSVMR0.h"
36	#include "dtrace/VBoxVMM.h"
37
38	#define HMSVM_USE_IEM_EVENT_REFLECTION
39	#ifdef DEBUG_ramshankar
40	# define HMSVM_SYNC_FULL_GUEST_STATE
41	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
42	# define HMSVM_ALWAYS_TRAP_PF
43	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
44	#endif
45
46
47	/*********************************************************************************************************************************
48	* Defined Constants And Macros *
49	*********************************************************************************************************************************/
50	#ifdef VBOX_WITH_STATISTICS
51	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
52	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
53	if ((u64ExitCode) == SVM_EXIT_NPF) \
54	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
55	else \
56	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
57	} while (0)
58	#else
59	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
60	#endif
61
62	/** If we decide to use a function table approach this can be useful to
63	* switch to a "static DECLCALLBACK(int)". */
64	#define HMSVM_EXIT_DECL static int
65
66	/** Macro for checking and returning from the using function for
67	* \#VMEXIT intercepts that maybe caused during delivering of another
68	* event in the guest. */
69	#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
70	do \
71	{ \
72	int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
73	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* likely */ } \
74	else if (rc == VINF_HM_DOUBLE_FAULT) \
75	return VINF_SUCCESS; \
76	else \
77	return rc; \
78	} while (0)
79
80	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
81	* instruction that exited. */
82	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
83	do { \
84	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
85	(a_rc) = VINF_EM_DBG_STEPPED; \
86	} while (0)
87
88	/** Assert that preemption is disabled or covered by thread-context hooks. */
89	#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
90	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
91
92	/** Assert that we haven't migrated CPUs when thread-context hooks are not
93	* used. */
94	#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHookIsEnabled(pVCpu) \
95	\|\| pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
96	("Illegal migration! Entered on CPU %u Current %u\n", \
97	pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
98
99	/** Exception bitmap mask for all contributory exceptions.
100	*
101	* Page fault is deliberately excluded here as it's conditional as to whether
102	* it's contributory or benign. Page faults are handled separately.
103	*/
104	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
105	\| RT_BIT(X86_XCPT_DE))
106
107	/** @name VMCB Clean Bits.
108	*
109	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
110	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
111	* memory.
112	*
113	* @{ */
114	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
115	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
116	/** I/O permission bitmap, MSR permission bitmap. */
117	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
118	/** ASID. */
119	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
120	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
121	V_INTR_VECTOR. */
122	#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
123	/** Nested Paging: Nested CR3 (nCR3), PAT. */
124	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
125	/** Control registers (CR0, CR3, CR4, EFER). */
126	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
127	/** Debug registers (DR6, DR7). */
128	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
129	/** GDT, IDT limit and base. */
130	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
131	/** Segment register: CS, SS, DS, ES limit and base. */
132	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
133	/** CR2.*/
134	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
135	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
136	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
137	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
138	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
139	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
140	/** Mask of all valid VMCB Clean bits. */
141	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
142	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
143	\| HMSVM_VMCB_CLEAN_ASID \
144	\| HMSVM_VMCB_CLEAN_TPR \
145	\| HMSVM_VMCB_CLEAN_NP \
146	\| HMSVM_VMCB_CLEAN_CRX_EFER \
147	\| HMSVM_VMCB_CLEAN_DRX \
148	\| HMSVM_VMCB_CLEAN_DT \
149	\| HMSVM_VMCB_CLEAN_SEG \
150	\| HMSVM_VMCB_CLEAN_CR2 \
151	\| HMSVM_VMCB_CLEAN_LBR \
152	\| HMSVM_VMCB_CLEAN_AVIC)
153	/** @} */
154
155	/** @name SVM transient.
156	*
157	* A state structure for holding miscellaneous information across AMD-V
158	* VMRUN/\#VMEXIT operation, restored after the transition.
159	*
160	* @{ */
161	typedef struct SVMTRANSIENT
162	{
163	/** The host's rflags/eflags. */
164	RTCCUINTREG fEFlags;
165	#if HC_ARCH_BITS == 32
166	uint32_t u32Alignment0;
167	#endif
168
169	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
170	uint64_t u64ExitCode;
171	/** The guest's TPR value used for TPR shadowing. */
172	uint8_t u8GuestTpr;
173	/** Alignment. */
174	uint8_t abAlignment0[7];
175
176	/** Whether the guest FPU state was active at the time of \#VMEXIT. */
177	bool fWasGuestFPUStateActive;
178	/** Whether the guest debug state was active at the time of \#VMEXIT. */
179	bool fWasGuestDebugStateActive;
180	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
181	bool fWasHyperDebugStateActive;
182	/** Whether the TSC offset mode needs to be updated. */
183	bool fUpdateTscOffsetting;
184	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
185	bool fRestoreTscAuxMsr;
186	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
187	* contributary exception or a page-fault. */
188	bool fVectoringDoublePF;
189	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
190	* external interrupt or NMI. */
191	bool fVectoringPF;
192	} SVMTRANSIENT, *PSVMTRANSIENT;
193	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
194	AssertCompileMemberAlignment(SVMTRANSIENT, fWasGuestFPUStateActive, sizeof(uint64_t));
195	/** @} */
196
197	/**
198	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
199	*/
200	typedef enum SVMMSREXITREAD
201	{
202	/** Reading this MSR causes a \#VMEXIT. */
203	SVMMSREXIT_INTERCEPT_READ = 0xb,
204	/** Reading this MSR does not cause a \#VMEXIT. */
205	SVMMSREXIT_PASSTHRU_READ
206	} SVMMSREXITREAD;
207
208	/**
209	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
210	*/
211	typedef enum SVMMSREXITWRITE
212	{
213	/** Writing to this MSR causes a \#VMEXIT. */
214	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
215	/** Writing to this MSR does not cause a \#VMEXIT. */
216	SVMMSREXIT_PASSTHRU_WRITE
217	} SVMMSREXITWRITE;
218
219	/**
220	* SVM \#VMEXIT handler.
221	*
222	* @returns VBox status code.
223	* @param pVCpu The cross context virtual CPU structure.
224	* @param pMixedCtx Pointer to the guest-CPU context.
225	* @param pSvmTransient Pointer to the SVM-transient structure.
226	*/
227	typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
228
229
230	/*********************************************************************************************************************************
231	* Internal Functions *
232	*********************************************************************************************************************************/
233	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite);
234	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
235	static void hmR0SvmLeave(PVMCPU pVCpu);
236
237	/** @name \#VMEXIT handlers.
238	* @{
239	*/
240	static FNSVMEXITHANDLER hmR0SvmExitIntr;
241	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
242	static FNSVMEXITHANDLER hmR0SvmExitInvd;
243	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
244	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
245	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
246	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
247	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
248	static FNSVMEXITHANDLER hmR0SvmExitHlt;
249	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
250	static FNSVMEXITHANDLER hmR0SvmExitMwait;
251	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
252	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
253	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
254	static FNSVMEXITHANDLER hmR0SvmExitSetPendingXcptUD;
255	static FNSVMEXITHANDLER hmR0SvmExitMsr;
256	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
257	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
258	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
259	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
260	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
261	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
262	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
263	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
264	static FNSVMEXITHANDLER hmR0SvmExitPause;
265	static FNSVMEXITHANDLER hmR0SvmExitIret;
266	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
267	static FNSVMEXITHANDLER hmR0SvmExitXcptNM;
268	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
269	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
270	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
271	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
272	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
273	#ifdef VBOX_WITH_NESTED_HWVIRT
274	static FNSVMEXITHANDLER hmR0SvmExitClgi;
275	static FNSVMEXITHANDLER hmR0SvmExitStgi;
276	static FNSVMEXITHANDLER hmR0SvmExitVmload;
277	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
278	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
279	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
280	#endif
281	/** @} */
282
283	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
284
285
286	/*********************************************************************************************************************************
287	* Global Variables *
288	*********************************************************************************************************************************/
289	/** Ring-0 memory object for the IO bitmap. */
290	RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
291	/** Physical address of the IO bitmap. */
292	RTHCPHYS g_HCPhysIOBitmap = 0;
293	/** Virtual address of the IO bitmap. */
294	R0PTRTYPE(void *) g_pvIOBitmap = NULL;
295
296
297	/**
298	* Sets up and activates AMD-V on the current CPU.
299	*
300	* @returns VBox status code.
301	* @param pCpu Pointer to the CPU info struct.
302	* @param pVM The cross context VM structure. Can be
303	* NULL after a resume!
304	* @param pvCpuPage Pointer to the global CPU page.
305	* @param HCPhysCpuPage Physical address of the global CPU page.
306	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
307	* @param pvArg Unused on AMD-V.
308	*/
309	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
310	void *pvArg)
311	{
312	Assert(!fEnabledByHost);
313	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
314	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
315	Assert(pvCpuPage); NOREF(pvCpuPage);
316	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
317
318	NOREF(pvArg);
319	NOREF(fEnabledByHost);
320
321	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
322	RTCCUINTREG fEFlags = ASMIntDisableFlags();
323
324	/*
325	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
326	*/
327	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
328	if (u64HostEfer & MSR_K6_EFER_SVME)
329	{
330	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
331	if ( pVM
332	&& pVM->hm.s.svm.fIgnoreInUseError)
333	{
334	pCpu->fIgnoreAMDVInUseError = true;
335	}
336
337	if (!pCpu->fIgnoreAMDVInUseError)
338	{
339	ASMSetFlags(fEFlags);
340	return VERR_SVM_IN_USE;
341	}
342	}
343
344	/* Turn on AMD-V in the EFER MSR. */
345	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
346
347	/* Write the physical page address where the CPU will store the host state while executing the VM. */
348	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
349
350	/* Restore interrupts. */
351	ASMSetFlags(fEFlags);
352
353	/*
354	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
355	* when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
356	* upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
357	* to flush the TLB with before using a new ASID.
358	*/
359	pCpu->fFlushAsidBeforeUse = true;
360
361	/*
362	* Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
363	*/
364	++pCpu->cTlbFlushes;
365
366	return VINF_SUCCESS;
367	}
368
369
370	/**
371	* Deactivates AMD-V on the current CPU.
372	*
373	* @returns VBox status code.
374	* @param pCpu Pointer to the CPU info struct.
375	* @param pvCpuPage Pointer to the global CPU page.
376	* @param HCPhysCpuPage Physical address of the global CPU page.
377	*/
378	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
379	{
380	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
381	AssertReturn( HCPhysCpuPage
382	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
383	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
384	NOREF(pCpu);
385
386	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
387	RTCCUINTREG fEFlags = ASMIntDisableFlags();
388
389	/* Turn off AMD-V in the EFER MSR. */
390	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
391	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
392
393	/* Invalidate host state physical address. */
394	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
395
396	/* Restore interrupts. */
397	ASMSetFlags(fEFlags);
398
399	return VINF_SUCCESS;
400	}
401
402
403	/**
404	* Does global AMD-V initialization (called during module initialization).
405	*
406	* @returns VBox status code.
407	*/
408	VMMR0DECL(int) SVMR0GlobalInit(void)
409	{
410	/*
411	* Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
412	* once globally here instead of per-VM.
413	*/
414	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
415	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
416	if (RT_FAILURE(rc))
417	return rc;
418
419	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
420	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
421
422	/* Set all bits to intercept all IO accesses. */
423	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
424	return VINF_SUCCESS;
425	}
426
427
428	/**
429	* Does global AMD-V termination (called during module termination).
430	*/
431	VMMR0DECL(void) SVMR0GlobalTerm(void)
432	{
433	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
434	{
435	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
436	g_pvIOBitmap = NULL;
437	g_HCPhysIOBitmap = 0;
438	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
439	}
440	}
441
442
443	/**
444	* Frees any allocated per-VCPU structures for a VM.
445	*
446	* @param pVM The cross context VM structure.
447	*/
448	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
449	{
450	for (uint32_t i = 0; i < pVM->cCpus; i++)
451	{
452	PVMCPU pVCpu = &pVM->aCpus[i];
453	AssertPtr(pVCpu);
454
455	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
456	{
457	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
458	pVCpu->hm.s.svm.pvVmcbHost = 0;
459	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
460	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
461	}
462
463	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
464	{
465	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
466	pVCpu->hm.s.svm.pvVmcb = 0;
467	pVCpu->hm.s.svm.HCPhysVmcb = 0;
468	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
469	}
470
471	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
472	{
473	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
474	pVCpu->hm.s.svm.pvMsrBitmap = 0;
475	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
476	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
477	}
478	}
479	}
480
481
482	/**
483	* Does per-VM AMD-V initialization.
484	*
485	* @returns VBox status code.
486	* @param pVM The cross context VM structure.
487	*/
488	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
489	{
490	int rc = VERR_INTERNAL_ERROR_5;
491
492	/*
493	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
494	*/
495	uint32_t u32Family;
496	uint32_t u32Model;
497	uint32_t u32Stepping;
498	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
499	{
500	Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
501	pVM->hm.s.svm.fAlwaysFlushTLB = true;
502	}
503
504	/*
505	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
506	*/
507	for (VMCPUID i = 0; i < pVM->cCpus; i++)
508	{
509	PVMCPU pVCpu = &pVM->aCpus[i];
510	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
511	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
512	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
513	}
514
515	for (VMCPUID i = 0; i < pVM->cCpus; i++)
516	{
517	PVMCPU pVCpu = &pVM->aCpus[i];
518
519	/*
520	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
521	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
522	*/
523	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
524	if (RT_FAILURE(rc))
525	goto failure_cleanup;
526
527	pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
528	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
529	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
530	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
531
532	/*
533	* Allocate one page for the guest-state VMCB.
534	*/
535	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
536	if (RT_FAILURE(rc))
537	goto failure_cleanup;
538
539	pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
540	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
541	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
542	ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
543
544	/*
545	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
546	* SVM to not require one.
547	*/
548	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
549	false /* fExecutable */);
550	if (RT_FAILURE(rc))
551	goto failure_cleanup;
552
553	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
554	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
555	/* Set all bits to intercept all MSR accesses (changed later on). */
556	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
557	}
558
559	return VINF_SUCCESS;
560
561	failure_cleanup:
562	hmR0SvmFreeStructs(pVM);
563	return rc;
564	}
565
566
567	/**
568	* Does per-VM AMD-V termination.
569	*
570	* @returns VBox status code.
571	* @param pVM The cross context VM structure.
572	*/
573	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
574	{
575	hmR0SvmFreeStructs(pVM);
576	return VINF_SUCCESS;
577	}
578
579
580	/**
581	* Sets the permission bits for the specified MSR in the MSRPM.
582	*
583	* @param pVCpu The cross context virtual CPU structure.
584	* @param uMsr The MSR for which the access permissions are being set.
585	* @param enmRead MSR read permissions.
586	* @param enmWrite MSR write permissions.
587	*/
588	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite)
589	{
590	uint16_t offMsrpm;
591	uint32_t uMsrpmBit;
592	int rc = HMSvmGetMsrpmOffsetAndBit(uMsr, &offMsrpm, &uMsrpmBit);
593	AssertRC(rc);
594
595	Assert(uMsrpmBit < 0x3fff);
596	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
597
598	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
599	pbMsrBitmap += offMsrpm;
600
601	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
602	ASMBitSet(pbMsrBitmap, uMsrpmBit);
603	else
604	ASMBitClear(pbMsrBitmap, uMsrpmBit);
605
606	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
607	ASMBitSet(pbMsrBitmap, uMsrpmBit + 1);
608	else
609	ASMBitClear(pbMsrBitmap, uMsrpmBit + 1);
610
611	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
612	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
613	}
614
615
616	/**
617	* Sets up AMD-V for the specified VM.
618	* This function is only called once per-VM during initalization.
619	*
620	* @returns VBox status code.
621	* @param pVM The cross context VM structure.
622	*/
623	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
624	{
625	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
626	AssertReturn(pVM, VERR_INVALID_PARAMETER);
627	Assert(pVM->hm.s.svm.fSupported);
628
629	bool const fPauseFilter = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
630	bool const fPauseFilterThreshold = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
631	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter && pVM->hm.s.svm.cPauseFilterThresholdTicks;
632
633	for (VMCPUID i = 0; i < pVM->cCpus; i++)
634	{
635	PVMCPU pVCpu = &pVM->aCpus[i];
636	PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
637
638	AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
639
640	/* Initialize the #VMEXIT history array with end-of-array markers (UINT16_MAX). */
641	Assert(!pVCpu->hm.s.idxExitHistoryFree);
642	HMCPU_EXIT_HISTORY_RESET(pVCpu);
643
644	/* Always trap #AC for reasons of security. */
645	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
646
647	/* Always trap #DB for reasons of security. */
648	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
649
650	/* Trap exceptions unconditionally (debug purposes). */
651	#ifdef HMSVM_ALWAYS_TRAP_PF
652	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
653	#endif
654	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
655	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
656	pVmcb->ctrl.u32InterceptXcpt \|= 0
657	\| RT_BIT(X86_XCPT_BP)
658	\| RT_BIT(X86_XCPT_DE)
659	\| RT_BIT(X86_XCPT_NM)
660	\| RT_BIT(X86_XCPT_UD)
661	\| RT_BIT(X86_XCPT_NP)
662	\| RT_BIT(X86_XCPT_SS)
663	\| RT_BIT(X86_XCPT_GP)
664	\| RT_BIT(X86_XCPT_PF)
665	\| RT_BIT(X86_XCPT_MF)
666	;
667	#endif
668
669	/* Set up unconditional intercepts and conditions. */
670	pVmcb->ctrl.u64InterceptCtrl = SVM_CTRL_INTERCEPT_INTR /* External interrupt causes a #VMEXIT. */
671	\| SVM_CTRL_INTERCEPT_NMI /* Non-maskable interrupts causes a #VMEXIT. */
672	\| SVM_CTRL_INTERCEPT_INIT /* INIT signal causes a #VMEXIT. */
673	\| SVM_CTRL_INTERCEPT_RDPMC /* RDPMC causes a #VMEXIT. */
674	\| SVM_CTRL_INTERCEPT_CPUID /* CPUID causes a #VMEXIT. */
675	\| SVM_CTRL_INTERCEPT_RSM /* RSM causes a #VMEXIT. */
676	\| SVM_CTRL_INTERCEPT_HLT /* HLT causes a #VMEXIT. */
677	\| SVM_CTRL_INTERCEPT_IOIO_PROT /* Use the IOPM to cause IOIO #VMEXITs. */
678	\| SVM_CTRL_INTERCEPT_MSR_PROT /* MSR access not covered by MSRPM causes a #VMEXIT.*/
679	\| SVM_CTRL_INTERCEPT_INVLPGA /* INVLPGA causes a #VMEXIT. */
680	\| SVM_CTRL_INTERCEPT_SHUTDOWN /* Shutdown events causes a #VMEXIT. */
681	\| SVM_CTRL_INTERCEPT_FERR_FREEZE /* Intercept "freezing" during legacy FPU handling. */
682	\| SVM_CTRL_INTERCEPT_VMRUN /* VMRUN causes a #VMEXIT. */
683	\| SVM_CTRL_INTERCEPT_VMMCALL /* VMMCALL causes a #VMEXIT. */
684	\| SVM_CTRL_INTERCEPT_VMLOAD /* VMLOAD causes a #VMEXIT. */
685	\| SVM_CTRL_INTERCEPT_VMSAVE /* VMSAVE causes a #VMEXIT. */
686	\| SVM_CTRL_INTERCEPT_STGI /* STGI causes a #VMEXIT. */
687	\| SVM_CTRL_INTERCEPT_CLGI /* CLGI causes a #VMEXIT. */
688	\| SVM_CTRL_INTERCEPT_SKINIT /* SKINIT causes a #VMEXIT. */
689	\| SVM_CTRL_INTERCEPT_WBINVD /* WBINVD causes a #VMEXIT. */
690	\| SVM_CTRL_INTERCEPT_MONITOR /* MONITOR causes a #VMEXIT. */
691	\| SVM_CTRL_INTERCEPT_MWAIT /* MWAIT causes a #VMEXIT. */
692	\| SVM_CTRL_INTERCEPT_XSETBV; /* XSETBV causes a #VMEXIT. */
693
694	/* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
695	pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) \| RT_BIT(4);
696
697	/* CR0, CR4 writes must be intercepted for the same reasons as above. */
698	pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) \| RT_BIT(4);
699
700	/* Intercept all DRx reads and writes by default. Changed later on. */
701	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
702	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
703
704	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
705	pVmcb->ctrl.IntCtrl.n.u1VIntrMasking = 1;
706
707	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
708	and we currently deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
709	pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
710
711	/* Set IO and MSR bitmap permission bitmap physical addresses. */
712	pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
713	pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
714
715	/* No LBR virtualization. */
716	pVmcb->ctrl.u64LBRVirt = 0;
717
718	/* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
719	pVmcb->ctrl.u64VmcbCleanBits = 0;
720
721	/* The host ASID MBZ, for the guest start with 1. */
722	pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
723
724	/*
725	* Setup the PAT MSR (applicable for Nested Paging only).
726	* The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
727	* so choose type 6 for all PAT slots.
728	*/
729	pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
730
731	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
732	pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
733
734	/* Without Nested Paging, we need additionally intercepts. */
735	if (!pVM->hm.s.fNestedPaging)
736	{
737	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
738	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(3);
739	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(3);
740
741	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
742	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
743	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
744
745	/* Page faults must be intercepted to implement shadow paging. */
746	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
747	}
748
749	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
750	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
751	#endif
752
753	/* Apply the exceptions intercepts needed by the GIM provider. */
754	if (pVCpu->hm.s.fGIMTrapXcptUD)
755	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
756
757	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
758	if (fUsePauseFilter)
759	{
760	pVmcb->ctrl.u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
761	if (fPauseFilterThreshold)
762	pVmcb->ctrl.u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
763	}
764
765	/*
766	* The following MSRs are saved/restored automatically during the world-switch.
767	* Don't intercept guest read/write accesses to these MSRs.
768	*/
769	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
770	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
771	hmR0SvmSetMsrPermission(pVCpu, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
772	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
773	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
774	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
775	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
776	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
777	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
778	hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
779	}
780
781	return VINF_SUCCESS;
782	}
783
784
785	/**
786	* Invalidates a guest page by guest virtual address.
787	*
788	* @returns VBox status code.
789	* @param pVM The cross context VM structure.
790	* @param pVCpu The cross context virtual CPU structure.
791	* @param GCVirt Guest virtual address of the page to invalidate.
792	*/
793	VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
794	{
795	AssertReturn(pVM, VERR_INVALID_PARAMETER);
796	Assert(pVM->hm.s.svm.fSupported);
797
798	bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
799
800	/* Skip it if a TLB flush is already pending. */
801	if (!fFlushPending)
802	{
803	Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
804
805	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
806	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
807
808	#if HC_ARCH_BITS == 32
809	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
810	if (CPUMIsGuestInLongMode(pVCpu))
811	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
812	else
813	#endif
814	{
815	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
816	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
817	}
818	}
819	return VINF_SUCCESS;
820	}
821
822
823	/**
824	* Flushes the appropriate tagged-TLB entries.
825	*
826	* @param pVCpu The cross context virtual CPU structure.
827	*/
828	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu)
829	{
830	PVM pVM = pVCpu->CTX_SUFF(pVM);
831	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
832	PHMGLOBALCPUINFO pCpu = hmR0GetCurrentCpu();
833
834	/*
835	* Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
836	* This can happen both for start & resume due to long jumps back to ring-3.
837	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
838	* so we cannot reuse the ASIDs without flushing.
839	*/
840	bool fNewAsid = false;
841	Assert(pCpu->idCpu != NIL_RTCPUID);
842	if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
843	\|\| pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
844	{
845	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
846	pVCpu->hm.s.fForceTLBFlush = true;
847	fNewAsid = true;
848	}
849
850	/* Set TLB flush state as checked until we return from the world switch. */
851	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
852
853	/* Check for explicit TLB flushes. */
854	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
855	{
856	pVCpu->hm.s.fForceTLBFlush = true;
857	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
858	}
859
860	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
861
862	if (pVM->hm.s.svm.fAlwaysFlushTLB)
863	{
864	/*
865	* This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
866	*/
867	pCpu->uCurrentAsid = 1;
868	pVCpu->hm.s.uCurrentAsid = 1;
869	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
870	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
871
872	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
873	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
874
875	/* Keep track of last CPU ID even when flushing all the time. */
876	if (fNewAsid)
877	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
878	}
879	else if (pVCpu->hm.s.fForceTLBFlush)
880	{
881	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
882	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
883
884	if (fNewAsid)
885	{
886	++pCpu->uCurrentAsid;
887	bool fHitASIDLimit = false;
888	if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
889	{
890	pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
891	pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
892	fHitASIDLimit = true;
893
894	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
895	{
896	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
897	pCpu->fFlushAsidBeforeUse = true;
898	}
899	else
900	{
901	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
902	pCpu->fFlushAsidBeforeUse = false;
903	}
904	}
905
906	if ( !fHitASIDLimit
907	&& pCpu->fFlushAsidBeforeUse)
908	{
909	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
910	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
911	else
912	{
913	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
914	pCpu->fFlushAsidBeforeUse = false;
915	}
916	}
917
918	pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
919	pVCpu->hm.s.idLastCpu = pCpu->idCpu;
920	pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
921	}
922	else
923	{
924	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
925	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
926	else
927	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
928	}
929
930	pVCpu->hm.s.fForceTLBFlush = false;
931	}
932
933	/* Update VMCB with the ASID. */
934	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
935	{
936	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
937	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
938	}
939
940	AssertMsg(pVCpu->hm.s.idLastCpu == pCpu->idCpu,
941	("vcpu idLastCpu=%u pcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pCpu->idCpu));
942	AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
943	("Flush count mismatch for cpu %u (%u vs %u)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
944	AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
945	("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
946	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
947	("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
948
949	#ifdef VBOX_WITH_STATISTICS
950	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
951	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
952	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
953	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
954	{
955	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
956	}
957	else
958	{
959	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
960	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
961	}
962	#endif
963	}
964
965
966	/** @name 64-bit guest on 32-bit host OS helper functions.
967	*
968	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
969	* mode (code segment, paging). These wrappers/helpers perform the necessary
970	* bits for the 32->64 switcher.
971	*
972	* @{ */
973	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
974	/**
975	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
976	*
977	* @returns VBox status code.
978	* @param HCPhysVmcbHost Physical address of host VMCB.
979	* @param HCPhysVmcb Physical address of the VMCB.
980	* @param pCtx Pointer to the guest-CPU context.
981	* @param pVM The cross context VM structure.
982	* @param pVCpu The cross context virtual CPU structure.
983	*/
984	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
985	{
986	uint32_t aParam[8];
987	aParam[0] = RT_LO_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
988	aParam[1] = RT_HI_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Hi. */
989	aParam[2] = RT_LO_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
990	aParam[3] = RT_HI_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Hi. */
991	aParam[4] = VM_RC_ADDR(pVM, pVM);
992	aParam[5] = 0;
993	aParam[6] = VM_RC_ADDR(pVM, pVCpu);
994	aParam[7] = 0;
995
996	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, RT_ELEMENTS(aParam), &aParam[0]);
997	}
998
999
1000	/**
1001	* Executes the specified VMRUN handler in 64-bit mode.
1002	*
1003	* @returns VBox status code.
1004	* @param pVM The cross context VM structure.
1005	* @param pVCpu The cross context virtual CPU structure.
1006	* @param pCtx Pointer to the guest-CPU context.
1007	* @param enmOp The operation to perform.
1008	* @param cParams Number of parameters.
1009	* @param paParam Array of 32-bit parameters.
1010	*/
1011	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp,
1012	uint32_t cParams, uint32_t *paParam)
1013	{
1014	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1015	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1016
1017	NOREF(pCtx);
1018
1019	/* Disable interrupts. */
1020	RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
1021
1022	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1023	RTCPUID idHostCpu = RTMpCpuId();
1024	CPUMR0SetLApic(pVCpu, idHostCpu);
1025	#endif
1026
1027	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1028	CPUMSetHyperEIP(pVCpu, enmOp);
1029	for (int i = (int)cParams - 1; i >= 0; i--)
1030	CPUMPushHyper(pVCpu, paParam[i]);
1031
1032	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1033	/* Call the switcher. */
1034	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1035	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1036
1037	/* Restore interrupts. */
1038	ASMSetFlags(uOldEFlags);
1039	return rc;
1040	}
1041
1042	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1043	/** @} */
1044
1045
1046	/**
1047	* Adds an exception to the intercept exception bitmap in the VMCB and updates
1048	* the corresponding VMCB Clean bit.
1049	*
1050	* @param pVmcb Pointer to the VM control block.
1051	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1052	*/
1053	DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1054	{
1055	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt)))
1056	{
1057	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(u32Xcpt);
1058	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1059	}
1060	}
1061
1062
1063	/**
1064	* Removes an exception from the intercept-exception bitmap in the VMCB and
1065	* updates the corresponding VMCB Clean bit.
1066	*
1067	* @param pVmcb Pointer to the VM control block.
1068	* @param u32Xcpt The value of the exception (X86_XCPT_*).
1069	*/
1070	DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1071	{
1072	Assert(u32Xcpt != X86_XCPT_DB);
1073	Assert(u32Xcpt != X86_XCPT_AC);
1074	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1075	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(u32Xcpt))
1076	{
1077	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(u32Xcpt);
1078	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1079	}
1080	#endif
1081	}
1082
1083
1084	/**
1085	* Loads the guest CR0 control register into the guest-state area in the VMCB.
1086	* Although the guest CR0 is a separate field in the VMCB we have to consider
1087	* the FPU state itself which is shared between the host and the guest.
1088	*
1089	* @returns VBox status code.
1090	* @param pVCpu The cross context virtual CPU structure.
1091	* @param pVmcb Pointer to the VM control block.
1092	* @param pCtx Pointer to the guest-CPU context.
1093	*
1094	* @remarks No-long-jump zone!!!
1095	*/
1096	static void hmR0SvmLoadSharedCR0(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1097	{
1098	/*
1099	* Guest CR0.
1100	*/
1101	PVM pVM = pVCpu->CTX_SUFF(pVM);
1102	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
1103	{
1104	uint64_t u64GuestCR0 = pCtx->cr0;
1105
1106	/* Always enable caching. */
1107	u64GuestCR0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1108
1109	/*
1110	* When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1111	*/
1112	if (!pVM->hm.s.fNestedPaging)
1113	{
1114	u64GuestCR0 \|= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1115	u64GuestCR0 \|= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1116	}
1117
1118	/*
1119	* Guest FPU bits.
1120	*/
1121	bool fInterceptNM = false;
1122	bool fInterceptMF = false;
1123	u64GuestCR0 \|= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1124	if (CPUMIsGuestFPUStateActive(pVCpu))
1125	{
1126	/* Catch floating point exceptions if we need to report them to the guest in a different way. */
1127	if (!(pCtx->cr0 & X86_CR0_NE))
1128	{
1129	Log4(("hmR0SvmLoadGuestControlRegs: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1130	fInterceptMF = true;
1131	}
1132	}
1133	else
1134	{
1135	fInterceptNM = true; /* Guest FPU inactive, #VMEXIT on #NM for lazy FPU loading. */
1136	u64GuestCR0 \|= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1137	\| X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1138	}
1139
1140	/*
1141	* Update the exception intercept bitmap.
1142	*/
1143	if (fInterceptNM)
1144	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1145	else
1146	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_NM);
1147
1148	if (fInterceptMF)
1149	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1150	else
1151	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_MF);
1152
1153	pVmcb->guest.u64CR0 = u64GuestCR0;
1154	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1155	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
1156	}
1157	}
1158
1159
1160	/**
1161	* Loads the guest control registers (CR2, CR3, CR4) into the VMCB.
1162	*
1163	* @returns VBox status code.
1164	* @param pVCpu The cross context virtual CPU structure.
1165	* @param pVmcb Pointer to the VM control block.
1166	* @param pCtx Pointer to the guest-CPU context.
1167	*
1168	* @remarks No-long-jump zone!!!
1169	*/
1170	static int hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1171	{
1172	PVM pVM = pVCpu->CTX_SUFF(pVM);
1173
1174	/*
1175	* Guest CR2.
1176	*/
1177	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR2))
1178	{
1179	pVmcb->guest.u64CR2 = pCtx->cr2;
1180	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1181	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
1182	}
1183
1184	/*
1185	* Guest CR3.
1186	*/
1187	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
1188	{
1189	if (pVM->hm.s.fNestedPaging)
1190	{
1191	PGMMODE enmShwPagingMode;
1192	#if HC_ARCH_BITS == 32
1193	if (CPUMIsGuestInLongModeEx(pCtx))
1194	enmShwPagingMode = PGMMODE_AMD64_NX;
1195	else
1196	#endif
1197	enmShwPagingMode = PGMGetHostMode(pVM);
1198
1199	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1200	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1201	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1202	pVmcb->guest.u64CR3 = pCtx->cr3;
1203	}
1204	else
1205	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1206
1207	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1208	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
1209	}
1210
1211	/*
1212	* Guest CR4.
1213	* ASSUMES this is done everytime we get in from ring-3! (XCR0)
1214	*/
1215	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
1216	{
1217	uint64_t u64GuestCR4 = pCtx->cr4;
1218	if (!pVM->hm.s.fNestedPaging)
1219	{
1220	switch (pVCpu->hm.s.enmShadowMode)
1221	{
1222	case PGMMODE_REAL:
1223	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1224	AssertFailed();
1225	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1226
1227	case PGMMODE_32_BIT: /* 32-bit paging. */
1228	u64GuestCR4 &= ~X86_CR4_PAE;
1229	break;
1230
1231	case PGMMODE_PAE: /* PAE paging. */
1232	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1233	/** Must use PAE paging as we could use physical memory > 4 GB */
1234	u64GuestCR4 \|= X86_CR4_PAE;
1235	break;
1236
1237	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1238	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1239	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1240	break;
1241	#else
1242	AssertFailed();
1243	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1244	#endif
1245
1246	default: /* shut up gcc */
1247	AssertFailed();
1248	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1249	}
1250	}
1251
1252	pVmcb->guest.u64CR4 = u64GuestCR4;
1253	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1254
1255	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1256	pVCpu->hm.s.fLoadSaveGuestXcr0 = (u64GuestCR4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1257
1258	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
1259	}
1260
1261	return VINF_SUCCESS;
1262	}
1263
1264
1265	/**
1266	* Loads the guest segment registers into the VMCB.
1267	*
1268	* @returns VBox status code.
1269	* @param pVCpu The cross context virtual CPU structure.
1270	* @param pVmcb Pointer to the VM control block.
1271	* @param pCtx Pointer to the guest-CPU context.
1272	*
1273	* @remarks No-long-jump zone!!!
1274	*/
1275	static void hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1276	{
1277	/* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1278	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
1279	{
1280	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1281	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1282	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1283	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1284	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1285	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1286
1287	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1288	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1289	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
1290	}
1291
1292	/* Guest TR. */
1293	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
1294	{
1295	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1296	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
1297	}
1298
1299	/* Guest LDTR. */
1300	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
1301	{
1302	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1303	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
1304	}
1305
1306	/* Guest GDTR. */
1307	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
1308	{
1309	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1310	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1311	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1312	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
1313	}
1314
1315	/* Guest IDTR. */
1316	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
1317	{
1318	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1319	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1320	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1321	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
1322	}
1323	}
1324
1325
1326	/**
1327	* Loads the guest MSRs into the VMCB.
1328	*
1329	* @param pVCpu The cross context virtual CPU structure.
1330	* @param pVmcb Pointer to the VM control block.
1331	* @param pCtx Pointer to the guest-CPU context.
1332	*
1333	* @remarks No-long-jump zone!!!
1334	*/
1335	static void hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1336	{
1337	/* Guest Sysenter MSRs. */
1338	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1339	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1340	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1341
1342	/*
1343	* Guest EFER MSR.
1344	* AMD-V requires guest EFER.SVME to be set. Weird.
1345	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1346	*/
1347	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_EFER_MSR))
1348	{
1349	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1350	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1351	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
1352	}
1353
1354	/* 64-bit MSRs. */
1355	if (CPUMIsGuestInLongModeEx(pCtx))
1356	{
1357	pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1358	pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1359	}
1360	else
1361	{
1362	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1363	if (pCtx->msrEFER & MSR_K6_EFER_LME)
1364	{
1365	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1366	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1367	}
1368	}
1369
1370
1371	/** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1372	* be writable in 32-bit mode. Clarify with AMD spec. */
1373	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1374	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1375	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1376	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1377	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1378	}
1379
1380
1381	/**
1382	* Loads the guest state into the VMCB and programs the necessary intercepts
1383	* accordingly.
1384	*
1385	* @param pVCpu The cross context virtual CPU structure.
1386	* @param pVmcb Pointer to the VM control block.
1387	* @param pCtx Pointer to the guest-CPU context.
1388	*
1389	* @remarks No-long-jump zone!!!
1390	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1391	*/
1392	static void hmR0SvmLoadSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1393	{
1394	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
1395	return;
1396	Assert((pCtx->dr[6] & X86_DR6_RA1_MASK) == X86_DR6_RA1_MASK); Assert((pCtx->dr[6] & X86_DR6_RAZ_MASK) == 0);
1397	Assert((pCtx->dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK); Assert((pCtx->dr[7] & X86_DR7_RAZ_MASK) == 0);
1398
1399	bool fInterceptMovDRx = false;
1400
1401	/*
1402	* Anyone single stepping on the host side? If so, we'll have to use the
1403	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1404	* the VMM level like the VT-x implementations does.
1405	*/
1406	bool const fStepping = pVCpu->hm.s.fSingleInstruction;
1407	if (fStepping)
1408	{
1409	pVCpu->hm.s.fClearTrapFlag = true;
1410	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1411	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1412	}
1413	else
1414	Assert(!DBGFIsStepping(pVCpu));
1415
1416	if ( fStepping
1417	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1418	{
1419	/*
1420	* Use the combined guest and host DRx values found in the hypervisor
1421	* register set because the debugger has breakpoints active or someone
1422	* is single stepping on the host side.
1423	*
1424	* Note! DBGF expects a clean DR6 state before executing guest code.
1425	*/
1426	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1427	if ( CPUMIsGuestInLongModeEx(pCtx)
1428	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
1429	{
1430	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1431	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1432	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1433	}
1434	else
1435	#endif
1436	if (!CPUMIsHyperDebugStateActive(pVCpu))
1437	{
1438	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1439	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1440	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1441	}
1442
1443	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1444	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1445	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1446	{
1447	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1448	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1449	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1450	pVCpu->hm.s.fUsingHyperDR7 = true;
1451	}
1452
1453	/** @todo If we cared, we could optimize to allow the guest to read registers
1454	* with the same values. */
1455	fInterceptMovDRx = true;
1456	Log5(("hmR0SvmLoadSharedDebugState: Loaded hyper DRx\n"));
1457	}
1458	else
1459	{
1460	/*
1461	* Update DR6, DR7 with the guest values if necessary.
1462	*/
1463	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1464	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1465	{
1466	pVmcb->guest.u64DR7 = pCtx->dr[7];
1467	pVmcb->guest.u64DR6 = pCtx->dr[6];
1468	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1469	pVCpu->hm.s.fUsingHyperDR7 = false;
1470	}
1471
1472	/*
1473	* If the guest has enabled debug registers, we need to load them prior to
1474	* executing guest code so they'll trigger at the right time.
1475	*/
1476	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1477	{
1478	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1479	if ( CPUMIsGuestInLongModeEx(pCtx)
1480	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1481	{
1482	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1483	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1484	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1485	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1486	}
1487	else
1488	#endif
1489	if (!CPUMIsGuestDebugStateActive(pVCpu))
1490	{
1491	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1492	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1493	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1494	Assert(CPUMIsGuestDebugStateActive(pVCpu));
1495	}
1496	Log5(("hmR0SvmLoadSharedDebugState: Loaded guest DRx\n"));
1497	}
1498	/*
1499	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
1500	* intercept #DB as DR6 is updated in the VMCB.
1501	*
1502	* Note! If we cared and dared, we could skip intercepting \#DB here.
1503	* However, \#DB shouldn't be performance critical, so we'll play safe
1504	* and keep the code similar to the VT-x code and always intercept it.
1505	*/
1506	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1507	else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
1508	&& !CPUMIsGuestDebugStateActive(pVCpu))
1509	#else
1510	else if (!CPUMIsGuestDebugStateActive(pVCpu))
1511	#endif
1512	{
1513	fInterceptMovDRx = true;
1514	}
1515	}
1516
1517	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
1518	if (fInterceptMovDRx)
1519	{
1520	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1521	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1522	{
1523	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1524	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1525	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1526	}
1527	}
1528	else
1529	{
1530	if ( pVmcb->ctrl.u16InterceptRdDRx
1531	\|\| pVmcb->ctrl.u16InterceptWrDRx)
1532	{
1533	pVmcb->ctrl.u16InterceptRdDRx = 0;
1534	pVmcb->ctrl.u16InterceptWrDRx = 0;
1535	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1536	}
1537	}
1538
1539	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
1540	}
1541
1542
1543	/**
1544	* Loads the guest APIC state (currently just the TPR).
1545	*
1546	* @returns VBox status code.
1547	* @param pVCpu The cross context virtual CPU structure.
1548	* @param pVmcb Pointer to the VM control block.
1549	* @param pCtx Pointer to the guest-CPU context.
1550	*/
1551	static int hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1552	{
1553	if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1554	return VINF_SUCCESS;
1555
1556	int rc = VINF_SUCCESS;
1557	PVM pVM = pVCpu->CTX_SUFF(pVM);
1558	if ( PDMHasApic(pVM)
1559	&& APICIsEnabled(pVCpu))
1560	{
1561	bool fPendingIntr;
1562	uint8_t u8Tpr;
1563	rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1564	AssertRCReturn(rc, rc);
1565
1566	/* Assume that we need to trap all TPR accesses and thus need not check on
1567	every #VMEXIT if we should update the TPR. */
1568	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
1569	pVCpu->hm.s.svm.fSyncVTpr = false;
1570
1571	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1572	if (pVM->hm.s.fTPRPatchingActive)
1573	{
1574	pCtx->msrLSTAR = u8Tpr;
1575
1576	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1577	if (fPendingIntr)
1578	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1579	else
1580	{
1581	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1582	pVCpu->hm.s.svm.fSyncVTpr = true;
1583	}
1584	}
1585	else
1586	{
1587	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1588	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1589
1590	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1591	if (fPendingIntr)
1592	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
1593	else
1594	{
1595	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1596	pVCpu->hm.s.svm.fSyncVTpr = true;
1597	}
1598
1599	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
1600	}
1601	}
1602
1603	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1604	return rc;
1605	}
1606
1607
1608	/**
1609	* Loads the exception interrupts required for guest execution in the VMCB.
1610	*
1611	* @returns VBox status code.
1612	* @param pVCpu The cross context virtual CPU structure.
1613	* @param pVmcb Pointer to the VM control block.
1614	* @param pCtx Pointer to the guest-CPU context.
1615	*/
1616	static int hmR0SvmLoadGuestXcptIntercepts(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1617	{
1618	NOREF(pCtx);
1619	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS))
1620	{
1621	/* Trap #UD for GIM provider (e.g. for hypercalls). */
1622	if (pVCpu->hm.s.fGIMTrapXcptUD)
1623	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_UD);
1624	else
1625	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_UD);
1626
1627	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
1628	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
1629	hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_BP);
1630	else
1631	hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_BP);
1632
1633	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmLoadSharedCR0(). */
1634	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_XCPT_INTERCEPTS);
1635	}
1636	return VINF_SUCCESS;
1637	}
1638
1639
1640	/**
1641	* Sets up the appropriate function to run guest code.
1642	*
1643	* @returns VBox status code.
1644	* @param pVCpu The cross context virtual CPU structure.
1645	* @param pCtx Pointer to the guest-CPU context.
1646	*
1647	* @remarks No-long-jump zone!!!
1648	*/
1649	static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pCtx)
1650	{
1651	if (CPUMIsGuestInLongModeEx(pCtx))
1652	{
1653	#ifndef VBOX_ENABLE_64_BITS_GUESTS
1654	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1655	#endif
1656	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1657	#if HC_ARCH_BITS == 32
1658	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1659	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1660	#else
1661	/* 64-bit host or hybrid host. */
1662	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1663	#endif
1664	}
1665	else
1666	{
1667	/* Guest is not in long mode, use the 32-bit handler. */
1668	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1669	}
1670	return VINF_SUCCESS;
1671	}
1672
1673
1674	/**
1675	* Enters the AMD-V session.
1676	*
1677	* @returns VBox status code.
1678	* @param pVM The cross context VM structure.
1679	* @param pVCpu The cross context virtual CPU structure.
1680	* @param pCpu Pointer to the CPU info struct.
1681	*/
1682	VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1683	{
1684	AssertPtr(pVM);
1685	AssertPtr(pVCpu);
1686	Assert(pVM->hm.s.svm.fSupported);
1687	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1688	NOREF(pVM); NOREF(pCpu);
1689
1690	LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1691	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1692
1693	pVCpu->hm.s.fLeaveDone = false;
1694	return VINF_SUCCESS;
1695	}
1696
1697
1698	/**
1699	* Thread-context callback for AMD-V.
1700	*
1701	* @param enmEvent The thread-context event.
1702	* @param pVCpu The cross context virtual CPU structure.
1703	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
1704	* @thread EMT(pVCpu)
1705	*/
1706	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
1707	{
1708	NOREF(fGlobalInit);
1709
1710	switch (enmEvent)
1711	{
1712	case RTTHREADCTXEVENT_OUT:
1713	{
1714	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1715	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
1716	VMCPU_ASSERT_EMT(pVCpu);
1717
1718	/* No longjmps (log-flush, locks) in this fragile context. */
1719	VMMRZCallRing3Disable(pVCpu);
1720
1721	if (!pVCpu->hm.s.fLeaveDone)
1722	{
1723	hmR0SvmLeave(pVCpu);
1724	pVCpu->hm.s.fLeaveDone = true;
1725	}
1726
1727	/* Leave HM context, takes care of local init (term). */
1728	int rc = HMR0LeaveCpu(pVCpu);
1729	AssertRC(rc); NOREF(rc);
1730
1731	/* Restore longjmp state. */
1732	VMMRZCallRing3Enable(pVCpu);
1733	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
1734	break;
1735	}
1736
1737	case RTTHREADCTXEVENT_IN:
1738	{
1739	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1740	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
1741	VMCPU_ASSERT_EMT(pVCpu);
1742
1743	/* No longjmps (log-flush, locks) in this fragile context. */
1744	VMMRZCallRing3Disable(pVCpu);
1745
1746	/*
1747	* Initialize the bare minimum state required for HM. This takes care of
1748	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
1749	*/
1750	int rc = HMR0EnterCpu(pVCpu);
1751	AssertRC(rc); NOREF(rc);
1752	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1753
1754	pVCpu->hm.s.fLeaveDone = false;
1755
1756	/* Restore longjmp state. */
1757	VMMRZCallRing3Enable(pVCpu);
1758	break;
1759	}
1760
1761	default:
1762	break;
1763	}
1764	}
1765
1766
1767	/**
1768	* Saves the host state.
1769	*
1770	* @returns VBox status code.
1771	* @param pVM The cross context VM structure.
1772	* @param pVCpu The cross context virtual CPU structure.
1773	*
1774	* @remarks No-long-jump zone!!!
1775	*/
1776	VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
1777	{
1778	NOREF(pVM);
1779	NOREF(pVCpu);
1780	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
1781	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
1782	return VINF_SUCCESS;
1783	}
1784
1785
1786	/**
1787	* Loads the guest state into the VMCB.
1788	*
1789	* The CPU state will be loaded from these fields on every successful VM-entry.
1790	* Also sets up the appropriate VMRUN function to execute guest code based on
1791	* the guest CPU mode.
1792	*
1793	* @returns VBox status code.
1794	* @param pVM The cross context VM structure.
1795	* @param pVCpu The cross context virtual CPU structure.
1796	* @param pCtx Pointer to the guest-CPU context.
1797	*
1798	* @remarks No-long-jump zone!!!
1799	*/
1800	static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1801	{
1802	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1803	AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1804
1805	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
1806
1807	int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
1808	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1809
1810	hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
1811	hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
1812
1813	pVmcb->guest.u64RIP = pCtx->rip;
1814	pVmcb->guest.u64RSP = pCtx->rsp;
1815	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
1816	pVmcb->guest.u64RAX = pCtx->rax;
1817
1818	rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
1819	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1820
1821	rc = hmR0SvmLoadGuestXcptIntercepts(pVCpu, pVmcb, pCtx);
1822	AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestXcptIntercepts! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1823
1824	rc = hmR0SvmSetupVMRunHandler(pVCpu, pCtx);
1825	AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1826
1827	/* Clear any unused and reserved bits. */
1828	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
1829	\| HM_CHANGED_GUEST_RSP
1830	\| HM_CHANGED_GUEST_RFLAGS
1831	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR
1832	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR
1833	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR
1834	\| HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
1835	\| HM_CHANGED_SVM_RESERVED1 /* Reserved. */
1836	\| HM_CHANGED_SVM_RESERVED2
1837	\| HM_CHANGED_SVM_RESERVED3
1838	\| HM_CHANGED_SVM_RESERVED4);
1839
1840	/* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
1841	AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
1842	\|\| HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE),
1843	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
1844
1845	Log4(("Load: CS:RIP=%04x:%RX64 EFL=%#x SS:RSP=%04x:%RX64\n", pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->ss.Sel, pCtx->rsp));
1846	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
1847	return rc;
1848	}
1849
1850
1851	/**
1852	* Loads the state shared between the host and guest into the
1853	* VMCB.
1854	*
1855	* @param pVCpu The cross context virtual CPU structure.
1856	* @param pVmcb Pointer to the VM control block.
1857	* @param pCtx Pointer to the guest-CPU context.
1858	*
1859	* @remarks No-long-jump zone!!!
1860	*/
1861	static void hmR0SvmLoadSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1862	{
1863	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1864	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1865
1866	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
1867	hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
1868
1869	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
1870	hmR0SvmLoadSharedDebugState(pVCpu, pVmcb, pCtx);
1871
1872	/* Unused on AMD-V. */
1873	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
1874
1875	AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
1876	("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
1877	}
1878
1879
1880	/**
1881	* Saves the entire guest state from the VMCB into the
1882	* guest-CPU context. Currently there is no residual state left in the CPU that
1883	* is not updated in the VMCB.
1884	*
1885	* @returns VBox status code.
1886	* @param pVCpu The cross context virtual CPU structure.
1887	* @param pMixedCtx Pointer to the guest-CPU context. The data may be
1888	* out-of-sync. Make sure to update the required fields
1889	* before using them.
1890	*/
1891	static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1892	{
1893	Assert(VMMRZCallRing3IsEnabled(pVCpu));
1894
1895	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1896
1897	pMixedCtx->rip = pVmcb->guest.u64RIP;
1898	pMixedCtx->rsp = pVmcb->guest.u64RSP;
1899	pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
1900	pMixedCtx->rax = pVmcb->guest.u64RAX;
1901
1902	/*
1903	* Guest interrupt shadow.
1904	*/
1905	if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1906	EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
1907	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1908	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1909
1910	/*
1911	* Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
1912	*/
1913	pMixedCtx->cr2 = pVmcb->guest.u64CR2;
1914
1915	/*
1916	* Guest MSRs.
1917	*/
1918	pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
1919	pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
1920	pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
1921	pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
1922	pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
1923	pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
1924	pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
1925	pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
1926
1927	/*
1928	* Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
1929	*/
1930	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, CS, cs);
1931	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, SS, ss);
1932	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, DS, ds);
1933	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, ES, es);
1934	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, FS, fs);
1935	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, GS, gs);
1936
1937	/*
1938	* Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
1939	* register (yet).
1940	*/
1941	/** @todo SELM might need to be fixed as it too should not care about the
1942	* granularity bit. See @bugref{6785}. */
1943	if ( !pMixedCtx->cs.Attr.n.u1Granularity
1944	&& pMixedCtx->cs.Attr.n.u1Present
1945	&& pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
1946	{
1947	Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
1948	pMixedCtx->cs.Attr.n.u1Granularity = 1;
1949	}
1950
1951	#ifdef VBOX_STRICT
1952	# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
1953	AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
1954	\|\| ( pMixedCtx->reg.Attr.n.u1Granularity \
1955	? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
1956	: pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
1957	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
1958	pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
1959
1960	HMSVM_ASSERT_SEG_GRANULARITY(cs);
1961	HMSVM_ASSERT_SEG_GRANULARITY(ss);
1962	HMSVM_ASSERT_SEG_GRANULARITY(ds);
1963	HMSVM_ASSERT_SEG_GRANULARITY(es);
1964	HMSVM_ASSERT_SEG_GRANULARITY(fs);
1965	HMSVM_ASSERT_SEG_GRANULARITY(gs);
1966
1967	# undef HMSVM_ASSERT_SEL_GRANULARITY
1968	#endif
1969
1970	/*
1971	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
1972	* and thus it's possible that when the CPL changes during guest execution that the SS DPL
1973	* isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
1974	* See AMD spec. 15.5.1 "Basic operation".
1975	*/
1976	Assert(!(pVmcb->guest.u8CPL & ~0x3));
1977	pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
1978
1979	/*
1980	* Guest TR.
1981	* Fixup TR attributes so it's compatible with Intel. Important when saved-states are used
1982	* between Intel and AMD. See @bugref{6208#c39}.
1983	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
1984	*/
1985	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, TR, tr);
1986	if (pMixedCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1987	{
1988	if ( pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1989	\|\| CPUMIsGuestInLongModeEx(pMixedCtx))
1990	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1991	else if (pMixedCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
1992	pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
1993	}
1994
1995	/*
1996	* Guest Descriptor-Table registers.
1997	*/
1998	HMSVM_SEG_REG_COPY_FROM_VMCB(pMixedCtx, &pVmcb->guest, LDTR, ldtr);
1999	pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
2000	pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
2001
2002	pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
2003	pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
2004
2005	/*
2006	* Guest Debug registers.
2007	*/
2008	if (!pVCpu->hm.s.fUsingHyperDR7)
2009	{
2010	pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
2011	pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
2012	}
2013	else
2014	{
2015	Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
2016	CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
2017	}
2018
2019	/*
2020	* With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
2021	* This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
2022	*/
2023	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
2024	&& pMixedCtx->cr3 != pVmcb->guest.u64CR3)
2025	{
2026	CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
2027	PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
2028	}
2029	}
2030
2031
2032	/**
2033	* Does the necessary state syncing before returning to ring-3 for any reason
2034	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2035	*
2036	* @param pVCpu The cross context virtual CPU structure.
2037	*
2038	* @remarks No-long-jmp zone!!!
2039	*/
2040	static void hmR0SvmLeave(PVMCPU pVCpu)
2041	{
2042	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2043	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2044	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2045
2046	/*
2047	* !!! IMPORTANT !!!
2048	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2049	*/
2050
2051	/* Restore host FPU state if necessary and resync on next R0 reentry .*/
2052	if (CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu))
2053	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
2054
2055	/*
2056	* Restore host debug registers if necessary and resync on next R0 reentry.
2057	*/
2058	#ifdef VBOX_STRICT
2059	if (CPUMIsHyperDebugStateActive(pVCpu))
2060	{
2061	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2062	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2063	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2064	}
2065	#endif
2066	if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
2067	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
2068
2069	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2070	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2071
2072	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2073	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
2074	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
2075	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
2076	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2077
2078	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2079	}
2080
2081
2082	/**
2083	* Leaves the AMD-V session.
2084	*
2085	* @returns VBox status code.
2086	* @param pVCpu The cross context virtual CPU structure.
2087	*/
2088	static int hmR0SvmLeaveSession(PVMCPU pVCpu)
2089	{
2090	HM_DISABLE_PREEMPT();
2091	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2092	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2093
2094	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
2095	and done this from the SVMR0ThreadCtxCallback(). */
2096	if (!pVCpu->hm.s.fLeaveDone)
2097	{
2098	hmR0SvmLeave(pVCpu);
2099	pVCpu->hm.s.fLeaveDone = true;
2100	}
2101
2102	/*
2103	* !!! IMPORTANT !!!
2104	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2105	*/
2106
2107	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2108	/* Deregister hook now that we've left HM context before re-enabling preemption. */
2109	VMMR0ThreadCtxHookDisable(pVCpu);
2110
2111	/* Leave HM context. This takes care of local init (term). */
2112	int rc = HMR0LeaveCpu(pVCpu);
2113
2114	HM_RESTORE_PREEMPT();
2115	return rc;
2116	}
2117
2118
2119	/**
2120	* Does the necessary state syncing before doing a longjmp to ring-3.
2121	*
2122	* @returns VBox status code.
2123	* @param pVCpu The cross context virtual CPU structure.
2124	*
2125	* @remarks No-long-jmp zone!!!
2126	*/
2127	static int hmR0SvmLongJmpToRing3(PVMCPU pVCpu)
2128	{
2129	return hmR0SvmLeaveSession(pVCpu);
2130	}
2131
2132
2133	/**
2134	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2135	* any remaining host state) before we longjump to ring-3 and possibly get
2136	* preempted.
2137	*
2138	* @param pVCpu The cross context virtual CPU structure.
2139	* @param enmOperation The operation causing the ring-3 longjump.
2140	* @param pvUser The user argument (pointer to the possibly
2141	* out-of-date guest-CPU context).
2142	*/
2143	static DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
2144	{
2145	RT_NOREF_PV(pvUser);
2146
2147	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
2148	{
2149	/*
2150	* !!! IMPORTANT !!!
2151	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
2152	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
2153	*/
2154	VMMRZCallRing3RemoveNotification(pVCpu);
2155	VMMRZCallRing3Disable(pVCpu);
2156	HM_DISABLE_PREEMPT();
2157
2158	/* Restore host FPU state if necessary and resync on next R0 reentry. */
2159	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
2160
2161	/* Restore host debug registers if necessary and resync on next R0 reentry. */
2162	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2163
2164	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
2165	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
2166	VMMR0ThreadCtxHookDisable(pVCpu);
2167
2168	/* Leave HM context. This takes care of local init (term). */
2169	HMR0LeaveCpu(pVCpu);
2170
2171	HM_RESTORE_PREEMPT();
2172	return VINF_SUCCESS;
2173	}
2174
2175	Assert(pVCpu);
2176	Assert(pvUser);
2177	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2178	HMSVM_ASSERT_PREEMPT_SAFE();
2179
2180	VMMRZCallRing3Disable(pVCpu);
2181	Assert(VMMR0IsLogFlushDisabled(pVCpu));
2182
2183	Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
2184	int rc = hmR0SvmLongJmpToRing3(pVCpu);
2185	AssertRCReturn(rc, rc);
2186
2187	VMMRZCallRing3Enable(pVCpu);
2188	return VINF_SUCCESS;
2189	}
2190
2191
2192	/**
2193	* Take necessary actions before going back to ring-3.
2194	*
2195	* An action requires us to go back to ring-3. This function does the necessary
2196	* steps before we can safely return to ring-3. This is not the same as longjmps
2197	* to ring-3, this is voluntary.
2198	*
2199	* @returns VBox status code.
2200	* @param pVM The cross context VM structure.
2201	* @param pVCpu The cross context virtual CPU structure.
2202	* @param pCtx Pointer to the guest-CPU context.
2203	* @param rcExit The reason for exiting to ring-3. Can be
2204	* VINF_VMM_UNKNOWN_RING3_CALL.
2205	*/
2206	static int hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2207	{
2208	Assert(pVM);
2209	Assert(pVCpu);
2210	Assert(pCtx);
2211	HMSVM_ASSERT_PREEMPT_SAFE();
2212
2213	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2214	VMMRZCallRing3Disable(pVCpu);
2215	Log4(("hmR0SvmExitToRing3: rcExit=%d\n", rcExit));
2216
2217	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2218	if (pVCpu->hm.s.Event.fPending)
2219	{
2220	hmR0SvmPendingEventToTrpmTrap(pVCpu);
2221	Assert(!pVCpu->hm.s.Event.fPending);
2222	}
2223
2224	/* Sync. the necessary state for going back to ring-3. */
2225	hmR0SvmLeaveSession(pVCpu);
2226	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2227
2228	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2229	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2230	\| CPUM_CHANGED_LDTR
2231	\| CPUM_CHANGED_GDTR
2232	\| CPUM_CHANGED_IDTR
2233	\| CPUM_CHANGED_TR
2234	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
2235	if ( pVM->hm.s.fNestedPaging
2236	&& CPUMIsGuestPagingEnabledEx(pCtx))
2237	{
2238	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
2239	}
2240
2241	/* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
2242	if (rcExit != VINF_EM_RAW_INTERRUPT)
2243	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2244
2245	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
2246
2247	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
2248	VMMRZCallRing3RemoveNotification(pVCpu);
2249	VMMRZCallRing3Enable(pVCpu);
2250
2251	/*
2252	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
2253	* and if we're injecting an event we should have a TRPM trap pending.
2254	*/
2255	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
2256	pVCpu->hm.s.u32HMError = rcExit,
2257	VERR_SVM_IPE_5);
2258	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
2259	pVCpu->hm.s.u32HMError = rcExit,
2260	VERR_SVM_IPE_4);
2261
2262	return rcExit;
2263	}
2264
2265
2266	/**
2267	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2268	* intercepts.
2269	*
2270	* @param pVM The cross context VM structure.
2271	* @param pVCpu The cross context virtual CPU structure.
2272	*
2273	* @remarks No-long-jump zone!!!
2274	*/
2275	static void hmR0SvmUpdateTscOffsetting(PVM pVM, PVMCPU pVCpu)
2276	{
2277	bool fParavirtTsc;
2278	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2279	bool fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVM, pVCpu, &pVmcb->ctrl.u64TSCOffset, &fParavirtTsc);
2280	if (fCanUseRealTsc)
2281	{
2282	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSC;
2283	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_RDTSCP;
2284	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2285	}
2286	else
2287	{
2288	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSC;
2289	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_RDTSCP;
2290	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2291	}
2292	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2293
2294	/** @todo later optimize this to be done elsewhere and not before every
2295	* VM-entry. */
2296	if (fParavirtTsc)
2297	{
2298	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
2299	information before every VM-entry, hence disable it for performance sake. */
2300	#if 0
2301	int rc = GIMR0UpdateParavirtTsc(pVM, 0 /* u64Offset */);
2302	AssertRC(rc);
2303	#endif
2304	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
2305	}
2306	}
2307
2308
2309	/**
2310	* Sets an event as a pending event to be injected into the guest.
2311	*
2312	* @param pVCpu The cross context virtual CPU structure.
2313	* @param pEvent Pointer to the SVM event.
2314	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
2315	* page-fault.
2316	*
2317	* @remarks Statistics counter assumes this is a guest event being reflected to
2318	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
2319	*/
2320	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
2321	{
2322	Assert(!pVCpu->hm.s.Event.fPending);
2323	Assert(pEvent->n.u1Valid);
2324
2325	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
2326	pVCpu->hm.s.Event.fPending = true;
2327	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
2328
2329	Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2330	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2331	}
2332
2333
2334	/**
2335	* Injects an event into the guest upon VMRUN by updating the relevant field
2336	* in the VMCB.
2337	*
2338	* @param pVCpu The cross context virtual CPU structure.
2339	* @param pVmcb Pointer to the guest VM control block.
2340	* @param pCtx Pointer to the guest-CPU context.
2341	* @param pEvent Pointer to the event.
2342	*
2343	* @remarks No-long-jump zone!!!
2344	* @remarks Requires CR0!
2345	*/
2346	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
2347	{
2348	NOREF(pVCpu); NOREF(pCtx);
2349
2350	pVmcb->ctrl.EventInject.u = pEvent->u;
2351	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
2352
2353	Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2354	pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2355	}
2356
2357
2358
2359	/**
2360	* Converts any TRPM trap into a pending HM event. This is typically used when
2361	* entering from ring-3 (not longjmp returns).
2362	*
2363	* @param pVCpu The cross context virtual CPU structure.
2364	*/
2365	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
2366	{
2367	Assert(TRPMHasTrap(pVCpu));
2368	Assert(!pVCpu->hm.s.Event.fPending);
2369
2370	uint8_t uVector;
2371	TRPMEVENT enmTrpmEvent;
2372	RTGCUINT uErrCode;
2373	RTGCUINTPTR GCPtrFaultAddress;
2374	uint8_t cbInstr;
2375
2376	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
2377	AssertRC(rc);
2378
2379	SVMEVENT Event;
2380	Event.u = 0;
2381	Event.n.u1Valid = 1;
2382	Event.n.u8Vector = uVector;
2383
2384	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
2385	if (enmTrpmEvent == TRPM_TRAP)
2386	{
2387	Event.n.u3Type = SVM_EVENT_EXCEPTION;
2388	switch (uVector)
2389	{
2390	case X86_XCPT_NMI:
2391	{
2392	Event.n.u3Type = SVM_EVENT_NMI;
2393	break;
2394	}
2395
2396	case X86_XCPT_PF:
2397	case X86_XCPT_DF:
2398	case X86_XCPT_TS:
2399	case X86_XCPT_NP:
2400	case X86_XCPT_SS:
2401	case X86_XCPT_GP:
2402	case X86_XCPT_AC:
2403	{
2404	Event.n.u1ErrorCodeValid = 1;
2405	Event.n.u32ErrorCode = uErrCode;
2406	break;
2407	}
2408	}
2409	}
2410	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
2411	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2412	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
2413	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
2414	else
2415	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
2416
2417	rc = TRPMResetTrap(pVCpu);
2418	AssertRC(rc);
2419
2420	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
2421	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
2422
2423	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
2424	}
2425
2426
2427	/**
2428	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
2429	* AMD-V to execute any instruction.
2430	*
2431	* @param pVCpu The cross context virtual CPU structure.
2432	*/
2433	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
2434	{
2435	Assert(pVCpu->hm.s.Event.fPending);
2436	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
2437
2438	SVMEVENT Event;
2439	Event.u = pVCpu->hm.s.Event.u64IntInfo;
2440
2441	uint8_t uVector = Event.n.u8Vector;
2442	uint8_t uVectorType = Event.n.u3Type;
2443	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event);
2444
2445	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
2446
2447	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
2448	AssertRC(rc);
2449
2450	if (Event.n.u1ErrorCodeValid)
2451	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
2452
2453	if ( uVectorType == SVM_EVENT_EXCEPTION
2454	&& uVector == X86_XCPT_PF)
2455	{
2456	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
2457	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
2458	}
2459	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
2460	{
2461	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
2462	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
2463	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
2464	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
2465	}
2466	pVCpu->hm.s.Event.fPending = false;
2467	}
2468
2469
2470	/**
2471	* Gets the guest's interrupt-shadow.
2472	*
2473	* @returns The guest's interrupt-shadow.
2474	* @param pVCpu The cross context virtual CPU structure.
2475	* @param pCtx Pointer to the guest-CPU context.
2476	*
2477	* @remarks No-long-jump zone!!!
2478	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
2479	*/
2480	DECLINLINE(uint32_t) hmR0SvmGetGuestIntrShadow(PVMCPU pVCpu, PCPUMCTX pCtx)
2481	{
2482	/*
2483	* Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
2484	* inhibit interrupts or clear any existing interrupt-inhibition.
2485	*/
2486	uint32_t uIntrState = 0;
2487	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2488	{
2489	if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2490	{
2491	/*
2492	* We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
2493	* AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
2494	*/
2495	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2496	}
2497	else
2498	uIntrState = SVM_INTERRUPT_SHADOW_ACTIVE;
2499	}
2500	return uIntrState;
2501	}
2502
2503
2504	/**
2505	* Sets the virtual interrupt intercept control in the VMCB which
2506	* instructs AMD-V to cause a \#VMEXIT as soon as the guest is in a state to
2507	* receive interrupts.
2508	*
2509	* @param pVmcb Pointer to the VM control block.
2510	*/
2511	DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
2512	{
2513	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
2514	{
2515	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1; /* A virtual interrupt is pending. */
2516	pVmcb->ctrl.IntCtrl.n.u8VIntrVector = 0; /* Vector not necessary as we #VMEXIT for delivering the interrupt. */
2517	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VINTR;
2518	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
2519
2520	Log4(("Setting VINTR intercept\n"));
2521	}
2522	}
2523
2524
2525	#if 0
2526	/**
2527	* Clears the virtual interrupt intercept control in the VMCB as
2528	* we are figured the guest is unable process any interrupts
2529	* at this point of time.
2530	*
2531	* @param pVmcb Pointer to the VM control block.
2532	*/
2533	DECLINLINE(void) hmR0SvmClearVirtIntrIntercept(PSVMVMCB pVmcb)
2534	{
2535	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR)
2536	{
2537	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
2538	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
2539	Log4(("Clearing VINTR intercept\n"));
2540	}
2541	}
2542	#endif
2543
2544
2545	/**
2546	* Sets the IRET intercept control in the VMCB which instructs AMD-V to cause a
2547	* \#VMEXIT as soon as a guest starts executing an IRET. This is used to unblock
2548	* virtual NMIs.
2549	*
2550	* @param pVmcb Pointer to the VM control block.
2551	*/
2552	DECLINLINE(void) hmR0SvmSetIretIntercept(PSVMVMCB pVmcb)
2553	{
2554	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET))
2555	{
2556	pVmcb->ctrl.u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_IRET;
2557	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
2558
2559	Log4(("Setting IRET intercept\n"));
2560	}
2561	}
2562
2563
2564	/**
2565	* Clears the IRET intercept control in the VMCB.
2566	*
2567	* @param pVmcb Pointer to the VM control block.
2568	*/
2569	DECLINLINE(void) hmR0SvmClearIretIntercept(PSVMVMCB pVmcb)
2570	{
2571	if (pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_IRET)
2572	{
2573	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_IRET;
2574	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
2575
2576	Log4(("Clearing IRET intercept\n"));
2577	}
2578	}
2579
2580
2581	/**
2582	* Evaluates the event to be delivered to the guest and sets it as the pending
2583	* event.
2584	*
2585	* @param pVCpu The cross context virtual CPU structure.
2586	* @param pCtx Pointer to the guest-CPU context.
2587	*/
2588	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2589	{
2590	Assert(!pVCpu->hm.s.Event.fPending);
2591	Log4Func(("\n"));
2592
2593	bool const fIntShadow = RT_BOOL(hmR0SvmGetGuestIntrShadow(pVCpu, pCtx));
2594	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2595	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
2596	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2597
2598	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
2599	APICUpdatePendingInterrupts(pVCpu);
2600
2601	SVMEVENT Event;
2602	Event.u = 0;
2603	/** @todo SMI. SMIs take priority over NMIs. */
2604	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts . */
2605	{
2606	if (fBlockNmi)
2607	hmR0SvmSetIretIntercept(pVmcb);
2608	else if (fIntShadow)
2609	hmR0SvmSetVirtIntrIntercept(pVmcb);
2610	else
2611	{
2612	Log4(("Pending NMI\n"));
2613
2614	Event.n.u1Valid = 1;
2615	Event.n.u8Vector = X86_XCPT_NMI;
2616	Event.n.u3Type = SVM_EVENT_NMI;
2617
2618	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2619	hmR0SvmSetIretIntercept(pVmcb);
2620	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2621	}
2622	}
2623	else if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
2624	&& !pVCpu->hm.s.fSingleInstruction)
2625	{
2626	/*
2627	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt() returns
2628	* a valid interrupt we -must- deliver the interrupt. We can no longer re-request it from the APIC.
2629	*/
2630	if ( !fBlockInt
2631	&& !fIntShadow)
2632	{
2633	uint8_t u8Interrupt;
2634	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
2635	if (RT_SUCCESS(rc))
2636	{
2637	Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
2638
2639	Event.n.u1Valid = 1;
2640	Event.n.u8Vector = u8Interrupt;
2641	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2642
2643	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2644	}
2645	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
2646	{
2647	/*
2648	* AMD-V has no TPR thresholding feature. We just avoid posting the interrupt.
2649	* We just avoid delivering the TPR-masked interrupt here. TPR will be updated
2650	* always via hmR0SvmLoadGuestState() -> hmR0SvmLoadGuestApicState().
2651	*/
2652	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
2653	}
2654	else
2655	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
2656	}
2657	else
2658	hmR0SvmSetVirtIntrIntercept(pVmcb);
2659	}
2660	}
2661
2662
2663	/**
2664	* Injects any pending events into the guest if the guest is in a state to
2665	* receive them.
2666	*
2667	* @param pVCpu The cross context virtual CPU structure.
2668	* @param pCtx Pointer to the guest-CPU context.
2669	*/
2670	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2671	{
2672	Assert(!TRPMHasTrap(pVCpu));
2673	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2674
2675	bool const fIntShadow = RT_BOOL(hmR0SvmGetGuestIntrShadow(pVCpu, pCtx));
2676	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2677	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2678
2679	if (pVCpu->hm.s.Event.fPending) /* First, inject any pending HM events. */
2680	{
2681	SVMEVENT Event;
2682	Event.u = pVCpu->hm.s.Event.u64IntInfo;
2683	Assert(Event.n.u1Valid);
2684	#ifdef VBOX_STRICT
2685	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2686	{
2687	Assert(!fBlockInt);
2688	Assert(!fIntShadow);
2689	}
2690	else if (Event.n.u3Type == SVM_EVENT_NMI)
2691	Assert(!fIntShadow);
2692	#endif
2693
2694	#ifndef RT_OS_WINDOWS
2695	/* Temporary test for returning guru, later make this function return void as before. */
2696	if ( Event.n.u3Type == SVM_EVENT_EXCEPTION
2697	&& Event.n.u8Vector == X86_XCPT_PF)
2698	{
2699	AssertRelease(pCtx->cr2 == pVCpu->hm.s.Event.GCPtrFaultAddress);
2700	}
2701	#endif
2702
2703	Log4(("Injecting pending HM event.\n"));
2704	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2705	pVCpu->hm.s.Event.fPending = false;
2706
2707	#ifdef VBOX_WITH_STATISTICS
2708	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2709	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
2710	else
2711	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
2712	#endif
2713	}
2714
2715	/* Update the guest interrupt shadow in the VMCB. */
2716	pVmcb->ctrl.u64IntShadow = !!fIntShadow;
2717	NOREF(fBlockInt);
2718	}
2719
2720
2721	/**
2722	* Reports world-switch error and dumps some useful debug info.
2723	*
2724	* @param pVM The cross context VM structure.
2725	* @param pVCpu The cross context virtual CPU structure.
2726	* @param rcVMRun The return code from VMRUN (or
2727	* VERR_SVM_INVALID_GUEST_STATE for invalid
2728	* guest-state).
2729	* @param pCtx Pointer to the guest-CPU context.
2730	*/
2731	static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
2732	{
2733	NOREF(pCtx);
2734	HMSVM_ASSERT_PREEMPT_SAFE();
2735	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2736
2737	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
2738	{
2739	hmR0DumpRegs(pVM, pVCpu, pCtx); NOREF(pVM);
2740	#ifdef VBOX_STRICT
2741	Log4(("ctrl.u64VmcbCleanBits %#RX64\n", pVmcb->ctrl.u64VmcbCleanBits));
2742	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
2743	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
2744	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
2745	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
2746	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
2747	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
2748	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
2749	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
2750	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
2751
2752	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
2753	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
2754	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
2755
2756	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
2757	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
2758	Log4(("ctrl.IntCtrl.u7Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
2759	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
2760	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
2761	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
2762	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
2763	Log4(("ctrl.IntCtrl.u6Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
2764	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
2765	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
2766
2767	Log4(("ctrl.u64IntShadow %#RX64\n", pVmcb->ctrl.u64IntShadow));
2768	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
2769	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
2770	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
2771	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
2772	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
2773	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
2774	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
2775	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
2776	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
2777	Log4(("ctrl.NestedPaging %#RX64\n", pVmcb->ctrl.NestedPaging.u));
2778	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
2779	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
2780	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
2781	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
2782	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
2783	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
2784
2785	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
2786	Log4(("ctrl.u64LBRVirt %#RX64\n", pVmcb->ctrl.u64LBRVirt));
2787
2788	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
2789	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
2790	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
2791	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
2792	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
2793	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
2794	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
2795	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
2796	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
2797	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
2798	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
2799	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
2800	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
2801	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
2802	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
2803	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
2804	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
2805	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
2806	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
2807	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
2808
2809	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
2810	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
2811
2812	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
2813	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
2814	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
2815	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
2816
2817	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
2818	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
2819
2820	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
2821	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
2822	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
2823	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
2824
2825	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
2826	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
2827	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
2828	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
2829	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
2830	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
2831	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
2832
2833	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
2834	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
2835	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
2836	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
2837
2838	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
2839	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
2840	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
2841
2842	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
2843	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
2844	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
2845	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
2846	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
2847	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
2848	Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
2849	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
2850	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
2851	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
2852	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
2853	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
2854	#endif /* VBOX_STRICT */
2855	}
2856	else
2857	Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
2858
2859	NOREF(pVmcb);
2860	}
2861
2862
2863	/**
2864	* Check per-VM and per-VCPU force flag actions that require us to go back to
2865	* ring-3 for one reason or another.
2866	*
2867	* @returns VBox status code (information status code included).
2868	* @retval VINF_SUCCESS if we don't have any actions that require going back to
2869	* ring-3.
2870	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
2871	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
2872	* interrupts)
2873	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
2874	* all EMTs to be in ring-3.
2875	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
2876	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
2877	* to the EM loop.
2878	*
2879	* @param pVM The cross context VM structure.
2880	* @param pVCpu The cross context virtual CPU structure.
2881	* @param pCtx Pointer to the guest-CPU context.
2882	*/
2883	static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2884	{
2885	Assert(VMMRZCallRing3IsEnabled(pVCpu));
2886
2887	/* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
2888	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
2889	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
2890
2891	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
2892	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
2893	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
2894	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
2895	{
2896	/* Pending PGM C3 sync. */
2897	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2898	{
2899	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2900	if (rc != VINF_SUCCESS)
2901	{
2902	Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
2903	return rc;
2904	}
2905	}
2906
2907	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
2908	/* -XXX- what was that about single stepping? */
2909	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
2910	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2911	{
2912	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
2913	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2914	Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
2915	return rc;
2916	}
2917
2918	/* Pending VM request packets, such as hardware interrupts. */
2919	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
2920	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
2921	{
2922	Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
2923	return VINF_EM_PENDING_REQUEST;
2924	}
2925
2926	/* Pending PGM pool flushes. */
2927	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
2928	{
2929	Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
2930	return VINF_PGM_POOL_FLUSH_PENDING;
2931	}
2932
2933	/* Pending DMA requests. */
2934	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
2935	{
2936	Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
2937	return VINF_EM_RAW_TO_R3;
2938	}
2939	}
2940
2941	return VINF_SUCCESS;
2942	}
2943
2944
2945	/**
2946	* Does the preparations before executing guest code in AMD-V.
2947	*
2948	* This may cause longjmps to ring-3 and may even result in rescheduling to the
2949	* recompiler. We must be cautious what we do here regarding committing
2950	* guest-state information into the VMCB assuming we assuredly execute the guest
2951	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
2952	* clearing the common-state (TRPM/forceflags), we must undo those changes so
2953	* that the recompiler can (and should) use them when it resumes guest
2954	* execution. Otherwise such operations must be done when we can no longer
2955	* exit to ring-3.
2956	*
2957	* @returns VBox status code (informational status codes included).
2958	* @retval VINF_SUCCESS if we can proceed with running the guest.
2959	* @retval VINF_* scheduling changes, we have to go back to ring-3.
2960	*
2961	* @param pVM The cross context VM structure.
2962	* @param pVCpu The cross context virtual CPU structure.
2963	* @param pCtx Pointer to the guest-CPU context.
2964	* @param pSvmTransient Pointer to the SVM transient structure.
2965	*/
2966	static int hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2967	{
2968	HMSVM_ASSERT_PREEMPT_SAFE();
2969
2970	#if defined(VBOX_WITH_NESTED_HWVIRT) && defined(VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM)
2971	/* Nested Hw. virt through SVM R0 execution is not yet implemented, IEM only, we shouldn't get here. */
2972	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2973	{
2974	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
2975	return VINF_EM_RESCHEDULE_REM;
2976	}
2977	#endif
2978
2979	/* Check force flag actions that might require us to go back to ring-3. */
2980	int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
2981	if (rc != VINF_SUCCESS)
2982	return rc;
2983
2984	if (TRPMHasTrap(pVCpu))
2985	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
2986	else if (!pVCpu->hm.s.Event.fPending)
2987	hmR0SvmEvaluatePendingEvent(pVCpu, pCtx);
2988
2989	/*
2990	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
2991	* Just do it in software, see @bugref{8411}.
2992	* NB: If we could continue a task switch exit we wouldn't need to do this.
2993	*/
2994	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending && (((pVCpu->hm.s.Event.u64IntInfo >> 8) & 7) == SVM_EVENT_NMI)))
2995	if (RT_UNLIKELY(!pVM->hm.s.svm.u32Features))
2996	return VINF_EM_RAW_INJECT_TRPM_EVENT;
2997
2998	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
2999	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
3000	#endif
3001
3002	/* Load the guest bits that are not shared with the host in any way since we can longjmp or get preempted. */
3003	rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
3004	AssertRCReturn(rc, rc);
3005	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
3006
3007	/*
3008	* If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
3009	* so we can update it on the way back if the guest changed the TPR.
3010	*/
3011	if (pVCpu->hm.s.svm.fSyncVTpr)
3012	{
3013	if (pVM->hm.s.fTPRPatchingActive)
3014	pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
3015	else
3016	{
3017	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3018	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
3019	}
3020	}
3021
3022	/*
3023	* No longjmps to ring-3 from this point on!!!
3024	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3025	* This also disables flushing of the R0-logger instance (if any).
3026	*/
3027	VMMRZCallRing3Disable(pVCpu);
3028
3029	/*
3030	* We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
3031	* when thread-context hooks aren't used and we've been running with preemption disabled for a while.
3032	*
3033	* We need to check for force-flags that could've possible been altered since we last checked them (e.g.
3034	* by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
3035	*
3036	* We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
3037	* executing guest code.
3038	*/
3039	pSvmTransient->fEFlags = ASMIntDisableFlags();
3040	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
3041	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
3042	{
3043	ASMSetFlags(pSvmTransient->fEFlags);
3044	VMMRZCallRing3Enable(pVCpu);
3045	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
3046	return VINF_EM_RAW_TO_R3;
3047	}
3048	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
3049	{
3050	ASMSetFlags(pSvmTransient->fEFlags);
3051	VMMRZCallRing3Enable(pVCpu);
3052	STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
3053	return VINF_EM_RAW_INTERRUPT;
3054	}
3055
3056	/*
3057	* If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
3058	* guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
3059	* AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
3060	*
3061	* With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
3062	* VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
3063	*/
3064	if (pVCpu->hm.s.Event.fPending)
3065	{
3066	SVMEVENT Event;
3067	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3068	if ( Event.n.u1Valid
3069	&& Event.n.u3Type == SVM_EVENT_NMI
3070	&& Event.n.u8Vector == X86_XCPT_NMI
3071	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
3072	{
3073	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3074	}
3075	}
3076
3077	return VINF_SUCCESS;
3078	}
3079
3080
3081	/**
3082	* Prepares to run guest code in AMD-V and we've committed to doing so. This
3083	* means there is no backing out to ring-3 or anywhere else at this
3084	* point.
3085	*
3086	* @param pVM The cross context VM structure.
3087	* @param pVCpu The cross context virtual CPU structure.
3088	* @param pCtx Pointer to the guest-CPU context.
3089	* @param pSvmTransient Pointer to the SVM transient structure.
3090	*
3091	* @remarks Called with preemption disabled.
3092	* @remarks No-long-jump zone!!!
3093	*/
3094	static void hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3095	{
3096	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3097	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3098	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3099
3100	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3101	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
3102
3103	hmR0SvmInjectPendingEvent(pVCpu, pCtx);
3104
3105	if ( pVCpu->hm.s.fPreloadGuestFpu
3106	&& !CPUMIsGuestFPUStateActive(pVCpu))
3107	{
3108	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
3109	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
3110	}
3111
3112	/* Load the state shared between host and guest (FPU, debug). */
3113	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3114	if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
3115	hmR0SvmLoadSharedState(pVCpu, pVmcb, pCtx);
3116	HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
3117	AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
3118
3119	/* Setup TSC offsetting. */
3120	RTCPUID idCurrentCpu = hmR0GetCurrentCpu()->idCpu;
3121	if ( pSvmTransient->fUpdateTscOffsetting
3122	\|\| idCurrentCpu != pVCpu->hm.s.idLastCpu)
3123	{
3124	hmR0SvmUpdateTscOffsetting(pVM, pVCpu);
3125	pSvmTransient->fUpdateTscOffsetting = false;
3126	}
3127
3128	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
3129	if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
3130	pVmcb->ctrl.u64VmcbCleanBits = 0;
3131
3132	/* Store status of the shared guest-host state at the time of VMRUN. */
3133	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
3134	if (CPUMIsGuestInLongModeEx(pCtx))
3135	{
3136	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
3137	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
3138	}
3139	else
3140	#endif
3141	{
3142	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
3143	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
3144	}
3145	pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
3146
3147	/* Flush the appropriate tagged-TLB entries. */
3148	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
3149	hmR0SvmFlushTaggedTlb(pVCpu);
3150	Assert(hmR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
3151
3152	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
3153
3154	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
3155	to start executing. */
3156
3157	/*
3158	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
3159	* RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
3160	*
3161	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
3162	*/
3163	if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
3164	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
3165	{
3166	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
3167	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
3168	uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
3169	if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
3170	ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
3171	pSvmTransient->fRestoreTscAuxMsr = true;
3172	}
3173	else
3174	{
3175	hmR0SvmSetMsrPermission(pVCpu, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
3176	pSvmTransient->fRestoreTscAuxMsr = false;
3177	}
3178
3179	/* If VMCB Clean bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
3180	if (!(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
3181	pVmcb->ctrl.u64VmcbCleanBits = 0;
3182	}
3183
3184
3185	/**
3186	* Wrapper for running the guest code in AMD-V.
3187	*
3188	* @returns VBox strict status code.
3189	* @param pVM The cross context VM structure.
3190	* @param pVCpu The cross context virtual CPU structure.
3191	* @param pCtx Pointer to the guest-CPU context.
3192	*
3193	* @remarks No-long-jump zone!!!
3194	*/
3195	DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3196	{
3197	/*
3198	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
3199	* using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
3200	* Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
3201	*/
3202	#ifdef VBOX_WITH_KERNEL_USING_XMM
3203	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
3204	pVCpu->hm.s.svm.pfnVMRun);
3205	#else
3206	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
3207	#endif
3208	}
3209
3210
3211	/**
3212	* Performs some essential restoration of state after running guest code in
3213	* AMD-V.
3214	*
3215	* @param pVM The cross context VM structure.
3216	* @param pVCpu The cross context virtual CPU structure.
3217	* @param pMixedCtx Pointer to the guest-CPU context. The data maybe
3218	* out-of-sync. Make sure to update the required fields
3219	* before using them.
3220	* @param pSvmTransient Pointer to the SVM transient structure.
3221	* @param rcVMRun Return code of VMRUN.
3222	*
3223	* @remarks Called with interrupts disabled.
3224	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
3225	* unconditionally when it is safe to do so.
3226	*/
3227	static void hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
3228	{
3229	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3230
3231	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
3232	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
3233
3234	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3235	pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
3236
3237	/* TSC read must be done early for maximum accuracy. */
3238	if (!(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
3239	TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset);
3240
3241	if (pSvmTransient->fRestoreTscAuxMsr)
3242	{
3243	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
3244	CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
3245	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
3246	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
3247	}
3248
3249	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
3250	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
3251	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3252
3253	Assert(!(ASMGetFlags() & X86_EFL_IF));
3254	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
3255	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
3256
3257	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
3258	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
3259	{
3260	Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
3261	return;
3262	}
3263
3264	pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
3265	HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcb->ctrl.u64ExitCode); /* Update the #VMEXIT history array. */
3266	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
3267	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
3268
3269	hmR0SvmSaveGuestState(pVCpu, pMixedCtx); /* Save the guest state from the VMCB to the guest-CPU context. */
3270
3271	if (RT_LIKELY(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID))
3272	{
3273	if (pVCpu->hm.s.svm.fSyncVTpr)
3274	{
3275	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
3276	if ( pVM->hm.s.fTPRPatchingActive
3277	&& (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
3278	{
3279	int rc = APICSetTpr(pVCpu, pMixedCtx->msrLSTAR & 0xff);
3280	AssertRC(rc);
3281	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
3282	}
3283	else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
3284	{
3285	int rc = APICSetTpr(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
3286	AssertRC(rc);
3287	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
3288	}
3289	}
3290	}
3291	}
3292
3293
3294	/**
3295	* Runs the guest code using AMD-V.
3296	*
3297	* @returns VBox status code.
3298	* @param pVM The cross context VM structure.
3299	* @param pVCpu The cross context virtual CPU structure.
3300	* @param pCtx Pointer to the guest-CPU context.
3301	*/
3302	static int hmR0SvmRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3303	{
3304	SVMTRANSIENT SvmTransient;
3305	SvmTransient.fUpdateTscOffsetting = true;
3306	uint32_t cLoops = 0;
3307	int rc = VERR_INTERNAL_ERROR_5;
3308
3309	for (;; cLoops++)
3310	{
3311	Assert(!HMR0SuspendPending());
3312	HMSVM_ASSERT_CPU_SAFE();
3313
3314	/* Preparatory work for running guest code, this may force us to return
3315	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
3316	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
3317	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
3318	if (rc != VINF_SUCCESS)
3319	break;
3320
3321	/*
3322	* No longjmps to ring-3 from this point on!!!
3323	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3324	* This also disables flushing of the R0-logger instance (if any).
3325	*/
3326	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
3327	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
3328
3329	/* Restore any residual host-state and save any bits shared between host
3330	and guest into the guest-CPU state. Re-enables interrupts! */
3331	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
3332
3333	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
3334	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
3335	{
3336	if (rc == VINF_SUCCESS)
3337	rc = VERR_SVM_INVALID_GUEST_STATE;
3338	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
3339	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
3340	break;
3341	}
3342
3343	/* Handle the #VMEXIT. */
3344	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
3345	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
3346	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb);
3347	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
3348	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
3349	if (rc != VINF_SUCCESS)
3350	break;
3351	if (cLoops > pVM->hm.s.cMaxResumeLoops)
3352	{
3353	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
3354	rc = VINF_EM_RAW_INTERRUPT;
3355	break;
3356	}
3357	}
3358
3359	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
3360	return rc;
3361	}
3362
3363
3364	/**
3365	* Runs the guest code using AMD-V in single step mode.
3366	*
3367	* @returns VBox status code.
3368	* @param pVM The cross context VM structure.
3369	* @param pVCpu The cross context virtual CPU structure.
3370	* @param pCtx Pointer to the guest-CPU context.
3371	*/
3372	static int hmR0SvmRunGuestCodeStep(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3373	{
3374	SVMTRANSIENT SvmTransient;
3375	SvmTransient.fUpdateTscOffsetting = true;
3376	uint32_t cLoops = 0;
3377	int rc = VERR_INTERNAL_ERROR_5;
3378	uint16_t uCsStart = pCtx->cs.Sel;
3379	uint64_t uRipStart = pCtx->rip;
3380
3381	for (;; cLoops++)
3382	{
3383	Assert(!HMR0SuspendPending());
3384	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
3385	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
3386	(unsigned)RTMpCpuId(), cLoops));
3387
3388	/* Preparatory work for running guest code, this may force us to return
3389	to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
3390	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
3391	rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
3392	if (rc != VINF_SUCCESS)
3393	break;
3394
3395	/*
3396	* No longjmps to ring-3 from this point on!!!
3397	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3398	* This also disables flushing of the R0-logger instance (if any).
3399	*/
3400	VMMRZCallRing3Disable(pVCpu);
3401	VMMRZCallRing3RemoveNotification(pVCpu);
3402	hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
3403
3404	rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
3405
3406	/*
3407	* Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
3408	* This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
3409	*/
3410	hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
3411	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
3412	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
3413	{
3414	if (rc == VINF_SUCCESS)
3415	rc = VERR_SVM_INVALID_GUEST_STATE;
3416	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
3417	hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
3418	return rc;
3419	}
3420
3421	/* Handle the #VMEXIT. */
3422	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
3423	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
3424	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb);
3425	rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
3426	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
3427	if (rc != VINF_SUCCESS)
3428	break;
3429	if (cLoops > pVM->hm.s.cMaxResumeLoops)
3430	{
3431	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
3432	rc = VINF_EM_RAW_INTERRUPT;
3433	break;
3434	}
3435
3436	/*
3437	* Did the RIP change, if so, consider it a single step.
3438	* Otherwise, make sure one of the TFs gets set.
3439	*/
3440	if ( pCtx->rip != uRipStart
3441	\|\| pCtx->cs.Sel != uCsStart)
3442	{
3443	rc = VINF_EM_DBG_STEPPED;
3444	break;
3445	}
3446	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_DEBUG;
3447	}
3448
3449	/*
3450	* Clear the X86_EFL_TF if necessary.
3451	*/
3452	if (pVCpu->hm.s.fClearTrapFlag)
3453	{
3454	pVCpu->hm.s.fClearTrapFlag = false;
3455	pCtx->eflags.Bits.u1TF = 0;
3456	}
3457
3458	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
3459	return rc;
3460	}
3461
3462
3463	/**
3464	* Runs the guest code using AMD-V.
3465	*
3466	* @returns Strict VBox status code.
3467	* @param pVM The cross context VM structure.
3468	* @param pVCpu The cross context virtual CPU structure.
3469	* @param pCtx Pointer to the guest-CPU context.
3470	*/
3471	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3472	{
3473	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3474	HMSVM_ASSERT_PREEMPT_SAFE();
3475	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pCtx);
3476
3477	int rc;
3478	if (!pVCpu->hm.s.fSingleInstruction)
3479	rc = hmR0SvmRunGuestCodeNormal(pVM, pVCpu, pCtx);
3480	else
3481	rc = hmR0SvmRunGuestCodeStep(pVM, pVCpu, pCtx);
3482
3483	if (rc == VERR_EM_INTERPRETER)
3484	rc = VINF_EM_RAW_EMULATE_INSTR;
3485	else if (rc == VINF_EM_RESET)
3486	rc = VINF_EM_TRIPLE_FAULT;
3487
3488	/* Prepare to return to ring-3. This will remove longjmp notifications. */
3489	rc = hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
3490	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
3491	return rc;
3492	}
3493
3494
3495	/**
3496	* Handles a \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
3497	*
3498	* @returns VBox status code (informational status codes included).
3499	* @param pVCpu The cross context virtual CPU structure.
3500	* @param pCtx Pointer to the guest-CPU context.
3501	* @param pSvmTransient Pointer to the SVM transient structure.
3502	*/
3503	DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3504	{
3505	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
3506	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
3507
3508	/*
3509	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs for most guests under
3510	* normal workloads (for some definition of "normal").
3511	*/
3512	uint32_t u32ExitCode = pSvmTransient->u64ExitCode;
3513	switch (pSvmTransient->u64ExitCode)
3514	{
3515	case SVM_EXIT_NPF:
3516	return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
3517
3518	case SVM_EXIT_IOIO:
3519	return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
3520
3521	case SVM_EXIT_RDTSC:
3522	return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
3523
3524	case SVM_EXIT_RDTSCP:
3525	return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
3526
3527	case SVM_EXIT_CPUID:
3528	return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
3529
3530	case SVM_EXIT_EXCEPTION_14: /* X86_XCPT_PF */
3531	return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
3532
3533	case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
3534	return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
3535
3536	case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
3537	return hmR0SvmExitXcptUD(pVCpu, pCtx, pSvmTransient);
3538
3539	case SVM_EXIT_EXCEPTION_16: /* X86_XCPT_MF */
3540	return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
3541
3542	case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
3543	return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
3544
3545	case SVM_EXIT_EXCEPTION_17: /* X86_XCPT_AC */
3546	return hmR0SvmExitXcptAC(pVCpu, pCtx, pSvmTransient);
3547
3548	case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
3549	return hmR0SvmExitXcptBP(pVCpu, pCtx, pSvmTransient);
3550
3551	case SVM_EXIT_MONITOR:
3552	return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
3553
3554	case SVM_EXIT_MWAIT:
3555	return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
3556
3557	case SVM_EXIT_HLT:
3558	return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
3559
3560	case SVM_EXIT_READ_CR0:
3561	case SVM_EXIT_READ_CR3:
3562	case SVM_EXIT_READ_CR4:
3563	return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
3564
3565	case SVM_EXIT_WRITE_CR0:
3566	case SVM_EXIT_WRITE_CR3:
3567	case SVM_EXIT_WRITE_CR4:
3568	case SVM_EXIT_WRITE_CR8:
3569	return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
3570
3571	case SVM_EXIT_PAUSE:
3572	return hmR0SvmExitPause(pVCpu, pCtx, pSvmTransient);
3573
3574	case SVM_EXIT_VMMCALL:
3575	return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
3576
3577	case SVM_EXIT_VINTR:
3578	return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
3579
3580	case SVM_EXIT_INTR:
3581	case SVM_EXIT_FERR_FREEZE:
3582	case SVM_EXIT_NMI:
3583	return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
3584
3585	case SVM_EXIT_MSR:
3586	return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
3587
3588	case SVM_EXIT_INVLPG:
3589	return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
3590
3591	case SVM_EXIT_WBINVD:
3592	return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
3593
3594	case SVM_EXIT_INVD:
3595	return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
3596
3597	case SVM_EXIT_RDPMC:
3598	return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
3599
3600	default:
3601	{
3602	switch (pSvmTransient->u64ExitCode)
3603	{
3604	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
3605	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
3606	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
3607	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
3608	return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
3609
3610	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
3611	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
3612	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
3613	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
3614	return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
3615
3616	case SVM_EXIT_XSETBV:
3617	return hmR0SvmExitXsetbv(pVCpu, pCtx, pSvmTransient);
3618
3619	case SVM_EXIT_TASK_SWITCH:
3620	return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
3621
3622	case SVM_EXIT_IRET:
3623	return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
3624
3625	case SVM_EXIT_SHUTDOWN:
3626	return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
3627
3628	case SVM_EXIT_SMI:
3629	case SVM_EXIT_INIT:
3630	{
3631	/*
3632	* We don't intercept NMIs. As for INIT signals, it really shouldn't ever happen here. If it ever does,
3633	* we want to know about it so log the exit code and bail.
3634	*/
3635	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
3636	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
3637	return VERR_SVM_UNEXPECTED_EXIT;
3638	}
3639
3640	#ifdef VBOX_WITH_NESTED_HWVIRT
3641	case SVM_EXIT_CLGI: return hmR0SvmExitClgi(pVCpu, pCtx, pSvmTransient);
3642	case SVM_EXIT_STGI: return hmR0SvmExitStgi(pVCpu, pCtx, pSvmTransient);
3643	case SVM_EXIT_VMLOAD: return hmR0SvmExitVmload(pVCpu, pCtx, pSvmTransient);
3644	case SVM_EXIT_VMSAVE: return hmR0SvmExitVmsave(pVCpu, pCtx, pSvmTransient);
3645	case SVM_EXIT_INVLPGA: return hmR0SvmExitInvlpga(pVCpu, pCtx, pSvmTransient);
3646	case SVM_EXIT_VMRUN: return hmR0SvmExitVmrun(pVCpu, pCtx, pSvmTransient);
3647	#else
3648	case SVM_EXIT_CLGI:
3649	case SVM_EXIT_STGI:
3650	case SVM_EXIT_VMLOAD:
3651	case SVM_EXIT_VMSAVE:
3652	case SVM_EXIT_INVLPGA:
3653	case SVM_EXIT_VMRUN:
3654	#endif
3655	case SVM_EXIT_RSM:
3656	case SVM_EXIT_SKINIT:
3657	return hmR0SvmExitSetPendingXcptUD(pVCpu, pCtx, pSvmTransient);
3658
3659	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
3660	case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
3661	/* SVM_EXIT_EXCEPTION_1: / / X86_XCPT_DB - Handled above. */
3662	case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
3663	/* SVM_EXIT_EXCEPTION_3: / / X86_XCPT_BP - Handled above. */
3664	case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
3665	case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
3666	/* SVM_EXIT_EXCEPTION_6: / / X86_XCPT_UD - Handled above. */
3667	/* SVM_EXIT_EXCEPTION_7: / / X86_XCPT_NM - Handled above. */
3668	case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
3669	case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
3670	case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_TS */
3671	case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_NP */
3672	case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_SS */
3673	case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_GP */
3674	/* SVM_EXIT_EXCEPTION_14: / / X86_XCPT_PF - Handled above. */
3675	case SVM_EXIT_EXCEPTION_15: /* Reserved. */
3676	/* SVM_EXIT_EXCEPTION_16: / / X86_XCPT_MF - Handled above. */
3677	/* SVM_EXIT_EXCEPTION_17: / / X86_XCPT_AC - Handled above. */
3678	case SVM_EXIT_EXCEPTION_18: /* X86_XCPT_MC */
3679	case SVM_EXIT_EXCEPTION_19: /* X86_XCPT_XF */
3680	case SVM_EXIT_EXCEPTION_20: case SVM_EXIT_EXCEPTION_21: case SVM_EXIT_EXCEPTION_22:
3681	case SVM_EXIT_EXCEPTION_23: case SVM_EXIT_EXCEPTION_24: case SVM_EXIT_EXCEPTION_25:
3682	case SVM_EXIT_EXCEPTION_26: case SVM_EXIT_EXCEPTION_27: case SVM_EXIT_EXCEPTION_28:
3683	case SVM_EXIT_EXCEPTION_29: case SVM_EXIT_EXCEPTION_30: case SVM_EXIT_EXCEPTION_31:
3684	{
3685	/** @todo r=ramshankar; We should be doing
3686	* HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY here! */
3687
3688	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3689	SVMEVENT Event;
3690	Event.u = 0;
3691	Event.n.u1Valid = 1;
3692	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3693	Event.n.u8Vector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
3694
3695	switch (Event.n.u8Vector)
3696	{
3697	case X86_XCPT_DE:
3698	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
3699	break;
3700
3701	case X86_XCPT_NP:
3702	Event.n.u1ErrorCodeValid = 1;
3703	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3704	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
3705	break;
3706
3707	case X86_XCPT_SS:
3708	Event.n.u1ErrorCodeValid = 1;
3709	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3710	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
3711	break;
3712
3713	case X86_XCPT_GP:
3714	Event.n.u1ErrorCodeValid = 1;
3715	Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3716	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
3717	break;
3718
3719	default:
3720	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit caused by exception %#x\n", Event.n.u8Vector));
3721	pVCpu->hm.s.u32HMError = Event.n.u8Vector;
3722	return VERR_SVM_UNEXPECTED_XCPT_EXIT;
3723	}
3724
3725	Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
3726	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3727	return VINF_SUCCESS;
3728	}
3729	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
3730
3731	default:
3732	{
3733	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#x\n", u32ExitCode));
3734	pVCpu->hm.s.u32HMError = u32ExitCode;
3735	return VERR_SVM_UNKNOWN_EXIT;
3736	}
3737	}
3738	}
3739	}
3740	/* not reached */
3741	}
3742
3743
3744	#ifdef DEBUG
3745	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
3746	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
3747	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
3748
3749	# define HMSVM_ASSERT_PREEMPT_CPUID() \
3750	do \
3751	{ \
3752	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
3753	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
3754	} while (0)
3755
3756	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
3757	do { \
3758	AssertPtr(pVCpu); \
3759	AssertPtr(pCtx); \
3760	AssertPtr(pSvmTransient); \
3761	Assert(ASMIntAreEnabled()); \
3762	HMSVM_ASSERT_PREEMPT_SAFE(); \
3763	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
3764	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
3765	HMSVM_ASSERT_PREEMPT_SAFE(); \
3766	if (VMMR0IsLogFlushDisabled(pVCpu)) \
3767	HMSVM_ASSERT_PREEMPT_CPUID(); \
3768	} while (0)
3769	#else /* Release builds */
3770	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { NOREF(pVCpu); NOREF(pCtx); NOREF(pSvmTransient); } while (0)
3771	#endif
3772
3773
3774	/**
3775	* Worker for hmR0SvmInterpretInvlpg().
3776	*
3777	* @return VBox status code.
3778	* @param pVCpu The cross context virtual CPU structure.
3779	* @param pCpu Pointer to the disassembler state.
3780	* @param pCtx The guest CPU context.
3781	*/
3782	static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTX pCtx)
3783	{
3784	DISQPVPARAMVAL Param1;
3785	RTGCPTR GCPtrPage;
3786
3787	int rc = DISQueryParamVal(CPUMCTX2CORE(pCtx), pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
3788	if (RT_FAILURE(rc))
3789	return VERR_EM_INTERPRETER;
3790
3791	if ( Param1.type == DISQPV_TYPE_IMMEDIATE
3792	\|\| Param1.type == DISQPV_TYPE_ADDRESS)
3793	{
3794	if (!(Param1.flags & (DISQPV_FLAG_32 \| DISQPV_FLAG_64)))
3795	return VERR_EM_INTERPRETER;
3796
3797	GCPtrPage = Param1.val.val64;
3798	VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx), GCPtrPage);
3799	rc = VBOXSTRICTRC_VAL(rc2);
3800	}
3801	else
3802	{
3803	Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
3804	rc = VERR_EM_INTERPRETER;
3805	}
3806
3807	return rc;
3808	}
3809
3810
3811	/**
3812	* Interprets INVLPG.
3813	*
3814	* @returns VBox status code.
3815	* @retval VINF_* Scheduling instructions.
3816	* @retval VERR_EM_INTERPRETER Something we can't cope with.
3817	* @retval VERR_* Fatal errors.
3818	*
3819	* @param pVM The cross context VM structure.
3820	* @param pVCpu The cross context virtual CPU structure.
3821	* @param pCtx The guest CPU context.
3822	*
3823	* @remarks Updates the RIP if the instruction was executed successfully.
3824	*/
3825	static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3826	{
3827	/* Only allow 32 & 64 bit code. */
3828	if (CPUMGetGuestCodeBits(pVCpu) != 16)
3829	{
3830	PDISSTATE pDis = &pVCpu->hm.s.DisState;
3831	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
3832	if ( RT_SUCCESS(rc)
3833	&& pDis->pCurInstr->uOpcode == OP_INVLPG)
3834	{
3835	rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pCtx);
3836	if (RT_SUCCESS(rc))
3837	pCtx->rip += pDis->cbInstr;
3838	return rc;
3839	}
3840	else
3841	Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
3842	}
3843	return VERR_EM_INTERPRETER;
3844	}
3845
3846
3847	/**
3848	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
3849	*
3850	* @param pVCpu The cross context virtual CPU structure.
3851	*/
3852	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3853	{
3854	SVMEVENT Event;
3855	Event.u = 0;
3856	Event.n.u1Valid = 1;
3857	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3858	Event.n.u8Vector = X86_XCPT_UD;
3859	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3860	}
3861
3862
3863	/**
3864	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
3865	*
3866	* @param pVCpu The cross context virtual CPU structure.
3867	*/
3868	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3869	{
3870	SVMEVENT Event;
3871	Event.u = 0;
3872	Event.n.u1Valid = 1;
3873	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3874	Event.n.u8Vector = X86_XCPT_DB;
3875	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3876	}
3877
3878
3879	/**
3880	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
3881	*
3882	* @param pVCpu The cross context virtual CPU structure.
3883	* @param pCtx Pointer to the guest-CPU context.
3884	* @param u32ErrCode The error-code for the page-fault.
3885	* @param uFaultAddress The page fault address (CR2).
3886	*
3887	* @remarks This updates the guest CR2 with @a uFaultAddress!
3888	*/
3889	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3890	{
3891	SVMEVENT Event;
3892	Event.u = 0;
3893	Event.n.u1Valid = 1;
3894	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3895	Event.n.u8Vector = X86_XCPT_PF;
3896	Event.n.u1ErrorCodeValid = 1;
3897	Event.n.u32ErrorCode = u32ErrCode;
3898
3899	/* Update CR2 of the guest. */
3900	if (pCtx->cr2 != uFaultAddress)
3901	{
3902	pCtx->cr2 = uFaultAddress;
3903	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR2);
3904	}
3905
3906	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3907	}
3908
3909
3910	/**
3911	* Sets a device-not-available (\#NM) exception as pending-for-injection into
3912	* the VM.
3913	*
3914	* @param pVCpu The cross context virtual CPU structure.
3915	*/
3916	DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
3917	{
3918	SVMEVENT Event;
3919	Event.u = 0;
3920	Event.n.u1Valid = 1;
3921	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3922	Event.n.u8Vector = X86_XCPT_NM;
3923	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3924	}
3925
3926
3927	/**
3928	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
3929	*
3930	* @param pVCpu The cross context virtual CPU structure.
3931	*/
3932	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3933	{
3934	SVMEVENT Event;
3935	Event.u = 0;
3936	Event.n.u1Valid = 1;
3937	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3938	Event.n.u8Vector = X86_XCPT_MF;
3939	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3940	}
3941
3942
3943	/**
3944	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
3945	*
3946	* @param pVCpu The cross context virtual CPU structure.
3947	*/
3948	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3949	{
3950	SVMEVENT Event;
3951	Event.u = 0;
3952	Event.n.u1Valid = 1;
3953	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3954	Event.n.u8Vector = X86_XCPT_DF;
3955	Event.n.u1ErrorCodeValid = 1;
3956	Event.n.u32ErrorCode = 0;
3957	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3958	}
3959
3960	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
3961	/**
3962	* Gets the IEM exception flags for the specified SVM event.
3963	*
3964	* @returns The IEM exception flags.
3965	* @param pEvent Pointer to the SVM event.
3966	*
3967	* @remarks This function currently only constructs flags required for
3968	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
3969	* and CR2 aspects of an exception are not included).
3970	*/
3971	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
3972	{
3973	uint8_t const uEventType = pEvent->n.u3Type;
3974	uint32_t fIemXcptFlags;
3975	switch (uEventType)
3976	{
3977	case SVM_EVENT_EXCEPTION:
3978	/*
3979	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
3980	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
3981	*/
3982	if (pEvent->n.u8Vector == X86_XCPT_BP)
3983	{
3984	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
3985	break;
3986	}
3987	if (pEvent->n.u8Vector == X86_XCPT_OF)
3988	{
3989	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
3990	break;
3991	}
3992	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
3993	/* fall thru */
3994	case SVM_EVENT_NMI:
3995	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
3996	break;
3997
3998	case SVM_EVENT_EXTERNAL_IRQ:
3999	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
4000	break;
4001
4002	case SVM_EVENT_SOFTWARE_INT:
4003	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
4004	break;
4005
4006	default:
4007	fIemXcptFlags = 0;
4008	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
4009	break;
4010	}
4011	return fIemXcptFlags;
4012	}
4013
4014	#else
4015	/**
4016	* Determines if an exception is a contributory exception.
4017	*
4018	* Contributory exceptions are ones which can cause double-faults unless the
4019	* original exception was a benign exception. Page-fault is intentionally not
4020	* included here as it's a conditional contributory exception.
4021	*
4022	* @returns true if the exception is contributory, false otherwise.
4023	* @param uVector The exception vector.
4024	*/
4025	DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
4026	{
4027	switch (uVector)
4028	{
4029	case X86_XCPT_GP:
4030	case X86_XCPT_SS:
4031	case X86_XCPT_NP:
4032	case X86_XCPT_TS:
4033	case X86_XCPT_DE:
4034	return true;
4035	default:
4036	break;
4037	}
4038	return false;
4039	}
4040	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
4041
4042
4043	/**
4044	* Handle a condition that occurred while delivering an event through the guest
4045	* IDT.
4046	*
4047	* @returns VBox status code (informational error codes included).
4048	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
4049	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
4050	* continue execution of the guest which will delivery the \#DF.
4051	* @retval VINF_EM_RESET if we detected a triple-fault condition.
4052	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
4053	*
4054	* @param pVCpu The cross context virtual CPU structure.
4055	* @param pCtx Pointer to the guest-CPU context.
4056	* @param pSvmTransient Pointer to the SVM transient structure.
4057	*
4058	* @remarks No-long-jump zone!!!
4059	*/
4060	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4061	{
4062	int rc = VINF_SUCCESS;
4063	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4064
4065	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
4066	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
4067	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
4068
4069	/* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
4070	* that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
4071	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
4072	{
4073	#ifdef HMSVM_USE_IEM_EVENT_REFLECTION
4074	IEMXCPTRAISE enmRaise;
4075	IEMXCPTRAISEINFO fRaiseInfo;
4076	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31;
4077	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
4078	if (fExitIsHwXcpt)
4079	{
4080	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
4081	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
4082	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
4083	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
4084	}
4085	else
4086	{
4087	/*
4088	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF) then we
4089	* end up here.
4090	*
4091	* If the event was:
4092	* - a software interrupt, we can re-execute the instruction which will regenerate
4093	* the event.
4094	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
4095	* - a hardware exception or external interrupt, we re-inject it.
4096	*/
4097	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
4098	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
4099	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
4100	else
4101	enmRaise = IEMXCPTRAISE_PREV_EVENT;
4102	}
4103
4104	switch (enmRaise)
4105	{
4106	case IEMXCPTRAISE_CURRENT_XCPT:
4107	case IEMXCPTRAISE_PREV_EVENT:
4108	{
4109	/* For software interrupts, we shall re-execute the instruction. */
4110	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
4111	{
4112	RTGCUINTPTR GCPtrFaultAddress = 0;
4113
4114	/* If we are re-injecting an NMI, clear NMI blocking. */
4115	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
4116	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
4117
4118	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
4119	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
4120	pSvmTransient->fVectoringPF = true;
4121	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
4122	&& uIdtVector == X86_XCPT_PF)
4123	{
4124	/*
4125	* If the previous exception was a #PF, we need to recover the CR2 value.
4126	* This can't happen with shadow paging.
4127	*/
4128	GCPtrFaultAddress = pCtx->cr2;
4129	}
4130
4131	/*
4132	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
4133	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
4134	*/
4135	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
4136	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
4137	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
4138
4139	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
4140	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
4141	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
4142	}
4143	break;
4144	}
4145
4146	case IEMXCPTRAISE_REEXEC_INSTR:
4147	{
4148	Assert(rc == VINF_SUCCESS);
4149	break;
4150	}
4151
4152	case IEMXCPTRAISE_DOUBLE_FAULT:
4153	{
4154	/*
4155	* Determing a vectoring double #PF condition. Used later, when PGM evaluates the
4156	* second #PF as a guest #PF (and not a shadow #PF) and needs to be converted into a #DF.
4157	*/
4158	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
4159	{
4160	pSvmTransient->fVectoringDoublePF = true;
4161	Assert(rc == VINF_SUCCESS);
4162	}
4163	else
4164	{
4165	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
4166	hmR0SvmSetPendingXcptDF(pVCpu);
4167	rc = VINF_HM_DOUBLE_FAULT;
4168	}
4169	break;
4170	}
4171
4172	case IEMXCPTRAISE_TRIPLE_FAULT:
4173	{
4174	rc = VINF_EM_RESET;
4175	break;
4176	}
4177
4178	case IEMXCPTRAISE_CPU_HANG:
4179	{
4180	rc = VERR_EM_GUEST_CPU_HANG;
4181	break;
4182	}
4183
4184	default:
4185	{
4186	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
4187	rc = VERR_SVM_IPE_2;
4188	break;
4189	}
4190	}
4191	#else
4192	uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
4193
4194	typedef enum
4195	{
4196	SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
4197	SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
4198	SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
4199	SVMREFLECTXCPT_HANG, /* Indicate bad VM trying to deadlock the CPU. */
4200	SVMREFLECTXCPT_NONE /* Nothing to reflect. */
4201	} SVMREFLECTXCPT;
4202
4203	SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
4204	bool fReflectingNmi = false;
4205	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
4206	{
4207	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31)
4208	{
4209	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
4210
4211	#ifdef VBOX_STRICT
4212	if ( hmR0SvmIsContributoryXcpt(uIdtVector)
4213	&& uExitVector == X86_XCPT_PF)
4214	{
4215	Log4(("IDT: Contributory #PF idCpu=%u uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
4216	}
4217	#endif
4218
4219	if ( uIdtVector == X86_XCPT_BP
4220	\|\| uIdtVector == X86_XCPT_OF)
4221	{
4222	/* Ignore INT3/INTO, just re-execute. See @bugref{8357}. */
4223	}
4224	else if ( uExitVector == X86_XCPT_PF
4225	&& uIdtVector == X86_XCPT_PF)
4226	{
4227	pSvmTransient->fVectoringDoublePF = true;
4228	Log4(("IDT: Vectoring double #PF uCR2=%#RX64\n", pCtx->cr2));
4229	}
4230	else if ( uExitVector == X86_XCPT_AC
4231	&& uIdtVector == X86_XCPT_AC)
4232	{
4233	enmReflect = SVMREFLECTXCPT_HANG;
4234	Log4(("IDT: Nested #AC - Bad guest\n"));
4235	}
4236	else if ( (pVmcb->ctrl.u32InterceptXcpt & HMSVM_CONTRIBUTORY_XCPT_MASK)
4237	&& hmR0SvmIsContributoryXcpt(uExitVector)
4238	&& ( hmR0SvmIsContributoryXcpt(uIdtVector)
4239	\|\| uIdtVector == X86_XCPT_PF))
4240	{
4241	enmReflect = SVMREFLECTXCPT_DF;
4242	Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
4243	uIdtVector, uExitVector));
4244	}
4245	else if (uIdtVector == X86_XCPT_DF)
4246	{
4247	enmReflect = SVMREFLECTXCPT_TF;
4248	Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n",
4249	pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
4250	}
4251	else
4252	enmReflect = SVMREFLECTXCPT_XCPT;
4253	}
4254	else
4255	{
4256	/*
4257	* If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
4258	* exception to the guest after handling the #VMEXIT.
4259	*/
4260	enmReflect = SVMREFLECTXCPT_XCPT;
4261	}
4262	}
4263	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
4264	\|\| pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
4265	{
4266	enmReflect = SVMREFLECTXCPT_XCPT;
4267	fReflectingNmi = RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI);
4268
4269	if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_31)
4270	{
4271	uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
4272	if (uExitVector == X86_XCPT_PF)
4273	{
4274	pSvmTransient->fVectoringPF = true;
4275	Log4(("IDT: Vectoring #PF due to Ext-Int/NMI. uCR2=%#RX64\n", pCtx->cr2));
4276	}
4277	}
4278	}
4279	/* else: Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
4280
4281	switch (enmReflect)
4282	{
4283	case SVMREFLECTXCPT_XCPT:
4284	{
4285	/* If we are re-injecting the NMI, clear NMI blocking. */
4286	if (fReflectingNmi)
4287	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
4288
4289	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
4290	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
4291	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
4292
4293	/* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
4294	Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
4295	!!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
4296	break;
4297	}
4298
4299	case SVMREFLECTXCPT_DF:
4300	{
4301	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
4302	hmR0SvmSetPendingXcptDF(pVCpu);
4303	rc = VINF_HM_DOUBLE_FAULT;
4304	break;
4305	}
4306
4307	case SVMREFLECTXCPT_TF:
4308	{
4309	rc = VINF_EM_RESET;
4310	break;
4311	}
4312
4313	case SVMREFLECTXCPT_HANG:
4314	{
4315	rc = VERR_EM_GUEST_CPU_HANG;
4316	break;
4317	}
4318
4319	default:
4320	Assert(rc == VINF_SUCCESS);
4321	break;
4322	}
4323	#endif /* HMSVM_USE_IEM_EVENT_REFLECTION */
4324	}
4325	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
4326	NOREF(pCtx);
4327	return rc;
4328	}
4329
4330
4331	/**
4332	* Updates interrupt shadow for the current RIP.
4333	*/
4334	#define HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx) \
4335	do { \
4336	/* Update interrupt shadow. */ \
4337	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS) \
4338	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu)) \
4339	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS); \
4340	} while (0)
4341
4342
4343	/**
4344	* Advances the guest RIP making use of the CPU's NRIP_SAVE feature if
4345	* supported, otherwise advances the RIP by the number of bytes specified in
4346	* @a cb.
4347	*
4348	* @param pVCpu The cross context virtual CPU structure.
4349	* @param pCtx Pointer to the guest-CPU context.
4350	* @param cb RIP increment value in bytes.
4351	*
4352	* @remarks Use this function only from \#VMEXIT's where the NRIP value is valid
4353	* when NRIP_SAVE is supported by the CPU, otherwise use
4354	* hmR0SvmAdvanceRipDumb!
4355	*/
4356	DECLINLINE(void) hmR0SvmAdvanceRipHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
4357	{
4358	if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4359	{
4360	PCSVMVMCB pVmcb = (PCSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4361	Assert(pVmcb->ctrl.u64NextRIP);
4362	AssertRelease(pVmcb->ctrl.u64NextRIP - pCtx->rip == cb); /* temporary, remove later */
4363	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4364	}
4365	else
4366	pCtx->rip += cb;
4367
4368	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
4369	}
4370
4371	/* Currently only used by nested hw.virt instructions, so ifdef'd as such, otherwise compilers start whining. */
4372	#ifdef VBOX_WITH_NESTED_HWVIRT
4373	/**
4374	* Gets the length of the current instruction if the CPU supports the NRIP_SAVE
4375	* feature. Otherwise, returns the value in @a cbLikely.
4376	*
4377	* @param pVCpu The cross context virtual CPU structure.
4378	* @param pCtx Pointer to the guest-CPU context.
4379	* @param cbLikely The likely instruction length.
4380	*/
4381	DECLINLINE(uint8_t) hmR0SvmGetInstrLengthHwAssist(PVMCPU pVCpu, PCPUMCTX pCtx, uint8_t cbLikely)
4382	{
4383	Assert(cbLikely <= 15); /* See Intel spec. 2.3.11 "AVX Instruction Length" */
4384	if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4385	{
4386	PCSVMVMCB pVmcb = (PCSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4387	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
4388	Assert(cbInstr == cbLikely);
4389	return cbInstr;
4390	}
4391	return cbLikely;
4392	}
4393	#endif
4394
4395	/**
4396	* Advances the guest RIP by the number of bytes specified in @a cb. This does
4397	* not make use of any hardware features to determine the instruction length.
4398	*
4399	* @param pVCpu The cross context virtual CPU structure.
4400	* @param pCtx Pointer to the guest-CPU context.
4401	* @param cb RIP increment value in bytes.
4402	*/
4403	DECLINLINE(void) hmR0SvmAdvanceRipDumb(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
4404	{
4405	pCtx->rip += cb;
4406	HMSVM_UPDATE_INTR_SHADOW(pVCpu, pCtx);
4407	}
4408	#undef HMSVM_UPDATE_INTR_SHADOW
4409
4410
4411	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
4412	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
4413	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
4414
4415	/** @name \#VMEXIT handlers.
4416	* @{
4417	*/
4418
4419	/**
4420	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
4421	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
4422	*/
4423	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4424	{
4425	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4426
4427	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
4428	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
4429	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
4430	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
4431
4432	/*
4433	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
4434	* fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
4435	* interrupt it is until the host actually take the interrupt.
4436	*
4437	* Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
4438	* AMD Phenom 9850 Quad-Core on Windows 64-bit host).
4439	*/
4440	return VINF_EM_RAW_INTERRUPT;
4441	}
4442
4443
4444	/**
4445	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
4446	*/
4447	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4448	{
4449	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4450
4451	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4452	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
4453	int rc = VINF_SUCCESS;
4454	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4455	return rc;
4456	}
4457
4458
4459	/**
4460	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
4461	*/
4462	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4463	{
4464	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4465
4466	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4467	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
4468	int rc = VINF_SUCCESS;
4469	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4470	return rc;
4471	}
4472
4473
4474	/**
4475	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
4476	*/
4477	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4478	{
4479	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4480	PVM pVM = pVCpu->CTX_SUFF(pVM);
4481	int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4482	if (RT_LIKELY(rc == VINF_SUCCESS))
4483	{
4484	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4485	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4486	}
4487	else
4488	{
4489	AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
4490	rc = VERR_EM_INTERPRETER;
4491	}
4492	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
4493	return rc;
4494	}
4495
4496
4497	/**
4498	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
4499	*/
4500	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4501	{
4502	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4503	PVM pVM = pVCpu->CTX_SUFF(pVM);
4504	int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4505	if (RT_LIKELY(rc == VINF_SUCCESS))
4506	{
4507	pSvmTransient->fUpdateTscOffsetting = true;
4508	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4509	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4510	}
4511	else
4512	{
4513	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
4514	rc = VERR_EM_INTERPRETER;
4515	}
4516	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
4517	return rc;
4518	}
4519
4520
4521	/**
4522	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
4523	*/
4524	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4525	{
4526	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4527	int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4528	if (RT_LIKELY(rc == VINF_SUCCESS))
4529	{
4530	pSvmTransient->fUpdateTscOffsetting = true;
4531	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
4532	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4533	}
4534	else
4535	{
4536	AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
4537	rc = VERR_EM_INTERPRETER;
4538	}
4539	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
4540	return rc;
4541	}
4542
4543
4544	/**
4545	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
4546	*/
4547	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4548	{
4549	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4550	int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4551	if (RT_LIKELY(rc == VINF_SUCCESS))
4552	{
4553	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4554	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4555	}
4556	else
4557	{
4558	AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
4559	rc = VERR_EM_INTERPRETER;
4560	}
4561	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
4562	return rc;
4563	}
4564
4565
4566	/**
4567	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
4568	*/
4569	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4570	{
4571	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4572	PVM pVM = pVCpu->CTX_SUFF(pVM);
4573	Assert(!pVM->hm.s.fNestedPaging);
4574	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
4575
4576	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST)
4577	{
4578	Assert(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
4579	PCSVMVMCB pVmcb = (PCSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4580	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
4581	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
4582	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
4583	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
4584	return VBOXSTRICTRC_VAL(rcStrict);
4585	}
4586
4587	int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, pCtx); /* Updates RIP if successful. */
4588	Assert(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER);
4589	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4590	return rc;
4591	}
4592
4593
4594	/**
4595	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
4596	*/
4597	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4598	{
4599	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4600
4601	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 1);
4602	int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
4603	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4604	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
4605	if (rc != VINF_SUCCESS)
4606	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
4607	return rc;
4608	}
4609
4610
4611	/**
4612	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
4613	*/
4614	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4615	{
4616	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4617	int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4618	if (RT_LIKELY(rc == VINF_SUCCESS))
4619	{
4620	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
4621	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4622	}
4623	else
4624	{
4625	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
4626	rc = VERR_EM_INTERPRETER;
4627	}
4628	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
4629	return rc;
4630	}
4631
4632
4633	/**
4634	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
4635	*/
4636	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4637	{
4638	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4639	VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4640	int rc = VBOXSTRICTRC_VAL(rc2);
4641	if ( rc == VINF_EM_HALT
4642	\|\| rc == VINF_SUCCESS)
4643	{
4644	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3);
4645
4646	if ( rc == VINF_EM_HALT
4647	&& EMMonitorWaitShouldContinue(pVCpu, pCtx))
4648	{
4649	rc = VINF_SUCCESS;
4650	}
4651	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4652	}
4653	else
4654	{
4655	AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
4656	rc = VERR_EM_INTERPRETER;
4657	}
4658	AssertMsg(rc == VINF_SUCCESS \|\| rc == VINF_EM_HALT \|\| rc == VERR_EM_INTERPRETER,
4659	("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
4660	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
4661	return rc;
4662	}
4663
4664
4665	/**
4666	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
4667	* \#VMEXIT.
4668	*/
4669	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4670	{
4671	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4672	return VINF_EM_RESET;
4673	}
4674
4675
4676	/**
4677	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
4678	*/
4679	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4680	{
4681	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4682
4683	Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4684	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
4685
4686	PVM pVM = pVCpu->CTX_SUFF(pVM);
4687	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST)
4688	{
4689	Assert(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
4690	PCSVMVMCB pVmcb = (PCSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4691	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
4692	if (fMovCRx)
4693	{
4694	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
4695	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
4696	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
4697	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
4698	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
4699	return VBOXSTRICTRC_VAL(rcStrict);
4700	}
4701	/* else: SMSW instruction, fall back below to IEM for this. */
4702	}
4703
4704	VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4705	int rc = VBOXSTRICTRC_VAL(rc2);
4706	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_EM_INTERPRETER \|\| rc == VINF_PGM_CHANGE_MODE \|\| rc == VINF_PGM_SYNC_CR3,
4707	("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
4708	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
4709	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4710	return rc;
4711	}
4712
4713
4714	/**
4715	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
4716	*/
4717	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4718	{
4719	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4720
4721	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0;
4722	Assert(iCrReg <= 15);
4723
4724	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
4725	PVM pVM = pVCpu->CTX_SUFF(pVM);
4726	bool fDecodedInstr = false;
4727	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST)
4728	{
4729	Assert(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
4730	PCSVMVMCB pVmcb = (PCSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4731	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
4732	if (fMovCRx)
4733	{
4734	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
4735	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
4736	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
4737	fDecodedInstr = true;
4738	}
4739	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
4740	}
4741
4742	if (!fDecodedInstr)
4743	{
4744	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(pCtx), NULL);
4745	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
4746	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
4747	rcStrict = VERR_EM_INTERPRETER;
4748	}
4749
4750	if (rcStrict == VINF_SUCCESS)
4751	{
4752	switch (iCrReg)
4753	{
4754	case 0: /* CR0. */
4755	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
4756	break;
4757
4758	case 3: /* CR3. */
4759	Assert(!pVM->hm.s.fNestedPaging);
4760	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
4761	break;
4762
4763	case 4: /* CR4. */
4764	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
4765	break;
4766
4767	case 8: /* CR8 (TPR). */
4768	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4769	break;
4770
4771	default:
4772	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
4773	pSvmTransient->u64ExitCode, iCrReg));
4774	break;
4775	}
4776	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
4777	}
4778	else
4779	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_CHANGE_MODE \|\| rcStrict == VINF_PGM_SYNC_CR3);
4780	return VBOXSTRICTRC_TODO(rcStrict);
4781	}
4782
4783
4784	/**
4785	* \#VMEXIT handler for instructions that result in a \#UD exception delivered
4786	* to the guest.
4787	*/
4788	HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4789	{
4790	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4791	hmR0SvmSetPendingXcptUD(pVCpu);
4792	return VINF_SUCCESS;
4793	}
4794
4795
4796	/**
4797	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
4798	* \#VMEXIT.
4799	*/
4800	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4801	{
4802	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4803	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4804	PVM pVM = pVCpu->CTX_SUFF(pVM);
4805
4806	int rc;
4807	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4808	{
4809	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
4810
4811	/* Handle TPR patching; intercepted LSTAR write. */
4812	if ( pVM->hm.s.fTPRPatchingActive
4813	&& pCtx->ecx == MSR_K8_LSTAR)
4814	{
4815	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
4816	{
4817	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
4818	int rc2 = APICSetTpr(pVCpu, pCtx->eax & 0xff);
4819	AssertRC(rc2);
4820	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4821	}
4822	rc = VINF_SUCCESS;
4823	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 2);
4824	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4825	return rc;
4826	}
4827
4828	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4829	{
4830	rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4831	if (RT_LIKELY(rc == VINF_SUCCESS))
4832	{
4833	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4834	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4835	}
4836	else
4837	AssertMsg( rc == VERR_EM_INTERPRETER
4838	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
4839	}
4840	else
4841	{
4842	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
4843	if (RT_LIKELY(rc == VINF_SUCCESS))
4844	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc); /* RIP updated by EMInterpretInstruction(). */
4845	else
4846	AssertMsg( rc == VERR_EM_INTERPRETER
4847	\|\| rc == VINF_CPUM_R3_MSR_WRITE, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4848	}
4849
4850	if (rc == VINF_SUCCESS)
4851	{
4852	/* If this is an X2APIC WRMSR access, update the APIC state as well. */
4853	if ( pCtx->ecx >= MSR_IA32_X2APIC_START
4854	&& pCtx->ecx <= MSR_IA32_X2APIC_END)
4855	{
4856	/*
4857	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
4858	* virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
4859	* EMInterpretWrmsr() changes it.
4860	*/
4861	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4862	}
4863	else if (pCtx->ecx == MSR_K6_EFER)
4864	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
4865	else if (pCtx->ecx == MSR_IA32_TSC)
4866	pSvmTransient->fUpdateTscOffsetting = true;
4867	}
4868	}
4869	else
4870	{
4871	/* MSR Read access. */
4872	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
4873	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
4874
4875	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4876	{
4877	rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4878	if (RT_LIKELY(rc == VINF_SUCCESS))
4879	{
4880	pCtx->rip = pVmcb->ctrl.u64NextRIP;
4881	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4882	}
4883	else
4884	AssertMsg( rc == VERR_EM_INTERPRETER
4885	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
4886	}
4887	else
4888	{
4889	rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
4890	if (RT_UNLIKELY(rc != VINF_SUCCESS))
4891	{
4892	AssertMsg( rc == VERR_EM_INTERPRETER
4893	\|\| rc == VINF_CPUM_R3_MSR_READ, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4894	}
4895	/* RIP updated by EMInterpretInstruction(). */
4896	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4897	}
4898	}
4899
4900	/* RIP has been updated by EMInterpret[Rd\|Wr]msr(). */
4901	return rc;
4902	}
4903
4904
4905	/**
4906	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
4907	*/
4908	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4909	{
4910	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4911	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
4912
4913	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
4914	if (pSvmTransient->fWasGuestDebugStateActive)
4915	{
4916	AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
4917	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
4918	return VERR_SVM_UNEXPECTED_EXIT;
4919	}
4920
4921	/*
4922	* Lazy DR0-3 loading.
4923	*/
4924	if (!pSvmTransient->fWasHyperDebugStateActive)
4925	{
4926	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
4927	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
4928
4929	/* Don't intercept DRx read and writes. */
4930	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4931	pVmcb->ctrl.u16InterceptRdDRx = 0;
4932	pVmcb->ctrl.u16InterceptWrDRx = 0;
4933	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
4934
4935	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
4936	VMMRZCallRing3Disable(pVCpu);
4937	HM_DISABLE_PREEMPT();
4938
4939	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
4940	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
4941	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
4942
4943	HM_RESTORE_PREEMPT();
4944	VMMRZCallRing3Enable(pVCpu);
4945
4946	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
4947	return VINF_SUCCESS;
4948	}
4949
4950	/*
4951	* Interpret the read/writing of DRx.
4952	*/
4953	/** @todo Decode assist. */
4954	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4955	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
4956	if (RT_LIKELY(rc == VINF_SUCCESS))
4957	{
4958	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
4959	/** @todo CPUM should set this flag! */
4960	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
4961	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4962	}
4963	else
4964	Assert(rc == VERR_EM_INTERPRETER);
4965	return VBOXSTRICTRC_TODO(rc);
4966	}
4967
4968
4969	/**
4970	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
4971	*/
4972	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4973	{
4974	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4975	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
4976	int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
4977	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
4978	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
4979	return rc;
4980	}
4981
4982
4983	/**
4984	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
4985	*/
4986	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4987	{
4988	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4989
4990	/** @todo decode assists... */
4991	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
4992	if (rcStrict == VINF_IEM_RAISED_XCPT)
4993	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
4994
4995	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
4996	Log4(("hmR0SvmExitXsetbv: New XCR0=%#RX64 fLoadSaveGuestXcr0=%d (cr4=%RX64) rcStrict=%Rrc\n",
4997	pCtx->aXcr[0], pVCpu->hm.s.fLoadSaveGuestXcr0, pCtx->cr4, VBOXSTRICTRC_VAL(rcStrict)));
4998
4999	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5000	return VBOXSTRICTRC_TODO(rcStrict);
5001	}
5002
5003
5004	/**
5005	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
5006	*/
5007	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5008	{
5009	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5010
5011	/* I/O operation lookup arrays. */
5012	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
5013	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
5014	the result (in AL/AX/EAX). */
5015	Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
5016
5017	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5018	PVM pVM = pVCpu->CTX_SUFF(pVM);
5019
5020	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
5021	SVMIOIOEXITINFO IoExitInfo;
5022	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
5023	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
5024	uint32_t cbValue = s_aIOSize[uIOWidth];
5025	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
5026
5027	if (RT_UNLIKELY(!cbValue))
5028	{
5029	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
5030	return VERR_EM_INTERPRETER;
5031	}
5032
5033	VBOXSTRICTRC rcStrict;
5034	bool fUpdateRipAlready = false;
5035	if (IoExitInfo.n.u1STR)
5036	{
5037	#ifdef VBOX_WITH_2ND_IEM_STEP
5038	/* INS/OUTS - I/O String instruction. */
5039	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
5040	* in EXITINFO1? Investigate once this thing is up and running. */
5041	Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
5042	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
5043	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
5044	static IEMMODE const s_aenmAddrMode[8] =
5045	{
5046	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
5047	};
5048	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
5049	if (enmAddrMode != (IEMMODE)-1)
5050	{
5051	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
5052	if (cbInstr <= 15 && cbInstr >= 1)
5053	{
5054	Assert(cbInstr >= 1U + IoExitInfo.n.u1REP);
5055	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
5056	{
5057	/* Don't know exactly how to detect whether u3SEG is valid, currently
5058	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
5059	2384 Opterons when only checking NRIP. */
5060	if ( (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
5061	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
5062	{
5063	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1REP,
5064	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3SEG, cbInstr, IoExitInfo.n.u1REP));
5065	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
5066	IoExitInfo.n.u3SEG, true /fIoChecked/);
5067	}
5068	else if (cbInstr == 1U + IoExitInfo.n.u1REP)
5069	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
5070	X86_SREG_DS, true /fIoChecked/);
5071	else
5072	rcStrict = IEMExecOne(pVCpu);
5073	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
5074	}
5075	else
5076	{
5077	AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3SEG));
5078	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
5079	true /fIoChecked/);
5080	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
5081	}
5082	}
5083	else
5084	{
5085	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
5086	rcStrict = IEMExecOne(pVCpu);
5087	}
5088	}
5089	else
5090	{
5091	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
5092	rcStrict = IEMExecOne(pVCpu);
5093	}
5094	fUpdateRipAlready = true;
5095
5096	#else
5097	/* INS/OUTS - I/O String instruction. */
5098	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
5099
5100	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
5101	* in EXITINFO1? Investigate once this thing is up and running. */
5102
5103	rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
5104	if (rcStrict == VINF_SUCCESS)
5105	{
5106	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
5107	{
5108	rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
5109	(DISCPUMODE)pDis->uAddrMode, cbValue);
5110	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
5111	}
5112	else
5113	{
5114	rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
5115	(DISCPUMODE)pDis->uAddrMode, cbValue);
5116	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
5117	}
5118	}
5119	else
5120	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
5121	#endif
5122	}
5123	else
5124	{
5125	/* IN/OUT - I/O instruction. */
5126	Assert(!IoExitInfo.n.u1REP);
5127
5128	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
5129	{
5130	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
5131	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
5132	}
5133	else
5134	{
5135	uint32_t u32Val = 0;
5136	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
5137	if (IOM_SUCCESS(rcStrict))
5138	{
5139	/* Save result of I/O IN instr. in AL/AX/EAX. */
5140	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
5141	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
5142	}
5143	else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
5144	HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
5145
5146	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
5147	}
5148	}
5149
5150	if (IOM_SUCCESS(rcStrict))
5151	{
5152	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
5153	if (!fUpdateRipAlready)
5154	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
5155
5156	/*
5157	* If any I/O breakpoints are armed, we need to check if one triggered
5158	* and take appropriate action.
5159	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
5160	*/
5161	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
5162	* execution engines about whether hyper BPs and such are pending. */
5163	uint32_t const uDr7 = pCtx->dr[7];
5164	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
5165	&& X86_DR7_ANY_RW_IO(uDr7)
5166	&& (pCtx->cr4 & X86_CR4_DE))
5167	\|\| DBGFBpIsHwIoArmed(pVM)))
5168	{
5169	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
5170	VMMRZCallRing3Disable(pVCpu);
5171	HM_DISABLE_PREEMPT();
5172
5173	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
5174	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
5175
5176	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
5177	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
5178	{
5179	/* Raise #DB. */
5180	pVmcb->guest.u64DR6 = pCtx->dr[6];
5181	pVmcb->guest.u64DR7 = pCtx->dr[7];
5182	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
5183	hmR0SvmSetPendingXcptDB(pVCpu);
5184	}
5185	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
5186	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
5187	else if ( rcStrict2 != VINF_SUCCESS
5188	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
5189	rcStrict = rcStrict2;
5190	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
5191
5192	HM_RESTORE_PREEMPT();
5193	VMMRZCallRing3Enable(pVCpu);
5194	}
5195
5196	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
5197	}
5198
5199	#ifdef VBOX_STRICT
5200	if (rcStrict == VINF_IOM_R3_IOPORT_READ)
5201	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
5202	else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE \|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE)
5203	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
5204	else
5205	{
5206	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
5207	* statuses, that the VMM device and some others may return. See
5208	* IOM_SUCCESS() for guidance. */
5209	AssertMsg( RT_FAILURE(rcStrict)
5210	\|\| rcStrict == VINF_SUCCESS
5211	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
5212	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
5213	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
5214	\|\| rcStrict == VINF_EM_RAW_TO_R3
5215	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
5216	}
5217	#endif
5218	return VBOXSTRICTRC_TODO(rcStrict);
5219	}
5220
5221
5222	/**
5223	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
5224	*/
5225	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5226	{
5227	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5228	PVM pVM = pVCpu->CTX_SUFF(pVM);
5229	Assert(pVM->hm.s.fNestedPaging);
5230
5231	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5232
5233	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
5234	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5235	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
5236	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
5237
5238	Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
5239
5240	#ifdef VBOX_HM_WITH_GUEST_PATCHING
5241	/* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
5242	if ( pVM->hm.s.fTprPatchingAllowed
5243	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
5244	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
5245	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
5246	&& !CPUMIsGuestInLongModeEx(pCtx)
5247	&& !CPUMGetGuestCPL(pVCpu)
5248	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
5249	{
5250	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
5251	GCPhysApicBase &= PAGE_BASE_GC_MASK;
5252
5253	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
5254	{
5255	/* Only attempt to patch the instruction once. */
5256	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
5257	if (!pPatch)
5258	return VINF_EM_HM_PATCH_TPR_INSTR;
5259	}
5260	}
5261	#endif
5262
5263	/*
5264	* Determine the nested paging mode.
5265	*/
5266	PGMMODE enmNestedPagingMode;
5267	#if HC_ARCH_BITS == 32
5268	if (CPUMIsGuestInLongModeEx(pCtx))
5269	enmNestedPagingMode = PGMMODE_AMD64_NX;
5270	else
5271	#endif
5272	enmNestedPagingMode = PGMGetHostMode(pVM);
5273
5274	/*
5275	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
5276	*/
5277	int rc;
5278	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
5279	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
5280	{
5281	/* If event delivery causes an MMIO #NPF, go back to instruction emulation as
5282	otherwise injecting the original pending event would most likely cause the same MMIO #NPF. */
5283	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
5284	return VINF_EM_RAW_INJECT_TRPM_EVENT;
5285
5286	VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
5287	u32ErrCode);
5288	rc = VBOXSTRICTRC_VAL(rc2);
5289
5290	/*
5291	* If we succeed, resume guest execution.
5292	* If we fail in interpreting the instruction because we couldn't get the guest physical address
5293	* of the page containing the instruction via the guest's page tables (we would invalidate the guest page
5294	* in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
5295	* weird case. See @bugref{6043}.
5296	*/
5297	if ( rc == VINF_SUCCESS
5298	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
5299	\|\| rc == VERR_PAGE_NOT_PRESENT)
5300	{
5301	/* Successfully handled MMIO operation. */
5302	HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
5303	rc = VINF_SUCCESS;
5304	}
5305	return rc;
5306	}
5307
5308	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
5309	rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
5310	TRPMResetTrap(pVCpu);
5311
5312	Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
5313
5314	/*
5315	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
5316	*/
5317	if ( rc == VINF_SUCCESS
5318	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
5319	\|\| rc == VERR_PAGE_NOT_PRESENT)
5320	{
5321	/* We've successfully synced our shadow page tables. */
5322	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
5323	rc = VINF_SUCCESS;
5324	}
5325
5326	return rc;
5327	}
5328
5329
5330	/**
5331	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
5332	* \#VMEXIT.
5333	*/
5334	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5335	{
5336	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5337
5338	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5339	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 0; /* No virtual interrupts pending, we'll inject the current one/NMI before reentry. */
5340	pVmcb->ctrl.IntCtrl.n.u8VIntrVector = 0;
5341
5342	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive interrupts/NMIs, it is now ready. */
5343	pVmcb->ctrl.u64InterceptCtrl &= ~SVM_CTRL_INTERCEPT_VINTR;
5344	pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_TPR);
5345
5346	/* Deliver the pending interrupt/NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
5347	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
5348	return VINF_SUCCESS;
5349	}
5350
5351
5352	/**
5353	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
5354	* \#VMEXIT.
5355	*/
5356	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5357	{
5358	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5359
5360	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5361
5362	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
5363	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
5364	#endif
5365
5366	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
5367	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
5368	{
5369	/*
5370	* AMD-V provides us with the exception which caused the TS; we collect
5371	* the information in the call to hmR0SvmCheckExitDueToEventDelivery.
5372	*/
5373	Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery.\n"));
5374	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
5375	return VINF_EM_RAW_INJECT_TRPM_EVENT;
5376	}
5377
5378	/** @todo Emulate task switch someday, currently just going back to ring-3 for
5379	* emulation. */
5380	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
5381	return VERR_EM_INTERPRETER;
5382	}
5383
5384
5385	/**
5386	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
5387	*/
5388	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5389	{
5390	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5391	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmcall);
5392
5393	bool fRipUpdated;
5394	VBOXSTRICTRC rcStrict = HMSvmVmmcall(pVCpu, pCtx, &fRipUpdated);
5395	if (RT_SUCCESS(rcStrict))
5396	{
5397	if (!fRipUpdated)
5398	hmR0SvmAdvanceRipHwAssist(pVCpu, pCtx, 3 /* cbInstr */);
5399
5400	/* If the hypercall or TPR patching changes anything other than guest's general-purpose registers,
5401	we would need to reload the guest changed bits here before VM-entry. */
5402	return VBOXSTRICTRC_VAL(rcStrict);
5403	}
5404
5405	hmR0SvmSetPendingXcptUD(pVCpu);
5406	return VINF_SUCCESS;
5407	}
5408
5409
5410	/**
5411	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
5412	*/
5413	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5414	{
5415	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5416	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitPause);
5417	return VINF_EM_RAW_INTERRUPT;
5418	}
5419
5420
5421	/**
5422	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
5423	*/
5424	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5425	{
5426	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5427
5428	/* Clear NMI blocking. */
5429	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5430
5431	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
5432	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5433	hmR0SvmClearIretIntercept(pVmcb);
5434
5435	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
5436	return VINF_SUCCESS;
5437	}
5438
5439
5440	/**
5441	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_14).
5442	* Conditional \#VMEXIT.
5443	*/
5444	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5445	{
5446	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5447
5448	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5449
5450	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
5451	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5452	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
5453	RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
5454	PVM pVM = pVCpu->CTX_SUFF(pVM);
5455
5456	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
5457	if (pVM->hm.s.fNestedPaging)
5458	{
5459	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
5460	if (!pSvmTransient->fVectoringDoublePF)
5461	{
5462	/* A genuine guest #PF, reflect it to the guest. */
5463	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
5464	Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
5465	uFaultAddress, u32ErrCode));
5466	}
5467	else
5468	{
5469	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
5470	hmR0SvmSetPendingXcptDF(pVCpu);
5471	Log4(("Pending #DF due to vectoring #PF. NP\n"));
5472	}
5473	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
5474	return VINF_SUCCESS;
5475	}
5476	#endif
5477
5478	Assert(!pVM->hm.s.fNestedPaging);
5479
5480	#ifdef VBOX_HM_WITH_GUEST_PATCHING
5481	/* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
5482	if ( pVM->hm.s.fTprPatchingAllowed
5483	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
5484	&& !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
5485	&& !CPUMIsGuestInLongModeEx(pCtx)
5486	&& !CPUMGetGuestCPL(pVCpu)
5487	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
5488	{
5489	RTGCPHYS GCPhysApicBase;
5490	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
5491	GCPhysApicBase &= PAGE_BASE_GC_MASK;
5492
5493	/* Check if the page at the fault-address is the APIC base. */
5494	RTGCPHYS GCPhysPage;
5495	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
5496	if ( rc2 == VINF_SUCCESS
5497	&& GCPhysPage == GCPhysApicBase)
5498	{
5499	/* Only attempt to patch the instruction once. */
5500	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
5501	if (!pPatch)
5502	return VINF_EM_HM_PATCH_TPR_INSTR;
5503	}
5504	}
5505	#endif
5506
5507	Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
5508	pCtx->rip, u32ErrCode, pCtx->cr3));
5509
5510	/* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
5511	of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
5512	if (pSvmTransient->fVectoringPF)
5513	{
5514	Assert(pVCpu->hm.s.Event.fPending);
5515	return VINF_EM_RAW_INJECT_TRPM_EVENT;
5516	}
5517
5518	TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
5519	int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
5520
5521	Log4(("#PF rc=%Rrc\n", rc));
5522
5523	if (rc == VINF_SUCCESS)
5524	{
5525	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
5526	TRPMResetTrap(pVCpu);
5527	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
5528	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
5529	return rc;
5530	}
5531	else if (rc == VINF_EM_RAW_GUEST_TRAP)
5532	{
5533	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
5534
5535	if (!pSvmTransient->fVectoringDoublePF)
5536	{
5537	/* It's a guest page fault and needs to be reflected to the guest. */
5538	u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
5539	TRPMResetTrap(pVCpu);
5540	hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
5541	}
5542	else
5543	{
5544	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
5545	TRPMResetTrap(pVCpu);
5546	hmR0SvmSetPendingXcptDF(pVCpu);
5547	Log4(("#PF: Pending #DF due to vectoring #PF\n"));
5548	}
5549
5550	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
5551	return VINF_SUCCESS;
5552	}
5553
5554	TRPMResetTrap(pVCpu);
5555	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
5556	return rc;
5557	}
5558
5559
5560	/**
5561	* \#VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
5562	* Conditional \#VMEXIT.
5563	*/
5564	HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5565	{
5566	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5567
5568	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
5569	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb; NOREF(pVmcb);
5570	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid);
5571
5572	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
5573	VMMRZCallRing3Disable(pVCpu);
5574	HM_DISABLE_PREEMPT();
5575
5576	int rc;
5577	/* If the guest FPU was active at the time of the #NM exit, then it's a guest fault. */
5578	if (pSvmTransient->fWasGuestFPUStateActive)
5579	{
5580	rc = VINF_EM_RAW_GUEST_TRAP;
5581	Assert(CPUMIsGuestFPUStateActive(pVCpu) \|\| HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
5582	}
5583	else
5584	{
5585	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5586	Assert(!pSvmTransient->fWasGuestFPUStateActive);
5587	#endif
5588	rc = CPUMR0Trap07Handler(pVCpu->CTX_SUFF(pVM), pVCpu); /* (No need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
5589	Assert( rc == VINF_EM_RAW_GUEST_TRAP
5590	\|\| ((rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED) && CPUMIsGuestFPUStateActive(pVCpu)));
5591	}
5592
5593	HM_RESTORE_PREEMPT();
5594	VMMRZCallRing3Enable(pVCpu);
5595
5596	if (rc == VINF_SUCCESS \|\| rc == VINF_CPUM_HOST_CR0_MODIFIED)
5597	{
5598	/* Guest FPU state was activated, we'll want to change CR0 FPU intercepts before the next VM-reentry. */
5599	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
5600	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
5601	pVCpu->hm.s.fPreloadGuestFpu = true;
5602	}
5603	else
5604	{
5605	/* Forward #NM to the guest. */
5606	Assert(rc == VINF_EM_RAW_GUEST_TRAP);
5607	hmR0SvmSetPendingXcptNM(pVCpu);
5608	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
5609	}
5610	return VINF_SUCCESS;
5611	}
5612
5613
5614	/**
5615	* \#VMEXIT handler for undefined opcode (SVM_EXIT_EXCEPTION_6).
5616	* Conditional \#VMEXIT.
5617	*/
5618	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5619	{
5620	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5621
5622	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
5623	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb; NOREF(pVmcb);
5624	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid);
5625
5626	int rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
5627	if (pVCpu->hm.s.fGIMTrapXcptUD)
5628	{
5629	uint8_t cbInstr = 0;
5630	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, pCtx, NULL /* pDis */, &cbInstr);
5631	if (rcStrict == VINF_SUCCESS)
5632	{
5633	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
5634	hmR0SvmAdvanceRipDumb(pVCpu, pCtx, cbInstr);
5635	rc = VINF_SUCCESS;
5636	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5637	}
5638	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
5639	rc = VINF_SUCCESS;
5640	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
5641	rc = VINF_GIM_R3_HYPERCALL;
5642	else
5643	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
5644	}
5645
5646	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
5647	if (RT_FAILURE(rc))
5648	{
5649	hmR0SvmSetPendingXcptUD(pVCpu);
5650	rc = VINF_SUCCESS;
5651	}
5652
5653	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
5654	return rc;
5655	}
5656
5657
5658	/**
5659	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_16).
5660	* Conditional \#VMEXIT.
5661	*/
5662	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5663	{
5664	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5665
5666	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
5667	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb; NOREF(pVmcb);
5668	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid);
5669
5670	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
5671
5672	if (!(pCtx->cr0 & X86_CR0_NE))
5673	{
5674	PVM pVM = pVCpu->CTX_SUFF(pVM);
5675	PDISSTATE pDis = &pVCpu->hm.s.DisState;
5676	unsigned cbOp;
5677	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
5678	if (RT_SUCCESS(rc))
5679	{
5680	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
5681	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
5682	if (RT_SUCCESS(rc))
5683	pCtx->rip += cbOp;
5684	}
5685	else
5686	Log4(("hmR0SvmExitXcptMF: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
5687	return rc;
5688	}
5689
5690	hmR0SvmSetPendingXcptMF(pVCpu);
5691	return VINF_SUCCESS;
5692	}
5693
5694
5695	/**
5696	* \#VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
5697	* \#VMEXIT.
5698	*/
5699	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5700	{
5701	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5702
5703	/* If this #DB is the result of delivering an event, go back to the interpreter. */
5704	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5705	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
5706	{
5707	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
5708	return VINF_EM_RAW_INJECT_TRPM_EVENT;
5709	}
5710
5711	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
5712
5713	/* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
5714	DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
5715	PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5716	PVM pVM = pVCpu->CTX_SUFF(pVM);
5717	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
5718	if (rc == VINF_EM_RAW_GUEST_TRAP)
5719	{
5720	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
5721	if (CPUMIsHyperDebugStateActive(pVCpu))
5722	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
5723
5724	/* Reflect the exception back to the guest. */
5725	hmR0SvmSetPendingXcptDB(pVCpu);
5726	rc = VINF_SUCCESS;
5727	}
5728
5729	/*
5730	* Update DR6.
5731	*/
5732	if (CPUMIsHyperDebugStateActive(pVCpu))
5733	{
5734	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
5735	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
5736	pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
5737	}
5738	else
5739	{
5740	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
5741	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
5742	}
5743
5744	return rc;
5745	}
5746
5747
5748	/**
5749	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_EXCEPTION_17).
5750	* Conditional \#VMEXIT.
5751	*/
5752	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5753	{
5754	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5755
5756	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5757
5758	SVMEVENT Event;
5759	Event.u = 0;
5760	Event.n.u1Valid = 1;
5761	Event.n.u3Type = SVM_EVENT_EXCEPTION;
5762	Event.n.u8Vector = X86_XCPT_AC;
5763	Event.n.u1ErrorCodeValid = 1;
5764	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
5765	return VINF_SUCCESS;
5766	}
5767
5768
5769	/**
5770	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_EXCEPTION_3).
5771	* Conditional \#VMEXIT.
5772	*/
5773	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5774	{
5775	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5776
5777	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5778
5779	int rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
5780	if (rc == VINF_EM_RAW_GUEST_TRAP)
5781	{
5782	SVMEVENT Event;
5783	Event.u = 0;
5784	Event.n.u1Valid = 1;
5785	Event.n.u3Type = SVM_EVENT_EXCEPTION;
5786	Event.n.u8Vector = X86_XCPT_BP;
5787	Event.n.u1ErrorCodeValid = 0;
5788	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
5789	}
5790
5791	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_EM_DBG_BREAKPOINT);
5792	return rc;
5793	}
5794
5795
5796	#ifdef VBOX_WITH_NESTED_HWVIRT
5797	/**
5798	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
5799	*/
5800	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5801	{
5802	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5803	/** @todo Stat. */
5804	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitClgi); */
5805	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
5806	VBOXSTRICTRC rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
5807	return VBOXSTRICTRC_VAL(rcStrict);
5808	}
5809
5810
5811	/**
5812	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
5813	*/
5814	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5815	{
5816	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5817	/** @todo Stat. */
5818	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitStgi); */
5819	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
5820	VBOXSTRICTRC rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
5821	return VBOXSTRICTRC_VAL(rcStrict);
5822	}
5823
5824
5825	/**
5826	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
5827	*/
5828	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5829	{
5830	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5831	/** @todo Stat. */
5832	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmload); */
5833	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
5834	VBOXSTRICTRC rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
5835	return VBOXSTRICTRC_VAL(rcStrict);
5836	}
5837
5838
5839	/**
5840	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
5841	*/
5842	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5843	{
5844	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5845	/** @todo Stat. */
5846	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmsave); */
5847	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
5848	VBOXSTRICTRC rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
5849	return VBOXSTRICTRC_VAL(rcStrict);
5850	}
5851
5852
5853	/**
5854	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
5855	*/
5856	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5857	{
5858	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5859	/** @todo Stat. */
5860	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpga); */
5861	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
5862	VBOXSTRICTRC rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
5863	return VBOXSTRICTRC_VAL(rcStrict);
5864	}
5865
5866
5867	/**
5868	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
5869	*/
5870	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5871	{
5872	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5873	/** @todo Stat. */
5874	/* STAM_COUNTER_INC(&pVCpu->hm.s.StatExitVmrun); */
5875	uint8_t const cbInstr = hmR0SvmGetInstrLengthHwAssist(pVCpu, pCtx, 3);
5876	VBOXSTRICTRC rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
5877	return VBOXSTRICTRC_VAL(rcStrict);
5878	}
5879	#endif /* VBOX_WITH_NESTED_HWVIRT */
5880
5881
5882	/** @} */
5883

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 67837

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