VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 54102

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1/* $Id: HMSVMR0.cpp 54102 2015-02-06 18:04:25Z vboxsync $ */
2/** @file
3 * HM SVM (AMD-V) - Host Context Ring-0.
4 */
5
6/*
7 * Copyright (C) 2013-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HM
22#include <iprt/asm-amd64-x86.h>
23#include <iprt/thread.h>
24
25#include "HMInternal.h"
26#include <VBox/vmm/vm.h>
27#include "HMSVMR0.h"
28#include <VBox/vmm/pdmapi.h>
29#include <VBox/vmm/dbgf.h>
30#include <VBox/vmm/iom.h>
31#include <VBox/vmm/tm.h>
32#include <VBox/vmm/gim.h>
33#include "dtrace/VBoxVMM.h"
34
35#ifdef DEBUG_ramshankar
36# define HMSVM_SYNC_FULL_GUEST_STATE
37# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
38# define HMSVM_ALWAYS_TRAP_PF
39# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
40#endif
41
42
43/*******************************************************************************
44* Defined Constants And Macros *
45*******************************************************************************/
46#ifdef VBOX_WITH_STATISTICS
47# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
48 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
49 if ((u64ExitCode) == SVM_EXIT_NPF) \
50 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
51 else \
52 STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
53 } while (0)
54#else
55# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
56#endif
57
58/** If we decide to use a function table approach this can be useful to
59 * switch to a "static DECLCALLBACK(int)". */
60#define HMSVM_EXIT_DECL static int
61
62/** @name Segment attribute conversion between CPU and AMD-V VMCB format.
63 *
64 * The CPU format of the segment attribute is described in X86DESCATTRBITS
65 * which is 16-bits (i.e. includes 4 bits of the segment limit).
66 *
67 * The AMD-V VMCB format the segment attribute is compact 12-bits (strictly
68 * only the attribute bits and nothing else). Upper 4-bits are unused.
69 *
70 * @{ */
71#define HMSVM_CPU_2_VMCB_SEG_ATTR(a) ( ((a) & 0xff) | (((a) & 0xf000) >> 4) )
72#define HMSVM_VMCB_2_CPU_SEG_ATTR(a) ( ((a) & 0xff) | (((a) & 0x0f00) << 4) )
73/** @} */
74
75/** @name Macros for loading, storing segment registers to/from the VMCB.
76 * @{ */
77#define HMSVM_LOAD_SEG_REG(REG, reg) \
78 do \
79 { \
80 Assert(pCtx->reg.fFlags & CPUMSELREG_FLAGS_VALID); \
81 Assert(pCtx->reg.ValidSel == pCtx->reg.Sel); \
82 pVmcb->guest.REG.u16Sel = pCtx->reg.Sel; \
83 pVmcb->guest.REG.u32Limit = pCtx->reg.u32Limit; \
84 pVmcb->guest.REG.u64Base = pCtx->reg.u64Base; \
85 pVmcb->guest.REG.u16Attr = HMSVM_CPU_2_VMCB_SEG_ATTR(pCtx->reg.Attr.u); \
86 } while (0)
87
88#define HMSVM_SAVE_SEG_REG(REG, reg) \
89 do \
90 { \
91 pMixedCtx->reg.Sel = pVmcb->guest.REG.u16Sel; \
92 pMixedCtx->reg.ValidSel = pVmcb->guest.REG.u16Sel; \
93 pMixedCtx->reg.fFlags = CPUMSELREG_FLAGS_VALID; \
94 pMixedCtx->reg.u32Limit = pVmcb->guest.REG.u32Limit; \
95 pMixedCtx->reg.u64Base = pVmcb->guest.REG.u64Base; \
96 pMixedCtx->reg.Attr.u = HMSVM_VMCB_2_CPU_SEG_ATTR(pVmcb->guest.REG.u16Attr); \
97 } while (0)
98/** @} */
99
100/** Macro for checking and returning from the using function for
101 * \#VMEXIT intercepts that maybe caused during delivering of another
102 * event in the guest. */
103#define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY() \
104 do \
105 { \
106 int rc = hmR0SvmCheckExitDueToEventDelivery(pVCpu, pCtx, pSvmTransient); \
107 if (RT_UNLIKELY(rc == VINF_HM_DOUBLE_FAULT)) \
108 return VINF_SUCCESS; \
109 else if (RT_UNLIKELY(rc == VINF_EM_RESET)) \
110 return rc; \
111 } while (0)
112
113/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
114 * instruction that exited. */
115#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
116 do { \
117 if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
118 (a_rc) = VINF_EM_DBG_STEPPED; \
119 } while (0)
120
121/** Assert that preemption is disabled or covered by thread-context hooks. */
122#define HMSVM_ASSERT_PREEMPT_SAFE() Assert( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
123 || !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
124
125/** Assert that we haven't migrated CPUs when thread-context hooks are not
126 * used. */
127#define HMSVM_ASSERT_CPU_SAFE() AssertMsg( VMMR0ThreadCtxHooksAreRegistered(pVCpu) \
128 || pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
129 ("Illegal migration! Entered on CPU %u Current %u\n", \
130 pVCpu->hm.s.idEnteredCpu, RTMpCpuId()));
131
132/** Exception bitmap mask for all contributory exceptions.
133 *
134 * Page fault is deliberately excluded here as it's conditional as to whether
135 * it's contributory or benign. Page faults are handled separately.
136 */
137#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_TS) \
138 | RT_BIT(X86_XCPT_DE))
139
140/** @name VMCB Clean Bits.
141 *
142 * These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
143 * AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
144 * memory.
145 *
146 * @{ */
147/** All intercepts vectors, TSC offset, PAUSE filter counter. */
148#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
149/** I/O permission bitmap, MSR permission bitmap. */
150#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
151/** ASID. */
152#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
153/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
154V_INTR_VECTOR. */
155#define HMSVM_VMCB_CLEAN_TPR RT_BIT(3)
156/** Nested Paging: Nested CR3 (nCR3), PAT. */
157#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
158/** Control registers (CR0, CR3, CR4, EFER). */
159#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
160/** Debug registers (DR6, DR7). */
161#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
162/** GDT, IDT limit and base. */
163#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
164/** Segment register: CS, SS, DS, ES limit and base. */
165#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
166/** CR2.*/
167#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
168/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
169#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
170/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
171PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
172#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
173/** Mask of all valid VMCB Clean bits. */
174#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
175 | HMSVM_VMCB_CLEAN_IOPM_MSRPM \
176 | HMSVM_VMCB_CLEAN_ASID \
177 | HMSVM_VMCB_CLEAN_TPR \
178 | HMSVM_VMCB_CLEAN_NP \
179 | HMSVM_VMCB_CLEAN_CRX_EFER \
180 | HMSVM_VMCB_CLEAN_DRX \
181 | HMSVM_VMCB_CLEAN_DT \
182 | HMSVM_VMCB_CLEAN_SEG \
183 | HMSVM_VMCB_CLEAN_CR2 \
184 | HMSVM_VMCB_CLEAN_LBR \
185 | HMSVM_VMCB_CLEAN_AVIC)
186/** @} */
187
188/** @name SVM transient.
189 *
190 * A state structure for holding miscellaneous information across AMD-V
191 * VMRUN/#VMEXIT operation, restored after the transition.
192 *
193 * @{ */
194typedef struct SVMTRANSIENT
195{
196 /** The host's rflags/eflags. */
197 RTCCUINTREG uEflags;
198#if HC_ARCH_BITS == 32
199 uint32_t u32Alignment0;
200#endif
201
202 /** The #VMEXIT exit code (the EXITCODE field in the VMCB). */
203 uint64_t u64ExitCode;
204 /** The guest's TPR value used for TPR shadowing. */
205 uint8_t u8GuestTpr;
206 /** Alignment. */
207 uint8_t abAlignment0[7];
208
209 /** Whether the guest FPU state was active at the time of #VMEXIT. */
210 bool fWasGuestFPUStateActive;
211 /** Whether the guest debug state was active at the time of #VMEXIT. */
212 bool fWasGuestDebugStateActive;
213 /** Whether the hyper debug state was active at the time of #VMEXIT. */
214 bool fWasHyperDebugStateActive;
215 /** Whether the TSC offset mode needs to be updated. */
216 bool fUpdateTscOffsetting;
217 /** Whether the TSC_AUX MSR needs restoring on #VMEXIT. */
218 bool fRestoreTscAuxMsr;
219 /** Whether the #VMEXIT was caused by a page-fault during delivery of a
220 * contributary exception or a page-fault. */
221 bool fVectoringDoublePF;
222 /** Whether the #VMEXIT was caused by a page-fault during delivery of an
223 * external interrupt or NMI. */
224 bool fVectoringPF;
225} SVMTRANSIENT, *PSVMTRANSIENT;
226AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
227AssertCompileMemberAlignment(SVMTRANSIENT, fWasGuestFPUStateActive, sizeof(uint64_t));
228/** @} */
229
230/**
231 * MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
232 */
233typedef enum SVMMSREXITREAD
234{
235 /** Reading this MSR causes a #VMEXIT. */
236 SVMMSREXIT_INTERCEPT_READ = 0xb,
237 /** Reading this MSR does not cause a #VMEXIT. */
238 SVMMSREXIT_PASSTHRU_READ
239} SVMMSREXITREAD;
240
241/**
242 * MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
243 */
244typedef enum SVMMSREXITWRITE
245{
246 /** Writing to this MSR causes a #VMEXIT. */
247 SVMMSREXIT_INTERCEPT_WRITE = 0xd,
248 /** Writing to this MSR does not cause a #VMEXIT. */
249 SVMMSREXIT_PASSTHRU_WRITE
250} SVMMSREXITWRITE;
251
252/**
253 * SVM #VMEXIT handler.
254 *
255 * @returns VBox status code.
256 * @param pVCpu Pointer to the VMCPU.
257 * @param pMixedCtx Pointer to the guest-CPU context.
258 * @param pSvmTransient Pointer to the SVM-transient structure.
259 */
260typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient);
261
262/*******************************************************************************
263* Internal Functions *
264*******************************************************************************/
265static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite);
266static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
267static void hmR0SvmLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
268
269/** @name #VMEXIT handlers.
270 * @{
271 */
272static FNSVMEXITHANDLER hmR0SvmExitIntr;
273static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
274static FNSVMEXITHANDLER hmR0SvmExitInvd;
275static FNSVMEXITHANDLER hmR0SvmExitCpuid;
276static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
277static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
278static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
279static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
280static FNSVMEXITHANDLER hmR0SvmExitHlt;
281static FNSVMEXITHANDLER hmR0SvmExitMonitor;
282static FNSVMEXITHANDLER hmR0SvmExitMwait;
283static FNSVMEXITHANDLER hmR0SvmExitShutdown;
284static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
285static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
286static FNSVMEXITHANDLER hmR0SvmExitSetPendingXcptUD;
287static FNSVMEXITHANDLER hmR0SvmExitMsr;
288static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
289static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
290static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
291static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
292static FNSVMEXITHANDLER hmR0SvmExitVIntr;
293static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
294static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
295static FNSVMEXITHANDLER hmR0SvmExitIret;
296static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
297static FNSVMEXITHANDLER hmR0SvmExitXcptNM;
298static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
299static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
300/** @} */
301
302DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient);
303
304/*******************************************************************************
305* Global Variables *
306*******************************************************************************/
307/** Ring-0 memory object for the IO bitmap. */
308RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
309/** Physical address of the IO bitmap. */
310RTHCPHYS g_HCPhysIOBitmap = 0;
311/** Virtual address of the IO bitmap. */
312R0PTRTYPE(void *) g_pvIOBitmap = NULL;
313
314
315/**
316 * Sets up and activates AMD-V on the current CPU.
317 *
318 * @returns VBox status code.
319 * @param pCpu Pointer to the CPU info struct.
320 * @param pVM Pointer to the VM (can be NULL after a resume!).
321 * @param pvCpuPage Pointer to the global CPU page.
322 * @param HCPhysCpuPage Physical address of the global CPU page.
323 * @param fEnabledByHost Whether the host OS has already initialized AMD-V.
324 * @param pvArg Unused on AMD-V.
325 */
326VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
327 void *pvArg)
328{
329 Assert(!fEnabledByHost);
330 Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
331 Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
332 Assert(pvCpuPage);
333 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
334
335 NOREF(pvArg);
336 NOREF(fEnabledByHost);
337
338 /* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
339 RTCCUINTREG uEflags = ASMIntDisableFlags();
340
341 /*
342 * We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
343 */
344 uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
345 if (u64HostEfer & MSR_K6_EFER_SVME)
346 {
347 /* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
348 if ( pVM
349 && pVM->hm.s.svm.fIgnoreInUseError)
350 {
351 pCpu->fIgnoreAMDVInUseError = true;
352 }
353
354 if (!pCpu->fIgnoreAMDVInUseError)
355 {
356 ASMSetFlags(uEflags);
357 return VERR_SVM_IN_USE;
358 }
359 }
360
361 /* Turn on AMD-V in the EFER MSR. */
362 ASMWrMsr(MSR_K6_EFER, u64HostEfer | MSR_K6_EFER_SVME);
363
364 /* Write the physical page address where the CPU will store the host state while executing the VM. */
365 ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
366
367 /* Restore interrupts. */
368 ASMSetFlags(uEflags);
369
370 /*
371 * Theoretically, other hypervisors may have used ASIDs, ideally we should flush all non-zero ASIDs
372 * when enabling SVM. AMD doesn't have an SVM instruction to flush all ASIDs (flushing is done
373 * upon VMRUN). Therefore, just set the fFlushAsidBeforeUse flag which instructs hmR0SvmSetupTLB()
374 * to flush the TLB with before using a new ASID.
375 */
376 pCpu->fFlushAsidBeforeUse = true;
377
378 /*
379 * Ensure each VCPU scheduled on this CPU gets a new VPID on resume. See @bugref{6255}.
380 */
381 ++pCpu->cTlbFlushes;
382
383 return VINF_SUCCESS;
384}
385
386
387/**
388 * Deactivates AMD-V on the current CPU.
389 *
390 * @returns VBox status code.
391 * @param pCpu Pointer to the CPU info struct.
392 * @param pvCpuPage Pointer to the global CPU page.
393 * @param HCPhysCpuPage Physical address of the global CPU page.
394 */
395VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
396{
397 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
398 AssertReturn( HCPhysCpuPage
399 && HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
400 AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
401 NOREF(pCpu);
402
403 /* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
404 RTCCUINTREG uEflags = ASMIntDisableFlags();
405
406 /* Turn off AMD-V in the EFER MSR. */
407 uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
408 ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
409
410 /* Invalidate host state physical address. */
411 ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
412
413 /* Restore interrupts. */
414 ASMSetFlags(uEflags);
415
416 return VINF_SUCCESS;
417}
418
419
420/**
421 * Does global AMD-V initialization (called during module initialization).
422 *
423 * @returns VBox status code.
424 */
425VMMR0DECL(int) SVMR0GlobalInit(void)
426{
427 /*
428 * Allocate 12 KB for the IO bitmap. Since this is non-optional and we always intercept all IO accesses, it's done
429 * once globally here instead of per-VM.
430 */
431 Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
432 int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, 3 << PAGE_SHIFT, false /* fExecutable */);
433 if (RT_FAILURE(rc))
434 return rc;
435
436 g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
437 g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
438
439 /* Set all bits to intercept all IO accesses. */
440 ASMMemFill32(g_pvIOBitmap, 3 << PAGE_SHIFT, UINT32_C(0xffffffff));
441 return VINF_SUCCESS;
442}
443
444
445/**
446 * Does global AMD-V termination (called during module termination).
447 */
448VMMR0DECL(void) SVMR0GlobalTerm(void)
449{
450 if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
451 {
452 RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
453 g_pvIOBitmap = NULL;
454 g_HCPhysIOBitmap = 0;
455 g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
456 }
457}
458
459
460/**
461 * Frees any allocated per-VCPU structures for a VM.
462 *
463 * @param pVM Pointer to the VM.
464 */
465DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
466{
467 for (uint32_t i = 0; i < pVM->cCpus; i++)
468 {
469 PVMCPU pVCpu = &pVM->aCpus[i];
470 AssertPtr(pVCpu);
471
472 if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
473 {
474 RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
475 pVCpu->hm.s.svm.pvVmcbHost = 0;
476 pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
477 pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
478 }
479
480 if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
481 {
482 RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
483 pVCpu->hm.s.svm.pvVmcb = 0;
484 pVCpu->hm.s.svm.HCPhysVmcb = 0;
485 pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
486 }
487
488 if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
489 {
490 RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
491 pVCpu->hm.s.svm.pvMsrBitmap = 0;
492 pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
493 pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
494 }
495 }
496}
497
498
499/**
500 * Does per-VM AMD-V initialization.
501 *
502 * @returns VBox status code.
503 * @param pVM Pointer to the VM.
504 */
505VMMR0DECL(int) SVMR0InitVM(PVM pVM)
506{
507 int rc = VERR_INTERNAL_ERROR_5;
508
509 /*
510 * Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
511 */
512 uint32_t u32Family;
513 uint32_t u32Model;
514 uint32_t u32Stepping;
515 if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
516 {
517 Log4(("SVMR0InitVM: AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
518 pVM->hm.s.svm.fAlwaysFlushTLB = true;
519 }
520
521 /*
522 * Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
523 */
524 for (VMCPUID i = 0; i < pVM->cCpus; i++)
525 {
526 PVMCPU pVCpu = &pVM->aCpus[i];
527 pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
528 pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
529 pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
530 }
531
532 for (VMCPUID i = 0; i < pVM->cCpus; i++)
533 {
534 PVMCPU pVCpu = &pVM->aCpus[i];
535
536 /*
537 * Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
538 * FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
539 */
540 rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, 1 << PAGE_SHIFT, false /* fExecutable */);
541 if (RT_FAILURE(rc))
542 goto failure_cleanup;
543
544 pVCpu->hm.s.svm.pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
545 pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
546 Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
547 ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcbHost);
548
549 /*
550 * Allocate one page for the guest-state VMCB.
551 */
552 rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, 1 << PAGE_SHIFT, false /* fExecutable */);
553 if (RT_FAILURE(rc))
554 goto failure_cleanup;
555
556 pVCpu->hm.s.svm.pvVmcb = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
557 pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
558 Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
559 ASMMemZeroPage(pVCpu->hm.s.svm.pvVmcb);
560
561 /*
562 * Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
563 * SVM to not require one.
564 */
565 rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, 2 << PAGE_SHIFT, false /* fExecutable */);
566 if (RT_FAILURE(rc))
567 goto failure_cleanup;
568
569 pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
570 pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
571 /* Set all bits to intercept all MSR accesses (changed later on). */
572 ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, 2 << PAGE_SHIFT, UINT32_C(0xffffffff));
573 }
574
575 return VINF_SUCCESS;
576
577failure_cleanup:
578 hmR0SvmFreeStructs(pVM);
579 return rc;
580}
581
582
583/**
584 * Does per-VM AMD-V termination.
585 *
586 * @returns VBox status code.
587 * @param pVM Pointer to the VM.
588 */
589VMMR0DECL(int) SVMR0TermVM(PVM pVM)
590{
591 hmR0SvmFreeStructs(pVM);
592 return VINF_SUCCESS;
593}
594
595
596/**
597 * Sets the permission bits for the specified MSR in the MSRPM.
598 *
599 * @param pVCpu Pointer to the VMCPU.
600 * @param uMsr The MSR for which the access permissions are being set.
601 * @param enmRead MSR read permissions.
602 * @param enmWrite MSR write permissions.
603 */
604static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, unsigned uMsr, SVMMSREXITREAD enmRead, SVMMSREXITWRITE enmWrite)
605{
606 unsigned ulBit;
607 uint8_t *pbMsrBitmap = (uint8_t *)pVCpu->hm.s.svm.pvMsrBitmap;
608
609 /*
610 * Layout:
611 * Byte offset MSR range
612 * 0x000 - 0x7ff 0x00000000 - 0x00001fff
613 * 0x800 - 0xfff 0xc0000000 - 0xc0001fff
614 * 0x1000 - 0x17ff 0xc0010000 - 0xc0011fff
615 * 0x1800 - 0x1fff Reserved
616 */
617 if (uMsr <= 0x00001FFF)
618 {
619 /* Pentium-compatible MSRs. */
620 ulBit = uMsr * 2;
621 }
622 else if ( uMsr >= 0xC0000000
623 && uMsr <= 0xC0001FFF)
624 {
625 /* AMD Sixth Generation x86 Processor MSRs. */
626 ulBit = (uMsr - 0xC0000000) * 2;
627 pbMsrBitmap += 0x800;
628 }
629 else if ( uMsr >= 0xC0010000
630 && uMsr <= 0xC0011FFF)
631 {
632 /* AMD Seventh and Eighth Generation Processor MSRs. */
633 ulBit = (uMsr - 0xC0001000) * 2;
634 pbMsrBitmap += 0x1000;
635 }
636 else
637 {
638 AssertFailed();
639 return;
640 }
641
642 Assert(ulBit < 0x3fff /* 16 * 1024 - 1 */);
643 if (enmRead == SVMMSREXIT_INTERCEPT_READ)
644 ASMBitSet(pbMsrBitmap, ulBit);
645 else
646 ASMBitClear(pbMsrBitmap, ulBit);
647
648 if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
649 ASMBitSet(pbMsrBitmap, ulBit + 1);
650 else
651 ASMBitClear(pbMsrBitmap, ulBit + 1);
652
653 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
654 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
655}
656
657
658/**
659 * Sets up AMD-V for the specified VM.
660 * This function is only called once per-VM during initalization.
661 *
662 * @returns VBox status code.
663 * @param pVM Pointer to the VM.
664 */
665VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
666{
667 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
668 AssertReturn(pVM, VERR_INVALID_PARAMETER);
669 Assert(pVM->hm.s.svm.fSupported);
670
671 for (VMCPUID i = 0; i < pVM->cCpus; i++)
672 {
673 PVMCPU pVCpu = &pVM->aCpus[i];
674 PSVMVMCB pVmcb = (PSVMVMCB)pVM->aCpus[i].hm.s.svm.pvVmcb;
675
676 AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
677
678 /* Initialize the #VMEXIT history array with end-of-array markers (UINT16_MAX). */
679 Assert(!pVCpu->hm.s.idxExitHistoryFree);
680 HMCPU_EXIT_HISTORY_RESET(pVCpu);
681
682 /* Trap exceptions unconditionally (debug purposes). */
683#ifdef HMSVM_ALWAYS_TRAP_PF
684 pVmcb->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_PF);
685#endif
686#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
687 /* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
688 pVmcb->ctrl.u32InterceptException |= 0
689 | RT_BIT(X86_XCPT_BP)
690 | RT_BIT(X86_XCPT_DB)
691 | RT_BIT(X86_XCPT_DE)
692 | RT_BIT(X86_XCPT_NM)
693 | RT_BIT(X86_XCPT_UD)
694 | RT_BIT(X86_XCPT_NP)
695 | RT_BIT(X86_XCPT_SS)
696 | RT_BIT(X86_XCPT_GP)
697 | RT_BIT(X86_XCPT_PF)
698 | RT_BIT(X86_XCPT_MF)
699 ;
700#endif
701
702 /* Set up unconditional intercepts and conditions. */
703 pVmcb->ctrl.u32InterceptCtrl1 = SVM_CTRL1_INTERCEPT_INTR /* External interrupt causes a #VMEXIT. */
704 | SVM_CTRL1_INTERCEPT_NMI /* Non-maskable interrupts causes a #VMEXIT. */
705 | SVM_CTRL1_INTERCEPT_INIT /* INIT signal causes a #VMEXIT. */
706 | SVM_CTRL1_INTERCEPT_RDPMC /* RDPMC causes a #VMEXIT. */
707 | SVM_CTRL1_INTERCEPT_CPUID /* CPUID causes a #VMEXIT. */
708 | SVM_CTRL1_INTERCEPT_RSM /* RSM causes a #VMEXIT. */
709 | SVM_CTRL1_INTERCEPT_HLT /* HLT causes a #VMEXIT. */
710 | SVM_CTRL1_INTERCEPT_INOUT_BITMAP /* Use the IOPM to cause IOIO #VMEXITs. */
711 | SVM_CTRL1_INTERCEPT_MSR_SHADOW /* MSR access not covered by MSRPM causes a #VMEXIT.*/
712 | SVM_CTRL1_INTERCEPT_INVLPGA /* INVLPGA causes a #VMEXIT. */
713 | SVM_CTRL1_INTERCEPT_SHUTDOWN /* Shutdown events causes a #VMEXIT. */
714 | SVM_CTRL1_INTERCEPT_FERR_FREEZE; /* Intercept "freezing" during legacy FPU handling. */
715
716 pVmcb->ctrl.u32InterceptCtrl2 = SVM_CTRL2_INTERCEPT_VMRUN /* VMRUN causes a #VMEXIT. */
717 | SVM_CTRL2_INTERCEPT_VMMCALL /* VMMCALL causes a #VMEXIT. */
718 | SVM_CTRL2_INTERCEPT_VMLOAD /* VMLOAD causes a #VMEXIT. */
719 | SVM_CTRL2_INTERCEPT_VMSAVE /* VMSAVE causes a #VMEXIT. */
720 | SVM_CTRL2_INTERCEPT_STGI /* STGI causes a #VMEXIT. */
721 | SVM_CTRL2_INTERCEPT_CLGI /* CLGI causes a #VMEXIT. */
722 | SVM_CTRL2_INTERCEPT_SKINIT /* SKINIT causes a #VMEXIT. */
723 | SVM_CTRL2_INTERCEPT_WBINVD /* WBINVD causes a #VMEXIT. */
724 | SVM_CTRL2_INTERCEPT_MONITOR /* MONITOR causes a #VMEXIT. */
725 | SVM_CTRL2_INTERCEPT_MWAIT; /* MWAIT causes a #VMEXIT. */
726
727 /* CR0, CR4 reads must be intercepted, our shadow values are not necessarily the same as the guest's. */
728 pVmcb->ctrl.u16InterceptRdCRx = RT_BIT(0) | RT_BIT(4);
729
730 /* CR0, CR4 writes must be intercepted for the same reasons as above. */
731 pVmcb->ctrl.u16InterceptWrCRx = RT_BIT(0) | RT_BIT(4);
732
733 /* Intercept all DRx reads and writes by default. Changed later on. */
734 pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
735 pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
736
737 /* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
738 pVmcb->ctrl.IntCtrl.n.u1VIrqMasking = 1;
739
740 /* Ignore the priority in the TPR. This is necessary for delivering PIC style (ExtInt) interrupts and we currently
741 deliver both PIC and APIC interrupts alike. See hmR0SvmInjectPendingEvent() */
742 pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR = 1;
743
744 /* Set IO and MSR bitmap permission bitmap physical addresses. */
745 pVmcb->ctrl.u64IOPMPhysAddr = g_HCPhysIOBitmap;
746 pVmcb->ctrl.u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
747
748 /* No LBR virtualization. */
749 pVmcb->ctrl.u64LBRVirt = 0;
750
751 /* Initially set all VMCB clean bits to 0 indicating that everything should be loaded from the VMCB in memory. */
752 pVmcb->ctrl.u64VmcbCleanBits = 0;
753
754 /* The host ASID MBZ, for the guest start with 1. */
755 pVmcb->ctrl.TLBCtrl.n.u32ASID = 1;
756
757 /*
758 * Setup the PAT MSR (applicable for Nested Paging only).
759 * The default value should be 0x0007040600070406ULL, but we want to treat all guest memory as WB,
760 * so choose type 6 for all PAT slots.
761 */
762 pVmcb->guest.u64GPAT = UINT64_C(0x0006060606060606);
763
764 /* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
765 pVmcb->ctrl.NestedPaging.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
766
767 /* Without Nested Paging, we need additionally intercepts. */
768 if (!pVM->hm.s.fNestedPaging)
769 {
770 /* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
771 pVmcb->ctrl.u16InterceptRdCRx |= RT_BIT(3);
772 pVmcb->ctrl.u16InterceptWrCRx |= RT_BIT(3);
773
774 /* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
775 pVmcb->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_INVLPG
776 | SVM_CTRL1_INTERCEPT_TASK_SWITCH;
777
778 /* Page faults must be intercepted to implement shadow paging. */
779 pVmcb->ctrl.u32InterceptException |= RT_BIT(X86_XCPT_PF);
780 }
781
782#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
783 pVmcb->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_TASK_SWITCH;
784#endif
785
786 /*
787 * The following MSRs are saved/restored automatically during the world-switch.
788 * Don't intercept guest read/write accesses to these MSRs.
789 */
790 hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
791 hmR0SvmSetMsrPermission(pVCpu, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
792 hmR0SvmSetMsrPermission(pVCpu, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
793 hmR0SvmSetMsrPermission(pVCpu, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
794 hmR0SvmSetMsrPermission(pVCpu, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
795 hmR0SvmSetMsrPermission(pVCpu, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
796 hmR0SvmSetMsrPermission(pVCpu, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
797 hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
798 hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
799 hmR0SvmSetMsrPermission(pVCpu, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
800 }
801
802 return VINF_SUCCESS;
803}
804
805
806/**
807 * Invalidates a guest page by guest virtual address.
808 *
809 * @returns VBox status code.
810 * @param pVM Pointer to the VM.
811 * @param pVCpu Pointer to the VMCPU.
812 * @param GCVirt Guest virtual address of the page to invalidate.
813 */
814VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, PVMCPU pVCpu, RTGCPTR GCVirt)
815{
816 AssertReturn(pVM, VERR_INVALID_PARAMETER);
817 Assert(pVM->hm.s.svm.fSupported);
818
819 bool fFlushPending = pVM->hm.s.svm.fAlwaysFlushTLB || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
820
821 /* Skip it if a TLB flush is already pending. */
822 if (!fFlushPending)
823 {
824 Log4(("SVMR0InvalidatePage %RGv\n", GCVirt));
825
826 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
827 AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
828
829#if HC_ARCH_BITS == 32
830 /* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
831 if (CPUMIsGuestInLongMode(pVCpu))
832 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
833 else
834#endif
835 {
836 SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
837 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
838 }
839 }
840 return VINF_SUCCESS;
841}
842
843
844/**
845 * Flushes the appropriate tagged-TLB entries.
846 *
847 * @param pVM Pointer to the VM.
848 * @param pVCpu Pointer to the VMCPU.
849 */
850static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu)
851{
852 PVM pVM = pVCpu->CTX_SUFF(pVM);
853 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
854 PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
855
856 /*
857 * Force a TLB flush for the first world switch if the current CPU differs from the one we ran on last.
858 * This can happen both for start & resume due to long jumps back to ring-3.
859 * If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while flushing the TLB,
860 * so we cannot reuse the ASIDs without flushing.
861 */
862 bool fNewAsid = false;
863 Assert(pCpu->idCpu != NIL_RTCPUID);
864 if ( pVCpu->hm.s.idLastCpu != pCpu->idCpu
865 || pVCpu->hm.s.cTlbFlushes != pCpu->cTlbFlushes)
866 {
867 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
868 pVCpu->hm.s.fForceTLBFlush = true;
869 fNewAsid = true;
870 }
871
872 /* Set TLB flush state as checked until we return from the world switch. */
873 ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
874
875 /* Check for explicit TLB shootdowns. */
876 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
877 {
878 pVCpu->hm.s.fForceTLBFlush = true;
879 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
880 }
881
882 pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
883
884 if (pVM->hm.s.svm.fAlwaysFlushTLB)
885 {
886 /*
887 * This is the AMD erratum 170. We need to flush the entire TLB for each world switch. Sad.
888 */
889 pCpu->uCurrentAsid = 1;
890 pVCpu->hm.s.uCurrentAsid = 1;
891 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
892 pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
893
894 /* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
895 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
896 }
897 else if (pVCpu->hm.s.fForceTLBFlush)
898 {
899 /* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
900 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
901
902 if (fNewAsid)
903 {
904 ++pCpu->uCurrentAsid;
905 bool fHitASIDLimit = false;
906 if (pCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
907 {
908 pCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
909 pCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new VPID. */
910 fHitASIDLimit = true;
911
912 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
913 {
914 pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
915 pCpu->fFlushAsidBeforeUse = true;
916 }
917 else
918 {
919 pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
920 pCpu->fFlushAsidBeforeUse = false;
921 }
922 }
923
924 if ( !fHitASIDLimit
925 && pCpu->fFlushAsidBeforeUse)
926 {
927 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
928 pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
929 else
930 {
931 pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
932 pCpu->fFlushAsidBeforeUse = false;
933 }
934 }
935
936 pVCpu->hm.s.uCurrentAsid = pCpu->uCurrentAsid;
937 pVCpu->hm.s.idLastCpu = pCpu->idCpu;
938 pVCpu->hm.s.cTlbFlushes = pCpu->cTlbFlushes;
939 }
940 else
941 {
942 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
943 pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
944 else
945 pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
946 }
947
948 pVCpu->hm.s.fForceTLBFlush = false;
949 }
950 /** @todo We never set VMCPU_FF_TLB_SHOOTDOWN anywhere so this path should
951 * not be executed. See hmQueueInvlPage() where it is commented
952 * out. Support individual entry flushing someday. */
953#if 0
954 else
955 {
956 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_SHOOTDOWN))
957 {
958 /* Deal with pending TLB shootdown actions which were queued when we were not executing code. */
959 STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
960 for (uint32_t i = 0; i < pVCpu->hm.s.TlbShootdown.cPages; i++)
961 SVMR0InvlpgA(pVCpu->hm.s.TlbShootdown.aPages[i], pVmcb->ctrl.TLBCtrl.n.u32ASID);
962
963 pVCpu->hm.s.TlbShootdown.cPages = 0;
964 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TLB_SHOOTDOWN);
965 }
966 }
967#endif
968
969
970 /* Update VMCB with the ASID. */
971 if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
972 {
973 pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
974 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
975 }
976
977 AssertMsg(pVCpu->hm.s.idLastCpu == pCpu->idCpu,
978 ("vcpu idLastCpu=%x pcpu idCpu=%x\n", pVCpu->hm.s.idLastCpu, pCpu->idCpu));
979 AssertMsg(pVCpu->hm.s.cTlbFlushes == pCpu->cTlbFlushes,
980 ("Flush count mismatch for cpu %d (%x vs %x)\n", pCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pCpu->cTlbFlushes));
981 AssertMsg(pCpu->uCurrentAsid >= 1 && pCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
982 ("cpu%d uCurrentAsid = %x\n", pCpu->idCpu, pCpu->uCurrentAsid));
983 AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
984 ("cpu%d VM uCurrentAsid = %x\n", pCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
985
986#ifdef VBOX_WITH_STATISTICS
987 if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
988 STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
989 else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
990 || pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
991 {
992 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
993 }
994 else
995 {
996 Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
997 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
998 }
999#endif
1000}
1001
1002
1003/** @name 64-bit guest on 32-bit host OS helper functions.
1004 *
1005 * The host CPU is still 64-bit capable but the host OS is running in 32-bit
1006 * mode (code segment, paging). These wrappers/helpers perform the necessary
1007 * bits for the 32->64 switcher.
1008 *
1009 * @{ */
1010#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1011/**
1012 * Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
1013 *
1014 * @returns VBox status code.
1015 * @param HCPhysVmcbHost Physical address of host VMCB.
1016 * @param HCPhysVmcb Physical address of the VMCB.
1017 * @param pCtx Pointer to the guest-CPU context.
1018 * @param pVM Pointer to the VM.
1019 * @param pVCpu Pointer to the VMCPU.
1020 */
1021DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
1022{
1023 uint32_t aParam[4];
1024 aParam[0] = (uint32_t)(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
1025 aParam[1] = (uint32_t)(HCPhysVmcbHost >> 32); /* Param 1: HCPhysVmcbHost - Hi. */
1026 aParam[2] = (uint32_t)(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
1027 aParam[3] = (uint32_t)(HCPhysVmcb >> 32); /* Param 2: HCPhysVmcb - Hi. */
1028
1029 return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_SVMRCVMRun64, 4, &aParam[0]);
1030}
1031
1032
1033/**
1034 * Executes the specified VMRUN handler in 64-bit mode.
1035 *
1036 * @returns VBox status code.
1037 * @param pVM Pointer to the VM.
1038 * @param pVCpu Pointer to the VMCPU.
1039 * @param pCtx Pointer to the guest-CPU context.
1040 * @param enmOp The operation to perform.
1041 * @param cbParam Number of parameters.
1042 * @param paParam Array of 32-bit parameters.
1043 */
1044VMMR0DECL(int) SVMR0Execute64BitsHandler(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, HM64ON32OP enmOp, uint32_t cbParam,
1045 uint32_t *paParam)
1046{
1047 AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1048 Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1049
1050 /* Disable interrupts. */
1051 RTHCUINTREG uOldEFlags = ASMIntDisableFlags();
1052
1053#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1054 RTCPUID idHostCpu = RTMpCpuId();
1055 CPUMR0SetLApic(pVCpu, idHostCpu);
1056#endif
1057
1058 CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1059 CPUMSetHyperEIP(pVCpu, enmOp);
1060 for (int i = (int)cbParam - 1; i >= 0; i--)
1061 CPUMPushHyper(pVCpu, paParam[i]);
1062
1063 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1064 /* Call the switcher. */
1065 int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_OFFSETOF(VM, aCpus[pVCpu->idCpu].cpum) - RT_OFFSETOF(VM, cpum));
1066 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1067
1068 /* Restore interrupts. */
1069 ASMSetFlags(uOldEFlags);
1070 return rc;
1071}
1072
1073#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1074/** @} */
1075
1076
1077/**
1078 * Adds an exception to the intercept exception bitmap in the VMCB and updates
1079 * the corresponding VMCB Clean bit.
1080 *
1081 * @param pVmcb Pointer to the VM control block.
1082 * @param u32Xcpt The value of the exception (X86_XCPT_*).
1083 */
1084DECLINLINE(void) hmR0SvmAddXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1085{
1086 if (!(pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt)))
1087 {
1088 pVmcb->ctrl.u32InterceptException |= RT_BIT(u32Xcpt);
1089 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1090 }
1091}
1092
1093
1094/**
1095 * Removes an exception from the intercept-exception bitmap in the VMCB and
1096 * updates the corresponding VMCB Clean bit.
1097 *
1098 * @param pVmcb Pointer to the VM control block.
1099 * @param u32Xcpt The value of the exception (X86_XCPT_*).
1100 */
1101DECLINLINE(void) hmR0SvmRemoveXcptIntercept(PSVMVMCB pVmcb, uint32_t u32Xcpt)
1102{
1103#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1104 if (pVmcb->ctrl.u32InterceptException & RT_BIT(u32Xcpt))
1105 {
1106 pVmcb->ctrl.u32InterceptException &= ~RT_BIT(u32Xcpt);
1107 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1108 }
1109#endif
1110}
1111
1112
1113/**
1114 * Loads the guest CR0 control register into the guest-state area in the VMCB.
1115 * Although the guest CR0 is a separate field in the VMCB we have to consider
1116 * the FPU state itself which is shared between the host and the guest.
1117 *
1118 * @returns VBox status code.
1119 * @param pVM Pointer to the VMCPU.
1120 * @param pVmcb Pointer to the VM control block.
1121 * @param pCtx Pointer to the guest-CPU context.
1122 *
1123 * @remarks No-long-jump zone!!!
1124 */
1125static void hmR0SvmLoadSharedCR0(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1126{
1127 /*
1128 * Guest CR0.
1129 */
1130 PVM pVM = pVCpu->CTX_SUFF(pVM);
1131 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
1132 {
1133 uint64_t u64GuestCR0 = pCtx->cr0;
1134
1135 /* Always enable caching. */
1136 u64GuestCR0 &= ~(X86_CR0_CD | X86_CR0_NW);
1137
1138 /*
1139 * When Nested Paging is not available use shadow page tables and intercept #PFs (the latter done in SVMR0SetupVM()).
1140 */
1141 if (!pVM->hm.s.fNestedPaging)
1142 {
1143 u64GuestCR0 |= X86_CR0_PG; /* When Nested Paging is not available, use shadow page tables. */
1144 u64GuestCR0 |= X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1145 }
1146
1147 /*
1148 * Guest FPU bits.
1149 */
1150 bool fInterceptNM = false;
1151 bool fInterceptMF = false;
1152 u64GuestCR0 |= X86_CR0_NE; /* Use internal x87 FPU exceptions handling rather than external interrupts. */
1153 if (CPUMIsGuestFPUStateActive(pVCpu))
1154 {
1155 /* Catch floating point exceptions if we need to report them to the guest in a different way. */
1156 if (!(pCtx->cr0 & X86_CR0_NE))
1157 {
1158 Log4(("hmR0SvmLoadGuestControlRegs: Intercepting Guest CR0.MP Old-style FPU handling!!!\n"));
1159 fInterceptMF = true;
1160 }
1161 }
1162 else
1163 {
1164 fInterceptNM = true; /* Guest FPU inactive, #VMEXIT on #NM for lazy FPU loading. */
1165 u64GuestCR0 |= X86_CR0_TS /* Guest can task switch quickly and do lazy FPU syncing. */
1166 | X86_CR0_MP; /* FWAIT/WAIT should not ignore CR0.TS and should generate #NM. */
1167 }
1168
1169 /*
1170 * Update the exception intercept bitmap.
1171 */
1172 if (fInterceptNM)
1173 hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_NM);
1174 else
1175 hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_NM);
1176
1177 if (fInterceptMF)
1178 hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_MF);
1179 else
1180 hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_MF);
1181
1182 pVmcb->guest.u64CR0 = u64GuestCR0;
1183 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1184 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR0);
1185 }
1186}
1187
1188
1189/**
1190 * Loads the guest control registers (CR2, CR3, CR4) into the VMCB.
1191 *
1192 * @returns VBox status code.
1193 * @param pVCpu Pointer to the VMCPU.
1194 * @param pVmcb Pointer to the VM control block.
1195 * @param pCtx Pointer to the guest-CPU context.
1196 *
1197 * @remarks No-long-jump zone!!!
1198 */
1199static int hmR0SvmLoadGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1200{
1201 PVM pVM = pVCpu->CTX_SUFF(pVM);
1202
1203 /*
1204 * Guest CR2.
1205 */
1206 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR2))
1207 {
1208 pVmcb->guest.u64CR2 = pCtx->cr2;
1209 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1210 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR2);
1211 }
1212
1213 /*
1214 * Guest CR3.
1215 */
1216 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR3))
1217 {
1218 if (pVM->hm.s.fNestedPaging)
1219 {
1220 PGMMODE enmShwPagingMode;
1221#if HC_ARCH_BITS == 32
1222 if (CPUMIsGuestInLongModeEx(pCtx))
1223 enmShwPagingMode = PGMMODE_AMD64_NX;
1224 else
1225#endif
1226 enmShwPagingMode = PGMGetHostMode(pVM);
1227
1228 pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1229 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1230 Assert(pVmcb->ctrl.u64NestedPagingCR3);
1231 pVmcb->guest.u64CR3 = pCtx->cr3;
1232 }
1233 else
1234 pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1235
1236 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1237 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR3);
1238 }
1239
1240 /*
1241 * Guest CR4.
1242 */
1243 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR4))
1244 {
1245 uint64_t u64GuestCR4 = pCtx->cr4;
1246 if (!pVM->hm.s.fNestedPaging)
1247 {
1248 switch (pVCpu->hm.s.enmShadowMode)
1249 {
1250 case PGMMODE_REAL:
1251 case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1252 AssertFailed();
1253 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1254
1255 case PGMMODE_32_BIT: /* 32-bit paging. */
1256 u64GuestCR4 &= ~X86_CR4_PAE;
1257 break;
1258
1259 case PGMMODE_PAE: /* PAE paging. */
1260 case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1261 /** Must use PAE paging as we could use physical memory > 4 GB */
1262 u64GuestCR4 |= X86_CR4_PAE;
1263 break;
1264
1265 case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1266 case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1267#ifdef VBOX_ENABLE_64_BITS_GUESTS
1268 break;
1269#else
1270 AssertFailed();
1271 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1272#endif
1273
1274 default: /* shut up gcc */
1275 AssertFailed();
1276 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1277 }
1278 }
1279
1280 pVmcb->guest.u64CR4 = u64GuestCR4;
1281 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1282 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_CR4);
1283 }
1284
1285 return VINF_SUCCESS;
1286}
1287
1288
1289/**
1290 * Loads the guest segment registers into the VMCB.
1291 *
1292 * @returns VBox status code.
1293 * @param pVCpu Pointer to the VMCPU.
1294 * @param pVmcb Pointer to the VM control block.
1295 * @param pCtx Pointer to the guest-CPU context.
1296 *
1297 * @remarks No-long-jump zone!!!
1298 */
1299static void hmR0SvmLoadGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1300{
1301 /* Guest Segment registers: CS, SS, DS, ES, FS, GS. */
1302 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
1303 {
1304 HMSVM_LOAD_SEG_REG(CS, cs);
1305 HMSVM_LOAD_SEG_REG(SS, ss);
1306 HMSVM_LOAD_SEG_REG(DS, ds);
1307 HMSVM_LOAD_SEG_REG(ES, es);
1308 HMSVM_LOAD_SEG_REG(FS, fs);
1309 HMSVM_LOAD_SEG_REG(GS, gs);
1310
1311 pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1312 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1313 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS);
1314 }
1315
1316 /* Guest TR. */
1317 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_TR))
1318 {
1319 HMSVM_LOAD_SEG_REG(TR, tr);
1320 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_TR);
1321 }
1322
1323 /* Guest LDTR. */
1324 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_LDTR))
1325 {
1326 HMSVM_LOAD_SEG_REG(LDTR, ldtr);
1327 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LDTR);
1328 }
1329
1330 /* Guest GDTR. */
1331 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_GDTR))
1332 {
1333 pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1334 pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1335 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1336 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_GDTR);
1337 }
1338
1339 /* Guest IDTR. */
1340 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_IDTR))
1341 {
1342 pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1343 pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1344 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1345 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_IDTR);
1346 }
1347}
1348
1349
1350/**
1351 * Loads the guest MSRs into the VMCB.
1352 *
1353 * @param pVCpu Pointer to the VMCPU.
1354 * @param pVmcb Pointer to the VM control block.
1355 * @param pCtx Pointer to the guest-CPU context.
1356 *
1357 * @remarks No-long-jump zone!!!
1358 */
1359static void hmR0SvmLoadGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1360{
1361 /* Guest Sysenter MSRs. */
1362 pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1363 pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1364 pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1365
1366 /*
1367 * Guest EFER MSR.
1368 * AMD-V requires guest EFER.SVME to be set. Weird.
1369 * See AMD spec. 15.5.1 "Basic Operation" | "Canonicalization and Consistency Checks".
1370 */
1371 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_EFER_MSR))
1372 {
1373 pVmcb->guest.u64EFER = pCtx->msrEFER | MSR_K6_EFER_SVME;
1374 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1375 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
1376 }
1377
1378 /* 64-bit MSRs. */
1379 if (CPUMIsGuestInLongModeEx(pCtx))
1380 {
1381 pVmcb->guest.FS.u64Base = pCtx->fs.u64Base;
1382 pVmcb->guest.GS.u64Base = pCtx->gs.u64Base;
1383 }
1384 else
1385 {
1386 /* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit from guest EFER otherwise AMD-V expects amd64 shadow paging. */
1387 if (pCtx->msrEFER & MSR_K6_EFER_LME)
1388 {
1389 pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1390 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1391 }
1392 }
1393
1394
1395 /** @todo The following are used in 64-bit only (SYSCALL/SYSRET) but they might
1396 * be writable in 32-bit mode. Clarify with AMD spec. */
1397 pVmcb->guest.u64STAR = pCtx->msrSTAR;
1398 pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1399 pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1400 pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1401 pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1402}
1403
1404
1405/**
1406 * Loads the guest state into the VMCB and programs the necessary intercepts
1407 * accordingly.
1408 *
1409 * @param pVCpu Pointer to the VMCPU.
1410 * @param pVmcb Pointer to the VM control block.
1411 * @param pCtx Pointer to the guest-CPU context.
1412 *
1413 * @remarks No-long-jump zone!!!
1414 * @remarks Requires EFLAGS to be up-to-date in the VMCB!
1415 */
1416static void hmR0SvmLoadSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1417{
1418 if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
1419 return;
1420 Assert((pCtx->dr[6] & X86_DR6_RA1_MASK) == X86_DR6_RA1_MASK); Assert((pCtx->dr[6] & X86_DR6_RAZ_MASK) == 0);
1421 Assert((pCtx->dr[7] & X86_DR7_RA1_MASK) == X86_DR7_RA1_MASK); Assert((pCtx->dr[7] & X86_DR7_RAZ_MASK) == 0);
1422
1423 bool fInterceptDB = false;
1424 bool fInterceptMovDRx = false;
1425
1426 /*
1427 * Anyone single stepping on the host side? If so, we'll have to use the
1428 * trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1429 * the VMM level like the VT-x implementations does.
1430 */
1431 bool const fStepping = pVCpu->hm.s.fSingleInstruction || DBGFIsStepping(pVCpu);
1432 if (fStepping)
1433 {
1434 pVCpu->hm.s.fClearTrapFlag = true;
1435 pVmcb->guest.u64RFlags |= X86_EFL_TF;
1436 fInterceptDB = true;
1437 fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1438 }
1439
1440 if ( fStepping
1441 || (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1442 {
1443 /*
1444 * Use the combined guest and host DRx values found in the hypervisor
1445 * register set because the debugger has breakpoints active or someone
1446 * is single stepping on the host side.
1447 *
1448 * Note! DBGF expects a clean DR6 state before executing guest code.
1449 */
1450#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1451 if ( CPUMIsGuestInLongModeEx(pCtx)
1452 && !CPUMIsHyperDebugStateActivePending(pVCpu))
1453 {
1454 CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1455 Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1456 Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1457 }
1458 else
1459#endif
1460 if (!CPUMIsHyperDebugStateActive(pVCpu))
1461 {
1462 CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1463 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1464 Assert(CPUMIsHyperDebugStateActive(pVCpu));
1465 }
1466
1467 /* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1468 if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1469 || pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1470 {
1471 pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1472 pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1473 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1474 pVCpu->hm.s.fUsingHyperDR7 = true;
1475 }
1476
1477 /** @todo If we cared, we could optimize to allow the guest to read registers
1478 * with the same values. */
1479 fInterceptDB = true;
1480 fInterceptMovDRx = true;
1481 Log5(("hmR0SvmLoadSharedDebugState: Loaded hyper DRx\n"));
1482 }
1483 else
1484 {
1485 /*
1486 * Update DR6, DR7 with the guest values if necessary.
1487 */
1488 if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1489 || pVmcb->guest.u64DR6 != pCtx->dr[6])
1490 {
1491 pVmcb->guest.u64DR7 = pCtx->dr[7];
1492 pVmcb->guest.u64DR6 = pCtx->dr[6];
1493 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1494 pVCpu->hm.s.fUsingHyperDR7 = false;
1495 }
1496
1497 /*
1498 * If the guest has enabled debug registers, we need to load them prior to
1499 * executing guest code so they'll trigger at the right time.
1500 */
1501 if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK | X86_DR7_GD)) /** @todo Why GD? */
1502 {
1503#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1504 if ( CPUMIsGuestInLongModeEx(pCtx)
1505 && !CPUMIsGuestDebugStateActivePending(pVCpu))
1506 {
1507 CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1508 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1509 Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1510 Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1511 }
1512 else
1513#endif
1514 if (!CPUMIsGuestDebugStateActive(pVCpu))
1515 {
1516 CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1517 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1518 Assert(!CPUMIsHyperDebugStateActive(pVCpu));
1519 Assert(CPUMIsGuestDebugStateActive(pVCpu));
1520 }
1521 Log5(("hmR0SvmLoadSharedDebugState: Loaded guest DRx\n"));
1522 }
1523 /*
1524 * If no debugging enabled, we'll lazy load DR0-3. We don't need to
1525 * intercept #DB as DR6 is updated in the VMCB.
1526 */
1527#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1528 else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
1529 && !CPUMIsGuestDebugStateActive(pVCpu))
1530#else
1531 else if (!CPUMIsGuestDebugStateActive(pVCpu))
1532#endif
1533 {
1534 fInterceptMovDRx = true;
1535 }
1536 }
1537
1538 /*
1539 * Set up the intercepts.
1540 */
1541 if (fInterceptDB)
1542 hmR0SvmAddXcptIntercept(pVmcb, X86_XCPT_DB);
1543 else
1544 hmR0SvmRemoveXcptIntercept(pVmcb, X86_XCPT_DB);
1545
1546 if (fInterceptMovDRx)
1547 {
1548 if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
1549 || pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
1550 {
1551 pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
1552 pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
1553 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1554 }
1555 }
1556 else
1557 {
1558 if ( pVmcb->ctrl.u16InterceptRdDRx
1559 || pVmcb->ctrl.u16InterceptWrDRx)
1560 {
1561 pVmcb->ctrl.u16InterceptRdDRx = 0;
1562 pVmcb->ctrl.u16InterceptWrDRx = 0;
1563 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1564 }
1565 }
1566
1567 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_DEBUG);
1568}
1569
1570
1571/**
1572 * Loads the guest APIC state (currently just the TPR).
1573 *
1574 * @returns VBox status code.
1575 * @param pVCpu Pointer to the VMCPU.
1576 * @param pVmcb Pointer to the VM control block.
1577 * @param pCtx Pointer to the guest-CPU context.
1578 */
1579static int hmR0SvmLoadGuestApicState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1580{
1581 if (!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE))
1582 return VINF_SUCCESS;
1583
1584 bool fPendingIntr;
1585 uint8_t u8Tpr;
1586 int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
1587 AssertRCReturn(rc, rc);
1588
1589 /* Assume that we need to trap all TPR accesses and thus need not check on
1590 every #VMEXIT if we should update the TPR. */
1591 Assert(pVmcb->ctrl.IntCtrl.n.u1VIrqMasking);
1592 pVCpu->hm.s.svm.fSyncVTpr = false;
1593
1594 /* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
1595 if (pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive)
1596 {
1597 pCtx->msrLSTAR = u8Tpr;
1598
1599 /* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
1600 if (fPendingIntr)
1601 hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
1602 else
1603 {
1604 hmR0SvmSetMsrPermission(pVCpu, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1605 pVCpu->hm.s.svm.fSyncVTpr = true;
1606 }
1607 }
1608 else
1609 {
1610 /* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
1611 pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
1612
1613 /* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we can deliver the interrupt to the guest. */
1614 if (fPendingIntr)
1615 pVmcb->ctrl.u16InterceptWrCRx |= RT_BIT(8);
1616 else
1617 {
1618 pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
1619 pVCpu->hm.s.svm.fSyncVTpr = true;
1620 }
1621
1622 pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS | HMSVM_VMCB_CLEAN_TPR);
1623 }
1624
1625 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
1626 return rc;
1627}
1628
1629
1630/**
1631 * Sets up the appropriate function to run guest code.
1632 *
1633 * @returns VBox status code.
1634 * @param pVCpu Pointer to the VMCPU.
1635 * @param pCtx Pointer to the guest-CPU context.
1636 *
1637 * @remarks No-long-jump zone!!!
1638 */
1639static int hmR0SvmSetupVMRunHandler(PVMCPU pVCpu, PCPUMCTX pCtx)
1640{
1641 if (CPUMIsGuestInLongModeEx(pCtx))
1642 {
1643#ifndef VBOX_ENABLE_64_BITS_GUESTS
1644 return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1645#endif
1646 Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
1647#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1648 /* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
1649 pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
1650#else
1651 /* 64-bit host or hybrid host. */
1652 pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
1653#endif
1654 }
1655 else
1656 {
1657 /* Guest is not in long mode, use the 32-bit handler. */
1658 pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
1659 }
1660 return VINF_SUCCESS;
1661}
1662
1663
1664/**
1665 * Enters the AMD-V session.
1666 *
1667 * @returns VBox status code.
1668 * @param pVM Pointer to the VM.
1669 * @param pVCpu Pointer to the VMCPU.
1670 * @param pCpu Pointer to the CPU info struct.
1671 */
1672VMMR0DECL(int) SVMR0Enter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
1673{
1674 AssertPtr(pVM);
1675 AssertPtr(pVCpu);
1676 Assert(pVM->hm.s.svm.fSupported);
1677 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1678 NOREF(pVM); NOREF(pCpu);
1679
1680 LogFlowFunc(("pVM=%p pVCpu=%p\n", pVM, pVCpu));
1681 Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
1682
1683 pVCpu->hm.s.fLeaveDone = false;
1684 return VINF_SUCCESS;
1685}
1686
1687
1688/**
1689 * Thread-context callback for AMD-V.
1690 *
1691 * @param enmEvent The thread-context event.
1692 * @param pVCpu Pointer to the VMCPU.
1693 * @param fGlobalInit Whether global VT-x/AMD-V init. is used.
1694 * @thread EMT(pVCpu)
1695 */
1696VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
1697{
1698 NOREF(fGlobalInit);
1699
1700 switch (enmEvent)
1701 {
1702 case RTTHREADCTXEVENT_PREEMPTING:
1703 {
1704 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1705 Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
1706 VMCPU_ASSERT_EMT(pVCpu);
1707
1708 PVM pVM = pVCpu->CTX_SUFF(pVM);
1709 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1710
1711 /* No longjmps (log-flush, locks) in this fragile context. */
1712 VMMRZCallRing3Disable(pVCpu);
1713
1714 if (!pVCpu->hm.s.fLeaveDone)
1715 {
1716 hmR0SvmLeave(pVM, pVCpu, pCtx);
1717 pVCpu->hm.s.fLeaveDone = true;
1718 }
1719
1720 /* Leave HM context, takes care of local init (term). */
1721 int rc = HMR0LeaveCpu(pVCpu);
1722 AssertRC(rc); NOREF(rc);
1723
1724 /* Restore longjmp state. */
1725 VMMRZCallRing3Enable(pVCpu);
1726 STAM_COUNTER_INC(&pVCpu->hm.s.StatPreemptPreempting);
1727 break;
1728 }
1729
1730 case RTTHREADCTXEVENT_RESUMED:
1731 {
1732 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1733 Assert(VMMR0ThreadCtxHooksAreRegistered(pVCpu));
1734 VMCPU_ASSERT_EMT(pVCpu);
1735
1736 /* No longjmps (log-flush, locks) in this fragile context. */
1737 VMMRZCallRing3Disable(pVCpu);
1738
1739 /*
1740 * Initialize the bare minimum state required for HM. This takes care of
1741 * initializing AMD-V if necessary (onlined CPUs, local init etc.)
1742 */
1743 int rc = HMR0EnterCpu(pVCpu);
1744 AssertRC(rc); NOREF(rc);
1745 Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE));
1746
1747 pVCpu->hm.s.fLeaveDone = false;
1748
1749 /* Restore longjmp state. */
1750 VMMRZCallRing3Enable(pVCpu);
1751 break;
1752 }
1753
1754 default:
1755 break;
1756 }
1757}
1758
1759
1760/**
1761 * Saves the host state.
1762 *
1763 * @returns VBox status code.
1764 * @param pVM Pointer to the VM.
1765 * @param pVCpu Pointer to the VMCPU.
1766 *
1767 * @remarks No-long-jump zone!!!
1768 */
1769VMMR0DECL(int) SVMR0SaveHostState(PVM pVM, PVMCPU pVCpu)
1770{
1771 NOREF(pVM);
1772 NOREF(pVCpu);
1773 /* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
1774 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT);
1775 return VINF_SUCCESS;
1776}
1777
1778
1779/**
1780 * Loads the guest state into the VMCB.
1781 *
1782 * The CPU state will be loaded from these fields on every successful VM-entry.
1783 * Also sets up the appropriate VMRUN function to execute guest code based on
1784 * the guest CPU mode.
1785 *
1786 * @returns VBox status code.
1787 * @param pVM Pointer to the VM.
1788 * @param pVCpu Pointer to the VMCPU.
1789 * @param pCtx Pointer to the guest-CPU context.
1790 *
1791 * @remarks No-long-jump zone!!!
1792 */
1793static int hmR0SvmLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1794{
1795 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1796 AssertMsgReturn(pVmcb, ("Invalid pVmcb\n"), VERR_SVM_INVALID_PVMCB);
1797
1798 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestState, x);
1799
1800 int rc = hmR0SvmLoadGuestControlRegs(pVCpu, pVmcb, pCtx);
1801 AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestControlRegs! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1802
1803 hmR0SvmLoadGuestSegmentRegs(pVCpu, pVmcb, pCtx);
1804 hmR0SvmLoadGuestMsrs(pVCpu, pVmcb, pCtx);
1805
1806 pVmcb->guest.u64RIP = pCtx->rip;
1807 pVmcb->guest.u64RSP = pCtx->rsp;
1808 pVmcb->guest.u64RFlags = pCtx->eflags.u32;
1809 pVmcb->guest.u64RAX = pCtx->rax;
1810
1811 rc = hmR0SvmLoadGuestApicState(pVCpu, pVmcb, pCtx);
1812 AssertLogRelMsgRCReturn(rc, ("hmR0SvmLoadGuestApicState! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1813
1814 rc = hmR0SvmSetupVMRunHandler(pVCpu, pCtx);
1815 AssertLogRelMsgRCReturn(rc, ("hmR0SvmSetupVMRunHandler! rc=%Rrc (pVM=%p pVCpu=%p)\n", rc, pVM, pVCpu), rc);
1816
1817 /* Clear any unused and reserved bits. */
1818 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_RIP /* Unused (loaded unconditionally). */
1819 | HM_CHANGED_GUEST_RSP
1820 | HM_CHANGED_GUEST_RFLAGS
1821 | HM_CHANGED_GUEST_SYSENTER_CS_MSR
1822 | HM_CHANGED_GUEST_SYSENTER_EIP_MSR
1823 | HM_CHANGED_GUEST_SYSENTER_ESP_MSR
1824 | HM_CHANGED_GUEST_LAZY_MSRS /* Unused. */
1825 | HM_CHANGED_SVM_RESERVED1 /* Reserved. */
1826 | HM_CHANGED_SVM_RESERVED2
1827 | HM_CHANGED_SVM_RESERVED3
1828 | HM_CHANGED_SVM_RESERVED4);
1829
1830 /* All the guest state bits should be loaded except maybe the host context and/or shared host/guest bits. */
1831 AssertMsg( !HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_ALL_GUEST)
1832 || HMCPU_CF_IS_PENDING_ONLY(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_HOST_GUEST_SHARED_STATE),
1833 ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
1834
1835 Log4(("Load: CS:RIP=%04x:%RX64 EFL=%#x SS:RSP=%04x:%RX64\n", pCtx->cs.Sel, pCtx->rip, pCtx->eflags.u, pCtx->ss, pCtx->rsp));
1836 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestState, x);
1837 return rc;
1838}
1839
1840
1841/**
1842 * Loads the state shared between the host and guest into the
1843 * VMCB.
1844 *
1845 * @param pVCpu Pointer to the VMCPU.
1846 * @param pVmcb Pointer to the VM control block.
1847 * @param pCtx Pointer to the guest-CPU context.
1848 *
1849 * @remarks No-long-jump zone!!!
1850 */
1851static void hmR0SvmLoadSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx)
1852{
1853 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1854 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
1855
1856 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0))
1857 hmR0SvmLoadSharedCR0(pVCpu, pVmcb, pCtx);
1858
1859 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_DEBUG))
1860 hmR0SvmLoadSharedDebugState(pVCpu, pVmcb, pCtx);
1861
1862 /* Unused on AMD-V. */
1863 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_GUEST_LAZY_MSRS);
1864
1865 AssertMsg(!HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE),
1866 ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
1867}
1868
1869
1870/**
1871 * Saves the entire guest state from the VMCB into the
1872 * guest-CPU context. Currently there is no residual state left in the CPU that
1873 * is not updated in the VMCB.
1874 *
1875 * @returns VBox status code.
1876 * @param pVCpu Pointer to the VMCPU.
1877 * @param pMixedCtx Pointer to the guest-CPU context. The data may be
1878 * out-of-sync. Make sure to update the required fields
1879 * before using them.
1880 */
1881static void hmR0SvmSaveGuestState(PVMCPU pVCpu, PCPUMCTX pMixedCtx)
1882{
1883 Assert(VMMRZCallRing3IsEnabled(pVCpu));
1884
1885 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
1886
1887 pMixedCtx->rip = pVmcb->guest.u64RIP;
1888 pMixedCtx->rsp = pVmcb->guest.u64RSP;
1889 pMixedCtx->eflags.u32 = pVmcb->guest.u64RFlags;
1890 pMixedCtx->rax = pVmcb->guest.u64RAX;
1891
1892 /*
1893 * Guest interrupt shadow.
1894 */
1895 if (pVmcb->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
1896 EMSetInhibitInterruptsPC(pVCpu, pMixedCtx->rip);
1897 else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1898 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1899
1900 /*
1901 * Guest Control registers: CR2, CR3 (handled at the end) - accesses to other control registers are always intercepted.
1902 */
1903 pMixedCtx->cr2 = pVmcb->guest.u64CR2;
1904
1905 /*
1906 * Guest MSRs.
1907 */
1908 pMixedCtx->msrSTAR = pVmcb->guest.u64STAR; /* legacy syscall eip, cs & ss */
1909 pMixedCtx->msrLSTAR = pVmcb->guest.u64LSTAR; /* 64-bit mode syscall rip */
1910 pMixedCtx->msrCSTAR = pVmcb->guest.u64CSTAR; /* compatibility mode syscall rip */
1911 pMixedCtx->msrSFMASK = pVmcb->guest.u64SFMASK; /* syscall flag mask */
1912 pMixedCtx->msrKERNELGSBASE = pVmcb->guest.u64KernelGSBase; /* swapgs exchange value */
1913 pMixedCtx->SysEnter.cs = pVmcb->guest.u64SysEnterCS;
1914 pMixedCtx->SysEnter.eip = pVmcb->guest.u64SysEnterEIP;
1915 pMixedCtx->SysEnter.esp = pVmcb->guest.u64SysEnterESP;
1916
1917 /*
1918 * Guest segment registers (includes FS, GS base MSRs for 64-bit guests).
1919 */
1920 HMSVM_SAVE_SEG_REG(CS, cs);
1921 HMSVM_SAVE_SEG_REG(SS, ss);
1922 HMSVM_SAVE_SEG_REG(DS, ds);
1923 HMSVM_SAVE_SEG_REG(ES, es);
1924 HMSVM_SAVE_SEG_REG(FS, fs);
1925 HMSVM_SAVE_SEG_REG(GS, gs);
1926
1927 /*
1928 * Correct the hidden CS granularity bit. Haven't seen it being wrong in any other
1929 * register (yet).
1930 */
1931 /** @todo SELM might need to be fixed as it too should not care about the
1932 * granularity bit. See @bugref{6785}. */
1933 if ( !pMixedCtx->cs.Attr.n.u1Granularity
1934 && pMixedCtx->cs.Attr.n.u1Present
1935 && pMixedCtx->cs.u32Limit > UINT32_C(0xfffff))
1936 {
1937 Assert((pMixedCtx->cs.u32Limit & 0xfff) == 0xfff);
1938 pMixedCtx->cs.Attr.n.u1Granularity = 1;
1939 }
1940
1941#ifdef VBOX_STRICT
1942# define HMSVM_ASSERT_SEG_GRANULARITY(reg) \
1943 AssertMsg( !pMixedCtx->reg.Attr.n.u1Present \
1944 || ( pMixedCtx->reg.Attr.n.u1Granularity \
1945 ? (pMixedCtx->reg.u32Limit & 0xfff) == 0xfff \
1946 : pMixedCtx->reg.u32Limit <= UINT32_C(0xfffff)), \
1947 ("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", pMixedCtx->reg.u32Limit, \
1948 pMixedCtx->reg.Attr.u, pMixedCtx->reg.u64Base))
1949
1950 HMSVM_ASSERT_SEG_GRANULARITY(cs);
1951 HMSVM_ASSERT_SEG_GRANULARITY(ss);
1952 HMSVM_ASSERT_SEG_GRANULARITY(ds);
1953 HMSVM_ASSERT_SEG_GRANULARITY(es);
1954 HMSVM_ASSERT_SEG_GRANULARITY(fs);
1955 HMSVM_ASSERT_SEG_GRANULARITY(gs);
1956
1957# undef HMSVM_ASSERT_SEL_GRANULARITY
1958#endif
1959
1960 /*
1961 * Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the VMCB and uses that
1962 * and thus it's possible that when the CPL changes during guest execution that the SS DPL
1963 * isn't updated by AMD-V. Observed on some AMD Fusion CPUs with 64-bit guests.
1964 * See AMD spec. 15.5.1 "Basic operation".
1965 */
1966 Assert(!(pVmcb->guest.u8CPL & ~0x3));
1967 pMixedCtx->ss.Attr.n.u2Dpl = pVmcb->guest.u8CPL & 0x3;
1968
1969 /*
1970 * Guest TR.
1971 * Fixup TR attributes so it's compatible with Intel. Important when saved-states are used
1972 * between Intel and AMD. See @bugref{6208} comment #39.
1973 */
1974 HMSVM_SAVE_SEG_REG(TR, tr);
1975 if (CPUMIsGuestInLongModeEx(pMixedCtx))
1976 pMixedCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
1977
1978 /*
1979 * Guest Descriptor-Table registers.
1980 */
1981 HMSVM_SAVE_SEG_REG(LDTR, ldtr);
1982 pMixedCtx->gdtr.cbGdt = pVmcb->guest.GDTR.u32Limit;
1983 pMixedCtx->gdtr.pGdt = pVmcb->guest.GDTR.u64Base;
1984
1985 pMixedCtx->idtr.cbIdt = pVmcb->guest.IDTR.u32Limit;
1986 pMixedCtx->idtr.pIdt = pVmcb->guest.IDTR.u64Base;
1987
1988 /*
1989 * Guest Debug registers.
1990 */
1991 if (!pVCpu->hm.s.fUsingHyperDR7)
1992 {
1993 pMixedCtx->dr[6] = pVmcb->guest.u64DR6;
1994 pMixedCtx->dr[7] = pVmcb->guest.u64DR7;
1995 }
1996 else
1997 {
1998 Assert(pVmcb->guest.u64DR7 == CPUMGetHyperDR7(pVCpu));
1999 CPUMSetHyperDR6(pVCpu, pVmcb->guest.u64DR6);
2000 }
2001
2002 /*
2003 * With Nested Paging, CR3 changes are not intercepted. Therefore, sync. it now.
2004 * This is done as the very last step of syncing the guest state, as PGMUpdateCR3() may cause longjmp's to ring-3.
2005 */
2006 if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
2007 && pMixedCtx->cr3 != pVmcb->guest.u64CR3)
2008 {
2009 CPUMSetGuestCR3(pVCpu, pVmcb->guest.u64CR3);
2010 PGMUpdateCR3(pVCpu, pVmcb->guest.u64CR3);
2011 }
2012}
2013
2014
2015/**
2016 * Does the necessary state syncing before returning to ring-3 for any reason
2017 * (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
2018 *
2019 * @param pVM Pointer to the VM.
2020 * @param pVCpu Pointer to the VMCPU.
2021 * @param pMixedCtx Pointer to the guest-CPU context.
2022 *
2023 * @remarks No-long-jmp zone!!!
2024 */
2025static void hmR0SvmLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2026{
2027 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2028 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2029 Assert(VMMR0IsLogFlushDisabled(pVCpu));
2030
2031 /*
2032 * !!! IMPORTANT !!!
2033 * If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2034 */
2035
2036 /* Restore host FPU state if necessary and resync on next R0 reentry .*/
2037 if (CPUMIsGuestFPUStateActive(pVCpu))
2038 {
2039 CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
2040 Assert(!CPUMIsGuestFPUStateActive(pVCpu));
2041 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
2042 }
2043
2044 /*
2045 * Restore host debug registers if necessary and resync on next R0 reentry.
2046 */
2047#ifdef VBOX_STRICT
2048 if (CPUMIsHyperDebugStateActive(pVCpu))
2049 {
2050 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2051 Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
2052 Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
2053 }
2054#endif
2055 if (CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */))
2056 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
2057
2058 Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2059 Assert(!CPUMIsGuestDebugStateActive(pVCpu));
2060
2061 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
2062 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatLoadGuestState);
2063 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit1);
2064 STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExit2);
2065 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2066
2067 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
2068}
2069
2070
2071/**
2072 * Leaves the AMD-V session.
2073 *
2074 * @returns VBox status code.
2075 * @param pVM Pointer to the VM.
2076 * @param pVCpu Pointer to the VMCPU.
2077 * @param pCtx Pointer to the guest-CPU context.
2078 */
2079static int hmR0SvmLeaveSession(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2080{
2081 HM_DISABLE_PREEMPT_IF_NEEDED();
2082 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2083 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2084
2085 /* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
2086 and done this from the SVMR0ThreadCtxCallback(). */
2087 if (!pVCpu->hm.s.fLeaveDone)
2088 {
2089 hmR0SvmLeave(pVM, pVCpu, pCtx);
2090 pVCpu->hm.s.fLeaveDone = true;
2091 }
2092
2093 /*
2094 * !!! IMPORTANT !!!
2095 * If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
2096 */
2097
2098 /* Deregister hook now that we've left HM context before re-enabling preemption. */
2099 if (VMMR0ThreadCtxHooksAreRegistered(pVCpu))
2100 VMMR0ThreadCtxHooksDeregister(pVCpu);
2101
2102 /* Leave HM context. This takes care of local init (term). */
2103 int rc = HMR0LeaveCpu(pVCpu);
2104
2105 HM_RESTORE_PREEMPT_IF_NEEDED();
2106 return rc;
2107}
2108
2109
2110/**
2111 * Does the necessary state syncing before doing a longjmp to ring-3.
2112 *
2113 * @returns VBox status code.
2114 * @param pVM Pointer to the VM.
2115 * @param pVCpu Pointer to the VMCPU.
2116 * @param pCtx Pointer to the guest-CPU context.
2117 *
2118 * @remarks No-long-jmp zone!!!
2119 */
2120static int hmR0SvmLongJmpToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2121{
2122 return hmR0SvmLeaveSession(pVM, pVCpu, pCtx);
2123}
2124
2125
2126/**
2127 * VMMRZCallRing3() callback wrapper which saves the guest state (or restores
2128 * any remaining host state) before we longjump to ring-3 and possibly get
2129 * preempted.
2130 *
2131 * @param pVCpu Pointer to the VMCPU.
2132 * @param enmOperation The operation causing the ring-3 longjump.
2133 * @param pvUser The user argument (pointer to the possibly
2134 * out-of-date guest-CPU context).
2135 */
2136DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
2137{
2138 if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
2139 {
2140 /*
2141 * !!! IMPORTANT !!!
2142 * If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
2143 * to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
2144 */
2145 VMMRZCallRing3RemoveNotification(pVCpu);
2146 VMMRZCallRing3Disable(pVCpu);
2147 HM_DISABLE_PREEMPT_IF_NEEDED();
2148
2149 /* Restore host FPU state if necessary and resync on next R0 reentry .*/
2150 if (CPUMIsGuestFPUStateActive(pVCpu))
2151 CPUMR0SaveGuestFPU(pVCpu->CTX_SUFF(pVM), pVCpu, (PCPUMCTX)pvUser);
2152
2153 /* Restore host debug registers if necessary and resync on next R0 reentry. */
2154 CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
2155
2156 /* Deregister hook now that we've left HM context before re-enabling preemption. */
2157 if (VMMR0ThreadCtxHooksAreRegistered(pVCpu))
2158 VMMR0ThreadCtxHooksDeregister(pVCpu);
2159
2160 /* Leave HM context. This takes care of local init (term). */
2161 HMR0LeaveCpu(pVCpu);
2162
2163 HM_RESTORE_PREEMPT_IF_NEEDED();
2164 return VINF_SUCCESS;
2165 }
2166
2167 Assert(pVCpu);
2168 Assert(pvUser);
2169 Assert(VMMRZCallRing3IsEnabled(pVCpu));
2170 HMSVM_ASSERT_PREEMPT_SAFE();
2171
2172 VMMRZCallRing3Disable(pVCpu);
2173 Assert(VMMR0IsLogFlushDisabled(pVCpu));
2174
2175 Log4(("hmR0SvmCallRing3Callback->hmR0SvmLongJmpToRing3\n"));
2176 int rc = hmR0SvmLongJmpToRing3(pVCpu->CTX_SUFF(pVM), pVCpu, (PCPUMCTX)pvUser);
2177 AssertRCReturn(rc, rc);
2178
2179 VMMRZCallRing3Enable(pVCpu);
2180 return VINF_SUCCESS;
2181}
2182
2183
2184/**
2185 * Take necessary actions before going back to ring-3.
2186 *
2187 * An action requires us to go back to ring-3. This function does the necessary
2188 * steps before we can safely return to ring-3. This is not the same as longjmps
2189 * to ring-3, this is voluntary.
2190 *
2191 * @param pVM Pointer to the VM.
2192 * @param pVCpu Pointer to the VMCPU.
2193 * @param pCtx Pointer to the guest-CPU context.
2194 * @param rcExit The reason for exiting to ring-3. Can be
2195 * VINF_VMM_UNKNOWN_RING3_CALL.
2196 */
2197static void hmR0SvmExitToRing3(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rcExit)
2198{
2199 Assert(pVM);
2200 Assert(pVCpu);
2201 Assert(pCtx);
2202 HMSVM_ASSERT_PREEMPT_SAFE();
2203
2204 /* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
2205 VMMRZCallRing3Disable(pVCpu);
2206 Log4(("hmR0SvmExitToRing3: rcExit=%d\n", rcExit));
2207
2208 /* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
2209 if (pVCpu->hm.s.Event.fPending)
2210 {
2211 hmR0SvmPendingEventToTrpmTrap(pVCpu);
2212 Assert(!pVCpu->hm.s.Event.fPending);
2213 }
2214
2215 /* If we're emulating an instruction, we shouldn't have any TRPM traps pending
2216 and if we're injecting an event we should have a TRPM trap pending. */
2217 Assert(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT || TRPMHasTrap(pVCpu));
2218 Assert(rcExit != VINF_EM_RAW_EMULATE_INSTR || !TRPMHasTrap(pVCpu));
2219
2220 /* Sync. the necessary state for going back to ring-3. */
2221 hmR0SvmLeaveSession(pVM, pVCpu, pCtx);
2222 STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
2223
2224 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
2225 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
2226 | CPUM_CHANGED_LDTR
2227 | CPUM_CHANGED_GDTR
2228 | CPUM_CHANGED_IDTR
2229 | CPUM_CHANGED_TR
2230 | CPUM_CHANGED_HIDDEN_SEL_REGS);
2231 if ( pVM->hm.s.fNestedPaging
2232 && CPUMIsGuestPagingEnabledEx(pCtx))
2233 {
2234 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
2235 }
2236
2237 /* On our way back from ring-3 reload the guest state if there is a possibility of it being changed. */
2238 if (rcExit != VINF_EM_RAW_INTERRUPT)
2239 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2240
2241 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
2242
2243 /* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
2244 VMMRZCallRing3RemoveNotification(pVCpu);
2245 VMMRZCallRing3Enable(pVCpu);
2246}
2247
2248
2249/**
2250 * Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
2251 * intercepts.
2252 *
2253 * @param pVCpu Pointer to the VMCPU.
2254 *
2255 * @remarks No-long-jump zone!!!
2256 */
2257static void hmR0SvmUpdateTscOffsetting(PVMCPU pVCpu)
2258{
2259 bool fParavirtTsc;
2260 bool fCanUseRealTsc;
2261 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2262 fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVCpu, &pVmcb->ctrl.u64TSCOffset, &fParavirtTsc);
2263 if (fCanUseRealTsc)
2264 {
2265 pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_RDTSC;
2266 pVmcb->ctrl.u32InterceptCtrl2 &= ~SVM_CTRL2_INTERCEPT_RDTSCP;
2267 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
2268 }
2269 else
2270 {
2271 pVmcb->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_RDTSC;
2272 pVmcb->ctrl.u32InterceptCtrl2 |= SVM_CTRL2_INTERCEPT_RDTSCP;
2273 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
2274 }
2275 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2276
2277 /** @todo later optimize this to be done elsewhere and not before every
2278 * VM-entry. */
2279 if (fParavirtTsc)
2280 {
2281 int rc = GIMR0UpdateParavirtTsc(pVCpu->CTX_SUFF(pVM), 0 /* u64Offset */);
2282 AssertRC(rc);
2283 STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
2284 }
2285}
2286
2287
2288/**
2289 * Sets an event as a pending event to be injected into the guest.
2290 *
2291 * @param pVCpu Pointer to the VMCPU.
2292 * @param pEvent Pointer to the SVM event.
2293 * @param GCPtrFaultAddress The fault-address (CR2) in case it's a
2294 * page-fault.
2295 *
2296 * @remarks Statistics counter assumes this is a guest event being reflected to
2297 * the guest i.e. 'StatInjectPendingReflect' is incremented always.
2298 */
2299DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
2300{
2301 Assert(!pVCpu->hm.s.Event.fPending);
2302 Assert(pEvent->n.u1Valid);
2303
2304 pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
2305 pVCpu->hm.s.Event.fPending = true;
2306 pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
2307
2308 Log4(("hmR0SvmSetPendingEvent: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2309 pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2310
2311 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
2312}
2313
2314
2315/**
2316 * Injects an event into the guest upon VMRUN by updating the relevant field
2317 * in the VMCB.
2318 *
2319 * @param pVCpu Pointer to the VMCPU.
2320 * @param pVmcb Pointer to the guest VM control block.
2321 * @param pCtx Pointer to the guest-CPU context.
2322 * @param pEvent Pointer to the event.
2323 *
2324 * @remarks No-long-jump zone!!!
2325 * @remarks Requires CR0!
2326 */
2327DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PCPUMCTX pCtx, PSVMEVENT pEvent)
2328{
2329 NOREF(pVCpu); NOREF(pCtx);
2330
2331 pVmcb->ctrl.EventInject.u = pEvent->u;
2332 STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
2333
2334 Log4(("hmR0SvmInjectEventVmcb: u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u,
2335 pEvent->n.u8Vector, (uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
2336}
2337
2338
2339
2340/**
2341 * Converts any TRPM trap into a pending HM event. This is typically used when
2342 * entering from ring-3 (not longjmp returns).
2343 *
2344 * @param pVCpu Pointer to the VMCPU.
2345 */
2346static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
2347{
2348 Assert(TRPMHasTrap(pVCpu));
2349 Assert(!pVCpu->hm.s.Event.fPending);
2350
2351 uint8_t uVector;
2352 TRPMEVENT enmTrpmEvent;
2353 RTGCUINT uErrCode;
2354 RTGCUINTPTR GCPtrFaultAddress;
2355 uint8_t cbInstr;
2356
2357 int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
2358 AssertRC(rc);
2359
2360 SVMEVENT Event;
2361 Event.u = 0;
2362 Event.n.u1Valid = 1;
2363 Event.n.u8Vector = uVector;
2364
2365 /* Refer AMD spec. 15.20 "Event Injection" for the format. */
2366 if (enmTrpmEvent == TRPM_TRAP)
2367 {
2368 Event.n.u3Type = SVM_EVENT_EXCEPTION;
2369 switch (uVector)
2370 {
2371 case X86_XCPT_NMI:
2372 {
2373 Event.n.u3Type = SVM_EVENT_NMI;
2374 break;
2375 }
2376
2377 case X86_XCPT_PF:
2378 case X86_XCPT_DF:
2379 case X86_XCPT_TS:
2380 case X86_XCPT_NP:
2381 case X86_XCPT_SS:
2382 case X86_XCPT_GP:
2383 case X86_XCPT_AC:
2384 {
2385 Event.n.u1ErrorCodeValid = 1;
2386 Event.n.u32ErrorCode = uErrCode;
2387 break;
2388 }
2389 }
2390 }
2391 else if (enmTrpmEvent == TRPM_HARDWARE_INT)
2392 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2393 else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
2394 Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
2395 else
2396 AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
2397
2398 rc = TRPMResetTrap(pVCpu);
2399 AssertRC(rc);
2400
2401 Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
2402 !!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
2403
2404 hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
2405 STAM_COUNTER_DEC(&pVCpu->hm.s.StatInjectPendingReflect);
2406}
2407
2408
2409/**
2410 * Converts any pending SVM event into a TRPM trap. Typically used when leaving
2411 * AMD-V to execute any instruction.
2412 *
2413 * @param pvCpu Pointer to the VMCPU.
2414 */
2415static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
2416{
2417 Assert(pVCpu->hm.s.Event.fPending);
2418 Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo */, NULL /* pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
2419
2420 SVMEVENT Event;
2421 Event.u = pVCpu->hm.s.Event.u64IntInfo;
2422
2423 uint8_t uVector = Event.n.u8Vector;
2424 uint8_t uVectorType = Event.n.u3Type;
2425
2426 TRPMEVENT enmTrapType;
2427 switch (uVectorType)
2428 {
2429 case SVM_EVENT_EXTERNAL_IRQ:
2430 enmTrapType = TRPM_HARDWARE_INT;
2431 break;
2432 case SVM_EVENT_SOFTWARE_INT:
2433 enmTrapType = TRPM_SOFTWARE_INT;
2434 break;
2435 case SVM_EVENT_EXCEPTION:
2436 case SVM_EVENT_NMI:
2437 enmTrapType = TRPM_TRAP;
2438 break;
2439 default:
2440 AssertMsgFailed(("Invalid pending-event type %#x\n", uVectorType));
2441 enmTrapType = TRPM_32BIT_HACK;
2442 break;
2443 }
2444
2445 Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
2446
2447 int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
2448 AssertRC(rc);
2449
2450 if (Event.n.u1ErrorCodeValid)
2451 TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
2452
2453 if ( uVectorType == SVM_EVENT_EXCEPTION
2454 && uVector == X86_XCPT_PF)
2455 {
2456 TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
2457 Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
2458 }
2459 else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
2460 {
2461 AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
2462 || (uVector == X86_XCPT_BP || uVector == X86_XCPT_OF),
2463 ("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
2464 TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
2465 }
2466 pVCpu->hm.s.Event.fPending = false;
2467}
2468
2469
2470/**
2471 * Gets the guest's interrupt-shadow.
2472 *
2473 * @returns The guest's interrupt-shadow.
2474 * @param pVCpu Pointer to the VMCPU.
2475 * @param pCtx Pointer to the guest-CPU context.
2476 *
2477 * @remarks No-long-jump zone!!!
2478 * @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
2479 */
2480DECLINLINE(uint32_t) hmR0SvmGetGuestIntrShadow(PVMCPU pVCpu, PCPUMCTX pCtx)
2481{
2482 /*
2483 * Instructions like STI and MOV SS inhibit interrupts till the next instruction completes. Check if we should
2484 * inhibit interrupts or clear any existing interrupt-inhibition.
2485 */
2486 uint32_t uIntrState = 0;
2487 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2488 {
2489 if (pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
2490 {
2491 /*
2492 * We can clear the inhibit force flag as even if we go back to the recompiler without executing guest code in
2493 * AMD-V, the flag's condition to be cleared is met and thus the cleared state is correct.
2494 */
2495 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2496 }
2497 else
2498 uIntrState = SVM_INTERRUPT_SHADOW_ACTIVE;
2499 }
2500 return uIntrState;
2501}
2502
2503
2504/**
2505 * Sets the virtual interrupt intercept control in the VMCB which
2506 * instructs AMD-V to cause a #VMEXIT as soon as the guest is in a state to
2507 * receive interrupts.
2508 *
2509 * @param pVmcb Pointer to the VM control block.
2510 */
2511DECLINLINE(void) hmR0SvmSetVirtIntrIntercept(PSVMVMCB pVmcb)
2512{
2513 if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_VINTR))
2514 {
2515 pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 1; /* A virtual interrupt is pending. */
2516 pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0; /* Not necessary as we #VMEXIT for delivering the interrupt. */
2517 pVmcb->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_VINTR;
2518 pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS | HMSVM_VMCB_CLEAN_TPR);
2519
2520 Log4(("Setting VINTR intercept\n"));
2521 }
2522}
2523
2524
2525/**
2526 * Sets the IRET intercept control in the VMCB which instructs AMD-V to cause a
2527 * #VMEXIT as soon as a guest starts executing an IRET. This is used to unblock
2528 * virtual NMIs.
2529 *
2530 * @param pVmcb Pointer to the VM control block.
2531 */
2532DECLINLINE(void) hmR0SvmSetIretIntercept(PSVMVMCB pVmcb)
2533{
2534 if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_IRET))
2535 {
2536 pVmcb->ctrl.u32InterceptCtrl1 |= SVM_CTRL1_INTERCEPT_IRET;
2537 pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
2538
2539 Log4(("Setting IRET intercept\n"));
2540 }
2541}
2542
2543
2544/**
2545 * Clears the IRET intercept control in the VMCB.
2546 *
2547 * @param pVmcb Pointer to the VM control block.
2548 */
2549DECLINLINE(void) hmR0SvmClearIretIntercept(PSVMVMCB pVmcb)
2550{
2551 if (pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_IRET)
2552 {
2553 pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_IRET;
2554 pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS);
2555
2556 Log4(("Clearing IRET intercept\n"));
2557 }
2558}
2559
2560
2561/**
2562 * Evaluates the event to be delivered to the guest and sets it as the pending
2563 * event.
2564 *
2565 * @param pVCpu Pointer to the VMCPU.
2566 * @param pCtx Pointer to the guest-CPU context.
2567 */
2568static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2569{
2570 Assert(!pVCpu->hm.s.Event.fPending);
2571 Log4Func(("\n"));
2572
2573 bool const fIntShadow = RT_BOOL(hmR0SvmGetGuestIntrShadow(pVCpu, pCtx));
2574 bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2575 bool const fBlockNmi = RT_BOOL(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS));
2576 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2577
2578 SVMEVENT Event;
2579 Event.u = 0;
2580 /** @todo SMI. SMIs take priority over NMIs. */
2581 if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)) /* NMI. NMIs take priority over regular interrupts . */
2582 {
2583 if (fBlockNmi)
2584 hmR0SvmSetIretIntercept(pVmcb);
2585 else if (fIntShadow)
2586 hmR0SvmSetVirtIntrIntercept(pVmcb);
2587 else
2588 {
2589 Log4(("Pending NMI\n"));
2590
2591 Event.n.u1Valid = 1;
2592 Event.n.u8Vector = X86_XCPT_NMI;
2593 Event.n.u3Type = SVM_EVENT_NMI;
2594
2595 hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2596 hmR0SvmSetIretIntercept(pVmcb);
2597 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2598 }
2599 }
2600 else if (VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)))
2601 {
2602 /*
2603 * Check if the guest can receive external interrupts (PIC/APIC). Once we do PDMGetInterrupt() we -must- deliver
2604 * the interrupt ASAP. We must not execute any guest code until we inject the interrupt which is why it is
2605 * evaluated here and not set as pending, solely based on the force-flags.
2606 */
2607 if ( !fBlockInt
2608 && !fIntShadow)
2609 {
2610 uint8_t u8Interrupt;
2611 int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
2612 if (RT_SUCCESS(rc))
2613 {
2614 Log4(("Injecting external interrupt u8Interrupt=%#x\n", u8Interrupt));
2615
2616 Event.n.u1Valid = 1;
2617 Event.n.u8Vector = u8Interrupt;
2618 Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
2619
2620 hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
2621 }
2622 else
2623 {
2624 /** @todo Does this actually happen? If not turn it into an assertion. */
2625 Assert(!VMCPU_FF_IS_PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)));
2626 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
2627 }
2628 }
2629 else
2630 hmR0SvmSetVirtIntrIntercept(pVmcb);
2631 }
2632}
2633
2634
2635/**
2636 * Injects any pending events into the guest if the guest is in a state to
2637 * receive them.
2638 *
2639 * @param pVCpu Pointer to the VMCPU.
2640 * @param pCtx Pointer to the guest-CPU context.
2641 */
2642static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PCPUMCTX pCtx)
2643{
2644 Assert(!TRPMHasTrap(pVCpu));
2645 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2646 Log4Func(("\n"));
2647
2648 bool const fIntShadow = RT_BOOL(hmR0SvmGetGuestIntrShadow(pVCpu, pCtx));
2649 bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
2650 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2651
2652 if (pVCpu->hm.s.Event.fPending) /* First, inject any pending HM events. */
2653 {
2654 SVMEVENT Event;
2655 Event.u = pVCpu->hm.s.Event.u64IntInfo;
2656 Assert(Event.n.u1Valid);
2657#ifdef VBOX_STRICT
2658 if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2659 {
2660 Assert(!fBlockInt);
2661 Assert(!fIntShadow);
2662 }
2663 else if (Event.n.u3Type == SVM_EVENT_NMI)
2664 Assert(!fIntShadow);
2665#endif
2666
2667 Log4(("Injecting pending HM event.\n"));
2668 hmR0SvmInjectEventVmcb(pVCpu, pVmcb, pCtx, &Event);
2669 pVCpu->hm.s.Event.fPending = false;
2670
2671#ifdef VBOX_WITH_STATISTICS
2672 if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
2673 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
2674 else
2675 STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
2676#endif
2677 }
2678
2679 /* Update the guest interrupt shadow in the VMCB. */
2680 pVmcb->ctrl.u64IntShadow = !!fIntShadow;
2681 NOREF(fBlockInt);
2682}
2683
2684
2685/**
2686 * Reports world-switch error and dumps some useful debug info.
2687 *
2688 * @param pVM Pointer to the VM.
2689 * @param pVCpu Pointer to the VMCPU.
2690 * @param rcVMRun The return code from VMRUN (or
2691 * VERR_SVM_INVALID_GUEST_STATE for invalid
2692 * guest-state).
2693 * @param pCtx Pointer to the guest-CPU context.
2694 */
2695static void hmR0SvmReportWorldSwitchError(PVM pVM, PVMCPU pVCpu, int rcVMRun, PCPUMCTX pCtx)
2696{
2697 NOREF(pCtx);
2698 HMSVM_ASSERT_PREEMPT_SAFE();
2699 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2700
2701 if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
2702 {
2703 HMDumpRegs(pVM, pVCpu, pCtx); NOREF(pVM);
2704#ifdef VBOX_STRICT
2705 Log4(("ctrl.u64VmcbCleanBits %#RX64\n", pVmcb->ctrl.u64VmcbCleanBits));
2706 Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
2707 Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
2708 Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
2709 Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
2710 Log4(("ctrl.u32InterceptException %#x\n", pVmcb->ctrl.u32InterceptException));
2711 Log4(("ctrl.u32InterceptCtrl1 %#x\n", pVmcb->ctrl.u32InterceptCtrl1));
2712 Log4(("ctrl.u32InterceptCtrl2 %#x\n", pVmcb->ctrl.u32InterceptCtrl2));
2713 Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
2714 Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
2715 Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
2716
2717 Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
2718 Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
2719 Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
2720
2721 Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
2722 Log4(("ctrl.IntCtrl.u1VIrqValid %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqValid));
2723 Log4(("ctrl.IntCtrl.u7Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u7Reserved));
2724 Log4(("ctrl.IntCtrl.u4VIrqPriority %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIrqPriority));
2725 Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
2726 Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
2727 Log4(("ctrl.IntCtrl.u1VIrqMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqMasking));
2728 Log4(("ctrl.IntCtrl.u6Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
2729 Log4(("ctrl.IntCtrl.u8VIrqVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIrqVector));
2730 Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
2731
2732 Log4(("ctrl.u64IntShadow %#RX64\n", pVmcb->ctrl.u64IntShadow));
2733 Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
2734 Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
2735 Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
2736 Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
2737 Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
2738 Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
2739 Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
2740 Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
2741 Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
2742 Log4(("ctrl.NestedPaging %#RX64\n", pVmcb->ctrl.NestedPaging.u));
2743 Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
2744 Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
2745 Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
2746 Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
2747 Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
2748 Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
2749
2750 Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
2751 Log4(("ctrl.u64LBRVirt %#RX64\n", pVmcb->ctrl.u64LBRVirt));
2752
2753 Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
2754 Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
2755 Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
2756 Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
2757 Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
2758 Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
2759 Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
2760 Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
2761 Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
2762 Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
2763 Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
2764 Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
2765 Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
2766 Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
2767 Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
2768 Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
2769 Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
2770 Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
2771 Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
2772 Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
2773
2774 Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
2775 Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
2776
2777 Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
2778 Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
2779 Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
2780 Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
2781
2782 Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
2783 Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
2784
2785 Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
2786 Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
2787 Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
2788 Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
2789
2790 Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
2791 Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
2792 Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
2793 Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
2794 Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
2795 Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
2796 Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
2797
2798 Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
2799 Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
2800 Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
2801 Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
2802
2803 Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
2804 Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
2805 Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
2806
2807 Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
2808 Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
2809 Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
2810 Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
2811 Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
2812 Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
2813 Log4(("guest.u64GPAT %#RX64\n", pVmcb->guest.u64GPAT));
2814 Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
2815 Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
2816 Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
2817 Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
2818 Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
2819#else
2820 NOREF(pVmcb);
2821#endif /* VBOX_STRICT */
2822 }
2823 else
2824 Log4(("hmR0SvmReportWorldSwitchError: rcVMRun=%d\n", rcVMRun));
2825}
2826
2827
2828/**
2829 * Check per-VM and per-VCPU force flag actions that require us to go back to
2830 * ring-3 for one reason or another.
2831 *
2832 * @returns VBox status code (information status code included).
2833 * @retval VINF_SUCCESS if we don't have any actions that require going back to
2834 * ring-3.
2835 * @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
2836 * @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
2837 * interrupts)
2838 * @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
2839 * all EMTs to be in ring-3.
2840 * @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
2841 * @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
2842 * to the EM loop.
2843 *
2844 * @param pVM Pointer to the VM.
2845 * @param pVCpu Pointer to the VMCPU.
2846 * @param pCtx Pointer to the guest-CPU context.
2847 */
2848static int hmR0SvmCheckForceFlags(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2849{
2850 Assert(VMMRZCallRing3IsEnabled(pVCpu));
2851
2852 /* On AMD-V we don't need to update CR3, PAE PDPES lazily. See hmR0SvmSaveGuestState(). */
2853 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
2854 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
2855
2856 if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
2857 ? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
2858 || VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
2859 ? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
2860 {
2861 /* Pending PGM C3 sync. */
2862 if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
2863 {
2864 int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
2865 if (rc != VINF_SUCCESS)
2866 {
2867 Log4(("hmR0SvmCheckForceFlags: PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
2868 return rc;
2869 }
2870 }
2871
2872 /* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
2873 /* -XXX- what was that about single stepping? */
2874 if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
2875 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2876 {
2877 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
2878 int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
2879 Log4(("hmR0SvmCheckForceFlags: HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
2880 return rc;
2881 }
2882
2883 /* Pending VM request packets, such as hardware interrupts. */
2884 if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
2885 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
2886 {
2887 Log4(("hmR0SvmCheckForceFlags: Pending VM request forcing us back to ring-3\n"));
2888 return VINF_EM_PENDING_REQUEST;
2889 }
2890
2891 /* Pending PGM pool flushes. */
2892 if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
2893 {
2894 Log4(("hmR0SvmCheckForceFlags: PGM pool flush pending forcing us back to ring-3\n"));
2895 return VINF_PGM_POOL_FLUSH_PENDING;
2896 }
2897
2898 /* Pending DMA requests. */
2899 if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
2900 {
2901 Log4(("hmR0SvmCheckForceFlags: Pending DMA request forcing us back to ring-3\n"));
2902 return VINF_EM_RAW_TO_R3;
2903 }
2904 }
2905
2906 return VINF_SUCCESS;
2907}
2908
2909
2910/**
2911 * Does the preparations before executing guest code in AMD-V.
2912 *
2913 * This may cause longjmps to ring-3 and may even result in rescheduling to the
2914 * recompiler. We must be cautious what we do here regarding committing
2915 * guest-state information into the the VMCB assuming we assuredly execute the
2916 * guest in AMD-V. If we fall back to the recompiler after updating the VMCB and
2917 * clearing the common-state (TRPM/forceflags), we must undo those changes so
2918 * that the recompiler can (and should) use them when it resumes guest
2919 * execution. Otherwise such operations must be done when we can no longer
2920 * exit to ring-3.
2921 *
2922 * @returns VBox status code (informational status codes included).
2923 * @retval VINF_SUCCESS if we can proceed with running the guest.
2924 * @retval VINF_* scheduling changes, we have to go back to ring-3.
2925 *
2926 * @param pVM Pointer to the VM.
2927 * @param pVCpu Pointer to the VMCPU.
2928 * @param pCtx Pointer to the guest-CPU context.
2929 * @param pSvmTransient Pointer to the SVM transient structure.
2930 */
2931static int hmR0SvmPreRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
2932{
2933 HMSVM_ASSERT_PREEMPT_SAFE();
2934
2935 /* Check force flag actions that might require us to go back to ring-3. */
2936 int rc = hmR0SvmCheckForceFlags(pVM, pVCpu, pCtx);
2937 if (rc != VINF_SUCCESS)
2938 return rc;
2939
2940 if (TRPMHasTrap(pVCpu))
2941 hmR0SvmTrpmTrapToPendingEvent(pVCpu);
2942 else if (!pVCpu->hm.s.Event.fPending)
2943 hmR0SvmEvaluatePendingEvent(pVCpu, pCtx);
2944
2945#ifdef HMSVM_SYNC_FULL_GUEST_STATE
2946 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2947#endif
2948
2949 /* Load the guest bits that are not shared with the host in any way since we can longjmp or get preempted. */
2950 rc = hmR0SvmLoadGuestState(pVM, pVCpu, pCtx);
2951 AssertRCReturn(rc, rc);
2952 STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadFull);
2953
2954 /*
2955 * If we're not intercepting TPR changes in the guest, save the guest TPR before the world-switch
2956 * so we can update it on the way back if the guest changed the TPR.
2957 */
2958 if (pVCpu->hm.s.svm.fSyncVTpr)
2959 {
2960 if (pVM->hm.s.fTPRPatchingActive)
2961 pSvmTransient->u8GuestTpr = pCtx->msrLSTAR;
2962 else
2963 {
2964 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
2965 pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
2966 }
2967 }
2968
2969 /*
2970 * No longjmps to ring-3 from this point on!!!
2971 * Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
2972 * This also disables flushing of the R0-logger instance (if any).
2973 */
2974 VMMRZCallRing3Disable(pVCpu);
2975
2976 /*
2977 * We disable interrupts so that we don't miss any interrupts that would flag preemption (IPI/timers etc.)
2978 * when thread-context hooks aren't used and we've been running with preemption disabled for a while.
2979 *
2980 * We need to check for force-flags that could've possible been altered since we last checked them (e.g.
2981 * by PDMGetInterrupt() leaving the PDM critical section, see @bugref{6398}).
2982 *
2983 * We also check a couple of other force-flags as a last opportunity to get the EMT back to ring-3 before
2984 * executing guest code.
2985 */
2986 pSvmTransient->uEflags = ASMIntDisableFlags();
2987 if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS | VM_FF_TM_VIRTUAL_SYNC)
2988 || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2989 {
2990 ASMSetFlags(pSvmTransient->uEflags);
2991 VMMRZCallRing3Enable(pVCpu);
2992 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
2993 return VINF_EM_RAW_TO_R3;
2994 }
2995 if (RTThreadPreemptIsPending(NIL_RTTHREAD))
2996 {
2997 ASMSetFlags(pSvmTransient->uEflags);
2998 VMMRZCallRing3Enable(pVCpu);
2999 STAM_COUNTER_INC(&pVCpu->hm.s.StatPendingHostIrq);
3000 return VINF_EM_RAW_INTERRUPT;
3001 }
3002
3003 /*
3004 * If we are injecting an NMI, we must set VMCPU_FF_BLOCK_NMIS only when we are going to execute
3005 * guest code for certain (no exits to ring-3). Otherwise, we could re-read the flag on re-entry into
3006 * AMD-V and conclude that NMI inhibition is active when we have not even delivered the NMI.
3007 *
3008 * With VT-x, this is handled by the Guest interruptibility information VMCS field which will set the
3009 * VMCS field after actually delivering the NMI which we read on VM-exit to determine the state.
3010 */
3011 if (pVCpu->hm.s.Event.fPending)
3012 {
3013 SVMEVENT Event;
3014 Event.u = pVCpu->hm.s.Event.u64IntInfo;
3015 if ( Event.n.u1Valid
3016 && Event.n.u3Type == SVM_EVENT_NMI
3017 && Event.n.u8Vector == X86_XCPT_NMI
3018 && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
3019 {
3020 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
3021 }
3022 }
3023
3024 return VINF_SUCCESS;
3025}
3026
3027
3028/**
3029 * Prepares to run guest code in AMD-V and we've committed to doing so. This
3030 * means there is no backing out to ring-3 or anywhere else at this
3031 * point.
3032 *
3033 * @param pVM Pointer to the VM.
3034 * @param pVCpu Pointer to the VMCPU.
3035 * @param pCtx Pointer to the guest-CPU context.
3036 * @param pSvmTransient Pointer to the SVM transient structure.
3037 *
3038 * @remarks Called with preemption disabled.
3039 * @remarks No-long-jump zone!!!
3040 */
3041static void hmR0SvmPreRunGuestCommitted(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3042{
3043 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3044 Assert(VMMR0IsLogFlushDisabled(pVCpu));
3045 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3046
3047 VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3048 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
3049
3050 hmR0SvmInjectPendingEvent(pVCpu, pCtx);
3051
3052 if ( pVCpu->hm.s.fUseGuestFpu
3053 && !CPUMIsGuestFPUStateActive(pVCpu))
3054 {
3055 CPUMR0LoadGuestFPU(pVM, pVCpu, pCtx);
3056 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
3057 }
3058
3059 /* Load the state shared between host and guest (FPU, debug). */
3060 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3061 if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_HOST_GUEST_SHARED_STATE))
3062 hmR0SvmLoadSharedState(pVCpu, pVmcb, pCtx);
3063 HMCPU_CF_CLEAR(pVCpu, HM_CHANGED_HOST_CONTEXT); /* Preemption might set this, nothing to do on AMD-V. */
3064 AssertMsg(!HMCPU_CF_VALUE(pVCpu), ("fContextUseFlags=%#RX32\n", HMCPU_CF_VALUE(pVCpu)));
3065
3066 /* Setup TSC offsetting. */
3067 RTCPUID idCurrentCpu = HMR0GetCurrentCpu()->idCpu;
3068 if ( pSvmTransient->fUpdateTscOffsetting
3069 || idCurrentCpu != pVCpu->hm.s.idLastCpu)
3070 {
3071 hmR0SvmUpdateTscOffsetting(pVCpu);
3072 pSvmTransient->fUpdateTscOffsetting = false;
3073 }
3074
3075 /* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
3076 if (idCurrentCpu != pVCpu->hm.s.idLastCpu)
3077 pVmcb->ctrl.u64VmcbCleanBits = 0;
3078
3079 /* Store status of the shared guest-host state at the time of VMRUN. */
3080#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3081 if (CPUMIsGuestInLongModeEx(pCtx))
3082 {
3083 pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
3084 pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
3085 }
3086 else
3087#endif
3088 {
3089 pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
3090 pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
3091 }
3092 pSvmTransient->fWasGuestFPUStateActive = CPUMIsGuestFPUStateActive(pVCpu);
3093
3094 /* Flush the appropriate tagged-TLB entries. */
3095 ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB-shootdowns, set this across the world switch. */
3096 hmR0SvmFlushTaggedTlb(pVCpu);
3097 Assert(HMR0GetCurrentCpu()->idCpu == pVCpu->hm.s.idLastCpu);
3098
3099 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
3100
3101 TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
3102 to start executing. */
3103
3104 /*
3105 * Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that
3106 * RDTSCPs (that don't cause exits) reads the guest MSR. See @bugref{3324}.
3107 *
3108 * This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
3109 */
3110 if ( (pVM->hm.s.cpuid.u32AMDFeatureEDX & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
3111 && !(pVmcb->ctrl.u32InterceptCtrl2 & SVM_CTRL2_INTERCEPT_RDTSCP))
3112 {
3113 hmR0SvmSetMsrPermission(pVCpu, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
3114 pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
3115 uint64_t u64GuestTscAux = CPUMR0GetGuestTscAux(pVCpu);
3116 if (u64GuestTscAux != pVCpu->hm.s.u64HostTscAux)
3117 ASMWrMsr(MSR_K8_TSC_AUX, u64GuestTscAux);
3118 pSvmTransient->fRestoreTscAuxMsr = true;
3119 }
3120 else
3121 {
3122 hmR0SvmSetMsrPermission(pVCpu, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
3123 pSvmTransient->fRestoreTscAuxMsr = false;
3124 }
3125
3126 /* If VMCB Clean bits isn't supported by the CPU, simply mark all state-bits as dirty, indicating (re)load-from-VMCB. */
3127 if (!(pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN))
3128 pVmcb->ctrl.u64VmcbCleanBits = 0;
3129}
3130
3131
3132/**
3133 * Wrapper for running the guest code in AMD-V.
3134 *
3135 * @returns VBox strict status code.
3136 * @param pVM Pointer to the VM.
3137 * @param pVCpu Pointer to the VMCPU.
3138 * @param pCtx Pointer to the guest-CPU context.
3139 *
3140 * @remarks No-long-jump zone!!!
3141 */
3142DECLINLINE(int) hmR0SvmRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3143{
3144 /*
3145 * 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses floating-point operations
3146 * using SSE instructions. Some XMM registers (XMM6-XMM15) are callee-saved and thus the need for this XMM wrapper.
3147 * Refer MSDN docs. "Configuring Programs for 64-bit / x64 Software Conventions / Register Usage" for details.
3148 */
3149#ifdef VBOX_WITH_KERNEL_USING_XMM
3150 return HMR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu,
3151 pVCpu->hm.s.svm.pfnVMRun);
3152#else
3153 return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, pVCpu->hm.s.svm.HCPhysVmcb, pCtx, pVM, pVCpu);
3154#endif
3155}
3156
3157
3158/**
3159 * Performs some essential restoration of state after running guest code in
3160 * AMD-V.
3161 *
3162 * @param pVM Pointer to the VM.
3163 * @param pVCpu Pointer to the VMCPU.
3164 * @param pMixedCtx Pointer to the guest-CPU context. The data maybe
3165 * out-of-sync. Make sure to update the required fields
3166 * before using them.
3167 * @param pSvmTransient Pointer to the SVM transient structure.
3168 * @param rcVMRun Return code of VMRUN.
3169 *
3170 * @remarks Called with interrupts disabled.
3171 * @remarks No-long-jump zone!!! This function will however re-enable longjmps
3172 * unconditionally when it is safe to do so.
3173 */
3174static void hmR0SvmPostRunGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pMixedCtx, PSVMTRANSIENT pSvmTransient, int rcVMRun)
3175{
3176 Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3177
3178 ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB-shootdowns. */
3179 ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for TLB-shootdowns. */
3180
3181 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3182 pVmcb->ctrl.u64VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
3183
3184 if (pSvmTransient->fRestoreTscAuxMsr)
3185 {
3186 uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
3187 CPUMR0SetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
3188 if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
3189 ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
3190 }
3191
3192 if (!(pVmcb->ctrl.u32InterceptCtrl1 & SVM_CTRL1_INTERCEPT_RDTSC))
3193 TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVmcb->ctrl.u64TSCOffset); /** @todo use SUPReadTSC() eventually. */
3194
3195 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
3196 TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
3197 VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
3198
3199 Assert(!(ASMGetFlags() & X86_EFL_IF));
3200 ASMSetFlags(pSvmTransient->uEflags); /* Enable interrupts. */
3201 VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
3202
3203 /* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
3204 if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
3205 {
3206 Log4(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
3207 return;
3208 }
3209
3210 pSvmTransient->u64ExitCode = pVmcb->ctrl.u64ExitCode; /* Save the #VMEXIT reason. */
3211 HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcb->ctrl.u64ExitCode); /* Update the #VMEXIT history array. */
3212 pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
3213 pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
3214
3215 hmR0SvmSaveGuestState(pVCpu, pMixedCtx); /* Save the guest state from the VMCB to the guest-CPU context. */
3216
3217 if (RT_LIKELY(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID))
3218 {
3219 if (pVCpu->hm.s.svm.fSyncVTpr)
3220 {
3221 /* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
3222 if ( pVM->hm.s.fTPRPatchingActive
3223 && (pMixedCtx->msrLSTAR & 0xff) != pSvmTransient->u8GuestTpr)
3224 {
3225 int rc = PDMApicSetTPR(pVCpu, pMixedCtx->msrLSTAR & 0xff);
3226 AssertRC(rc);
3227 HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
3228 }
3229 else if (pSvmTransient->u8GuestTpr != pVmcb->ctrl.IntCtrl.n.u8VTPR)
3230 {
3231 int rc = PDMApicSetTPR(pVCpu, pVmcb->ctrl.IntCtrl.n.u8VTPR << 4);
3232 AssertRC(rc);
3233 HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
3234 }
3235 }
3236 }
3237}
3238
3239
3240/**
3241 * Runs the guest code using AMD-V.
3242 *
3243 * @returns VBox status code.
3244 * @param pVM Pointer to the VM.
3245 * @param pVCpu Pointer to the VMCPU.
3246 */
3247static int hmR0SvmRunGuestCodeNormal(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3248{
3249 SVMTRANSIENT SvmTransient;
3250 SvmTransient.fUpdateTscOffsetting = true;
3251 uint32_t cLoops = 0;
3252 int rc = VERR_INTERNAL_ERROR_5;
3253
3254 for (;; cLoops++)
3255 {
3256 Assert(!HMR0SuspendPending());
3257 HMSVM_ASSERT_CPU_SAFE();
3258
3259 /* Preparatory work for running guest code, this may force us to return
3260 to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
3261 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
3262 rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
3263 if (rc != VINF_SUCCESS)
3264 break;
3265
3266 /*
3267 * No longjmps to ring-3 from this point on!!!
3268 * Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3269 * This also disables flushing of the R0-logger instance (if any).
3270 */
3271 hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
3272 rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
3273
3274 /* Restore any residual host-state and save any bits shared between host
3275 and guest into the guest-CPU state. Re-enables interrupts! */
3276 hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
3277
3278 if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
3279 || SvmTransient.u64ExitCode == (uint64_t)SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
3280 {
3281 if (rc == VINF_SUCCESS)
3282 rc = VERR_SVM_INVALID_GUEST_STATE;
3283 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
3284 hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
3285 break;
3286 }
3287
3288 /* Handle the #VMEXIT. */
3289 HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
3290 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
3291 VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb);
3292 rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
3293 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
3294 if (rc != VINF_SUCCESS)
3295 break;
3296 if (cLoops > pVM->hm.s.cMaxResumeLoops)
3297 {
3298 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMaxResume);
3299 rc = VINF_EM_RAW_INTERRUPT;
3300 break;
3301 }
3302 }
3303
3304 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
3305 return rc;
3306}
3307
3308
3309/**
3310 * Runs the guest code using AMD-V in single step mode.
3311 *
3312 * @returns VBox status code.
3313 * @param pVM Pointer to the VM.
3314 * @param pVCpu Pointer to the VMCPU.
3315 * @param pCtx Pointer to the guest-CPU context.
3316 */
3317static int hmR0SvmRunGuestCodeStep(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3318{
3319 SVMTRANSIENT SvmTransient;
3320 SvmTransient.fUpdateTscOffsetting = true;
3321 uint32_t cLoops = 0;
3322 int rc = VERR_INTERNAL_ERROR_5;
3323 uint16_t uCsStart = pCtx->cs.Sel;
3324 uint64_t uRipStart = pCtx->rip;
3325
3326 for (;; cLoops++)
3327 {
3328 Assert(!HMR0SuspendPending());
3329 AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
3330 ("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
3331 (unsigned)RTMpCpuId(), cLoops));
3332
3333 /* Preparatory work for running guest code, this may force us to return
3334 to ring-3. This bugger disables interrupts on VINF_SUCCESS! */
3335 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
3336 rc = hmR0SvmPreRunGuest(pVM, pVCpu, pCtx, &SvmTransient);
3337 if (rc != VINF_SUCCESS)
3338 break;
3339
3340 /*
3341 * No longjmps to ring-3 from this point on!!!
3342 * Asserts() will still longjmp to ring-3 (but won't return), which is intentional, better than a kernel panic.
3343 * This also disables flushing of the R0-logger instance (if any).
3344 */
3345 VMMRZCallRing3Disable(pVCpu);
3346 VMMRZCallRing3RemoveNotification(pVCpu);
3347 hmR0SvmPreRunGuestCommitted(pVM, pVCpu, pCtx, &SvmTransient);
3348
3349 rc = hmR0SvmRunGuest(pVM, pVCpu, pCtx);
3350
3351 /*
3352 * Restore any residual host-state and save any bits shared between host and guest into the guest-CPU state.
3353 * This will also re-enable longjmps to ring-3 when it has reached a safe point!!!
3354 */
3355 hmR0SvmPostRunGuest(pVM, pVCpu, pCtx, &SvmTransient, rc);
3356 if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
3357 || SvmTransient.u64ExitCode == (uint64_t)SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
3358 {
3359 if (rc == VINF_SUCCESS)
3360 rc = VERR_SVM_INVALID_GUEST_STATE;
3361 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit1, x);
3362 hmR0SvmReportWorldSwitchError(pVM, pVCpu, rc, pCtx);
3363 return rc;
3364 }
3365
3366 /* Handle the #VMEXIT. */
3367 HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
3368 STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatExit1, &pVCpu->hm.s.StatExit2, x);
3369 VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb);
3370 rc = hmR0SvmHandleExit(pVCpu, pCtx, &SvmTransient);
3371 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExit2, x);
3372 if (rc != VINF_SUCCESS)
3373 break;
3374 if (cLoops > pVM->hm.s.cMaxResumeLoops)
3375 {
3376 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMaxResume);
3377 rc = VINF_EM_RAW_INTERRUPT;
3378 break;
3379 }
3380
3381 /*
3382 * Did the RIP change, if so, consider it a single step.
3383 * Otherwise, make sure one of the TFs gets set.
3384 */
3385 if ( pCtx->rip != uRipStart
3386 || pCtx->cs.Sel != uCsStart)
3387 {
3388 rc = VINF_EM_DBG_STEPPED;
3389 break;
3390 }
3391 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_GUEST_DEBUG;
3392 }
3393
3394 /*
3395 * Clear the X86_EFL_TF if necessary.
3396 */
3397 if (pVCpu->hm.s.fClearTrapFlag)
3398 {
3399 pVCpu->hm.s.fClearTrapFlag = false;
3400 pCtx->eflags.Bits.u1TF = 0;
3401 }
3402
3403 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
3404 return rc;
3405}
3406
3407
3408/**
3409 * Runs the guest code using AMD-V.
3410 *
3411 * @returns VBox status code.
3412 * @param pVM Pointer to the VM.
3413 * @param pVCpu Pointer to the VMCPU.
3414 * @param pCtx Pointer to the guest-CPU context.
3415 */
3416VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3417{
3418 Assert(VMMRZCallRing3IsEnabled(pVCpu));
3419 HMSVM_ASSERT_PREEMPT_SAFE();
3420 VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, pCtx);
3421
3422 int rc;
3423 if (!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu))
3424 rc = hmR0SvmRunGuestCodeNormal(pVM, pVCpu, pCtx);
3425 else
3426 rc = hmR0SvmRunGuestCodeStep(pVM, pVCpu, pCtx);
3427
3428 if (rc == VERR_EM_INTERPRETER)
3429 rc = VINF_EM_RAW_EMULATE_INSTR;
3430 else if (rc == VINF_EM_RESET)
3431 rc = VINF_EM_TRIPLE_FAULT;
3432
3433 /* Prepare to return to ring-3. This will remove longjmp notifications. */
3434 hmR0SvmExitToRing3(pVM, pVCpu, pCtx, rc);
3435 Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
3436 return rc;
3437}
3438
3439
3440/**
3441 * Handles a #VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
3442 *
3443 * @returns VBox status code (informational status codes included).
3444 * @param pVCpu Pointer to the VMCPU.
3445 * @param pCtx Pointer to the guest-CPU context.
3446 * @param pSvmTransient Pointer to the SVM transient structure.
3447 */
3448DECLINLINE(int) hmR0SvmHandleExit(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
3449{
3450 Assert(pSvmTransient->u64ExitCode != (uint64_t)SVM_EXIT_INVALID);
3451 Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
3452
3453 /*
3454 * The ordering of the case labels is based on most-frequently-occurring #VMEXITs for most guests under
3455 * normal workloads (for some definition of "normal").
3456 */
3457 uint32_t u32ExitCode = pSvmTransient->u64ExitCode;
3458 switch (pSvmTransient->u64ExitCode)
3459 {
3460 case SVM_EXIT_NPF:
3461 return hmR0SvmExitNestedPF(pVCpu, pCtx, pSvmTransient);
3462
3463 case SVM_EXIT_IOIO:
3464 return hmR0SvmExitIOInstr(pVCpu, pCtx, pSvmTransient);
3465
3466 case SVM_EXIT_RDTSC:
3467 return hmR0SvmExitRdtsc(pVCpu, pCtx, pSvmTransient);
3468
3469 case SVM_EXIT_RDTSCP:
3470 return hmR0SvmExitRdtscp(pVCpu, pCtx, pSvmTransient);
3471
3472 case SVM_EXIT_CPUID:
3473 return hmR0SvmExitCpuid(pVCpu, pCtx, pSvmTransient);
3474
3475 case SVM_EXIT_EXCEPTION_E: /* X86_XCPT_PF */
3476 return hmR0SvmExitXcptPF(pVCpu, pCtx, pSvmTransient);
3477
3478 case SVM_EXIT_EXCEPTION_7: /* X86_XCPT_NM */
3479 return hmR0SvmExitXcptNM(pVCpu, pCtx, pSvmTransient);
3480
3481 case SVM_EXIT_EXCEPTION_10: /* X86_XCPT_MF */
3482 return hmR0SvmExitXcptMF(pVCpu, pCtx, pSvmTransient);
3483
3484 case SVM_EXIT_EXCEPTION_1: /* X86_XCPT_DB */
3485 return hmR0SvmExitXcptDB(pVCpu, pCtx, pSvmTransient);
3486
3487 case SVM_EXIT_MONITOR:
3488 return hmR0SvmExitMonitor(pVCpu, pCtx, pSvmTransient);
3489
3490 case SVM_EXIT_MWAIT:
3491 return hmR0SvmExitMwait(pVCpu, pCtx, pSvmTransient);
3492
3493 case SVM_EXIT_HLT:
3494 return hmR0SvmExitHlt(pVCpu, pCtx, pSvmTransient);
3495
3496 case SVM_EXIT_READ_CR0:
3497 case SVM_EXIT_READ_CR3:
3498 case SVM_EXIT_READ_CR4:
3499 return hmR0SvmExitReadCRx(pVCpu, pCtx, pSvmTransient);
3500
3501 case SVM_EXIT_WRITE_CR0:
3502 case SVM_EXIT_WRITE_CR3:
3503 case SVM_EXIT_WRITE_CR4:
3504 case SVM_EXIT_WRITE_CR8:
3505 return hmR0SvmExitWriteCRx(pVCpu, pCtx, pSvmTransient);
3506
3507 case SVM_EXIT_VINTR:
3508 return hmR0SvmExitVIntr(pVCpu, pCtx, pSvmTransient);
3509
3510 case SVM_EXIT_INTR:
3511 case SVM_EXIT_FERR_FREEZE:
3512 case SVM_EXIT_NMI:
3513 return hmR0SvmExitIntr(pVCpu, pCtx, pSvmTransient);
3514
3515 case SVM_EXIT_MSR:
3516 return hmR0SvmExitMsr(pVCpu, pCtx, pSvmTransient);
3517
3518 case SVM_EXIT_INVLPG:
3519 return hmR0SvmExitInvlpg(pVCpu, pCtx, pSvmTransient);
3520
3521 case SVM_EXIT_WBINVD:
3522 return hmR0SvmExitWbinvd(pVCpu, pCtx, pSvmTransient);
3523
3524 case SVM_EXIT_INVD:
3525 return hmR0SvmExitInvd(pVCpu, pCtx, pSvmTransient);
3526
3527 case SVM_EXIT_RDPMC:
3528 return hmR0SvmExitRdpmc(pVCpu, pCtx, pSvmTransient);
3529
3530 default:
3531 {
3532 switch (pSvmTransient->u64ExitCode)
3533 {
3534 case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
3535 case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
3536 case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
3537 case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
3538 return hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
3539
3540 case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
3541 case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
3542 case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
3543 case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
3544 return hmR0SvmExitWriteDRx(pVCpu, pCtx, pSvmTransient);
3545
3546 case SVM_EXIT_TASK_SWITCH:
3547 return hmR0SvmExitTaskSwitch(pVCpu, pCtx, pSvmTransient);
3548
3549 case SVM_EXIT_VMMCALL:
3550 return hmR0SvmExitVmmCall(pVCpu, pCtx, pSvmTransient);
3551
3552 case SVM_EXIT_IRET:
3553 return hmR0SvmExitIret(pVCpu, pCtx, pSvmTransient);
3554
3555 case SVM_EXIT_SHUTDOWN:
3556 return hmR0SvmExitShutdown(pVCpu, pCtx, pSvmTransient);
3557
3558 case SVM_EXIT_SMI:
3559 case SVM_EXIT_INIT:
3560 {
3561 /*
3562 * We don't intercept NMIs. As for INIT signals, it really shouldn't ever happen here. If it ever does,
3563 * we want to know about it so log the exit code and bail.
3564 */
3565 AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
3566 pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
3567 return VERR_SVM_UNEXPECTED_EXIT;
3568 }
3569
3570 case SVM_EXIT_INVLPGA:
3571 case SVM_EXIT_RSM:
3572 case SVM_EXIT_VMRUN:
3573 case SVM_EXIT_VMLOAD:
3574 case SVM_EXIT_VMSAVE:
3575 case SVM_EXIT_STGI:
3576 case SVM_EXIT_CLGI:
3577 case SVM_EXIT_SKINIT:
3578 return hmR0SvmExitSetPendingXcptUD(pVCpu, pCtx, pSvmTransient);
3579
3580#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
3581 case SVM_EXIT_EXCEPTION_0: /* X86_XCPT_DE */
3582 /* SVM_EXIT_EXCEPTION_1: */ /* X86_XCPT_DB - Handled above. */
3583 case SVM_EXIT_EXCEPTION_2: /* X86_XCPT_NMI */
3584 case SVM_EXIT_EXCEPTION_3: /* X86_XCPT_BP */
3585 case SVM_EXIT_EXCEPTION_4: /* X86_XCPT_OF */
3586 case SVM_EXIT_EXCEPTION_5: /* X86_XCPT_BR */
3587 case SVM_EXIT_EXCEPTION_6: /* X86_XCPT_UD */
3588 /* SVM_EXIT_EXCEPTION_7: */ /* X86_XCPT_NM - Handled above. */
3589 case SVM_EXIT_EXCEPTION_8: /* X86_XCPT_DF */
3590 case SVM_EXIT_EXCEPTION_9: /* X86_XCPT_CO_SEG_OVERRUN */
3591 case SVM_EXIT_EXCEPTION_A: /* X86_XCPT_TS */
3592 case SVM_EXIT_EXCEPTION_B: /* X86_XCPT_NP */
3593 case SVM_EXIT_EXCEPTION_C: /* X86_XCPT_SS */
3594 case SVM_EXIT_EXCEPTION_D: /* X86_XCPT_GP */
3595 /* SVM_EXIT_EXCEPTION_E: */ /* X86_XCPT_PF - Handled above. */
3596 /* SVM_EXIT_EXCEPTION_10: */ /* X86_XCPT_MF - Handled above. */
3597 case SVM_EXIT_EXCEPTION_11: /* X86_XCPT_AC */
3598 case SVM_EXIT_EXCEPTION_12: /* X86_XCPT_MC */
3599 case SVM_EXIT_EXCEPTION_13: /* X86_XCPT_XF */
3600 case SVM_EXIT_EXCEPTION_F: /* Reserved */
3601 case SVM_EXIT_EXCEPTION_14: case SVM_EXIT_EXCEPTION_15: case SVM_EXIT_EXCEPTION_16:
3602 case SVM_EXIT_EXCEPTION_17: case SVM_EXIT_EXCEPTION_18: case SVM_EXIT_EXCEPTION_19:
3603 case SVM_EXIT_EXCEPTION_1A: case SVM_EXIT_EXCEPTION_1B: case SVM_EXIT_EXCEPTION_1C:
3604 case SVM_EXIT_EXCEPTION_1D: case SVM_EXIT_EXCEPTION_1E: case SVM_EXIT_EXCEPTION_1F:
3605 {
3606 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
3607 SVMEVENT Event;
3608 Event.u = 0;
3609 Event.n.u1Valid = 1;
3610 Event.n.u3Type = SVM_EVENT_EXCEPTION;
3611 Event.n.u8Vector = pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0;
3612
3613 switch (Event.n.u8Vector)
3614 {
3615 case X86_XCPT_DE:
3616 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDE);
3617 break;
3618
3619 case X86_XCPT_BP:
3620 /** Saves the wrong EIP on the stack (pointing to the int3) instead of the
3621 * next instruction. */
3622 /** @todo Investigate this later. */
3623 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
3624 break;
3625
3626 case X86_XCPT_UD:
3627 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
3628 break;
3629
3630 case X86_XCPT_NP:
3631 Event.n.u1ErrorCodeValid = 1;
3632 Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3633 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNP);
3634 break;
3635
3636 case X86_XCPT_SS:
3637 Event.n.u1ErrorCodeValid = 1;
3638 Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3639 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestSS);
3640 break;
3641
3642 case X86_XCPT_GP:
3643 Event.n.u1ErrorCodeValid = 1;
3644 Event.n.u32ErrorCode = pVmcb->ctrl.u64ExitInfo1;
3645 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
3646 break;
3647
3648 default:
3649 AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit caused by exception %#x\n", Event.n.u8Vector));
3650 pVCpu->hm.s.u32HMError = Event.n.u8Vector;
3651 return VERR_SVM_UNEXPECTED_XCPT_EXIT;
3652 }
3653
3654 Log4(("#Xcpt: Vector=%#x at CS:RIP=%04x:%RGv\n", Event.n.u8Vector, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
3655 hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3656 return VINF_SUCCESS;
3657 }
3658#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
3659
3660 default:
3661 {
3662 AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#x\n", u32ExitCode));
3663 pVCpu->hm.s.u32HMError = u32ExitCode;
3664 return VERR_SVM_UNKNOWN_EXIT;
3665 }
3666 }
3667 }
3668 }
3669 return VERR_INTERNAL_ERROR_5; /* Should never happen. */
3670}
3671
3672
3673#ifdef DEBUG
3674/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
3675# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
3676 RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
3677
3678# define HMSVM_ASSERT_PREEMPT_CPUID() \
3679 do \
3680 { \
3681 RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
3682 AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
3683 } while (0)
3684
3685# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() \
3686 do { \
3687 AssertPtr(pVCpu); \
3688 AssertPtr(pCtx); \
3689 AssertPtr(pSvmTransient); \
3690 Assert(ASMIntAreEnabled()); \
3691 HMSVM_ASSERT_PREEMPT_SAFE(); \
3692 HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
3693 Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (uint32_t)pVCpu->idCpu)); \
3694 HMSVM_ASSERT_PREEMPT_SAFE(); \
3695 if (VMMR0IsLogFlushDisabled(pVCpu)) \
3696 HMSVM_ASSERT_PREEMPT_CPUID(); \
3697 } while (0)
3698#else /* Release builds */
3699# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS() do { NOREF(pVCpu); NOREF(pCtx); NOREF(pSvmTransient); } while (0)
3700#endif
3701
3702
3703/**
3704 * Worker for hmR0SvmInterpretInvlpg().
3705 *
3706 * @return VBox status code.
3707 * @param pVCpu Pointer to the VMCPU.
3708 * @param pCpu Pointer to the disassembler state.
3709 * @param pRegFrame Pointer to the register frame.
3710 */
3711static int hmR0SvmInterpretInvlPgEx(PVMCPU pVCpu, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame)
3712{
3713 DISQPVPARAMVAL Param1;
3714 RTGCPTR GCPtrPage;
3715
3716 int rc = DISQueryParamVal(pRegFrame, pCpu, &pCpu->Param1, &Param1, DISQPVWHICH_SRC);
3717 if (RT_FAILURE(rc))
3718 return VERR_EM_INTERPRETER;
3719
3720 if ( Param1.type == DISQPV_TYPE_IMMEDIATE
3721 || Param1.type == DISQPV_TYPE_ADDRESS)
3722 {
3723 if (!(Param1.flags & (DISQPV_FLAG_32 | DISQPV_FLAG_64)))
3724 return VERR_EM_INTERPRETER;
3725
3726 GCPtrPage = Param1.val.val64;
3727 VBOXSTRICTRC rc2 = EMInterpretInvlpg(pVCpu->CTX_SUFF(pVM), pVCpu, pRegFrame, GCPtrPage);
3728 rc = VBOXSTRICTRC_VAL(rc2);
3729 }
3730 else
3731 {
3732 Log4(("hmR0SvmInterpretInvlPgEx invalid parameter type %#x\n", Param1.type));
3733 rc = VERR_EM_INTERPRETER;
3734 }
3735
3736 return rc;
3737}
3738
3739
3740/**
3741 * Interprets INVLPG.
3742 *
3743 * @returns VBox status code.
3744 * @retval VINF_* Scheduling instructions.
3745 * @retval VERR_EM_INTERPRETER Something we can't cope with.
3746 * @retval VERR_* Fatal errors.
3747 *
3748 * @param pVM Pointer to the VM.
3749 * @param pRegFrame Pointer to the register frame.
3750 *
3751 * @remarks Updates the RIP if the instruction was executed successfully.
3752 */
3753static int hmR0SvmInterpretInvlpg(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame)
3754{
3755 /* Only allow 32 & 64 bit code. */
3756 if (CPUMGetGuestCodeBits(pVCpu) != 16)
3757 {
3758 PDISSTATE pDis = &pVCpu->hm.s.DisState;
3759 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL /* pcbInstr */);
3760 if ( RT_SUCCESS(rc)
3761 && pDis->pCurInstr->uOpcode == OP_INVLPG)
3762 {
3763 rc = hmR0SvmInterpretInvlPgEx(pVCpu, pDis, pRegFrame);
3764 if (RT_SUCCESS(rc))
3765 pRegFrame->rip += pDis->cbInstr;
3766 return rc;
3767 }
3768 else
3769 Log4(("hmR0SvmInterpretInvlpg: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
3770 }
3771 return VERR_EM_INTERPRETER;
3772}
3773
3774
3775/**
3776 * Sets an invalid-opcode (#UD) exception as pending-for-injection into the VM.
3777 *
3778 * @param pVCpu Pointer to the VMCPU.
3779 */
3780DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3781{
3782 SVMEVENT Event;
3783 Event.u = 0;
3784 Event.n.u1Valid = 1;
3785 Event.n.u3Type = SVM_EVENT_EXCEPTION;
3786 Event.n.u8Vector = X86_XCPT_UD;
3787 hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3788}
3789
3790
3791/**
3792 * Sets a debug (#DB) exception as pending-for-injection into the VM.
3793 *
3794 * @param pVCpu Pointer to the VMCPU.
3795 */
3796DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3797{
3798 SVMEVENT Event;
3799 Event.u = 0;
3800 Event.n.u1Valid = 1;
3801 Event.n.u3Type = SVM_EVENT_EXCEPTION;
3802 Event.n.u8Vector = X86_XCPT_DB;
3803 hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3804}
3805
3806
3807/**
3808 * Sets a page fault (#PF) exception as pending-for-injection into the VM.
3809 *
3810 * @param pVCpu Pointer to the VMCPU.
3811 * @param pCtx Pointer to the guest-CPU context.
3812 * @param u32ErrCode The error-code for the page-fault.
3813 * @param uFaultAddress The page fault address (CR2).
3814 *
3815 * @remarks This updates the guest CR2 with @a uFaultAddress!
3816 */
3817DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3818{
3819 SVMEVENT Event;
3820 Event.u = 0;
3821 Event.n.u1Valid = 1;
3822 Event.n.u3Type = SVM_EVENT_EXCEPTION;
3823 Event.n.u8Vector = X86_XCPT_PF;
3824 Event.n.u1ErrorCodeValid = 1;
3825 Event.n.u32ErrorCode = u32ErrCode;
3826
3827 /* Update CR2 of the guest. */
3828 if (pCtx->cr2 != uFaultAddress)
3829 {
3830 pCtx->cr2 = uFaultAddress;
3831 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR2);
3832 }
3833
3834 hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3835}
3836
3837
3838/**
3839 * Sets a device-not-available (#NM) exception as pending-for-injection into the
3840 * VM.
3841 *
3842 * @param pVCpu Pointer to the VMCPU.
3843 */
3844DECLINLINE(void) hmR0SvmSetPendingXcptNM(PVMCPU pVCpu)
3845{
3846 SVMEVENT Event;
3847 Event.u = 0;
3848 Event.n.u1Valid = 1;
3849 Event.n.u3Type = SVM_EVENT_EXCEPTION;
3850 Event.n.u8Vector = X86_XCPT_NM;
3851 hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3852}
3853
3854
3855/**
3856 * Sets a math-fault (#MF) exception as pending-for-injection into the VM.
3857 *
3858 * @param pVCpu Pointer to the VMCPU.
3859 */
3860DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3861{
3862 SVMEVENT Event;
3863 Event.u = 0;
3864 Event.n.u1Valid = 1;
3865 Event.n.u3Type = SVM_EVENT_EXCEPTION;
3866 Event.n.u8Vector = X86_XCPT_MF;
3867 hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3868}
3869
3870
3871/**
3872 * Sets a double fault (#DF) exception as pending-for-injection into the VM.
3873 *
3874 * @param pVCpu Pointer to the VMCPU.
3875 */
3876DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3877{
3878 SVMEVENT Event;
3879 Event.u = 0;
3880 Event.n.u1Valid = 1;
3881 Event.n.u3Type = SVM_EVENT_EXCEPTION;
3882 Event.n.u8Vector = X86_XCPT_DF;
3883 Event.n.u1ErrorCodeValid = 1;
3884 Event.n.u32ErrorCode = 0;
3885 hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3886}
3887
3888
3889/**
3890 * Emulates a simple MOV TPR (CR8) instruction, used for TPR patching on 32-bit
3891 * guests. This simply looks up the patch record at EIP and does the required.
3892 *
3893 * This VMMCALL is used a fallback mechanism when mov to/from cr8 isn't exactly
3894 * like how we want it to be (e.g. not followed by shr 4 as is usually done for
3895 * TPR). See hmR3ReplaceTprInstr() for the details.
3896 *
3897 * @returns VBox status code.
3898 * @retval VINF_SUCCESS if the access was handled successfully.
3899 * @retval VERR_NOT_FOUND if no patch record for this eip could be found.
3900 * @retval VERR_SVM_UNEXPECTED_PATCH_TYPE if the found patch type is invalid.
3901 *
3902 * @param pVM Pointer to the VM.
3903 * @param pVCpu Pointer to the VMCPU.
3904 * @param pCtx Pointer to the guest-CPU context.
3905 */
3906static int hmR0SvmEmulateMovTpr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3907{
3908 Log4(("Emulated VMMCall TPR access replacement at RIP=%RGv\n", pCtx->rip));
3909
3910 /*
3911 * We do this in a loop as we increment the RIP after a successful emulation
3912 * and the new RIP may be a patched instruction which needs emulation as well.
3913 */
3914 bool fPatchFound = false;
3915 for (;;)
3916 {
3917 bool fPending;
3918 uint8_t u8Tpr;
3919
3920 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
3921 if (!pPatch)
3922 break;
3923
3924 fPatchFound = true;
3925 switch (pPatch->enmType)
3926 {
3927 case HMTPRINSTR_READ:
3928 {
3929 int rc = PDMApicGetTPR(pVCpu, &u8Tpr, &fPending, NULL /* pu8PendingIrq */);
3930 AssertRC(rc);
3931
3932 rc = DISWriteReg32(CPUMCTX2CORE(pCtx), pPatch->uDstOperand, u8Tpr);
3933 AssertRC(rc);
3934 pCtx->rip += pPatch->cbOp;
3935 break;
3936 }
3937
3938 case HMTPRINSTR_WRITE_REG:
3939 case HMTPRINSTR_WRITE_IMM:
3940 {
3941 if (pPatch->enmType == HMTPRINSTR_WRITE_REG)
3942 {
3943 uint32_t u32Val;
3944 int rc = DISFetchReg32(CPUMCTX2CORE(pCtx), pPatch->uSrcOperand, &u32Val);
3945 AssertRC(rc);
3946 u8Tpr = u32Val;
3947 }
3948 else
3949 u8Tpr = (uint8_t)pPatch->uSrcOperand;
3950
3951 int rc2 = PDMApicSetTPR(pVCpu, u8Tpr);
3952 AssertRC(rc2);
3953 HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
3954
3955 pCtx->rip += pPatch->cbOp;
3956 break;
3957 }
3958
3959 default:
3960 AssertMsgFailed(("Unexpected patch type %d\n", pPatch->enmType));
3961 pVCpu->hm.s.u32HMError = pPatch->enmType;
3962 return VERR_SVM_UNEXPECTED_PATCH_TYPE;
3963 }
3964 }
3965
3966 if (fPatchFound)
3967 return VINF_SUCCESS;
3968 return VERR_NOT_FOUND;
3969}
3970
3971
3972/**
3973 * Determines if an exception is a contributory exception.
3974 *
3975 * Contributory exceptions are ones which can cause double-faults unless the
3976 * original exception was a benign exception. Page-fault is intentionally not
3977 * included here as it's a conditional contributory exception.
3978 *
3979 * @returns true if the exception is contributory, false otherwise.
3980 * @param uVector The exception vector.
3981 */
3982DECLINLINE(bool) hmR0SvmIsContributoryXcpt(const uint32_t uVector)
3983{
3984 switch (uVector)
3985 {
3986 case X86_XCPT_GP:
3987 case X86_XCPT_SS:
3988 case X86_XCPT_NP:
3989 case X86_XCPT_TS:
3990 case X86_XCPT_DE:
3991 return true;
3992 default:
3993 break;
3994 }
3995 return false;
3996}
3997
3998
3999/**
4000 * Handle a condition that occurred while delivering an event through the guest
4001 * IDT.
4002 *
4003 * @returns VBox status code (informational error codes included).
4004 * @retval VINF_SUCCESS if we should continue handling the #VMEXIT.
4005 * @retval VINF_HM_DOUBLE_FAULT if a #DF condition was detected and we ought to
4006 * continue execution of the guest which will delivery the #DF.
4007 * @retval VINF_EM_RESET if we detected a triple-fault condition.
4008 *
4009 * @param pVCpu Pointer to the VMCPU.
4010 * @param pCtx Pointer to the guest-CPU context.
4011 * @param pSvmTransient Pointer to the SVM transient structure.
4012 *
4013 * @remarks No-long-jump zone!!!
4014 */
4015static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4016{
4017 int rc = VINF_SUCCESS;
4018 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4019
4020 /* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code". The EXITINTINFO (if valid) contains the prior exception (IDT vector)
4021 * that was trying to be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector). */
4022 if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
4023 {
4024 uint8_t uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
4025
4026 typedef enum
4027 {
4028 SVMREFLECTXCPT_XCPT, /* Reflect the exception to the guest or for further evaluation by VMM. */
4029 SVMREFLECTXCPT_DF, /* Reflect the exception as a double-fault to the guest. */
4030 SVMREFLECTXCPT_TF, /* Indicate a triple faulted state to the VMM. */
4031 SVMREFLECTXCPT_NONE /* Nothing to reflect. */
4032 } SVMREFLECTXCPT;
4033
4034 SVMREFLECTXCPT enmReflect = SVMREFLECTXCPT_NONE;
4035 bool fReflectingNmi = false;
4036 if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION)
4037 {
4038 if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_1F)
4039 {
4040 uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
4041
4042#ifdef VBOX_STRICT
4043 if ( hmR0SvmIsContributoryXcpt(uIdtVector)
4044 && uExitVector == X86_XCPT_PF)
4045 {
4046 Log4(("IDT: Contributory #PF uCR2=%#RX64\n", pVCpu->idCpu, pCtx->cr2));
4047 }
4048#endif
4049 if ( uExitVector == X86_XCPT_PF
4050 && uIdtVector == X86_XCPT_PF)
4051 {
4052 pSvmTransient->fVectoringDoublePF = true;
4053 Log4(("IDT: Vectoring double #PF uCR2=%#RX64\n", pCtx->cr2));
4054 }
4055 else if ( (pVmcb->ctrl.u32InterceptException & HMSVM_CONTRIBUTORY_XCPT_MASK)
4056 && hmR0SvmIsContributoryXcpt(uExitVector)
4057 && ( hmR0SvmIsContributoryXcpt(uIdtVector)
4058 || uIdtVector == X86_XCPT_PF))
4059 {
4060 enmReflect = SVMREFLECTXCPT_DF;
4061 Log4(("IDT: Pending vectoring #DF %#RX64 uIdtVector=%#x uExitVector=%#x\n", pVCpu->hm.s.Event.u64IntInfo,
4062 uIdtVector, uExitVector));
4063 }
4064 else if (uIdtVector == X86_XCPT_DF)
4065 {
4066 enmReflect = SVMREFLECTXCPT_TF;
4067 Log4(("IDT: Pending vectoring triple-fault %#RX64 uIdtVector=%#x uExitVector=%#x\n",
4068 pVCpu->hm.s.Event.u64IntInfo, uIdtVector, uExitVector));
4069 }
4070 else
4071 enmReflect = SVMREFLECTXCPT_XCPT;
4072 }
4073 else
4074 {
4075 /*
4076 * If event delivery caused an #VMEXIT that is not an exception (e.g. #NPF) then reflect the original
4077 * exception to the guest after handling the #VMEXIT.
4078 */
4079 enmReflect = SVMREFLECTXCPT_XCPT;
4080 }
4081 }
4082 else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXTERNAL_IRQ
4083 || pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
4084 {
4085 enmReflect = SVMREFLECTXCPT_XCPT;
4086 fReflectingNmi = RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI);
4087
4088 if (pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0 <= SVM_EXIT_EXCEPTION_1F)
4089 {
4090 uint8_t uExitVector = (uint8_t)(pSvmTransient->u64ExitCode - SVM_EXIT_EXCEPTION_0);
4091 if (uExitVector == X86_XCPT_PF)
4092 {
4093 pSvmTransient->fVectoringPF = true;
4094 Log4(("IDT: Vectoring #PF due to Ext-Int/NMI. uCR2=%#RX64\n", pCtx->cr2));
4095 }
4096 }
4097 }
4098 /* else: Ignore software interrupts (INT n) as they reoccur when restarting the instruction. */
4099
4100 switch (enmReflect)
4101 {
4102 case SVMREFLECTXCPT_XCPT:
4103 {
4104 /* If we are re-injecting the NMI, clear NMI blocking. */
4105 if (fReflectingNmi)
4106 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
4107
4108 Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
4109 hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, 0 /* GCPtrFaultAddress */);
4110
4111 /* If uExitVector is #PF, CR2 value will be updated from the VMCB if it's a guest #PF. See hmR0SvmExitXcptPF(). */
4112 Log4(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32\n", pVmcb->ctrl.ExitIntInfo.u,
4113 !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid, pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
4114 break;
4115 }
4116
4117 case SVMREFLECTXCPT_DF:
4118 {
4119 hmR0SvmSetPendingXcptDF(pVCpu);
4120 rc = VINF_HM_DOUBLE_FAULT;
4121 break;
4122 }
4123
4124 case SVMREFLECTXCPT_TF:
4125 {
4126 rc = VINF_EM_RESET;
4127 break;
4128 }
4129
4130 default:
4131 Assert(rc == VINF_SUCCESS);
4132 break;
4133 }
4134 }
4135 Assert(rc == VINF_SUCCESS || rc == VINF_HM_DOUBLE_FAULT || rc == VINF_EM_RESET);
4136 NOREF(pCtx);
4137 return rc;
4138}
4139
4140
4141/**
4142 * Advances the guest RIP in the if the NRIP_SAVE feature is supported by the
4143 * CPU, otherwise advances the RIP by @a cb bytes.
4144 *
4145 * @param pVCpu Pointer to the VMCPU.
4146 * @param pCtx Pointer to the guest-CPU context.
4147 * @param cb RIP increment value in bytes.
4148 *
4149 * @remarks Use this function only from #VMEXIT's where the NRIP value is valid
4150 * when NRIP_SAVE is supported by the CPU!
4151 */
4152DECLINLINE(void) hmR0SvmUpdateRip(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t cb)
4153{
4154 if (pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4155 {
4156 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4157 pCtx->rip = pVmcb->ctrl.u64NextRIP;
4158 }
4159 else
4160 pCtx->rip += cb;
4161}
4162
4163
4164/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
4165/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
4166/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
4167
4168/** @name #VMEXIT handlers.
4169 * @{
4170 */
4171
4172/**
4173 * #VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
4174 * signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
4175 */
4176HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4177{
4178 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4179
4180 if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
4181 STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
4182 else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
4183 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
4184
4185 /*
4186 * AMD-V has no preemption timer and the generic periodic preemption timer has no way to signal -before- the timer
4187 * fires if the current interrupt is our own timer or a some other host interrupt. We also cannot examine what
4188 * interrupt it is until the host actually take the interrupt.
4189 *
4190 * Going back to executing guest code here unconditionally causes random scheduling problems (observed on an
4191 * AMD Phenom 9850 Quad-Core on Windows 64-bit host).
4192 */
4193 return VINF_EM_RAW_INTERRUPT;
4194}
4195
4196
4197/**
4198 * #VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional #VMEXIT.
4199 */
4200HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4201{
4202 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4203
4204 hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4205 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWbinvd);
4206 int rc = VINF_SUCCESS;
4207 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4208 return rc;
4209}
4210
4211
4212/**
4213 * #VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional #VMEXIT.
4214 */
4215HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4216{
4217 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4218
4219 hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4220 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvd);
4221 int rc = VINF_SUCCESS;
4222 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4223 return rc;
4224}
4225
4226
4227/**
4228 * #VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional #VMEXIT.
4229 */
4230HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4231{
4232 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4233 PVM pVM = pVCpu->CTX_SUFF(pVM);
4234 int rc = EMInterpretCpuId(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4235 if (RT_LIKELY(rc == VINF_SUCCESS))
4236 {
4237 hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4238 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4239 }
4240 else
4241 {
4242 AssertMsgFailed(("hmR0SvmExitCpuid: EMInterpretCpuId failed with %Rrc\n", rc));
4243 rc = VERR_EM_INTERPRETER;
4244 }
4245 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCpuid);
4246 return rc;
4247}
4248
4249
4250/**
4251 * #VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional #VMEXIT.
4252 */
4253HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4254{
4255 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4256 PVM pVM = pVCpu->CTX_SUFF(pVM);
4257 int rc = EMInterpretRdtsc(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4258 if (RT_LIKELY(rc == VINF_SUCCESS))
4259 {
4260 hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4261 pSvmTransient->fUpdateTscOffsetting = true;
4262
4263 /* Single step check. */
4264 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4265 }
4266 else
4267 {
4268 AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtsc failed with %Rrc\n", rc));
4269 rc = VERR_EM_INTERPRETER;
4270 }
4271 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtsc);
4272 return rc;
4273}
4274
4275
4276/**
4277 * #VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional #VMEXIT.
4278 */
4279HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4280{
4281 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4282 int rc = EMInterpretRdtscp(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4283 if (RT_LIKELY(rc == VINF_SUCCESS))
4284 {
4285 hmR0SvmUpdateRip(pVCpu, pCtx, 3);
4286 pSvmTransient->fUpdateTscOffsetting = true;
4287 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4288 }
4289 else
4290 {
4291 AssertMsgFailed(("hmR0SvmExitRdtsc: EMInterpretRdtscp failed with %Rrc\n", rc));
4292 rc = VERR_EM_INTERPRETER;
4293 }
4294 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdtscp);
4295 return rc;
4296}
4297
4298
4299/**
4300 * #VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional #VMEXIT.
4301 */
4302HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4303{
4304 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4305 int rc = EMInterpretRdpmc(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4306 if (RT_LIKELY(rc == VINF_SUCCESS))
4307 {
4308 hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4309 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4310 }
4311 else
4312 {
4313 AssertMsgFailed(("hmR0SvmExitRdpmc: EMInterpretRdpmc failed with %Rrc\n", rc));
4314 rc = VERR_EM_INTERPRETER;
4315 }
4316 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdpmc);
4317 return rc;
4318}
4319
4320
4321/**
4322 * #VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional #VMEXIT.
4323 */
4324HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4325{
4326 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4327 PVM pVM = pVCpu->CTX_SUFF(pVM);
4328 Assert(!pVM->hm.s.fNestedPaging);
4329
4330 /** @todo Decode Assist. */
4331 int rc = hmR0SvmInterpretInvlpg(pVM, pVCpu, CPUMCTX2CORE(pCtx)); /* Updates RIP if successful. */
4332 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitInvlpg);
4333 Assert(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER);
4334 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4335 return rc;
4336}
4337
4338
4339/**
4340 * #VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional #VMEXIT.
4341 */
4342HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4343{
4344 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4345 hmR0SvmUpdateRip(pVCpu, pCtx, 1);
4346 int rc = EMShouldContinueAfterHalt(pVCpu, pCtx) ? VINF_SUCCESS : VINF_EM_HALT;
4347 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4348 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
4349 if (rc != VINF_SUCCESS)
4350 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHltToR3);
4351 return rc;
4352}
4353
4354
4355/**
4356 * #VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional #VMEXIT.
4357 */
4358HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4359{
4360 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4361 int rc = EMInterpretMonitor(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4362 if (RT_LIKELY(rc == VINF_SUCCESS))
4363 {
4364 hmR0SvmUpdateRip(pVCpu, pCtx, 3);
4365 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4366 }
4367 else
4368 {
4369 AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMonitor: EMInterpretMonitor failed with %Rrc\n", rc));
4370 rc = VERR_EM_INTERPRETER;
4371 }
4372 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
4373 return rc;
4374}
4375
4376
4377/**
4378 * #VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional #VMEXIT.
4379 */
4380HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4381{
4382 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4383 VBOXSTRICTRC rc2 = EMInterpretMWait(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
4384 int rc = VBOXSTRICTRC_VAL(rc2);
4385 if ( rc == VINF_EM_HALT
4386 || rc == VINF_SUCCESS)
4387 {
4388 hmR0SvmUpdateRip(pVCpu, pCtx, 3);
4389
4390 if ( rc == VINF_EM_HALT
4391 && EMMonitorWaitShouldContinue(pVCpu, pCtx))
4392 {
4393 rc = VINF_SUCCESS;
4394 }
4395 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4396 }
4397 else
4398 {
4399 AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMwait: EMInterpretMWait failed with %Rrc\n", rc));
4400 rc = VERR_EM_INTERPRETER;
4401 }
4402 AssertMsg(rc == VINF_SUCCESS || rc == VINF_EM_HALT || rc == VERR_EM_INTERPRETER,
4403 ("hmR0SvmExitMwait: EMInterpretMWait failed rc=%Rrc\n", rc));
4404 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
4405 return rc;
4406}
4407
4408
4409/**
4410 * #VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN).
4411 * Conditional #VMEXIT.
4412 */
4413HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4414{
4415 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4416 return VINF_EM_RESET;
4417}
4418
4419
4420/**
4421 * #VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional #VMEXIT.
4422 */
4423HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4424{
4425 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4426
4427 Log4(("hmR0SvmExitReadCRx: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4428
4429 /** @todo Decode Assist. */
4430 VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4431 int rc = VBOXSTRICTRC_VAL(rc2);
4432 AssertMsg(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3,
4433 ("hmR0SvmExitReadCRx: EMInterpretInstruction failed rc=%Rrc\n", rc));
4434 Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
4435 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCRxRead[pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0]);
4436 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4437 return rc;
4438}
4439
4440
4441/**
4442 * #VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional #VMEXIT.
4443 */
4444HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4445{
4446 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4447 /** @todo Decode Assist. */
4448 VBOXSTRICTRC rc2 = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4449 int rc = VBOXSTRICTRC_VAL(rc2);
4450 if (rc == VINF_SUCCESS)
4451 {
4452 /* RIP has been updated by EMInterpretInstruction(). */
4453 Assert((pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0) <= 15);
4454 switch (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0)
4455 {
4456 case 0: /* CR0. */
4457 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
4458 break;
4459
4460 case 3: /* CR3. */
4461 Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
4462 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR3);
4463 break;
4464
4465 case 4: /* CR4. */
4466 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR4);
4467 break;
4468
4469 case 8: /* CR8 (TPR). */
4470 HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4471 break;
4472
4473 default:
4474 AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x CRx=%#RX64\n",
4475 pSvmTransient->u64ExitCode, pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0));
4476 break;
4477 }
4478 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4479 }
4480 else
4481 Assert(rc == VERR_EM_INTERPRETER || rc == VINF_PGM_CHANGE_MODE || rc == VINF_PGM_SYNC_CR3);
4482 return rc;
4483}
4484
4485
4486/**
4487 * #VMEXIT handler for instructions that result in a #UD exception delivered to
4488 * the guest.
4489 */
4490HMSVM_EXIT_DECL hmR0SvmExitSetPendingXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4491{
4492 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4493 hmR0SvmSetPendingXcptUD(pVCpu);
4494 return VINF_SUCCESS;
4495}
4496
4497
4498/**
4499 * #VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional #VMEXIT.
4500 */
4501HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4502{
4503 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4504 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4505 PVM pVM = pVCpu->CTX_SUFF(pVM);
4506
4507 int rc;
4508 if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
4509 {
4510 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
4511
4512 /* Handle TPR patching; intercepted LSTAR write. */
4513 if ( pVM->hm.s.fTPRPatchingActive
4514 && pCtx->ecx == MSR_K8_LSTAR)
4515 {
4516 if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
4517 {
4518 /* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
4519 int rc2 = PDMApicSetTPR(pVCpu, pCtx->eax & 0xff);
4520 AssertRC(rc2);
4521 HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4522 }
4523 hmR0SvmUpdateRip(pVCpu, pCtx, 2);
4524 rc = VINF_SUCCESS;
4525 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4526 return rc;
4527 }
4528
4529 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4530 {
4531 rc = EMInterpretWrmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4532 if (RT_LIKELY(rc == VINF_SUCCESS))
4533 {
4534 pCtx->rip = pVmcb->ctrl.u64NextRIP;
4535 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4536 }
4537 else
4538 AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretWrmsr failed rc=%Rrc\n", rc));
4539 }
4540 else
4541 {
4542 rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */));
4543 if (RT_LIKELY(rc == VINF_SUCCESS))
4544 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc); /* RIP updated by EMInterpretInstruction(). */
4545 else
4546 AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: WrMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4547 }
4548
4549 if (rc == VINF_SUCCESS)
4550 {
4551 /* If this is an X2APIC WRMSR access, update the APIC state as well. */
4552 if ( pCtx->ecx >= MSR_IA32_X2APIC_START
4553 && pCtx->ecx <= MSR_IA32_X2APIC_END)
4554 {
4555 /*
4556 * We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest(). When full APIC register
4557 * virtualization is implemented we'll have to make sure APIC state is saved from the VMCB before
4558 * EMInterpretWrmsr() changes it.
4559 */
4560 HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4561 }
4562 else if (pCtx->ecx == MSR_K6_EFER)
4563 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_EFER_MSR);
4564 else if (pCtx->ecx == MSR_IA32_TSC)
4565 pSvmTransient->fUpdateTscOffsetting = true;
4566 }
4567 }
4568 else
4569 {
4570 /* MSR Read access. */
4571 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
4572 Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ);
4573
4574 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
4575 {
4576 rc = EMInterpretRdmsr(pVM, pVCpu, CPUMCTX2CORE(pCtx));
4577 if (RT_LIKELY(rc == VINF_SUCCESS))
4578 {
4579 pCtx->rip = pVmcb->ctrl.u64NextRIP;
4580 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4581 }
4582 else
4583 AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: EMInterpretRdmsr failed rc=%Rrc\n", rc));
4584 }
4585 else
4586 {
4587 rc = VBOXSTRICTRC_TODO(EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0));
4588 if (RT_UNLIKELY(rc != VINF_SUCCESS))
4589 AssertMsg(rc == VERR_EM_INTERPRETER, ("hmR0SvmExitMsr: RdMsr. EMInterpretInstruction failed rc=%Rrc\n", rc));
4590 /* RIP updated by EMInterpretInstruction(). */
4591 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4592 }
4593 }
4594
4595 /* RIP has been updated by EMInterpret[Rd|Wr]msr(). */
4596 return rc;
4597}
4598
4599
4600/**
4601 * #VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional #VMEXIT.
4602 */
4603HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4604{
4605 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4606 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
4607
4608 /* We should -not- get this #VMEXIT if the guest's debug registers were active. */
4609 if (pSvmTransient->fWasGuestDebugStateActive)
4610 {
4611 AssertMsgFailed(("hmR0SvmHandleExit: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
4612 pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
4613 return VERR_SVM_UNEXPECTED_EXIT;
4614 }
4615
4616 /*
4617 * Lazy DR0-3 loading.
4618 */
4619 if (!pSvmTransient->fWasHyperDebugStateActive)
4620 {
4621 Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
4622 Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
4623
4624 /* Don't intercept DRx read and writes. */
4625 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4626 pVmcb->ctrl.u16InterceptRdDRx = 0;
4627 pVmcb->ctrl.u16InterceptWrDRx = 0;
4628 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
4629
4630 /* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
4631 VMMRZCallRing3Disable(pVCpu);
4632 HM_DISABLE_PREEMPT_IF_NEEDED();
4633
4634 /* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
4635 CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
4636 Assert(CPUMIsGuestDebugStateActive(pVCpu) || HC_ARCH_BITS == 32);
4637
4638 HM_RESTORE_PREEMPT_IF_NEEDED();
4639 VMMRZCallRing3Enable(pVCpu);
4640
4641 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
4642 return VINF_SUCCESS;
4643 }
4644
4645 /*
4646 * Interpret the read/writing of DRx.
4647 */
4648 /** @todo Decode assist. */
4649 VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
4650 Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
4651 if (RT_LIKELY(rc == VINF_SUCCESS))
4652 {
4653 /* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
4654 /** @todo CPUM should set this flag! */
4655 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_DEBUG);
4656 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
4657 }
4658 else
4659 Assert(rc == VERR_EM_INTERPRETER);
4660 return VBOXSTRICTRC_TODO(rc);
4661}
4662
4663
4664/**
4665 * #VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional #VMEXIT.
4666 */
4667HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4668{
4669 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4670 /* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
4671 int rc = hmR0SvmExitReadDRx(pVCpu, pCtx, pSvmTransient);
4672 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
4673 STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
4674 return rc;
4675}
4676
4677
4678/**
4679 * #VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional #VMEXIT.
4680 */
4681HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4682{
4683 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4684
4685 /* I/O operation lookup arrays. */
4686 static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
4687 static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
4688 the result (in AL/AX/EAX). */
4689 Log4(("hmR0SvmExitIOInstr: CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
4690
4691 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4692 PVM pVM = pVCpu->CTX_SUFF(pVM);
4693
4694 /* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
4695 SVMIOIOEXIT IoExitInfo;
4696 IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
4697 uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
4698 uint32_t cbValue = s_aIOSize[uIOWidth];
4699 uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
4700
4701 if (RT_UNLIKELY(!cbValue))
4702 {
4703 AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
4704 return VERR_EM_INTERPRETER;
4705 }
4706
4707 VBOXSTRICTRC rcStrict;
4708 if (IoExitInfo.n.u1STR)
4709 {
4710 /* INS/OUTS - I/O String instruction. */
4711 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
4712
4713 /** @todo Huh? why can't we use the segment prefix information given by AMD-V
4714 * in EXITINFO1? Investigate once this thing is up and running. */
4715
4716 rcStrict = EMInterpretDisasCurrent(pVM, pVCpu, pDis, NULL);
4717 if (rcStrict == VINF_SUCCESS)
4718 {
4719 if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4720 {
4721 rcStrict = IOMInterpretOUTSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4722 (DISCPUMODE)pDis->uAddrMode, cbValue);
4723 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
4724 }
4725 else
4726 {
4727 rcStrict = IOMInterpretINSEx(pVM, pVCpu, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, pDis->fPrefix,
4728 (DISCPUMODE)pDis->uAddrMode, cbValue);
4729 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
4730 }
4731 }
4732 else
4733 rcStrict = VINF_EM_RAW_EMULATE_INSTR;
4734 }
4735 else
4736 {
4737 /* IN/OUT - I/O instruction. */
4738 Assert(!IoExitInfo.n.u1REP);
4739
4740 if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
4741 {
4742 rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
4743 if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
4744 HMR0SavePendingIOPortWrite(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
4745
4746 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
4747 }
4748 else
4749 {
4750 uint32_t u32Val = 0;
4751
4752 rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
4753 if (IOM_SUCCESS(rcStrict))
4754 {
4755 /* Save result of I/O IN instr. in AL/AX/EAX. */
4756 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
4757 }
4758 else if (rcStrict == VINF_IOM_R3_IOPORT_READ)
4759 HMR0SavePendingIOPortRead(pVCpu, pCtx->rip, pVmcb->ctrl.u64ExitInfo2, IoExitInfo.n.u16Port, uAndVal, cbValue);
4760
4761 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
4762 }
4763 }
4764
4765 if (IOM_SUCCESS(rcStrict))
4766 {
4767 /* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
4768 pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
4769
4770 /*
4771 * If any I/O breakpoints are armed, we need to check if one triggered
4772 * and take appropriate action.
4773 * Note that the I/O breakpoint type is undefined if CR4.DE is 0.
4774 */
4775 /** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
4776 * execution engines about whether hyper BPs and such are pending. */
4777 uint32_t const uDr7 = pCtx->dr[7];
4778 if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
4779 && X86_DR7_ANY_RW_IO(uDr7)
4780 && (pCtx->cr4 & X86_CR4_DE))
4781 || DBGFBpIsHwIoArmed(pVM)))
4782 {
4783 /* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
4784 VMMRZCallRing3Disable(pVCpu);
4785 HM_DISABLE_PREEMPT_IF_NEEDED();
4786
4787 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
4788 CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /*fDr6*/);
4789
4790 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, IoExitInfo.n.u16Port, cbValue);
4791 if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
4792 {
4793 /* Raise #DB. */
4794 pVmcb->guest.u64DR6 = pCtx->dr[6];
4795 pVmcb->guest.u64DR7 = pCtx->dr[7];
4796 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
4797 hmR0SvmSetPendingXcptDB(pVCpu);
4798 }
4799 /* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
4800 else if ( rcStrict2 != VINF_SUCCESS
4801 && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
4802 rcStrict = rcStrict2;
4803
4804 HM_RESTORE_PREEMPT_IF_NEEDED();
4805 VMMRZCallRing3Enable(pVCpu);
4806 }
4807
4808 HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
4809 }
4810
4811#ifdef VBOX_STRICT
4812 if (rcStrict == VINF_IOM_R3_IOPORT_READ)
4813 Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
4814 else if (rcStrict == VINF_IOM_R3_IOPORT_WRITE)
4815 Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
4816 else
4817 {
4818 /** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
4819 * statuses, that the VMM device and some others may return. See
4820 * IOM_SUCCESS() for guidance. */
4821 AssertMsg( RT_FAILURE(rcStrict)
4822 || rcStrict == VINF_SUCCESS
4823 || rcStrict == VINF_EM_RAW_EMULATE_INSTR
4824 || rcStrict == VINF_EM_DBG_BREAKPOINT
4825 || rcStrict == VINF_EM_RAW_GUEST_TRAP
4826 || rcStrict == VINF_TRPM_XCPT_DISPATCHED, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
4827 }
4828#endif
4829 return VBOXSTRICTRC_TODO(rcStrict);
4830}
4831
4832
4833/**
4834 * #VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional
4835 * #VMEXIT.
4836 */
4837HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4838{
4839 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4840 PVM pVM = pVCpu->CTX_SUFF(pVM);
4841 Assert(pVM->hm.s.fNestedPaging);
4842
4843 HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
4844
4845 /* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
4846 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4847 uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
4848 RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
4849
4850 Log4(("#NPF at CS:RIP=%04x:%#RX64 faultaddr=%RGp errcode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr, u32ErrCode));
4851
4852#ifdef VBOX_HM_WITH_GUEST_PATCHING
4853 /* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions. */
4854 if ( pVM->hm.s.fTprPatchingAllowed
4855 && (GCPhysFaultAddr & PAGE_OFFSET_MASK) == 0x80 /* TPR offset. */
4856 && ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
4857 || (u32ErrCode & (X86_TRAP_PF_P | X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P | X86_TRAP_PF_RSVD)) /* MMIO page. */
4858 && !CPUMIsGuestInLongModeEx(pCtx)
4859 && !CPUMGetGuestCPL(pVCpu)
4860 && pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
4861 {
4862 RTGCPHYS GCPhysApicBase = pCtx->msrApicBase;
4863 GCPhysApicBase &= PAGE_BASE_GC_MASK;
4864
4865 if (GCPhysFaultAddr == GCPhysApicBase + 0x80)
4866 {
4867 /* Only attempt to patch the instruction once. */
4868 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
4869 if (!pPatch)
4870 return VINF_EM_HM_PATCH_TPR_INSTR;
4871 }
4872 }
4873#endif
4874
4875 /*
4876 * Determine the nested paging mode.
4877 */
4878 PGMMODE enmNestedPagingMode;
4879#if HC_ARCH_BITS == 32
4880 if (CPUMIsGuestInLongModeEx(pCtx))
4881 enmNestedPagingMode = PGMMODE_AMD64_NX;
4882 else
4883#endif
4884 enmNestedPagingMode = PGMGetHostMode(pVM);
4885
4886 /*
4887 * MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
4888 */
4889 int rc;
4890 Assert((u32ErrCode & (X86_TRAP_PF_RSVD | X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
4891 if ((u32ErrCode & (X86_TRAP_PF_RSVD | X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD | X86_TRAP_PF_P))
4892 {
4893 VBOXSTRICTRC rc2 = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
4894 u32ErrCode);
4895 rc = VBOXSTRICTRC_VAL(rc2);
4896
4897 /*
4898 * If we succeed, resume guest execution.
4899 * If we fail in interpreting the instruction because we couldn't get the guest physical address
4900 * of the page containing the instruction via the guest's page tables (we would invalidate the guest page
4901 * in the host TLB), resume execution which would cause a guest page fault to let the guest handle this
4902 * weird case. See @bugref{6043}.
4903 */
4904 if ( rc == VINF_SUCCESS
4905 || rc == VERR_PAGE_TABLE_NOT_PRESENT
4906 || rc == VERR_PAGE_NOT_PRESENT)
4907 {
4908 /* Successfully handled MMIO operation. */
4909 HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
4910 rc = VINF_SUCCESS;
4911 }
4912 return rc;
4913 }
4914
4915 TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
4916 rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
4917 TRPMResetTrap(pVCpu);
4918
4919 Log4(("#NPF: PGMR0Trap0eHandlerNestedPaging returned %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
4920
4921 /*
4922 * Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
4923 */
4924 if ( rc == VINF_SUCCESS
4925 || rc == VERR_PAGE_TABLE_NOT_PRESENT
4926 || rc == VERR_PAGE_NOT_PRESENT)
4927 {
4928 /* We've successfully synced our shadow page tables. */
4929 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
4930 rc = VINF_SUCCESS;
4931 }
4932
4933 return rc;
4934}
4935
4936
4937/**
4938 * #VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional #VMEXIT.
4939 */
4940HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4941{
4942 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4943
4944 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4945 pVmcb->ctrl.IntCtrl.n.u1VIrqValid = 0; /* No virtual interrupts pending, we'll inject the current one/NMI before reentry. */
4946 pVmcb->ctrl.IntCtrl.n.u8VIrqVector = 0;
4947
4948 /* Indicate that we no longer need to #VMEXIT when the guest is ready to receive interrupts/NMIs, it is now ready. */
4949 pVmcb->ctrl.u32InterceptCtrl1 &= ~SVM_CTRL1_INTERCEPT_VINTR;
4950 pVmcb->ctrl.u64VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS | HMSVM_VMCB_CLEAN_TPR);
4951
4952 /* Deliver the pending interrupt/NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
4953 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
4954 return VINF_SUCCESS;
4955}
4956
4957
4958/**
4959 * #VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional #VMEXIT.
4960 */
4961HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4962{
4963 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4964
4965#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
4966 Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
4967#endif
4968
4969 /* Check if this task-switch occurred while delivery an event through the guest IDT. */
4970 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
4971 if ( !(pVmcb->ctrl.u64ExitInfo2 & (SVM_EXIT2_TASK_SWITCH_IRET | SVM_EXIT2_TASK_SWITCH_JMP))
4972 && pVCpu->hm.s.Event.fPending) /** @todo fPending cannot be 'true', see hmR0SvmInjectPendingEvent(). See @bugref{7362}.*/
4973 {
4974 /*
4975 * AMD-V does not provide us with the original exception but we have it in u64IntInfo since we
4976 * injected the event during VM-entry.
4977 */
4978 Log4(("hmR0SvmExitTaskSwitch: TS occurred during event delivery.\n"));
4979 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
4980 return VINF_EM_RAW_INJECT_TRPM_EVENT;
4981 }
4982
4983 /** @todo Emulate task switch someday, currently just going back to ring-3 for
4984 * emulation. */
4985 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
4986 return VERR_EM_INTERPRETER;
4987}
4988
4989
4990/**
4991 * #VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional #VMEXIT.
4992 */
4993HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
4994{
4995 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
4996
4997 /* First check if this is a patched VMMCALL for mov TPR */
4998 int rc = hmR0SvmEmulateMovTpr(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
4999 if (rc == VINF_SUCCESS)
5000 HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
5001 else if (rc == VERR_NOT_FOUND)
5002 {
5003 /* Handle GIM provider hypercalls. */
5004 rc = VERR_NOT_SUPPORTED;
5005 if (GIMAreHypercallsEnabled(pVCpu))
5006 rc = GIMHypercall(pVCpu, pCtx);
5007 }
5008
5009 if (rc != VINF_SUCCESS)
5010 hmR0SvmSetPendingXcptUD(pVCpu);
5011 return VINF_SUCCESS;
5012}
5013
5014
5015/**
5016 * #VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional #VMEXIT.
5017 */
5018HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5019{
5020 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5021
5022 /* Clear NMI blocking. */
5023 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5024
5025 /* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
5026 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5027 hmR0SvmClearIretIntercept(pVmcb);
5028
5029 /* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
5030 return VINF_SUCCESS;
5031}
5032
5033
5034/**
5035 * #VMEXIT handler for page-fault exceptions (SVM_EXIT_EXCEPTION_E). Conditional
5036 * #VMEXIT.
5037 */
5038HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5039{
5040 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5041
5042 HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5043
5044 /* See AMD spec. 15.12.15 "#PF (Page Fault)". */
5045 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5046 uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1;
5047 RTGCUINTPTR uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
5048 PVM pVM = pVCpu->CTX_SUFF(pVM);
5049
5050#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) || defined(HMSVM_ALWAYS_TRAP_PF)
5051 if (pVM->hm.s.fNestedPaging)
5052 {
5053 pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
5054 if (!pSvmTransient->fVectoringDoublePF)
5055 {
5056 /* A genuine guest #PF, reflect it to the guest. */
5057 hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
5058 Log4(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RGv ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
5059 uFaultAddress, u32ErrCode));
5060 }
5061 else
5062 {
5063 /* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
5064 hmR0SvmSetPendingXcptDF(pVCpu);
5065 Log4(("Pending #DF due to vectoring #PF. NP\n"));
5066 }
5067 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
5068 return VINF_SUCCESS;
5069 }
5070#endif
5071
5072 Assert(!pVM->hm.s.fNestedPaging);
5073
5074#ifdef VBOX_HM_WITH_GUEST_PATCHING
5075 /* Shortcut for APIC TPR reads and writes; only applicable to 32-bit guests. */
5076 if ( pVM->hm.s.fTprPatchingAllowed
5077 && (uFaultAddress & 0xfff) == 0x80 /* TPR offset. */
5078 && !(u32ErrCode & X86_TRAP_PF_P) /* Not present. */
5079 && !CPUMIsGuestInLongModeEx(pCtx)
5080 && !CPUMGetGuestCPL(pVCpu)
5081 && pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
5082 {
5083 RTGCPHYS GCPhysApicBase;
5084 GCPhysApicBase = pCtx->msrApicBase;
5085 GCPhysApicBase &= PAGE_BASE_GC_MASK;
5086
5087 /* Check if the page at the fault-address is the APIC base. */
5088 RTGCPHYS GCPhysPage;
5089 int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
5090 if ( rc2 == VINF_SUCCESS
5091 && GCPhysPage == GCPhysApicBase)
5092 {
5093 /* Only attempt to patch the instruction once. */
5094 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
5095 if (!pPatch)
5096 return VINF_EM_HM_PATCH_TPR_INSTR;
5097 }
5098 }
5099#endif
5100
5101 Log4(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 u32ErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
5102 pCtx->rip, u32ErrCode, pCtx->cr3));
5103
5104 /* If it's a vectoring #PF, emulate injecting the original event injection as PGMTrap0eHandler() is incapable
5105 of differentiating between instruction emulation and event injection that caused a #PF. See @bugref{6607}. */
5106 if (pSvmTransient->fVectoringPF)
5107 {
5108 Assert(pVCpu->hm.s.Event.fPending);
5109 return VINF_EM_RAW_INJECT_TRPM_EVENT;
5110 }
5111
5112 TRPMAssertXcptPF(pVCpu, uFaultAddress, u32ErrCode);
5113 int rc = PGMTrap0eHandler(pVCpu, u32ErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
5114
5115 Log4(("#PF rc=%Rrc\n", rc));
5116
5117 if (rc == VINF_SUCCESS)
5118 {
5119 /* Successfully synced shadow pages tables or emulated an MMIO instruction. */
5120 TRPMResetTrap(pVCpu);
5121 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
5122 HMCPU_CF_SET(pVCpu, HM_CHANGED_SVM_GUEST_APIC_STATE);
5123 return rc;
5124 }
5125 else if (rc == VINF_EM_RAW_GUEST_TRAP)
5126 {
5127 pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
5128
5129 if (!pSvmTransient->fVectoringDoublePF)
5130 {
5131 /* It's a guest page fault and needs to be reflected to the guest. */
5132 u32ErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
5133 TRPMResetTrap(pVCpu);
5134 hmR0SvmSetPendingXcptPF(pVCpu, pCtx, u32ErrCode, uFaultAddress);
5135 }
5136 else
5137 {
5138 /* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
5139 TRPMResetTrap(pVCpu);
5140 hmR0SvmSetPendingXcptDF(pVCpu);
5141 Log4(("#PF: Pending #DF due to vectoring #PF\n"));
5142 }
5143
5144 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
5145 return VINF_SUCCESS;
5146 }
5147
5148 TRPMResetTrap(pVCpu);
5149 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
5150 return rc;
5151}
5152
5153
5154/**
5155 * #VMEXIT handler for device-not-available exceptions (SVM_EXIT_EXCEPTION_7).
5156 * Conditional #VMEXIT.
5157 */
5158HMSVM_EXIT_DECL hmR0SvmExitXcptNM(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5159{
5160 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5161
5162 HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5163
5164 /* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
5165 VMMRZCallRing3Disable(pVCpu);
5166 HM_DISABLE_PREEMPT_IF_NEEDED();
5167
5168 int rc;
5169 /* If the guest FPU was active at the time of the #NM exit, then it's a guest fault. */
5170 if (pSvmTransient->fWasGuestFPUStateActive)
5171 {
5172 rc = VINF_EM_RAW_GUEST_TRAP;
5173 Assert(CPUMIsGuestFPUStateActive(pVCpu) || HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_CR0));
5174 }
5175 else
5176 {
5177#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5178 Assert(!pSvmTransient->fWasGuestFPUStateActive);
5179#endif
5180 rc = CPUMR0Trap07Handler(pVCpu->CTX_SUFF(pVM), pVCpu, pCtx);
5181 Assert(rc == VINF_EM_RAW_GUEST_TRAP || (rc == VINF_SUCCESS && CPUMIsGuestFPUStateActive(pVCpu)));
5182 }
5183
5184 HM_RESTORE_PREEMPT_IF_NEEDED();
5185 VMMRZCallRing3Enable(pVCpu);
5186
5187 if (rc == VINF_SUCCESS)
5188 {
5189 /* Guest FPU state was activated, we'll want to change CR0 FPU intercepts before the next VM-reentry. */
5190 HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
5191 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowNM);
5192 pVCpu->hm.s.fUseGuestFpu = true;
5193 }
5194 else
5195 {
5196 /* Forward #NM to the guest. */
5197 Assert(rc == VINF_EM_RAW_GUEST_TRAP);
5198 hmR0SvmSetPendingXcptNM(pVCpu);
5199 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestNM);
5200 }
5201 return VINF_SUCCESS;
5202}
5203
5204
5205/**
5206 * #VMEXIT handler for math-fault exceptions (SVM_EXIT_EXCEPTION_10).
5207 * Conditional #VMEXIT.
5208 */
5209HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5210{
5211 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5212
5213 HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5214
5215 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
5216
5217 if (!(pCtx->cr0 & X86_CR0_NE))
5218 {
5219 PVM pVM = pVCpu->CTX_SUFF(pVM);
5220 PDISSTATE pDis = &pVCpu->hm.s.DisState;
5221 unsigned cbOp;
5222 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
5223 if (RT_SUCCESS(rc))
5224 {
5225 /* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
5226 rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13, 1, 0 /* uTagSrc */);
5227 if (RT_SUCCESS(rc))
5228 pCtx->rip += cbOp;
5229 }
5230 else
5231 Log4(("hmR0SvmExitXcptMF: EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
5232 return rc;
5233 }
5234
5235 hmR0SvmSetPendingXcptMF(pVCpu);
5236 return VINF_SUCCESS;
5237}
5238
5239
5240/**
5241 * #VMEXIT handler for debug exceptions (SVM_EXIT_EXCEPTION_1). Conditional
5242 * #VMEXIT.
5243 */
5244HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PCPUMCTX pCtx, PSVMTRANSIENT pSvmTransient)
5245{
5246 HMSVM_VALIDATE_EXIT_HANDLER_PARAMS();
5247
5248 HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY();
5249
5250 STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
5251
5252 /* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data breakpoint). However, for both cases
5253 DR6 and DR7 are updated to what the exception handler expects. See AMD spec. 15.12.2 "#DB (Debug)". */
5254 PSVMVMCB pVmcb = (PSVMVMCB)pVCpu->hm.s.svm.pvVmcb;
5255 PVM pVM = pVCpu->CTX_SUFF(pVM);
5256 int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
5257 if (rc == VINF_EM_RAW_GUEST_TRAP)
5258 {
5259 Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
5260 if (CPUMIsHyperDebugStateActive(pVCpu))
5261 CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) | pVmcb->guest.u64DR6);
5262
5263 /* Reflect the exception back to the guest. */
5264 hmR0SvmSetPendingXcptDB(pVCpu);
5265 rc = VINF_SUCCESS;
5266 }
5267
5268 /*
5269 * Update DR6.
5270 */
5271 if (CPUMIsHyperDebugStateActive(pVCpu))
5272 {
5273 Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
5274 pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
5275 pVmcb->ctrl.u64VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
5276 }
5277 else
5278 {
5279 AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
5280 Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
5281 }
5282
5283 return rc;
5284}
5285
5286/** @} */
5287
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