HMSVMR0.cpp@ 73299

Last change on this file since 73299 was 73293, checked in by vboxsync, 6 years ago
VMM, SUPDrv: Nested VMX: bugref:9180 Read VMX true control MSRs, dump them. Remove pVM->hm.cpuid as we for a long time now have cpum.ro.HostFeatures available. Related cleanups and simplifications.
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File size: 319.3 KB

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1	/* $Id: HMSVMR0.cpp 73293 2018-07-21 15:11:53Z vboxsync $ */
2	/** @file
3	* HM SVM (AMD-V) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2013-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <iprt/asm-amd64-x86.h>
25	#include <iprt/thread.h>
26
27	#include <VBox/vmm/pdmapi.h>
28	#include <VBox/vmm/dbgf.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/tm.h>
32	#include <VBox/vmm/gim.h>
33	#include <VBox/vmm/apic.h>
34	#include "HMInternal.h"
35	#include <VBox/vmm/vm.h>
36	#include "HMSVMR0.h"
37	#include "dtrace/VBoxVMM.h"
38
39	#ifdef DEBUG_ramshankar
40	# define HMSVM_SYNC_FULL_GUEST_STATE
41	# define HMSVM_ALWAYS_TRAP_ALL_XCPTS
42	# define HMSVM_ALWAYS_TRAP_PF
43	# define HMSVM_ALWAYS_TRAP_TASK_SWITCH
44	#endif
45
46
47	/*********************************************************************************************************************************
48	* Defined Constants And Macros *
49	*********************************************************************************************************************************/
50	#ifdef VBOX_WITH_STATISTICS
51	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
52	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
53	if ((u64ExitCode) == SVM_EXIT_NPF) \
54	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitReasonNpf); \
55	else \
56	STAM_COUNTER_INC(&pVCpu->hm.s.paStatExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
57	} while (0)
58
59	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
60	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { \
61	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitAll); \
62	if ((u64ExitCode) == SVM_EXIT_NPF) \
63	STAM_COUNTER_INC(&pVCpu->hm.s.StatNestedExitReasonNpf); \
64	else \
65	STAM_COUNTER_INC(&pVCpu->hm.s.paStatNestedExitReasonR0[(u64ExitCode) & MASK_EXITREASON_STAT]); \
66	} while (0)
67	# endif
68	#else
69	# define HMSVM_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
70	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
71	# define HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(u64ExitCode) do { } while (0)
72	# endif
73	#endif /* !VBOX_WITH_STATISTICS */
74
75	/** If we decide to use a function table approach this can be useful to
76	* switch to a "static DECLCALLBACK(int)". */
77	#define HMSVM_EXIT_DECL static int
78
79	/**
80	* Subset of the guest-CPU state that is kept by SVM R0 code while executing the
81	* guest using hardware-assisted SVM.
82	*
83	* This excludes state like TSC AUX, GPRs (other than RSP, RAX) which are always
84	* are swapped and restored across the world-switch and also registers like
85	* EFER, PAT MSR etc. which cannot be modified by the guest without causing a
86	* \#VMEXIT.
87	*/
88	#define HMSVM_CPUMCTX_EXTRN_ALL ( CPUMCTX_EXTRN_RIP \
89	\| CPUMCTX_EXTRN_RFLAGS \
90	\| CPUMCTX_EXTRN_RAX \
91	\| CPUMCTX_EXTRN_RSP \
92	\| CPUMCTX_EXTRN_SREG_MASK \
93	\| CPUMCTX_EXTRN_CR0 \
94	\| CPUMCTX_EXTRN_CR2 \
95	\| CPUMCTX_EXTRN_CR3 \
96	\| CPUMCTX_EXTRN_TABLE_MASK \
97	\| CPUMCTX_EXTRN_DR6 \
98	\| CPUMCTX_EXTRN_DR7 \
99	\| CPUMCTX_EXTRN_KERNEL_GS_BASE \
100	\| CPUMCTX_EXTRN_SYSCALL_MSRS \
101	\| CPUMCTX_EXTRN_SYSENTER_MSRS \
102	\| CPUMCTX_EXTRN_HWVIRT \
103	\| CPUMCTX_EXTRN_HM_SVM_MASK)
104
105	/**
106	* Subset of the guest-CPU state that is shared between the guest and host.
107	*/
108	#define HMSVM_CPUMCTX_SHARED_STATE CPUMCTX_EXTRN_DR_MASK
109
110	/** Macro for importing guest state from the VMCB back into CPUMCTX. */
111	#define HMSVM_CPUMCTX_IMPORT_STATE(a_pVCpu, a_fWhat) \
112	do { \
113	if ((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fWhat)) \
114	hmR0SvmImportGuestState((a_pVCpu), (a_fWhat)); \
115	} while (0)
116
117	/** Assert that the required state bits are fetched. */
118	#define HMSVM_CPUMCTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
119	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", \
120	(a_pVCpu)->cpum.GstCtx.fExtrn, (a_fExtrnMbz)))
121
122	/** Assert that preemption is disabled or covered by thread-context hooks. */
123	#define HMSVM_ASSERT_PREEMPT_SAFE(a_pVCpu) Assert( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
124	\|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
125
126	/** Assert that we haven't migrated CPUs when thread-context hooks are not
127	* used. */
128	#define HMSVM_ASSERT_CPU_SAFE(a_pVCpu) AssertMsg( VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
129	\|\| (a_pVCpu)->hm.s.idEnteredCpu == RTMpCpuId(), \
130	("Illegal migration! Entered on CPU %u Current %u\n", \
131	(a_pVCpu)->hm.s.idEnteredCpu, RTMpCpuId()));
132
133	/** Assert that we're not executing a nested-guest. */
134	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
135	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) Assert(!CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
136	#else
137	# define HMSVM_ASSERT_NOT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
138	#endif
139
140	/** Assert that we're executing a nested-guest. */
141	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
142	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) Assert(CPUMIsGuestInSvmNestedHwVirtMode((a_pCtx)))
143	#else
144	# define HMSVM_ASSERT_IN_NESTED_GUEST(a_pCtx) do { NOREF((a_pCtx)); } while (0)
145	#endif
146
147	/** Macro for checking and returning from the using function for
148	* \#VMEXIT intercepts that maybe caused during delivering of another
149	* event in the guest. */
150	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
151	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(a_pVCpu, a_pSvmTransient) \
152	do \
153	{ \
154	int rc = hmR0SvmCheckExitDueToEventDelivery((a_pVCpu), (a_pSvmTransient)); \
155	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
156	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
157	else if ( rc == VINF_EM_RESET \
158	&& CPUMIsGuestSvmCtrlInterceptSet((a_pVCpu), &(a_pVCpu)->cpum.GstCtx, SVM_CTRL_INTERCEPT_SHUTDOWN)) \
159	{ \
160	HMSVM_CPUMCTX_IMPORT_STATE((a_pVCpu), HMSVM_CPUMCTX_EXTRN_ALL); \
161	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit((a_pVCpu), SVM_EXIT_SHUTDOWN, 0, 0)); \
162	} \
163	else \
164	return rc; \
165	} while (0)
166	#else
167	# define HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(a_pVCpu, a_pSvmTransient) \
168	do \
169	{ \
170	int rc = hmR0SvmCheckExitDueToEventDelivery((a_pVCpu), (a_pSvmTransient)); \
171	if (RT_LIKELY(rc == VINF_SUCCESS)) { /* continue #VMEXIT handling */ } \
172	else if ( rc == VINF_HM_DOUBLE_FAULT) { return VINF_SUCCESS; } \
173	else \
174	return rc; \
175	} while (0)
176	#endif
177
178	/** Macro for upgrading a @a a_rc to VINF_EM_DBG_STEPPED after emulating an
179	* instruction that exited. */
180	#define HMSVM_CHECK_SINGLE_STEP(a_pVCpu, a_rc) \
181	do { \
182	if ((a_pVCpu)->hm.s.fSingleInstruction && (a_rc) == VINF_SUCCESS) \
183	(a_rc) = VINF_EM_DBG_STEPPED; \
184	} while (0)
185
186	/** Validate segment descriptor granularity bit. */
187	#ifdef VBOX_STRICT
188	# define HMSVM_ASSERT_SEG_GRANULARITY(a_pCtx, reg) \
189	AssertMsg( !(a_pCtx)->reg.Attr.n.u1Present \
190	\|\| ( (a_pCtx)->reg.Attr.n.u1Granularity \
191	? ((a_pCtx)->reg.u32Limit & 0xfff) == 0xfff \
192	: (a_pCtx)->reg.u32Limit <= UINT32_C(0xfffff)), \
193	("Invalid Segment Attributes Limit=%#RX32 Attr=%#RX32 Base=%#RX64\n", (a_pCtx)->reg.u32Limit, \
194	(a_pCtx)->reg.Attr.u, (a_pCtx)->reg.u64Base))
195	#else
196	# define HMSVM_ASSERT_SEG_GRANULARITY(a_pCtx, reg) do { } while (0)
197	#endif
198
199	/**
200	* Exception bitmap mask for all contributory exceptions.
201	*
202	* Page fault is deliberately excluded here as it's conditional as to whether
203	* it's contributory or benign. Page faults are handled separately.
204	*/
205	#define HMSVM_CONTRIBUTORY_XCPT_MASK ( RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_TS) \
206	\| RT_BIT(X86_XCPT_DE))
207
208	/**
209	* Mandatory/unconditional guest control intercepts.
210	*
211	* SMIs can and do happen in normal operation. We need not intercept them
212	* while executing the guest (or nested-guest).
213	*/
214	#define HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS ( SVM_CTRL_INTERCEPT_INTR \
215	\| SVM_CTRL_INTERCEPT_NMI \
216	\| SVM_CTRL_INTERCEPT_INIT \
217	\| SVM_CTRL_INTERCEPT_RDPMC \
218	\| SVM_CTRL_INTERCEPT_CPUID \
219	\| SVM_CTRL_INTERCEPT_RSM \
220	\| SVM_CTRL_INTERCEPT_HLT \
221	\| SVM_CTRL_INTERCEPT_IOIO_PROT \
222	\| SVM_CTRL_INTERCEPT_MSR_PROT \
223	\| SVM_CTRL_INTERCEPT_INVLPGA \
224	\| SVM_CTRL_INTERCEPT_SHUTDOWN \
225	\| SVM_CTRL_INTERCEPT_FERR_FREEZE \
226	\| SVM_CTRL_INTERCEPT_VMRUN \
227	\| SVM_CTRL_INTERCEPT_SKINIT \
228	\| SVM_CTRL_INTERCEPT_WBINVD \
229	\| SVM_CTRL_INTERCEPT_MONITOR \
230	\| SVM_CTRL_INTERCEPT_MWAIT \
231	\| SVM_CTRL_INTERCEPT_CR0_SEL_WRITE \
232	\| SVM_CTRL_INTERCEPT_XSETBV)
233
234	/** @name VMCB Clean Bits.
235	*
236	* These flags are used for VMCB-state caching. A set VMCB Clean bit indicates
237	* AMD-V doesn't need to reload the corresponding value(s) from the VMCB in
238	* memory.
239	*
240	* @{ */
241	/** All intercepts vectors, TSC offset, PAUSE filter counter. */
242	#define HMSVM_VMCB_CLEAN_INTERCEPTS RT_BIT(0)
243	/** I/O permission bitmap, MSR permission bitmap. */
244	#define HMSVM_VMCB_CLEAN_IOPM_MSRPM RT_BIT(1)
245	/** ASID. */
246	#define HMSVM_VMCB_CLEAN_ASID RT_BIT(2)
247	/** TRP: V_TPR, V_IRQ, V_INTR_PRIO, V_IGN_TPR, V_INTR_MASKING,
248	V_INTR_VECTOR. */
249	#define HMSVM_VMCB_CLEAN_INT_CTRL RT_BIT(3)
250	/** Nested Paging: Nested CR3 (nCR3), PAT. */
251	#define HMSVM_VMCB_CLEAN_NP RT_BIT(4)
252	/** Control registers (CR0, CR3, CR4, EFER). */
253	#define HMSVM_VMCB_CLEAN_CRX_EFER RT_BIT(5)
254	/** Debug registers (DR6, DR7). */
255	#define HMSVM_VMCB_CLEAN_DRX RT_BIT(6)
256	/** GDT, IDT limit and base. */
257	#define HMSVM_VMCB_CLEAN_DT RT_BIT(7)
258	/** Segment register: CS, SS, DS, ES limit and base. */
259	#define HMSVM_VMCB_CLEAN_SEG RT_BIT(8)
260	/** CR2.*/
261	#define HMSVM_VMCB_CLEAN_CR2 RT_BIT(9)
262	/** Last-branch record (DbgCtlMsr, br_from, br_to, lastint_from, lastint_to) */
263	#define HMSVM_VMCB_CLEAN_LBR RT_BIT(10)
264	/** AVIC (AVIC APIC_BAR; AVIC APIC_BACKING_PAGE, AVIC
265	PHYSICAL_TABLE and AVIC LOGICAL_TABLE Pointers). */
266	#define HMSVM_VMCB_CLEAN_AVIC RT_BIT(11)
267	/** Mask of all valid VMCB Clean bits. */
268	#define HMSVM_VMCB_CLEAN_ALL ( HMSVM_VMCB_CLEAN_INTERCEPTS \
269	\| HMSVM_VMCB_CLEAN_IOPM_MSRPM \
270	\| HMSVM_VMCB_CLEAN_ASID \
271	\| HMSVM_VMCB_CLEAN_INT_CTRL \
272	\| HMSVM_VMCB_CLEAN_NP \
273	\| HMSVM_VMCB_CLEAN_CRX_EFER \
274	\| HMSVM_VMCB_CLEAN_DRX \
275	\| HMSVM_VMCB_CLEAN_DT \
276	\| HMSVM_VMCB_CLEAN_SEG \
277	\| HMSVM_VMCB_CLEAN_CR2 \
278	\| HMSVM_VMCB_CLEAN_LBR \
279	\| HMSVM_VMCB_CLEAN_AVIC)
280	/** @} */
281
282	/** @name SVM transient.
283	*
284	* A state structure for holding miscellaneous information across AMD-V
285	* VMRUN/\#VMEXIT operation, restored after the transition.
286	*
287	* @{ */
288	typedef struct SVMTRANSIENT
289	{
290	/** The host's rflags/eflags. */
291	RTCCUINTREG fEFlags;
292	#if HC_ARCH_BITS == 32
293	uint32_t u32Alignment0;
294	#endif
295
296	/** The \#VMEXIT exit code (the EXITCODE field in the VMCB). */
297	uint64_t u64ExitCode;
298	/** The guest's TPR value used for TPR shadowing. */
299	uint8_t u8GuestTpr;
300	/** Alignment. */
301	uint8_t abAlignment0[7];
302
303	/** Pointer to the currently executing VMCB. */
304	PSVMVMCB pVmcb;
305	/** Whether we are currently executing a nested-guest. */
306	bool fIsNestedGuest;
307
308	/** Whether the guest debug state was active at the time of \#VMEXIT. */
309	bool fWasGuestDebugStateActive;
310	/** Whether the hyper debug state was active at the time of \#VMEXIT. */
311	bool fWasHyperDebugStateActive;
312	/** Whether the TSC offset mode needs to be updated. */
313	bool fUpdateTscOffsetting;
314	/** Whether the TSC_AUX MSR needs restoring on \#VMEXIT. */
315	bool fRestoreTscAuxMsr;
316	/** Whether the \#VMEXIT was caused by a page-fault during delivery of a
317	* contributary exception or a page-fault. */
318	bool fVectoringDoublePF;
319	/** Whether the \#VMEXIT was caused by a page-fault during delivery of an
320	* external interrupt or NMI. */
321	bool fVectoringPF;
322	} SVMTRANSIENT, *PSVMTRANSIENT;
323	AssertCompileMemberAlignment(SVMTRANSIENT, u64ExitCode, sizeof(uint64_t));
324	AssertCompileMemberAlignment(SVMTRANSIENT, pVmcb, sizeof(uint64_t));
325	/** @} */
326
327	/**
328	* MSRPM (MSR permission bitmap) read permissions (for guest RDMSR).
329	*/
330	typedef enum SVMMSREXITREAD
331	{
332	/** Reading this MSR causes a \#VMEXIT. */
333	SVMMSREXIT_INTERCEPT_READ = 0xb,
334	/** Reading this MSR does not cause a \#VMEXIT. */
335	SVMMSREXIT_PASSTHRU_READ
336	} SVMMSREXITREAD;
337
338	/**
339	* MSRPM (MSR permission bitmap) write permissions (for guest WRMSR).
340	*/
341	typedef enum SVMMSREXITWRITE
342	{
343	/** Writing to this MSR causes a \#VMEXIT. */
344	SVMMSREXIT_INTERCEPT_WRITE = 0xd,
345	/** Writing to this MSR does not cause a \#VMEXIT. */
346	SVMMSREXIT_PASSTHRU_WRITE
347	} SVMMSREXITWRITE;
348
349	/**
350	* SVM \#VMEXIT handler.
351	*
352	* @returns VBox status code.
353	* @param pVCpu The cross context virtual CPU structure.
354	* @param pSvmTransient Pointer to the SVM-transient structure.
355	*/
356	typedef int FNSVMEXITHANDLER(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient);
357
358
359	/*********************************************************************************************************************************
360	* Internal Functions *
361	*********************************************************************************************************************************/
362	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu);
363	static void hmR0SvmLeave(PVMCPU pVCpu, bool fImportState);
364
365
366	/** @name \#VMEXIT handlers.
367	* @{
368	*/
369	static FNSVMEXITHANDLER hmR0SvmExitIntr;
370	static FNSVMEXITHANDLER hmR0SvmExitWbinvd;
371	static FNSVMEXITHANDLER hmR0SvmExitInvd;
372	static FNSVMEXITHANDLER hmR0SvmExitCpuid;
373	static FNSVMEXITHANDLER hmR0SvmExitRdtsc;
374	static FNSVMEXITHANDLER hmR0SvmExitRdtscp;
375	static FNSVMEXITHANDLER hmR0SvmExitRdpmc;
376	static FNSVMEXITHANDLER hmR0SvmExitInvlpg;
377	static FNSVMEXITHANDLER hmR0SvmExitHlt;
378	static FNSVMEXITHANDLER hmR0SvmExitMonitor;
379	static FNSVMEXITHANDLER hmR0SvmExitMwait;
380	static FNSVMEXITHANDLER hmR0SvmExitShutdown;
381	static FNSVMEXITHANDLER hmR0SvmExitUnexpected;
382	static FNSVMEXITHANDLER hmR0SvmExitReadCRx;
383	static FNSVMEXITHANDLER hmR0SvmExitWriteCRx;
384	static FNSVMEXITHANDLER hmR0SvmExitMsr;
385	static FNSVMEXITHANDLER hmR0SvmExitReadDRx;
386	static FNSVMEXITHANDLER hmR0SvmExitWriteDRx;
387	static FNSVMEXITHANDLER hmR0SvmExitXsetbv;
388	static FNSVMEXITHANDLER hmR0SvmExitIOInstr;
389	static FNSVMEXITHANDLER hmR0SvmExitNestedPF;
390	static FNSVMEXITHANDLER hmR0SvmExitVIntr;
391	static FNSVMEXITHANDLER hmR0SvmExitTaskSwitch;
392	static FNSVMEXITHANDLER hmR0SvmExitVmmCall;
393	static FNSVMEXITHANDLER hmR0SvmExitPause;
394	static FNSVMEXITHANDLER hmR0SvmExitFerrFreeze;
395	static FNSVMEXITHANDLER hmR0SvmExitIret;
396	static FNSVMEXITHANDLER hmR0SvmExitXcptPF;
397	static FNSVMEXITHANDLER hmR0SvmExitXcptUD;
398	static FNSVMEXITHANDLER hmR0SvmExitXcptMF;
399	static FNSVMEXITHANDLER hmR0SvmExitXcptDB;
400	static FNSVMEXITHANDLER hmR0SvmExitXcptAC;
401	static FNSVMEXITHANDLER hmR0SvmExitXcptBP;
402	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
403	static FNSVMEXITHANDLER hmR0SvmExitXcptGeneric;
404	#endif
405	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
406	static FNSVMEXITHANDLER hmR0SvmExitClgi;
407	static FNSVMEXITHANDLER hmR0SvmExitStgi;
408	static FNSVMEXITHANDLER hmR0SvmExitVmload;
409	static FNSVMEXITHANDLER hmR0SvmExitVmsave;
410	static FNSVMEXITHANDLER hmR0SvmExitInvlpga;
411	static FNSVMEXITHANDLER hmR0SvmExitVmrun;
412	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptDB;
413	static FNSVMEXITHANDLER hmR0SvmNestedExitXcptBP;
414	#endif
415	/** @} */
416
417	static int hmR0SvmHandleExit(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient);
418	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
419	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient);
420	#endif
421
422
423	/*********************************************************************************************************************************
424	* Global Variables *
425	*********************************************************************************************************************************/
426	/** Ring-0 memory object for the IO bitmap. */
427	static RTR0MEMOBJ g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
428	/** Physical address of the IO bitmap. */
429	static RTHCPHYS g_HCPhysIOBitmap;
430	/** Pointer to the IO bitmap. */
431	static R0PTRTYPE(void *) g_pvIOBitmap;
432
433	#ifdef VBOX_STRICT
434	# define HMSVM_LOG_RBP_RSP RT_BIT_32(0)
435	# define HMSVM_LOG_CR_REGS RT_BIT_32(1)
436	# define HMSVM_LOG_CS RT_BIT_32(2)
437	# define HMSVM_LOG_SS RT_BIT_32(3)
438	# define HMSVM_LOG_FS RT_BIT_32(4)
439	# define HMSVM_LOG_GS RT_BIT_32(5)
440	# define HMSVM_LOG_LBR RT_BIT_32(6)
441	# define HMSVM_LOG_ALL ( HMSVM_LOG_RBP_RSP \
442	\| HMSVM_LOG_CR_REGS \
443	\| HMSVM_LOG_CS \
444	\| HMSVM_LOG_SS \
445	\| HMSVM_LOG_FS \
446	\| HMSVM_LOG_GS \
447	\| HMSVM_LOG_LBR)
448
449	/**
450	* Dumps virtual CPU state and additional info. to the logger for diagnostics.
451	*
452	* @param pVCpu The cross context virtual CPU structure.
453	* @param pVmcb Pointer to the VM control block.
454	* @param pszPrefix Log prefix.
455	* @param fFlags Log flags, see HMSVM_LOG_XXX.
456	* @param uVerbose The verbosity level, currently unused.
457	*/
458	static void hmR0SvmLogState(PVMCPU pVCpu, PCSVMVMCB pVmcb, const char *pszPrefix, uint32_t fFlags, uint8_t uVerbose)
459	{
460	RT_NOREF2(pVCpu, uVerbose);
461	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
462
463	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
464	Log4(("%s: cs:rip=%04x:%RX64 efl=%#RX64\n", pszPrefix, pCtx->cs.Sel, pCtx->rip, pCtx->rflags.u));
465
466	if (fFlags & HMSVM_LOG_RBP_RSP)
467	{
468	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_RBP);
469	Log4(("%s: rsp=%#RX64 rbp=%#RX64\n", pszPrefix, pCtx->rsp, pCtx->rbp));
470	}
471
472	if (fFlags & HMSVM_LOG_CR_REGS)
473	{
474	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4);
475	Log4(("%s: cr0=%#RX64 cr3=%#RX64 cr4=%#RX64\n", pszPrefix, pCtx->cr0, pCtx->cr3, pCtx->cr4));
476	}
477
478	if (fFlags & HMSVM_LOG_CS)
479	{
480	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS);
481	Log4(("%s: cs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base,
482	pCtx->cs.u32Limit, pCtx->cs.Attr.u));
483	}
484	if (fFlags & HMSVM_LOG_SS)
485	{
486	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_SS);
487	Log4(("%s: ss={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base,
488	pCtx->ss.u32Limit, pCtx->ss.Attr.u));
489	}
490	if (fFlags & HMSVM_LOG_FS)
491	{
492	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_FS);
493	Log4(("%s: fs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base,
494	pCtx->fs.u32Limit, pCtx->fs.Attr.u));
495	}
496	if (fFlags & HMSVM_LOG_GS)
497	{
498	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_GS);
499	Log4(("%s: gs={%04x base=%016RX64 limit=%08x flags=%08x}\n", pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base,
500	pCtx->gs.u32Limit, pCtx->gs.Attr.u));
501	}
502
503	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
504	if (fFlags & HMSVM_LOG_LBR)
505	{
506	Log4(("%s: br_from=%#RX64 br_to=%#RX64 lastxcpt_from=%#RX64 lastxcpt_to=%#RX64\n", pszPrefix, pVmcbGuest->u64BR_FROM,
507	pVmcbGuest->u64BR_TO, pVmcbGuest->u64LASTEXCPFROM, pVmcbGuest->u64LASTEXCPTO));
508	}
509	NOREF(pVmcbGuest); NOREF(pCtx);
510	}
511	#endif /* VBOX_STRICT */
512
513
514	/**
515	* Sets up and activates AMD-V on the current CPU.
516	*
517	* @returns VBox status code.
518	* @param pHostCpu Pointer to the CPU info struct.
519	* @param pVM The cross context VM structure. Can be
520	* NULL after a resume!
521	* @param pvCpuPage Pointer to the global CPU page.
522	* @param HCPhysCpuPage Physical address of the global CPU page.
523	* @param fEnabledByHost Whether the host OS has already initialized AMD-V.
524	* @param pvArg Unused on AMD-V.
525	*/
526	VMMR0DECL(int) SVMR0EnableCpu(PHMGLOBALCPUINFO pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage, bool fEnabledByHost,
527	void *pvArg)
528	{
529	Assert(!fEnabledByHost);
530	Assert(HCPhysCpuPage && HCPhysCpuPage != NIL_RTHCPHYS);
531	Assert(RT_ALIGN_T(HCPhysCpuPage, _4K, RTHCPHYS) == HCPhysCpuPage);
532	Assert(pvCpuPage); NOREF(pvCpuPage);
533	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
534
535	NOREF(pvArg);
536	NOREF(fEnabledByHost);
537
538	/* Paranoid: Disable interrupt as, in theory, interrupt handlers might mess with EFER. */
539	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
540
541	/*
542	* We must turn on AMD-V and setup the host state physical address, as those MSRs are per CPU.
543	*/
544	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
545	if (u64HostEfer & MSR_K6_EFER_SVME)
546	{
547	/* If the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE is active, then we blindly use AMD-V. */
548	if ( pVM
549	&& pVM->hm.s.svm.fIgnoreInUseError)
550	pHostCpu->fIgnoreAMDVInUseError = true;
551
552	if (!pHostCpu->fIgnoreAMDVInUseError)
553	{
554	ASMSetFlags(fEFlags);
555	return VERR_SVM_IN_USE;
556	}
557	}
558
559	/* Turn on AMD-V in the EFER MSR. */
560	ASMWrMsr(MSR_K6_EFER, u64HostEfer \| MSR_K6_EFER_SVME);
561
562	/* Write the physical page address where the CPU will store the host state while executing the VM. */
563	ASMWrMsr(MSR_K8_VM_HSAVE_PA, HCPhysCpuPage);
564
565	/* Restore interrupts. */
566	ASMSetFlags(fEFlags);
567
568	/*
569	* Theoretically, other hypervisors may have used ASIDs, ideally we should flush all
570	* non-zero ASIDs when enabling SVM. AMD doesn't have an SVM instruction to flush all
571	* ASIDs (flushing is done upon VMRUN). Therefore, flag that we need to flush the TLB
572	* entirely with before executing any guest code.
573	*/
574	pHostCpu->fFlushAsidBeforeUse = true;
575
576	/*
577	* Ensure each VCPU scheduled on this CPU gets a new ASID on resume. See @bugref{6255}.
578	*/
579	++pHostCpu->cTlbFlushes;
580
581	return VINF_SUCCESS;
582	}
583
584
585	/**
586	* Deactivates AMD-V on the current CPU.
587	*
588	* @returns VBox status code.
589	* @param pHostCpu Pointer to the CPU info struct.
590	* @param pvCpuPage Pointer to the global CPU page.
591	* @param HCPhysCpuPage Physical address of the global CPU page.
592	*/
593	VMMR0DECL(int) SVMR0DisableCpu(PHMGLOBALCPUINFO pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
594	{
595	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
596	AssertReturn( HCPhysCpuPage
597	&& HCPhysCpuPage != NIL_RTHCPHYS, VERR_INVALID_PARAMETER);
598	AssertReturn(pvCpuPage, VERR_INVALID_PARAMETER);
599	RT_NOREF(pHostCpu);
600
601	/* Paranoid: Disable interrupts as, in theory, interrupt handlers might mess with EFER. */
602	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
603
604	/* Turn off AMD-V in the EFER MSR. */
605	uint64_t u64HostEfer = ASMRdMsr(MSR_K6_EFER);
606	ASMWrMsr(MSR_K6_EFER, u64HostEfer & ~MSR_K6_EFER_SVME);
607
608	/* Invalidate host state physical address. */
609	ASMWrMsr(MSR_K8_VM_HSAVE_PA, 0);
610
611	/* Restore interrupts. */
612	ASMSetFlags(fEFlags);
613
614	return VINF_SUCCESS;
615	}
616
617
618	/**
619	* Does global AMD-V initialization (called during module initialization).
620	*
621	* @returns VBox status code.
622	*/
623	VMMR0DECL(int) SVMR0GlobalInit(void)
624	{
625	/*
626	* Allocate 12 KB (3 pages) for the IO bitmap. Since this is non-optional and we always
627	* intercept all IO accesses, it's done once globally here instead of per-VM.
628	*/
629	Assert(g_hMemObjIOBitmap == NIL_RTR0MEMOBJ);
630	int rc = RTR0MemObjAllocCont(&g_hMemObjIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, false /* fExecutable */);
631	if (RT_FAILURE(rc))
632	return rc;
633
634	g_pvIOBitmap = RTR0MemObjAddress(g_hMemObjIOBitmap);
635	g_HCPhysIOBitmap = RTR0MemObjGetPagePhysAddr(g_hMemObjIOBitmap, 0 /* iPage */);
636
637	/* Set all bits to intercept all IO accesses. */
638	ASMMemFill32(g_pvIOBitmap, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
639
640	return VINF_SUCCESS;
641	}
642
643
644	/**
645	* Does global AMD-V termination (called during module termination).
646	*/
647	VMMR0DECL(void) SVMR0GlobalTerm(void)
648	{
649	if (g_hMemObjIOBitmap != NIL_RTR0MEMOBJ)
650	{
651	RTR0MemObjFree(g_hMemObjIOBitmap, true /* fFreeMappings */);
652	g_pvIOBitmap = NULL;
653	g_HCPhysIOBitmap = 0;
654	g_hMemObjIOBitmap = NIL_RTR0MEMOBJ;
655	}
656	}
657
658
659	/**
660	* Frees any allocated per-VCPU structures for a VM.
661	*
662	* @param pVM The cross context VM structure.
663	*/
664	DECLINLINE(void) hmR0SvmFreeStructs(PVM pVM)
665	{
666	for (uint32_t i = 0; i < pVM->cCpus; i++)
667	{
668	PVMCPU pVCpu = &pVM->aCpus[i];
669	AssertPtr(pVCpu);
670
671	if (pVCpu->hm.s.svm.hMemObjVmcbHost != NIL_RTR0MEMOBJ)
672	{
673	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcbHost, false);
674	pVCpu->hm.s.svm.HCPhysVmcbHost = 0;
675	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
676	}
677
678	if (pVCpu->hm.s.svm.hMemObjVmcb != NIL_RTR0MEMOBJ)
679	{
680	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjVmcb, false);
681	pVCpu->hm.s.svm.pVmcb = NULL;
682	pVCpu->hm.s.svm.HCPhysVmcb = 0;
683	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
684	}
685
686	if (pVCpu->hm.s.svm.hMemObjMsrBitmap != NIL_RTR0MEMOBJ)
687	{
688	RTR0MemObjFree(pVCpu->hm.s.svm.hMemObjMsrBitmap, false);
689	pVCpu->hm.s.svm.pvMsrBitmap = NULL;
690	pVCpu->hm.s.svm.HCPhysMsrBitmap = 0;
691	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
692	}
693	}
694	}
695
696
697	/**
698	* Does per-VM AMD-V initialization.
699	*
700	* @returns VBox status code.
701	* @param pVM The cross context VM structure.
702	*/
703	VMMR0DECL(int) SVMR0InitVM(PVM pVM)
704	{
705	int rc = VERR_INTERNAL_ERROR_5;
706
707	/*
708	* Check for an AMD CPU erratum which requires us to flush the TLB before every world-switch.
709	*/
710	uint32_t u32Family;
711	uint32_t u32Model;
712	uint32_t u32Stepping;
713	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
714	{
715	Log4Func(("AMD cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
716	pVM->hm.s.svm.fAlwaysFlushTLB = true;
717	}
718
719	/*
720	* Initialize the R0 memory objects up-front so we can properly cleanup on allocation failures.
721	*/
722	for (VMCPUID i = 0; i < pVM->cCpus; i++)
723	{
724	PVMCPU pVCpu = &pVM->aCpus[i];
725	pVCpu->hm.s.svm.hMemObjVmcbHost = NIL_RTR0MEMOBJ;
726	pVCpu->hm.s.svm.hMemObjVmcb = NIL_RTR0MEMOBJ;
727	pVCpu->hm.s.svm.hMemObjMsrBitmap = NIL_RTR0MEMOBJ;
728	}
729
730	for (VMCPUID i = 0; i < pVM->cCpus; i++)
731	{
732	PVMCPU pVCpu = &pVM->aCpus[i];
733
734	/*
735	* Allocate one page for the host-context VM control block (VMCB). This is used for additional host-state (such as
736	* FS, GS, Kernel GS Base, etc.) apart from the host-state save area specified in MSR_K8_VM_HSAVE_PA.
737	*/
738	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcbHost, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
739	if (RT_FAILURE(rc))
740	goto failure_cleanup;
741
742	void *pvVmcbHost = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcbHost);
743	pVCpu->hm.s.svm.HCPhysVmcbHost = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcbHost, 0 /* iPage */);
744	Assert(pVCpu->hm.s.svm.HCPhysVmcbHost < _4G);
745	ASMMemZeroPage(pvVmcbHost);
746
747	/*
748	* Allocate one page for the guest-state VMCB.
749	*/
750	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjVmcb, SVM_VMCB_PAGES << PAGE_SHIFT, false /* fExecutable */);
751	if (RT_FAILURE(rc))
752	goto failure_cleanup;
753
754	pVCpu->hm.s.svm.pVmcb = (PSVMVMCB)RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjVmcb);
755	pVCpu->hm.s.svm.HCPhysVmcb = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjVmcb, 0 /* iPage */);
756	Assert(pVCpu->hm.s.svm.HCPhysVmcb < _4G);
757	ASMMemZeroPage(pVCpu->hm.s.svm.pVmcb);
758
759	/*
760	* Allocate two pages (8 KB) for the MSR permission bitmap. There doesn't seem to be a way to convince
761	* SVM to not require one.
762	*/
763	rc = RTR0MemObjAllocCont(&pVCpu->hm.s.svm.hMemObjMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
764	false /* fExecutable */);
765	if (RT_FAILURE(rc))
766	goto failure_cleanup;
767
768	pVCpu->hm.s.svm.pvMsrBitmap = RTR0MemObjAddress(pVCpu->hm.s.svm.hMemObjMsrBitmap);
769	pVCpu->hm.s.svm.HCPhysMsrBitmap = RTR0MemObjGetPagePhysAddr(pVCpu->hm.s.svm.hMemObjMsrBitmap, 0 /* iPage */);
770	/* Set all bits to intercept all MSR accesses (changed later on). */
771	ASMMemFill32(pVCpu->hm.s.svm.pvMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
772	}
773
774	return VINF_SUCCESS;
775
776	failure_cleanup:
777	hmR0SvmFreeStructs(pVM);
778	return rc;
779	}
780
781
782	/**
783	* Does per-VM AMD-V termination.
784	*
785	* @returns VBox status code.
786	* @param pVM The cross context VM structure.
787	*/
788	VMMR0DECL(int) SVMR0TermVM(PVM pVM)
789	{
790	hmR0SvmFreeStructs(pVM);
791	return VINF_SUCCESS;
792	}
793
794
795	/**
796	* Returns whether the VMCB Clean Bits feature is supported.
797	*
798	* @return @c true if supported, @c false otherwise.
799	* @param pVCpu The cross context virtual CPU structure.
800	*/
801	DECLINLINE(bool) hmR0SvmSupportsVmcbCleanBits(PVMCPU pVCpu)
802	{
803	PVM pVM = pVCpu->CTX_SUFF(pVM);
804	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
805	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
806	{
807	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN)
808	&& pVM->cpum.ro.GuestFeatures.fSvmVmcbClean;
809	}
810	#endif
811	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN);
812	}
813
814
815	/**
816	* Returns whether the decode assists feature is supported.
817	*
818	* @return @c true if supported, @c false otherwise.
819	* @param pVCpu The cross context virtual CPU structure.
820	*/
821	DECLINLINE(bool) hmR0SvmSupportsDecodeAssists(PVMCPU pVCpu)
822	{
823	PVM pVM = pVCpu->CTX_SUFF(pVM);
824	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
825	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
826	{
827	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS)
828	&& pVM->cpum.ro.GuestFeatures.fSvmDecodeAssists;
829	}
830	#endif
831	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
832	}
833
834
835	/**
836	* Returns whether the NRIP_SAVE feature is supported.
837	*
838	* @return @c true if supported, @c false otherwise.
839	* @param pVCpu The cross context virtual CPU structure.
840	*/
841	DECLINLINE(bool) hmR0SvmSupportsNextRipSave(PVMCPU pVCpu)
842	{
843	PVM pVM = pVCpu->CTX_SUFF(pVM);
844	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
845	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
846	{
847	return (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE)
848	&& pVM->cpum.ro.GuestFeatures.fSvmNextRipSave;
849	}
850	#endif
851	return RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE);
852	}
853
854
855	/**
856	* Sets the permission bits for the specified MSR in the MSRPM bitmap.
857	*
858	* @param pVCpu The cross context virtual CPU structure.
859	* @param pbMsrBitmap Pointer to the MSR bitmap.
860	* @param idMsr The MSR for which the permissions are being set.
861	* @param enmRead MSR read permissions.
862	* @param enmWrite MSR write permissions.
863	*
864	* @remarks This function does -not- clear the VMCB clean bits for MSRPM. The
865	* caller needs to take care of this.
866	*/
867	static void hmR0SvmSetMsrPermission(PVMCPU pVCpu, uint8_t *pbMsrBitmap, uint32_t idMsr, SVMMSREXITREAD enmRead,
868	SVMMSREXITWRITE enmWrite)
869	{
870	bool const fInNestedGuestMode = CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx);
871	uint16_t offMsrpm;
872	uint8_t uMsrpmBit;
873	int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
874	AssertRC(rc);
875
876	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
877	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
878
879	pbMsrBitmap += offMsrpm;
880	if (enmRead == SVMMSREXIT_INTERCEPT_READ)
881	*pbMsrBitmap \|= RT_BIT(uMsrpmBit);
882	else
883	{
884	if (!fInNestedGuestMode)
885	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
886	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
887	else
888	{
889	/* Only clear the bit if the nested-guest is also not intercepting the MSR read.*/
890	uint8_t const pbNstGstMsrBitmap = (uint8_t )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
891	pbNstGstMsrBitmap += offMsrpm;
892	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit)))
893	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit);
894	else
895	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit));
896	}
897	#endif
898	}
899
900	if (enmWrite == SVMMSREXIT_INTERCEPT_WRITE)
901	*pbMsrBitmap \|= RT_BIT(uMsrpmBit + 1);
902	else
903	{
904	if (!fInNestedGuestMode)
905	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
906	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
907	else
908	{
909	/* Only clear the bit if the nested-guest is also not intercepting the MSR write.*/
910	uint8_t const pbNstGstMsrBitmap = (uint8_t )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
911	pbNstGstMsrBitmap += offMsrpm;
912	if (!(*pbNstGstMsrBitmap & RT_BIT(uMsrpmBit + 1)))
913	*pbMsrBitmap &= ~RT_BIT(uMsrpmBit + 1);
914	else
915	Assert(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
916	}
917	#endif
918	}
919	}
920
921
922	/**
923	* Sets up AMD-V for the specified VM.
924	* This function is only called once per-VM during initalization.
925	*
926	* @returns VBox status code.
927	* @param pVM The cross context VM structure.
928	*/
929	VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
930	{
931	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
932	AssertReturn(pVM, VERR_INVALID_PARAMETER);
933	Assert(pVM->hm.s.svm.fSupported);
934
935	bool const fPauseFilter = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER);
936	bool const fPauseFilterThreshold = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD);
937	bool const fUsePauseFilter = fPauseFilter && pVM->hm.s.svm.cPauseFilter;
938
939	bool const fLbrVirt = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT);
940	bool const fUseLbrVirt = fLbrVirt; /** @todo CFGM, IEM implementation etc. */
941
942	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
943	bool const fVirtVmsaveVmload = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD);
944	bool const fUseVirtVmsaveVmload = fVirtVmsaveVmload && pVM->hm.s.svm.fVirtVmsaveVmload && pVM->hm.s.fNestedPaging;
945
946	bool const fVGif = RT_BOOL(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF);
947	bool const fUseVGif = fVGif && pVM->hm.s.svm.fVGif;
948	#endif
949
950	PVMCPU pVCpu = &pVM->aCpus[0];
951	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
952	AssertMsgReturn(pVmcb, ("Invalid pVmcb for vcpu[0]\n"), VERR_SVM_INVALID_PVMCB);
953	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
954
955	/* Always trap #AC for reasons of security. */
956	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_AC);
957
958	/* Always trap #DB for reasons of security. */
959	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT_32(X86_XCPT_DB);
960
961	/* Trap exceptions unconditionally (debug purposes). */
962	#ifdef HMSVM_ALWAYS_TRAP_PF
963	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
964	#endif
965	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
966	/* If you add any exceptions here, make sure to update hmR0SvmHandleExit(). */
967	pVmcbCtrl->u32InterceptXcpt \|= 0
968	\| RT_BIT(X86_XCPT_BP)
969	\| RT_BIT(X86_XCPT_DE)
970	\| RT_BIT(X86_XCPT_NM)
971	\| RT_BIT(X86_XCPT_UD)
972	\| RT_BIT(X86_XCPT_NP)
973	\| RT_BIT(X86_XCPT_SS)
974	\| RT_BIT(X86_XCPT_GP)
975	\| RT_BIT(X86_XCPT_PF)
976	\| RT_BIT(X86_XCPT_MF)
977	;
978	#endif
979
980	/* Apply the exceptions intercepts needed by the GIM provider. */
981	if (pVCpu->hm.s.fGIMTrapXcptUD)
982	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT(X86_XCPT_UD);
983
984	/* Set up unconditional intercepts and conditions. */
985	pVmcbCtrl->u64InterceptCtrl = HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS
986	\| SVM_CTRL_INTERCEPT_VMMCALL;
987
988	#ifdef HMSVM_ALWAYS_TRAP_TASK_SWITCH
989	pVmcbCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_TASK_SWITCH;
990	#endif
991
992	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
993	/* Virtualized VMSAVE/VMLOAD. */
994	pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload = fUseVirtVmsaveVmload;
995	if (!fUseVirtVmsaveVmload)
996	{
997	pVmcbCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
998	\| SVM_CTRL_INTERCEPT_VMLOAD;
999	}
1000
1001	/* Virtual GIF. */
1002	pVmcbCtrl->IntCtrl.n.u1VGifEnable = fUseVGif;
1003	if (!fUseVGif)
1004	{
1005	pVmcbCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
1006	\| SVM_CTRL_INTERCEPT_STGI;
1007	}
1008	#endif
1009
1010	/* CR4 writes must always be intercepted for tracking PGM mode changes. */
1011	pVmcbCtrl->u16InterceptWrCRx = RT_BIT(4);
1012
1013	/* Intercept all DRx reads and writes by default. Changed later on. */
1014	pVmcbCtrl->u16InterceptRdDRx = 0xffff;
1015	pVmcbCtrl->u16InterceptWrDRx = 0xffff;
1016
1017	/* Virtualize masking of INTR interrupts. (reads/writes from/to CR8 go to the V_TPR register) */
1018	pVmcbCtrl->IntCtrl.n.u1VIntrMasking = 1;
1019
1020	/* Ignore the priority in the virtual TPR. This is necessary for delivering PIC style (ExtInt) interrupts
1021	and we currently deliver both PIC and APIC interrupts alike, see hmR0SvmEvaluatePendingEvent() */
1022	pVmcbCtrl->IntCtrl.n.u1IgnoreTPR = 1;
1023
1024	/* Set the IO permission bitmap physical addresses. */
1025	pVmcbCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
1026
1027	/* LBR virtualization. */
1028	pVmcbCtrl->LbrVirt.n.u1LbrVirt = fUseLbrVirt;
1029
1030	/* The host ASID MBZ, for the guest start with 1. */
1031	pVmcbCtrl->TLBCtrl.n.u32ASID = 1;
1032
1033	/* Setup Nested Paging. This doesn't change throughout the execution time of the VM. */
1034	pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging = pVM->hm.s.fNestedPaging;
1035
1036	/* Without Nested Paging, we need additionally intercepts. */
1037	if (!pVM->hm.s.fNestedPaging)
1038	{
1039	/* CR3 reads/writes must be intercepted; our shadow values differ from the guest values. */
1040	pVmcbCtrl->u16InterceptRdCRx \|= RT_BIT(3);
1041	pVmcbCtrl->u16InterceptWrCRx \|= RT_BIT(3);
1042
1043	/* Intercept INVLPG and task switches (may change CR3, EFLAGS, LDT). */
1044	pVmcbCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_INVLPG
1045	\| SVM_CTRL_INTERCEPT_TASK_SWITCH;
1046
1047	/* Page faults must be intercepted to implement shadow paging. */
1048	pVmcbCtrl->u32InterceptXcpt \|= RT_BIT(X86_XCPT_PF);
1049	}
1050
1051	/* Setup Pause Filter for guest pause-loop (spinlock) exiting. */
1052	if (fUsePauseFilter)
1053	{
1054	Assert(pVM->hm.s.svm.cPauseFilter > 0);
1055	pVmcbCtrl->u16PauseFilterCount = pVM->hm.s.svm.cPauseFilter;
1056	if (fPauseFilterThreshold)
1057	pVmcbCtrl->u16PauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
1058	pVmcbCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_PAUSE;
1059	}
1060
1061	/*
1062	* Setup the MSR permission bitmap.
1063	* The following MSRs are saved/restored automatically during the world-switch.
1064	* Don't intercept guest read/write accesses to these MSRs.
1065	*/
1066	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
1067	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1068	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_CSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1069	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K6_STAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1070	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_SF_MASK, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1071	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_FS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1072	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1073	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_KERNEL_GS_BASE, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1074	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_IA32_SYSENTER_CS, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1075	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_IA32_SYSENTER_ESP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1076	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_IA32_SYSENTER_EIP, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
1077	pVmcbCtrl->u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
1078
1079	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1080	Assert(pVmcbCtrl->u32VmcbCleanBits == 0);
1081
1082	for (VMCPUID i = 1; i < pVM->cCpus; i++)
1083	{
1084	PVMCPU pVCpuCur = &pVM->aCpus[i];
1085	PSVMVMCB pVmcbCur = pVM->aCpus[i].hm.s.svm.pVmcb;
1086	AssertMsgReturn(pVmcbCur, ("Invalid pVmcb for vcpu[%u]\n", i), VERR_SVM_INVALID_PVMCB);
1087	PSVMVMCBCTRL pVmcbCtrlCur = &pVmcbCur->ctrl;
1088
1089	/* Copy the VMCB control area. */
1090	memcpy(pVmcbCtrlCur, pVmcbCtrl, sizeof(*pVmcbCtrlCur));
1091
1092	/* Copy the MSR bitmap and setup the VCPU-specific host physical address. */
1093	uint8_t pbMsrBitmapCur = (uint8_t )pVCpuCur->hm.s.svm.pvMsrBitmap;
1094	memcpy(pbMsrBitmapCur, pbMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1095	pVmcbCtrlCur->u64MSRPMPhysAddr = pVCpuCur->hm.s.svm.HCPhysMsrBitmap;
1096
1097	/* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
1098	Assert(pVmcbCtrlCur->u32VmcbCleanBits == 0);
1099
1100	/* Verify our assumption that GIM providers trap #UD uniformly across VCPUs initially. */
1101	Assert(pVCpuCur->hm.s.fGIMTrapXcptUD == pVCpu->hm.s.fGIMTrapXcptUD);
1102	}
1103
1104	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1105	LogRel(("HM: fUsePauseFilter=%RTbool fUseLbrVirt=%RTbool fUseVGif=%RTbool fUseVirtVmsaveVmload=%RTbool\n", fUsePauseFilter,
1106	fUseLbrVirt, fUseVGif, fUseVirtVmsaveVmload));
1107	#else
1108	LogRel(("HM: fUsePauseFilter=%RTbool fUseLbrVirt=%RTbool\n", fUsePauseFilter, fUseLbrVirt));
1109	#endif
1110	return VINF_SUCCESS;
1111	}
1112
1113
1114	/**
1115	* Gets a pointer to the currently active guest (or nested-guest) VMCB.
1116	*
1117	* @returns Pointer to the current context VMCB.
1118	* @param pVCpu The cross context virtual CPU structure.
1119	*/
1120	DECLINLINE(PSVMVMCB) hmR0SvmGetCurrentVmcb(PVMCPU pVCpu)
1121	{
1122	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1123	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
1124	return pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
1125	#endif
1126	return pVCpu->hm.s.svm.pVmcb;
1127	}
1128
1129
1130	/**
1131	* Gets a pointer to the nested-guest VMCB cache.
1132	*
1133	* @returns Pointer to the nested-guest VMCB cache.
1134	* @param pVCpu The cross context virtual CPU structure.
1135	*/
1136	DECLINLINE(PSVMNESTEDVMCBCACHE) hmR0SvmGetNestedVmcbCache(PVMCPU pVCpu)
1137	{
1138	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1139	Assert(pVCpu->hm.s.svm.NstGstVmcbCache.fCacheValid);
1140	return &pVCpu->hm.s.svm.NstGstVmcbCache;
1141	#else
1142	RT_NOREF(pVCpu);
1143	return NULL;
1144	#endif
1145	}
1146
1147
1148	/**
1149	* Invalidates a guest page by guest virtual address.
1150	*
1151	* @returns VBox status code.
1152	* @param pVCpu The cross context virtual CPU structure.
1153	* @param GCVirt Guest virtual address of the page to invalidate.
1154	*/
1155	VMMR0DECL(int) SVMR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)
1156	{
1157	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
1158
1159	bool const fFlushPending = pVCpu->CTX_SUFF(pVM)->hm.s.svm.fAlwaysFlushTLB \|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
1160
1161	/* Skip it if a TLB flush is already pending. */
1162	if (!fFlushPending)
1163	{
1164	Log4Func(("%#RGv\n", GCVirt));
1165
1166	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
1167	AssertMsgReturn(pVmcb, ("Invalid pVmcb!\n"), VERR_SVM_INVALID_PVMCB);
1168
1169	#if HC_ARCH_BITS == 32
1170	/* If we get a flush in 64-bit guest mode, then force a full TLB flush. INVLPGA takes only 32-bit addresses. */
1171	if (CPUMIsGuestInLongMode(pVCpu))
1172	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1173	else
1174	#endif
1175	{
1176	SVMR0InvlpgA(GCVirt, pVmcb->ctrl.TLBCtrl.n.u32ASID);
1177	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgVirt);
1178	}
1179	}
1180	return VINF_SUCCESS;
1181	}
1182
1183
1184	/**
1185	* Flushes the appropriate tagged-TLB entries.
1186	*
1187	* @param pVCpu The cross context virtual CPU structure.
1188	* @param pVmcb Pointer to the VM control block.
1189	* @param pHostCpu Pointer to the HM host-CPU info.
1190	*/
1191	static void hmR0SvmFlushTaggedTlb(PVMCPU pVCpu, PSVMVMCB pVmcb, PHMGLOBALCPUINFO pHostCpu)
1192	{
1193	/*
1194	* Force a TLB flush for the first world switch if the current CPU differs from the one
1195	* we ran on last. This can happen both for start & resume due to long jumps back to
1196	* ring-3.
1197	*
1198	* We also force a TLB flush every time when executing a nested-guest VCPU as there is no
1199	* correlation between it and the physical CPU.
1200	*
1201	* If the TLB flush count changed, another VM (VCPU rather) has hit the ASID limit while
1202	* flushing the TLB, so we cannot reuse the ASIDs without flushing.
1203	*/
1204	bool fNewAsid = false;
1205	Assert(pHostCpu->idCpu != NIL_RTCPUID);
1206	if ( pVCpu->hm.s.idLastCpu != pHostCpu->idCpu
1207	\|\| pVCpu->hm.s.cTlbFlushes != pHostCpu->cTlbFlushes
1208	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1209	\|\| CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx)
1210	#endif
1211	)
1212	{
1213	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbWorldSwitch);
1214	pVCpu->hm.s.fForceTLBFlush = true;
1215	fNewAsid = true;
1216	}
1217
1218	/* Set TLB flush state as checked until we return from the world switch. */
1219	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true);
1220
1221	/* Check for explicit TLB flushes. */
1222	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_TLB_FLUSH))
1223	{
1224	pVCpu->hm.s.fForceTLBFlush = true;
1225	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlb);
1226	}
1227
1228	/*
1229	* If the AMD CPU erratum 170, We need to flush the entire TLB for each world switch. Sad.
1230	* This Host CPU requirement takes precedence.
1231	*/
1232	PVM pVM = pVCpu->CTX_SUFF(pVM);
1233	if (pVM->hm.s.svm.fAlwaysFlushTLB)
1234	{
1235	pHostCpu->uCurrentAsid = 1;
1236	pVCpu->hm.s.uCurrentAsid = 1;
1237	pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1238	pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
1239	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1240
1241	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1242	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1243	}
1244	else
1245	{
1246	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_NOTHING;
1247	if (pVCpu->hm.s.fForceTLBFlush)
1248	{
1249	/* Clear the VMCB Clean Bit for NP while flushing the TLB. See @bugref{7152}. */
1250	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1251
1252	if (fNewAsid)
1253	{
1254	++pHostCpu->uCurrentAsid;
1255
1256	bool fHitASIDLimit = false;
1257	if (pHostCpu->uCurrentAsid >= pVM->hm.s.uMaxAsid)
1258	{
1259	pHostCpu->uCurrentAsid = 1; /* Wraparound at 1; host uses 0 */
1260	pHostCpu->cTlbFlushes++; /* All VCPUs that run on this host CPU must use a new ASID. */
1261	fHitASIDLimit = true;
1262	}
1263
1264	if ( fHitASIDLimit
1265	\|\| pHostCpu->fFlushAsidBeforeUse)
1266	{
1267	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1268	pHostCpu->fFlushAsidBeforeUse = false;
1269	}
1270
1271	pVCpu->hm.s.uCurrentAsid = pHostCpu->uCurrentAsid;
1272	pVCpu->hm.s.idLastCpu = pHostCpu->idCpu;
1273	pVCpu->hm.s.cTlbFlushes = pHostCpu->cTlbFlushes;
1274	}
1275	else
1276	{
1277	if (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID)
1278	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_SINGLE_CONTEXT;
1279	else
1280	pVmcb->ctrl.TLBCtrl.n.u8TLBFlush = SVM_TLB_FLUSH_ENTIRE;
1281	}
1282
1283	pVCpu->hm.s.fForceTLBFlush = false;
1284	}
1285	}
1286
1287	/* Update VMCB with the ASID. */
1288	if (pVmcb->ctrl.TLBCtrl.n.u32ASID != pVCpu->hm.s.uCurrentAsid)
1289	{
1290	pVmcb->ctrl.TLBCtrl.n.u32ASID = pVCpu->hm.s.uCurrentAsid;
1291	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_ASID;
1292	}
1293
1294	AssertMsg(pVCpu->hm.s.idLastCpu == pHostCpu->idCpu,
1295	("vcpu idLastCpu=%u hostcpu idCpu=%u\n", pVCpu->hm.s.idLastCpu, pHostCpu->idCpu));
1296	AssertMsg(pVCpu->hm.s.cTlbFlushes == pHostCpu->cTlbFlushes,
1297	("Flush count mismatch for cpu %u (%u vs %u)\n", pHostCpu->idCpu, pVCpu->hm.s.cTlbFlushes, pHostCpu->cTlbFlushes));
1298	AssertMsg(pHostCpu->uCurrentAsid >= 1 && pHostCpu->uCurrentAsid < pVM->hm.s.uMaxAsid,
1299	("cpu%d uCurrentAsid = %x\n", pHostCpu->idCpu, pHostCpu->uCurrentAsid));
1300	AssertMsg(pVCpu->hm.s.uCurrentAsid >= 1 && pVCpu->hm.s.uCurrentAsid < pVM->hm.s.uMaxAsid,
1301	("cpu%d VM uCurrentAsid = %x\n", pHostCpu->idCpu, pVCpu->hm.s.uCurrentAsid));
1302
1303	#ifdef VBOX_WITH_STATISTICS
1304	if (pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_NOTHING)
1305	STAM_COUNTER_INC(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch);
1306	else if ( pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT
1307	\|\| pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_SINGLE_CONTEXT_RETAIN_GLOBALS)
1308	{
1309	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushAsid);
1310	}
1311	else
1312	{
1313	Assert(pVmcb->ctrl.TLBCtrl.n.u8TLBFlush == SVM_TLB_FLUSH_ENTIRE);
1314	STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushEntire);
1315	}
1316	#endif
1317	}
1318
1319
1320	/** @name 64-bit guest on 32-bit host OS helper functions.
1321	*
1322	* The host CPU is still 64-bit capable but the host OS is running in 32-bit
1323	* mode (code segment, paging). These wrappers/helpers perform the necessary
1324	* bits for the 32->64 switcher.
1325	*
1326	* @{ */
1327	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1328	/**
1329	* Prepares for and executes VMRUN (64-bit guests on a 32-bit host).
1330	*
1331	* @returns VBox status code.
1332	* @param HCPhysVmcbHost Physical address of host VMCB.
1333	* @param HCPhysVmcb Physical address of the VMCB.
1334	* @param pCtx Pointer to the guest-CPU context.
1335	* @param pVM The cross context VM structure.
1336	* @param pVCpu The cross context virtual CPU structure.
1337	*/
1338	DECLASM(int) SVMR0VMSwitcherRun64(RTHCPHYS HCPhysVmcbHost, RTHCPHYS HCPhysVmcb, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu)
1339	{
1340	RT_NOREF2(pVM, pCtx);
1341	uint32_t aParam[8];
1342	aParam[0] = RT_LO_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Lo. */
1343	aParam[1] = RT_HI_U32(HCPhysVmcbHost); /* Param 1: HCPhysVmcbHost - Hi. */
1344	aParam[2] = RT_LO_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Lo. */
1345	aParam[3] = RT_HI_U32(HCPhysVmcb); /* Param 2: HCPhysVmcb - Hi. */
1346	aParam[4] = VM_RC_ADDR(pVM, pVM);
1347	aParam[5] = 0;
1348	aParam[6] = VM_RC_ADDR(pVM, pVCpu);
1349	aParam[7] = 0;
1350
1351	return SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_SVMRCVMRun64, RT_ELEMENTS(aParam), &aParam[0]);
1352	}
1353
1354
1355	/**
1356	* Executes the specified VMRUN handler in 64-bit mode.
1357	*
1358	* @returns VBox status code.
1359	* @param pVCpu The cross context virtual CPU structure.
1360	* @param enmOp The operation to perform.
1361	* @param cParams Number of parameters.
1362	* @param paParam Array of 32-bit parameters.
1363	*/
1364	VMMR0DECL(int) SVMR0Execute64BitsHandler(PVMCPU pVCpu, HM64ON32OP enmOp, uint32_t cParams, uint32_t *paParam)
1365	{
1366	PVM pVM = pVCpu->CTX_SUFF(pVM);
1367	AssertReturn(pVM->hm.s.pfnHost32ToGuest64R0, VERR_HM_NO_32_TO_64_SWITCHER);
1368	Assert(enmOp > HM64ON32OP_INVALID && enmOp < HM64ON32OP_END);
1369
1370	/* Disable interrupts. */
1371	RTHCUINTREG const fEFlags = ASMIntDisableFlags();
1372
1373	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1374	RTCPUID idHostCpu = RTMpCpuId();
1375	CPUMR0SetLApic(pVCpu, idHostCpu);
1376	#endif
1377
1378	CPUMSetHyperESP(pVCpu, VMMGetStackRC(pVCpu));
1379	CPUMSetHyperEIP(pVCpu, enmOp);
1380	for (int i = (int)cParams - 1; i >= 0; i--)
1381	CPUMPushHyper(pVCpu, paParam[i]);
1382
1383	/* Call the switcher. */
1384	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1385	int rc = pVM->hm.s.pfnHost32ToGuest64R0(pVM, RT_UOFFSETOF_DYN(VM, aCpus[pVCpu->idCpu].cpum) - RT_UOFFSETOF(VM, cpum));
1386	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1387
1388	/* Restore interrupts. */
1389	ASMSetFlags(fEFlags);
1390	return rc;
1391	}
1392
1393	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) */
1394	/** @} */
1395
1396
1397	/**
1398	* Sets an exception intercept in the specified VMCB.
1399	*
1400	* @param pVmcb Pointer to the VM control block.
1401	* @param uXcpt The exception (X86_XCPT_*).
1402	*/
1403	DECLINLINE(void) hmR0SvmSetXcptIntercept(PSVMVMCB pVmcb, uint8_t uXcpt)
1404	{
1405	if (!(pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt)))
1406	{
1407	pVmcb->ctrl.u32InterceptXcpt \|= RT_BIT(uXcpt);
1408	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1409	}
1410	}
1411
1412
1413	/**
1414	* Clears an exception intercept in the specified VMCB.
1415	*
1416	* @param pVCpu The cross context virtual CPU structure.
1417	* @param pVmcb Pointer to the VM control block.
1418	* @param uXcpt The exception (X86_XCPT_*).
1419	*
1420	* @remarks This takes into account if we're executing a nested-guest and only
1421	* removes the exception intercept if both the guest -and- nested-guest
1422	* are not intercepting it.
1423	*/
1424	DECLINLINE(void) hmR0SvmClearXcptIntercept(PVMCPU pVCpu, PSVMVMCB pVmcb, uint8_t uXcpt)
1425	{
1426	Assert(uXcpt != X86_XCPT_DB);
1427	Assert(uXcpt != X86_XCPT_AC);
1428	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
1429	if (pVmcb->ctrl.u32InterceptXcpt & RT_BIT(uXcpt))
1430	{
1431	bool fRemove = true;
1432	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1433	/* Only remove the intercept if the nested-guest is also not intercepting it! */
1434	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1435	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1436	{
1437	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1438	fRemove = !(pVmcbNstGstCache->u32InterceptXcpt & RT_BIT(uXcpt));
1439	}
1440	# else
1441	RT_NOREF(pVCpu);
1442	# endif
1443	if (fRemove)
1444	{
1445	pVmcb->ctrl.u32InterceptXcpt &= ~RT_BIT(uXcpt);
1446	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1447	}
1448	}
1449	#else
1450	RT_NOREF3(pVCpu, pVmcb, uXcpt);
1451	#endif
1452	}
1453
1454
1455	/**
1456	* Sets a control intercept in the specified VMCB.
1457	*
1458	* @param pVmcb Pointer to the VM control block.
1459	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1460	*/
1461	DECLINLINE(void) hmR0SvmSetCtrlIntercept(PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1462	{
1463	if (!(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept))
1464	{
1465	pVmcb->ctrl.u64InterceptCtrl \|= fCtrlIntercept;
1466	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1467	}
1468	}
1469
1470
1471	/**
1472	* Clears a control intercept in the specified VMCB.
1473	*
1474	* @returns @c true if the intercept is still set, @c false otherwise.
1475	* @param pVCpu The cross context virtual CPU structure.
1476	* @param pVmcb Pointer to the VM control block.
1477	* @param fCtrlIntercept The control intercept (SVM_CTRL_INTERCEPT_*).
1478	*
1479	* @remarks This takes into account if we're executing a nested-guest and only
1480	* removes the control intercept if both the guest -and- nested-guest
1481	* are not intercepting it.
1482	*/
1483	static bool hmR0SvmClearCtrlIntercept(PVMCPU pVCpu, PSVMVMCB pVmcb, uint64_t fCtrlIntercept)
1484	{
1485	if (pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept)
1486	{
1487	bool fRemove = true;
1488	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1489	/* Only remove the control intercept if the nested-guest is also not intercepting it! */
1490	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
1491	{
1492	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1493	fRemove = !(pVmcbNstGstCache->u64InterceptCtrl & fCtrlIntercept);
1494	}
1495	#else
1496	RT_NOREF(pVCpu);
1497	#endif
1498	if (fRemove)
1499	{
1500	pVmcb->ctrl.u64InterceptCtrl &= ~fCtrlIntercept;
1501	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1502	}
1503	}
1504
1505	return RT_BOOL(pVmcb->ctrl.u64InterceptCtrl & fCtrlIntercept);
1506	}
1507
1508
1509	/**
1510	* Exports the guest (or nested-guest) CR0 into the VMCB.
1511	*
1512	* @param pVCpu The cross context virtual CPU structure.
1513	* @param pVmcb Pointer to the VM control block.
1514	*
1515	* @remarks This assumes we always pre-load the guest FPU.
1516	* @remarks No-long-jump zone!!!
1517	*/
1518	static void hmR0SvmExportGuestCR0(PVMCPU pVCpu, PSVMVMCB pVmcb)
1519	{
1520	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1521
1522	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1523	uint64_t const uGuestCr0 = pCtx->cr0;
1524	uint64_t uShadowCr0 = uGuestCr0;
1525
1526	/* Always enable caching. */
1527	uShadowCr0 &= ~(X86_CR0_CD \| X86_CR0_NW);
1528
1529	/* When Nested Paging is not available use shadow page tables and intercept #PFs (latter done in SVMR0SetupVM()). */
1530	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1531	{
1532	uShadowCr0 \|= X86_CR0_PG /* Use shadow page tables. */
1533	\| X86_CR0_WP; /* Guest CPL 0 writes to its read-only pages should cause a #PF #VMEXIT. */
1534	}
1535
1536	/*
1537	* Use the #MF style of legacy-FPU error reporting for now. Although AMD-V has MSRs that
1538	* lets us isolate the host from it, IEM/REM still needs work to emulate it properly,
1539	* see @bugref{7243#c103}.
1540	*/
1541	if (!(uGuestCr0 & X86_CR0_NE))
1542	{
1543	uShadowCr0 \|= X86_CR0_NE;
1544	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_MF);
1545	}
1546	else
1547	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_MF);
1548
1549	/*
1550	* If the shadow and guest CR0 are identical we can avoid intercepting CR0 reads.
1551	*
1552	* CR0 writes still needs interception as PGM requires tracking paging mode changes,
1553	* see @bugref{6944}.
1554	*
1555	* We also don't ever want to honor weird things like cache disable from the guest.
1556	* However, we can avoid intercepting changes to the TS & MP bits by clearing the CR0
1557	* write intercept below and keeping SVM_CTRL_INTERCEPT_CR0_SEL_WRITE instead.
1558	*/
1559	if (uShadowCr0 == uGuestCr0)
1560	{
1561	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1562	{
1563	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(0);
1564	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(0);
1565	Assert(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_CR0_SEL_WRITE);
1566	}
1567	else
1568	{
1569	/* If the nested-hypervisor intercepts CR0 reads/writes, we need to continue intercepting them. */
1570	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1571	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(0))
1572	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(0));
1573	pVmcb->ctrl.u16InterceptWrCRx = (pVmcb->ctrl.u16InterceptWrCRx & ~RT_BIT(0))
1574	\| (pVmcbNstGstCache->u16InterceptWrCRx & RT_BIT(0));
1575	}
1576	}
1577	else
1578	{
1579	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(0);
1580	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(0);
1581	}
1582	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
1583
1584	Assert(!RT_HI_U32(uShadowCr0));
1585	if (pVmcb->guest.u64CR0 != uShadowCr0)
1586	{
1587	pVmcb->guest.u64CR0 = uShadowCr0;
1588	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1589	}
1590	}
1591
1592
1593	/**
1594	* Exports the guest (or nested-guest) CR3 into the VMCB.
1595	*
1596	* @param pVCpu The cross context virtual CPU structure.
1597	* @param pVmcb Pointer to the VM control block.
1598	*
1599	* @remarks No-long-jump zone!!!
1600	*/
1601	static void hmR0SvmExportGuestCR3(PVMCPU pVCpu, PSVMVMCB pVmcb)
1602	{
1603	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1604
1605	PVM pVM = pVCpu->CTX_SUFF(pVM);
1606	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1607	if (pVM->hm.s.fNestedPaging)
1608	{
1609	PGMMODE enmShwPagingMode;
1610	#if HC_ARCH_BITS == 32
1611	if (CPUMIsGuestInLongModeEx(pCtx))
1612	enmShwPagingMode = PGMMODE_AMD64_NX;
1613	else
1614	#endif
1615	enmShwPagingMode = PGMGetHostMode(pVM);
1616
1617	pVmcb->ctrl.u64NestedPagingCR3 = PGMGetNestedCR3(pVCpu, enmShwPagingMode);
1618	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_NP;
1619	pVmcb->guest.u64CR3 = pCtx->cr3;
1620	Assert(pVmcb->ctrl.u64NestedPagingCR3);
1621	}
1622	else
1623	pVmcb->guest.u64CR3 = PGMGetHyperCR3(pVCpu);
1624
1625	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1626	}
1627
1628
1629	/**
1630	* Exports the guest (or nested-guest) CR4 into the VMCB.
1631	*
1632	* @param pVCpu The cross context virtual CPU structure.
1633	* @param pVmcb Pointer to the VM control block.
1634	*
1635	* @remarks No-long-jump zone!!!
1636	*/
1637	static int hmR0SvmExportGuestCR4(PVMCPU pVCpu, PSVMVMCB pVmcb)
1638	{
1639	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1640
1641	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1642	uint64_t uShadowCr4 = pCtx->cr4;
1643	if (!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging)
1644	{
1645	switch (pVCpu->hm.s.enmShadowMode)
1646	{
1647	case PGMMODE_REAL:
1648	case PGMMODE_PROTECTED: /* Protected mode, no paging. */
1649	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1650
1651	case PGMMODE_32_BIT: /* 32-bit paging. */
1652	uShadowCr4 &= ~X86_CR4_PAE;
1653	break;
1654
1655	case PGMMODE_PAE: /* PAE paging. */
1656	case PGMMODE_PAE_NX: /* PAE paging with NX enabled. */
1657	/** Must use PAE paging as we could use physical memory > 4 GB */
1658	uShadowCr4 \|= X86_CR4_PAE;
1659	break;
1660
1661	case PGMMODE_AMD64: /* 64-bit AMD paging (long mode). */
1662	case PGMMODE_AMD64_NX: /* 64-bit AMD paging (long mode) with NX enabled. */
1663	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1664	break;
1665	#else
1666	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1667	#endif
1668
1669	default: /* shut up gcc */
1670	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
1671	}
1672	}
1673
1674	/* Whether to save/load/restore XCR0 during world switch depends on CR4.OSXSAVE and host+guest XCR0. */
1675	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
1676
1677	/* Avoid intercepting CR4 reads if the guest and shadow CR4 values are identical. */
1678	if (uShadowCr4 == pCtx->cr4)
1679	{
1680	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
1681	pVmcb->ctrl.u16InterceptRdCRx &= ~RT_BIT(4);
1682	else
1683	{
1684	/* If the nested-hypervisor intercepts CR4 reads, we need to continue intercepting them. */
1685	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = hmR0SvmGetNestedVmcbCache(pVCpu);
1686	pVmcb->ctrl.u16InterceptRdCRx = (pVmcb->ctrl.u16InterceptRdCRx & ~RT_BIT(4))
1687	\| (pVmcbNstGstCache->u16InterceptRdCRx & RT_BIT(4));
1688	}
1689	}
1690	else
1691	pVmcb->ctrl.u16InterceptRdCRx \|= RT_BIT(4);
1692
1693	/* CR4 writes are always intercepted (both guest, nested-guest) for tracking PGM mode changes. */
1694	Assert(pVmcb->ctrl.u16InterceptWrCRx & RT_BIT(4));
1695
1696	/* Update VMCB with the shadow CR4 the appropriate VMCB clean bits. */
1697	Assert(!RT_HI_U32(uShadowCr4));
1698	pVmcb->guest.u64CR4 = uShadowCr4;
1699	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_CRX_EFER \| HMSVM_VMCB_CLEAN_INTERCEPTS);
1700
1701	return VINF_SUCCESS;
1702	}
1703
1704
1705	/**
1706	* Exports the guest (or nested-guest) control registers into the VMCB.
1707	*
1708	* @returns VBox status code.
1709	* @param pVCpu The cross context virtual CPU structure.
1710	* @param pVmcb Pointer to the VM control block.
1711	*
1712	* @remarks No-long-jump zone!!!
1713	*/
1714	static int hmR0SvmExportGuestControlRegs(PVMCPU pVCpu, PSVMVMCB pVmcb)
1715	{
1716	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1717
1718	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR_MASK)
1719	{
1720	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR0)
1721	hmR0SvmExportGuestCR0(pVCpu, pVmcb);
1722
1723	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR2)
1724	{
1725	pVmcb->guest.u64CR2 = pVCpu->cpum.GstCtx.cr2;
1726	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CR2;
1727	}
1728
1729	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR3)
1730	hmR0SvmExportGuestCR3(pVCpu, pVmcb);
1731
1732	/* CR4 re-loading is ASSUMED to be done everytime we get in from ring-3! (XCR0) */
1733	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CR4)
1734	{
1735	int rc = hmR0SvmExportGuestCR4(pVCpu, pVmcb);
1736	if (RT_FAILURE(rc))
1737	return rc;
1738	}
1739
1740	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_CR_MASK;
1741	}
1742	return VINF_SUCCESS;
1743	}
1744
1745
1746	/**
1747	* Exports the guest (or nested-guest) segment registers into the VMCB.
1748	*
1749	* @returns VBox status code.
1750	* @param pVCpu The cross context virtual CPU structure.
1751	* @param pVmcb Pointer to the VM control block.
1752	*
1753	* @remarks No-long-jump zone!!!
1754	*/
1755	static void hmR0SvmExportGuestSegmentRegs(PVMCPU pVCpu, PSVMVMCB pVmcb)
1756	{
1757	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1758	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1759
1760	/* Guest segment registers. */
1761	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SREG_MASK)
1762	{
1763	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_CS)
1764	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, CS, cs);
1765
1766	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SS)
1767	{
1768	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, SS, ss);
1769	pVmcb->guest.u8CPL = pCtx->ss.Attr.n.u2Dpl;
1770	}
1771
1772	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DS)
1773	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, DS, ds);
1774
1775	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_ES)
1776	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, ES, es);
1777
1778	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_FS)
1779	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, FS, fs);
1780
1781	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_GS)
1782	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, GS, gs);
1783
1784	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_SEG;
1785	}
1786
1787	/* Guest TR. */
1788	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_TR)
1789	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, TR, tr);
1790
1791	/* Guest LDTR. */
1792	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_LDTR)
1793	HMSVM_SEG_REG_COPY_TO_VMCB(pCtx, &pVmcb->guest, LDTR, ldtr);
1794
1795	/* Guest GDTR. */
1796	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_GDTR)
1797	{
1798	pVmcb->guest.GDTR.u32Limit = pCtx->gdtr.cbGdt;
1799	pVmcb->guest.GDTR.u64Base = pCtx->gdtr.pGdt;
1800	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1801	}
1802
1803	/* Guest IDTR. */
1804	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_IDTR)
1805	{
1806	pVmcb->guest.IDTR.u32Limit = pCtx->idtr.cbIdt;
1807	pVmcb->guest.IDTR.u64Base = pCtx->idtr.pIdt;
1808	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DT;
1809	}
1810
1811	pVCpu->hm.s.fCtxChanged &= ~( HM_CHANGED_GUEST_SREG_MASK
1812	\| HM_CHANGED_GUEST_TABLE_MASK);
1813	}
1814
1815
1816	/**
1817	* Exports the guest (or nested-guest) MSRs into the VMCB.
1818	*
1819	* @param pVCpu The cross context virtual CPU structure.
1820	* @param pVmcb Pointer to the VM control block.
1821	*
1822	* @remarks No-long-jump zone!!!
1823	*/
1824	static void hmR0SvmExportGuestMsrs(PVMCPU pVCpu, PSVMVMCB pVmcb)
1825	{
1826	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1827	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1828
1829	/* Guest Sysenter MSRs. */
1830	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_MSR_MASK)
1831	{
1832	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_CS_MSR)
1833	pVmcb->guest.u64SysEnterCS = pCtx->SysEnter.cs;
1834
1835	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_EIP_MSR)
1836	pVmcb->guest.u64SysEnterEIP = pCtx->SysEnter.eip;
1837
1838	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSENTER_ESP_MSR)
1839	pVmcb->guest.u64SysEnterESP = pCtx->SysEnter.esp;
1840	}
1841
1842	/*
1843	* Guest EFER MSR.
1844	* AMD-V requires guest EFER.SVME to be set. Weird.
1845	* See AMD spec. 15.5.1 "Basic Operation" \| "Canonicalization and Consistency Checks".
1846	*/
1847	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_EFER_MSR)
1848	{
1849	pVmcb->guest.u64EFER = pCtx->msrEFER \| MSR_K6_EFER_SVME;
1850	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1851	}
1852
1853	/* If the guest isn't in 64-bit mode, clear MSR_K6_LME bit, otherwise SVM expects amd64 shadow paging. */
1854	if ( !CPUMIsGuestInLongModeEx(pCtx)
1855	&& (pCtx->msrEFER & MSR_K6_EFER_LME))
1856	{
1857	pVmcb->guest.u64EFER &= ~MSR_K6_EFER_LME;
1858	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_CRX_EFER;
1859	}
1860
1861	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_SYSCALL_MSRS)
1862	{
1863	pVmcb->guest.u64STAR = pCtx->msrSTAR;
1864	pVmcb->guest.u64LSTAR = pCtx->msrLSTAR;
1865	pVmcb->guest.u64CSTAR = pCtx->msrCSTAR;
1866	pVmcb->guest.u64SFMASK = pCtx->msrSFMASK;
1867	}
1868
1869	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_KERNEL_GS_BASE)
1870	pVmcb->guest.u64KernelGSBase = pCtx->msrKERNELGSBASE;
1871
1872	pVCpu->hm.s.fCtxChanged &= ~( HM_CHANGED_GUEST_SYSENTER_MSR_MASK
1873	\| HM_CHANGED_GUEST_EFER_MSR
1874	\| HM_CHANGED_GUEST_SYSCALL_MSRS
1875	\| HM_CHANGED_GUEST_KERNEL_GS_BASE);
1876
1877	/*
1878	* Setup the PAT MSR (applicable for Nested Paging only).
1879	*
1880	* While guests can modify and see the modified values through the shadow values,
1881	* we shall not honor any guest modifications of this MSR to ensure caching is always
1882	* enabled similar to how we clear CR0.CD and NW bits.
1883	*
1884	* For nested-guests this needs to always be set as well, see @bugref{7243#c109}.
1885	*/
1886	pVmcb->guest.u64PAT = MSR_IA32_CR_PAT_INIT_VAL;
1887
1888	/* Enable the last branch record bit if LBR virtualization is enabled. */
1889	if (pVmcb->ctrl.LbrVirt.n.u1LbrVirt)
1890	pVmcb->guest.u64DBGCTL = MSR_IA32_DEBUGCTL_LBR;
1891	}
1892
1893
1894	/**
1895	* Exports the guest (or nested-guest) debug state into the VMCB and programs
1896	* the necessary intercepts accordingly.
1897	*
1898	* @param pVCpu The cross context virtual CPU structure.
1899	* @param pVmcb Pointer to the VM control block.
1900	*
1901	* @remarks No-long-jump zone!!!
1902	* @remarks Requires EFLAGS to be up-to-date in the VMCB!
1903	*/
1904	static void hmR0SvmExportSharedDebugState(PVMCPU pVCpu, PSVMVMCB pVmcb)
1905	{
1906	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1907
1908	/*
1909	* Anyone single stepping on the host side? If so, we'll have to use the
1910	* trap flag in the guest EFLAGS since AMD-V doesn't have a trap flag on
1911	* the VMM level like the VT-x implementations does.
1912	*/
1913	bool fInterceptMovDRx = false;
1914	bool const fStepping = pVCpu->hm.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
1915	if (fStepping)
1916	{
1917	pVCpu->hm.s.fClearTrapFlag = true;
1918	pVmcb->guest.u64RFlags \|= X86_EFL_TF;
1919	fInterceptMovDRx = true; /* Need clean DR6, no guest mess. */
1920	}
1921
1922	if ( fStepping
1923	\|\| (CPUMGetHyperDR7(pVCpu) & X86_DR7_ENABLED_MASK))
1924	{
1925	/*
1926	* Use the combined guest and host DRx values found in the hypervisor
1927	* register set because the debugger has breakpoints active or someone
1928	* is single stepping on the host side.
1929	*
1930	* Note! DBGF expects a clean DR6 state before executing guest code.
1931	*/
1932	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1933	if ( CPUMIsGuestInLongModeEx(pCtx)
1934	&& !CPUMIsHyperDebugStateActivePending(pVCpu))
1935	{
1936	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1937	Assert(!CPUMIsGuestDebugStateActivePending(pVCpu));
1938	Assert(CPUMIsHyperDebugStateActivePending(pVCpu));
1939	}
1940	else
1941	#endif
1942	if (!CPUMIsHyperDebugStateActive(pVCpu))
1943	{
1944	CPUMR0LoadHyperDebugState(pVCpu, false /* include DR6 */);
1945	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
1946	Assert(CPUMIsHyperDebugStateActive(pVCpu));
1947	}
1948
1949	/* Update DR6 & DR7. (The other DRx values are handled by CPUM one way or the other.) */
1950	if ( pVmcb->guest.u64DR6 != X86_DR6_INIT_VAL
1951	\|\| pVmcb->guest.u64DR7 != CPUMGetHyperDR7(pVCpu))
1952	{
1953	pVmcb->guest.u64DR7 = CPUMGetHyperDR7(pVCpu);
1954	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
1955	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1956	}
1957
1958	/** @todo If we cared, we could optimize to allow the guest to read registers
1959	* with the same values. */
1960	fInterceptMovDRx = true;
1961	pVCpu->hm.s.fUsingHyperDR7 = true;
1962	Log5(("hmR0SvmExportSharedDebugState: Loaded hyper DRx\n"));
1963	}
1964	else
1965	{
1966	/*
1967	* Update DR6, DR7 with the guest values if necessary.
1968	*/
1969	if ( pVmcb->guest.u64DR7 != pCtx->dr[7]
1970	\|\| pVmcb->guest.u64DR6 != pCtx->dr[6])
1971	{
1972	pVmcb->guest.u64DR7 = pCtx->dr[7];
1973	pVmcb->guest.u64DR6 = pCtx->dr[6];
1974	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
1975	}
1976	pVCpu->hm.s.fUsingHyperDR7 = false;
1977
1978	/*
1979	* If the guest has enabled debug registers, we need to load them prior to
1980	* executing guest code so they'll trigger at the right time.
1981	*/
1982	if (pCtx->dr[7] & (X86_DR7_ENABLED_MASK \| X86_DR7_GD)) /** @todo Why GD? */
1983	{
1984	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
1985	if ( CPUMIsGuestInLongModeEx(pCtx)
1986	&& !CPUMIsGuestDebugStateActivePending(pVCpu))
1987	{
1988	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1989	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1990	Assert(!CPUMIsHyperDebugStateActivePending(pVCpu));
1991	Assert(CPUMIsGuestDebugStateActivePending(pVCpu));
1992	}
1993	else
1994	#endif
1995	if (!CPUMIsGuestDebugStateActive(pVCpu))
1996	{
1997	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
1998	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxArmed);
1999	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
2000	Assert(CPUMIsGuestDebugStateActive(pVCpu));
2001	}
2002	Log5(("hmR0SvmExportSharedDebugState: Loaded guest DRx\n"));
2003	}
2004	/*
2005	* If no debugging enabled, we'll lazy load DR0-3. We don't need to
2006	* intercept #DB as DR6 is updated in the VMCB.
2007	*
2008	* Note! If we cared and dared, we could skip intercepting \#DB here.
2009	* However, \#DB shouldn't be performance critical, so we'll play safe
2010	* and keep the code similar to the VT-x code and always intercept it.
2011	*/
2012	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
2013	else if ( !CPUMIsGuestDebugStateActivePending(pVCpu)
2014	&& !CPUMIsGuestDebugStateActive(pVCpu))
2015	#else
2016	else if (!CPUMIsGuestDebugStateActive(pVCpu))
2017	#endif
2018	{
2019	fInterceptMovDRx = true;
2020	}
2021	}
2022
2023	Assert(pVmcb->ctrl.u32InterceptXcpt & RT_BIT_32(X86_XCPT_DB));
2024	if (fInterceptMovDRx)
2025	{
2026	if ( pVmcb->ctrl.u16InterceptRdDRx != 0xffff
2027	\|\| pVmcb->ctrl.u16InterceptWrDRx != 0xffff)
2028	{
2029	pVmcb->ctrl.u16InterceptRdDRx = 0xffff;
2030	pVmcb->ctrl.u16InterceptWrDRx = 0xffff;
2031	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2032	}
2033	}
2034	else
2035	{
2036	if ( pVmcb->ctrl.u16InterceptRdDRx
2037	\|\| pVmcb->ctrl.u16InterceptWrDRx)
2038	{
2039	pVmcb->ctrl.u16InterceptRdDRx = 0;
2040	pVmcb->ctrl.u16InterceptWrDRx = 0;
2041	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2042	}
2043	}
2044	Log4Func(("DR6=%#RX64 DR7=%#RX64\n", pCtx->dr[6], pCtx->dr[7]));
2045	}
2046
2047	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2048	/**
2049	* Exports the nested-guest hardware virtualization state into the nested-guest
2050	* VMCB.
2051	*
2052	* @param pVCpu The cross context virtual CPU structure.
2053	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
2054	*
2055	* @remarks No-long-jump zone!!!
2056	*/
2057	static void hmR0SvmExportGuestHwvirtStateNested(PVMCPU pVCpu, PSVMVMCB pVmcbNstGst)
2058	{
2059	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2060
2061	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_HWVIRT)
2062	{
2063	/*
2064	* Ensure the nested-guest pause-filter counters don't exceed the outer guest values esp.
2065	* since SVM doesn't have a preemption timer.
2066	*
2067	* We do this here rather than in hmR0SvmSetupVmcbNested() as we may have been executing the
2068	* nested-guest in IEM incl. PAUSE instructions which would update the pause-filter counters
2069	* and may continue execution in SVM R0 without a nested-guest #VMEXIT in between.
2070	*/
2071	PVM pVM = pVCpu->CTX_SUFF(pVM);
2072	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2073	uint16_t const uGuestPauseFilterCount = pVM->hm.s.svm.cPauseFilter;
2074	uint16_t const uGuestPauseFilterThreshold = pVM->hm.s.svm.cPauseFilterThresholdTicks;
2075	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_PAUSE))
2076	{
2077	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2078	pVmcbNstGstCtrl->u16PauseFilterCount = RT_MIN(pCtx->hwvirt.svm.cPauseFilter, uGuestPauseFilterCount);
2079	pVmcbNstGstCtrl->u16PauseFilterThreshold = RT_MIN(pCtx->hwvirt.svm.cPauseFilterThreshold, uGuestPauseFilterThreshold);
2080	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2081	}
2082	else
2083	{
2084	pVmcbNstGstCtrl->u16PauseFilterCount = uGuestPauseFilterCount;
2085	pVmcbNstGstCtrl->u16PauseFilterThreshold = uGuestPauseFilterThreshold;
2086	}
2087
2088	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_HWVIRT;
2089	}
2090	}
2091	#endif
2092
2093	/**
2094	* Exports the guest APIC TPR state into the VMCB.
2095	*
2096	* @returns VBox status code.
2097	* @param pVCpu The cross context virtual CPU structure.
2098	* @param pVmcb Pointer to the VM control block.
2099	*/
2100	static int hmR0SvmExportGuestApicTpr(PVMCPU pVCpu, PSVMVMCB pVmcb)
2101	{
2102	if (ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged) & HM_CHANGED_GUEST_APIC_TPR)
2103	{
2104	PVM pVM = pVCpu->CTX_SUFF(pVM);
2105	if ( PDMHasApic(pVM)
2106	&& APICIsEnabled(pVCpu))
2107	{
2108	bool fPendingIntr;
2109	uint8_t u8Tpr;
2110	int rc = APICGetTpr(pVCpu, &u8Tpr, &fPendingIntr, NULL /* pu8PendingIrq */);
2111	AssertRCReturn(rc, rc);
2112
2113	/* Assume that we need to trap all TPR accesses and thus need not check on
2114	every #VMEXIT if we should update the TPR. */
2115	Assert(pVmcb->ctrl.IntCtrl.n.u1VIntrMasking);
2116	pVCpu->hm.s.svm.fSyncVTpr = false;
2117
2118	if (!pVM->hm.s.fTPRPatchingActive)
2119	{
2120	/* Bits 3-0 of the VTPR field correspond to bits 7-4 of the TPR (which is the Task-Priority Class). */
2121	pVmcb->ctrl.IntCtrl.n.u8VTPR = (u8Tpr >> 4);
2122
2123	/* If there are interrupts pending, intercept CR8 writes to evaluate ASAP if we
2124	can deliver the interrupt to the guest. */
2125	if (fPendingIntr)
2126	pVmcb->ctrl.u16InterceptWrCRx \|= RT_BIT(8);
2127	else
2128	{
2129	pVmcb->ctrl.u16InterceptWrCRx &= ~RT_BIT(8);
2130	pVCpu->hm.s.svm.fSyncVTpr = true;
2131	}
2132
2133	pVmcb->ctrl.u32VmcbCleanBits &= ~(HMSVM_VMCB_CLEAN_INTERCEPTS \| HMSVM_VMCB_CLEAN_INT_CTRL);
2134	}
2135	else
2136	{
2137	/* 32-bit guests uses LSTAR MSR for patching guest code which touches the TPR. */
2138	pVmcb->guest.u64LSTAR = u8Tpr;
2139	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
2140
2141	/* If there are interrupts pending, intercept LSTAR writes, otherwise don't intercept reads or writes. */
2142	if (fPendingIntr)
2143	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_INTERCEPT_WRITE);
2144	else
2145	{
2146	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_LSTAR, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
2147	pVCpu->hm.s.svm.fSyncVTpr = true;
2148	}
2149	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
2150	}
2151	}
2152	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_GUEST_APIC_TPR);
2153	}
2154	return VINF_SUCCESS;
2155	}
2156
2157
2158	/**
2159	* Sets up the exception interrupts required for guest (or nested-guest)
2160	* execution in the VMCB.
2161	*
2162	* @param pVCpu The cross context virtual CPU structure.
2163	* @param pVmcb Pointer to the VM control block.
2164	*
2165	* @remarks No-long-jump zone!!!
2166	*/
2167	static void hmR0SvmExportGuestXcptIntercepts(PVMCPU pVCpu, PSVMVMCB pVmcb)
2168	{
2169	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2170
2171	/* If we modify intercepts from here, please check & adjust hmR0SvmMergeVmcbCtrlsNested() if required. */
2172	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_GUEST_XCPT_INTERCEPTS)
2173	{
2174	/* Trap #UD for GIM provider (e.g. for hypercalls). */
2175	if (pVCpu->hm.s.fGIMTrapXcptUD)
2176	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_UD);
2177	else
2178	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_UD);
2179
2180	/* Trap #BP for INT3 debug breakpoints set by the VM debugger. */
2181	if (pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
2182	hmR0SvmSetXcptIntercept(pVmcb, X86_XCPT_BP);
2183	else
2184	hmR0SvmClearXcptIntercept(pVCpu, pVmcb, X86_XCPT_BP);
2185
2186	/* The remaining intercepts are handled elsewhere, e.g. in hmR0SvmExportGuestCR0(). */
2187	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_SVM_GUEST_XCPT_INTERCEPTS;
2188	}
2189	}
2190
2191
2192	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2193	/**
2194	* Merges guest and nested-guest intercepts for executing the nested-guest using
2195	* hardware-assisted SVM.
2196	*
2197	* This merges the guest and nested-guest intercepts in a way that if the outer
2198	* guest intercept is set we need to intercept it in the nested-guest as
2199	* well.
2200	*
2201	* @param pVCpu The cross context virtual CPU structure.
2202	* @param pVmcbNstGst Pointer to the nested-guest VM control block.
2203	*/
2204	static void hmR0SvmMergeVmcbCtrlsNested(PVMCPU pVCpu)
2205	{
2206	PVM pVM = pVCpu->CTX_SUFF(pVM);
2207	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2208	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2209	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2210
2211	/* Merge the guest's CR intercepts into the nested-guest VMCB. */
2212	pVmcbNstGstCtrl->u16InterceptRdCRx \|= pVmcb->ctrl.u16InterceptRdCRx;
2213	pVmcbNstGstCtrl->u16InterceptWrCRx \|= pVmcb->ctrl.u16InterceptWrCRx;
2214
2215	/* Always intercept CR4 writes for tracking PGM mode changes. */
2216	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(4);
2217
2218	/* Without nested paging, intercept CR3 reads and writes as we load shadow page tables. */
2219	if (!pVM->hm.s.fNestedPaging)
2220	{
2221	pVmcbNstGstCtrl->u16InterceptRdCRx \|= RT_BIT(3);
2222	pVmcbNstGstCtrl->u16InterceptWrCRx \|= RT_BIT(3);
2223	}
2224
2225	/** @todo Figure out debugging with nested-guests, till then just intercept
2226	* all DR[0-15] accesses. */
2227	pVmcbNstGstCtrl->u16InterceptRdDRx \|= 0xffff;
2228	pVmcbNstGstCtrl->u16InterceptWrDRx \|= 0xffff;
2229
2230	/*
2231	* Merge the guest's exception intercepts into the nested-guest VMCB.
2232	*
2233	* - \#UD: Exclude these as the outer guest's GIM hypercalls are not applicable
2234	* while executing the nested-guest.
2235	*
2236	* - \#BP: Exclude breakpoints set by the VM debugger for the outer guest. This can
2237	* be tweaked later depending on how we wish to implement breakpoints.
2238	*
2239	* Warning!! This ASSUMES we only intercept \#UD for hypercall purposes and \#BP
2240	* for VM debugger breakpoints, see hmR0SvmExportGuestXcptIntercepts().
2241	*/
2242	#ifndef HMSVM_ALWAYS_TRAP_ALL_XCPTS
2243	pVmcbNstGstCtrl->u32InterceptXcpt \|= (pVmcb->ctrl.u32InterceptXcpt & ~( RT_BIT(X86_XCPT_UD)
2244	\| RT_BIT(X86_XCPT_BP)));
2245	#else
2246	pVmcbNstGstCtrl->u32InterceptXcpt \|= pVmcb->ctrl.u32InterceptXcpt;
2247	#endif
2248
2249	/*
2250	* Adjust intercepts while executing the nested-guest that differ from the
2251	* outer guest intercepts.
2252	*
2253	* - VINTR: Exclude the outer guest intercept as we don't need to cause VINTR #VMEXITs
2254	* that belong to the nested-guest to the outer guest.
2255	*
2256	* - VMMCALL: Exclude the outer guest intercept as when it's also not intercepted by
2257	* the nested-guest, the physical CPU raises a \#UD exception as expected.
2258	*/
2259	pVmcbNstGstCtrl->u64InterceptCtrl \|= (pVmcb->ctrl.u64InterceptCtrl & ~( SVM_CTRL_INTERCEPT_VINTR
2260	\| SVM_CTRL_INTERCEPT_VMMCALL))
2261	\| HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS;
2262
2263	Assert( (pVmcbNstGstCtrl->u64InterceptCtrl & HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS)
2264	== HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS);
2265
2266	/* Finally, update the VMCB clean bits. */
2267	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2268	}
2269	#endif
2270
2271
2272	/**
2273	* Selects the appropriate function to run guest code.
2274	*
2275	* @returns VBox status code.
2276	* @param pVCpu The cross context virtual CPU structure.
2277	*
2278	* @remarks No-long-jump zone!!!
2279	*/
2280	static int hmR0SvmSelectVMRunHandler(PVMCPU pVCpu)
2281	{
2282	if (CPUMIsGuestInLongMode(pVCpu))
2283	{
2284	#ifndef VBOX_ENABLE_64_BITS_GUESTS
2285	return VERR_PGM_UNSUPPORTED_SHADOW_PAGING_MODE;
2286	#endif
2287	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fAllow64BitGuests); /* Guaranteed by hmR3InitFinalizeR0(). */
2288	#if HC_ARCH_BITS == 32
2289	/* 32-bit host. We need to switch to 64-bit before running the 64-bit guest. */
2290	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMSwitcherRun64;
2291	#else
2292	/* 64-bit host or hybrid host. */
2293	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun64;
2294	#endif
2295	}
2296	else
2297	{
2298	/* Guest is not in long mode, use the 32-bit handler. */
2299	pVCpu->hm.s.svm.pfnVMRun = SVMR0VMRun;
2300	}
2301	return VINF_SUCCESS;
2302	}
2303
2304
2305	/**
2306	* Enters the AMD-V session.
2307	*
2308	* @returns VBox status code.
2309	* @param pVCpu The cross context virtual CPU structure.
2310	* @param pHostCpu Pointer to the CPU info struct.
2311	*/
2312	VMMR0DECL(int) SVMR0Enter(PVMCPU pVCpu, PHMGLOBALCPUINFO pHostCpu)
2313	{
2314	AssertPtr(pVCpu);
2315	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
2316	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2317	RT_NOREF(pHostCpu);
2318
2319	LogFlowFunc(("pVCpu=%p\n", pVCpu));
2320	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
2321	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
2322
2323	pVCpu->hm.s.fLeaveDone = false;
2324	return VINF_SUCCESS;
2325	}
2326
2327
2328	/**
2329	* Thread-context callback for AMD-V.
2330	*
2331	* @param enmEvent The thread-context event.
2332	* @param pVCpu The cross context virtual CPU structure.
2333	* @param fGlobalInit Whether global VT-x/AMD-V init. is used.
2334	* @thread EMT(pVCpu)
2335	*/
2336	VMMR0DECL(void) SVMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
2337	{
2338	NOREF(fGlobalInit);
2339
2340	switch (enmEvent)
2341	{
2342	case RTTHREADCTXEVENT_OUT:
2343	{
2344	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2345	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2346	VMCPU_ASSERT_EMT(pVCpu);
2347
2348	/* No longjmps (log-flush, locks) in this fragile context. */
2349	VMMRZCallRing3Disable(pVCpu);
2350
2351	if (!pVCpu->hm.s.fLeaveDone)
2352	{
2353	hmR0SvmLeave(pVCpu, false /* fImportState */);
2354	pVCpu->hm.s.fLeaveDone = true;
2355	}
2356
2357	/* Leave HM context, takes care of local init (term). */
2358	int rc = HMR0LeaveCpu(pVCpu);
2359	AssertRC(rc); NOREF(rc);
2360
2361	/* Restore longjmp state. */
2362	VMMRZCallRing3Enable(pVCpu);
2363	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatSwitchPreempt);
2364	break;
2365	}
2366
2367	case RTTHREADCTXEVENT_IN:
2368	{
2369	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2370	Assert(VMMR0ThreadCtxHookIsEnabled(pVCpu));
2371	VMCPU_ASSERT_EMT(pVCpu);
2372
2373	/* No longjmps (log-flush, locks) in this fragile context. */
2374	VMMRZCallRing3Disable(pVCpu);
2375
2376	/*
2377	* Initialize the bare minimum state required for HM. This takes care of
2378	* initializing AMD-V if necessary (onlined CPUs, local init etc.)
2379	*/
2380	int rc = hmR0EnterCpu(pVCpu);
2381	AssertRC(rc); NOREF(rc);
2382	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
2383	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
2384
2385	pVCpu->hm.s.fLeaveDone = false;
2386
2387	/* Restore longjmp state. */
2388	VMMRZCallRing3Enable(pVCpu);
2389	break;
2390	}
2391
2392	default:
2393	break;
2394	}
2395	}
2396
2397
2398	/**
2399	* Saves the host state.
2400	*
2401	* @returns VBox status code.
2402	* @param pVCpu The cross context virtual CPU structure.
2403	*
2404	* @remarks No-long-jump zone!!!
2405	*/
2406	VMMR0DECL(int) SVMR0ExportHostState(PVMCPU pVCpu)
2407	{
2408	NOREF(pVCpu);
2409
2410	/* Nothing to do here. AMD-V does this for us automatically during the world-switch. */
2411	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~HM_CHANGED_HOST_CONTEXT);
2412	return VINF_SUCCESS;
2413	}
2414
2415
2416	/**
2417	* Exports the guest state from the guest-CPU context into the VMCB.
2418	*
2419	* The CPU state will be loaded from these fields on every successful VM-entry.
2420	* Also sets up the appropriate VMRUN function to execute guest code based on
2421	* the guest CPU mode.
2422	*
2423	* @returns VBox status code.
2424	* @param pVCpu The cross context virtual CPU structure.
2425	*
2426	* @remarks No-long-jump zone!!!
2427	*/
2428	static int hmR0SvmExportGuestState(PVMCPU pVCpu)
2429	{
2430	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExportGuestState, x);
2431
2432	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
2433	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2434
2435	Assert(pVmcb);
2436	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
2437
2438	pVmcb->guest.u64RIP = pCtx->rip;
2439	pVmcb->guest.u64RSP = pCtx->rsp;
2440	pVmcb->guest.u64RFlags = pCtx->eflags.u32;
2441	pVmcb->guest.u64RAX = pCtx->rax;
2442	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2443	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable)
2444	{
2445	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_VGIF);
2446	pVmcb->ctrl.IntCtrl.n.u1VGif = pCtx->hwvirt.fGif;
2447	}
2448	#endif
2449
2450	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2451
2452	int rc = hmR0SvmExportGuestControlRegs(pVCpu, pVmcb);
2453	AssertRCReturnStmt(rc, ASMSetFlags(fEFlags), rc);
2454
2455	hmR0SvmExportGuestSegmentRegs(pVCpu, pVmcb);
2456	hmR0SvmExportGuestMsrs(pVCpu, pVmcb);
2457	hmR0SvmExportGuestXcptIntercepts(pVCpu, pVmcb);
2458
2459	ASMSetFlags(fEFlags);
2460
2461	/* hmR0SvmExportGuestApicTpr() must be called -after- hmR0SvmExportGuestMsrs() as we
2462	otherwise we would overwrite the LSTAR MSR that we use for TPR patching. */
2463	hmR0SvmExportGuestApicTpr(pVCpu, pVmcb);
2464
2465	rc = hmR0SvmSelectVMRunHandler(pVCpu);
2466	AssertRCReturn(rc, rc);
2467
2468	/* Clear any bits that may be set but exported unconditionally or unused/reserved bits. */
2469	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~( HM_CHANGED_GUEST_RIP
2470	\| HM_CHANGED_GUEST_RFLAGS
2471	\| HM_CHANGED_GUEST_GPRS_MASK
2472	\| HM_CHANGED_GUEST_X87
2473	\| HM_CHANGED_GUEST_SSE_AVX
2474	\| HM_CHANGED_GUEST_OTHER_XSAVE
2475	\| HM_CHANGED_GUEST_XCRx
2476	\| HM_CHANGED_GUEST_TSC_AUX
2477	\| HM_CHANGED_GUEST_OTHER_MSRS
2478	\| HM_CHANGED_GUEST_HWVIRT
2479	\| (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_SVM_GUEST_XCPT_INTERCEPTS)));
2480
2481	#ifdef VBOX_STRICT
2482	/*
2483	* All of the guest-CPU state and SVM keeper bits should be exported here by now,
2484	* except for the host-context and/or shared host-guest context bits.
2485	*/
2486	uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
2487	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
2488	AssertMsg(!(fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)),
2489	("fCtxChanged=%#RX64\n", fCtxChanged));
2490
2491	/*
2492	* If we need to log state that isn't always imported, we'll need to import them here.
2493	* See hmR0SvmPostRunGuest() for which part of the state is imported uncondtionally.
2494	*/
2495	hmR0SvmLogState(pVCpu, pVmcb, "hmR0SvmExportGuestState", 0 /* fFlags /, 0 / uVerbose */);
2496	#endif
2497
2498	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExportGuestState, x);
2499	return VINF_SUCCESS;
2500	}
2501
2502
2503	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2504	/**
2505	* Merges the guest and nested-guest MSR permission bitmap.
2506	*
2507	* If the guest is intercepting an MSR we need to intercept it regardless of
2508	* whether the nested-guest is intercepting it or not.
2509	*
2510	* @param pHostCpu Pointer to the physical CPU HM info. struct.
2511	* @param pVCpu The cross context virtual CPU structure.
2512	*
2513	* @remarks No-long-jmp zone!!!
2514	*/
2515	DECLINLINE(void) hmR0SvmMergeMsrpmNested(PHMGLOBALCPUINFO pHostCpu, PVMCPU pVCpu)
2516	{
2517	uint64_t const pu64GstMsrpm = (uint64_t const )pVCpu->hm.s.svm.pvMsrBitmap;
2518	uint64_t const pu64NstGstMsrpm = (uint64_t const )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
2519	uint64_t pu64DstMsrpm = (uint64_t )pHostCpu->n.svm.pvNstGstMsrpm;
2520
2521	/* MSRPM bytes from offset 0x1800 are reserved, so we stop merging there. */
2522	uint32_t const offRsvdQwords = 0x1800 >> 3;
2523	for (uint32_t i = 0; i < offRsvdQwords; i++)
2524	pu64DstMsrpm[i] = pu64NstGstMsrpm[i] \| pu64GstMsrpm[i];
2525	}
2526
2527
2528	/**
2529	* Caches the nested-guest VMCB fields before we modify them for execution using
2530	* hardware-assisted SVM.
2531	*
2532	* @returns true if the VMCB was previously already cached, false otherwise.
2533	* @param pVCpu The cross context virtual CPU structure.
2534	*
2535	* @sa HMSvmNstGstVmExitNotify.
2536	*/
2537	static bool hmR0SvmCacheVmcbNested(PVMCPU pVCpu)
2538	{
2539	/*
2540	* Cache the nested-guest programmed VMCB fields if we have not cached it yet.
2541	* Otherwise we risk re-caching the values we may have modified, see @bugref{7243#c44}.
2542	*
2543	* Nested-paging CR3 is not saved back into the VMCB on #VMEXIT, hence no need to
2544	* cache and restore it, see AMD spec. 15.25.4 "Nested Paging and VMRUN/#VMEXIT".
2545	*/
2546	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
2547	bool const fWasCached = pVmcbNstGstCache->fCacheValid;
2548	if (!fWasCached)
2549	{
2550	PCSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2551	PCSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2552	pVmcbNstGstCache->u16InterceptRdCRx = pVmcbNstGstCtrl->u16InterceptRdCRx;
2553	pVmcbNstGstCache->u16InterceptWrCRx = pVmcbNstGstCtrl->u16InterceptWrCRx;
2554	pVmcbNstGstCache->u16InterceptRdDRx = pVmcbNstGstCtrl->u16InterceptRdDRx;
2555	pVmcbNstGstCache->u16InterceptWrDRx = pVmcbNstGstCtrl->u16InterceptWrDRx;
2556	pVmcbNstGstCache->u16PauseFilterThreshold = pVmcbNstGstCtrl->u16PauseFilterThreshold;
2557	pVmcbNstGstCache->u16PauseFilterCount = pVmcbNstGstCtrl->u16PauseFilterCount;
2558	pVmcbNstGstCache->u32InterceptXcpt = pVmcbNstGstCtrl->u32InterceptXcpt;
2559	pVmcbNstGstCache->u64InterceptCtrl = pVmcbNstGstCtrl->u64InterceptCtrl;
2560	pVmcbNstGstCache->u64TSCOffset = pVmcbNstGstCtrl->u64TSCOffset;
2561	pVmcbNstGstCache->fVIntrMasking = pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking;
2562	pVmcbNstGstCache->fNestedPaging = pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging;
2563	pVmcbNstGstCache->fLbrVirt = pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt;
2564	pVmcbNstGstCache->fCacheValid = true;
2565	Log4Func(("Cached VMCB fields\n"));
2566	}
2567
2568	return fWasCached;
2569	}
2570
2571
2572	/**
2573	* Sets up the nested-guest VMCB for execution using hardware-assisted SVM.
2574	*
2575	* This is done the first time we enter nested-guest execution using SVM R0
2576	* until the nested-guest \#VMEXIT (not to be confused with physical CPU
2577	* \#VMEXITs which may or may not cause a corresponding nested-guest \#VMEXIT).
2578	*
2579	* @param pVCpu The cross context virtual CPU structure.
2580	*/
2581	static void hmR0SvmSetupVmcbNested(PVMCPU pVCpu)
2582	{
2583	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
2584	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
2585
2586	/*
2587	* First cache the nested-guest VMCB fields we may potentially modify.
2588	*/
2589	bool const fVmcbCached = hmR0SvmCacheVmcbNested(pVCpu);
2590	if (!fVmcbCached)
2591	{
2592	/*
2593	* The IOPM of the nested-guest can be ignored because the the guest always
2594	* intercepts all IO port accesses. Thus, we'll swap to the guest IOPM rather
2595	* than the nested-guest IOPM and swap the field back on the #VMEXIT.
2596	*/
2597	pVmcbNstGstCtrl->u64IOPMPhysAddr = g_HCPhysIOBitmap;
2598
2599	/*
2600	* Use the same nested-paging as the outer guest. We can't dynamically switch off
2601	* nested-paging suddenly while executing a VM (see assertion at the end of
2602	* Trap0eHandler() in PGMAllBth.h).
2603	*/
2604	pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging = pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging;
2605
2606	/* Always enable V_INTR_MASKING as we do not want to allow access to the physical APIC TPR. */
2607	pVmcbNstGstCtrl->IntCtrl.n.u1VIntrMasking = 1;
2608
2609	/*
2610	* Turn off TPR syncing on #VMEXIT for nested-guests as CR8 intercepts are subject
2611	* to the nested-guest intercepts and we always run with V_INTR_MASKING.
2612	*/
2613	pVCpu->hm.s.svm.fSyncVTpr = false;
2614
2615	#ifdef DEBUG_ramshankar
2616	/* For debugging purposes - copy the LBR info. from outer guest VMCB. */
2617	pVmcbNstGstCtrl->LbrVirt.n.u1LbrVirt = pVmcb->ctrl.LbrVirt.n.u1LbrVirt;
2618	#endif
2619
2620	/*
2621	* If we don't expose Virtualized-VMSAVE/VMLOAD feature to the outer guest, we
2622	* need to intercept VMSAVE/VMLOAD instructions executed by the nested-guest.
2623	*/
2624	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVirtVmsaveVmload)
2625	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_VMSAVE
2626	\| SVM_CTRL_INTERCEPT_VMLOAD;
2627
2628	/*
2629	* If we don't expose Virtual GIF feature to the outer guest, we need to intercept
2630	* CLGI/STGI instructions executed by the nested-guest.
2631	*/
2632	if (!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fSvmVGif)
2633	pVmcbNstGstCtrl->u64InterceptCtrl \|= SVM_CTRL_INTERCEPT_CLGI
2634	\| SVM_CTRL_INTERCEPT_STGI;
2635
2636	/* Merge the guest and nested-guest intercepts. */
2637	hmR0SvmMergeVmcbCtrlsNested(pVCpu);
2638
2639	/* Update the VMCB clean bits. */
2640	pVmcbNstGstCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
2641	}
2642	else
2643	{
2644	Assert(!pVCpu->hm.s.svm.fSyncVTpr);
2645	Assert(pVmcbNstGstCtrl->u64IOPMPhysAddr == g_HCPhysIOBitmap);
2646	Assert(RT_BOOL(pVmcbNstGstCtrl->NestedPagingCtrl.n.u1NestedPaging) == pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
2647	}
2648	}
2649
2650
2651	/**
2652	* Exports the nested-guest state into the VMCB.
2653	*
2654	* We need to export the entire state as we could be continuing nested-guest
2655	* execution at any point (not just immediately after VMRUN) and thus the VMCB
2656	* can be out-of-sync with the nested-guest state if it was executed in IEM.
2657	*
2658	* @returns VBox status code.
2659	* @param pVCpu The cross context virtual CPU structure.
2660	* @param pCtx Pointer to the guest-CPU context.
2661	*
2662	* @remarks No-long-jump zone!!!
2663	*/
2664	static int hmR0SvmExportGuestStateNested(PVMCPU pVCpu)
2665	{
2666	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExportGuestState, x);
2667
2668	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2669	PSVMVMCB pVmcbNstGst = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
2670	Assert(pVmcbNstGst);
2671
2672	hmR0SvmSetupVmcbNested(pVCpu);
2673
2674	pVmcbNstGst->guest.u64RIP = pCtx->rip;
2675	pVmcbNstGst->guest.u64RSP = pCtx->rsp;
2676	pVmcbNstGst->guest.u64RFlags = pCtx->eflags.u32;
2677	pVmcbNstGst->guest.u64RAX = pCtx->rax;
2678
2679	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2680
2681	int rc = hmR0SvmExportGuestControlRegs(pVCpu, pVmcbNstGst);
2682	AssertRCReturnStmt(rc, ASMSetFlags(fEFlags), rc);
2683
2684	hmR0SvmExportGuestSegmentRegs(pVCpu, pVmcbNstGst);
2685	hmR0SvmExportGuestMsrs(pVCpu, pVmcbNstGst);
2686	hmR0SvmExportGuestHwvirtStateNested(pVCpu, pVmcbNstGst);
2687
2688	ASMSetFlags(fEFlags);
2689
2690	/* Nested VGIF not supported yet. */
2691	Assert(!pVmcbNstGst->ctrl.IntCtrl.n.u1VGifEnable);
2692
2693	rc = hmR0SvmSelectVMRunHandler(pVCpu);
2694	AssertRCReturn(rc, rc);
2695
2696	/* Clear any bits that may be set but exported unconditionally or unused/reserved bits. */
2697	ASMAtomicUoAndU64(&pVCpu->hm.s.fCtxChanged, ~( HM_CHANGED_GUEST_RIP
2698	\| HM_CHANGED_GUEST_RFLAGS
2699	\| HM_CHANGED_GUEST_GPRS_MASK
2700	\| HM_CHANGED_GUEST_APIC_TPR
2701	\| HM_CHANGED_GUEST_X87
2702	\| HM_CHANGED_GUEST_SSE_AVX
2703	\| HM_CHANGED_GUEST_OTHER_XSAVE
2704	\| HM_CHANGED_GUEST_XCRx
2705	\| HM_CHANGED_GUEST_TSC_AUX
2706	\| HM_CHANGED_GUEST_OTHER_MSRS
2707	\| HM_CHANGED_SVM_GUEST_XCPT_INTERCEPTS
2708	\| (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_SVM_MASK)));
2709
2710	#ifdef VBOX_STRICT
2711	/*
2712	* All of the guest-CPU state and SVM keeper bits should be exported here by now, except
2713	* for the host-context and/or shared host-guest context bits.
2714	*/
2715	uint64_t const fCtxChanged = ASMAtomicUoReadU64(&pVCpu->hm.s.fCtxChanged);
2716	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
2717	AssertMsg(!(fCtxChanged & (HM_CHANGED_ALL_GUEST & ~HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)),
2718	("fCtxChanged=%#RX64\n", fCtxChanged));
2719
2720	/*
2721	* If we need to log state that isn't always imported, we'll need to import them here.
2722	* See hmR0SvmPostRunGuest() for which part of the state is imported uncondtionally.
2723	*/
2724	hmR0SvmLogState(pVCpu, pVmcbNstGst, "hmR0SvmExportGuestStateNested", 0 /* fFlags /, 0 / uVerbose */);
2725	#endif
2726
2727	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExportGuestState, x);
2728	return rc;
2729	}
2730	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
2731
2732
2733	/**
2734	* Exports the state shared between the host and guest (or nested-guest) into
2735	* the VMCB.
2736	*
2737	* @param pVCpu The cross context virtual CPU structure.
2738	* @param pVmcb Pointer to the VM control block.
2739	*
2740	* @remarks No-long-jump zone!!!
2741	*/
2742	static void hmR0SvmExportSharedState(PVMCPU pVCpu, PSVMVMCB pVmcb)
2743	{
2744	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
2745	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
2746
2747	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_GUEST_DR_MASK)
2748	{
2749	/** @todo Figure out stepping with nested-guest. */
2750	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2751	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
2752	hmR0SvmExportSharedDebugState(pVCpu, pVmcb);
2753	else
2754	{
2755	pVmcb->guest.u64DR6 = pCtx->dr[6];
2756	pVmcb->guest.u64DR7 = pCtx->dr[7];
2757	}
2758	}
2759
2760	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_GUEST_DR_MASK;
2761	AssertMsg(!(pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE),
2762	("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
2763	}
2764
2765
2766	/**
2767	* Worker for SVMR0ImportStateOnDemand.
2768	*
2769	* @param pVCpu The cross context virtual CPU structure.
2770	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2771	*/
2772	static void hmR0SvmImportGuestState(PVMCPU pVCpu, uint64_t fWhat)
2773	{
2774	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatImportGuestState, x);
2775
2776	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2777	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
2778	PCSVMVMCBSTATESAVE pVmcbGuest = &pVmcb->guest;
2779	PCSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
2780
2781	Log4Func(("fExtrn=%#RX64 fWhat=%#RX64\n", pCtx->fExtrn, fWhat));
2782
2783	/*
2784	* We disable interrupts to make the updating of the state and in particular
2785	* the fExtrn modification atomic wrt to preemption hooks.
2786	*/
2787	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
2788
2789	fWhat &= pCtx->fExtrn;
2790	if (fWhat)
2791	{
2792	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2793	if (fWhat & CPUMCTX_EXTRN_HWVIRT)
2794	{
2795	if ( !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
2796	&& pVmcbCtrl->IntCtrl.n.u1VGifEnable)
2797	{
2798	/* We don't yet support passing VGIF feature to the guest. */
2799	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fVGif);
2800	pCtx->hwvirt.fGif = pVmcbCtrl->IntCtrl.n.u1VGif;
2801	}
2802	}
2803
2804	if (fWhat & CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ)
2805	{
2806	if ( !pVmcbCtrl->IntCtrl.n.u1VIrqPending
2807	&& VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
2808	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
2809	}
2810	#endif
2811
2812	if (fWhat & CPUMCTX_EXTRN_HM_SVM_INT_SHADOW)
2813	{
2814	if (pVmcbCtrl->IntShadow.n.u1IntShadow)
2815	EMSetInhibitInterruptsPC(pVCpu, pVmcbGuest->u64RIP);
2816	else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2817	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2818	}
2819
2820	if (fWhat & CPUMCTX_EXTRN_RIP)
2821	pCtx->rip = pVmcbGuest->u64RIP;
2822
2823	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
2824	pCtx->eflags.u32 = pVmcbGuest->u64RFlags;
2825
2826	if (fWhat & CPUMCTX_EXTRN_RSP)
2827	pCtx->rsp = pVmcbGuest->u64RSP;
2828
2829	if (fWhat & CPUMCTX_EXTRN_RAX)
2830	pCtx->rax = pVmcbGuest->u64RAX;
2831
2832	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
2833	{
2834	if (fWhat & CPUMCTX_EXTRN_CS)
2835	{
2836	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, CS, cs);
2837	/* Correct the CS granularity bit. Haven't seen it being wrong in any other register (yet). */
2838	/** @todo SELM might need to be fixed as it too should not care about the
2839	* granularity bit. See @bugref{6785}. */
2840	if ( !pCtx->cs.Attr.n.u1Granularity
2841	&& pCtx->cs.Attr.n.u1Present
2842	&& pCtx->cs.u32Limit > UINT32_C(0xfffff))
2843	{
2844	Assert((pCtx->cs.u32Limit & 0xfff) == 0xfff);
2845	pCtx->cs.Attr.n.u1Granularity = 1;
2846	}
2847	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, cs);
2848	}
2849	if (fWhat & CPUMCTX_EXTRN_SS)
2850	{
2851	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, SS, ss);
2852	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, ss);
2853	/*
2854	* Sync the hidden SS DPL field. AMD CPUs have a separate CPL field in the
2855	* VMCB and uses that and thus it's possible that when the CPL changes during
2856	* guest execution that the SS DPL isn't updated by AMD-V. Observed on some
2857	* AMD Fusion CPUs with 64-bit guests.
2858	*
2859	* See AMD spec. 15.5.1 "Basic operation".
2860	*/
2861	Assert(!(pVmcbGuest->u8CPL & ~0x3));
2862	uint8_t const uCpl = pVmcbGuest->u8CPL;
2863	if (pCtx->ss.Attr.n.u2Dpl != uCpl)
2864	pCtx->ss.Attr.n.u2Dpl = uCpl & 0x3;
2865	}
2866	if (fWhat & CPUMCTX_EXTRN_DS)
2867	{
2868	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, DS, ds);
2869	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, ds);
2870	}
2871	if (fWhat & CPUMCTX_EXTRN_ES)
2872	{
2873	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, ES, es);
2874	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, es);
2875	}
2876	if (fWhat & CPUMCTX_EXTRN_FS)
2877	{
2878	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, FS, fs);
2879	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, fs);
2880	}
2881	if (fWhat & CPUMCTX_EXTRN_GS)
2882	{
2883	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, GS, gs);
2884	HMSVM_ASSERT_SEG_GRANULARITY(pCtx, gs);
2885	}
2886	}
2887
2888	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
2889	{
2890	if (fWhat & CPUMCTX_EXTRN_TR)
2891	{
2892	/*
2893	* Fixup TR attributes so it's compatible with Intel. Important when saved-states
2894	* are used between Intel and AMD, see @bugref{6208#c39}.
2895	* ASSUME that it's normally correct and that we're in 32-bit or 64-bit mode.
2896	*/
2897	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, TR, tr);
2898	if (pCtx->tr.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2899	{
2900	if ( pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
2901	\|\| CPUMIsGuestInLongModeEx(pCtx))
2902	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
2903	else if (pCtx->tr.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_AVAIL)
2904	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
2905	}
2906	}
2907
2908	if (fWhat & CPUMCTX_EXTRN_LDTR)
2909	HMSVM_SEG_REG_COPY_FROM_VMCB(pCtx, pVmcbGuest, LDTR, ldtr);
2910
2911	if (fWhat & CPUMCTX_EXTRN_GDTR)
2912	{
2913	pCtx->gdtr.cbGdt = pVmcbGuest->GDTR.u32Limit;
2914	pCtx->gdtr.pGdt = pVmcbGuest->GDTR.u64Base;
2915	}
2916
2917	if (fWhat & CPUMCTX_EXTRN_IDTR)
2918	{
2919	pCtx->idtr.cbIdt = pVmcbGuest->IDTR.u32Limit;
2920	pCtx->idtr.pIdt = pVmcbGuest->IDTR.u64Base;
2921	}
2922	}
2923
2924	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
2925	{
2926	pCtx->msrSTAR = pVmcbGuest->u64STAR;
2927	pCtx->msrLSTAR = pVmcbGuest->u64LSTAR;
2928	pCtx->msrCSTAR = pVmcbGuest->u64CSTAR;
2929	pCtx->msrSFMASK = pVmcbGuest->u64SFMASK;
2930	}
2931
2932	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
2933	{
2934	pCtx->SysEnter.cs = pVmcbGuest->u64SysEnterCS;
2935	pCtx->SysEnter.eip = pVmcbGuest->u64SysEnterEIP;
2936	pCtx->SysEnter.esp = pVmcbGuest->u64SysEnterESP;
2937	}
2938
2939	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
2940	pCtx->msrKERNELGSBASE = pVmcbGuest->u64KernelGSBase;
2941
2942	if (fWhat & CPUMCTX_EXTRN_DR_MASK)
2943	{
2944	if (fWhat & CPUMCTX_EXTRN_DR6)
2945	{
2946	if (!pVCpu->hm.s.fUsingHyperDR7)
2947	pCtx->dr[6] = pVmcbGuest->u64DR6;
2948	else
2949	CPUMSetHyperDR6(pVCpu, pVmcbGuest->u64DR6);
2950	}
2951
2952	if (fWhat & CPUMCTX_EXTRN_DR7)
2953	{
2954	if (!pVCpu->hm.s.fUsingHyperDR7)
2955	pCtx->dr[7] = pVmcbGuest->u64DR7;
2956	else
2957	Assert(pVmcbGuest->u64DR7 == CPUMGetHyperDR7(pVCpu));
2958	}
2959	}
2960
2961	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
2962	{
2963	if (fWhat & CPUMCTX_EXTRN_CR0)
2964	{
2965	/* We intercept changes to all CR0 bits except maybe TS & MP bits. */
2966	uint64_t const uCr0 = (pCtx->cr0 & ~(X86_CR0_TS \| X86_CR0_MP))
2967	\| (pVmcbGuest->u64CR0 & (X86_CR0_TS \| X86_CR0_MP));
2968	VMMRZCallRing3Disable(pVCpu); /* Calls into PGM which has Log statements. */
2969	CPUMSetGuestCR0(pVCpu, uCr0);
2970	VMMRZCallRing3Enable(pVCpu);
2971	}
2972
2973	if (fWhat & CPUMCTX_EXTRN_CR2)
2974	pCtx->cr2 = pVmcbGuest->u64CR2;
2975
2976	if (fWhat & CPUMCTX_EXTRN_CR3)
2977	{
2978	if ( pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging
2979	&& pCtx->cr3 != pVmcbGuest->u64CR3)
2980	{
2981	CPUMSetGuestCR3(pVCpu, pVmcbGuest->u64CR3);
2982	VMCPU_FF_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3);
2983	}
2984	}
2985
2986	/* Changes to CR4 are always intercepted. */
2987	}
2988
2989	/* Update fExtrn. */
2990	pCtx->fExtrn &= ~fWhat;
2991
2992	/* If everything has been imported, clear the HM keeper bit. */
2993	if (!(pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL))
2994	{
2995	pCtx->fExtrn &= ~CPUMCTX_EXTRN_KEEPER_HM;
2996	Assert(!pCtx->fExtrn);
2997	}
2998	}
2999	else
3000	Assert(!pCtx->fExtrn \|\| (pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
3001
3002	ASMSetFlags(fEFlags);
3003
3004	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatImportGuestState, x);
3005
3006	/*
3007	* Honor any pending CR3 updates.
3008	*
3009	* Consider this scenario: #VMEXIT -> VMMRZCallRing3Enable() -> do stuff that causes a longjmp
3010	* -> hmR0SvmCallRing3Callback() -> VMMRZCallRing3Disable() -> hmR0SvmImportGuestState()
3011	* -> Sets VMCPU_FF_HM_UPDATE_CR3 pending -> return from the longjmp -> continue with #VMEXIT
3012	* handling -> hmR0SvmImportGuestState() and here we are.
3013	*
3014	* The reason for such complicated handling is because VM-exits that call into PGM expect
3015	* CR3 to be up-to-date and thus any CR3-saves -before- the VM-exit (longjmp) would've
3016	* postponed the CR3 update via the force-flag and cleared CR3 from fExtrn. Any SVM R0
3017	* VM-exit handler that requests CR3 to be saved will end up here and we call PGMUpdateCR3().
3018	*
3019	* The longjmp exit path can't check these CR3 force-flags and call code that takes a lock again,
3020	* and does not process force-flag like regular exits to ring-3 either, we cover for it here.
3021	*/
3022	if ( VMMRZCallRing3IsEnabled(pVCpu)
3023	&& VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
3024	{
3025	Assert(pCtx->cr3 == pVmcbGuest->u64CR3);
3026	PGMUpdateCR3(pVCpu, pCtx->cr3);
3027	}
3028	}
3029
3030
3031	/**
3032	* Saves the guest (or nested-guest) state from the VMCB into the guest-CPU
3033	* context.
3034	*
3035	* Currently there is no residual state left in the CPU that is not updated in the
3036	* VMCB.
3037	*
3038	* @returns VBox status code.
3039	* @param pVCpu The cross context virtual CPU structure.
3040	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
3041	*/
3042	VMMR0DECL(int) SVMR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat)
3043	{
3044	hmR0SvmImportGuestState(pVCpu, fWhat);
3045	return VINF_SUCCESS;
3046	}
3047
3048
3049	/**
3050	* Does the necessary state syncing before returning to ring-3 for any reason
3051	* (longjmp, preemption, voluntary exits to ring-3) from AMD-V.
3052	*
3053	* @param pVCpu The cross context virtual CPU structure.
3054	* @param fImportState Whether to import the guest state from the VMCB back
3055	* to the guest-CPU context.
3056	*
3057	* @remarks No-long-jmp zone!!!
3058	*/
3059	static void hmR0SvmLeave(PVMCPU pVCpu, bool fImportState)
3060	{
3061	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3062	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3063	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3064
3065	/*
3066	* !!! IMPORTANT !!!
3067	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
3068	*/
3069
3070	/* Save the guest state if necessary. */
3071	if (fImportState)
3072	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3073
3074	/* Restore host FPU state if necessary and resync on next R0 reentry. */
3075	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
3076	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
3077
3078	/*
3079	* Restore host debug registers if necessary and resync on next R0 reentry.
3080	*/
3081	#ifdef VBOX_STRICT
3082	if (CPUMIsHyperDebugStateActive(pVCpu))
3083	{
3084	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb; /** @todo nested-guest. */
3085	Assert(pVmcb->ctrl.u16InterceptRdDRx == 0xffff);
3086	Assert(pVmcb->ctrl.u16InterceptWrDRx == 0xffff);
3087	}
3088	#endif
3089	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
3090	Assert(!CPUMIsHyperDebugStateActive(pVCpu));
3091	Assert(!CPUMIsGuestDebugStateActive(pVCpu));
3092
3093	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatEntry);
3094	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatImportGuestState);
3095	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExportGuestState);
3096	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatPreExit);
3097	STAM_PROFILE_ADV_SET_STOPPED(&pVCpu->hm.s.StatExitHandling);
3098	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
3099
3100	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_HM, VMCPUSTATE_STARTED_EXEC);
3101	}
3102
3103
3104	/**
3105	* Leaves the AMD-V session.
3106	*
3107	* Only used while returning to ring-3 either due to longjump or exits to
3108	* ring-3.
3109	*
3110	* @returns VBox status code.
3111	* @param pVCpu The cross context virtual CPU structure.
3112	*/
3113	static int hmR0SvmLeaveSession(PVMCPU pVCpu)
3114	{
3115	HM_DISABLE_PREEMPT(pVCpu);
3116	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3117	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
3118
3119	/* When thread-context hooks are used, we can avoid doing the leave again if we had been preempted before
3120	and done this from the SVMR0ThreadCtxCallback(). */
3121	if (!pVCpu->hm.s.fLeaveDone)
3122	{
3123	hmR0SvmLeave(pVCpu, true /* fImportState */);
3124	pVCpu->hm.s.fLeaveDone = true;
3125	}
3126
3127	/*
3128	* !!! IMPORTANT !!!
3129	* If you modify code here, make sure to check whether hmR0SvmCallRing3Callback() needs to be updated too.
3130	*/
3131
3132	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
3133	/* Deregister hook now that we've left HM context before re-enabling preemption. */
3134	VMMR0ThreadCtxHookDisable(pVCpu);
3135
3136	/* Leave HM context. This takes care of local init (term). */
3137	int rc = HMR0LeaveCpu(pVCpu);
3138
3139	HM_RESTORE_PREEMPT();
3140	return rc;
3141	}
3142
3143
3144	/**
3145	* Does the necessary state syncing before doing a longjmp to ring-3.
3146	*
3147	* @returns VBox status code.
3148	* @param pVCpu The cross context virtual CPU structure.
3149	*
3150	* @remarks No-long-jmp zone!!!
3151	*/
3152	static int hmR0SvmLongJmpToRing3(PVMCPU pVCpu)
3153	{
3154	return hmR0SvmLeaveSession(pVCpu);
3155	}
3156
3157
3158	/**
3159	* VMMRZCallRing3() callback wrapper which saves the guest state (or restores
3160	* any remaining host state) before we longjump to ring-3 and possibly get
3161	* preempted.
3162	*
3163	* @param pVCpu The cross context virtual CPU structure.
3164	* @param enmOperation The operation causing the ring-3 longjump.
3165	* @param pvUser The user argument, NULL (currently unused).
3166	*/
3167	static DECLCALLBACK(int) hmR0SvmCallRing3Callback(PVMCPU pVCpu, VMMCALLRING3 enmOperation, void *pvUser)
3168	{
3169	RT_NOREF_PV(pvUser);
3170
3171	if (enmOperation == VMMCALLRING3_VM_R0_ASSERTION)
3172	{
3173	/*
3174	* !!! IMPORTANT !!!
3175	* If you modify code here, make sure to check whether hmR0SvmLeave() and hmR0SvmLeaveSession() needs
3176	* to be updated too. This is a stripped down version which gets out ASAP trying to not trigger any assertion.
3177	*/
3178	VMMRZCallRing3RemoveNotification(pVCpu);
3179	VMMRZCallRing3Disable(pVCpu);
3180	HM_DISABLE_PREEMPT(pVCpu);
3181
3182	/* Import the entire guest state. */
3183	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3184
3185	/* Restore host FPU state if necessary and resync on next R0 reentry. */
3186	CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(pVCpu);
3187
3188	/* Restore host debug registers if necessary and resync on next R0 reentry. */
3189	CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, false /* save DR6 */);
3190
3191	/* Deregister the hook now that we've left HM context before re-enabling preemption. */
3192	/** @todo eliminate the need for calling VMMR0ThreadCtxHookDisable here! */
3193	VMMR0ThreadCtxHookDisable(pVCpu);
3194
3195	/* Leave HM context. This takes care of local init (term). */
3196	HMR0LeaveCpu(pVCpu);
3197
3198	HM_RESTORE_PREEMPT();
3199	return VINF_SUCCESS;
3200	}
3201
3202	Assert(pVCpu);
3203	Assert(VMMRZCallRing3IsEnabled(pVCpu));
3204	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3205
3206	VMMRZCallRing3Disable(pVCpu);
3207	Assert(VMMR0IsLogFlushDisabled(pVCpu));
3208
3209	Log4Func(("Calling hmR0SvmLongJmpToRing3\n"));
3210	int rc = hmR0SvmLongJmpToRing3(pVCpu);
3211	AssertRCReturn(rc, rc);
3212
3213	VMMRZCallRing3Enable(pVCpu);
3214	return VINF_SUCCESS;
3215	}
3216
3217
3218	/**
3219	* Take necessary actions before going back to ring-3.
3220	*
3221	* An action requires us to go back to ring-3. This function does the necessary
3222	* steps before we can safely return to ring-3. This is not the same as longjmps
3223	* to ring-3, this is voluntary.
3224	*
3225	* @returns VBox status code.
3226	* @param pVCpu The cross context virtual CPU structure.
3227	* @param rcExit The reason for exiting to ring-3. Can be
3228	* VINF_VMM_UNKNOWN_RING3_CALL.
3229	*/
3230	static int hmR0SvmExitToRing3(PVMCPU pVCpu, int rcExit)
3231	{
3232	Assert(pVCpu);
3233	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
3234
3235	/* Please, no longjumps here (any logging shouldn't flush jump back to ring-3). NO LOGGING BEFORE THIS POINT! */
3236	VMMRZCallRing3Disable(pVCpu);
3237	Log4Func(("rcExit=%d LocalFF=%#RX32 GlobalFF=%#RX32\n", rcExit, pVCpu->fLocalForcedActions,
3238	pVCpu->CTX_SUFF(pVM)->fGlobalForcedActions));
3239
3240	/* We need to do this only while truly exiting the "inner loop" back to ring-3 and -not- for any longjmp to ring3. */
3241	if (pVCpu->hm.s.Event.fPending)
3242	{
3243	hmR0SvmPendingEventToTrpmTrap(pVCpu);
3244	Assert(!pVCpu->hm.s.Event.fPending);
3245	}
3246
3247	/* Sync. the necessary state for going back to ring-3. */
3248	hmR0SvmLeaveSession(pVCpu);
3249	STAM_COUNTER_DEC(&pVCpu->hm.s.StatSwitchLongJmpToR3);
3250
3251	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
3252	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_SYSENTER_MSR
3253	\| CPUM_CHANGED_LDTR
3254	\| CPUM_CHANGED_GDTR
3255	\| CPUM_CHANGED_IDTR
3256	\| CPUM_CHANGED_TR
3257	\| CPUM_CHANGED_HIDDEN_SEL_REGS);
3258	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging
3259	&& CPUMIsGuestPagingEnabledEx(&pVCpu->cpum.GstCtx))
3260	{
3261	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
3262	}
3263
3264	/* Update the exit-to-ring 3 reason. */
3265	pVCpu->hm.s.rcLastExitToR3 = rcExit;
3266
3267	/* On our way back from ring-3, reload the guest-CPU state if it may change while in ring-3. */
3268	if ( rcExit != VINF_EM_RAW_INTERRUPT
3269	\|\| CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
3270	{
3271	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
3272	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
3273	}
3274
3275	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchExitToR3);
3276
3277	/* We do -not- want any longjmp notifications after this! We must return to ring-3 ASAP. */
3278	VMMRZCallRing3RemoveNotification(pVCpu);
3279	VMMRZCallRing3Enable(pVCpu);
3280
3281	/*
3282	* If we're emulating an instruction, we shouldn't have any TRPM traps pending
3283	* and if we're injecting an event we should have a TRPM trap pending.
3284	*/
3285	AssertReturnStmt(rcExit != VINF_EM_RAW_INJECT_TRPM_EVENT \|\| TRPMHasTrap(pVCpu),
3286	pVCpu->hm.s.u32HMError = rcExit,
3287	VERR_SVM_IPE_5);
3288	AssertReturnStmt(rcExit != VINF_EM_RAW_EMULATE_INSTR \|\| !TRPMHasTrap(pVCpu),
3289	pVCpu->hm.s.u32HMError = rcExit,
3290	VERR_SVM_IPE_4);
3291
3292	return rcExit;
3293	}
3294
3295
3296	/**
3297	* Updates the use of TSC offsetting mode for the CPU and adjusts the necessary
3298	* intercepts.
3299	*
3300	* @param pVCpu The cross context virtual CPU structure.
3301	* @param pVmcb Pointer to the VM control block.
3302	*
3303	* @remarks No-long-jump zone!!!
3304	*/
3305	static void hmR0SvmUpdateTscOffsetting(PVMCPU pVCpu, PSVMVMCB pVmcb)
3306	{
3307	/*
3308	* Avoid intercepting RDTSC/RDTSCP if we determined the host TSC (++) is stable
3309	* and in case of a nested-guest, if the nested-VMCB specifies it is not intercepting
3310	* RDTSC/RDTSCP as well.
3311	*/
3312	bool fParavirtTsc;
3313	uint64_t uTscOffset;
3314	bool const fCanUseRealTsc = TMCpuTickCanUseRealTSC(pVCpu->CTX_SUFF(pVM), pVCpu, &uTscOffset, &fParavirtTsc);
3315
3316	bool fIntercept;
3317	if (fCanUseRealTsc)
3318	fIntercept = hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3319	else
3320	{
3321	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_RDTSC \| SVM_CTRL_INTERCEPT_RDTSCP);
3322	fIntercept = true;
3323	}
3324
3325	if (!fIntercept)
3326	{
3327	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3328	/* Apply the nested-guest VMCB's TSC offset over the guest TSC offset. */
3329	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
3330	uTscOffset = HMSvmNstGstApplyTscOffset(pVCpu, uTscOffset);
3331	#endif
3332
3333	/* Update the TSC offset in the VMCB and the relevant clean bits. */
3334	pVmcb->ctrl.u64TSCOffset = uTscOffset;
3335	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
3336
3337	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscOffset);
3338	}
3339	else
3340	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscIntercept);
3341
3342	/* Currently neither Hyper-V nor KVM need to update their paravirt. TSC
3343	information before every VM-entry, hence we have nothing to do here at the moment. */
3344	if (fParavirtTsc)
3345	STAM_COUNTER_INC(&pVCpu->hm.s.StatTscParavirt);
3346	}
3347
3348
3349	/**
3350	* Sets an event as a pending event to be injected into the guest.
3351	*
3352	* @param pVCpu The cross context virtual CPU structure.
3353	* @param pEvent Pointer to the SVM event.
3354	* @param GCPtrFaultAddress The fault-address (CR2) in case it's a
3355	* page-fault.
3356	*
3357	* @remarks Statistics counter assumes this is a guest event being reflected to
3358	* the guest i.e. 'StatInjectPendingReflect' is incremented always.
3359	*/
3360	DECLINLINE(void) hmR0SvmSetPendingEvent(PVMCPU pVCpu, PSVMEVENT pEvent, RTGCUINTPTR GCPtrFaultAddress)
3361	{
3362	Assert(!pVCpu->hm.s.Event.fPending);
3363	Assert(pEvent->n.u1Valid);
3364
3365	pVCpu->hm.s.Event.u64IntInfo = pEvent->u;
3366	pVCpu->hm.s.Event.fPending = true;
3367	pVCpu->hm.s.Event.GCPtrFaultAddress = GCPtrFaultAddress;
3368
3369	Log4Func(("u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, pEvent->n.u8Vector,
3370	(uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3371	}
3372
3373
3374	/**
3375	* Sets an invalid-opcode (\#UD) exception as pending-for-injection into the VM.
3376	*
3377	* @param pVCpu The cross context virtual CPU structure.
3378	*/
3379	DECLINLINE(void) hmR0SvmSetPendingXcptUD(PVMCPU pVCpu)
3380	{
3381	SVMEVENT Event;
3382	Event.u = 0;
3383	Event.n.u1Valid = 1;
3384	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3385	Event.n.u8Vector = X86_XCPT_UD;
3386	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3387	}
3388
3389
3390	/**
3391	* Sets a debug (\#DB) exception as pending-for-injection into the VM.
3392	*
3393	* @param pVCpu The cross context virtual CPU structure.
3394	*/
3395	DECLINLINE(void) hmR0SvmSetPendingXcptDB(PVMCPU pVCpu)
3396	{
3397	SVMEVENT Event;
3398	Event.u = 0;
3399	Event.n.u1Valid = 1;
3400	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3401	Event.n.u8Vector = X86_XCPT_DB;
3402	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3403	}
3404
3405
3406	/**
3407	* Sets a page fault (\#PF) exception as pending-for-injection into the VM.
3408	*
3409	* @param pVCpu The cross context virtual CPU structure.
3410	* @param u32ErrCode The error-code for the page-fault.
3411	* @param uFaultAddress The page fault address (CR2).
3412	*
3413	* @remarks This updates the guest CR2 with @a uFaultAddress!
3414	*/
3415	DECLINLINE(void) hmR0SvmSetPendingXcptPF(PVMCPU pVCpu, uint32_t u32ErrCode, RTGCUINTPTR uFaultAddress)
3416	{
3417	SVMEVENT Event;
3418	Event.u = 0;
3419	Event.n.u1Valid = 1;
3420	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3421	Event.n.u8Vector = X86_XCPT_PF;
3422	Event.n.u1ErrorCodeValid = 1;
3423	Event.n.u32ErrorCode = u32ErrCode;
3424
3425	/* Update CR2 of the guest. */
3426	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR2);
3427	if (pVCpu->cpum.GstCtx.cr2 != uFaultAddress)
3428	{
3429	pVCpu->cpum.GstCtx.cr2 = uFaultAddress;
3430	/* The VMCB clean bit for CR2 will be updated while re-loading the guest state. */
3431	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR2);
3432	}
3433
3434	hmR0SvmSetPendingEvent(pVCpu, &Event, uFaultAddress);
3435	}
3436
3437
3438	/**
3439	* Sets a math-fault (\#MF) exception as pending-for-injection into the VM.
3440	*
3441	* @param pVCpu The cross context virtual CPU structure.
3442	*/
3443	DECLINLINE(void) hmR0SvmSetPendingXcptMF(PVMCPU pVCpu)
3444	{
3445	SVMEVENT Event;
3446	Event.u = 0;
3447	Event.n.u1Valid = 1;
3448	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3449	Event.n.u8Vector = X86_XCPT_MF;
3450	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3451	}
3452
3453
3454	/**
3455	* Sets a double fault (\#DF) exception as pending-for-injection into the VM.
3456	*
3457	* @param pVCpu The cross context virtual CPU structure.
3458	*/
3459	DECLINLINE(void) hmR0SvmSetPendingXcptDF(PVMCPU pVCpu)
3460	{
3461	SVMEVENT Event;
3462	Event.u = 0;
3463	Event.n.u1Valid = 1;
3464	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3465	Event.n.u8Vector = X86_XCPT_DF;
3466	Event.n.u1ErrorCodeValid = 1;
3467	Event.n.u32ErrorCode = 0;
3468	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3469	}
3470
3471
3472	/**
3473	* Injects an event into the guest upon VMRUN by updating the relevant field
3474	* in the VMCB.
3475	*
3476	* @param pVCpu The cross context virtual CPU structure.
3477	* @param pVmcb Pointer to the guest VM control block.
3478	* @param pEvent Pointer to the event.
3479	*
3480	* @remarks No-long-jump zone!!!
3481	* @remarks Requires CR0!
3482	*/
3483	DECLINLINE(void) hmR0SvmInjectEventVmcb(PVMCPU pVCpu, PSVMVMCB pVmcb, PSVMEVENT pEvent)
3484	{
3485	Assert(!pVmcb->ctrl.EventInject.n.u1Valid);
3486	pVmcb->ctrl.EventInject.u = pEvent->u;
3487	STAM_COUNTER_INC(&pVCpu->hm.s.paStatInjectedIrqsR0[pEvent->n.u8Vector & MASK_INJECT_IRQ_STAT]);
3488	RT_NOREF(pVCpu);
3489
3490	Log4Func(("u=%#RX64 u8Vector=%#x Type=%#x ErrorCodeValid=%RTbool ErrorCode=%#RX32\n", pEvent->u, pEvent->n.u8Vector,
3491	(uint8_t)pEvent->n.u3Type, !!pEvent->n.u1ErrorCodeValid, pEvent->n.u32ErrorCode));
3492	}
3493
3494
3495
3496	/**
3497	* Converts any TRPM trap into a pending HM event. This is typically used when
3498	* entering from ring-3 (not longjmp returns).
3499	*
3500	* @param pVCpu The cross context virtual CPU structure.
3501	*/
3502	static void hmR0SvmTrpmTrapToPendingEvent(PVMCPU pVCpu)
3503	{
3504	Assert(TRPMHasTrap(pVCpu));
3505	Assert(!pVCpu->hm.s.Event.fPending);
3506
3507	uint8_t uVector;
3508	TRPMEVENT enmTrpmEvent;
3509	RTGCUINT uErrCode;
3510	RTGCUINTPTR GCPtrFaultAddress;
3511	uint8_t cbInstr;
3512
3513	int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrpmEvent, &uErrCode, &GCPtrFaultAddress, &cbInstr);
3514	AssertRC(rc);
3515
3516	SVMEVENT Event;
3517	Event.u = 0;
3518	Event.n.u1Valid = 1;
3519	Event.n.u8Vector = uVector;
3520
3521	/* Refer AMD spec. 15.20 "Event Injection" for the format. */
3522	if (enmTrpmEvent == TRPM_TRAP)
3523	{
3524	Event.n.u3Type = SVM_EVENT_EXCEPTION;
3525	switch (uVector)
3526	{
3527	case X86_XCPT_NMI:
3528	{
3529	Event.n.u3Type = SVM_EVENT_NMI;
3530	break;
3531	}
3532
3533	case X86_XCPT_PF:
3534	case X86_XCPT_DF:
3535	case X86_XCPT_TS:
3536	case X86_XCPT_NP:
3537	case X86_XCPT_SS:
3538	case X86_XCPT_GP:
3539	case X86_XCPT_AC:
3540	{
3541	Event.n.u1ErrorCodeValid = 1;
3542	Event.n.u32ErrorCode = uErrCode;
3543	break;
3544	}
3545	}
3546	}
3547	else if (enmTrpmEvent == TRPM_HARDWARE_INT)
3548	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3549	else if (enmTrpmEvent == TRPM_SOFTWARE_INT)
3550	Event.n.u3Type = SVM_EVENT_SOFTWARE_INT;
3551	else
3552	AssertMsgFailed(("Invalid TRPM event type %d\n", enmTrpmEvent));
3553
3554	rc = TRPMResetTrap(pVCpu);
3555	AssertRC(rc);
3556
3557	Log4(("TRPM->HM event: u=%#RX64 u8Vector=%#x uErrorCodeValid=%RTbool uErrorCode=%#RX32\n", Event.u, Event.n.u8Vector,
3558	!!Event.n.u1ErrorCodeValid, Event.n.u32ErrorCode));
3559
3560	hmR0SvmSetPendingEvent(pVCpu, &Event, GCPtrFaultAddress);
3561	}
3562
3563
3564	/**
3565	* Converts any pending SVM event into a TRPM trap. Typically used when leaving
3566	* AMD-V to execute any instruction.
3567	*
3568	* @param pVCpu The cross context virtual CPU structure.
3569	*/
3570	static void hmR0SvmPendingEventToTrpmTrap(PVMCPU pVCpu)
3571	{
3572	Assert(pVCpu->hm.s.Event.fPending);
3573	Assert(TRPMQueryTrap(pVCpu, NULL /* pu8TrapNo /, NULL / pEnmType */) == VERR_TRPM_NO_ACTIVE_TRAP);
3574
3575	SVMEVENT Event;
3576	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3577
3578	uint8_t uVector = Event.n.u8Vector;
3579	uint8_t uVectorType = Event.n.u3Type;
3580	TRPMEVENT enmTrapType = HMSvmEventToTrpmEventType(&Event);
3581
3582	Log4(("HM event->TRPM: uVector=%#x enmTrapType=%d\n", uVector, uVectorType));
3583
3584	int rc = TRPMAssertTrap(pVCpu, uVector, enmTrapType);
3585	AssertRC(rc);
3586
3587	if (Event.n.u1ErrorCodeValid)
3588	TRPMSetErrorCode(pVCpu, Event.n.u32ErrorCode);
3589
3590	if ( uVectorType == SVM_EVENT_EXCEPTION
3591	&& uVector == X86_XCPT_PF)
3592	{
3593	TRPMSetFaultAddress(pVCpu, pVCpu->hm.s.Event.GCPtrFaultAddress);
3594	Assert(pVCpu->hm.s.Event.GCPtrFaultAddress == CPUMGetGuestCR2(pVCpu));
3595	}
3596	else if (uVectorType == SVM_EVENT_SOFTWARE_INT)
3597	{
3598	AssertMsg( uVectorType == SVM_EVENT_SOFTWARE_INT
3599	\|\| (uVector == X86_XCPT_BP \|\| uVector == X86_XCPT_OF),
3600	("Invalid vector: uVector=%#x uVectorType=%#x\n", uVector, uVectorType));
3601	TRPMSetInstrLength(pVCpu, pVCpu->hm.s.Event.cbInstr);
3602	}
3603	pVCpu->hm.s.Event.fPending = false;
3604	}
3605
3606
3607	/**
3608	* Checks if the guest (or nested-guest) has an interrupt shadow active right
3609	* now.
3610	*
3611	* @returns @c true if the interrupt shadow is active, @c false otherwise.
3612	* @param pVCpu The cross context virtual CPU structure.
3613	*
3614	* @remarks No-long-jump zone!!!
3615	* @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
3616	*/
3617	static bool hmR0SvmIsIntrShadowActive(PVMCPU pVCpu)
3618	{
3619	/*
3620	* Instructions like STI and MOV SS inhibit interrupts till the next instruction
3621	* completes. Check if we should inhibit interrupts or clear any existing
3622	* interrupt inhibition.
3623	*/
3624	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
3625	{
3626	if (pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
3627	{
3628	/*
3629	* We can clear the inhibit force flag as even if we go back to the recompiler
3630	* without executing guest code in AMD-V, the flag's condition to be cleared is
3631	* met and thus the cleared state is correct.
3632	*/
3633	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
3634	return false;
3635	}
3636	return true;
3637	}
3638	return false;
3639	}
3640
3641
3642	/**
3643	* Sets the virtual interrupt intercept control in the VMCB.
3644	*
3645	* @param pVCpu The cross context virtual CPU structure.
3646	* @param pVmcb Pointer to the VM control block.
3647	*/
3648	static void hmR0SvmSetIntWindowExiting(PVMCPU pVCpu, PSVMVMCB pVmcb)
3649	{
3650	/*
3651	* When AVIC isn't supported, set up an interrupt window to cause a #VMEXIT when the guest
3652	* is ready to accept interrupts. At #VMEXIT, we then get the interrupt from the APIC
3653	* (updating ISR at the right time) and inject the interrupt.
3654	*
3655	* With AVIC is supported, we could make use of the asynchronously delivery without
3656	* #VMEXIT and we would be passing the AVIC page to SVM.
3657	*
3658	* In AMD-V, an interrupt window is achieved using a combination of V_IRQ (an interrupt
3659	* is pending), V_IGN_TPR (ignore TPR priorities) and the VINTR intercept all being set.
3660	*/
3661	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3662	/*
3663	* Currently we don't overlay interupt windows and if there's any V_IRQ pending in the
3664	* nested-guest VMCB, we avoid setting up any interrupt window on behalf of the outer
3665	* guest.
3666	*/
3667	/** @todo Does this mean we end up prioritizing virtual interrupt
3668	* delivery/window over a physical interrupt (from the outer guest)
3669	* might be pending? */
3670	bool const fEnableIntWindow = !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
3671	if (!fEnableIntWindow)
3672	{
3673	Assert(CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx));
3674	Log4(("Nested-guest V_IRQ already pending\n"));
3675	}
3676	#else
3677	bool const fEnableIntWindow = true;
3678	RT_NOREF(pVCpu);
3679	#endif
3680	if (fEnableIntWindow)
3681	{
3682	Assert(pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR);
3683	pVmcb->ctrl.IntCtrl.n.u1VIrqPending = 1;
3684	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INT_CTRL;
3685	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_VINTR);
3686	Log4(("Set VINTR intercept\n"));
3687	}
3688	}
3689
3690
3691	/**
3692	* Clears the virtual interrupt intercept control in the VMCB as
3693	* we are figured the guest is unable process any interrupts
3694	* at this point of time.
3695	*
3696	* @param pVCpu The cross context virtual CPU structure.
3697	* @param pVmcb Pointer to the VM control block.
3698	*/
3699	static void hmR0SvmClearIntWindowExiting(PVMCPU pVCpu, PSVMVMCB pVmcb)
3700	{
3701	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
3702	if ( pVmcbCtrl->IntCtrl.n.u1VIrqPending
3703	\|\| (pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_VINTR))
3704	{
3705	pVmcbCtrl->IntCtrl.n.u1VIrqPending = 0;
3706	pVmcbCtrl->u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INT_CTRL;
3707	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_VINTR);
3708	Log4(("Cleared VINTR intercept\n"));
3709	}
3710	}
3711
3712	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3713	/**
3714	* Evaluates the event to be delivered to the nested-guest and sets it as the
3715	* pending event.
3716	*
3717	* @returns VBox strict status code.
3718	* @param pVCpu The cross context virtual CPU structure.
3719	*/
3720	static VBOXSTRICTRC hmR0SvmEvaluatePendingEventNested(PVMCPU pVCpu)
3721	{
3722	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3723	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
3724	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT
3725	\| CPUMCTX_EXTRN_RFLAGS
3726	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW
3727	\| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ);
3728
3729	Assert(!pVCpu->hm.s.Event.fPending);
3730	Assert(pCtx->hwvirt.fGif);
3731	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3732	Assert(pVmcb);
3733
3734	bool const fVirtualGif = CPUMGetSvmNstGstVGif(pCtx);
3735	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3736	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3737
3738	Log4Func(("fVirtualGif=%RTbool fBlockNmi=%RTbool fIntShadow=%RTbool fIntPending=%RTbool fNmiPending=%RTbool\n",
3739	fVirtualGif, fBlockNmi, fIntShadow, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC),
3740	VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)));
3741
3742	/** @todo SMI. SMIs take priority over NMIs. */
3743
3744	/*
3745	* Check if the guest can receive NMIs.
3746	* Nested NMIs are not allowed, see AMD spec. 8.1.4 "Masking External Interrupts".
3747	* NMIs take priority over maskable interrupts, see AMD spec. 8.5 "Priorities".
3748	*/
3749	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)
3750	&& !fBlockNmi)
3751	{
3752	if ( fVirtualGif
3753	&& !fIntShadow)
3754	{
3755	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_NMI))
3756	{
3757	Log4(("Intercepting NMI -> #VMEXIT\n"));
3758	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3759	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_NMI, 0, 0);
3760	}
3761
3762	Log4(("Setting NMI pending for injection\n"));
3763	SVMEVENT Event;
3764	Event.u = 0;
3765	Event.n.u1Valid = 1;
3766	Event.n.u8Vector = X86_XCPT_NMI;
3767	Event.n.u3Type = SVM_EVENT_NMI;
3768	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3769	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3770	}
3771	else if (!fVirtualGif)
3772	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3773	else
3774	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3775	}
3776	/*
3777	* Check if the nested-guest can receive external interrupts (generated by the guest's
3778	* PIC/APIC).
3779	*
3780	* External intercepts, NMI, SMI etc. from the physical CPU are -always- intercepted
3781	* when executing using hardware-assisted SVM, see HMSVM_MANDATORY_GUEST_CTRL_INTERCEPTS.
3782	*
3783	* External interrupts that are generated for the outer guest may be intercepted
3784	* depending on how the nested-guest VMCB was programmed by guest software.
3785	*
3786	* Physical interrupts always take priority over virtual interrupts,
3787	* see AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts".
3788	*/
3789	else if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3790	&& !pVCpu->hm.s.fSingleInstruction)
3791	{
3792	if ( fVirtualGif
3793	&& !fIntShadow
3794	&& CPUMCanSvmNstGstTakePhysIntr(pVCpu, pCtx))
3795	{
3796	if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, pCtx, SVM_CTRL_INTERCEPT_INTR))
3797	{
3798	Log4(("Intercepting INTR -> #VMEXIT\n"));
3799	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
3800	return IEMExecSvmVmexit(pVCpu, SVM_EXIT_INTR, 0, 0);
3801	}
3802
3803	uint8_t u8Interrupt;
3804	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3805	if (RT_SUCCESS(rc))
3806	{
3807	Log4(("Setting external interrupt %#x pending for injection\n", u8Interrupt));
3808	SVMEVENT Event;
3809	Event.u = 0;
3810	Event.n.u1Valid = 1;
3811	Event.n.u8Vector = u8Interrupt;
3812	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3813	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3814	}
3815	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3816	{
3817	/*
3818	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3819	* updated eventually when the TPR is written by the guest.
3820	*/
3821	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3822	}
3823	else
3824	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3825	}
3826	else if (!fVirtualGif)
3827	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3828	else
3829	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3830	}
3831
3832	return VINF_SUCCESS;
3833	}
3834	#endif
3835
3836	/**
3837	* Evaluates the event to be delivered to the guest and sets it as the pending
3838	* event.
3839	*
3840	* @param pVCpu The cross context virtual CPU structure.
3841	*/
3842	static void hmR0SvmEvaluatePendingEvent(PVMCPU pVCpu)
3843	{
3844	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3845	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(pCtx);
3846	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT
3847	\| CPUMCTX_EXTRN_RFLAGS
3848	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW);
3849
3850	Assert(!pVCpu->hm.s.Event.fPending);
3851	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
3852	Assert(pVmcb);
3853
3854	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3855	bool const fGif = pCtx->hwvirt.fGif;
3856	#else
3857	bool const fGif = true;
3858	#endif
3859	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3860	bool const fBlockInt = !(pCtx->eflags.u32 & X86_EFL_IF);
3861	bool const fBlockNmi = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
3862
3863	Log4Func(("fGif=%RTbool fBlockNmi=%RTbool fBlockInt=%RTbool fIntShadow=%RTbool fIntPending=%RTbool NMI pending=%RTbool\n",
3864	fGif, fBlockNmi, fBlockInt, fIntShadow,
3865	VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC),
3866	VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)));
3867
3868	/** @todo SMI. SMIs take priority over NMIs. */
3869
3870	/*
3871	* Check if the guest can receive NMIs.
3872	* Nested NMIs are not allowed, see AMD spec. 8.1.4 "Masking External Interrupts".
3873	* NMIs take priority over maskable interrupts, see AMD spec. 8.5 "Priorities".
3874	*/
3875	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)
3876	&& !fBlockNmi)
3877	{
3878	if ( fGif
3879	&& !fIntShadow)
3880	{
3881	Log4(("Setting NMI pending for injection\n"));
3882	SVMEVENT Event;
3883	Event.u = 0;
3884	Event.n.u1Valid = 1;
3885	Event.n.u8Vector = X86_XCPT_NMI;
3886	Event.n.u3Type = SVM_EVENT_NMI;
3887	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3888	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
3889	}
3890	else if (!fGif)
3891	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3892	else
3893	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3894	}
3895	/*
3896	* Check if the guest can receive external interrupts (PIC/APIC). Once PDMGetInterrupt()
3897	* returns a valid interrupt we -must- deliver the interrupt. We can no longer re-request
3898	* it from the APIC device.
3899	*/
3900	else if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC)
3901	&& !pVCpu->hm.s.fSingleInstruction)
3902	{
3903	if ( fGif
3904	&& !fBlockInt
3905	&& !fIntShadow)
3906	{
3907	uint8_t u8Interrupt;
3908	int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
3909	if (RT_SUCCESS(rc))
3910	{
3911	Log4(("Setting external interrupt %#x pending for injection\n", u8Interrupt));
3912	SVMEVENT Event;
3913	Event.u = 0;
3914	Event.n.u1Valid = 1;
3915	Event.n.u8Vector = u8Interrupt;
3916	Event.n.u3Type = SVM_EVENT_EXTERNAL_IRQ;
3917	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
3918	}
3919	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
3920	{
3921	/*
3922	* AMD-V has no TPR thresholding feature. TPR and the force-flag will be
3923	* updated eventually when the TPR is written by the guest.
3924	*/
3925	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
3926	}
3927	else
3928	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchGuestIrq);
3929	}
3930	else if (!fGif)
3931	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_STGI);
3932	else
3933	hmR0SvmSetIntWindowExiting(pVCpu, pVmcb);
3934	}
3935	}
3936
3937
3938	/**
3939	* Injects any pending events into the guest (or nested-guest).
3940	*
3941	* @param pVCpu The cross context virtual CPU structure.
3942	* @param pVmcb Pointer to the VM control block.
3943	*
3944	* @remarks Must only be called when we are guaranteed to enter
3945	* hardware-assisted SVM execution and not return to ring-3
3946	* prematurely.
3947	*/
3948	static void hmR0SvmInjectPendingEvent(PVMCPU pVCpu, PSVMVMCB pVmcb)
3949	{
3950	Assert(!TRPMHasTrap(pVCpu));
3951	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
3952
3953	bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
3954	#ifdef VBOX_STRICT
3955	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
3956	bool const fGif = pCtx->hwvirt.fGif;
3957	bool fAllowInt = fGif;
3958	if (fGif)
3959	{
3960	/*
3961	* For nested-guests we have no way to determine if we're injecting a physical or
3962	* virtual interrupt at this point. Hence the partial verification below.
3963	*/
3964	if (CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
3965	fAllowInt = CPUMCanSvmNstGstTakePhysIntr(pVCpu, pCtx) \|\| CPUMCanSvmNstGstTakeVirtIntr(pVCpu, pCtx);
3966	else
3967	fAllowInt = RT_BOOL(pCtx->eflags.u32 & X86_EFL_IF);
3968	}
3969	#endif
3970
3971	if (pVCpu->hm.s.Event.fPending)
3972	{
3973	SVMEVENT Event;
3974	Event.u = pVCpu->hm.s.Event.u64IntInfo;
3975	Assert(Event.n.u1Valid);
3976
3977	/*
3978	* Validate event injection pre-conditions.
3979	*/
3980	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
3981	{
3982	Assert(fAllowInt);
3983	Assert(!fIntShadow);
3984	}
3985	else if (Event.n.u3Type == SVM_EVENT_NMI)
3986	{
3987	Assert(fGif);
3988	Assert(!fIntShadow);
3989	}
3990
3991	/*
3992	* Before injecting an NMI we must set VMCPU_FF_BLOCK_NMIS to prevent nested NMIs. We
3993	* do this only when we are surely going to inject the NMI as otherwise if we return
3994	* to ring-3 prematurely we could leave NMIs blocked indefinitely upon re-entry into
3995	* SVM R0.
3996	*
3997	* With VT-x, this is handled by the Guest interruptibility information VMCS field
3998	* which will set the VMCS field after actually delivering the NMI which we read on
3999	* VM-exit to determine the state.
4000	*/
4001	if ( Event.n.u3Type == SVM_EVENT_NMI
4002	&& Event.n.u8Vector == X86_XCPT_NMI
4003	&& !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
4004	{
4005	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
4006	}
4007
4008	/*
4009	* Inject it (update VMCB for injection by the hardware).
4010	*/
4011	Log4(("Injecting pending HM event\n"));
4012	hmR0SvmInjectEventVmcb(pVCpu, pVmcb, &Event);
4013	pVCpu->hm.s.Event.fPending = false;
4014
4015	if (Event.n.u3Type == SVM_EVENT_EXTERNAL_IRQ)
4016	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectInterrupt);
4017	else
4018	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectXcpt);
4019	}
4020	else
4021	Assert(pVmcb->ctrl.EventInject.n.u1Valid == 0);
4022
4023	/*
4024	* We could have injected an NMI through IEM and continue guest execution using
4025	* hardware-assisted SVM. In which case, we would not have any events pending (above)
4026	* but we still need to intercept IRET in order to eventually clear NMI inhibition.
4027	*/
4028	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
4029	hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_IRET);
4030
4031	/*
4032	* Update the guest interrupt shadow in the guest (or nested-guest) VMCB.
4033	*
4034	* For nested-guests: We need to update it too for the scenario where IEM executes
4035	* the nested-guest but execution later continues here with an interrupt shadow active.
4036	*/
4037	pVmcb->ctrl.IntShadow.n.u1IntShadow = fIntShadow;
4038	}
4039
4040
4041	/**
4042	* Reports world-switch error and dumps some useful debug info.
4043	*
4044	* @param pVCpu The cross context virtual CPU structure.
4045	* @param rcVMRun The return code from VMRUN (or
4046	* VERR_SVM_INVALID_GUEST_STATE for invalid
4047	* guest-state).
4048	*/
4049	static void hmR0SvmReportWorldSwitchError(PVMCPU pVCpu, int rcVMRun)
4050	{
4051	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4052	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
4053	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4054
4055	if (rcVMRun == VERR_SVM_INVALID_GUEST_STATE)
4056	{
4057	#ifdef VBOX_STRICT
4058	hmR0DumpRegs(pVCpu);
4059	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
4060	Log4(("ctrl.u32VmcbCleanBits %#RX32\n", pVmcb->ctrl.u32VmcbCleanBits));
4061	Log4(("ctrl.u16InterceptRdCRx %#x\n", pVmcb->ctrl.u16InterceptRdCRx));
4062	Log4(("ctrl.u16InterceptWrCRx %#x\n", pVmcb->ctrl.u16InterceptWrCRx));
4063	Log4(("ctrl.u16InterceptRdDRx %#x\n", pVmcb->ctrl.u16InterceptRdDRx));
4064	Log4(("ctrl.u16InterceptWrDRx %#x\n", pVmcb->ctrl.u16InterceptWrDRx));
4065	Log4(("ctrl.u32InterceptXcpt %#x\n", pVmcb->ctrl.u32InterceptXcpt));
4066	Log4(("ctrl.u64InterceptCtrl %#RX64\n", pVmcb->ctrl.u64InterceptCtrl));
4067	Log4(("ctrl.u64IOPMPhysAddr %#RX64\n", pVmcb->ctrl.u64IOPMPhysAddr));
4068	Log4(("ctrl.u64MSRPMPhysAddr %#RX64\n", pVmcb->ctrl.u64MSRPMPhysAddr));
4069	Log4(("ctrl.u64TSCOffset %#RX64\n", pVmcb->ctrl.u64TSCOffset));
4070
4071	Log4(("ctrl.TLBCtrl.u32ASID %#x\n", pVmcb->ctrl.TLBCtrl.n.u32ASID));
4072	Log4(("ctrl.TLBCtrl.u8TLBFlush %#x\n", pVmcb->ctrl.TLBCtrl.n.u8TLBFlush));
4073	Log4(("ctrl.TLBCtrl.u24Reserved %#x\n", pVmcb->ctrl.TLBCtrl.n.u24Reserved));
4074
4075	Log4(("ctrl.IntCtrl.u8VTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u8VTPR));
4076	Log4(("ctrl.IntCtrl.u1VIrqPending %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
4077	Log4(("ctrl.IntCtrl.u1VGif %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGif));
4078	Log4(("ctrl.IntCtrl.u6Reserved0 %#x\n", pVmcb->ctrl.IntCtrl.n.u6Reserved));
4079	Log4(("ctrl.IntCtrl.u4VIntrPrio %#x\n", pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
4080	Log4(("ctrl.IntCtrl.u1IgnoreTPR %#x\n", pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
4081	Log4(("ctrl.IntCtrl.u3Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u3Reserved));
4082	Log4(("ctrl.IntCtrl.u1VIntrMasking %#x\n", pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
4083	Log4(("ctrl.IntCtrl.u1VGifEnable %#x\n", pVmcb->ctrl.IntCtrl.n.u1VGifEnable));
4084	Log4(("ctrl.IntCtrl.u5Reserved1 %#x\n", pVmcb->ctrl.IntCtrl.n.u5Reserved));
4085	Log4(("ctrl.IntCtrl.u8VIntrVector %#x\n", pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
4086	Log4(("ctrl.IntCtrl.u24Reserved %#x\n", pVmcb->ctrl.IntCtrl.n.u24Reserved));
4087
4088	Log4(("ctrl.IntShadow.u1IntShadow %#x\n", pVmcb->ctrl.IntShadow.n.u1IntShadow));
4089	Log4(("ctrl.IntShadow.u1GuestIntMask %#x\n", pVmcb->ctrl.IntShadow.n.u1GuestIntMask));
4090	Log4(("ctrl.u64ExitCode %#RX64\n", pVmcb->ctrl.u64ExitCode));
4091	Log4(("ctrl.u64ExitInfo1 %#RX64\n", pVmcb->ctrl.u64ExitInfo1));
4092	Log4(("ctrl.u64ExitInfo2 %#RX64\n", pVmcb->ctrl.u64ExitInfo2));
4093	Log4(("ctrl.ExitIntInfo.u8Vector %#x\n", pVmcb->ctrl.ExitIntInfo.n.u8Vector));
4094	Log4(("ctrl.ExitIntInfo.u3Type %#x\n", pVmcb->ctrl.ExitIntInfo.n.u3Type));
4095	Log4(("ctrl.ExitIntInfo.u1ErrorCodeValid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid));
4096	Log4(("ctrl.ExitIntInfo.u19Reserved %#x\n", pVmcb->ctrl.ExitIntInfo.n.u19Reserved));
4097	Log4(("ctrl.ExitIntInfo.u1Valid %#x\n", pVmcb->ctrl.ExitIntInfo.n.u1Valid));
4098	Log4(("ctrl.ExitIntInfo.u32ErrorCode %#x\n", pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode));
4099	Log4(("ctrl.NestedPagingCtrl.u1NestedPaging %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1NestedPaging));
4100	Log4(("ctrl.NestedPagingCtrl.u1Sev %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1Sev));
4101	Log4(("ctrl.NestedPagingCtrl.u1SevEs %#x\n", pVmcb->ctrl.NestedPagingCtrl.n.u1SevEs));
4102	Log4(("ctrl.EventInject.u8Vector %#x\n", pVmcb->ctrl.EventInject.n.u8Vector));
4103	Log4(("ctrl.EventInject.u3Type %#x\n", pVmcb->ctrl.EventInject.n.u3Type));
4104	Log4(("ctrl.EventInject.u1ErrorCodeValid %#x\n", pVmcb->ctrl.EventInject.n.u1ErrorCodeValid));
4105	Log4(("ctrl.EventInject.u19Reserved %#x\n", pVmcb->ctrl.EventInject.n.u19Reserved));
4106	Log4(("ctrl.EventInject.u1Valid %#x\n", pVmcb->ctrl.EventInject.n.u1Valid));
4107	Log4(("ctrl.EventInject.u32ErrorCode %#x\n", pVmcb->ctrl.EventInject.n.u32ErrorCode));
4108
4109	Log4(("ctrl.u64NestedPagingCR3 %#RX64\n", pVmcb->ctrl.u64NestedPagingCR3));
4110
4111	Log4(("ctrl.LbrVirt.u1LbrVirt %#x\n", pVmcb->ctrl.LbrVirt.n.u1LbrVirt));
4112	Log4(("ctrl.LbrVirt.u1VirtVmsaveVmload %#x\n", pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload));
4113
4114	Log4(("guest.CS.u16Sel %RTsel\n", pVmcb->guest.CS.u16Sel));
4115	Log4(("guest.CS.u16Attr %#x\n", pVmcb->guest.CS.u16Attr));
4116	Log4(("guest.CS.u32Limit %#RX32\n", pVmcb->guest.CS.u32Limit));
4117	Log4(("guest.CS.u64Base %#RX64\n", pVmcb->guest.CS.u64Base));
4118	Log4(("guest.DS.u16Sel %#RTsel\n", pVmcb->guest.DS.u16Sel));
4119	Log4(("guest.DS.u16Attr %#x\n", pVmcb->guest.DS.u16Attr));
4120	Log4(("guest.DS.u32Limit %#RX32\n", pVmcb->guest.DS.u32Limit));
4121	Log4(("guest.DS.u64Base %#RX64\n", pVmcb->guest.DS.u64Base));
4122	Log4(("guest.ES.u16Sel %RTsel\n", pVmcb->guest.ES.u16Sel));
4123	Log4(("guest.ES.u16Attr %#x\n", pVmcb->guest.ES.u16Attr));
4124	Log4(("guest.ES.u32Limit %#RX32\n", pVmcb->guest.ES.u32Limit));
4125	Log4(("guest.ES.u64Base %#RX64\n", pVmcb->guest.ES.u64Base));
4126	Log4(("guest.FS.u16Sel %RTsel\n", pVmcb->guest.FS.u16Sel));
4127	Log4(("guest.FS.u16Attr %#x\n", pVmcb->guest.FS.u16Attr));
4128	Log4(("guest.FS.u32Limit %#RX32\n", pVmcb->guest.FS.u32Limit));
4129	Log4(("guest.FS.u64Base %#RX64\n", pVmcb->guest.FS.u64Base));
4130	Log4(("guest.GS.u16Sel %RTsel\n", pVmcb->guest.GS.u16Sel));
4131	Log4(("guest.GS.u16Attr %#x\n", pVmcb->guest.GS.u16Attr));
4132	Log4(("guest.GS.u32Limit %#RX32\n", pVmcb->guest.GS.u32Limit));
4133	Log4(("guest.GS.u64Base %#RX64\n", pVmcb->guest.GS.u64Base));
4134
4135	Log4(("guest.GDTR.u32Limit %#RX32\n", pVmcb->guest.GDTR.u32Limit));
4136	Log4(("guest.GDTR.u64Base %#RX64\n", pVmcb->guest.GDTR.u64Base));
4137
4138	Log4(("guest.LDTR.u16Sel %RTsel\n", pVmcb->guest.LDTR.u16Sel));
4139	Log4(("guest.LDTR.u16Attr %#x\n", pVmcb->guest.LDTR.u16Attr));
4140	Log4(("guest.LDTR.u32Limit %#RX32\n", pVmcb->guest.LDTR.u32Limit));
4141	Log4(("guest.LDTR.u64Base %#RX64\n", pVmcb->guest.LDTR.u64Base));
4142
4143	Log4(("guest.IDTR.u32Limit %#RX32\n", pVmcb->guest.IDTR.u32Limit));
4144	Log4(("guest.IDTR.u64Base %#RX64\n", pVmcb->guest.IDTR.u64Base));
4145
4146	Log4(("guest.TR.u16Sel %RTsel\n", pVmcb->guest.TR.u16Sel));
4147	Log4(("guest.TR.u16Attr %#x\n", pVmcb->guest.TR.u16Attr));
4148	Log4(("guest.TR.u32Limit %#RX32\n", pVmcb->guest.TR.u32Limit));
4149	Log4(("guest.TR.u64Base %#RX64\n", pVmcb->guest.TR.u64Base));
4150
4151	Log4(("guest.u8CPL %#x\n", pVmcb->guest.u8CPL));
4152	Log4(("guest.u64CR0 %#RX64\n", pVmcb->guest.u64CR0));
4153	Log4(("guest.u64CR2 %#RX64\n", pVmcb->guest.u64CR2));
4154	Log4(("guest.u64CR3 %#RX64\n", pVmcb->guest.u64CR3));
4155	Log4(("guest.u64CR4 %#RX64\n", pVmcb->guest.u64CR4));
4156	Log4(("guest.u64DR6 %#RX64\n", pVmcb->guest.u64DR6));
4157	Log4(("guest.u64DR7 %#RX64\n", pVmcb->guest.u64DR7));
4158
4159	Log4(("guest.u64RIP %#RX64\n", pVmcb->guest.u64RIP));
4160	Log4(("guest.u64RSP %#RX64\n", pVmcb->guest.u64RSP));
4161	Log4(("guest.u64RAX %#RX64\n", pVmcb->guest.u64RAX));
4162	Log4(("guest.u64RFlags %#RX64\n", pVmcb->guest.u64RFlags));
4163
4164	Log4(("guest.u64SysEnterCS %#RX64\n", pVmcb->guest.u64SysEnterCS));
4165	Log4(("guest.u64SysEnterEIP %#RX64\n", pVmcb->guest.u64SysEnterEIP));
4166	Log4(("guest.u64SysEnterESP %#RX64\n", pVmcb->guest.u64SysEnterESP));
4167
4168	Log4(("guest.u64EFER %#RX64\n", pVmcb->guest.u64EFER));
4169	Log4(("guest.u64STAR %#RX64\n", pVmcb->guest.u64STAR));
4170	Log4(("guest.u64LSTAR %#RX64\n", pVmcb->guest.u64LSTAR));
4171	Log4(("guest.u64CSTAR %#RX64\n", pVmcb->guest.u64CSTAR));
4172	Log4(("guest.u64SFMASK %#RX64\n", pVmcb->guest.u64SFMASK));
4173	Log4(("guest.u64KernelGSBase %#RX64\n", pVmcb->guest.u64KernelGSBase));
4174	Log4(("guest.u64PAT %#RX64\n", pVmcb->guest.u64PAT));
4175	Log4(("guest.u64DBGCTL %#RX64\n", pVmcb->guest.u64DBGCTL));
4176	Log4(("guest.u64BR_FROM %#RX64\n", pVmcb->guest.u64BR_FROM));
4177	Log4(("guest.u64BR_TO %#RX64\n", pVmcb->guest.u64BR_TO));
4178	Log4(("guest.u64LASTEXCPFROM %#RX64\n", pVmcb->guest.u64LASTEXCPFROM));
4179	Log4(("guest.u64LASTEXCPTO %#RX64\n", pVmcb->guest.u64LASTEXCPTO));
4180
4181	NOREF(pVmcb);
4182	#endif /* VBOX_STRICT */
4183	}
4184	else
4185	Log4Func(("rcVMRun=%d\n", rcVMRun));
4186	}
4187
4188
4189	/**
4190	* Check per-VM and per-VCPU force flag actions that require us to go back to
4191	* ring-3 for one reason or another.
4192	*
4193	* @returns VBox status code (information status code included).
4194	* @retval VINF_SUCCESS if we don't have any actions that require going back to
4195	* ring-3.
4196	* @retval VINF_PGM_SYNC_CR3 if we have pending PGM CR3 sync.
4197	* @retval VINF_EM_PENDING_REQUEST if we have pending requests (like hardware
4198	* interrupts)
4199	* @retval VINF_PGM_POOL_FLUSH_PENDING if PGM is doing a pool flush and requires
4200	* all EMTs to be in ring-3.
4201	* @retval VINF_EM_RAW_TO_R3 if there is pending DMA requests.
4202	* @retval VINF_EM_NO_MEMORY PGM is out of memory, we need to return
4203	* to the EM loop.
4204	*
4205	* @param pVCpu The cross context virtual CPU structure.
4206	*/
4207	static int hmR0SvmCheckForceFlags(PVMCPU pVCpu)
4208	{
4209	Assert(VMMRZCallRing3IsEnabled(pVCpu));
4210	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
4211
4212	/* Could happen as a result of longjump. */
4213	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
4214	PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
4215
4216	/* Update pending interrupts into the APIC's IRR. */
4217	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
4218	APICUpdatePendingInterrupts(pVCpu);
4219
4220	PVM pVM = pVCpu->CTX_SUFF(pVM);
4221	if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction
4222	? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
4223	\|\| VMCPU_FF_IS_PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction
4224	? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
4225	{
4226	/* Pending PGM C3 sync. */
4227	if (VMCPU_FF_IS_PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
4228	{
4229	int rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4,
4230	VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4231	if (rc != VINF_SUCCESS)
4232	{
4233	Log4Func(("PGMSyncCR3 forcing us back to ring-3. rc=%d\n", rc));
4234	return rc;
4235	}
4236	}
4237
4238	/* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */
4239	/* -XXX- what was that about single stepping? */
4240	if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK)
4241	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4242	{
4243	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4244	int rc = RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)) ? VINF_EM_NO_MEMORY : VINF_EM_RAW_TO_R3;
4245	Log4Func(("HM_TO_R3 forcing us back to ring-3. rc=%d\n", rc));
4246	return rc;
4247	}
4248
4249	/* Pending VM request packets, such as hardware interrupts. */
4250	if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
4251	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
4252	{
4253	Log4Func(("Pending VM request forcing us back to ring-3\n"));
4254	return VINF_EM_PENDING_REQUEST;
4255	}
4256
4257	/* Pending PGM pool flushes. */
4258	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_POOL_FLUSH_PENDING))
4259	{
4260	Log4Func(("PGM pool flush pending forcing us back to ring-3\n"));
4261	return VINF_PGM_POOL_FLUSH_PENDING;
4262	}
4263
4264	/* Pending DMA requests. */
4265	if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
4266	{
4267	Log4Func(("Pending DMA request forcing us back to ring-3\n"));
4268	return VINF_EM_RAW_TO_R3;
4269	}
4270	}
4271
4272	return VINF_SUCCESS;
4273	}
4274
4275
4276	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4277	/**
4278	* Does the preparations before executing nested-guest code in AMD-V.
4279	*
4280	* @returns VBox status code (informational status codes included).
4281	* @retval VINF_SUCCESS if we can proceed with running the guest.
4282	* @retval VINF_* scheduling changes, we have to go back to ring-3.
4283	*
4284	* @param pVCpu The cross context virtual CPU structure.
4285	* @param pSvmTransient Pointer to the SVM transient structure.
4286	*
4287	* @remarks Same caveats regarding longjumps as hmR0SvmPreRunGuest applies.
4288	* @sa hmR0SvmPreRunGuest.
4289	*/
4290	static int hmR0SvmPreRunGuestNested(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
4291	{
4292	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4293	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4294	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4295
4296	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM_ONLY_IN_IEM
4297	Log2(("hmR0SvmPreRunGuest: Rescheduling to IEM due to nested-hwvirt or forced IEM exec -> VINF_EM_RESCHEDULE_REM\n"));
4298	return VINF_EM_RESCHEDULE_REM;
4299	#endif
4300
4301	/* Check force flag actions that might require us to go back to ring-3. */
4302	int rc = hmR0SvmCheckForceFlags(pVCpu);
4303	if (rc != VINF_SUCCESS)
4304	return rc;
4305
4306	if (TRPMHasTrap(pVCpu))
4307	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4308	else if (!pVCpu->hm.s.Event.fPending)
4309	{
4310	VBOXSTRICTRC rcStrict = hmR0SvmEvaluatePendingEventNested(pVCpu);
4311	if ( rcStrict != VINF_SUCCESS
4312	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
4313	return VBOXSTRICTRC_VAL(rcStrict);
4314	}
4315
4316	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
4317
4318	/*
4319	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4320	* Just do it in software, see @bugref{8411}.
4321	* NB: If we could continue a task switch exit we wouldn't need to do this.
4322	*/
4323	PVM pVM = pVCpu->CTX_SUFF(pVM);
4324	if (RT_UNLIKELY( !pVM->hm.s.svm.u32Features
4325	&& pVCpu->hm.s.Event.fPending
4326	&& SVM_EVENT_GET_TYPE(pVCpu->hm.s.Event.u64IntInfo) == SVM_EVENT_NMI))
4327	{
4328	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4329	}
4330
4331	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4332	Assert(!(pCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4333	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
4334	#endif
4335
4336	/*
4337	* Export the nested-guest state bits that are not shared with the host in any way as we
4338	* can longjmp or get preempted in the midst of exporting some of the state.
4339	*/
4340	rc = hmR0SvmExportGuestStateNested(pVCpu);
4341	AssertRCReturn(rc, rc);
4342	STAM_COUNTER_INC(&pVCpu->hm.s.StatExportFull);
4343
4344	/* Ensure we've cached (and hopefully modified) the VMCB for execution using hardware-assisted SVM. */
4345	Assert(pVCpu->hm.s.svm.NstGstVmcbCache.fCacheValid);
4346
4347	/*
4348	* No longjmps to ring-3 from this point on!!!
4349	*
4350	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4351	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4352	*/
4353	VMMRZCallRing3Disable(pVCpu);
4354
4355	/*
4356	* We disable interrupts so that we don't miss any interrupts that would flag preemption
4357	* (IPI/timers etc.) when thread-context hooks aren't used and we've been running with
4358	* preemption disabled for a while. Since this is purly to aid the
4359	* RTThreadPreemptIsPending() code, it doesn't matter that it may temporarily reenable and
4360	* disable interrupt on NT.
4361	*
4362	* We need to check for force-flags that could've possible been altered since we last
4363	* checked them (e.g. by PDMGetInterrupt() leaving the PDM critical section,
4364	* see @bugref{6398}).
4365	*
4366	* We also check a couple of other force-flags as a last opportunity to get the EMT back
4367	* to ring-3 before executing guest code.
4368	*/
4369	pSvmTransient->fEFlags = ASMIntDisableFlags();
4370	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4371	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4372	{
4373	ASMSetFlags(pSvmTransient->fEFlags);
4374	VMMRZCallRing3Enable(pVCpu);
4375	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4376	return VINF_EM_RAW_TO_R3;
4377	}
4378	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4379	{
4380	ASMSetFlags(pSvmTransient->fEFlags);
4381	VMMRZCallRing3Enable(pVCpu);
4382	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPendingHostIrq);
4383	return VINF_EM_RAW_INTERRUPT;
4384	}
4385	return VINF_SUCCESS;
4386	}
4387	#endif
4388
4389
4390	/**
4391	* Does the preparations before executing guest code in AMD-V.
4392	*
4393	* This may cause longjmps to ring-3 and may even result in rescheduling to the
4394	* recompiler. We must be cautious what we do here regarding committing
4395	* guest-state information into the VMCB assuming we assuredly execute the guest
4396	* in AMD-V. If we fall back to the recompiler after updating the VMCB and
4397	* clearing the common-state (TRPM/forceflags), we must undo those changes so
4398	* that the recompiler can (and should) use them when it resumes guest
4399	* execution. Otherwise such operations must be done when we can no longer
4400	* exit to ring-3.
4401	*
4402	* @returns VBox status code (informational status codes included).
4403	* @retval VINF_SUCCESS if we can proceed with running the guest.
4404	* @retval VINF_* scheduling changes, we have to go back to ring-3.
4405	*
4406	* @param pVCpu The cross context virtual CPU structure.
4407	* @param pSvmTransient Pointer to the SVM transient structure.
4408	*/
4409	static int hmR0SvmPreRunGuest(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
4410	{
4411	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
4412	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
4413
4414	/* Check force flag actions that might require us to go back to ring-3. */
4415	int rc = hmR0SvmCheckForceFlags(pVCpu);
4416	if (rc != VINF_SUCCESS)
4417	return rc;
4418
4419	if (TRPMHasTrap(pVCpu))
4420	hmR0SvmTrpmTrapToPendingEvent(pVCpu);
4421	else if (!pVCpu->hm.s.Event.fPending)
4422	hmR0SvmEvaluatePendingEvent(pVCpu);
4423
4424	/*
4425	* On the oldest AMD-V systems, we may not get enough information to reinject an NMI.
4426	* Just do it in software, see @bugref{8411}.
4427	* NB: If we could continue a task switch exit we wouldn't need to do this.
4428	*/
4429	PVM pVM = pVCpu->CTX_SUFF(pVM);
4430	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending && (((pVCpu->hm.s.Event.u64IntInfo >> 8) & 7) == SVM_EVENT_NMI)))
4431	if (RT_UNLIKELY(!pVM->hm.s.svm.u32Features))
4432	return VINF_EM_RAW_INJECT_TRPM_EVENT;
4433
4434	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4435	Assert(!(pVCpu->cpum.GstCtx->fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4436	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
4437	#endif
4438
4439	/*
4440	* Export the guest state bits that are not shared with the host in any way as we can
4441	* longjmp or get preempted in the midst of exporting some of the state.
4442	*/
4443	rc = hmR0SvmExportGuestState(pVCpu);
4444	AssertRCReturn(rc, rc);
4445	STAM_COUNTER_INC(&pVCpu->hm.s.StatExportFull);
4446
4447	/*
4448	* If we're not intercepting TPR changes in the guest, save the guest TPR before the
4449	* world-switch so we can update it on the way back if the guest changed the TPR.
4450	*/
4451	if (pVCpu->hm.s.svm.fSyncVTpr)
4452	{
4453	PCSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
4454	if (pVM->hm.s.fTPRPatchingActive)
4455	pSvmTransient->u8GuestTpr = pVmcb->guest.u64LSTAR;
4456	else
4457	pSvmTransient->u8GuestTpr = pVmcb->ctrl.IntCtrl.n.u8VTPR;
4458	}
4459
4460	/*
4461	* No longjmps to ring-3 from this point on!!!
4462	*
4463	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4464	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4465	*/
4466	VMMRZCallRing3Disable(pVCpu);
4467
4468	/*
4469	* We disable interrupts so that we don't miss any interrupts that would flag preemption
4470	* (IPI/timers etc.) when thread-context hooks aren't used and we've been running with
4471	* preemption disabled for a while. Since this is purly to aid the
4472	* RTThreadPreemptIsPending() code, it doesn't matter that it may temporarily reenable and
4473	* disable interrupt on NT.
4474	*
4475	* We need to check for force-flags that could've possible been altered since we last
4476	* checked them (e.g. by PDMGetInterrupt() leaving the PDM critical section,
4477	* see @bugref{6398}).
4478	*
4479	* We also check a couple of other force-flags as a last opportunity to get the EMT back
4480	* to ring-3 before executing guest code.
4481	*/
4482	pSvmTransient->fEFlags = ASMIntDisableFlags();
4483	if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
4484	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
4485	{
4486	ASMSetFlags(pSvmTransient->fEFlags);
4487	VMMRZCallRing3Enable(pVCpu);
4488	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF);
4489	return VINF_EM_RAW_TO_R3;
4490	}
4491	if (RTThreadPreemptIsPending(NIL_RTTHREAD))
4492	{
4493	ASMSetFlags(pSvmTransient->fEFlags);
4494	VMMRZCallRing3Enable(pVCpu);
4495	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchPendingHostIrq);
4496	return VINF_EM_RAW_INTERRUPT;
4497	}
4498
4499	return VINF_SUCCESS;
4500	}
4501
4502
4503	/**
4504	* Prepares to run guest (or nested-guest) code in AMD-V and we've committed to
4505	* doing so.
4506	*
4507	* This means there is no backing out to ring-3 or anywhere else at this point.
4508	*
4509	* @param pVCpu The cross context virtual CPU structure.
4510	* @param pSvmTransient Pointer to the SVM transient structure.
4511	*
4512	* @remarks Called with preemption disabled.
4513	* @remarks No-long-jump zone!!!
4514	*/
4515	static void hmR0SvmPreRunGuestCommitted(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
4516	{
4517	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4518	Assert(VMMR0IsLogFlushDisabled(pVCpu));
4519	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
4520
4521	VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4522	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC); /* Indicate the start of guest execution. */
4523
4524	PVM pVM = pVCpu->CTX_SUFF(pVM);
4525	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4526
4527	hmR0SvmInjectPendingEvent(pVCpu, pVmcb);
4528
4529	if (!CPUMIsGuestFPUStateActive(pVCpu))
4530	{
4531	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4532	CPUMR0LoadGuestFPU(pVM, pVCpu); /* (Ignore rc, no need to set HM_CHANGED_HOST_CONTEXT for SVM.) */
4533	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatLoadGuestFpuState, x);
4534	STAM_COUNTER_INC(&pVCpu->hm.s.StatLoadGuestFpu);
4535	}
4536
4537	/* Load the state shared between host and guest (FPU, debug). */
4538	if (pVCpu->hm.s.fCtxChanged & HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE)
4539	hmR0SvmExportSharedState(pVCpu, pVmcb);
4540
4541	pVCpu->hm.s.fCtxChanged &= ~HM_CHANGED_HOST_CONTEXT; /* Preemption might set this, nothing to do on AMD-V. */
4542	AssertMsg(!pVCpu->hm.s.fCtxChanged, ("fCtxChanged=%#RX64\n", pVCpu->hm.s.fCtxChanged));
4543
4544	PHMGLOBALCPUINFO pHostCpu = hmR0GetCurrentCpu();
4545	RTCPUID const idHostCpu = pHostCpu->idCpu;
4546	bool const fMigratedHostCpu = idHostCpu != pVCpu->hm.s.idLastCpu;
4547
4548	/* Setup TSC offsetting. */
4549	if ( pSvmTransient->fUpdateTscOffsetting
4550	\|\| fMigratedHostCpu)
4551	{
4552	hmR0SvmUpdateTscOffsetting(pVCpu, pVmcb);
4553	pSvmTransient->fUpdateTscOffsetting = false;
4554	}
4555
4556	/* If we've migrating CPUs, mark the VMCB Clean bits as dirty. */
4557	if (fMigratedHostCpu)
4558	pVmcb->ctrl.u32VmcbCleanBits = 0;
4559
4560	/* Store status of the shared guest-host state at the time of VMRUN. */
4561	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
4562	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx))
4563	{
4564	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActivePending(pVCpu);
4565	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActivePending(pVCpu);
4566	}
4567	else
4568	#endif
4569	{
4570	pSvmTransient->fWasGuestDebugStateActive = CPUMIsGuestDebugStateActive(pVCpu);
4571	pSvmTransient->fWasHyperDebugStateActive = CPUMIsHyperDebugStateActive(pVCpu);
4572	}
4573
4574	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4575	uint8_t *pbMsrBitmap;
4576	if (!pSvmTransient->fIsNestedGuest)
4577	pbMsrBitmap = (uint8_t *)pVCpu->hm.s.svm.pvMsrBitmap;
4578	else
4579	{
4580	hmR0SvmMergeMsrpmNested(pHostCpu, pVCpu);
4581
4582	/* Update the nested-guest VMCB with the newly merged MSRPM (clean bits updated below). */
4583	pVmcb->ctrl.u64MSRPMPhysAddr = pHostCpu->n.svm.HCPhysNstGstMsrpm;
4584	pbMsrBitmap = (uint8_t *)pHostCpu->n.svm.pvNstGstMsrpm;
4585	}
4586	#else
4587	uint8_t pbMsrBitmap = (uint8_t )pVCpu->hm.s.svm.pvMsrBitmap;
4588	#endif
4589
4590	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, true); /* Used for TLB flushing, set this across the world switch. */
4591	/* Flush the appropriate tagged-TLB entries. */
4592	hmR0SvmFlushTaggedTlb(pVCpu, pVmcb, pHostCpu);
4593	Assert(pVCpu->hm.s.idLastCpu == idHostCpu);
4594
4595	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatEntry, &pVCpu->hm.s.StatInGC, x);
4596
4597	TMNotifyStartOfExecution(pVCpu); /* Finally, notify TM to resume its clocks as we're about
4598	to start executing. */
4599
4600	/*
4601	* Save the current Host TSC_AUX and write the guest TSC_AUX to the host, so that RDTSCPs
4602	* (that don't cause exits) reads the guest MSR, see @bugref{3324}.
4603	*
4604	* This should be done -after- any RDTSCPs for obtaining the host timestamp (TM, STAM etc).
4605	*/
4606	if ( pVM->cpum.ro.HostFeatures.fRdTscP
4607	&& !(pVmcb->ctrl.u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSCP))
4608	{
4609	uint64_t const uGuestTscAux = CPUMGetGuestTscAux(pVCpu);
4610	pVCpu->hm.s.u64HostTscAux = ASMRdMsr(MSR_K8_TSC_AUX);
4611	if (uGuestTscAux != pVCpu->hm.s.u64HostTscAux)
4612	ASMWrMsr(MSR_K8_TSC_AUX, uGuestTscAux);
4613	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_PASSTHRU_READ, SVMMSREXIT_PASSTHRU_WRITE);
4614	pSvmTransient->fRestoreTscAuxMsr = true;
4615	}
4616	else
4617	{
4618	hmR0SvmSetMsrPermission(pVCpu, pbMsrBitmap, MSR_K8_TSC_AUX, SVMMSREXIT_INTERCEPT_READ, SVMMSREXIT_INTERCEPT_WRITE);
4619	pSvmTransient->fRestoreTscAuxMsr = false;
4620	}
4621	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_IOPM_MSRPM;
4622
4623	/*
4624	* If VMCB Clean bits isn't supported by the CPU or exposed to the guest in the nested
4625	* virtualization case, mark all state-bits as dirty indicating to the CPU to re-load
4626	* from the VMCB.
4627	*/
4628	bool const fSupportsVmcbCleanBits = hmR0SvmSupportsVmcbCleanBits(pVCpu);
4629	if (!fSupportsVmcbCleanBits)
4630	pVmcb->ctrl.u32VmcbCleanBits = 0;
4631	}
4632
4633
4634	/**
4635	* Wrapper for running the guest (or nested-guest) code in AMD-V.
4636	*
4637	* @returns VBox strict status code.
4638	* @param pVCpu The cross context virtual CPU structure.
4639	* @param HCPhysVmcb The host physical address of the VMCB.
4640	*
4641	* @remarks No-long-jump zone!!!
4642	*/
4643	DECLINLINE(int) hmR0SvmRunGuest(PVMCPU pVCpu, RTHCPHYS HCPhysVmcb)
4644	{
4645	/* Mark that HM is the keeper of all guest-CPU registers now that we're going to execute guest code. */
4646	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4647	pCtx->fExtrn \|= HMSVM_CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_KEEPER_HM;
4648
4649	/*
4650	* 64-bit Windows uses XMM registers in the kernel as the Microsoft compiler expresses
4651	* floating-point operations using SSE instructions. Some XMM registers (XMM6-XMM15) are
4652	* callee-saved and thus the need for this XMM wrapper.
4653	*
4654	* Refer MSDN "Configuring Programs for 64-bit/x64 Software Conventions / Register Usage".
4655	*/
4656	PVM pVM = pVCpu->CTX_SUFF(pVM);
4657	#ifdef VBOX_WITH_KERNEL_USING_XMM
4658	return hmR0SVMRunWrapXMM(pVCpu->hm.s.svm.HCPhysVmcbHost, HCPhysVmcb, pCtx, pVM, pVCpu, pVCpu->hm.s.svm.pfnVMRun);
4659	#else
4660	return pVCpu->hm.s.svm.pfnVMRun(pVCpu->hm.s.svm.HCPhysVmcbHost, HCPhysVmcb, pCtx, pVM, pVCpu);
4661	#endif
4662	}
4663
4664
4665	/**
4666	* Undoes the TSC offset applied for an SVM nested-guest and returns the TSC
4667	* value for the guest.
4668	*
4669	* @returns The TSC offset after undoing any nested-guest TSC offset.
4670	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
4671	* @param uTicks The nested-guest TSC.
4672	*
4673	* @note If you make any changes to this function, please check if
4674	* hmR0SvmNstGstUndoTscOffset() needs adjusting.
4675	*
4676	* @sa HMSvmNstGstApplyTscOffset().
4677	*/
4678	DECLINLINE(uint64_t) hmR0SvmNstGstUndoTscOffset(PVMCPU pVCpu, uint64_t uTicks)
4679	{
4680	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
4681	Assert(pVmcbNstGstCache->fCacheValid);
4682	return uTicks - pVmcbNstGstCache->u64TSCOffset;
4683	}
4684
4685
4686	/**
4687	* Performs some essential restoration of state after running guest (or
4688	* nested-guest) code in AMD-V.
4689	*
4690	* @param pVCpu The cross context virtual CPU structure.
4691	* @param pSvmTransient Pointer to the SVM transient structure.
4692	* @param rcVMRun Return code of VMRUN.
4693	*
4694	* @remarks Called with interrupts disabled.
4695	* @remarks No-long-jump zone!!! This function will however re-enable longjmps
4696	* unconditionally when it is safe to do so.
4697	*/
4698	static void hmR0SvmPostRunGuest(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient, int rcVMRun)
4699	{
4700	Assert(!VMMRZCallRing3IsEnabled(pVCpu));
4701
4702	uint64_t const uHostTsc = ASMReadTSC(); /* Read the TSC as soon as possible. */
4703	ASMAtomicWriteBool(&pVCpu->hm.s.fCheckedTLBFlush, false); /* See HMInvalidatePageOnAllVCpus(): used for TLB flushing. */
4704	ASMAtomicIncU32(&pVCpu->hm.s.cWorldSwitchExits); /* Initialized in vmR3CreateUVM(): used for EMT poking. */
4705
4706	PSVMVMCB pVmcb = pSvmTransient->pVmcb;
4707	PSVMVMCBCTRL pVmcbCtrl = &pVmcb->ctrl;
4708
4709	/* TSC read must be done early for maximum accuracy. */
4710	if (!(pVmcbCtrl->u64InterceptCtrl & SVM_CTRL_INTERCEPT_RDTSC))
4711	{
4712	if (!pSvmTransient->fIsNestedGuest)
4713	TMCpuTickSetLastSeen(pVCpu, uHostTsc + pVmcbCtrl->u64TSCOffset);
4714	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4715	else
4716	{
4717	/* The nested-guest VMCB TSC offset shall eventually be restored on #VMEXIT via HMSvmNstGstVmExitNotify(). */
4718	uint64_t const uGstTsc = hmR0SvmNstGstUndoTscOffset(pVCpu, uHostTsc + pVmcbCtrl->u64TSCOffset);
4719	TMCpuTickSetLastSeen(pVCpu, uGstTsc);
4720	}
4721	#endif
4722	}
4723
4724	if (pSvmTransient->fRestoreTscAuxMsr)
4725	{
4726	uint64_t u64GuestTscAuxMsr = ASMRdMsr(MSR_K8_TSC_AUX);
4727	CPUMSetGuestTscAux(pVCpu, u64GuestTscAuxMsr);
4728	if (u64GuestTscAuxMsr != pVCpu->hm.s.u64HostTscAux)
4729	ASMWrMsr(MSR_K8_TSC_AUX, pVCpu->hm.s.u64HostTscAux);
4730	}
4731
4732	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatPreExit, x);
4733	TMNotifyEndOfExecution(pVCpu); /* Notify TM that the guest is no longer running. */
4734	VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HM);
4735
4736	Assert(!(ASMGetFlags() & X86_EFL_IF));
4737	ASMSetFlags(pSvmTransient->fEFlags); /* Enable interrupts. */
4738	VMMRZCallRing3Enable(pVCpu); /* It is now safe to do longjmps to ring-3!!! */
4739
4740	/* If VMRUN failed, we can bail out early. This does -not- cover SVM_EXIT_INVALID. */
4741	if (RT_UNLIKELY(rcVMRun != VINF_SUCCESS))
4742	{
4743	Log4Func(("VMRUN failure: rcVMRun=%Rrc\n", rcVMRun));
4744	return;
4745	}
4746
4747	pSvmTransient->u64ExitCode = pVmcbCtrl->u64ExitCode; /* Save the #VMEXIT reason. */
4748	pVmcbCtrl->u32VmcbCleanBits = HMSVM_VMCB_CLEAN_ALL; /* Mark the VMCB-state cache as unmodified by VMM. */
4749	pSvmTransient->fVectoringDoublePF = false; /* Vectoring double page-fault needs to be determined later. */
4750	pSvmTransient->fVectoringPF = false; /* Vectoring page-fault needs to be determined later. */
4751
4752	#ifdef HMSVM_SYNC_FULL_GUEST_STATE
4753	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4754	Assert(!(pVCpu->cpum.GstCtx.fExtrn & HMSVM_CPUMCTX_EXTRN_ALL));
4755	#else
4756	/*
4757	* Always import the following:
4758	*
4759	* - RIP for exit optimizations and evaluating event injection on re-entry.
4760	* - RFLAGS for evaluating event injection on VM re-entry and for exporting shared debug
4761	* state on preemption.
4762	* - Interrupt shadow, GIF for evaluating event injection on VM re-entry.
4763	* - CS for exit optimizations.
4764	* - RAX, RSP for simplifying assumptions on GPRs. All other GPRs are swapped by the
4765	* assembly switcher code.
4766	* - Shared state (only DR7 currently) for exporting shared debug state on preemption.
4767	*/
4768	hmR0SvmImportGuestState(pVCpu, CPUMCTX_EXTRN_RIP
4769	\| CPUMCTX_EXTRN_RFLAGS
4770	\| CPUMCTX_EXTRN_RAX
4771	\| CPUMCTX_EXTRN_RSP
4772	\| CPUMCTX_EXTRN_CS
4773	\| CPUMCTX_EXTRN_HWVIRT
4774	\| CPUMCTX_EXTRN_HM_SVM_INT_SHADOW
4775	\| CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ
4776	\| HMSVM_CPUMCTX_SHARED_STATE);
4777	#endif
4778
4779	if ( pSvmTransient->u64ExitCode != SVM_EXIT_INVALID
4780	&& pVCpu->hm.s.svm.fSyncVTpr)
4781	{
4782	Assert(!pSvmTransient->fIsNestedGuest);
4783	/* TPR patching (for 32-bit guests) uses LSTAR MSR for holding the TPR value, otherwise uses the VTPR. */
4784	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive
4785	&& (pVmcb->guest.u64LSTAR & 0xff) != pSvmTransient->u8GuestTpr)
4786	{
4787	int rc = APICSetTpr(pVCpu, pVmcb->guest.u64LSTAR & 0xff);
4788	AssertRC(rc);
4789	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
4790	}
4791	/* Sync TPR when we aren't intercepting CR8 writes. */
4792	else if (pSvmTransient->u8GuestTpr != pVmcbCtrl->IntCtrl.n.u8VTPR)
4793	{
4794	int rc = APICSetTpr(pVCpu, pVmcbCtrl->IntCtrl.n.u8VTPR << 4);
4795	AssertRC(rc);
4796	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
4797	}
4798	}
4799
4800	#ifdef DEBUG_ramshankar
4801	if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
4802	{
4803	hmR0SvmImportGuestState(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
4804	hmR0SvmLogState(pVCpu, pVmcb, pVCpu->cpum.GstCtx, "hmR0SvmPostRunGuestNested", HMSVM_LOG_ALL & ~HMSVM_LOG_LBR,
4805	0 /* uVerbose */);
4806	}
4807	#endif
4808
4809	HMSVM_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
4810	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_SVM, pSvmTransient->u64ExitCode & EMEXIT_F_TYPE_MASK),
4811	pVCpu->cpum.GstCtx.cs.u64Base + pVCpu->cpum.GstCtx.rip, uHostTsc);
4812	}
4813
4814
4815	/**
4816	* Runs the guest code using AMD-V.
4817	*
4818	* @returns VBox status code.
4819	* @param pVCpu The cross context virtual CPU structure.
4820	* @param pcLoops Pointer to the number of executed loops.
4821	*/
4822	static int hmR0SvmRunGuestCodeNormal(PVMCPU pVCpu, uint32_t *pcLoops)
4823	{
4824	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops;
4825	Assert(pcLoops);
4826	Assert(*pcLoops <= cMaxResumeLoops);
4827
4828	SVMTRANSIENT SvmTransient;
4829	RT_ZERO(SvmTransient);
4830	SvmTransient.fUpdateTscOffsetting = true;
4831	SvmTransient.pVmcb = pVCpu->hm.s.svm.pVmcb;
4832
4833	int rc = VERR_INTERNAL_ERROR_5;
4834	for (;;)
4835	{
4836	Assert(!HMR0SuspendPending());
4837	HMSVM_ASSERT_CPU_SAFE(pVCpu);
4838
4839	/* Preparatory work for running nested-guest code, this may force us to return to
4840	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4841	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4842	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4843	if (rc != VINF_SUCCESS)
4844	break;
4845
4846	/*
4847	* No longjmps to ring-3 from this point on!!!
4848	*
4849	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4850	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4851	*/
4852	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4853	rc = hmR0SvmRunGuest(pVCpu, pVCpu->hm.s.svm.HCPhysVmcb);
4854
4855	/* Restore any residual host-state and save any bits shared between host and guest
4856	into the guest-CPU state. Re-enables interrupts! */
4857	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4858
4859	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4860	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4861	{
4862	if (rc == VINF_SUCCESS)
4863	rc = VERR_SVM_INVALID_GUEST_STATE;
4864	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
4865	hmR0SvmReportWorldSwitchError(pVCpu, rc);
4866	break;
4867	}
4868
4869	/* Handle the #VMEXIT. */
4870	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4871	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4872	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, &pVCpu->cpum.GstCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4873	rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
4874	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4875	if (rc != VINF_SUCCESS)
4876	break;
4877	if (++(*pcLoops) >= cMaxResumeLoops)
4878	{
4879	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4880	rc = VINF_EM_RAW_INTERRUPT;
4881	break;
4882	}
4883	}
4884
4885	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4886	return rc;
4887	}
4888
4889
4890	/**
4891	* Runs the guest code using AMD-V in single step mode.
4892	*
4893	* @returns VBox status code.
4894	* @param pVCpu The cross context virtual CPU structure.
4895	* @param pcLoops Pointer to the number of executed loops.
4896	*/
4897	static int hmR0SvmRunGuestCodeStep(PVMCPU pVCpu, uint32_t *pcLoops)
4898	{
4899	uint32_t const cMaxResumeLoops = pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops;
4900	Assert(pcLoops);
4901	Assert(*pcLoops <= cMaxResumeLoops);
4902
4903	SVMTRANSIENT SvmTransient;
4904	RT_ZERO(SvmTransient);
4905	SvmTransient.fUpdateTscOffsetting = true;
4906	SvmTransient.pVmcb = pVCpu->hm.s.svm.pVmcb;
4907
4908	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
4909	uint16_t uCsStart = pCtx->cs.Sel;
4910	uint64_t uRipStart = pCtx->rip;
4911
4912	int rc = VERR_INTERNAL_ERROR_5;
4913	for (;;)
4914	{
4915	Assert(!HMR0SuspendPending());
4916	AssertMsg(pVCpu->hm.s.idEnteredCpu == RTMpCpuId(),
4917	("Illegal migration! Entered on CPU %u Current %u cLoops=%u\n", (unsigned)pVCpu->hm.s.idEnteredCpu,
4918	(unsigned)RTMpCpuId(), *pcLoops));
4919
4920	/* Preparatory work for running nested-guest code, this may force us to return to
4921	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
4922	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
4923	rc = hmR0SvmPreRunGuest(pVCpu, &SvmTransient);
4924	if (rc != VINF_SUCCESS)
4925	break;
4926
4927	/*
4928	* No longjmps to ring-3 from this point on!!!
4929	*
4930	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
4931	* better than a kernel panic. This also disables flushing of the R0-logger instance.
4932	*/
4933	VMMRZCallRing3Disable(pVCpu);
4934	VMMRZCallRing3RemoveNotification(pVCpu);
4935	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
4936
4937	rc = hmR0SvmRunGuest(pVCpu, pVCpu->hm.s.svm.HCPhysVmcb);
4938
4939	/* Restore any residual host-state and save any bits shared between host and guest
4940	into the guest-CPU state. Re-enables interrupts! */
4941	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
4942
4943	if (RT_UNLIKELY( rc != VINF_SUCCESS /* Check for VMRUN errors. */
4944	\|\| SvmTransient.u64ExitCode == SVM_EXIT_INVALID)) /* Check for invalid guest-state errors. */
4945	{
4946	if (rc == VINF_SUCCESS)
4947	rc = VERR_SVM_INVALID_GUEST_STATE;
4948	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPreExit, x);
4949	hmR0SvmReportWorldSwitchError(pVCpu, rc);
4950	return rc;
4951	}
4952
4953	/* Handle the #VMEXIT. */
4954	HMSVM_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
4955	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
4956	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pVCpu->hm.s.svm.pVmcb);
4957	rc = hmR0SvmHandleExit(pVCpu, &SvmTransient);
4958	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
4959	if (rc != VINF_SUCCESS)
4960	break;
4961	if (++(*pcLoops) >= cMaxResumeLoops)
4962	{
4963	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
4964	rc = VINF_EM_RAW_INTERRUPT;
4965	break;
4966	}
4967
4968	/*
4969	* Did the RIP change, if so, consider it a single step.
4970	* Otherwise, make sure one of the TFs gets set.
4971	*/
4972	if ( pCtx->rip != uRipStart
4973	\|\| pCtx->cs.Sel != uCsStart)
4974	{
4975	rc = VINF_EM_DBG_STEPPED;
4976	break;
4977	}
4978	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_GUEST_DR_MASK;
4979	}
4980
4981	/*
4982	* Clear the X86_EFL_TF if necessary.
4983	*/
4984	if (pVCpu->hm.s.fClearTrapFlag)
4985	{
4986	pVCpu->hm.s.fClearTrapFlag = false;
4987	pCtx->eflags.Bits.u1TF = 0;
4988	}
4989
4990	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
4991	return rc;
4992	}
4993
4994	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4995	/**
4996	* Runs the nested-guest code using AMD-V.
4997	*
4998	* @returns VBox status code.
4999	* @param pVCpu The cross context virtual CPU structure.
5000	* @param pcLoops Pointer to the number of executed loops. If we're switching
5001	* from the guest-code execution loop to this nested-guest
5002	* execution loop pass the remainder value, else pass 0.
5003	*/
5004	static int hmR0SvmRunGuestCodeNested(PVMCPU pVCpu, uint32_t *pcLoops)
5005	{
5006	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
5007	HMSVM_ASSERT_IN_NESTED_GUEST(pCtx);
5008	Assert(pcLoops);
5009	Assert(*pcLoops <= pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops);
5010
5011	SVMTRANSIENT SvmTransient;
5012	RT_ZERO(SvmTransient);
5013	SvmTransient.fUpdateTscOffsetting = true;
5014	SvmTransient.pVmcb = pCtx->hwvirt.svm.CTX_SUFF(pVmcb);
5015	SvmTransient.fIsNestedGuest = true;
5016
5017	int rc = VERR_INTERNAL_ERROR_4;
5018	for (;;)
5019	{
5020	Assert(!HMR0SuspendPending());
5021	HMSVM_ASSERT_CPU_SAFE(pVCpu);
5022
5023	/* Preparatory work for running nested-guest code, this may force us to return to
5024	ring-3. This bugger disables interrupts on VINF_SUCCESS! */
5025	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatEntry, x);
5026	rc = hmR0SvmPreRunGuestNested(pVCpu, &SvmTransient);
5027	if ( rc != VINF_SUCCESS
5028	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
5029	{
5030	break;
5031	}
5032
5033	/*
5034	* No longjmps to ring-3 from this point on!!!
5035	*
5036	* Asserts() will still longjmp to ring-3 (but won't return), which is intentional,
5037	* better than a kernel panic. This also disables flushing of the R0-logger instance.
5038	*/
5039	hmR0SvmPreRunGuestCommitted(pVCpu, &SvmTransient);
5040
5041	rc = hmR0SvmRunGuest(pVCpu, pCtx->hwvirt.svm.HCPhysVmcb);
5042
5043	/* Restore any residual host-state and save any bits shared between host and guest
5044	into the guest-CPU state. Re-enables interrupts! */
5045	hmR0SvmPostRunGuest(pVCpu, &SvmTransient, rc);
5046
5047	if (RT_LIKELY( rc == VINF_SUCCESS
5048	&& SvmTransient.u64ExitCode != SVM_EXIT_INVALID))
5049	{ /* extremely likely */ }
5050	else
5051	{
5052	/* VMRUN failed, shouldn't really happen, Guru. */
5053	if (rc != VINF_SUCCESS)
5054	break;
5055
5056	/* Invalid nested-guest state. Cause a #VMEXIT but assert on strict builds. */
5057	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
5058	AssertMsgFailed(("Invalid nested-guest state. rc=%Rrc u64ExitCode=%#RX64\n", rc, SvmTransient.u64ExitCode));
5059	rc = VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_INVALID, 0, 0));
5060	break;
5061	}
5062
5063	/* Handle the #VMEXIT. */
5064	HMSVM_NESTED_EXITCODE_STAM_COUNTER_INC(SvmTransient.u64ExitCode);
5065	STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatPreExit, &pVCpu->hm.s.StatExitHandling, x);
5066	VBOXVMM_R0_HMSVM_VMEXIT(pVCpu, pCtx, SvmTransient.u64ExitCode, pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
5067	rc = hmR0SvmHandleExitNested(pVCpu, &SvmTransient);
5068	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitHandling, x);
5069	if ( rc != VINF_SUCCESS
5070	\|\| !CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
5071	break;
5072	if (++(*pcLoops) >= pVCpu->CTX_SUFF(pVM)->hm.s.cMaxResumeLoops)
5073	{
5074	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchMaxResumeLoops);
5075	rc = VINF_EM_RAW_INTERRUPT;
5076	break;
5077	}
5078
5079	/** @todo handle single-stepping */
5080	}
5081
5082	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatEntry, x);
5083	return rc;
5084	}
5085	#endif
5086
5087
5088	/**
5089	* Runs the guest code using AMD-V.
5090	*
5091	* @returns Strict VBox status code.
5092	* @param pVCpu The cross context virtual CPU structure.
5093	*/
5094	VMMR0DECL(VBOXSTRICTRC) SVMR0RunGuestCode(PVMCPU pVCpu)
5095	{
5096	Assert(VMMRZCallRing3IsEnabled(pVCpu));
5097	HMSVM_ASSERT_PREEMPT_SAFE(pVCpu);
5098	VMMRZCallRing3SetNotification(pVCpu, hmR0SvmCallRing3Callback, NULL /* pvUser */);
5099
5100	uint32_t cLoops = 0;
5101	int rc;
5102	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5103	if (!CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
5104	#endif
5105	{
5106	if (!pVCpu->hm.s.fSingleInstruction)
5107	rc = hmR0SvmRunGuestCodeNormal(pVCpu, &cLoops);
5108	else
5109	rc = hmR0SvmRunGuestCodeStep(pVCpu, &cLoops);
5110	}
5111	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5112	else
5113	{
5114	rc = VINF_SVM_VMRUN;
5115	}
5116
5117	/* Re-check the nested-guest condition here as we may be transitioning from the normal
5118	execution loop into the nested-guest, hence this is not placed in the 'else' part above. */
5119	if (rc == VINF_SVM_VMRUN)
5120	{
5121	rc = hmR0SvmRunGuestCodeNested(pVCpu, &cLoops);
5122	if (rc == VINF_SVM_VMEXIT)
5123	rc = VINF_SUCCESS;
5124	}
5125	#endif
5126
5127	/* Fixup error codes. */
5128	if (rc == VERR_EM_INTERPRETER)
5129	rc = VINF_EM_RAW_EMULATE_INSTR;
5130	else if (rc == VINF_EM_RESET)
5131	rc = VINF_EM_TRIPLE_FAULT;
5132
5133	/* Prepare to return to ring-3. This will remove longjmp notifications. */
5134	rc = hmR0SvmExitToRing3(pVCpu, rc);
5135	Assert(!VMMRZCallRing3IsNotificationSet(pVCpu));
5136	return rc;
5137	}
5138
5139
5140	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5141	/**
5142	* Determines whether an IOIO intercept is active for the nested-guest or not.
5143	*
5144	* @param pvIoBitmap Pointer to the nested-guest IO bitmap.
5145	* @param pIoExitInfo Pointer to the SVMIOIOEXITINFO.
5146	*/
5147	static bool hmR0SvmIsIoInterceptActive(void *pvIoBitmap, PSVMIOIOEXITINFO pIoExitInfo)
5148	{
5149	const uint16_t u16Port = pIoExitInfo->n.u16Port;
5150	const SVMIOIOTYPE enmIoType = (SVMIOIOTYPE)pIoExitInfo->n.u1Type;
5151	const uint8_t cbReg = (pIoExitInfo->u >> SVM_IOIO_OP_SIZE_SHIFT) & 7;
5152	const uint8_t cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
5153	const uint8_t iEffSeg = pIoExitInfo->n.u3Seg;
5154	const bool fRep = pIoExitInfo->n.u1Rep;
5155	const bool fStrIo = pIoExitInfo->n.u1Str;
5156
5157	return HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
5158	NULL /* pIoExitInfo */);
5159	}
5160
5161
5162	/**
5163	* Handles a nested-guest \#VMEXIT (for all EXITCODE values except
5164	* SVM_EXIT_INVALID).
5165	*
5166	* @returns VBox status code (informational status codes included).
5167	* @param pVCpu The cross context virtual CPU structure.
5168	* @param pSvmTransient Pointer to the SVM transient structure.
5169	*/
5170	static int hmR0SvmHandleExitNested(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
5171	{
5172	HMSVM_ASSERT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
5173	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5174	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5175
5176	/*
5177	* We import the complete state here because we use separate VMCBs for the guest and the
5178	* nested-guest, and the guest's VMCB is used after the #VMEXIT. We can only save/restore
5179	* the #VMEXIT specific state if we used the same VMCB for both guest and nested-guest.
5180	*/
5181	#define NST_GST_VMEXIT_CALL_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
5182	do { \
5183	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL); \
5184	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2))); \
5185	} while (0)
5186
5187	/*
5188	* For all the #VMEXITs here we primarily figure out if the #VMEXIT is expected by the
5189	* nested-guest. If it isn't, it should be handled by the (outer) guest.
5190	*/
5191	PSVMVMCB pVmcbNstGst = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pVmcb);
5192	PSVMVMCBCTRL pVmcbNstGstCtrl = &pVmcbNstGst->ctrl;
5193	uint64_t const uExitCode = pVmcbNstGstCtrl->u64ExitCode;
5194	uint64_t const uExitInfo1 = pVmcbNstGstCtrl->u64ExitInfo1;
5195	uint64_t const uExitInfo2 = pVmcbNstGstCtrl->u64ExitInfo2;
5196
5197	Assert(uExitCode == pVmcbNstGstCtrl->u64ExitCode);
5198	switch (uExitCode)
5199	{
5200	case SVM_EXIT_CPUID:
5201	{
5202	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_CPUID))
5203	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5204	return hmR0SvmExitCpuid(pVCpu, pSvmTransient);
5205	}
5206
5207	case SVM_EXIT_RDTSC:
5208	{
5209	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_RDTSC))
5210	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5211	return hmR0SvmExitRdtsc(pVCpu, pSvmTransient);
5212	}
5213
5214	case SVM_EXIT_RDTSCP:
5215	{
5216	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_RDTSCP))
5217	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5218	return hmR0SvmExitRdtscp(pVCpu, pSvmTransient);
5219	}
5220
5221	case SVM_EXIT_MONITOR:
5222	{
5223	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_MONITOR))
5224	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5225	return hmR0SvmExitMonitor(pVCpu, pSvmTransient);
5226	}
5227
5228	case SVM_EXIT_MWAIT:
5229	{
5230	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_MWAIT))
5231	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5232	return hmR0SvmExitMwait(pVCpu, pSvmTransient);
5233	}
5234
5235	case SVM_EXIT_HLT:
5236	{
5237	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_HLT))
5238	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5239	return hmR0SvmExitHlt(pVCpu, pSvmTransient);
5240	}
5241
5242	case SVM_EXIT_MSR:
5243	{
5244	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_MSR_PROT))
5245	{
5246	uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
5247	uint16_t offMsrpm;
5248	uint8_t uMsrpmBit;
5249	int rc = HMSvmGetMsrpmOffsetAndBit(idMsr, &offMsrpm, &uMsrpmBit);
5250	if (RT_SUCCESS(rc))
5251	{
5252	Assert(uMsrpmBit == 0 \|\| uMsrpmBit == 2 \|\| uMsrpmBit == 4 \|\| uMsrpmBit == 6);
5253	Assert(offMsrpm < SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
5254
5255	uint8_t const pbMsrBitmap = (uint8_t const )pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvMsrBitmap);
5256	pbMsrBitmap += offMsrpm;
5257	bool const fInterceptRead = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit));
5258	bool const fInterceptWrite = RT_BOOL(*pbMsrBitmap & RT_BIT(uMsrpmBit + 1));
5259
5260	if ( (fInterceptWrite && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_WRITE)
5261	\|\| (fInterceptRead && pVmcbNstGstCtrl->u64ExitInfo1 == SVM_EXIT1_MSR_READ))
5262	{
5263	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5264	}
5265	}
5266	else
5267	{
5268	/*
5269	* MSRs not covered by the MSRPM automatically cause an #VMEXIT.
5270	* See AMD-V spec. "15.11 MSR Intercepts".
5271	*/
5272	Assert(rc == VERR_OUT_OF_RANGE);
5273	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5274	}
5275	}
5276	return hmR0SvmExitMsr(pVCpu, pSvmTransient);
5277	}
5278
5279	case SVM_EXIT_IOIO:
5280	{
5281	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_IOIO_PROT))
5282	{
5283	void *pvIoBitmap = pVCpu->cpum.GstCtx.hwvirt.svm.CTX_SUFF(pvIoBitmap);
5284	SVMIOIOEXITINFO IoExitInfo;
5285	IoExitInfo.u = pVmcbNstGst->ctrl.u64ExitInfo1;
5286	bool const fIntercept = hmR0SvmIsIoInterceptActive(pvIoBitmap, &IoExitInfo);
5287	if (fIntercept)
5288	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5289	}
5290	return hmR0SvmExitIOInstr(pVCpu, pSvmTransient);
5291	}
5292
5293	case SVM_EXIT_XCPT_PF:
5294	{
5295	PVM pVM = pVCpu->CTX_SUFF(pVM);
5296	if (pVM->hm.s.fNestedPaging)
5297	{
5298	uint32_t const u32ErrCode = pVmcbNstGstCtrl->u64ExitInfo1;
5299	uint64_t const uFaultAddress = pVmcbNstGstCtrl->u64ExitInfo2;
5300
5301	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
5302	if (HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_PF))
5303	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, u32ErrCode, uFaultAddress);
5304
5305	/* If the nested-guest is not intercepting #PFs, forward the #PF to the guest. */
5306	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR2);
5307	hmR0SvmSetPendingXcptPF(pVCpu, u32ErrCode, uFaultAddress);
5308	return VINF_SUCCESS;
5309	}
5310	return hmR0SvmExitXcptPF(pVCpu, pSvmTransient);
5311	}
5312
5313	case SVM_EXIT_XCPT_UD:
5314	{
5315	if (HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_UD))
5316	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5317	hmR0SvmSetPendingXcptUD(pVCpu);
5318	return VINF_SUCCESS;
5319	}
5320
5321	case SVM_EXIT_XCPT_MF:
5322	{
5323	if (HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_MF))
5324	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5325	return hmR0SvmExitXcptMF(pVCpu, pSvmTransient);
5326	}
5327
5328	case SVM_EXIT_XCPT_DB:
5329	{
5330	if (HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_DB))
5331	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5332	return hmR0SvmNestedExitXcptDB(pVCpu, pSvmTransient);
5333	}
5334
5335	case SVM_EXIT_XCPT_AC:
5336	{
5337	if (HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_AC))
5338	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5339	return hmR0SvmExitXcptAC(pVCpu, pSvmTransient);
5340	}
5341
5342	case SVM_EXIT_XCPT_BP:
5343	{
5344	if (HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_BP))
5345	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5346	return hmR0SvmNestedExitXcptBP(pVCpu, pSvmTransient);
5347	}
5348
5349	case SVM_EXIT_READ_CR0:
5350	case SVM_EXIT_READ_CR3:
5351	case SVM_EXIT_READ_CR4:
5352	{
5353	uint8_t const uCr = uExitCode - SVM_EXIT_READ_CR0;
5354	if (HMIsGuestSvmReadCRxInterceptSet(pVCpu, uCr))
5355	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5356	return hmR0SvmExitReadCRx(pVCpu, pSvmTransient);
5357	}
5358
5359	case SVM_EXIT_CR0_SEL_WRITE:
5360	{
5361	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_CR0_SEL_WRITE))
5362	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5363	return hmR0SvmExitWriteCRx(pVCpu, pSvmTransient);
5364	}
5365
5366	case SVM_EXIT_WRITE_CR0:
5367	case SVM_EXIT_WRITE_CR3:
5368	case SVM_EXIT_WRITE_CR4:
5369	case SVM_EXIT_WRITE_CR8: /* CR8 writes would go to the V_TPR rather than here, since we run with V_INTR_MASKING. */
5370	{
5371	uint8_t const uCr = uExitCode - SVM_EXIT_WRITE_CR0;
5372	Log4Func(("Write CR%u: uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", uCr, uExitInfo1, uExitInfo2));
5373
5374	if (HMIsGuestSvmWriteCRxInterceptSet(pVCpu, uCr))
5375	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5376	return hmR0SvmExitWriteCRx(pVCpu, pSvmTransient);
5377	}
5378
5379	case SVM_EXIT_PAUSE:
5380	{
5381	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_PAUSE))
5382	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5383	return hmR0SvmExitPause(pVCpu, pSvmTransient);
5384	}
5385
5386	case SVM_EXIT_VINTR:
5387	{
5388	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_VINTR))
5389	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5390	return hmR0SvmExitUnexpected(pVCpu, pSvmTransient);
5391	}
5392
5393	case SVM_EXIT_INTR:
5394	case SVM_EXIT_NMI:
5395	case SVM_EXIT_SMI:
5396	case SVM_EXIT_XCPT_NMI: /* Should not occur, SVM_EXIT_NMI is used instead. */
5397	{
5398	/*
5399	* We shouldn't direct physical interrupts, NMIs, SMIs to the nested-guest.
5400	*
5401	* Although we don't intercept SMIs, the nested-guest might. Therefore, we might
5402	* get an SMI #VMEXIT here so simply ignore rather than causing a corresponding
5403	* nested-guest #VMEXIT.
5404	*
5405	* We shall import the complete state here as we may cause #VMEXITs from ring-3
5406	* while trying to inject interrupts, see comment at the top of this function.
5407	*/
5408	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_ALL);
5409	return hmR0SvmExitIntr(pVCpu, pSvmTransient);
5410	}
5411
5412	case SVM_EXIT_FERR_FREEZE:
5413	{
5414	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_FERR_FREEZE))
5415	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5416	return hmR0SvmExitFerrFreeze(pVCpu, pSvmTransient);
5417	}
5418
5419	case SVM_EXIT_INVLPG:
5420	{
5421	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_INVLPG))
5422	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5423	return hmR0SvmExitInvlpg(pVCpu, pSvmTransient);
5424	}
5425
5426	case SVM_EXIT_WBINVD:
5427	{
5428	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_WBINVD))
5429	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5430	return hmR0SvmExitWbinvd(pVCpu, pSvmTransient);
5431	}
5432
5433	case SVM_EXIT_INVD:
5434	{
5435	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_INVD))
5436	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5437	return hmR0SvmExitInvd(pVCpu, pSvmTransient);
5438	}
5439
5440	case SVM_EXIT_RDPMC:
5441	{
5442	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_RDPMC))
5443	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5444	return hmR0SvmExitRdpmc(pVCpu, pSvmTransient);
5445	}
5446
5447	default:
5448	{
5449	switch (uExitCode)
5450	{
5451	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5452	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5453	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5454	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5455	{
5456	uint8_t const uDr = uExitCode - SVM_EXIT_READ_DR0;
5457	if (HMIsGuestSvmReadDRxInterceptSet(pVCpu, uDr))
5458	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5459	return hmR0SvmExitReadDRx(pVCpu, pSvmTransient);
5460	}
5461
5462	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5463	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5464	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5465	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5466	{
5467	uint8_t const uDr = uExitCode - SVM_EXIT_WRITE_DR0;
5468	if (HMIsGuestSvmWriteDRxInterceptSet(pVCpu, uDr))
5469	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5470	return hmR0SvmExitWriteDRx(pVCpu, pSvmTransient);
5471	}
5472
5473	case SVM_EXIT_XCPT_DE:
5474	/* SVM_EXIT_XCPT_DB: / / Handled above. */
5475	/* SVM_EXIT_XCPT_NMI: / / Handled above. */
5476	/* SVM_EXIT_XCPT_BP: / / Handled above. */
5477	case SVM_EXIT_XCPT_OF:
5478	case SVM_EXIT_XCPT_BR:
5479	/* SVM_EXIT_XCPT_UD: / / Handled above. */
5480	case SVM_EXIT_XCPT_NM:
5481	case SVM_EXIT_XCPT_DF:
5482	case SVM_EXIT_XCPT_CO_SEG_OVERRUN:
5483	case SVM_EXIT_XCPT_TS:
5484	case SVM_EXIT_XCPT_NP:
5485	case SVM_EXIT_XCPT_SS:
5486	case SVM_EXIT_XCPT_GP:
5487	/* SVM_EXIT_XCPT_PF: / / Handled above. */
5488	case SVM_EXIT_XCPT_15: /* Reserved. */
5489	/* SVM_EXIT_XCPT_MF: / / Handled above. */
5490	/* SVM_EXIT_XCPT_AC: / / Handled above. */
5491	case SVM_EXIT_XCPT_MC:
5492	case SVM_EXIT_XCPT_XF:
5493	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5494	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5495	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5496	{
5497	uint8_t const uVector = uExitCode - SVM_EXIT_XCPT_0;
5498	if (HMIsGuestSvmXcptInterceptSet(pVCpu, uVector))
5499	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5500	return hmR0SvmExitXcptGeneric(pVCpu, pSvmTransient);
5501	}
5502
5503	case SVM_EXIT_XSETBV:
5504	{
5505	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_XSETBV))
5506	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5507	return hmR0SvmExitXsetbv(pVCpu, pSvmTransient);
5508	}
5509
5510	case SVM_EXIT_TASK_SWITCH:
5511	{
5512	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_TASK_SWITCH))
5513	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5514	return hmR0SvmExitTaskSwitch(pVCpu, pSvmTransient);
5515	}
5516
5517	case SVM_EXIT_IRET:
5518	{
5519	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_IRET))
5520	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5521	return hmR0SvmExitIret(pVCpu, pSvmTransient);
5522	}
5523
5524	case SVM_EXIT_SHUTDOWN:
5525	{
5526	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_SHUTDOWN))
5527	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5528	return hmR0SvmExitShutdown(pVCpu, pSvmTransient);
5529	}
5530
5531	case SVM_EXIT_VMMCALL:
5532	{
5533	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_VMMCALL))
5534	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5535	return hmR0SvmExitVmmCall(pVCpu, pSvmTransient);
5536	}
5537
5538	case SVM_EXIT_CLGI:
5539	{
5540	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_CLGI))
5541	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5542	return hmR0SvmExitClgi(pVCpu, pSvmTransient);
5543	}
5544
5545	case SVM_EXIT_STGI:
5546	{
5547	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_STGI))
5548	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5549	return hmR0SvmExitStgi(pVCpu, pSvmTransient);
5550	}
5551
5552	case SVM_EXIT_VMLOAD:
5553	{
5554	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_VMLOAD))
5555	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5556	return hmR0SvmExitVmload(pVCpu, pSvmTransient);
5557	}
5558
5559	case SVM_EXIT_VMSAVE:
5560	{
5561	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_VMSAVE))
5562	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5563	return hmR0SvmExitVmsave(pVCpu, pSvmTransient);
5564	}
5565
5566	case SVM_EXIT_INVLPGA:
5567	{
5568	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_INVLPGA))
5569	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5570	return hmR0SvmExitInvlpga(pVCpu, pSvmTransient);
5571	}
5572
5573	case SVM_EXIT_VMRUN:
5574	{
5575	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_VMRUN))
5576	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5577	return hmR0SvmExitVmrun(pVCpu, pSvmTransient);
5578	}
5579
5580	case SVM_EXIT_RSM:
5581	{
5582	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_RSM))
5583	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5584	hmR0SvmSetPendingXcptUD(pVCpu);
5585	return VINF_SUCCESS;
5586	}
5587
5588	case SVM_EXIT_SKINIT:
5589	{
5590	if (HMIsGuestSvmCtrlInterceptSet(pVCpu, SVM_CTRL_INTERCEPT_SKINIT))
5591	NST_GST_VMEXIT_CALL_RET(pVCpu, uExitCode, uExitInfo1, uExitInfo2);
5592	hmR0SvmSetPendingXcptUD(pVCpu);
5593	return VINF_SUCCESS;
5594	}
5595
5596	case SVM_EXIT_NPF:
5597	{
5598	Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
5599	return hmR0SvmExitNestedPF(pVCpu, pSvmTransient);
5600	}
5601
5602	case SVM_EXIT_INIT: /* We shouldn't get INIT signals while executing a nested-guest. */
5603	return hmR0SvmExitUnexpected(pVCpu, pSvmTransient);
5604
5605	default:
5606	{
5607	AssertMsgFailed(("hmR0SvmHandleExitNested: Unknown exit code %#x\n", pSvmTransient->u64ExitCode));
5608	pVCpu->hm.s.u32HMError = pSvmTransient->u64ExitCode;
5609	return VERR_SVM_UNKNOWN_EXIT;
5610	}
5611	}
5612	}
5613	}
5614	/* not reached */
5615
5616	#undef NST_GST_VMEXIT_CALL_RET
5617	}
5618	#endif
5619
5620
5621	/**
5622	* Handles a guest \#VMEXIT (for all EXITCODE values except SVM_EXIT_INVALID).
5623	*
5624	* @returns VBox status code (informational status codes included).
5625	* @param pVCpu The cross context virtual CPU structure.
5626	* @param pSvmTransient Pointer to the SVM transient structure.
5627	*/
5628	static int hmR0SvmHandleExit(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
5629	{
5630	Assert(pSvmTransient->u64ExitCode != SVM_EXIT_INVALID);
5631	Assert(pSvmTransient->u64ExitCode <= SVM_EXIT_MAX);
5632
5633	#ifdef DEBUG_ramshankar
5634	# define VMEXIT_CALL_RET(a_fDbg, a_CallExpr) \
5635	do { \
5636	if ((a_fDbg) == 1) \
5637	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL); \
5638	int rc = a_CallExpr; \
5639	if ((a_fDbg) == 1) \
5640	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST); \
5641	return rc; \
5642	} while (0)
5643	#else
5644	# define VMEXIT_CALL_RET(a_fDbg, a_CallExpr) return a_CallExpr
5645	#endif
5646
5647	/*
5648	* The ordering of the case labels is based on most-frequently-occurring #VMEXITs
5649	* for most guests under normal workloads (for some definition of "normal").
5650	*/
5651	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
5652	switch (uExitCode)
5653	{
5654	case SVM_EXIT_NPF: VMEXIT_CALL_RET(0, hmR0SvmExitNestedPF(pVCpu, pSvmTransient));
5655	case SVM_EXIT_IOIO: VMEXIT_CALL_RET(0, hmR0SvmExitIOInstr(pVCpu, pSvmTransient));
5656	case SVM_EXIT_RDTSC: VMEXIT_CALL_RET(0, hmR0SvmExitRdtsc(pVCpu, pSvmTransient));
5657	case SVM_EXIT_RDTSCP: VMEXIT_CALL_RET(0, hmR0SvmExitRdtscp(pVCpu, pSvmTransient));
5658	case SVM_EXIT_CPUID: VMEXIT_CALL_RET(0, hmR0SvmExitCpuid(pVCpu, pSvmTransient));
5659	case SVM_EXIT_XCPT_PF: VMEXIT_CALL_RET(0, hmR0SvmExitXcptPF(pVCpu, pSvmTransient));
5660	case SVM_EXIT_MSR: VMEXIT_CALL_RET(0, hmR0SvmExitMsr(pVCpu, pSvmTransient));
5661	case SVM_EXIT_MONITOR: VMEXIT_CALL_RET(0, hmR0SvmExitMonitor(pVCpu, pSvmTransient));
5662	case SVM_EXIT_MWAIT: VMEXIT_CALL_RET(0, hmR0SvmExitMwait(pVCpu, pSvmTransient));
5663	case SVM_EXIT_HLT: VMEXIT_CALL_RET(0, hmR0SvmExitHlt(pVCpu, pSvmTransient));
5664
5665	case SVM_EXIT_XCPT_NMI: /* Should not occur, SVM_EXIT_NMI is used instead. */
5666	case SVM_EXIT_INTR:
5667	case SVM_EXIT_NMI: VMEXIT_CALL_RET(0, hmR0SvmExitIntr(pVCpu, pSvmTransient));
5668
5669	case SVM_EXIT_READ_CR0:
5670	case SVM_EXIT_READ_CR3:
5671	case SVM_EXIT_READ_CR4: VMEXIT_CALL_RET(0, hmR0SvmExitReadCRx(pVCpu, pSvmTransient));
5672
5673	case SVM_EXIT_CR0_SEL_WRITE:
5674	case SVM_EXIT_WRITE_CR0:
5675	case SVM_EXIT_WRITE_CR3:
5676	case SVM_EXIT_WRITE_CR4:
5677	case SVM_EXIT_WRITE_CR8: VMEXIT_CALL_RET(0, hmR0SvmExitWriteCRx(pVCpu, pSvmTransient));
5678
5679	case SVM_EXIT_VINTR: VMEXIT_CALL_RET(0, hmR0SvmExitVIntr(pVCpu, pSvmTransient));
5680	case SVM_EXIT_PAUSE: VMEXIT_CALL_RET(0, hmR0SvmExitPause(pVCpu, pSvmTransient));
5681	case SVM_EXIT_VMMCALL: VMEXIT_CALL_RET(0, hmR0SvmExitVmmCall(pVCpu, pSvmTransient));
5682	case SVM_EXIT_INVLPG: VMEXIT_CALL_RET(0, hmR0SvmExitInvlpg(pVCpu, pSvmTransient));
5683	case SVM_EXIT_WBINVD: VMEXIT_CALL_RET(0, hmR0SvmExitWbinvd(pVCpu, pSvmTransient));
5684	case SVM_EXIT_INVD: VMEXIT_CALL_RET(0, hmR0SvmExitInvd(pVCpu, pSvmTransient));
5685	case SVM_EXIT_RDPMC: VMEXIT_CALL_RET(0, hmR0SvmExitRdpmc(pVCpu, pSvmTransient));
5686	case SVM_EXIT_IRET: VMEXIT_CALL_RET(0, hmR0SvmExitIret(pVCpu, pSvmTransient));
5687	case SVM_EXIT_XCPT_UD: VMEXIT_CALL_RET(0, hmR0SvmExitXcptUD(pVCpu, pSvmTransient));
5688	case SVM_EXIT_XCPT_MF: VMEXIT_CALL_RET(0, hmR0SvmExitXcptMF(pVCpu, pSvmTransient));
5689	case SVM_EXIT_XCPT_DB: VMEXIT_CALL_RET(0, hmR0SvmExitXcptDB(pVCpu, pSvmTransient));
5690	case SVM_EXIT_XCPT_AC: VMEXIT_CALL_RET(0, hmR0SvmExitXcptAC(pVCpu, pSvmTransient));
5691	case SVM_EXIT_XCPT_BP: VMEXIT_CALL_RET(0, hmR0SvmExitXcptBP(pVCpu, pSvmTransient));
5692	case SVM_EXIT_XSETBV: VMEXIT_CALL_RET(0, hmR0SvmExitXsetbv(pVCpu, pSvmTransient));
5693	case SVM_EXIT_FERR_FREEZE: VMEXIT_CALL_RET(0, hmR0SvmExitFerrFreeze(pVCpu, pSvmTransient));
5694
5695	default:
5696	{
5697	switch (pSvmTransient->u64ExitCode)
5698	{
5699	case SVM_EXIT_READ_DR0: case SVM_EXIT_READ_DR1: case SVM_EXIT_READ_DR2: case SVM_EXIT_READ_DR3:
5700	case SVM_EXIT_READ_DR6: case SVM_EXIT_READ_DR7: case SVM_EXIT_READ_DR8: case SVM_EXIT_READ_DR9:
5701	case SVM_EXIT_READ_DR10: case SVM_EXIT_READ_DR11: case SVM_EXIT_READ_DR12: case SVM_EXIT_READ_DR13:
5702	case SVM_EXIT_READ_DR14: case SVM_EXIT_READ_DR15:
5703	VMEXIT_CALL_RET(0, hmR0SvmExitReadDRx(pVCpu, pSvmTransient));
5704
5705	case SVM_EXIT_WRITE_DR0: case SVM_EXIT_WRITE_DR1: case SVM_EXIT_WRITE_DR2: case SVM_EXIT_WRITE_DR3:
5706	case SVM_EXIT_WRITE_DR6: case SVM_EXIT_WRITE_DR7: case SVM_EXIT_WRITE_DR8: case SVM_EXIT_WRITE_DR9:
5707	case SVM_EXIT_WRITE_DR10: case SVM_EXIT_WRITE_DR11: case SVM_EXIT_WRITE_DR12: case SVM_EXIT_WRITE_DR13:
5708	case SVM_EXIT_WRITE_DR14: case SVM_EXIT_WRITE_DR15:
5709	VMEXIT_CALL_RET(0, hmR0SvmExitWriteDRx(pVCpu, pSvmTransient));
5710
5711	case SVM_EXIT_TASK_SWITCH: VMEXIT_CALL_RET(0, hmR0SvmExitTaskSwitch(pVCpu, pSvmTransient));
5712	case SVM_EXIT_SHUTDOWN: VMEXIT_CALL_RET(0, hmR0SvmExitShutdown(pVCpu, pSvmTransient));
5713
5714	case SVM_EXIT_SMI:
5715	case SVM_EXIT_INIT:
5716	{
5717	/*
5718	* We don't intercept SMIs. As for INIT signals, it really shouldn't ever happen here.
5719	* If it ever does, we want to know about it so log the exit code and bail.
5720	*/
5721	VMEXIT_CALL_RET(0, hmR0SvmExitUnexpected(pVCpu, pSvmTransient));
5722	}
5723
5724	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
5725	case SVM_EXIT_CLGI: VMEXIT_CALL_RET(0, hmR0SvmExitClgi(pVCpu, pSvmTransient));
5726	case SVM_EXIT_STGI: VMEXIT_CALL_RET(0, hmR0SvmExitStgi(pVCpu, pSvmTransient));
5727	case SVM_EXIT_VMLOAD: VMEXIT_CALL_RET(0, hmR0SvmExitVmload(pVCpu, pSvmTransient));
5728	case SVM_EXIT_VMSAVE: VMEXIT_CALL_RET(0, hmR0SvmExitVmsave(pVCpu, pSvmTransient));
5729	case SVM_EXIT_INVLPGA: VMEXIT_CALL_RET(0, hmR0SvmExitInvlpga(pVCpu, pSvmTransient));
5730	case SVM_EXIT_VMRUN: VMEXIT_CALL_RET(0, hmR0SvmExitVmrun(pVCpu, pSvmTransient));
5731	#else
5732	case SVM_EXIT_CLGI:
5733	case SVM_EXIT_STGI:
5734	case SVM_EXIT_VMLOAD:
5735	case SVM_EXIT_VMSAVE:
5736	case SVM_EXIT_INVLPGA:
5737	case SVM_EXIT_VMRUN:
5738	#endif
5739	case SVM_EXIT_RSM:
5740	case SVM_EXIT_SKINIT:
5741	{
5742	hmR0SvmSetPendingXcptUD(pVCpu);
5743	return VINF_SUCCESS;
5744	}
5745
5746	#ifdef HMSVM_ALWAYS_TRAP_ALL_XCPTS
5747	case SVM_EXIT_XCPT_DE:
5748	/* SVM_EXIT_XCPT_DB: / / Handled above. */
5749	/* SVM_EXIT_XCPT_NMI: / / Handled above. */
5750	/* SVM_EXIT_XCPT_BP: / / Handled above. */
5751	case SVM_EXIT_XCPT_OF:
5752	case SVM_EXIT_XCPT_BR:
5753	/* SVM_EXIT_XCPT_UD: / / Handled above. */
5754	case SVM_EXIT_XCPT_NM:
5755	case SVM_EXIT_XCPT_DF:
5756	case SVM_EXIT_XCPT_CO_SEG_OVERRUN:
5757	case SVM_EXIT_XCPT_TS:
5758	case SVM_EXIT_XCPT_NP:
5759	case SVM_EXIT_XCPT_SS:
5760	case SVM_EXIT_XCPT_GP:
5761	/* SVM_EXIT_XCPT_PF: */
5762	case SVM_EXIT_XCPT_15: /* Reserved. */
5763	/* SVM_EXIT_XCPT_MF: / / Handled above. */
5764	/* SVM_EXIT_XCPT_AC: / / Handled above. */
5765	case SVM_EXIT_XCPT_MC:
5766	case SVM_EXIT_XCPT_XF:
5767	case SVM_EXIT_XCPT_20: case SVM_EXIT_XCPT_21: case SVM_EXIT_XCPT_22: case SVM_EXIT_XCPT_23:
5768	case SVM_EXIT_XCPT_24: case SVM_EXIT_XCPT_25: case SVM_EXIT_XCPT_26: case SVM_EXIT_XCPT_27:
5769	case SVM_EXIT_XCPT_28: case SVM_EXIT_XCPT_29: case SVM_EXIT_XCPT_30: case SVM_EXIT_XCPT_31:
5770	VMEXIT_CALL_RET(0, hmR0SvmExitXcptGeneric(pVCpu, pSvmTransient));
5771	#endif /* HMSVM_ALWAYS_TRAP_ALL_XCPTS */
5772
5773	default:
5774	{
5775	AssertMsgFailed(("hmR0SvmHandleExit: Unknown exit code %#RX64\n", uExitCode));
5776	pVCpu->hm.s.u32HMError = uExitCode;
5777	return VERR_SVM_UNKNOWN_EXIT;
5778	}
5779	}
5780	}
5781	}
5782	/* not reached */
5783	#undef VMEXIT_CALL_RET
5784	}
5785
5786
5787	#ifdef VBOX_STRICT
5788	/* Is there some generic IPRT define for this that are not in Runtime/internal/\* ?? */
5789	# define HMSVM_ASSERT_PREEMPT_CPUID_VAR() \
5790	RTCPUID const idAssertCpu = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId()
5791
5792	# define HMSVM_ASSERT_PREEMPT_CPUID() \
5793	do \
5794	{ \
5795	RTCPUID const idAssertCpuNow = RTThreadPreemptIsEnabled(NIL_RTTHREAD) ? NIL_RTCPUID : RTMpCpuId(); \
5796	AssertMsg(idAssertCpu == idAssertCpuNow, ("SVM %#x, %#x\n", idAssertCpu, idAssertCpuNow)); \
5797	} while (0)
5798
5799	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pSvmTransient) \
5800	do { \
5801	AssertPtr((a_pVCpu)); \
5802	AssertPtr((a_pSvmTransient)); \
5803	Assert(ASMIntAreEnabled()); \
5804	HMSVM_ASSERT_PREEMPT_SAFE((a_pVCpu)); \
5805	HMSVM_ASSERT_PREEMPT_CPUID_VAR(); \
5806	Log4Func(("vcpu[%u] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-\n", (a_pVCpu)->idCpu)); \
5807	HMSVM_ASSERT_PREEMPT_SAFE((a_pVCpu)); \
5808	if (VMMR0IsLogFlushDisabled((a_pVCpu))) \
5809	HMSVM_ASSERT_PREEMPT_CPUID(); \
5810	} while (0)
5811	#else
5812	# define HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pSvmTransient) \
5813	do { \
5814	RT_NOREF2(a_pVCpu, a_pSvmTransient); \
5815	} while (0)
5816	#endif
5817
5818
5819	/**
5820	* Gets the IEM exception flags for the specified SVM event.
5821	*
5822	* @returns The IEM exception flags.
5823	* @param pEvent Pointer to the SVM event.
5824	*
5825	* @remarks This function currently only constructs flags required for
5826	* IEMEvaluateRecursiveXcpt and not the complete flags (e.g. error-code
5827	* and CR2 aspects of an exception are not included).
5828	*/
5829	static uint32_t hmR0SvmGetIemXcptFlags(PCSVMEVENT pEvent)
5830	{
5831	uint8_t const uEventType = pEvent->n.u3Type;
5832	uint32_t fIemXcptFlags;
5833	switch (uEventType)
5834	{
5835	case SVM_EVENT_EXCEPTION:
5836	/*
5837	* Only INT3 and INTO instructions can raise #BP and #OF exceptions.
5838	* See AMD spec. Table 8-1. "Interrupt Vector Source and Cause".
5839	*/
5840	if (pEvent->n.u8Vector == X86_XCPT_BP)
5841	{
5842	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_BP_INSTR;
5843	break;
5844	}
5845	if (pEvent->n.u8Vector == X86_XCPT_OF)
5846	{
5847	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT \| IEM_XCPT_FLAGS_OF_INSTR;
5848	break;
5849	}
5850	/** @todo How do we distinguish ICEBP \#DB from the regular one? */
5851	RT_FALL_THRU();
5852	case SVM_EVENT_NMI:
5853	fIemXcptFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5854	break;
5855
5856	case SVM_EVENT_EXTERNAL_IRQ:
5857	fIemXcptFlags = IEM_XCPT_FLAGS_T_EXT_INT;
5858	break;
5859
5860	case SVM_EVENT_SOFTWARE_INT:
5861	fIemXcptFlags = IEM_XCPT_FLAGS_T_SOFT_INT;
5862	break;
5863
5864	default:
5865	fIemXcptFlags = 0;
5866	AssertMsgFailed(("Unexpected event type! uEventType=%#x uVector=%#x", uEventType, pEvent->n.u8Vector));
5867	break;
5868	}
5869	return fIemXcptFlags;
5870	}
5871
5872
5873	/**
5874	* Handle a condition that occurred while delivering an event through the guest
5875	* IDT.
5876	*
5877	* @returns VBox status code (informational error codes included).
5878	* @retval VINF_SUCCESS if we should continue handling the \#VMEXIT.
5879	* @retval VINF_HM_DOUBLE_FAULT if a \#DF condition was detected and we ought to
5880	* continue execution of the guest which will delivery the \#DF.
5881	* @retval VINF_EM_RESET if we detected a triple-fault condition.
5882	* @retval VERR_EM_GUEST_CPU_HANG if we detected a guest CPU hang.
5883	*
5884	* @param pVCpu The cross context virtual CPU structure.
5885	* @param pSvmTransient Pointer to the SVM transient structure.
5886	*
5887	* @remarks No-long-jump zone!!!
5888	*/
5889	static int hmR0SvmCheckExitDueToEventDelivery(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
5890	{
5891	int rc = VINF_SUCCESS;
5892	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
5893	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR2);
5894
5895	Log4(("EXITINTINFO: Pending vectoring event %#RX64 Valid=%RTbool ErrValid=%RTbool Err=%#RX32 Type=%u Vector=%u\n",
5896	pVmcb->ctrl.ExitIntInfo.u, !!pVmcb->ctrl.ExitIntInfo.n.u1Valid, !!pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid,
5897	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, pVmcb->ctrl.ExitIntInfo.n.u3Type, pVmcb->ctrl.ExitIntInfo.n.u8Vector));
5898
5899	/*
5900	* The EXITINTINFO (if valid) contains the prior exception (IDT vector) that was trying to
5901	* be delivered to the guest which caused a #VMEXIT which was intercepted (Exit vector).
5902	*
5903	* See AMD spec. 15.7.3 "EXITINFO Pseudo-Code".
5904	*/
5905	if (pVmcb->ctrl.ExitIntInfo.n.u1Valid)
5906	{
5907	IEMXCPTRAISE enmRaise;
5908	IEMXCPTRAISEINFO fRaiseInfo;
5909	bool const fExitIsHwXcpt = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0 <= SVM_EXIT_XCPT_31;
5910	uint8_t const uIdtVector = pVmcb->ctrl.ExitIntInfo.n.u8Vector;
5911	if (fExitIsHwXcpt)
5912	{
5913	uint8_t const uExitVector = pSvmTransient->u64ExitCode - SVM_EXIT_XCPT_0;
5914	uint32_t const fIdtVectorFlags = hmR0SvmGetIemXcptFlags(&pVmcb->ctrl.ExitIntInfo);
5915	uint32_t const fExitVectorFlags = IEM_XCPT_FLAGS_T_CPU_XCPT;
5916	enmRaise = IEMEvaluateRecursiveXcpt(pVCpu, fIdtVectorFlags, uIdtVector, fExitVectorFlags, uExitVector, &fRaiseInfo);
5917	}
5918	else
5919	{
5920	/*
5921	* If delivery of an event caused a #VMEXIT that is not an exception (e.g. #NPF)
5922	* then we end up here.
5923	*
5924	* If the event was:
5925	* - a software interrupt, we can re-execute the instruction which will
5926	* regenerate the event.
5927	* - an NMI, we need to clear NMI blocking and re-inject the NMI.
5928	* - a hardware exception or external interrupt, we re-inject it.
5929	*/
5930	fRaiseInfo = IEMXCPTRAISEINFO_NONE;
5931	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_SOFTWARE_INT)
5932	enmRaise = IEMXCPTRAISE_REEXEC_INSTR;
5933	else
5934	enmRaise = IEMXCPTRAISE_PREV_EVENT;
5935	}
5936
5937	switch (enmRaise)
5938	{
5939	case IEMXCPTRAISE_CURRENT_XCPT:
5940	case IEMXCPTRAISE_PREV_EVENT:
5941	{
5942	/* For software interrupts, we shall re-execute the instruction. */
5943	if (!(fRaiseInfo & IEMXCPTRAISEINFO_SOFT_INT_XCPT))
5944	{
5945	RTGCUINTPTR GCPtrFaultAddress = 0;
5946
5947	/* If we are re-injecting an NMI, clear NMI blocking. */
5948	if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
5949	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
5950
5951	/* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
5952	if (fRaiseInfo & (IEMXCPTRAISEINFO_EXT_INT_PF \| IEMXCPTRAISEINFO_NMI_PF))
5953	{
5954	pSvmTransient->fVectoringPF = true;
5955	Log4Func(("IDT: Pending vectoring #PF due to delivery of Ext-Int/NMI. uCR2=%#RX64\n",
5956	pVCpu->cpum.GstCtx.cr2));
5957	}
5958	else if ( pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_EXCEPTION
5959	&& uIdtVector == X86_XCPT_PF)
5960	{
5961	/*
5962	* If the previous exception was a #PF, we need to recover the CR2 value.
5963	* This can't happen with shadow paging.
5964	*/
5965	GCPtrFaultAddress = pVCpu->cpum.GstCtx.cr2;
5966	}
5967
5968	/*
5969	* Without nested paging, when uExitVector is #PF, CR2 value will be updated from the VMCB's
5970	* exit info. fields, if it's a guest #PF, see hmR0SvmExitXcptPF().
5971	*/
5972	Assert(pVmcb->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT);
5973	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
5974	hmR0SvmSetPendingEvent(pVCpu, &pVmcb->ctrl.ExitIntInfo, GCPtrFaultAddress);
5975
5976	Log4Func(("IDT: Pending vectoring event %#RX64 ErrValid=%RTbool Err=%#RX32 GCPtrFaultAddress=%#RX64\n",
5977	pVmcb->ctrl.ExitIntInfo.u, RT_BOOL(pVmcb->ctrl.ExitIntInfo.n.u1ErrorCodeValid),
5978	pVmcb->ctrl.ExitIntInfo.n.u32ErrorCode, GCPtrFaultAddress));
5979	}
5980	break;
5981	}
5982
5983	case IEMXCPTRAISE_REEXEC_INSTR:
5984	{
5985	Assert(rc == VINF_SUCCESS);
5986	break;
5987	}
5988
5989	case IEMXCPTRAISE_DOUBLE_FAULT:
5990	{
5991	/*
5992	* Determing a vectoring double #PF condition. Used later, when PGM evaluates
5993	* the second #PF as a guest #PF (and not a shadow #PF) and needs to be
5994	* converted into a #DF.
5995	*/
5996	if (fRaiseInfo & IEMXCPTRAISEINFO_PF_PF)
5997	{
5998	Log4Func(("IDT: Pending vectoring double #PF uCR2=%#RX64\n", pVCpu->cpum.GstCtx.cr2));
5999	pSvmTransient->fVectoringDoublePF = true;
6000	Assert(rc == VINF_SUCCESS);
6001	}
6002	else
6003	{
6004	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingReflect);
6005	hmR0SvmSetPendingXcptDF(pVCpu);
6006	rc = VINF_HM_DOUBLE_FAULT;
6007	}
6008	break;
6009	}
6010
6011	case IEMXCPTRAISE_TRIPLE_FAULT:
6012	{
6013	rc = VINF_EM_RESET;
6014	break;
6015	}
6016
6017	case IEMXCPTRAISE_CPU_HANG:
6018	{
6019	rc = VERR_EM_GUEST_CPU_HANG;
6020	break;
6021	}
6022
6023	default:
6024	AssertMsgFailedBreakStmt(("Bogus enmRaise value: %d (%#x)\n", enmRaise, enmRaise), rc = VERR_SVM_IPE_2);
6025	}
6026	}
6027	Assert(rc == VINF_SUCCESS \|\| rc == VINF_HM_DOUBLE_FAULT \|\| rc == VINF_EM_RESET \|\| rc == VERR_EM_GUEST_CPU_HANG);
6028	return rc;
6029	}
6030
6031
6032	/**
6033	* Advances the guest RIP by the number of bytes specified in @a cb.
6034	*
6035	* @param pVCpu The cross context virtual CPU structure.
6036	* @param cb RIP increment value in bytes.
6037	*/
6038	DECLINLINE(void) hmR0SvmAdvanceRip(PVMCPU pVCpu, uint32_t cb)
6039	{
6040	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6041	pCtx->rip += cb;
6042
6043	/* Update interrupt shadow. */
6044	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
6045	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
6046	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
6047	}
6048
6049
6050	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
6051	/* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- #VMEXIT handlers -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
6052	/* -=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
6053
6054	/** @name \#VMEXIT handlers.
6055	* @{
6056	*/
6057
6058	/**
6059	* \#VMEXIT handler for external interrupts, NMIs, FPU assertion freeze and INIT
6060	* signals (SVM_EXIT_INTR, SVM_EXIT_NMI, SVM_EXIT_FERR_FREEZE, SVM_EXIT_INIT).
6061	*/
6062	HMSVM_EXIT_DECL hmR0SvmExitIntr(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6063	{
6064	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6065
6066	if (pSvmTransient->u64ExitCode == SVM_EXIT_NMI)
6067	STAM_REL_COUNTER_INC(&pVCpu->hm.s.StatExitHostNmiInGC);
6068	else if (pSvmTransient->u64ExitCode == SVM_EXIT_INTR)
6069	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
6070
6071	/*
6072	* AMD-V has no preemption timer and the generic periodic preemption timer has no way to
6073	* signal -before- the timer fires if the current interrupt is our own timer or a some
6074	* other host interrupt. We also cannot examine what interrupt it is until the host
6075	* actually take the interrupt.
6076	*
6077	* Going back to executing guest code here unconditionally causes random scheduling
6078	* problems (observed on an AMD Phenom 9850 Quad-Core on Windows 64-bit host).
6079	*/
6080	return VINF_EM_RAW_INTERRUPT;
6081	}
6082
6083
6084	/**
6085	* \#VMEXIT handler for WBINVD (SVM_EXIT_WBINVD). Conditional \#VMEXIT.
6086	*/
6087	HMSVM_EXIT_DECL hmR0SvmExitWbinvd(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6088	{
6089	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6090
6091	VBOXSTRICTRC rcStrict;
6092	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6093	if (fSupportsNextRipSave)
6094	{
6095	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6096	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6097	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6098	rcStrict = IEMExecDecodedWbinvd(pVCpu, cbInstr);
6099	}
6100	else
6101	{
6102	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6103	rcStrict = IEMExecOne(pVCpu);
6104	}
6105
6106	if (rcStrict == VINF_IEM_RAISED_XCPT)
6107	{
6108	rcStrict = VINF_SUCCESS;
6109	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6110	}
6111	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6112	return VBOXSTRICTRC_TODO(rcStrict);
6113	}
6114
6115
6116	/**
6117	* \#VMEXIT handler for INVD (SVM_EXIT_INVD). Unconditional \#VMEXIT.
6118	*/
6119	HMSVM_EXIT_DECL hmR0SvmExitInvd(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6120	{
6121	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6122
6123	VBOXSTRICTRC rcStrict;
6124	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6125	if (fSupportsNextRipSave)
6126	{
6127	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6128	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6129	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6130	rcStrict = IEMExecDecodedInvd(pVCpu, cbInstr);
6131	}
6132	else
6133	{
6134	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6135	rcStrict = IEMExecOne(pVCpu);
6136	}
6137
6138	if (rcStrict == VINF_IEM_RAISED_XCPT)
6139	{
6140	rcStrict = VINF_SUCCESS;
6141	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6142	}
6143	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6144	return VBOXSTRICTRC_TODO(rcStrict);
6145	}
6146
6147
6148	/**
6149	* \#VMEXIT handler for INVD (SVM_EXIT_CPUID). Conditional \#VMEXIT.
6150	*/
6151	HMSVM_EXIT_DECL hmR0SvmExitCpuid(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6152	{
6153	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6154
6155	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RCX);
6156	VBOXSTRICTRC rcStrict;
6157	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
6158	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_CPUID),
6159	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
6160	if (!pExitRec)
6161	{
6162	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6163	if (fSupportsNextRipSave)
6164	{
6165	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6166	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6167	rcStrict = IEMExecDecodedCpuid(pVCpu, cbInstr);
6168	}
6169	else
6170	{
6171	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6172	rcStrict = IEMExecOne(pVCpu);
6173	}
6174
6175	if (rcStrict == VINF_IEM_RAISED_XCPT)
6176	{
6177	rcStrict = VINF_SUCCESS;
6178	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6179	}
6180	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6181	}
6182	else
6183	{
6184	/*
6185	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
6186	*/
6187	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6188
6189	Log4(("CpuIdExit/%u: %04x:%08RX64: %#x/%#x -> EMHistoryExec\n",
6190	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eax, pVCpu->cpum.GstCtx.ecx));
6191
6192	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
6193
6194	Log4(("CpuIdExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
6195	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
6196	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
6197	}
6198	return VBOXSTRICTRC_TODO(rcStrict);
6199	}
6200
6201
6202	/**
6203	* \#VMEXIT handler for RDTSC (SVM_EXIT_RDTSC). Conditional \#VMEXIT.
6204	*/
6205	HMSVM_EXIT_DECL hmR0SvmExitRdtsc(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6206	{
6207	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6208
6209	VBOXSTRICTRC rcStrict;
6210	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6211	if (fSupportsNextRipSave)
6212	{
6213	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4);
6214	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6215	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6216	rcStrict = IEMExecDecodedRdtsc(pVCpu, cbInstr);
6217	}
6218	else
6219	{
6220	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6221	rcStrict = IEMExecOne(pVCpu);
6222	}
6223
6224	if (rcStrict == VINF_SUCCESS)
6225	pSvmTransient->fUpdateTscOffsetting = true;
6226	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6227	{
6228	rcStrict = VINF_SUCCESS;
6229	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6230	}
6231	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6232	return VBOXSTRICTRC_TODO(rcStrict);
6233	}
6234
6235
6236	/**
6237	* \#VMEXIT handler for RDTSCP (SVM_EXIT_RDTSCP). Conditional \#VMEXIT.
6238	*/
6239	HMSVM_EXIT_DECL hmR0SvmExitRdtscp(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6240	{
6241	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6242
6243	VBOXSTRICTRC rcStrict;
6244	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6245	if (fSupportsNextRipSave)
6246	{
6247	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_TSC_AUX);
6248	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6249	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6250	rcStrict = IEMExecDecodedRdtscp(pVCpu, cbInstr);
6251	}
6252	else
6253	{
6254	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6255	rcStrict = IEMExecOne(pVCpu);
6256	}
6257
6258	if (rcStrict == VINF_SUCCESS)
6259	pSvmTransient->fUpdateTscOffsetting = true;
6260	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6261	{
6262	rcStrict = VINF_SUCCESS;
6263	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6264	}
6265	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6266	return VBOXSTRICTRC_TODO(rcStrict);
6267	}
6268
6269
6270	/**
6271	* \#VMEXIT handler for RDPMC (SVM_EXIT_RDPMC). Conditional \#VMEXIT.
6272	*/
6273	HMSVM_EXIT_DECL hmR0SvmExitRdpmc(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6274	{
6275	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6276
6277	VBOXSTRICTRC rcStrict;
6278	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6279	if (fSupportsNextRipSave)
6280	{
6281	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR4);
6282	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6283	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6284	rcStrict = IEMExecDecodedRdpmc(pVCpu, cbInstr);
6285	}
6286	else
6287	{
6288	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6289	rcStrict = IEMExecOne(pVCpu);
6290	}
6291
6292	if (rcStrict == VINF_IEM_RAISED_XCPT)
6293	{
6294	rcStrict = VINF_SUCCESS;
6295	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6296	}
6297	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6298	return VBOXSTRICTRC_TODO(rcStrict);
6299	}
6300
6301
6302	/**
6303	* \#VMEXIT handler for INVLPG (SVM_EXIT_INVLPG). Conditional \#VMEXIT.
6304	*/
6305	HMSVM_EXIT_DECL hmR0SvmExitInvlpg(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6306	{
6307	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6308	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
6309
6310	VBOXSTRICTRC rcStrict;
6311	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6312	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6313	if ( fSupportsDecodeAssists
6314	&& fSupportsNextRipSave)
6315	{
6316	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK);
6317	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6318	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6319	RTGCPTR const GCPtrPage = pVmcb->ctrl.u64ExitInfo1;
6320	rcStrict = IEMExecDecodedInvlpg(pVCpu, cbInstr, GCPtrPage);
6321	}
6322	else
6323	{
6324	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6325	rcStrict = IEMExecOne(pVCpu);
6326	}
6327
6328	if (rcStrict == VINF_IEM_RAISED_XCPT)
6329	{
6330	rcStrict = VINF_SUCCESS;
6331	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6332	}
6333	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6334	return VBOXSTRICTRC_VAL(rcStrict);
6335	}
6336
6337
6338	/**
6339	* \#VMEXIT handler for HLT (SVM_EXIT_HLT). Conditional \#VMEXIT.
6340	*/
6341	HMSVM_EXIT_DECL hmR0SvmExitHlt(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6342	{
6343	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6344
6345	VBOXSTRICTRC rcStrict;
6346	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6347	if (fSupportsNextRipSave)
6348	{
6349	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6350	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6351	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6352	rcStrict = IEMExecDecodedHlt(pVCpu, cbInstr);
6353	}
6354	else
6355	{
6356	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6357	rcStrict = IEMExecOne(pVCpu);
6358	}
6359
6360	if ( rcStrict == VINF_EM_HALT
6361	\|\| rcStrict == VINF_SUCCESS)
6362	rcStrict = EMShouldContinueAfterHalt(pVCpu, &pVCpu->cpum.GstCtx) ? VINF_SUCCESS : VINF_EM_HALT;
6363	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6364	{
6365	rcStrict = VINF_SUCCESS;
6366	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6367	}
6368	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6369	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitHlt);
6370	if (rcStrict != VINF_SUCCESS)
6371	STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHltToR3);
6372	return VBOXSTRICTRC_VAL(rcStrict);;
6373	}
6374
6375
6376	/**
6377	* \#VMEXIT handler for MONITOR (SVM_EXIT_MONITOR). Conditional \#VMEXIT.
6378	*/
6379	HMSVM_EXIT_DECL hmR0SvmExitMonitor(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6380	{
6381	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6382
6383	/*
6384	* If the instruction length is supplied by the CPU is 3 bytes, we can be certain that no
6385	* segment override prefix is present (and thus use the default segment DS). Otherwise, a
6386	* segment override prefix or other prefixes might be used, in which case we fallback to
6387	* IEMExecOne() to figure out.
6388	*/
6389	VBOXSTRICTRC rcStrict;
6390	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6391	uint8_t const cbInstr = hmR0SvmSupportsNextRipSave(pVCpu) ? pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip : 0;
6392	if (cbInstr)
6393	{
6394	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_DS);
6395	rcStrict = IEMExecDecodedMonitor(pVCpu, cbInstr);
6396	}
6397	else
6398	{
6399	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6400	rcStrict = IEMExecOne(pVCpu);
6401	}
6402
6403	if (rcStrict == VINF_IEM_RAISED_XCPT)
6404	{
6405	rcStrict = VINF_SUCCESS;
6406	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6407	}
6408	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6409	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMonitor);
6410	return VBOXSTRICTRC_TODO(rcStrict);
6411	}
6412
6413
6414	/**
6415	* \#VMEXIT handler for MWAIT (SVM_EXIT_MWAIT). Conditional \#VMEXIT.
6416	*/
6417	HMSVM_EXIT_DECL hmR0SvmExitMwait(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6418	{
6419	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6420
6421	VBOXSTRICTRC rcStrict;
6422	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6423	if (fSupportsNextRipSave)
6424	{
6425	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
6426	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6427	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6428	rcStrict = IEMExecDecodedMwait(pVCpu, cbInstr);
6429	}
6430	else
6431	{
6432	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6433	rcStrict = IEMExecOne(pVCpu);
6434	}
6435
6436	if ( rcStrict == VINF_EM_HALT
6437	&& EMMonitorWaitShouldContinue(pVCpu, &pVCpu->cpum.GstCtx))
6438	rcStrict = VINF_SUCCESS;
6439	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6440	{
6441	rcStrict = VINF_SUCCESS;
6442	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6443	}
6444	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6445	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitMwait);
6446	return VBOXSTRICTRC_TODO(rcStrict);
6447	}
6448
6449
6450	/**
6451	* \#VMEXIT handler for shutdown (triple-fault) (SVM_EXIT_SHUTDOWN). Conditional
6452	* \#VMEXIT.
6453	*/
6454	HMSVM_EXIT_DECL hmR0SvmExitShutdown(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6455	{
6456	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6457	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6458	return VINF_EM_RESET;
6459	}
6460
6461
6462	/**
6463	* \#VMEXIT handler for unexpected exits. Conditional \#VMEXIT.
6464	*/
6465	HMSVM_EXIT_DECL hmR0SvmExitUnexpected(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6466	{
6467	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6468	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6469	AssertMsgFailed(("hmR0SvmExitUnexpected: ExitCode=%#RX64 uExitInfo1=%#RX64 uExitInfo2=%#RX64\n", pSvmTransient->u64ExitCode,
6470	pVmcb->ctrl.u64ExitInfo1, pVmcb->ctrl.u64ExitInfo2));
6471	RT_NOREF(pVmcb);
6472	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6473	return VERR_SVM_UNEXPECTED_EXIT;
6474	}
6475
6476
6477	/**
6478	* \#VMEXIT handler for CRx reads (SVM_EXIT_READ_CR*). Conditional \#VMEXIT.
6479	*/
6480	HMSVM_EXIT_DECL hmR0SvmExitReadCRx(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6481	{
6482	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6483
6484	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6485	Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6486	#ifdef VBOX_WITH_STATISTICS
6487	switch (pSvmTransient->u64ExitCode)
6488	{
6489	case SVM_EXIT_READ_CR0: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Read); break;
6490	case SVM_EXIT_READ_CR2: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Read); break;
6491	case SVM_EXIT_READ_CR3: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Read); break;
6492	case SVM_EXIT_READ_CR4: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Read); break;
6493	case SVM_EXIT_READ_CR8: STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Read); break;
6494	}
6495	#endif
6496
6497	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6498	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6499	if ( fSupportsDecodeAssists
6500	&& fSupportsNextRipSave)
6501	{
6502	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6503	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6504	if (fMovCRx)
6505	{
6506	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_CR_MASK
6507	\| CPUMCTX_EXTRN_APIC_TPR);
6508	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6509	uint8_t const iCrReg = pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0;
6510	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6511	VBOXSTRICTRC rcStrict = IEMExecDecodedMovCRxRead(pVCpu, cbInstr, iGReg, iCrReg);
6512	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6513	return VBOXSTRICTRC_VAL(rcStrict);
6514	}
6515	/* else: SMSW instruction, fall back below to IEM for this. */
6516	}
6517
6518	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6519	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6520	AssertMsg( rcStrict == VINF_SUCCESS
6521	\|\| rcStrict == VINF_PGM_SYNC_CR3
6522	\|\| rcStrict == VINF_IEM_RAISED_XCPT,
6523	("hmR0SvmExitReadCRx: IEMExecOne failed rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6524	Assert((pSvmTransient->u64ExitCode - SVM_EXIT_READ_CR0) <= 15);
6525	if (rcStrict == VINF_IEM_RAISED_XCPT)
6526	{
6527	rcStrict = VINF_SUCCESS;
6528	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6529	}
6530	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6531	return VBOXSTRICTRC_TODO(rcStrict);
6532	}
6533
6534
6535	/**
6536	* \#VMEXIT handler for CRx writes (SVM_EXIT_WRITE_CR*). Conditional \#VMEXIT.
6537	*/
6538	HMSVM_EXIT_DECL hmR0SvmExitWriteCRx(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6539	{
6540	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6541
6542	uint64_t const uExitCode = pSvmTransient->u64ExitCode;
6543	uint8_t const iCrReg = uExitCode == SVM_EXIT_CR0_SEL_WRITE ? 0 : (pSvmTransient->u64ExitCode - SVM_EXIT_WRITE_CR0);
6544	Assert(iCrReg <= 15);
6545
6546	VBOXSTRICTRC rcStrict = VERR_SVM_IPE_5;
6547	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6548	bool fDecodedInstr = false;
6549	bool const fSupportsDecodeAssists = hmR0SvmSupportsDecodeAssists(pVCpu);
6550	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6551	if ( fSupportsDecodeAssists
6552	&& fSupportsNextRipSave)
6553	{
6554	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6555	bool const fMovCRx = RT_BOOL(pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_MASK);
6556	if (fMovCRx)
6557	{
6558	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4
6559	\| CPUMCTX_EXTRN_APIC_TPR);
6560	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pCtx->rip;
6561	uint8_t const iGReg = pVmcb->ctrl.u64ExitInfo1 & SVM_EXIT1_MOV_CRX_GPR_NUMBER;
6562	Log4Func(("Mov CR%u w/ iGReg=%#x\n", iCrReg, iGReg));
6563	rcStrict = IEMExecDecodedMovCRxWrite(pVCpu, cbInstr, iCrReg, iGReg);
6564	fDecodedInstr = true;
6565	}
6566	/* else: LMSW or CLTS instruction, fall back below to IEM for this. */
6567	}
6568
6569	if (!fDecodedInstr)
6570	{
6571	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6572	Log4Func(("iCrReg=%#x\n", iCrReg));
6573	rcStrict = IEMExecOne(pVCpu);
6574	if (RT_UNLIKELY( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
6575	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED))
6576	rcStrict = VERR_EM_INTERPRETER;
6577	}
6578
6579	if (rcStrict == VINF_SUCCESS)
6580	{
6581	switch (iCrReg)
6582	{
6583	case 0:
6584	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
6585	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR0Write);
6586	break;
6587
6588	case 2:
6589	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR2);
6590	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR2Write);
6591	break;
6592
6593	case 3:
6594	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR3);
6595	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR3Write);
6596	break;
6597
6598	case 4:
6599	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR4);
6600	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR4Write);
6601	break;
6602
6603	case 8:
6604	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6605	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Write);
6606	break;
6607
6608	default:
6609	{
6610	AssertMsgFailed(("hmR0SvmExitWriteCRx: Invalid/Unexpected Write-CRx exit. u64ExitCode=%#RX64 %#x\n",
6611	pSvmTransient->u64ExitCode, iCrReg));
6612	break;
6613	}
6614	}
6615	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6616	}
6617	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6618	{
6619	rcStrict = VINF_SUCCESS;
6620	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6621	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6622	}
6623	else
6624	Assert(rcStrict == VERR_EM_INTERPRETER \|\| rcStrict == VINF_PGM_SYNC_CR3);
6625	return VBOXSTRICTRC_TODO(rcStrict);
6626	}
6627
6628
6629	/**
6630	* \#VMEXIT helper for read MSRs, see hmR0SvmExitMsr.
6631	*
6632	* @returns Strict VBox status code.
6633	* @param pVCpu The cross context virtual CPU structure.
6634	* @param pVmcb Pointer to the VM control block.
6635	*/
6636	static VBOXSTRICTRC hmR0SvmExitReadMsr(PVMCPU pVCpu, PSVMVMCB pVmcb)
6637	{
6638	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitRdmsr);
6639	Log4Func(("idMsr=%#RX32\n", pVCpu->cpum.GstCtx.ecx));
6640
6641	VBOXSTRICTRC rcStrict;
6642	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6643	if (fSupportsNextRipSave)
6644	{
6645	/** @todo Optimize this: Only retrieve the MSR bits we need here. CPUMAllMsrs.cpp
6646	* can ask for what it needs instead of using CPUMCTX_EXTRN_ALL_MSRS. */
6647	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6648	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6649	rcStrict = IEMExecDecodedRdmsr(pVCpu, cbInstr);
6650	}
6651	else
6652	{
6653	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6654	rcStrict = IEMExecOne(pVCpu);
6655	}
6656
6657	AssertMsg( rcStrict == VINF_SUCCESS
6658	\|\| rcStrict == VINF_IEM_RAISED_XCPT
6659	\|\| rcStrict == VINF_CPUM_R3_MSR_READ,
6660	("hmR0SvmExitReadMsr: Unexpected status %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6661
6662	if (rcStrict == VINF_IEM_RAISED_XCPT)
6663	{
6664	rcStrict = VINF_SUCCESS;
6665	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6666	}
6667	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6668	return rcStrict;
6669	}
6670
6671
6672	/**
6673	* \#VMEXIT helper for write MSRs, see hmR0SvmExitMsr.
6674	*
6675	* @returns Strict VBox status code.
6676	* @param pVCpu The cross context virtual CPU structure.
6677	* @param pVmcb Pointer to the VM control block.
6678	* @param pSvmTransient Pointer to the SVM-transient structure.
6679	*/
6680	static VBOXSTRICTRC hmR0SvmExitWriteMsr(PVMCPU pVCpu, PSVMVMCB pVmcb, PSVMTRANSIENT pSvmTransient)
6681	{
6682	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6683	uint32_t const idMsr = pCtx->ecx;
6684	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitWrmsr);
6685	Log4Func(("idMsr=%#RX32\n", idMsr));
6686
6687	/*
6688	* Handle TPR patching MSR writes.
6689	* We utilitize the LSTAR MSR for patching.
6690	*/
6691	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6692	if ( pVCpu->CTX_SUFF(pVM)->hm.s.fTPRPatchingActive
6693	&& idMsr == MSR_K8_LSTAR)
6694	{
6695	unsigned cbInstr;
6696	if (fSupportsNextRipSave)
6697	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6698	else
6699	{
6700	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
6701	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
6702	if ( rc == VINF_SUCCESS
6703	&& pDis->pCurInstr->uOpcode == OP_WRMSR)
6704	Assert(cbInstr > 0);
6705	else
6706	cbInstr = 0;
6707	}
6708
6709	/* Our patch code uses LSTAR for TPR caching for 32-bit guests. */
6710	if ((pCtx->eax & 0xff) != pSvmTransient->u8GuestTpr)
6711	{
6712	int rc = APICSetTpr(pVCpu, pCtx->eax & 0xff);
6713	AssertRCReturn(rc, rc);
6714	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6715	}
6716
6717	int rc = VINF_SUCCESS;
6718	hmR0SvmAdvanceRip(pVCpu, cbInstr);
6719	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6720	return rc;
6721	}
6722
6723	/*
6724	* Handle regular MSR writes.
6725	*/
6726	VBOXSTRICTRC rcStrict;
6727	if (fSupportsNextRipSave)
6728	{
6729	/** @todo Optimize this: We don't need to get much of the MSR state here
6730	* since we're only updating. CPUMAllMsrs.cpp can ask for what it needs and
6731	* clear the applicable extern flags. */
6732	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6733	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
6734	rcStrict = IEMExecDecodedWrmsr(pVCpu, cbInstr);
6735	}
6736	else
6737	{
6738	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_ALL_MSRS);
6739	rcStrict = IEMExecOne(pVCpu);
6740	}
6741
6742	AssertMsg( rcStrict == VINF_SUCCESS
6743	\|\| rcStrict == VINF_IEM_RAISED_XCPT
6744	\|\| rcStrict == VINF_CPUM_R3_MSR_WRITE,
6745	("hmR0SvmExitWriteMsr: Unexpected status %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
6746
6747	if (rcStrict == VINF_SUCCESS)
6748	{
6749	/* If this is an X2APIC WRMSR access, update the APIC TPR state. */
6750	if ( idMsr >= MSR_IA32_X2APIC_START
6751	&& idMsr <= MSR_IA32_X2APIC_END)
6752	{
6753	/*
6754	* We've already saved the APIC related guest-state (TPR) in hmR0SvmPostRunGuest().
6755	* When full APIC register virtualization is implemented we'll have to make sure
6756	* APIC state is saved from the VMCB before IEM changes it.
6757	*/
6758	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
6759	}
6760	else
6761	{
6762	switch (idMsr)
6763	{
6764	case MSR_IA32_TSC: pSvmTransient->fUpdateTscOffsetting = true; break;
6765	case MSR_K6_EFER: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_EFER_MSR); break;
6766	case MSR_K8_FS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS); break;
6767	case MSR_K8_GS_BASE: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_GS); break;
6768	case MSR_IA32_SYSENTER_CS: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_CS_MSR); break;
6769	case MSR_IA32_SYSENTER_EIP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_EIP_MSR); break;
6770	case MSR_IA32_SYSENTER_ESP: ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_SYSENTER_ESP_MSR); break;
6771	}
6772	}
6773	}
6774	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6775	{
6776	rcStrict = VINF_SUCCESS;
6777	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6778	}
6779	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6780	return rcStrict;
6781	}
6782
6783
6784	/**
6785	* \#VMEXIT handler for MSR read and writes (SVM_EXIT_MSR). Conditional
6786	* \#VMEXIT.
6787	*/
6788	HMSVM_EXIT_DECL hmR0SvmExitMsr(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6789	{
6790	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6791
6792	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6793	if (pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_READ)
6794	return VBOXSTRICTRC_TODO(hmR0SvmExitReadMsr(pVCpu, pVmcb));
6795
6796	Assert(pVmcb->ctrl.u64ExitInfo1 == SVM_EXIT1_MSR_WRITE);
6797	return VBOXSTRICTRC_TODO(hmR0SvmExitWriteMsr(pVCpu, pVmcb, pSvmTransient));
6798	}
6799
6800
6801	/**
6802	* \#VMEXIT handler for DRx read (SVM_EXIT_READ_DRx). Conditional \#VMEXIT.
6803	*/
6804	HMSVM_EXIT_DECL hmR0SvmExitReadDRx(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6805	{
6806	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6807	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
6808
6809	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxRead);
6810
6811	/** @todo Stepping with nested-guest. */
6812	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6813	if (!CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
6814	{
6815	/* We should -not- get this #VMEXIT if the guest's debug registers were active. */
6816	if (pSvmTransient->fWasGuestDebugStateActive)
6817	{
6818	AssertMsgFailed(("hmR0SvmExitReadDRx: Unexpected exit %#RX32\n", (uint32_t)pSvmTransient->u64ExitCode));
6819	pVCpu->hm.s.u32HMError = (uint32_t)pSvmTransient->u64ExitCode;
6820	return VERR_SVM_UNEXPECTED_EXIT;
6821	}
6822
6823	/*
6824	* Lazy DR0-3 loading.
6825	*/
6826	if (!pSvmTransient->fWasHyperDebugStateActive)
6827	{
6828	Assert(!DBGFIsStepping(pVCpu)); Assert(!pVCpu->hm.s.fSingleInstruction);
6829	Log5(("hmR0SvmExitReadDRx: Lazy loading guest debug registers\n"));
6830
6831	/* Don't intercept DRx read and writes. */
6832	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
6833	pVmcb->ctrl.u16InterceptRdDRx = 0;
6834	pVmcb->ctrl.u16InterceptWrDRx = 0;
6835	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_INTERCEPTS;
6836
6837	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
6838	VMMRZCallRing3Disable(pVCpu);
6839	HM_DISABLE_PREEMPT(pVCpu);
6840
6841	/* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
6842	CPUMR0LoadGuestDebugState(pVCpu, false /* include DR6 */);
6843	Assert(CPUMIsGuestDebugStateActive(pVCpu) \|\| HC_ARCH_BITS == 32);
6844
6845	HM_RESTORE_PREEMPT();
6846	VMMRZCallRing3Enable(pVCpu);
6847
6848	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxContextSwitch);
6849	return VINF_SUCCESS;
6850	}
6851	}
6852
6853	/*
6854	* Interpret the read/writing of DRx.
6855	*/
6856	/** @todo Decode assist. */
6857	VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
6858	Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
6859	if (RT_LIKELY(rc == VINF_SUCCESS))
6860	{
6861	/* Not necessary for read accesses but whatever doesn't hurt for now, will be fixed with decode assist. */
6862	/** @todo CPUM should set this flag! */
6863	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_DR_MASK);
6864	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
6865	}
6866	else
6867	Assert(rc == VERR_EM_INTERPRETER);
6868	return VBOXSTRICTRC_TODO(rc);
6869	}
6870
6871
6872	/**
6873	* \#VMEXIT handler for DRx write (SVM_EXIT_WRITE_DRx). Conditional \#VMEXIT.
6874	*/
6875	HMSVM_EXIT_DECL hmR0SvmExitWriteDRx(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6876	{
6877	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6878	/* For now it's the same since we interpret the instruction anyway. Will change when using of Decode Assist is implemented. */
6879	int rc = hmR0SvmExitReadDRx(pVCpu, pSvmTransient);
6880	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitDRxWrite);
6881	STAM_COUNTER_DEC(&pVCpu->hm.s.StatExitDRxRead);
6882	return rc;
6883	}
6884
6885
6886	/**
6887	* \#VMEXIT handler for XCRx write (SVM_EXIT_XSETBV). Conditional \#VMEXIT.
6888	*/
6889	HMSVM_EXIT_DECL hmR0SvmExitXsetbv(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6890	{
6891	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6892	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
6893
6894	/** @todo decode assists... */
6895	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
6896	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
6897	{
6898	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6899	pVCpu->hm.s.fLoadSaveGuestXcr0 = (pCtx->cr4 & X86_CR4_OSXSAVE) && pCtx->aXcr[0] != ASMGetXcr0();
6900	Log4Func(("New XCR0=%#RX64 fLoadSaveGuestXcr0=%RTbool (cr4=%#RX64)\n", pCtx->aXcr[0], pVCpu->hm.s.fLoadSaveGuestXcr0,
6901	pCtx->cr4));
6902	}
6903	else if (rcStrict == VINF_IEM_RAISED_XCPT)
6904	{
6905	rcStrict = VINF_SUCCESS;
6906	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
6907	}
6908	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
6909	return VBOXSTRICTRC_TODO(rcStrict);
6910	}
6911
6912
6913	/**
6914	* \#VMEXIT handler for I/O instructions (SVM_EXIT_IOIO). Conditional \#VMEXIT.
6915	*/
6916	HMSVM_EXIT_DECL hmR0SvmExitIOInstr(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
6917	{
6918	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
6919	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_SREG_MASK);
6920
6921	/* I/O operation lookup arrays. */
6922	static uint32_t const s_aIOSize[8] = { 0, 1, 2, 0, 4, 0, 0, 0 }; /* Size of the I/O accesses in bytes. */
6923	static uint32_t const s_aIOOpAnd[8] = { 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 }; /* AND masks for saving
6924	the result (in AL/AX/EAX). */
6925	PVM pVM = pVCpu->CTX_SUFF(pVM);
6926	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
6927	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
6928
6929	Log4Func(("CS:RIP=%04x:%#RX64\n", pCtx->cs.Sel, pCtx->rip));
6930
6931	/* Refer AMD spec. 15.10.2 "IN and OUT Behaviour" and Figure 15-2. "EXITINFO1 for IOIO Intercept" for the format. */
6932	SVMIOIOEXITINFO IoExitInfo;
6933	IoExitInfo.u = (uint32_t)pVmcb->ctrl.u64ExitInfo1;
6934	uint32_t uIOWidth = (IoExitInfo.u >> 4) & 0x7;
6935	uint32_t cbValue = s_aIOSize[uIOWidth];
6936	uint32_t uAndVal = s_aIOOpAnd[uIOWidth];
6937
6938	if (RT_UNLIKELY(!cbValue))
6939	{
6940	AssertMsgFailed(("hmR0SvmExitIOInstr: Invalid IO operation. uIOWidth=%u\n", uIOWidth));
6941	return VERR_EM_INTERPRETER;
6942	}
6943
6944	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS);
6945	VBOXSTRICTRC rcStrict;
6946	PCEMEXITREC pExitRec = NULL;
6947	if ( !pVCpu->hm.s.fSingleInstruction
6948	&& !pVCpu->cpum.GstCtx.eflags.Bits.u1TF)
6949	pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
6950	!IoExitInfo.n.u1Str
6951	? IoExitInfo.n.u1Type == SVM_IOIO_READ
6952	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_READ)
6953	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_WRITE)
6954	: IoExitInfo.n.u1Type == SVM_IOIO_READ
6955	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_READ)
6956	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_IO_PORT_STR_WRITE),
6957	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
6958	if (!pExitRec)
6959	{
6960	bool fUpdateRipAlready = false;
6961	if (IoExitInfo.n.u1Str)
6962	{
6963	/* INS/OUTS - I/O String instruction. */
6964	/** @todo Huh? why can't we use the segment prefix information given by AMD-V
6965	* in EXITINFO1? Investigate once this thing is up and running. */
6966	Log4Func(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, IoExitInfo.n.u16Port, cbValue,
6967	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? 'w' : 'r'));
6968	AssertReturn(pCtx->dx == IoExitInfo.n.u16Port, VERR_SVM_IPE_2);
6969	static IEMMODE const s_aenmAddrMode[8] =
6970	{
6971	(IEMMODE)-1, IEMMODE_16BIT, IEMMODE_32BIT, (IEMMODE)-1, IEMMODE_64BIT, (IEMMODE)-1, (IEMMODE)-1, (IEMMODE)-1
6972	};
6973	IEMMODE enmAddrMode = s_aenmAddrMode[(IoExitInfo.u >> 7) & 0x7];
6974	if (enmAddrMode != (IEMMODE)-1)
6975	{
6976	uint64_t cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
6977	if (cbInstr <= 15 && cbInstr >= 1)
6978	{
6979	Assert(cbInstr >= 1U + IoExitInfo.n.u1Rep);
6980	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
6981	{
6982	/* Don't know exactly how to detect whether u3Seg is valid, currently
6983	only enabling it for Bulldozer and later with NRIP. OS/2 broke on
6984	2384 Opterons when only checking NRIP. */
6985	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
6986	if ( fSupportsNextRipSave
6987	&& pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
6988	{
6989	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_DS \|\| cbInstr > 1U + IoExitInfo.n.u1Rep,
6990	("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3Seg, cbInstr, IoExitInfo.n.u1Rep));
6991	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6992	IoExitInfo.n.u3Seg, true /fIoChecked/);
6993	}
6994	else if (cbInstr == 1U + IoExitInfo.n.u1Rep)
6995	rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
6996	X86_SREG_DS, true /fIoChecked/);
6997	else
6998	rcStrict = IEMExecOne(pVCpu);
6999	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringWrite);
7000	}
7001	else
7002	{
7003	AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_ES /=0/, ("%#x\n", IoExitInfo.n.u3Seg));
7004	rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
7005	true /fIoChecked/);
7006	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
7007	}
7008	}
7009	else
7010	{
7011	AssertMsgFailed(("rip=%RX64 nrip=%#RX64 cbInstr=%#RX64\n", pCtx->rip, pVmcb->ctrl.u64ExitInfo2, cbInstr));
7012	rcStrict = IEMExecOne(pVCpu);
7013	}
7014	}
7015	else
7016	{
7017	AssertMsgFailed(("IoExitInfo=%RX64\n", IoExitInfo.u));
7018	rcStrict = IEMExecOne(pVCpu);
7019	}
7020	fUpdateRipAlready = true;
7021	}
7022	else
7023	{
7024	/* IN/OUT - I/O instruction. */
7025	Assert(!IoExitInfo.n.u1Rep);
7026
7027	uint8_t const cbInstr = pVmcb->ctrl.u64ExitInfo2 - pCtx->rip;
7028	if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
7029	{
7030	rcStrict = IOMIOPortWrite(pVM, pVCpu, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, cbValue);
7031	if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
7032	&& !pCtx->eflags.Bits.u1TF)
7033	rcStrict = EMRZSetPendingIoPortWrite(pVCpu, IoExitInfo.n.u16Port, cbInstr, cbValue, pCtx->eax & uAndVal);
7034	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOWrite);
7035	}
7036	else
7037	{
7038	uint32_t u32Val = 0;
7039	rcStrict = IOMIOPortRead(pVM, pVCpu, IoExitInfo.n.u16Port, &u32Val, cbValue);
7040	if (IOM_SUCCESS(rcStrict))
7041	{
7042	/* Save result of I/O IN instr. in AL/AX/EAX. */
7043	/** @todo r=bird: 32-bit op size should clear high bits of rax! */
7044	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
7045	}
7046	else if ( rcStrict == VINF_IOM_R3_IOPORT_READ
7047	&& !pCtx->eflags.Bits.u1TF)
7048	rcStrict = EMRZSetPendingIoPortRead(pVCpu, IoExitInfo.n.u16Port, cbInstr, cbValue);
7049
7050	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIORead);
7051	}
7052	}
7053
7054	if (IOM_SUCCESS(rcStrict))
7055	{
7056	/* AMD-V saves the RIP of the instruction following the IO instruction in EXITINFO2. */
7057	if (!fUpdateRipAlready)
7058	pCtx->rip = pVmcb->ctrl.u64ExitInfo2;
7059
7060	/*
7061	* If any I/O breakpoints are armed, we need to check if one triggered
7062	* and take appropriate action.
7063	* Note that the I/O breakpoint type is undefined if CR4.DE is 0.
7064	*/
7065	/** @todo Optimize away the DBGFBpIsHwIoArmed call by having DBGF tell the
7066	* execution engines about whether hyper BPs and such are pending. */
7067	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_DR7);
7068	uint32_t const uDr7 = pCtx->dr[7];
7069	if (RT_UNLIKELY( ( (uDr7 & X86_DR7_ENABLED_MASK)
7070	&& X86_DR7_ANY_RW_IO(uDr7)
7071	&& (pCtx->cr4 & X86_CR4_DE))
7072	\|\| DBGFBpIsHwIoArmed(pVM)))
7073	{
7074	/* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
7075	VMMRZCallRing3Disable(pVCpu);
7076	HM_DISABLE_PREEMPT(pVCpu);
7077
7078	STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);
7079	CPUMR0DebugStateMaybeSaveGuest(pVCpu, false /fDr6/);
7080
7081	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, &pVCpu->cpum.GstCtx, IoExitInfo.n.u16Port, cbValue);
7082	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
7083	{
7084	/* Raise #DB. */
7085	pVmcb->guest.u64DR6 = pCtx->dr[6];
7086	pVmcb->guest.u64DR7 = pCtx->dr[7];
7087	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7088	hmR0SvmSetPendingXcptDB(pVCpu);
7089	}
7090	/* rcStrict is VINF_SUCCESS, VINF_IOM_R3_IOPORT_COMMIT_WRITE, or in [VINF_EM_FIRST..VINF_EM_LAST],
7091	however we can ditch VINF_IOM_R3_IOPORT_COMMIT_WRITE as it has VMCPU_FF_IOM as backup. */
7092	else if ( rcStrict2 != VINF_SUCCESS
7093	&& (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
7094	rcStrict = rcStrict2;
7095	AssertCompile(VINF_EM_LAST < VINF_IOM_R3_IOPORT_COMMIT_WRITE);
7096
7097	HM_RESTORE_PREEMPT();
7098	VMMRZCallRing3Enable(pVCpu);
7099	}
7100
7101	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7102	}
7103
7104	#ifdef VBOX_STRICT
7105	if ( rcStrict == VINF_IOM_R3_IOPORT_READ
7106	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_READ)
7107	Assert(IoExitInfo.n.u1Type == SVM_IOIO_READ);
7108	else if ( rcStrict == VINF_IOM_R3_IOPORT_WRITE
7109	\|\| rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE
7110	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_WRITE)
7111	Assert(IoExitInfo.n.u1Type == SVM_IOIO_WRITE);
7112	else
7113	{
7114	/** @todo r=bird: This is missing a bunch of VINF_EM_FIRST..VINF_EM_LAST
7115	* statuses, that the VMM device and some others may return. See
7116	* IOM_SUCCESS() for guidance. */
7117	AssertMsg( RT_FAILURE(rcStrict)
7118	\|\| rcStrict == VINF_SUCCESS
7119	\|\| rcStrict == VINF_EM_RAW_EMULATE_INSTR
7120	\|\| rcStrict == VINF_EM_DBG_BREAKPOINT
7121	\|\| rcStrict == VINF_EM_RAW_GUEST_TRAP
7122	\|\| rcStrict == VINF_EM_RAW_TO_R3
7123	\|\| rcStrict == VINF_TRPM_XCPT_DISPATCHED
7124	\|\| rcStrict == VINF_EM_TRIPLE_FAULT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
7125	}
7126	#endif
7127	}
7128	else
7129	{
7130	/*
7131	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
7132	*/
7133	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7134	STAM_COUNTER_INC(!IoExitInfo.n.u1Str
7135	? IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOWrite : &pVCpu->hm.s.StatExitIORead
7136	: IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? &pVCpu->hm.s.StatExitIOStringWrite : &pVCpu->hm.s.StatExitIOStringRead);
7137	Log4(("IOExit/%u: %04x:%08RX64: %s%s%s %#x LB %u -> EMHistoryExec\n",
7138	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, IoExitInfo.n.u1Rep ? "REP " : "",
7139	IoExitInfo.n.u1Type == SVM_IOIO_WRITE ? "OUT" : "IN", IoExitInfo.n.u1Str ? "S" : "", IoExitInfo.n.u16Port, uIOWidth));
7140
7141	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
7142	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7143
7144	Log4(("IOExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
7145	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
7146	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
7147	}
7148	return VBOXSTRICTRC_TODO(rcStrict);
7149	}
7150
7151
7152	/**
7153	* \#VMEXIT handler for Nested Page-faults (SVM_EXIT_NPF). Conditional \#VMEXIT.
7154	*/
7155	HMSVM_EXIT_DECL hmR0SvmExitNestedPF(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7156	{
7157	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7158	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7159	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7160
7161	PVM pVM = pVCpu->CTX_SUFF(pVM);
7162	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7163	Assert(pVM->hm.s.fNestedPaging);
7164
7165	/* See AMD spec. 15.25.6 "Nested versus Guest Page Faults, Fault Ordering" for VMCB details for #NPF. */
7166	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7167	RTGCPHYS GCPhysFaultAddr = pVmcb->ctrl.u64ExitInfo2;
7168	uint32_t u32ErrCode = pVmcb->ctrl.u64ExitInfo1; /* Note! High bits in EXITINFO1 may contain additional info and are
7169	thus intentionally not copied into u32ErrCode. */
7170
7171	Log4Func(("#NPF at CS:RIP=%04x:%#RX64 GCPhysFaultAddr=%RGp ErrCode=%#x \n", pCtx->cs.Sel, pCtx->rip, GCPhysFaultAddr,
7172	u32ErrCode));
7173
7174	/*
7175	* TPR patching for 32-bit guests, using the reserved bit in the page tables for MMIO regions.
7176	*/
7177	if ( pVM->hm.s.fTprPatchingAllowed
7178	&& (GCPhysFaultAddr & PAGE_OFFSET_MASK) == XAPIC_OFF_TPR
7179	&& ( !(u32ErrCode & X86_TRAP_PF_P) /* Not present */
7180	\|\| (u32ErrCode & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) /* MMIO page. */
7181	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7182	&& !CPUMIsGuestInLongModeEx(pCtx)
7183	&& !CPUMGetGuestCPL(pVCpu)
7184	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7185	{
7186	RTGCPHYS GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7187	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7188
7189	if (GCPhysFaultAddr == GCPhysApicBase + XAPIC_OFF_TPR)
7190	{
7191	/* Only attempt to patch the instruction once. */
7192	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7193	if (!pPatch)
7194	return VINF_EM_HM_PATCH_TPR_INSTR;
7195	}
7196	}
7197
7198	/*
7199	* Determine the nested paging mode.
7200	*/
7201	/** @todo r=bird: Gotta love this nested paging hacking we're still carrying with us... (Split PGM_TYPE_NESTED.) */
7202	PGMMODE enmNestedPagingMode;
7203	#if HC_ARCH_BITS == 32
7204	if (CPUMIsGuestInLongModeEx(pCtx))
7205	enmNestedPagingMode = PGMMODE_AMD64_NX;
7206	else
7207	#endif
7208	enmNestedPagingMode = PGMGetHostMode(pVM);
7209
7210	/*
7211	* MMIO optimization using the reserved (RSVD) bit in the guest page tables for MMIO pages.
7212	*/
7213	Assert((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != X86_TRAP_PF_RSVD);
7214	if ((u32ErrCode & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
7215	{
7216	/*
7217	* If event delivery causes an MMIO #NPF, go back to instruction emulation as otherwise
7218	* injecting the original pending event would most likely cause the same MMIO #NPF.
7219	*/
7220	if (pVCpu->hm.s.Event.fPending)
7221	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7222
7223	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RIP);
7224	VBOXSTRICTRC rcStrict;
7225	PCEMEXITREC pExitRec = EMHistoryUpdateFlagsAndTypeAndPC(pVCpu,
7226	EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM \| EMEXIT_F_HM, EMEXITTYPE_MMIO),
7227	pVCpu->cpum.GstCtx.rip + pVCpu->cpum.GstCtx.cs.u64Base);
7228	if (!pExitRec)
7229	{
7230
7231	rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
7232	u32ErrCode);
7233
7234	/*
7235	* If we succeed, resume guest execution.
7236	*
7237	* If we fail in interpreting the instruction because we couldn't get the guest
7238	* physical address of the page containing the instruction via the guest's page
7239	* tables (we would invalidate the guest page in the host TLB), resume execution
7240	* which would cause a guest page fault to let the guest handle this weird case.
7241	*
7242	* See @bugref{6043}.
7243	*/
7244	if ( rcStrict == VINF_SUCCESS
7245	\|\| rcStrict == VERR_PAGE_TABLE_NOT_PRESENT
7246	\|\| rcStrict == VERR_PAGE_NOT_PRESENT)
7247	{
7248	/* Successfully handled MMIO operation. */
7249	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
7250	rcStrict = VINF_SUCCESS;
7251	}
7252	}
7253	else
7254	{
7255	/*
7256	* Frequent exit or something needing probing. Get state and call EMHistoryExec.
7257	*/
7258	Assert(pCtx == &pVCpu->cpum.GstCtx);
7259	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7260	Log4(("EptMisscfgExit/%u: %04x:%08RX64: %RGp -> EMHistoryExec\n",
7261	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, GCPhysFaultAddr));
7262
7263	rcStrict = EMHistoryExec(pVCpu, pExitRec, 0);
7264	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7265
7266	Log4(("EptMisscfgExit/%u: %04x:%08RX64: EMHistoryExec -> %Rrc + %04x:%08RX64\n",
7267	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
7268	VBOXSTRICTRC_VAL(rcStrict), pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
7269	}
7270	return VBOXSTRICTRC_TODO(rcStrict);
7271	}
7272
7273	TRPMAssertXcptPF(pVCpu, GCPhysFaultAddr, u32ErrCode);
7274	int rc = PGMR0Trap0eHandlerNestedPaging(pVM, pVCpu, enmNestedPagingMode, u32ErrCode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr);
7275	TRPMResetTrap(pVCpu);
7276
7277	Log4Func(("#NPF: PGMR0Trap0eHandlerNestedPaging returns %Rrc CS:RIP=%04x:%#RX64\n", rc, pCtx->cs.Sel, pCtx->rip));
7278
7279	/*
7280	* Same case as PGMR0Trap0eHandlerNPMisconfig(). See comment above, @bugref{6043}.
7281	*/
7282	if ( rc == VINF_SUCCESS
7283	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT
7284	\|\| rc == VERR_PAGE_NOT_PRESENT)
7285	{
7286	/* We've successfully synced our shadow page tables. */
7287	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7288	rc = VINF_SUCCESS;
7289	}
7290
7291	return rc;
7292	}
7293
7294
7295	/**
7296	* \#VMEXIT handler for virtual interrupt (SVM_EXIT_VINTR). Conditional
7297	* \#VMEXIT.
7298	*/
7299	HMSVM_EXIT_DECL hmR0SvmExitVIntr(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7300	{
7301	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7302	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
7303
7304	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7305	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7306	hmR0SvmClearIntWindowExiting(pVCpu, pVmcb);
7307
7308	/* Deliver the pending interrupt via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7309	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIntWindow);
7310	return VINF_SUCCESS;
7311	}
7312
7313
7314	/**
7315	* \#VMEXIT handler for task switches (SVM_EXIT_TASK_SWITCH). Conditional
7316	* \#VMEXIT.
7317	*/
7318	HMSVM_EXIT_DECL hmR0SvmExitTaskSwitch(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7319	{
7320	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7321	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7322
7323	#ifndef HMSVM_ALWAYS_TRAP_TASK_SWITCH
7324	Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
7325	#endif
7326
7327	/* Check if this task-switch occurred while delivering an event through the guest IDT. */
7328	if (pVCpu->hm.s.Event.fPending) /* Can happen with exceptions/NMI. See @bugref{8411}. */
7329	{
7330	/*
7331	* AMD-V provides us with the exception which caused the TS; we collect
7332	* the information in the call to hmR0SvmCheckExitDueToEventDelivery().
7333	*/
7334	Log4Func(("TS occurred during event delivery\n"));
7335	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7336	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7337	}
7338
7339	/** @todo Emulate task switch someday, currently just going back to ring-3 for
7340	* emulation. */
7341	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitTaskSwitch);
7342	return VERR_EM_INTERPRETER;
7343	}
7344
7345
7346	/**
7347	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7348	*/
7349	HMSVM_EXIT_DECL hmR0SvmExitVmmCall(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7350	{
7351	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7352	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7353
7354	if (pVCpu->CTX_SUFF(pVM)->hm.s.fTprPatchingAllowed)
7355	{
7356	int rc = hmSvmEmulateMovTpr(pVCpu);
7357	if (rc != VERR_NOT_FOUND)
7358	{
7359	Log4Func(("hmSvmEmulateMovTpr returns %Rrc\n", rc));
7360	return rc;
7361	}
7362	}
7363
7364	if (EMAreHypercallInstructionsEnabled(pVCpu))
7365	{
7366	unsigned cbInstr;
7367	if (hmR0SvmSupportsNextRipSave(pVCpu))
7368	{
7369	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7370	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7371	}
7372	else
7373	{
7374	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
7375	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
7376	if ( rc == VINF_SUCCESS
7377	&& pDis->pCurInstr->uOpcode == OP_VMMCALL)
7378	Assert(cbInstr > 0);
7379	else
7380	cbInstr = 0;
7381	}
7382
7383	VBOXSTRICTRC rcStrict = GIMHypercall(pVCpu, &pVCpu->cpum.GstCtx);
7384	if (RT_SUCCESS(rcStrict))
7385	{
7386	/* Only update the RIP if we're continuing guest execution and not in the case
7387	of say VINF_GIM_R3_HYPERCALL. */
7388	if (rcStrict == VINF_SUCCESS)
7389	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7390
7391	return VBOXSTRICTRC_VAL(rcStrict);
7392	}
7393	else
7394	Log4Func(("GIMHypercall returns %Rrc -> #UD\n", VBOXSTRICTRC_VAL(rcStrict)));
7395	}
7396
7397	hmR0SvmSetPendingXcptUD(pVCpu);
7398	return VINF_SUCCESS;
7399	}
7400
7401
7402	/**
7403	* \#VMEXIT handler for VMMCALL (SVM_EXIT_VMMCALL). Conditional \#VMEXIT.
7404	*/
7405	HMSVM_EXIT_DECL hmR0SvmExitPause(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7406	{
7407	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7408
7409	unsigned cbInstr;
7410	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7411	if (fSupportsNextRipSave)
7412	{
7413	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7414	cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7415	}
7416	else
7417	{
7418	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
7419	int rc = EMInterpretDisasCurrent(pVCpu->CTX_SUFF(pVM), pVCpu, pDis, &cbInstr);
7420	if ( rc == VINF_SUCCESS
7421	&& pDis->pCurInstr->uOpcode == OP_PAUSE)
7422	Assert(cbInstr > 0);
7423	else
7424	cbInstr = 0;
7425	}
7426
7427	/** @todo The guest has likely hit a contended spinlock. We might want to
7428	* poke a schedule different guest VCPU. */
7429	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7430	return VINF_EM_RAW_INTERRUPT;
7431	}
7432
7433
7434	/**
7435	* \#VMEXIT handler for FERR intercept (SVM_EXIT_FERR_FREEZE). Conditional
7436	* \#VMEXIT.
7437	*/
7438	HMSVM_EXIT_DECL hmR0SvmExitFerrFreeze(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7439	{
7440	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7441	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_CR0);
7442	Assert(!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_NE));
7443
7444	Log4Func(("Raising IRQ 13 in response to #FERR\n"));
7445	return PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7446	}
7447
7448
7449	/**
7450	* \#VMEXIT handler for IRET (SVM_EXIT_IRET). Conditional \#VMEXIT.
7451	*/
7452	HMSVM_EXIT_DECL hmR0SvmExitIret(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7453	{
7454	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7455
7456	/* Clear NMI blocking. */
7457	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
7458	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
7459
7460	/* Indicate that we no longer need to #VMEXIT when the guest is ready to receive NMIs, it is now ready. */
7461	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7462	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_IRET);
7463
7464	/* Deliver the pending NMI via hmR0SvmEvaluatePendingEvent() and resume guest execution. */
7465	return VINF_SUCCESS;
7466	}
7467
7468
7469	/**
7470	* \#VMEXIT handler for page-fault exceptions (SVM_EXIT_XCPT_14).
7471	* Conditional \#VMEXIT.
7472	*/
7473	HMSVM_EXIT_DECL hmR0SvmExitXcptPF(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7474	{
7475	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7476	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7477	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7478
7479	/* See AMD spec. 15.12.15 "#PF (Page Fault)". */
7480	PVM pVM = pVCpu->CTX_SUFF(pVM);
7481	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7482	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7483	uint32_t uErrCode = pVmcb->ctrl.u64ExitInfo1;
7484	uint64_t const uFaultAddress = pVmcb->ctrl.u64ExitInfo2;
7485
7486	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(HMSVM_ALWAYS_TRAP_PF)
7487	if (pVM->hm.s.fNestedPaging)
7488	{
7489	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7490	if ( !pSvmTransient->fVectoringDoublePF
7491	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
7492	{
7493	/* A genuine guest #PF, reflect it to the guest. */
7494	hmR0SvmSetPendingXcptPF(pVCpu, uErrCode, uFaultAddress);
7495	Log4Func(("#PF: Guest page fault at %04X:%RGv FaultAddr=%RX64 ErrCode=%#x\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip,
7496	uFaultAddress, uErrCode));
7497	}
7498	else
7499	{
7500	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7501	hmR0SvmSetPendingXcptDF(pVCpu);
7502	Log4Func(("Pending #DF due to vectoring #PF. NP\n"));
7503	}
7504	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7505	return VINF_SUCCESS;
7506	}
7507	#endif
7508
7509	Assert(!pVM->hm.s.fNestedPaging);
7510
7511	/*
7512	* TPR patching shortcut for APIC TPR reads and writes; only applicable to 32-bit guests.
7513	*/
7514	if ( pVM->hm.s.fTprPatchingAllowed
7515	&& (uFaultAddress & 0xfff) == XAPIC_OFF_TPR
7516	&& !(uErrCode & X86_TRAP_PF_P) /* Not present. */
7517	&& !CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7518	&& !CPUMIsGuestInLongModeEx(pCtx)
7519	&& !CPUMGetGuestCPL(pVCpu)
7520	&& pVM->hm.s.cPatches < RT_ELEMENTS(pVM->hm.s.aPatches))
7521	{
7522	RTGCPHYS GCPhysApicBase;
7523	GCPhysApicBase = APICGetBaseMsrNoCheck(pVCpu);
7524	GCPhysApicBase &= PAGE_BASE_GC_MASK;
7525
7526	/* Check if the page at the fault-address is the APIC base. */
7527	RTGCPHYS GCPhysPage;
7528	int rc2 = PGMGstGetPage(pVCpu, (RTGCPTR)uFaultAddress, NULL /* pfFlags */, &GCPhysPage);
7529	if ( rc2 == VINF_SUCCESS
7530	&& GCPhysPage == GCPhysApicBase)
7531	{
7532	/* Only attempt to patch the instruction once. */
7533	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
7534	if (!pPatch)
7535	return VINF_EM_HM_PATCH_TPR_INSTR;
7536	}
7537	}
7538
7539	Log4Func(("#PF: uFaultAddress=%#RX64 CS:RIP=%#04x:%#RX64 uErrCode %#RX32 cr3=%#RX64\n", uFaultAddress, pCtx->cs.Sel,
7540	pCtx->rip, uErrCode, pCtx->cr3));
7541
7542	/*
7543	* If it's a vectoring #PF, emulate injecting the original event injection as
7544	* PGMTrap0eHandler() is incapable of differentiating between instruction emulation and
7545	* event injection that caused a #PF. See @bugref{6607}.
7546	*/
7547	if (pSvmTransient->fVectoringPF)
7548	{
7549	Assert(pVCpu->hm.s.Event.fPending);
7550	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7551	}
7552
7553	TRPMAssertXcptPF(pVCpu, uFaultAddress, uErrCode);
7554	int rc = PGMTrap0eHandler(pVCpu, uErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
7555
7556	Log4Func(("#PF: rc=%Rrc\n", rc));
7557
7558	if (rc == VINF_SUCCESS)
7559	{
7560	/* Successfully synced shadow pages tables or emulated an MMIO instruction. */
7561	TRPMResetTrap(pVCpu);
7562	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPF);
7563	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
7564	return rc;
7565	}
7566
7567	if (rc == VINF_EM_RAW_GUEST_TRAP)
7568	{
7569	pVCpu->hm.s.Event.fPending = false; /* In case it's a contributory or vectoring #PF. */
7570
7571	/*
7572	* If a nested-guest delivers a #PF and that causes a #PF which is -not- a shadow #PF,
7573	* we should simply forward the #PF to the guest and is up to the nested-hypervisor to
7574	* determine whether it is a nested-shadow #PF or a #DF, see @bugref{7243#c121}.
7575	*/
7576	if ( !pSvmTransient->fVectoringDoublePF
7577	\|\| CPUMIsGuestInSvmNestedHwVirtMode(pCtx))
7578	{
7579	/* It's a guest (or nested-guest) page fault and needs to be reflected. */
7580	uErrCode = TRPMGetErrorCode(pVCpu); /* The error code might have been changed. */
7581	TRPMResetTrap(pVCpu);
7582
7583	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7584	/* If the nested-guest is intercepting #PFs, cause a #PF #VMEXIT. */
7585	if ( CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
7586	&& HMIsGuestSvmXcptInterceptSet(pVCpu, X86_XCPT_PF))
7587	return VBOXSTRICTRC_TODO(IEMExecSvmVmexit(pVCpu, SVM_EXIT_XCPT_PF, uErrCode, uFaultAddress));
7588	#endif
7589
7590	hmR0SvmSetPendingXcptPF(pVCpu, uErrCode, uFaultAddress);
7591	}
7592	else
7593	{
7594	/* A guest page-fault occurred during delivery of a page-fault. Inject #DF. */
7595	TRPMResetTrap(pVCpu);
7596	hmR0SvmSetPendingXcptDF(pVCpu);
7597	Log4Func(("#PF: Pending #DF due to vectoring #PF\n"));
7598	}
7599
7600	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestPF);
7601	return VINF_SUCCESS;
7602	}
7603
7604	TRPMResetTrap(pVCpu);
7605	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitShadowPFEM);
7606	return rc;
7607	}
7608
7609
7610	/**
7611	* \#VMEXIT handler for undefined opcode (SVM_EXIT_XCPT_6).
7612	* Conditional \#VMEXIT.
7613	*/
7614	HMSVM_EXIT_DECL hmR0SvmExitXcptUD(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7615	{
7616	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7617	HMSVM_ASSERT_NOT_IN_NESTED_GUEST(&pVCpu->cpum.GstCtx);
7618
7619	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7620	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7621	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7622
7623	int rc = VERR_SVM_UNEXPECTED_XCPT_EXIT;
7624	if (pVCpu->hm.s.fGIMTrapXcptUD)
7625	{
7626	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7627	uint8_t cbInstr = 0;
7628	VBOXSTRICTRC rcStrict = GIMXcptUD(pVCpu, &pVCpu->cpum.GstCtx, NULL /* pDis */, &cbInstr);
7629	if (rcStrict == VINF_SUCCESS)
7630	{
7631	/* #UD #VMEXIT does not have valid NRIP information, manually advance RIP. See @bugref{7270#c170}. */
7632	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7633	rc = VINF_SUCCESS;
7634	HMSVM_CHECK_SINGLE_STEP(pVCpu, rc);
7635	}
7636	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
7637	rc = VINF_SUCCESS;
7638	else if (rcStrict == VINF_GIM_R3_HYPERCALL)
7639	rc = VINF_GIM_R3_HYPERCALL;
7640	else
7641	Assert(RT_FAILURE(VBOXSTRICTRC_VAL(rcStrict)));
7642	}
7643
7644	/* If the GIM #UD exception handler didn't succeed for some reason or wasn't needed, raise #UD. */
7645	if (RT_FAILURE(rc))
7646	{
7647	hmR0SvmSetPendingXcptUD(pVCpu);
7648	rc = VINF_SUCCESS;
7649	}
7650
7651	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestUD);
7652	return rc;
7653	}
7654
7655
7656	/**
7657	* \#VMEXIT handler for math-fault exceptions (SVM_EXIT_XCPT_16).
7658	* Conditional \#VMEXIT.
7659	*/
7660	HMSVM_EXIT_DECL hmR0SvmExitXcptMF(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7661	{
7662	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7663	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7664
7665	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7666	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7667
7668	/* Paranoia; Ensure we cannot be called as a result of event delivery. */
7669	Assert(!pVmcb->ctrl.ExitIntInfo.n.u1Valid); NOREF(pVmcb);
7670
7671	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
7672
7673	if (!(pCtx->cr0 & X86_CR0_NE))
7674	{
7675	PVM pVM = pVCpu->CTX_SUFF(pVM);
7676	PDISSTATE pDis = &pVCpu->hm.s.DisState;
7677	unsigned cbInstr;
7678	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbInstr);
7679	if (RT_SUCCESS(rc))
7680	{
7681	/* Convert a #MF into a FERR -> IRQ 13. See @bugref{6117}. */
7682	rc = PDMIsaSetIrq(pVCpu->CTX_SUFF(pVM), 13 /* u8Irq /, 1 / u8Level /, 0 / uTagSrc */);
7683	if (RT_SUCCESS(rc))
7684	hmR0SvmAdvanceRip(pVCpu, cbInstr);
7685	}
7686	else
7687	Log4Func(("EMInterpretDisasCurrent returned %Rrc uOpCode=%#x\n", rc, pDis->pCurInstr->uOpcode));
7688	return rc;
7689	}
7690
7691	hmR0SvmSetPendingXcptMF(pVCpu);
7692	return VINF_SUCCESS;
7693	}
7694
7695
7696	/**
7697	* \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1). Conditional
7698	* \#VMEXIT.
7699	*/
7700	HMSVM_EXIT_DECL hmR0SvmExitXcptDB(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7701	{
7702	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7703	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7704	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7705
7706	if (RT_UNLIKELY(pVCpu->hm.s.Event.fPending))
7707	{
7708	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
7709	return VINF_EM_RAW_INJECT_TRPM_EVENT;
7710	}
7711
7712	STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
7713
7714	/*
7715	* This can be a fault-type #DB (instruction breakpoint) or a trap-type #DB (data
7716	* breakpoint). However, for both cases DR6 and DR7 are updated to what the exception
7717	* handler expects. See AMD spec. 15.12.2 "#DB (Debug)".
7718	*/
7719	PVM pVM = pVCpu->CTX_SUFF(pVM);
7720	PSVMVMCB pVmcb = pVCpu->hm.s.svm.pVmcb;
7721	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7722	int rc = DBGFRZTrap01Handler(pVM, pVCpu, CPUMCTX2CORE(pCtx), pVmcb->guest.u64DR6, pVCpu->hm.s.fSingleInstruction);
7723	if (rc == VINF_EM_RAW_GUEST_TRAP)
7724	{
7725	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> guest trap\n", pVmcb->guest.u64DR6));
7726	if (CPUMIsHyperDebugStateActive(pVCpu))
7727	CPUMSetGuestDR6(pVCpu, CPUMGetGuestDR6(pVCpu) \| pVmcb->guest.u64DR6);
7728
7729	/* Reflect the exception back to the guest. */
7730	hmR0SvmSetPendingXcptDB(pVCpu);
7731	rc = VINF_SUCCESS;
7732	}
7733
7734	/*
7735	* Update DR6.
7736	*/
7737	if (CPUMIsHyperDebugStateActive(pVCpu))
7738	{
7739	Log5(("hmR0SvmExitXcptDB: DR6=%#RX64 -> %Rrc\n", pVmcb->guest.u64DR6, rc));
7740	pVmcb->guest.u64DR6 = X86_DR6_INIT_VAL;
7741	pVmcb->ctrl.u32VmcbCleanBits &= ~HMSVM_VMCB_CLEAN_DRX;
7742	}
7743	else
7744	{
7745	AssertMsg(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc));
7746	Assert(!pVCpu->hm.s.fSingleInstruction && !DBGFIsStepping(pVCpu));
7747	}
7748
7749	return rc;
7750	}
7751
7752
7753	/**
7754	* \#VMEXIT handler for alignment check exceptions (SVM_EXIT_XCPT_17).
7755	* Conditional \#VMEXIT.
7756	*/
7757	HMSVM_EXIT_DECL hmR0SvmExitXcptAC(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7758	{
7759	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7760	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7761
7762	SVMEVENT Event;
7763	Event.u = 0;
7764	Event.n.u1Valid = 1;
7765	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7766	Event.n.u8Vector = X86_XCPT_AC;
7767	Event.n.u1ErrorCodeValid = 1;
7768	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7769	return VINF_SUCCESS;
7770	}
7771
7772
7773	/**
7774	* \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
7775	* Conditional \#VMEXIT.
7776	*/
7777	HMSVM_EXIT_DECL hmR0SvmExitXcptBP(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7778	{
7779	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7780	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
7781	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7782
7783	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
7784	int rc = DBGFRZTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, CPUMCTX2CORE(pCtx));
7785	if (rc == VINF_EM_RAW_GUEST_TRAP)
7786	{
7787	SVMEVENT Event;
7788	Event.u = 0;
7789	Event.n.u1Valid = 1;
7790	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7791	Event.n.u8Vector = X86_XCPT_BP;
7792	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7793	}
7794
7795	Assert(rc == VINF_SUCCESS \|\| rc == VINF_EM_RAW_GUEST_TRAP \|\| rc == VINF_EM_DBG_BREAKPOINT);
7796	return rc;
7797	}
7798
7799
7800	#if defined(HMSVM_ALWAYS_TRAP_ALL_XCPTS) \|\| defined(VBOX_WITH_NESTED_HWVIRT_SVM)
7801	/**
7802	* \#VMEXIT handler for generic exceptions. Conditional \#VMEXIT.
7803	*/
7804	HMSVM_EXIT_DECL hmR0SvmExitXcptGeneric(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7805	{
7806	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7807	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
7808
7809	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7810	uint8_t const uVector = pVmcb->ctrl.u64ExitCode - SVM_EXIT_XCPT_0;
7811	uint32_t const uErrCode = pVmcb->ctrl.u64ExitInfo1;
7812	Assert(pSvmTransient->u64ExitCode == pVmcb->ctrl.u64ExitCode);
7813	Assert(uVector <= X86_XCPT_LAST);
7814	Log4Func(("uVector=%#x uErrCode=%u\n", uVector, uErrCode));
7815
7816	SVMEVENT Event;
7817	Event.u = 0;
7818	Event.n.u1Valid = 1;
7819	Event.n.u3Type = SVM_EVENT_EXCEPTION;
7820	Event.n.u8Vector = uVector;
7821	switch (uVector)
7822	{
7823	/* Shouldn't be here for reflecting #PFs (among other things, the fault address isn't passed along). */
7824	case X86_XCPT_PF: AssertMsgFailed(("hmR0SvmExitXcptGeneric: Unexpected exception")); return VERR_SVM_IPE_5;
7825	case X86_XCPT_DF:
7826	case X86_XCPT_TS:
7827	case X86_XCPT_NP:
7828	case X86_XCPT_SS:
7829	case X86_XCPT_GP:
7830	case X86_XCPT_AC:
7831	{
7832	Event.n.u1ErrorCodeValid = 1;
7833	Event.n.u32ErrorCode = uErrCode;
7834	break;
7835	}
7836	}
7837
7838	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
7839	return VINF_SUCCESS;
7840	}
7841	#endif
7842
7843	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
7844	/**
7845	* \#VMEXIT handler for CLGI (SVM_EXIT_CLGI). Conditional \#VMEXIT.
7846	*/
7847	HMSVM_EXIT_DECL hmR0SvmExitClgi(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7848	{
7849	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7850
7851	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7852	Assert(pVmcb);
7853	Assert(!pVmcb->ctrl.IntCtrl.n.u1VGifEnable);
7854
7855	VBOXSTRICTRC rcStrict;
7856	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7857	uint64_t const fImport = CPUMCTX_EXTRN_HWVIRT;
7858	if (fSupportsNextRipSave)
7859	{
7860	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7861	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7862	rcStrict = IEMExecDecodedClgi(pVCpu, cbInstr);
7863	}
7864	else
7865	{
7866	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7867	rcStrict = IEMExecOne(pVCpu);
7868	}
7869
7870	if (rcStrict == VINF_SUCCESS)
7871	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
7872	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7873	{
7874	rcStrict = VINF_SUCCESS;
7875	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7876	}
7877	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7878	return VBOXSTRICTRC_TODO(rcStrict);
7879	}
7880
7881
7882	/**
7883	* \#VMEXIT handler for STGI (SVM_EXIT_STGI). Conditional \#VMEXIT.
7884	*/
7885	HMSVM_EXIT_DECL hmR0SvmExitStgi(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7886	{
7887	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7888
7889	/*
7890	* When VGIF is not used we always intercept STGI instructions. When VGIF is used,
7891	* we only intercept STGI when events are pending for GIF to become 1.
7892	*/
7893	PSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7894	if (pVmcb->ctrl.IntCtrl.n.u1VGifEnable)
7895	hmR0SvmClearCtrlIntercept(pVCpu, pVmcb, SVM_CTRL_INTERCEPT_STGI);
7896
7897	VBOXSTRICTRC rcStrict;
7898	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7899	uint64_t const fImport = CPUMCTX_EXTRN_HWVIRT;
7900	if (fSupportsNextRipSave)
7901	{
7902	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7903	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7904	rcStrict = IEMExecDecodedStgi(pVCpu, cbInstr);
7905	}
7906	else
7907	{
7908	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7909	rcStrict = IEMExecOne(pVCpu);
7910	}
7911
7912	if (rcStrict == VINF_SUCCESS)
7913	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_HWVIRT);
7914	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7915	{
7916	rcStrict = VINF_SUCCESS;
7917	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7918	}
7919	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7920	return VBOXSTRICTRC_TODO(rcStrict);
7921	}
7922
7923
7924	/**
7925	* \#VMEXIT handler for VMLOAD (SVM_EXIT_VMLOAD). Conditional \#VMEXIT.
7926	*/
7927	HMSVM_EXIT_DECL hmR0SvmExitVmload(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7928	{
7929	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7930
7931	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7932	Assert(pVmcb);
7933	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7934
7935	VBOXSTRICTRC rcStrict;
7936	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7937	uint64_t const fImport = CPUMCTX_EXTRN_FS \| CPUMCTX_EXTRN_GS \| CPUMCTX_EXTRN_KERNEL_GS_BASE
7938	\| CPUMCTX_EXTRN_TR \| CPUMCTX_EXTRN_LDTR \| CPUMCTX_EXTRN_SYSCALL_MSRS
7939	\| CPUMCTX_EXTRN_SYSENTER_MSRS;
7940	if (fSupportsNextRipSave)
7941	{
7942	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \| fImport);
7943	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7944	rcStrict = IEMExecDecodedVmload(pVCpu, cbInstr);
7945	}
7946	else
7947	{
7948	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK \| fImport);
7949	rcStrict = IEMExecOne(pVCpu);
7950	}
7951
7952	if (rcStrict == VINF_SUCCESS)
7953	{
7954	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_FS \| HM_CHANGED_GUEST_GS
7955	\| HM_CHANGED_GUEST_TR \| HM_CHANGED_GUEST_LDTR
7956	\| HM_CHANGED_GUEST_KERNEL_GS_BASE \| HM_CHANGED_GUEST_SYSCALL_MSRS
7957	\| HM_CHANGED_GUEST_SYSENTER_MSR_MASK);
7958	}
7959	else if (rcStrict == VINF_IEM_RAISED_XCPT)
7960	{
7961	rcStrict = VINF_SUCCESS;
7962	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7963	}
7964	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7965	return VBOXSTRICTRC_TODO(rcStrict);
7966	}
7967
7968
7969	/**
7970	* \#VMEXIT handler for VMSAVE (SVM_EXIT_VMSAVE). Conditional \#VMEXIT.
7971	*/
7972	HMSVM_EXIT_DECL hmR0SvmExitVmsave(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
7973	{
7974	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
7975
7976	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
7977	Assert(!pVmcb->ctrl.LbrVirt.n.u1VirtVmsaveVmload);
7978
7979	VBOXSTRICTRC rcStrict;
7980	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
7981	if (fSupportsNextRipSave)
7982	{
7983	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
7984	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
7985	rcStrict = IEMExecDecodedVmsave(pVCpu, cbInstr);
7986	}
7987	else
7988	{
7989	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
7990	rcStrict = IEMExecOne(pVCpu);
7991	}
7992
7993	if (rcStrict == VINF_IEM_RAISED_XCPT)
7994	{
7995	rcStrict = VINF_SUCCESS;
7996	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
7997	}
7998	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
7999	return VBOXSTRICTRC_TODO(rcStrict);
8000	}
8001
8002
8003	/**
8004	* \#VMEXIT handler for INVLPGA (SVM_EXIT_INVLPGA). Conditional \#VMEXIT.
8005	*/
8006	HMSVM_EXIT_DECL hmR0SvmExitInvlpga(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
8007	{
8008	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8009
8010	VBOXSTRICTRC rcStrict;
8011	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
8012	if (fSupportsNextRipSave)
8013	{
8014	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
8015	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
8016	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
8017	rcStrict = IEMExecDecodedInvlpga(pVCpu, cbInstr);
8018	}
8019	else
8020	{
8021	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
8022	rcStrict = IEMExecOne(pVCpu);
8023	}
8024
8025	if (rcStrict == VINF_IEM_RAISED_XCPT)
8026	{
8027	rcStrict = VINF_SUCCESS;
8028	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
8029	}
8030	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
8031	return VBOXSTRICTRC_TODO(rcStrict);
8032	}
8033
8034
8035	/**
8036	* \#VMEXIT handler for STGI (SVM_EXIT_VMRUN). Conditional \#VMEXIT.
8037	*/
8038	HMSVM_EXIT_DECL hmR0SvmExitVmrun(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
8039	{
8040	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8041	/* We shall import the entire state here, just in case we enter and continue execution of
8042	the nested-guest with hardware-assisted SVM in ring-0, we would be switching VMCBs and
8043	could lose lose part of CPU state. */
8044	HMSVM_CPUMCTX_IMPORT_STATE(pVCpu, HMSVM_CPUMCTX_EXTRN_ALL);
8045
8046	VBOXSTRICTRC rcStrict;
8047	bool const fSupportsNextRipSave = hmR0SvmSupportsNextRipSave(pVCpu);
8048	if (fSupportsNextRipSave)
8049	{
8050	PCSVMVMCB pVmcb = hmR0SvmGetCurrentVmcb(pVCpu);
8051	uint8_t const cbInstr = pVmcb->ctrl.u64NextRIP - pVCpu->cpum.GstCtx.rip;
8052	rcStrict = IEMExecDecodedVmrun(pVCpu, cbInstr);
8053	}
8054	else
8055	{
8056	/* We use IEMExecOneBypassEx() here as it supresses attempt to continue emulating any
8057	instruction(s) when interrupt inhibition is set as part of emulating the VMRUN
8058	instruction itself, see @bugref{7243#c126} */
8059	rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), NULL /* pcbWritten */);
8060	}
8061
8062	if (rcStrict == VINF_SUCCESS)
8063	{
8064	rcStrict = VINF_SVM_VMRUN;
8065	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_SVM_VMRUN_MASK);
8066	}
8067	else if (rcStrict == VINF_IEM_RAISED_XCPT)
8068	{
8069	rcStrict = VINF_SUCCESS;
8070	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
8071	}
8072	HMSVM_CHECK_SINGLE_STEP(pVCpu, rcStrict);
8073	return VBOXSTRICTRC_TODO(rcStrict);
8074	}
8075
8076
8077	/**
8078	* Nested-guest \#VMEXIT handler for debug exceptions (SVM_EXIT_XCPT_1).
8079	* Unconditional \#VMEXIT.
8080	*/
8081	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptDB(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
8082	{
8083	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8084	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
8085
8086	if (pVCpu->hm.s.Event.fPending)
8087	{
8088	STAM_COUNTER_INC(&pVCpu->hm.s.StatInjectPendingInterpret);
8089	return VINF_EM_RAW_INJECT_TRPM_EVENT;
8090	}
8091
8092	hmR0SvmSetPendingXcptDB(pVCpu);
8093	return VINF_SUCCESS;
8094	}
8095
8096
8097	/**
8098	* Nested-guest \#VMEXIT handler for breakpoint exceptions (SVM_EXIT_XCPT_3).
8099	* Conditional \#VMEXIT.
8100	*/
8101	HMSVM_EXIT_DECL hmR0SvmNestedExitXcptBP(PVMCPU pVCpu, PSVMTRANSIENT pSvmTransient)
8102	{
8103	HMSVM_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pSvmTransient);
8104	HMSVM_CHECK_EXIT_DUE_TO_EVENT_DELIVERY(pVCpu, pSvmTransient);
8105
8106	SVMEVENT Event;
8107	Event.u = 0;
8108	Event.n.u1Valid = 1;
8109	Event.n.u3Type = SVM_EVENT_EXCEPTION;
8110	Event.n.u8Vector = X86_XCPT_BP;
8111	hmR0SvmSetPendingEvent(pVCpu, &Event, 0 /* GCPtrFaultAddress */);
8112	return VINF_SUCCESS;
8113	}
8114	#endif /* VBOX_WITH_NESTED_HWVIRT_SVM */
8115
8116	/** @} */
8117

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp@ 73299

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