HMR0.cpp@ 80274

Last change on this file since 80274 was 80274, checked in by vboxsync, 5 years ago
VMM: Refactoring VMMR0/* and VMMRZ/* to use VMCC & VMMCPUCC. bugref:9217
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 68.5 KB

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1	/* $Id: HMR0.cpp 80274 2019-08-14 14:34:38Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define VBOX_BUGREF_9217_PART_I
23	#define LOG_GROUP LOG_GROUP_HM
24	#define VMCPU_INCL_CPUM_GST_CTX
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/pgm.h>
27	#include "HMInternal.h"
28	#include <VBox/vmm/vmcc.h>
29	#include <VBox/vmm/hm_svm.h>
30	#include <VBox/vmm/hmvmxinline.h>
31	#include <VBox/err.h>
32	#include <VBox/log.h>
33	#include <iprt/assert.h>
34	#include <iprt/asm.h>
35	#include <iprt/asm-amd64-x86.h>
36	#include <iprt/cpuset.h>
37	#include <iprt/mem.h>
38	#include <iprt/memobj.h>
39	#include <iprt/once.h>
40	#include <iprt/param.h>
41	#include <iprt/power.h>
42	#include <iprt/string.h>
43	#include <iprt/thread.h>
44	#include <iprt/x86.h>
45	#include "HMVMXR0.h"
46	#include "HMSVMR0.h"
47
48
49	/*********************************************************************************************************************************
50	* Internal Functions *
51	*********************************************************************************************************************************/
52	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
56	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
57	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
58
59
60	/*********************************************************************************************************************************
61	* Structures and Typedefs *
62	*********************************************************************************************************************************/
63	/**
64	* This is used to manage the status code of a RTMpOnAll in HM.
65	*/
66	typedef struct HMR0FIRSTRC
67	{
68	/** The status code. */
69	int32_t volatile rc;
70	/** The ID of the CPU reporting the first failure. */
71	RTCPUID volatile idCpu;
72	} HMR0FIRSTRC;
73	/** Pointer to a first return code structure. */
74	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
75
76
77	/*********************************************************************************************************************************
78	* Global Variables *
79	*********************************************************************************************************************************/
80	/**
81	* Global data.
82	*/
83	static struct
84	{
85	/** Per CPU globals. */
86	HMPHYSCPU aCpuInfo[RTCPUSET_MAX_CPUS];
87
88	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
89	* @{ */
90	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVMCPUCC pVCpu));
91	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit));
92	DECLR0CALLBACKMEMBER(int, pfnExportHostState, (PVMCPUCC pVCpu));
93	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnRunGuestCode, (PVMCPUCC pVCpu));
94	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
95	bool fEnabledByHost, PCSUPHWVIRTMSRS pHwvirtMsrs));
96	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
97	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVMCC pVM));
98	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVMCC pVM));
99	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVMCC pVM));
100	/** @} */
101
102	/** Hardware-virtualization data. */
103	struct
104	{
105	union
106	{
107	/** VT-x data. */
108	struct
109	{
110	/** Host CR4 value (set by ring-0 VMX init) */
111	uint64_t u64HostCr4;
112	/** Host EFER value (set by ring-0 VMX init) */
113	uint64_t u64HostMsrEfer;
114	/** Host SMM monitor control (used for logging/diagnostics) */
115	uint64_t u64HostSmmMonitorCtl;
116	/** Last instruction error. */
117	uint32_t ulLastInstrError;
118	/** The shift mask employed by the VMX-Preemption timer. */
119	uint8_t cPreemptTimerShift;
120	/** Padding. */
121	uint8_t abPadding[3];
122	/** Whether we're using the preemption timer or not. */
123	bool fUsePreemptTimer;
124	/** Whether we're using SUPR0EnableVTx or not. */
125	bool fUsingSUPR0EnableVTx;
126	/** Set if we've called SUPR0EnableVTx(true) and should disable it during
127	* module termination. */
128	bool fCalledSUPR0EnableVTx;
129	/** Set to by us to indicate VMX is supported by the CPU. */
130	bool fSupported;
131	} vmx;
132
133	/** AMD-V data. */
134	struct
135	{
136	/** SVM revision. */
137	uint32_t u32Rev;
138	/** SVM feature bits from cpuid 0x8000000a */
139	uint32_t u32Features;
140	/** Padding. */
141	bool afPadding[3];
142	/** Set by us to indicate SVM is supported by the CPU. */
143	bool fSupported;
144	} svm;
145	} u;
146	/** Maximum allowed ASID/VPID (inclusive). */
147	uint32_t uMaxAsid;
148	/** MSRs. */
149	SUPHWVIRTMSRS Msrs;
150	} hwvirt;
151
152	/** Last recorded error code during HM ring-0 init. */
153	int32_t rcInit;
154
155	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
156	* enabled and disabled each time it's used to execute guest code. */
157	bool fGlobalInit;
158	/** Indicates whether the host is suspending or not. We'll refuse a few
159	* actions when the host is being suspended to speed up the suspending and
160	* avoid trouble. */
161	bool volatile fSuspended;
162
163	/** Whether we've already initialized all CPUs.
164	* @remarks We could check the EnableAllCpusOnce state, but this is
165	* simpler and hopefully easier to understand. */
166	bool fEnabled;
167	/** Serialize initialization in HMR0EnableAllCpus. */
168	RTONCE EnableAllCpusOnce;
169	} g_HmR0;
170
171
172	/**
173	* Initializes a first return code structure.
174	*
175	* @param pFirstRc The structure to init.
176	*/
177	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
178	{
179	pFirstRc->rc = VINF_SUCCESS;
180	pFirstRc->idCpu = NIL_RTCPUID;
181	}
182
183
184	/**
185	* Try set the status code (success ignored).
186	*
187	* @param pFirstRc The first return code structure.
188	* @param rc The status code.
189	*/
190	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
191	{
192	if ( RT_FAILURE(rc)
193	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
194	pFirstRc->idCpu = RTMpCpuId();
195	}
196
197
198	/**
199	* Get the status code of a first return code structure.
200	*
201	* @returns The status code; VINF_SUCCESS or error status, no informational or
202	* warning errors.
203	* @param pFirstRc The first return code structure.
204	*/
205	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
206	{
207	return pFirstRc->rc;
208	}
209
210
211	#ifdef VBOX_STRICT
212	# ifndef DEBUG_bird
213	/**
214	* Get the CPU ID on which the failure status code was reported.
215	*
216	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
217	* @param pFirstRc The first return code structure.
218	*/
219	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
220	{
221	return pFirstRc->idCpu;
222	}
223	# endif
224	#endif /* VBOX_STRICT */
225
226
227	/** @name Dummy callback handlers.
228	* @{ */
229
230	static DECLCALLBACK(int) hmR0DummyEnter(PVMCPUCC pVCpu)
231	{
232	RT_NOREF1(pVCpu);
233	return VINF_SUCCESS;
234	}
235
236	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit)
237	{
238	RT_NOREF3(enmEvent, pVCpu, fGlobalInit);
239	}
240
241	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
242	bool fEnabledBySystem, PCSUPHWVIRTMSRS pHwvirtMsrs)
243	{
244	RT_NOREF6(pHostCpu, pVM, pvCpuPage, HCPhysCpuPage, fEnabledBySystem, pHwvirtMsrs);
245	return VINF_SUCCESS;
246	}
247
248	static DECLCALLBACK(int) hmR0DummyDisableCpu(void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
249	{
250	RT_NOREF2(pvCpuPage, HCPhysCpuPage);
251	return VINF_SUCCESS;
252	}
253
254	static DECLCALLBACK(int) hmR0DummyInitVM(PVMCC pVM)
255	{
256	RT_NOREF1(pVM);
257	return VINF_SUCCESS;
258	}
259
260	static DECLCALLBACK(int) hmR0DummyTermVM(PVMCC pVM)
261	{
262	RT_NOREF1(pVM);
263	return VINF_SUCCESS;
264	}
265
266	static DECLCALLBACK(int) hmR0DummySetupVM(PVMCC pVM)
267	{
268	RT_NOREF1(pVM);
269	return VINF_SUCCESS;
270	}
271
272	static DECLCALLBACK(VBOXSTRICTRC) hmR0DummyRunGuestCode(PVMCPUCC pVCpu)
273	{
274	RT_NOREF(pVCpu);
275	return VINF_SUCCESS;
276	}
277
278	static DECLCALLBACK(int) hmR0DummyExportHostState(PVMCPUCC pVCpu)
279	{
280	RT_NOREF1(pVCpu);
281	return VINF_SUCCESS;
282	}
283
284	/** @} */
285
286
287	/**
288	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
289	* Down at the Rate Specified" erratum.
290	*
291	* Errata names and related steppings:
292	* - BA86 - D0.
293	* - AAX65 - C2.
294	* - AAU65 - C2, K0.
295	* - AAO95 - B1.
296	* - AAT59 - C2.
297	* - AAK139 - D0.
298	* - AAM126 - C0, C1, D0.
299	* - AAN92 - B1.
300	* - AAJ124 - C0, D0.
301	* - AAP86 - B1.
302	*
303	* Steppings: B1, C0, C1, C2, D0, K0.
304	*
305	* @returns true if subject to it, false if not.
306	*/
307	static bool hmR0InitIntelIsSubjectToVmxPreemptTimerErratum(void)
308	{
309	uint32_t u = ASMCpuId_EAX(1);
310	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
311	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
312	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
313	/* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
314	/* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
315	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
316	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
317	/* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
318	/* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
319	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
320	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
321	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
322	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
323	/* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
324	/* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
325	)
326	return true;
327	return false;
328	}
329
330
331	/**
332	* Intel specific initialization code.
333	*
334	* @returns VBox status code (will only fail if out of memory).
335	*/
336	static int hmR0InitIntel(void)
337	{
338	/* Read this MSR now as it may be useful for error reporting when initializing VT-x fails. */
339	g_HmR0.hwvirt.Msrs.u.vmx.u64FeatCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
340
341	/*
342	* First try use native kernel API for controlling VT-x.
343	* (This is only supported by some Mac OS X kernels atm.)
344	*/
345	int rc = g_HmR0.rcInit = SUPR0EnableVTx(true /* fEnable */);
346	g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
347	if (g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
348	{
349	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
350	if (RT_SUCCESS(rc))
351	{
352	g_HmR0.hwvirt.u.vmx.fSupported = true;
353	rc = SUPR0EnableVTx(false /* fEnable */);
354	AssertLogRelRC(rc);
355	}
356	}
357	else
358	{
359	HMR0FIRSTRC FirstRc;
360	hmR0FirstRcInit(&FirstRc);
361	g_HmR0.rcInit = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
362	if (RT_SUCCESS(g_HmR0.rcInit))
363	g_HmR0.rcInit = hmR0FirstRcGetStatus(&FirstRc);
364	}
365
366	if (RT_SUCCESS(g_HmR0.rcInit))
367	{
368	/* Read CR4 and EFER for logging/diagnostic purposes. */
369	g_HmR0.hwvirt.u.vmx.u64HostCr4 = ASMGetCR4();
370	g_HmR0.hwvirt.u.vmx.u64HostMsrEfer = ASMRdMsr(MSR_K6_EFER);
371
372	/* Get VMX MSRs for determining VMX features we can ultimately use. */
373	SUPR0GetHwvirtMsrs(&g_HmR0.hwvirt.Msrs, SUPVTCAPS_VT_X, false /* fForce */);
374
375	/*
376	* Nested KVM workaround: Intel SDM section 34.15.5 describes that
377	* MSR_IA32_SMM_MONITOR_CTL depends on bit 49 of MSR_IA32_VMX_BASIC while
378	* table 35-2 says that this MSR is available if either VMX or SMX is supported.
379	*/
380	uint64_t const uVmxBasicMsr = g_HmR0.hwvirt.Msrs.u.vmx.u64Basic;
381	if (RT_BF_GET(uVmxBasicMsr, VMX_BF_BASIC_DUAL_MON))
382	g_HmR0.hwvirt.u.vmx.u64HostSmmMonitorCtl = ASMRdMsr(MSR_IA32_SMM_MONITOR_CTL);
383
384	/* Initialize VPID - 16 bits ASID. */
385	g_HmR0.hwvirt.uMaxAsid = 0x10000; /* exclusive */
386
387	/*
388	* If the host OS has not enabled VT-x for us, try enter VMX root mode
389	* to really verify if VT-x is usable.
390	*/
391	if (!g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
392	{
393	/* Allocate a temporary VMXON region. */
394	RTR0MEMOBJ hScatchMemObj;
395	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
396	if (RT_FAILURE(rc))
397	{
398	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
399	return rc;
400	}
401	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
402	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
403	ASMMemZeroPage(pvScatchPage);
404
405	/* Set revision dword at the beginning of the VMXON structure. */
406	(uint32_t )pvScatchPage = RT_BF_GET(uVmxBasicMsr, VMX_BF_BASIC_VMCS_ID);
407
408	/* Make sure we don't get rescheduled to another CPU during this probe. */
409	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
410
411	/* Check CR4.VMXE. */
412	g_HmR0.hwvirt.u.vmx.u64HostCr4 = ASMGetCR4();
413	if (!(g_HmR0.hwvirt.u.vmx.u64HostCr4 & X86_CR4_VMXE))
414	{
415	/* In theory this bit could be cleared behind our back. Which would cause #UD
416	faults when we try to execute the VMX instructions... */
417	ASMSetCR4(g_HmR0.hwvirt.u.vmx.u64HostCr4 \| X86_CR4_VMXE);
418	}
419
420	/*
421	* The only way of checking if we're in VMX root mode or not is to try and enter it.
422	* There is no instruction or control bit that tells us if we're in VMX root mode.
423	* Therefore, try and enter VMX root mode here.
424	*/
425	rc = VMXEnable(HCPhysScratchPage);
426	if (RT_SUCCESS(rc))
427	{
428	g_HmR0.hwvirt.u.vmx.fSupported = true;
429	VMXDisable();
430	}
431	else
432	{
433	/*
434	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
435	* it will crash the host when we enter raw mode, because:
436	*
437	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
438	* this bit), and
439	* (b) turning off paging causes a #GP (unavoidable when switching
440	* from long to 32 bits mode or 32 bits to PAE).
441	*
442	* They should fix their code, but until they do we simply refuse to run.
443	*/
444	g_HmR0.rcInit = VERR_VMX_IN_VMX_ROOT_MODE;
445	Assert(g_HmR0.hwvirt.u.vmx.fSupported == false);
446	}
447
448	/*
449	* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it was not
450	* set before (some software could incorrectly think it is in VMX mode).
451	*/
452	ASMSetCR4(g_HmR0.hwvirt.u.vmx.u64HostCr4);
453	ASMSetFlags(fEFlags);
454
455	RTR0MemObjFree(hScatchMemObj, false);
456	}
457
458	if (g_HmR0.hwvirt.u.vmx.fSupported)
459	{
460	rc = VMXR0GlobalInit();
461	if (RT_FAILURE(rc))
462	g_HmR0.rcInit = rc;
463
464	/*
465	* Install the VT-x methods.
466	*/
467	g_HmR0.pfnEnterSession = VMXR0Enter;
468	g_HmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
469	g_HmR0.pfnExportHostState = VMXR0ExportHostState;
470	g_HmR0.pfnRunGuestCode = VMXR0RunGuestCode;
471	g_HmR0.pfnEnableCpu = VMXR0EnableCpu;
472	g_HmR0.pfnDisableCpu = VMXR0DisableCpu;
473	g_HmR0.pfnInitVM = VMXR0InitVM;
474	g_HmR0.pfnTermVM = VMXR0TermVM;
475	g_HmR0.pfnSetupVM = VMXR0SetupVM;
476
477	/*
478	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
479	* Timer Does Not Count Down at the Rate Specified" CPU erratum.
480	*/
481	VMXCTLSMSR PinCtls;
482	PinCtls.u = g_HmR0.hwvirt.Msrs.u.vmx.u64PinCtls;
483	if (PinCtls.n.allowed1 & VMX_PIN_CTLS_PREEMPT_TIMER)
484	{
485	uint64_t const uVmxMiscMsr = g_HmR0.hwvirt.Msrs.u.vmx.u64Misc;
486	g_HmR0.hwvirt.u.vmx.fUsePreemptTimer = true;
487	g_HmR0.hwvirt.u.vmx.cPreemptTimerShift = RT_BF_GET(uVmxMiscMsr, VMX_BF_MISC_PREEMPT_TIMER_TSC);
488	if (hmR0InitIntelIsSubjectToVmxPreemptTimerErratum())
489	g_HmR0.hwvirt.u.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
490	}
491	}
492	}
493	#ifdef LOG_ENABLED
494	else
495	SUPR0Printf("hmR0InitIntelCpu failed with rc=%Rrc\n", g_HmR0.rcInit);
496	#endif
497	return VINF_SUCCESS;
498	}
499
500
501	/**
502	* AMD-specific initialization code.
503	*
504	* @returns VBox status code (will only fail if out of memory).
505	*/
506	static int hmR0InitAmd(void)
507	{
508	/* Call the global AMD-V initialization routine (should only fail in out-of-memory situations). */
509	int rc = SVMR0GlobalInit();
510	if (RT_FAILURE(rc))
511	{
512	g_HmR0.rcInit = rc;
513	return rc;
514	}
515
516	/*
517	* Install the AMD-V methods.
518	*/
519	g_HmR0.pfnEnterSession = SVMR0Enter;
520	g_HmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
521	g_HmR0.pfnExportHostState = SVMR0ExportHostState;
522	g_HmR0.pfnRunGuestCode = SVMR0RunGuestCode;
523	g_HmR0.pfnEnableCpu = SVMR0EnableCpu;
524	g_HmR0.pfnDisableCpu = SVMR0DisableCpu;
525	g_HmR0.pfnInitVM = SVMR0InitVM;
526	g_HmR0.pfnTermVM = SVMR0TermVM;
527	g_HmR0.pfnSetupVM = SVMR0SetupVM;
528
529	/* Query AMD features. */
530	uint32_t u32Dummy;
531	ASMCpuId(0x8000000a, &g_HmR0.hwvirt.u.svm.u32Rev, &g_HmR0.hwvirt.uMaxAsid, &u32Dummy, &g_HmR0.hwvirt.u.svm.u32Features);
532
533	/*
534	* We need to check if AMD-V has been properly initialized on all CPUs.
535	* Some BIOSes might do a poor job.
536	*/
537	HMR0FIRSTRC FirstRc;
538	hmR0FirstRcInit(&FirstRc);
539	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
540	AssertRC(rc);
541	if (RT_SUCCESS(rc))
542	rc = hmR0FirstRcGetStatus(&FirstRc);
543	#ifndef DEBUG_bird
544	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
545	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
546	#endif
547	if (RT_SUCCESS(rc))
548	{
549	SUPR0GetHwvirtMsrs(&g_HmR0.hwvirt.Msrs, SUPVTCAPS_AMD_V, false /* fForce */);
550	g_HmR0.hwvirt.u.svm.fSupported = true;
551	}
552	else
553	{
554	g_HmR0.rcInit = rc;
555	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
556	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
557	}
558	return rc;
559	}
560
561
562	/**
563	* Does global Ring-0 HM initialization (at module init).
564	*
565	* @returns VBox status code.
566	*/
567	VMMR0_INT_DECL(int) HMR0Init(void)
568	{
569	/*
570	* Initialize the globals.
571	*/
572	g_HmR0.fEnabled = false;
573	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
574	g_HmR0.EnableAllCpusOnce = s_OnceInit;
575	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
576	{
577	g_HmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
578	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
579	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
580	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
581	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
582	g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
583	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
584	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
585	#endif
586	}
587
588	/* Fill in all callbacks with placeholders. */
589	g_HmR0.pfnEnterSession = hmR0DummyEnter;
590	g_HmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
591	g_HmR0.pfnExportHostState = hmR0DummyExportHostState;
592	g_HmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
593	g_HmR0.pfnEnableCpu = hmR0DummyEnableCpu;
594	g_HmR0.pfnDisableCpu = hmR0DummyDisableCpu;
595	g_HmR0.pfnInitVM = hmR0DummyInitVM;
596	g_HmR0.pfnTermVM = hmR0DummyTermVM;
597	g_HmR0.pfnSetupVM = hmR0DummySetupVM;
598
599	/* Default is global VT-x/AMD-V init. */
600	g_HmR0.fGlobalInit = true;
601
602	/*
603	* Make sure aCpuInfo is big enough for all the CPUs on this system.
604	*/
605	if (RTMpGetArraySize() > RT_ELEMENTS(g_HmR0.aCpuInfo))
606	{
607	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HmR0.aCpuInfo)));
608	return VERR_TOO_MANY_CPUS;
609	}
610
611	/*
612	* Check for VT-x or AMD-V support.
613	* Return failure only in out-of-memory situations.
614	*/
615	uint32_t fCaps = 0;
616	int rc = SUPR0GetVTSupport(&fCaps);
617	if (RT_SUCCESS(rc))
618	{
619	if (fCaps & SUPVTCAPS_VT_X)
620	{
621	rc = hmR0InitIntel();
622	if (RT_FAILURE(rc))
623	return rc;
624	}
625	else
626	{
627	Assert(fCaps & SUPVTCAPS_AMD_V);
628	rc = hmR0InitAmd();
629	if (RT_FAILURE(rc))
630	return rc;
631	}
632	}
633	else
634	g_HmR0.rcInit = VERR_UNSUPPORTED_CPU;
635
636	/*
637	* Register notification callbacks that we can use to disable/enable CPUs
638	* when brought offline/online or suspending/resuming.
639	*/
640	if (!g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
641	{
642	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
643	AssertRC(rc);
644
645	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
646	AssertRC(rc);
647	}
648
649	/* We return success here because module init shall not fail if HM fails to initialize. */
650	return VINF_SUCCESS;
651	}
652
653
654	/**
655	* Does global Ring-0 HM termination (at module termination).
656	*
657	* @returns VBox status code.
658	*/
659	VMMR0_INT_DECL(int) HMR0Term(void)
660	{
661	int rc;
662	if ( g_HmR0.hwvirt.u.vmx.fSupported
663	&& g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
664	{
665	/*
666	* Simple if the host OS manages VT-x.
667	*/
668	Assert(g_HmR0.fGlobalInit);
669
670	if (g_HmR0.hwvirt.u.vmx.fCalledSUPR0EnableVTx)
671	{
672	rc = SUPR0EnableVTx(false /* fEnable */);
673	g_HmR0.hwvirt.u.vmx.fCalledSUPR0EnableVTx = false;
674	}
675	else
676	rc = VINF_SUCCESS;
677
678	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HmR0.aCpuInfo); iCpu++)
679	{
680	g_HmR0.aCpuInfo[iCpu].fConfigured = false;
681	Assert(g_HmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
682	}
683	}
684	else
685	{
686	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
687
688	/* Doesn't really matter if this fails. */
689	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
690	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
691
692	/*
693	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
694	*/
695	if (g_HmR0.fGlobalInit)
696	{
697	HMR0FIRSTRC FirstRc;
698	hmR0FirstRcInit(&FirstRc);
699	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
700	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
701	if (RT_SUCCESS(rc))
702	rc = hmR0FirstRcGetStatus(&FirstRc);
703	}
704
705	/*
706	* Free the per-cpu pages used for VT-x and AMD-V.
707	*/
708	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
709	{
710	if (g_HmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
711	{
712	RTR0MemObjFree(g_HmR0.aCpuInfo[i].hMemObj, false);
713	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
714	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
715	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
716	}
717	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
718	if (g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm != NIL_RTR0MEMOBJ)
719	{
720	RTR0MemObjFree(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, false);
721	g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
722	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
723	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
724	}
725	#endif
726	}
727	}
728
729	/** @todo This needs cleaning up. There's no matching
730	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
731	* should move into their respective modules. */
732	/* Finally, call global VT-x/AMD-V termination. */
733	if (g_HmR0.hwvirt.u.vmx.fSupported)
734	VMXR0GlobalTerm();
735	else if (g_HmR0.hwvirt.u.svm.fSupported)
736	SVMR0GlobalTerm();
737
738	return rc;
739	}
740
741
742	/**
743	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
744	* on a CPU.
745	*
746	* @param idCpu The identifier for the CPU the function is called on.
747	* @param pvUser1 Pointer to the first RC structure.
748	* @param pvUser2 Ignored.
749	*/
750	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
751	{
752	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
753	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
754	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
755	NOREF(idCpu); NOREF(pvUser2);
756
757	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
758	hmR0FirstRcSetStatus(pFirstRc, rc);
759	}
760
761
762	/**
763	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
764	* on a CPU.
765	*
766	* @param idCpu The identifier for the CPU the function is called on.
767	* @param pvUser1 Pointer to the first RC structure.
768	* @param pvUser2 Ignored.
769	*/
770	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
771	{
772	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
773	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
774	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
775	NOREF(idCpu); NOREF(pvUser2);
776
777	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
778	hmR0FirstRcSetStatus(pFirstRc, rc);
779	}
780
781
782	/**
783	* Enable VT-x or AMD-V on the current CPU
784	*
785	* @returns VBox status code.
786	* @param pVM The cross context VM structure. Can be NULL.
787	* @param idCpu The identifier for the CPU the function is called on.
788	*
789	* @remarks Maybe called with interrupts disabled!
790	*/
791	static int hmR0EnableCpu(PVMCC pVM, RTCPUID idCpu)
792	{
793	PHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
794
795	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
796	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
797	Assert(!pHostCpu->fConfigured);
798	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
799
800	pHostCpu->idCpu = idCpu;
801	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
802
803	int rc;
804	if ( g_HmR0.hwvirt.u.vmx.fSupported
805	&& g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
806	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmR0.hwvirt.Msrs);
807	else
808	{
809	AssertLogRelMsgReturn(pHostCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
810	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, &g_HmR0.hwvirt.Msrs);
811	}
812	if (RT_SUCCESS(rc))
813	pHostCpu->fConfigured = true;
814	return rc;
815	}
816
817
818	/**
819	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
820	*
821	* @param idCpu The identifier for the CPU the function is called on.
822	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
823	* @param pvUser2 The 2nd user argument.
824	*/
825	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
826	{
827	PVMCC pVM = (PVMCC)pvUser1; /* can be NULL! */
828	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
829	AssertReturnVoid(g_HmR0.fGlobalInit);
830	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
831	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
832	}
833
834
835	/**
836	* RTOnce callback employed by HMR0EnableAllCpus.
837	*
838	* @returns VBox status code.
839	* @param pvUser Pointer to the VM.
840	*/
841	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
842	{
843	PVMCC pVM = (PVMCC)pvUser;
844
845	/*
846	* Indicate that we've initialized.
847	*
848	* Note! There is a potential race between this function and the suspend
849	* notification. Kind of unlikely though, so ignored for now.
850	*/
851	AssertReturn(!g_HmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
852	ASMAtomicWriteBool(&g_HmR0.fEnabled, true);
853
854	/*
855	* The global init variable is set by the first VM.
856	*/
857	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
858
859	#ifdef VBOX_STRICT
860	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
861	{
862	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
863	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj == NIL_RTHCPHYS);
864	Assert(g_HmR0.aCpuInfo[i].pvMemObj == NULL);
865	Assert(!g_HmR0.aCpuInfo[i].fConfigured);
866	Assert(!g_HmR0.aCpuInfo[i].cTlbFlushes);
867	Assert(!g_HmR0.aCpuInfo[i].uCurrentAsid);
868	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
869	Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
870	Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm == NIL_RTHCPHYS);
871	Assert(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm == NULL);
872	# endif
873	}
874	#endif
875
876	int rc;
877	if ( g_HmR0.hwvirt.u.vmx.fSupported
878	&& g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx)
879	{
880	/*
881	* Global VT-x initialization API (only darwin for now).
882	*/
883	rc = SUPR0EnableVTx(true /* fEnable */);
884	if (RT_SUCCESS(rc))
885	{
886	g_HmR0.hwvirt.u.vmx.fCalledSUPR0EnableVTx = true;
887	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
888	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
889	}
890	else
891	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
892	}
893	else
894	{
895	/*
896	* We're doing the job ourselves.
897	*/
898	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
899	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
900	{
901	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
902	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
903	Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
904	#endif
905	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
906	{
907	/** @todo NUMA */
908	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
909	AssertLogRelRCReturn(rc, rc);
910
911	g_HmR0.aCpuInfo[i].HCPhysMemObj = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].hMemObj, 0);
912	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj != NIL_RTHCPHYS);
913	Assert(!(g_HmR0.aCpuInfo[i].HCPhysMemObj & PAGE_OFFSET_MASK));
914
915	g_HmR0.aCpuInfo[i].pvMemObj = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].hMemObj);
916	AssertPtr(g_HmR0.aCpuInfo[i].pvMemObj);
917	ASMMemZeroPage(g_HmR0.aCpuInfo[i].pvMemObj);
918
919	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
920	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
921	false /* executable R0 mapping */);
922	AssertLogRelRCReturn(rc, rc);
923
924	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, 0);
925	Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm != NIL_RTHCPHYS);
926	Assert(!(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm & PAGE_OFFSET_MASK));
927
928	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm);
929	AssertPtr(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm);
930	ASMMemFill32(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
931	#endif
932	}
933	}
934
935	rc = VINF_SUCCESS;
936	}
937
938	if ( RT_SUCCESS(rc)
939	&& g_HmR0.fGlobalInit)
940	{
941	/* First time, so initialize each cpu/core. */
942	HMR0FIRSTRC FirstRc;
943	hmR0FirstRcInit(&FirstRc);
944	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
945	if (RT_SUCCESS(rc))
946	rc = hmR0FirstRcGetStatus(&FirstRc);
947	}
948
949	return rc;
950	}
951
952
953	/**
954	* Sets up HM on all cpus.
955	*
956	* @returns VBox status code.
957	* @param pVM The cross context VM structure.
958	*/
959	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVMCC pVM)
960	{
961	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
962	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
963	return VERR_HM_SUSPEND_PENDING;
964
965	return RTOnce(&g_HmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
966	}
967
968
969	/**
970	* Disable VT-x or AMD-V on the current CPU.
971	*
972	* @returns VBox status code.
973	* @param idCpu The identifier for the CPU this function is called on.
974	*
975	* @remarks Must be called with preemption disabled.
976	*/
977	static int hmR0DisableCpu(RTCPUID idCpu)
978	{
979	PHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
980
981	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
982	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
983	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
984	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
985	Assert(!pHostCpu->fConfigured \|\| pHostCpu->hMemObj != NIL_RTR0MEMOBJ);
986	AssertRelease(idCpu == RTMpCpuId());
987
988	if (pHostCpu->hMemObj == NIL_RTR0MEMOBJ)
989	return pHostCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
990	AssertPtr(pHostCpu->pvMemObj);
991	Assert(pHostCpu->HCPhysMemObj != NIL_RTHCPHYS);
992
993	int rc;
994	if (pHostCpu->fConfigured)
995	{
996	rc = g_HmR0.pfnDisableCpu(pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj);
997	AssertRCReturn(rc, rc);
998
999	pHostCpu->fConfigured = false;
1000	pHostCpu->idCpu = NIL_RTCPUID;
1001	}
1002	else
1003	rc = VINF_SUCCESS; /* nothing to do */
1004	return rc;
1005	}
1006
1007
1008	/**
1009	* Worker function passed to RTMpOnAll() that is to be called on the target
1010	* CPUs.
1011	*
1012	* @param idCpu The identifier for the CPU the function is called on.
1013	* @param pvUser1 The 1st user argument.
1014	* @param pvUser2 Opaque pointer to the FirstRc.
1015	*/
1016	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1017	{
1018	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1019	AssertReturnVoid(g_HmR0.fGlobalInit);
1020	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1021	}
1022
1023
1024	/**
1025	* Worker function passed to RTMpOnSpecific() that is to be called on the target
1026	* CPU.
1027	*
1028	* @param idCpu The identifier for the CPU the function is called on.
1029	* @param pvUser1 Null, not used.
1030	* @param pvUser2 Null, not used.
1031	*/
1032	static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1033	{
1034	NOREF(pvUser1);
1035	NOREF(pvUser2);
1036	hmR0DisableCpu(idCpu);
1037	}
1038
1039
1040	/**
1041	* Callback function invoked when a cpu goes online or offline.
1042	*
1043	* @param enmEvent The Mp event.
1044	* @param idCpu The identifier for the CPU the function is called on.
1045	* @param pvData Opaque data (PVMCC pointer).
1046	*/
1047	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1048	{
1049	NOREF(pvData);
1050	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
1051
1052	/*
1053	* We only care about uninitializing a CPU that is going offline. When a
1054	* CPU comes online, the initialization is done lazily in HMR0Enter().
1055	*/
1056	switch (enmEvent)
1057	{
1058	case RTMPEVENT_OFFLINE:
1059	{
1060	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1061	RTThreadPreemptDisable(&PreemptState);
1062	if (idCpu == RTMpCpuId())
1063	{
1064	int rc = hmR0DisableCpu(idCpu);
1065	AssertRC(rc);
1066	RTThreadPreemptRestore(&PreemptState);
1067	}
1068	else
1069	{
1070	RTThreadPreemptRestore(&PreemptState);
1071	RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 /, NULL / pvUser2 */);
1072	}
1073	break;
1074	}
1075
1076	default:
1077	break;
1078	}
1079	}
1080
1081
1082	/**
1083	* Called whenever a system power state change occurs.
1084	*
1085	* @param enmEvent The Power event.
1086	* @param pvUser User argument.
1087	*/
1088	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1089	{
1090	NOREF(pvUser);
1091	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
1092
1093	#ifdef LOG_ENABLED
1094	if (enmEvent == RTPOWEREVENT_SUSPEND)
1095	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1096	else
1097	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1098	#endif
1099
1100	if (enmEvent == RTPOWEREVENT_SUSPEND)
1101	ASMAtomicWriteBool(&g_HmR0.fSuspended, true);
1102
1103	if (g_HmR0.fEnabled)
1104	{
1105	int rc;
1106	HMR0FIRSTRC FirstRc;
1107	hmR0FirstRcInit(&FirstRc);
1108
1109	if (enmEvent == RTPOWEREVENT_SUSPEND)
1110	{
1111	if (g_HmR0.fGlobalInit)
1112	{
1113	/* Turn off VT-x or AMD-V on all CPUs. */
1114	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1115	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1116	}
1117	/* else nothing to do here for the local init case */
1118	}
1119	else
1120	{
1121	/* Reinit the CPUs from scratch as the suspend state might have
1122	messed with the MSRs. (lousy BIOSes as usual) */
1123	if (g_HmR0.hwvirt.u.vmx.fSupported)
1124	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1125	else
1126	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1127	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1128	if (RT_SUCCESS(rc))
1129	rc = hmR0FirstRcGetStatus(&FirstRc);
1130	#ifdef LOG_ENABLED
1131	if (RT_FAILURE(rc))
1132	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1133	#endif
1134	if (g_HmR0.fGlobalInit)
1135	{
1136	/* Turn VT-x or AMD-V back on on all CPUs. */
1137	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1138	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1139	}
1140	/* else nothing to do here for the local init case */
1141	}
1142	}
1143
1144	if (enmEvent == RTPOWEREVENT_RESUME)
1145	ASMAtomicWriteBool(&g_HmR0.fSuspended, false);
1146	}
1147
1148
1149	/**
1150	* Does ring-0 per-VM HM initialization.
1151	*
1152	* This will call the CPU specific init. routine which may initialize and allocate
1153	* resources for virtual CPUs.
1154	*
1155	* @returns VBox status code.
1156	* @param pVM The cross context VM structure.
1157	*
1158	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1159	* vmR3InitRing3().
1160	*/
1161	VMMR0_INT_DECL(int) HMR0InitVM(PVMCC pVM)
1162	{
1163	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1164
1165	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1166	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1167	return VERR_HM_SUSPEND_PENDING;
1168
1169	/*
1170	* Copy globals to the VM structure.
1171	*/
1172	Assert(!(pVM->hm.s.vmx.fSupported && pVM->hm.s.svm.fSupported));
1173	if (pVM->hm.s.vmx.fSupported)
1174	{
1175	pVM->hm.s.vmx.fUsePreemptTimer &= g_HmR0.hwvirt.u.vmx.fUsePreemptTimer; /* Can be overridden by CFGM in HMR3Init(). */
1176	pVM->hm.s.vmx.cPreemptTimerShift = g_HmR0.hwvirt.u.vmx.cPreemptTimerShift;
1177	pVM->hm.s.vmx.u64HostCr4 = g_HmR0.hwvirt.u.vmx.u64HostCr4;
1178	pVM->hm.s.vmx.u64HostMsrEfer = g_HmR0.hwvirt.u.vmx.u64HostMsrEfer;
1179	pVM->hm.s.vmx.u64HostSmmMonitorCtl = g_HmR0.hwvirt.u.vmx.u64HostSmmMonitorCtl;
1180	HMGetVmxMsrsFromHwvirtMsrs(&g_HmR0.hwvirt.Msrs, &pVM->hm.s.vmx.Msrs);
1181	/* If you need to tweak host MSRs for testing VMX R0 code, do it here. */
1182
1183	/* Enable VPID if supported and configured. */
1184	if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VPID)
1185	pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid; /* Can be overridden by CFGM in HMR3Init(). */
1186
1187	/* Use VMCS shadowing if supported. */
1188	Assert(!pVM->hm.s.vmx.fUseVmcsShadowing);
1189	if ( pVM->cpum.ro.GuestFeatures.fVmx
1190	&& (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VMCS_SHADOWING))
1191	pVM->hm.s.vmx.fUseVmcsShadowing = true;
1192
1193	/* Use the VMCS controls for swapping the EFER MSR if supported. */
1194	Assert(!pVM->hm.s.vmx.fSupportsVmcsEfer);
1195	if ( (pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1 & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
1196	&& (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1197	&& (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_SAVE_EFER_MSR))
1198	pVM->hm.s.vmx.fSupportsVmcsEfer = true;
1199
1200	#if 0
1201	/* Enable APIC register virtualization and virtual-interrupt delivery if supported. */
1202	if ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT)
1203	&& (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY))
1204	pVM->hm.s.fVirtApicRegs = true;
1205
1206	/* Enable posted-interrupt processing if supported. */
1207	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1208	* here. */
1209	if ( (pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_POSTED_INT)
1210	&& (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT))
1211	pVM->hm.s.fPostedIntrs = true;
1212	#endif
1213	}
1214	else if (pVM->hm.s.svm.fSupported)
1215	{
1216	pVM->hm.s.svm.u32Rev = g_HmR0.hwvirt.u.svm.u32Rev;
1217	pVM->hm.s.svm.u32Features = g_HmR0.hwvirt.u.svm.u32Features;
1218	pVM->hm.s.svm.u64MsrHwcr = g_HmR0.hwvirt.Msrs.u.svm.u64MsrHwcr;
1219	/* If you need to tweak host MSRs for testing SVM R0 code, do it here. */
1220	}
1221	pVM->hm.s.rcInit = g_HmR0.rcInit;
1222	pVM->hm.s.uMaxAsid = g_HmR0.hwvirt.uMaxAsid;
1223
1224	/*
1225	* Set default maximum inner loops in ring-0 before returning to ring-3.
1226	* Can be overriden using CFGM.
1227	*/
1228	if (!pVM->hm.s.cMaxResumeLoops)
1229	{
1230	pVM->hm.s.cMaxResumeLoops = 1024;
1231	if (RTThreadPreemptIsPendingTrusty())
1232	pVM->hm.s.cMaxResumeLoops = 8192;
1233	}
1234
1235	/*
1236	* Initialize some per-VCPU fields.
1237	*/
1238	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1239	{
1240	PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
1241	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1242	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1243
1244	/* We'll aways increment this the first time (host uses ASID 0). */
1245	AssertReturn(!pVCpu->hm.s.uCurrentAsid, VERR_HM_IPE_3);
1246	}
1247
1248	/*
1249	* Get host kernel features that HM might need to know in order
1250	* to co-operate and function properly with the host OS (e.g. SMAP).
1251	*
1252	* Technically, we could do this as part of the pre-init VM procedure
1253	* but it shouldn't be done later than this point so we do it here.
1254	*/
1255	pVM->hm.s.fHostKernelFeatures = SUPR0GetKernelFeatures();
1256
1257	/*
1258	* Call the hardware specific initialization method.
1259	*/
1260	return g_HmR0.pfnInitVM(pVM);
1261	}
1262
1263
1264	/**
1265	* Does ring-0 per VM HM termination.
1266	*
1267	* @returns VBox status code.
1268	* @param pVM The cross context VM structure.
1269	*/
1270	VMMR0_INT_DECL(int) HMR0TermVM(PVMCC pVM)
1271	{
1272	Log(("HMR0TermVM: %p\n", pVM));
1273	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1274
1275	/*
1276	* Call the hardware specific method.
1277	*
1278	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1279	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1280	*/
1281	return g_HmR0.pfnTermVM(pVM);
1282	}
1283
1284
1285	/**
1286	* Sets up a VT-x or AMD-V session.
1287	*
1288	* This is mostly about setting up the hardware VM state.
1289	*
1290	* @returns VBox status code.
1291	* @param pVM The cross context VM structure.
1292	*/
1293	VMMR0_INT_DECL(int) HMR0SetupVM(PVMCC pVM)
1294	{
1295	Log(("HMR0SetupVM: %p\n", pVM));
1296	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1297
1298	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1299	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1300
1301	/* On first entry we'll sync everything. */
1302	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1303
1304	/*
1305	* Call the hardware specific setup VM method. This requires the CPU to be
1306	* enabled for AMD-V/VT-x and preemption to be prevented.
1307	*/
1308	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1309	RTThreadPreemptDisable(&PreemptState);
1310	RTCPUID const idCpu = RTMpCpuId();
1311
1312	/* Enable VT-x or AMD-V if local init is required. */
1313	int rc;
1314	if (!g_HmR0.fGlobalInit)
1315	{
1316	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
1317	rc = hmR0EnableCpu(pVM, idCpu);
1318	if (RT_FAILURE(rc))
1319	{
1320	RTThreadPreemptRestore(&PreemptState);
1321	return rc;
1322	}
1323	}
1324
1325	/* Setup VT-x or AMD-V. */
1326	rc = g_HmR0.pfnSetupVM(pVM);
1327
1328	/* Disable VT-x or AMD-V if local init was done before. */
1329	if (!g_HmR0.fGlobalInit)
1330	{
1331	Assert(!g_HmR0.hwvirt.u.vmx.fSupported \|\| !g_HmR0.hwvirt.u.vmx.fUsingSUPR0EnableVTx);
1332	int rc2 = hmR0DisableCpu(idCpu);
1333	AssertRC(rc2);
1334	}
1335
1336	RTThreadPreemptRestore(&PreemptState);
1337	return rc;
1338	}
1339
1340
1341	/**
1342	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1343	* required for entering HM context.
1344	*
1345	* @returns VBox status code.
1346	* @param pVCpu The cross context virtual CPU structure.
1347	*
1348	* @remarks No-long-jump zone!!!
1349	*/
1350	VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPUCC pVCpu)
1351	{
1352	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1353
1354	int rc = VINF_SUCCESS;
1355	RTCPUID const idCpu = RTMpCpuId();
1356	PHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1357	AssertPtr(pHostCpu);
1358
1359	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1360	if (!pHostCpu->fConfigured)
1361	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1362
1363	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1364	if (g_HmR0.hwvirt.u.vmx.fSupported)
1365	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE;
1366	else
1367	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE;
1368
1369	Assert(pHostCpu->idCpu == idCpu && pHostCpu->idCpu != NIL_RTCPUID);
1370	pVCpu->hm.s.idEnteredCpu = idCpu;
1371	return rc;
1372	}
1373
1374
1375	/**
1376	* Enters the VT-x or AMD-V session.
1377	*
1378	* @returns VBox status code.
1379	* @param pVCpu The cross context virtual CPU structure.
1380	*
1381	* @remarks This is called with preemption disabled.
1382	*/
1383	VMMR0_INT_DECL(int) HMR0Enter(PVMCPUCC pVCpu)
1384	{
1385	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1386	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1387	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1388
1389	/* Load the bare minimum state required for entering HM. */
1390	int rc = hmR0EnterCpu(pVCpu);
1391	if (RT_SUCCESS(rc))
1392	{
1393	if (g_HmR0.hwvirt.u.vmx.fSupported)
1394	{
1395	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
1396	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
1397	}
1398	else
1399	{
1400	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
1401	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
1402	}
1403
1404	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1405	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_5);
1406	bool const fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1407	#endif
1408
1409	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1410	rc = g_HmR0.pfnEnterSession(pVCpu);
1411	AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu), pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID, rc);
1412
1413	/* Exports the host-state as we may be resuming code after a longjmp and quite
1414	possibly now be scheduled on a different CPU. */
1415	rc = g_HmR0.pfnExportHostState(pVCpu);
1416	AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu), pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID, rc);
1417
1418	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1419	if (fStartedSet)
1420	PGMRZDynMapReleaseAutoSet(pVCpu);
1421	#endif
1422	}
1423	return rc;
1424	}
1425
1426
1427	/**
1428	* Deinitializes the bare minimum state used for HM context and if necessary
1429	* disable HM on the CPU.
1430	*
1431	* @returns VBox status code.
1432	* @param pVCpu The cross context virtual CPU structure.
1433	*
1434	* @remarks No-long-jump zone!!!
1435	*/
1436	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPUCC pVCpu)
1437	{
1438	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1439	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1440
1441	RTCPUID const idCpu = RTMpCpuId();
1442	PCHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1443
1444	if ( !g_HmR0.fGlobalInit
1445	&& pHostCpu->fConfigured)
1446	{
1447	int rc = hmR0DisableCpu(idCpu);
1448	AssertRCReturn(rc, rc);
1449	Assert(!pHostCpu->fConfigured);
1450	Assert(pHostCpu->idCpu == NIL_RTCPUID);
1451
1452	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1453	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1454	}
1455
1456	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1457	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1458
1459	return VINF_SUCCESS;
1460	}
1461
1462
1463	/**
1464	* Thread-context hook for HM.
1465	*
1466	* @param enmEvent The thread-context event.
1467	* @param pvUser Opaque pointer to the VMCPU.
1468	*/
1469	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1470	{
1471	PVMCPUCC pVCpu = (PVMCPUCC)pvUser;
1472	Assert(pVCpu);
1473	Assert(g_HmR0.pfnThreadCtxCallback);
1474
1475	g_HmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HmR0.fGlobalInit);
1476	}
1477
1478
1479	/**
1480	* Runs guest code in a hardware accelerated VM.
1481	*
1482	* @returns Strict VBox status code. (VBOXSTRICTRC isn't used because it's
1483	* called from setjmp assembly.)
1484	* @param pVM The cross context VM structure.
1485	* @param pVCpu The cross context virtual CPU structure.
1486	*
1487	* @remarks Can be called with preemption enabled if thread-context hooks are
1488	* used!!!
1489	*/
1490	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVMCC pVM, PVMCPUCC pVCpu)
1491	{
1492	RT_NOREF(pVM);
1493
1494	#ifdef VBOX_STRICT
1495	/* With thread-context hooks we would be running this code with preemption enabled. */
1496	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1497	{
1498	PCHMPHYSCPU pHostCpu = &g_HmR0.aCpuInfo[RTMpCpuId()];
1499	Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1500	Assert(pHostCpu->fConfigured);
1501	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1502	}
1503	#endif
1504
1505	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1506	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_4);
1507	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1508	PGMRZDynMapStartAutoSet(pVCpu);
1509	#endif
1510
1511	VBOXSTRICTRC rcStrict = g_HmR0.pfnRunGuestCode(pVCpu);
1512
1513	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1514	PGMRZDynMapReleaseAutoSet(pVCpu);
1515	#endif
1516	return VBOXSTRICTRC_VAL(rcStrict);
1517	}
1518
1519
1520	/**
1521	* Notification from CPUM that it has unloaded the guest FPU/SSE/AVX state from
1522	* the host CPU and that guest access to it must be intercepted.
1523	*
1524	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1525	*/
1526	VMMR0_INT_DECL(void) HMR0NotifyCpumUnloadedGuestFpuState(PVMCPUCC pVCpu)
1527	{
1528	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
1529	}
1530
1531
1532	/**
1533	* Notification from CPUM that it has modified the host CR0 (because of FPU).
1534	*
1535	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1536	*/
1537	VMMR0_INT_DECL(void) HMR0NotifyCpumModifiedHostCr0(PVMCPUCC pVCpu)
1538	{
1539	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_HOST_CONTEXT);
1540	}
1541
1542
1543	/**
1544	* Returns suspend status of the host.
1545	*
1546	* @returns Suspend pending or not.
1547	*/
1548	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1549	{
1550	return ASMAtomicReadBool(&g_HmR0.fSuspended);
1551	}
1552
1553
1554	/**
1555	* Invalidates a guest page from the host TLB.
1556	*
1557	* @param pVCpu The cross context virtual CPU structure.
1558	* @param GCVirt Page to invalidate.
1559	*/
1560	VMMR0_INT_DECL(int) HMR0InvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt)
1561	{
1562	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1563	if (pVM->hm.s.vmx.fSupported)
1564	return VMXR0InvalidatePage(pVCpu, GCVirt);
1565	return SVMR0InvalidatePage(pVCpu, GCVirt);
1566	}
1567
1568
1569	/**
1570	* Returns the cpu structure for the current cpu.
1571	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1572	*
1573	* @returns The cpu structure pointer.
1574	*/
1575	VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void)
1576	{
1577	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1578	RTCPUID const idCpu = RTMpCpuId();
1579	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1580	return &g_HmR0.aCpuInfo[idCpu];
1581	}
1582
1583
1584	/**
1585	* Interface for importing state on demand (used by IEM).
1586	*
1587	* @returns VBox status code.
1588	* @param pVCpu The cross context CPU structure.
1589	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1590	*/
1591	VMMR0_INT_DECL(int) HMR0ImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
1592	{
1593	if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported)
1594	return VMXR0ImportStateOnDemand(pVCpu, fWhat);
1595	return SVMR0ImportStateOnDemand(pVCpu, fWhat);
1596	}
1597
1598	#ifdef VBOX_STRICT
1599
1600	/**
1601	* Dumps a descriptor.
1602	*
1603	* @param pDesc Descriptor to dump.
1604	* @param Sel The selector.
1605	* @param pszSel The name of the selector.
1606	*/
1607	VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszSel)
1608	{
1609	/*
1610	* Make variable description string.
1611	*/
1612	static struct
1613	{
1614	unsigned cch;
1615	const char *psz;
1616	} const s_aTypes[32] =
1617	{
1618	# define STRENTRY(str) { sizeof(str) - 1, str }
1619
1620	/* system */
1621	# if HC_ARCH_BITS == 64
1622	STRENTRY("Reserved0 "), /* 0x00 */
1623	STRENTRY("Reserved1 "), /* 0x01 */
1624	STRENTRY("LDT "), /* 0x02 */
1625	STRENTRY("Reserved3 "), /* 0x03 */
1626	STRENTRY("Reserved4 "), /* 0x04 */
1627	STRENTRY("Reserved5 "), /* 0x05 */
1628	STRENTRY("Reserved6 "), /* 0x06 */
1629	STRENTRY("Reserved7 "), /* 0x07 */
1630	STRENTRY("Reserved8 "), /* 0x08 */
1631	STRENTRY("TSS64Avail "), /* 0x09 */
1632	STRENTRY("ReservedA "), /* 0x0a */
1633	STRENTRY("TSS64Busy "), /* 0x0b */
1634	STRENTRY("Call64 "), /* 0x0c */
1635	STRENTRY("ReservedD "), /* 0x0d */
1636	STRENTRY("Int64 "), /* 0x0e */
1637	STRENTRY("Trap64 "), /* 0x0f */
1638	# else
1639	STRENTRY("Reserved0 "), /* 0x00 */
1640	STRENTRY("TSS16Avail "), /* 0x01 */
1641	STRENTRY("LDT "), /* 0x02 */
1642	STRENTRY("TSS16Busy "), /* 0x03 */
1643	STRENTRY("Call16 "), /* 0x04 */
1644	STRENTRY("Task "), /* 0x05 */
1645	STRENTRY("Int16 "), /* 0x06 */
1646	STRENTRY("Trap16 "), /* 0x07 */
1647	STRENTRY("Reserved8 "), /* 0x08 */
1648	STRENTRY("TSS32Avail "), /* 0x09 */
1649	STRENTRY("ReservedA "), /* 0x0a */
1650	STRENTRY("TSS32Busy "), /* 0x0b */
1651	STRENTRY("Call32 "), /* 0x0c */
1652	STRENTRY("ReservedD "), /* 0x0d */
1653	STRENTRY("Int32 "), /* 0x0e */
1654	STRENTRY("Trap32 "), /* 0x0f */
1655	# endif
1656	/* non system */
1657	STRENTRY("DataRO "), /* 0x10 */
1658	STRENTRY("DataRO Accessed "), /* 0x11 */
1659	STRENTRY("DataRW "), /* 0x12 */
1660	STRENTRY("DataRW Accessed "), /* 0x13 */
1661	STRENTRY("DataDownRO "), /* 0x14 */
1662	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1663	STRENTRY("DataDownRW "), /* 0x16 */
1664	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1665	STRENTRY("CodeEO "), /* 0x18 */
1666	STRENTRY("CodeEO Accessed "), /* 0x19 */
1667	STRENTRY("CodeER "), /* 0x1a */
1668	STRENTRY("CodeER Accessed "), /* 0x1b */
1669	STRENTRY("CodeConfEO "), /* 0x1c */
1670	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1671	STRENTRY("CodeConfER "), /* 0x1e */
1672	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1673	# undef SYSENTRY
1674	};
1675	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1676	char szMsg[128];
1677	char *psz = &szMsg[0];
1678	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1679	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1680	psz += s_aTypes[i].cch;
1681
1682	if (pDesc->Gen.u1Present)
1683	ADD_STR(psz, "Present ");
1684	else
1685	ADD_STR(psz, "Not-Present ");
1686	# if HC_ARCH_BITS == 64
1687	if (pDesc->Gen.u1Long)
1688	ADD_STR(psz, "64-bit ");
1689	else
1690	ADD_STR(psz, "Comp ");
1691	# else
1692	if (pDesc->Gen.u1Granularity)
1693	ADD_STR(psz, "Page ");
1694	if (pDesc->Gen.u1DefBig)
1695	ADD_STR(psz, "32-bit ");
1696	else
1697	ADD_STR(psz, "16-bit ");
1698	# endif
1699	# undef ADD_STR
1700	*psz = '\0';
1701
1702	/*
1703	* Limit and Base and format the output.
1704	*/
1705	#ifdef LOG_ENABLED
1706	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1707
1708	# if HC_ARCH_BITS == 64
1709	uint64_t const u64Base = X86DESC64_BASE(pDesc);
1710	Log((" %s { %#04x - %#RX64 %#RX64 - base=%#RX64 limit=%#08x dpl=%d } %s\n", pszSel,
1711	Sel, pDesc->au64[0], pDesc->au64[1], u64Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1712	# else
1713	uint32_t const u32Base = X86DESC_BASE(pDesc);
1714	Log((" %s { %#04x - %#08x %#08x - base=%#08x limit=%#08x dpl=%d } %s\n", pszSel,
1715	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1716	# endif
1717	#else
1718	NOREF(Sel); NOREF(pszSel);
1719	#endif
1720	}
1721
1722
1723	/**
1724	* Formats a full register dump.
1725	*
1726	* @param pVCpu The cross context virtual CPU structure.
1727	* @param fFlags The dumping flags (HM_DUMP_REG_FLAGS_XXX).
1728	*/
1729	VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPUCC pVCpu, uint32_t fFlags)
1730	{
1731	/*
1732	* Format the flags.
1733	*/
1734	static struct
1735	{
1736	const char *pszSet;
1737	const char *pszClear;
1738	uint32_t fFlag;
1739	} const s_aFlags[] =
1740	{
1741	{ "vip", NULL, X86_EFL_VIP },
1742	{ "vif", NULL, X86_EFL_VIF },
1743	{ "ac", NULL, X86_EFL_AC },
1744	{ "vm", NULL, X86_EFL_VM },
1745	{ "rf", NULL, X86_EFL_RF },
1746	{ "nt", NULL, X86_EFL_NT },
1747	{ "ov", "nv", X86_EFL_OF },
1748	{ "dn", "up", X86_EFL_DF },
1749	{ "ei", "di", X86_EFL_IF },
1750	{ "tf", NULL, X86_EFL_TF },
1751	{ "nt", "pl", X86_EFL_SF },
1752	{ "nz", "zr", X86_EFL_ZF },
1753	{ "ac", "na", X86_EFL_AF },
1754	{ "po", "pe", X86_EFL_PF },
1755	{ "cy", "nc", X86_EFL_CF },
1756	};
1757	char szEFlags[80];
1758	char *psz = szEFlags;
1759	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1760	uint32_t uEFlags = pCtx->eflags.u32;
1761	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1762	{
1763	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1764	if (pszAdd)
1765	{
1766	strcpy(psz, pszAdd);
1767	psz += strlen(pszAdd);
1768	*psz++ = ' ';
1769	}
1770	}
1771	psz[-1] = '\0';
1772
1773	if (fFlags & HM_DUMP_REG_FLAGS_GPRS)
1774	{
1775	/*
1776	* Format the registers.
1777	*/
1778	if (CPUMIsGuestIn64BitCode(pVCpu))
1779	{
1780	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1781	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1782	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1783	"r14=%016RX64 r15=%016RX64\n"
1784	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1785	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1786	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1787	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1788	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1789	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1790	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1791	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1792	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1793	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1794	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1795	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1796	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1797	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1798	,
1799	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1800	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1801	pCtx->r14, pCtx->r15,
1802	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1803	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1804	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1805	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1806	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1807	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1808	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1809	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1810	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1811	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1812	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1813	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1814	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1815	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1816	}
1817	else
1818	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1819	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1820	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1821	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1822	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1823	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1824	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1825	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1826	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1827	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1828	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1829	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1830	,
1831	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1832	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1833	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
1834	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
1835	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
1836	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
1837	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
1838	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
1839	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1840	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1841	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1842	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1843	}
1844
1845	if (fFlags & HM_DUMP_REG_FLAGS_FPU)
1846	{
1847	PCX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1848	Log(("FPU:\n"
1849	"FCW=%04x FSW=%04x FTW=%02x\n"
1850	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1851	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1852	,
1853	pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
1854	pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
1855	pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
1856	pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
1857	NOREF(pFpuCtx);
1858	}
1859
1860	if (fFlags & HM_DUMP_REG_FLAGS_MSRS)
1861	{
1862	Log(("MSR:\n"
1863	"EFER =%016RX64\n"
1864	"PAT =%016RX64\n"
1865	"STAR =%016RX64\n"
1866	"CSTAR =%016RX64\n"
1867	"LSTAR =%016RX64\n"
1868	"SFMASK =%016RX64\n"
1869	"KERNELGSBASE =%016RX64\n",
1870	pCtx->msrEFER,
1871	pCtx->msrPAT,
1872	pCtx->msrSTAR,
1873	pCtx->msrCSTAR,
1874	pCtx->msrLSTAR,
1875	pCtx->msrSFMASK,
1876	pCtx->msrKERNELGSBASE));
1877	}
1878	}
1879
1880	#endif /* VBOX_STRICT */
1881

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 80274

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