HMR0.cpp@ 62338

Last change on this file since 62338 was 61317, checked in by vboxsync, 8 years ago
CPUM,HM: CPUM must tell VT-x that it modified the host CR0 because it caches the value in the VMCS and state corruption may ensue if it restores it because we'll take a #NM when saving the guest state, probably ending up with the FPU state of the EMT instead.
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1	/* $Id: HMR0.cpp 61317 2016-05-31 04:55:10Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/hm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/vmm/gim.h>
30	#include <VBox/err.h>
31	#include <VBox/log.h>
32	#include <iprt/assert.h>
33	#include <iprt/asm.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/cpuset.h>
36	#include <iprt/mem.h>
37	#include <iprt/memobj.h>
38	#include <iprt/once.h>
39	#include <iprt/param.h>
40	#include <iprt/power.h>
41	#include <iprt/string.h>
42	#include <iprt/thread.h>
43	#include <iprt/x86.h>
44	#include "HMVMXR0.h"
45	#include "HMSVMR0.h"
46
47
48	/*********************************************************************************************************************************
49	* Internal Functions *
50	*********************************************************************************************************************************/
51	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
56	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
57
58
59	/*********************************************************************************************************************************
60	* Structures and Typedefs *
61	*********************************************************************************************************************************/
62	/**
63	* This is used to manage the status code of a RTMpOnAll in HM.
64	*/
65	typedef struct HMR0FIRSTRC
66	{
67	/** The status code. */
68	int32_t volatile rc;
69	/** The ID of the CPU reporting the first failure. */
70	RTCPUID volatile idCpu;
71	} HMR0FIRSTRC;
72	/** Pointer to a first return code structure. */
73	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
74
75
76	/*********************************************************************************************************************************
77	* Global Variables *
78	*********************************************************************************************************************************/
79	/**
80	* Global data.
81	*/
82	static struct
83	{
84	/** Per CPU globals. */
85	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
86
87	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
88	* @{ */
89	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
90	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
91	DECLR0CALLBACKMEMBER(int, pfnSaveHostState, (PVM pVM, PVMCPU pVCpu));
92	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnRunGuestCode, (PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
93	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
94	bool fEnabledByHost, void *pvArg));
95	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
96	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
98	DECLR0CALLBACKMEMBER(int, pfnSetupVM ,(PVM pVM));
99	/** @} */
100
101	/** Maximum ASID allowed. */
102	uint32_t uMaxAsid;
103
104	/** VT-x data. */
105	struct
106	{
107	/** Set to by us to indicate VMX is supported by the CPU. */
108	bool fSupported;
109	/** Whether we're using SUPR0EnableVTx or not. */
110	bool fUsingSUPR0EnableVTx;
111	/** Whether we're using the preemption timer or not. */
112	bool fUsePreemptTimer;
113	/** The shift mask employed by the VMX-Preemption timer. */
114	uint8_t cPreemptTimerShift;
115
116	/** Host CR4 value (set by ring-0 VMX init) */
117	uint64_t u64HostCr4;
118
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t u64HostEfer;
121
122	/** Host SMM monitor control (used for logging/diagnostics) */
123	uint64_t u64HostSmmMonitorCtl;
124
125	/** VMX MSR values */
126	VMXMSRS Msrs;
127
128	/** Last instruction error. */
129	uint32_t ulLastInstrError;
130
131	/** Set if we've called SUPR0EnableVTx(true) and should disable it during
132	* module termination. */
133	bool fCalledSUPR0EnableVTx;
134	} vmx;
135
136	/** AMD-V information. */
137	struct
138	{
139	/* HWCR MSR (for diagnostics) */
140	uint64_t u64MsrHwcr;
141
142	/** SVM revision. */
143	uint32_t u32Rev;
144
145	/** SVM feature bits from cpuid 0x8000000a */
146	uint32_t u32Features;
147
148	/** Set by us to indicate SVM is supported by the CPU. */
149	bool fSupported;
150	} svm;
151	/** Saved error from detection */
152	int32_t lLastError;
153
154	/** CPUID 0x80000001 ecx:edx features */
155	struct
156	{
157	uint32_t u32AMDFeatureECX;
158	uint32_t u32AMDFeatureEDX;
159	} cpuid;
160
161	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
162	* enabled and disabled each time it's used to execute guest code. */
163	bool fGlobalInit;
164	/** Indicates whether the host is suspending or not. We'll refuse a few
165	* actions when the host is being suspended to speed up the suspending and
166	* avoid trouble. */
167	volatile bool fSuspended;
168
169	/** Whether we've already initialized all CPUs.
170	* @remarks We could check the EnableAllCpusOnce state, but this is
171	* simpler and hopefully easier to understand. */
172	bool fEnabled;
173	/** Serialize initialization in HMR0EnableAllCpus. */
174	RTONCE EnableAllCpusOnce;
175	} g_HmR0;
176
177
178
179	/**
180	* Initializes a first return code structure.
181	*
182	* @param pFirstRc The structure to init.
183	*/
184	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
185	{
186	pFirstRc->rc = VINF_SUCCESS;
187	pFirstRc->idCpu = NIL_RTCPUID;
188	}
189
190
191	/**
192	* Try set the status code (success ignored).
193	*
194	* @param pFirstRc The first return code structure.
195	* @param rc The status code.
196	*/
197	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
198	{
199	if ( RT_FAILURE(rc)
200	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
201	pFirstRc->idCpu = RTMpCpuId();
202	}
203
204
205	/**
206	* Get the status code of a first return code structure.
207	*
208	* @returns The status code; VINF_SUCCESS or error status, no informational or
209	* warning errors.
210	* @param pFirstRc The first return code structure.
211	*/
212	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
213	{
214	return pFirstRc->rc;
215	}
216
217
218	#ifdef VBOX_STRICT
219	/**
220	* Get the CPU ID on which the failure status code was reported.
221	*
222	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
223	* @param pFirstRc The first return code structure.
224	*/
225	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
226	{
227	return pFirstRc->idCpu;
228	}
229	#endif /* VBOX_STRICT */
230
231
232	/** @name Dummy callback handlers.
233	* @{ */
234
235	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
236	{
237	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
238	return VINF_SUCCESS;
239	}
240
241	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
242	{
243	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
244	}
245
246	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
247	bool fEnabledBySystem, void *pvArg)
248	{
249	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem); NOREF(pvArg);
250	return VINF_SUCCESS;
251	}
252
253	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
254	{
255	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
256	return VINF_SUCCESS;
257	}
258
259	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
260	{
261	NOREF(pVM);
262	return VINF_SUCCESS;
263	}
264
265	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
266	{
267	NOREF(pVM);
268	return VINF_SUCCESS;
269	}
270
271	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
272	{
273	NOREF(pVM);
274	return VINF_SUCCESS;
275	}
276
277	static DECLCALLBACK(VBOXSTRICTRC) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
278	{
279	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
280	return VINF_SUCCESS;
281	}
282
283	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
284	{
285	NOREF(pVM); NOREF(pVCpu);
286	return VINF_SUCCESS;
287	}
288
289	/** @} */
290
291
292	/**
293	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
294	* Down at the Rate Specified" erratum.
295	*
296	* Errata names and related steppings:
297	* - BA86 - D0.
298	* - AAX65 - C2.
299	* - AAU65 - C2, K0.
300	* - AAO95 - B1.
301	* - AAT59 - C2.
302	* - AAK139 - D0.
303	* - AAM126 - C0, C1, D0.
304	* - AAN92 - B1.
305	* - AAJ124 - C0, D0.
306	*
307	* - AAP86 - B1.
308	*
309	* Steppings: B1, C0, C1, C2, D0, K0.
310	*
311	* @returns true if subject to it, false if not.
312	*/
313	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
314	{
315	uint32_t u = ASMCpuId_EAX(1);
316	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
317	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
318	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
319	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
320	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
321	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
322	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
323	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
324	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
325	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
326	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
327	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
328	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
329	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
330	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
331	)
332	return true;
333	return false;
334	}
335
336
337	/**
338	* Intel specific initialization code.
339	*
340	* @returns VBox status code (will only fail if out of memory).
341	*/
342	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
343	{
344	/*
345	* Check that all the required VT-x features are present.
346	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
347	*/
348	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
349	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
350	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
351	)
352	{
353	/* Read this MSR now as it may be useful for error reporting when initializing VT-x fails. */
354	g_HmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
355
356	/*
357	* First try use native kernel API for controlling VT-x.
358	* (This is only supported by some Mac OS X kernels atm.)
359	*/
360	int rc = g_HmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
361	g_HmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
362	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
363	{
364	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
365	if (RT_SUCCESS(rc))
366	{
367	g_HmR0.vmx.fSupported = true;
368	rc = SUPR0EnableVTx(false /* fEnable */);
369	AssertLogRelRC(rc);
370	}
371	}
372	else
373	{
374	HMR0FIRSTRC FirstRc;
375	hmR0FirstRcInit(&FirstRc);
376	g_HmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
377	if (RT_SUCCESS(g_HmR0.lLastError))
378	g_HmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
379	}
380	if (RT_SUCCESS(g_HmR0.lLastError))
381	{
382	/* Reread in case it was changed by SUPR0GetVmxUsability(). */
383	g_HmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
384
385	/*
386	* Read all relevant registers and MSRs.
387	*/
388	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
389	g_HmR0.vmx.u64HostSmmMonitorCtl = ASMRdMsr(MSR_IA32_SMM_MONITOR_CTL);
390	g_HmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
391	g_HmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
392	g_HmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
393	g_HmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
394	g_HmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
395	g_HmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
396	g_HmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
397	g_HmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
398	g_HmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
399	g_HmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
400	g_HmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
401	g_HmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
402	/* VPID 16 bits ASID. */
403	g_HmR0.uMaxAsid = 0x10000; /* exclusive */
404
405	if (g_HmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
406	{
407	g_HmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
408	if (g_HmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
409	g_HmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
410
411	if (g_HmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
412	g_HmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
413	}
414
415	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
416	{
417	/*
418	* Enter root mode
419	*/
420	RTR0MEMOBJ hScatchMemObj;
421	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
422	if (RT_FAILURE(rc))
423	{
424	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
425	return rc;
426	}
427
428	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
429	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
430	ASMMemZeroPage(pvScatchPage);
431
432	/* Set revision dword at the beginning of the structure. */
433	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HmR0.vmx.Msrs.u64BasicInfo);
434
435	/* Make sure we don't get rescheduled to another cpu during this probe. */
436	RTCCUINTREG fFlags = ASMIntDisableFlags();
437
438	/*
439	* Check CR4.VMXE
440	*/
441	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
442	if (!(g_HmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
443	{
444	/* In theory this bit could be cleared behind our back. Which would cause
445	#UD faults when we try to execute the VMX instructions... */
446	ASMSetCR4(g_HmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
447	}
448
449	/*
450	* The only way of checking if we're in VMX root mode or not is to try and enter it.
451	* There is no instruction or control bit that tells us if we're in VMX root mode.
452	* Therefore, try and enter VMX root mode here.
453	*/
454	rc = VMXEnable(HCPhysScratchPage);
455	if (RT_SUCCESS(rc))
456	{
457	g_HmR0.vmx.fSupported = true;
458	VMXDisable();
459	}
460	else
461	{
462	/*
463	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
464	* it will crash the host when we enter raw mode, because:
465	*
466	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
467	* this bit), and
468	* (b) turning off paging causes a #GP (unavoidable when switching
469	* from long to 32 bits mode or 32 bits to PAE).
470	*
471	* They should fix their code, but until they do we simply refuse to run.
472	*/
473	g_HmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
474	Assert(g_HmR0.vmx.fSupported == false);
475	}
476
477	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
478	if it wasn't so before (some software could incorrectly
479	think it's in VMX mode). */
480	ASMSetCR4(g_HmR0.vmx.u64HostCr4);
481	ASMSetFlags(fFlags);
482
483	RTR0MemObjFree(hScatchMemObj, false);
484	}
485
486	if (g_HmR0.vmx.fSupported)
487	{
488	rc = VMXR0GlobalInit();
489	if (RT_FAILURE(rc))
490	g_HmR0.lLastError = rc;
491
492	/*
493	* Install the VT-x methods.
494	*/
495	g_HmR0.pfnEnterSession = VMXR0Enter;
496	g_HmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
497	g_HmR0.pfnSaveHostState = VMXR0SaveHostState;
498	g_HmR0.pfnRunGuestCode = VMXR0RunGuestCode;
499	g_HmR0.pfnEnableCpu = VMXR0EnableCpu;
500	g_HmR0.pfnDisableCpu = VMXR0DisableCpu;
501	g_HmR0.pfnInitVM = VMXR0InitVM;
502	g_HmR0.pfnTermVM = VMXR0TermVM;
503	g_HmR0.pfnSetupVM = VMXR0SetupVM;
504
505	/*
506	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
507	* Timer Does Not Count Down at the Rate Specified" erratum.
508	*/
509	if (g_HmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
510	{
511	g_HmR0.vmx.fUsePreemptTimer = true;
512	g_HmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HmR0.vmx.Msrs.u64Misc);
513	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
514	g_HmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
515	}
516	}
517	}
518	#ifdef LOG_ENABLED
519	else
520	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HmR0.lLastError);
521	#endif
522	}
523	else
524	g_HmR0.lLastError = VERR_VMX_NO_VMX;
525	return VINF_SUCCESS;
526	}
527
528
529	/**
530	* AMD-specific initialization code.
531	*
532	* @returns VBox status code.
533	*/
534	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
535	{
536	/*
537	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
538	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
539	*/
540	int rc;
541	if ( (g_HmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
542	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
543	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
544	&& ASMIsValidExtRange(uMaxExtLeaf)
545	&& uMaxExtLeaf >= 0x8000000a
546	)
547	{
548	/* Call the global AMD-V initialization routine. */
549	rc = SVMR0GlobalInit();
550	if (RT_FAILURE(rc))
551	{
552	g_HmR0.lLastError = rc;
553	return rc;
554	}
555
556	/*
557	* Install the AMD-V methods.
558	*/
559	g_HmR0.pfnEnterSession = SVMR0Enter;
560	g_HmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
561	g_HmR0.pfnSaveHostState = SVMR0SaveHostState;
562	g_HmR0.pfnRunGuestCode = SVMR0RunGuestCode;
563	g_HmR0.pfnEnableCpu = SVMR0EnableCpu;
564	g_HmR0.pfnDisableCpu = SVMR0DisableCpu;
565	g_HmR0.pfnInitVM = SVMR0InitVM;
566	g_HmR0.pfnTermVM = SVMR0TermVM;
567	g_HmR0.pfnSetupVM = SVMR0SetupVM;
568
569	/* Query AMD features. */
570	uint32_t u32Dummy;
571	ASMCpuId(0x8000000a, &g_HmR0.svm.u32Rev, &g_HmR0.uMaxAsid, &u32Dummy, &g_HmR0.svm.u32Features);
572
573	/*
574	* We need to check if AMD-V has been properly initialized on all CPUs.
575	* Some BIOSes might do a poor job.
576	*/
577	HMR0FIRSTRC FirstRc;
578	hmR0FirstRcInit(&FirstRc);
579	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
580	AssertRC(rc);
581	if (RT_SUCCESS(rc))
582	rc = hmR0FirstRcGetStatus(&FirstRc);
583	#ifndef DEBUG_bird
584	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
585	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
586	#endif
587	if (RT_SUCCESS(rc))
588	{
589	/* Read the HWCR MSR for diagnostics. */
590	g_HmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
591	g_HmR0.svm.fSupported = true;
592	}
593	else
594	{
595	g_HmR0.lLastError = rc;
596	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
597	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
598	}
599	}
600	else
601	{
602	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
603	g_HmR0.lLastError = VERR_SVM_NO_SVM;
604	}
605	return rc;
606	}
607
608
609	/**
610	* Does global Ring-0 HM initialization (at module init).
611	*
612	* @returns VBox status code.
613	*/
614	VMMR0_INT_DECL(int) HMR0Init(void)
615	{
616	/*
617	* Initialize the globals.
618	*/
619	g_HmR0.fEnabled = false;
620	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
621	g_HmR0.EnableAllCpusOnce = s_OnceInit;
622	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
623	{
624	g_HmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
625	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
626	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
627	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
628	}
629
630	/* Fill in all callbacks with placeholders. */
631	g_HmR0.pfnEnterSession = hmR0DummyEnter;
632	g_HmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
633	g_HmR0.pfnSaveHostState = hmR0DummySaveHostState;
634	g_HmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
635	g_HmR0.pfnEnableCpu = hmR0DummyEnableCpu;
636	g_HmR0.pfnDisableCpu = hmR0DummyDisableCpu;
637	g_HmR0.pfnInitVM = hmR0DummyInitVM;
638	g_HmR0.pfnTermVM = hmR0DummyTermVM;
639	g_HmR0.pfnSetupVM = hmR0DummySetupVM;
640
641	/* Default is global VT-x/AMD-V init. */
642	g_HmR0.fGlobalInit = true;
643
644	/*
645	* Make sure aCpuInfo is big enough for all the CPUs on this system.
646	*/
647	if (RTMpGetArraySize() > RT_ELEMENTS(g_HmR0.aCpuInfo))
648	{
649	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HmR0.aCpuInfo)));
650	return VERR_TOO_MANY_CPUS;
651	}
652
653	/*
654	* Check for VT-x and AMD-V capabilities.
655	*/
656	int rc;
657	if (ASMHasCpuId())
658	{
659	/* Standard features. */
660	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
661	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
662	if (ASMIsValidStdRange(uMaxLeaf))
663	{
664	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
665	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
666
667	/* Query AMD features. */
668	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
669	if (ASMIsValidExtRange(uMaxExtLeaf))
670	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
671	&g_HmR0.cpuid.u32AMDFeatureECX,
672	&g_HmR0.cpuid.u32AMDFeatureEDX);
673	else
674	g_HmR0.cpuid.u32AMDFeatureECX = g_HmR0.cpuid.u32AMDFeatureEDX = 0;
675
676	/* Go to CPU specific initialization code. */
677	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
678	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
679	{
680	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
681	if (RT_FAILURE(rc))
682	return rc;
683	}
684	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
685	{
686	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
687	if (RT_FAILURE(rc))
688	return rc;
689	}
690	else
691	g_HmR0.lLastError = VERR_HM_UNKNOWN_CPU;
692	}
693	else
694	g_HmR0.lLastError = VERR_HM_UNKNOWN_CPU;
695	}
696	else
697	g_HmR0.lLastError = VERR_HM_NO_CPUID;
698
699	/*
700	* Register notification callbacks that we can use to disable/enable CPUs
701	* when brought offline/online or suspending/resuming.
702	*/
703	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
704	{
705	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
706	AssertRC(rc);
707
708	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
709	AssertRC(rc);
710	}
711
712	/* We return success here because module init shall not fail if HM
713	fails to initialize. */
714	return VINF_SUCCESS;
715	}
716
717
718	/**
719	* Does global Ring-0 HM termination (at module termination).
720	*
721	* @returns VBox status code.
722	*/
723	VMMR0_INT_DECL(int) HMR0Term(void)
724	{
725	int rc;
726	if ( g_HmR0.vmx.fSupported
727	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
728	{
729	/*
730	* Simple if the host OS manages VT-x.
731	*/
732	Assert(g_HmR0.fGlobalInit);
733
734	if (g_HmR0.vmx.fCalledSUPR0EnableVTx)
735	{
736	rc = SUPR0EnableVTx(false /* fEnable */);
737	g_HmR0.vmx.fCalledSUPR0EnableVTx = false;
738	}
739	else
740	rc = VINF_SUCCESS;
741
742	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HmR0.aCpuInfo); iCpu++)
743	{
744	g_HmR0.aCpuInfo[iCpu].fConfigured = false;
745	Assert(g_HmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
746	}
747	}
748	else
749	{
750	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
751
752	/* Doesn't really matter if this fails. */
753	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
754	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
755
756	/*
757	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
758	*/
759	if (g_HmR0.fGlobalInit)
760	{
761	HMR0FIRSTRC FirstRc;
762	hmR0FirstRcInit(&FirstRc);
763	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
764	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
765	if (RT_SUCCESS(rc))
766	rc = hmR0FirstRcGetStatus(&FirstRc);
767	}
768
769	/*
770	* Free the per-cpu pages used for VT-x and AMD-V.
771	*/
772	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
773	{
774	if (g_HmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
775	{
776	RTR0MemObjFree(g_HmR0.aCpuInfo[i].hMemObj, false);
777	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
778	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
779	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
780	}
781	}
782	}
783
784	/** @todo This needs cleaning up. There's no matching
785	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
786	* should move into their respective modules. */
787	/* Finally, call global VT-x/AMD-V termination. */
788	if (g_HmR0.vmx.fSupported)
789	VMXR0GlobalTerm();
790	else if (g_HmR0.svm.fSupported)
791	SVMR0GlobalTerm();
792
793	return rc;
794	}
795
796
797	/**
798	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
799	* on a CPU.
800	*
801	* @param idCpu The identifier for the CPU the function is called on.
802	* @param pvUser1 Pointer to the first RC structure.
803	* @param pvUser2 Ignored.
804	*/
805	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
806	{
807	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
808	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
809	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
810	NOREF(idCpu); NOREF(pvUser2);
811
812	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
813	hmR0FirstRcSetStatus(pFirstRc, rc);
814	}
815
816
817	/**
818	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
819	* on a CPU.
820	*
821	* @param idCpu The identifier for the CPU the function is called on.
822	* @param pvUser1 Pointer to the first RC structure.
823	* @param pvUser2 Ignored.
824	*/
825	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
826	{
827	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
828	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
829	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
830	NOREF(idCpu); NOREF(pvUser2);
831
832	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
833	hmR0FirstRcSetStatus(pFirstRc, rc);
834	}
835
836
837	/**
838	* Enable VT-x or AMD-V on the current CPU
839	*
840	* @returns VBox status code.
841	* @param pVM The cross context VM structure. Can be NULL.
842	* @param idCpu The identifier for the CPU the function is called on.
843	*
844	* @remarks Maybe called with interrupts disabled!
845	*/
846	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
847	{
848	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
849
850	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
851	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
852	Assert(!pCpu->fConfigured);
853	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
854
855	pCpu->idCpu = idCpu;
856	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
857
858	int rc;
859	if (g_HmR0.vmx.fSupported && g_HmR0.vmx.fUsingSUPR0EnableVTx)
860	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmR0.vmx.Msrs);
861	else
862	{
863	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
864	if (g_HmR0.vmx.fSupported)
865	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, pCpu->pvMemObj, pCpu->HCPhysMemObj, false, &g_HmR0.vmx.Msrs);
866	else
867	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, pCpu->pvMemObj, pCpu->HCPhysMemObj, false, NULL /* pvArg */);
868	}
869	if (RT_SUCCESS(rc))
870	pCpu->fConfigured = true;
871
872	return rc;
873	}
874
875
876	/**
877	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
878	*
879	* @param idCpu The identifier for the CPU the function is called on.
880	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
881	* @param pvUser2 The 2nd user argument.
882	*/
883	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
884	{
885	PVM pVM = (PVM)pvUser1; /* can be NULL! */
886	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
887	AssertReturnVoid(g_HmR0.fGlobalInit);
888	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
889	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
890	}
891
892
893	/**
894	* RTOnce callback employed by HMR0EnableAllCpus.
895	*
896	* @returns VBox status code.
897	* @param pvUser Pointer to the VM.
898	*/
899	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
900	{
901	PVM pVM = (PVM)pvUser;
902
903	/*
904	* Indicate that we've initialized.
905	*
906	* Note! There is a potential race between this function and the suspend
907	* notification. Kind of unlikely though, so ignored for now.
908	*/
909	AssertReturn(!g_HmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
910	ASMAtomicWriteBool(&g_HmR0.fEnabled, true);
911
912	/*
913	* The global init variable is set by the first VM.
914	*/
915	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
916
917	#ifdef VBOX_STRICT
918	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
919	{
920	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
921	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj == NIL_RTHCPHYS);
922	Assert(g_HmR0.aCpuInfo[i].pvMemObj == NULL);
923	Assert(!g_HmR0.aCpuInfo[i].fConfigured);
924	Assert(!g_HmR0.aCpuInfo[i].cTlbFlushes);
925	Assert(!g_HmR0.aCpuInfo[i].uCurrentAsid);
926	}
927	#endif
928
929	int rc;
930	if ( g_HmR0.vmx.fSupported
931	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
932	{
933	/*
934	* Global VT-x initialization API (only darwin for now).
935	*/
936	rc = SUPR0EnableVTx(true /* fEnable */);
937	if (RT_SUCCESS(rc))
938	{
939	g_HmR0.vmx.fCalledSUPR0EnableVTx = true;
940	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
941	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
942	}
943	else
944	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
945	}
946	else
947	{
948	/*
949	* We're doing the job ourselves.
950	*/
951	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
952	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
953	{
954	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
955
956	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
957	{
958	/** @todo NUMA */
959	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
960	AssertLogRelRCReturn(rc, rc);
961
962	g_HmR0.aCpuInfo[i].HCPhysMemObj = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].hMemObj, 0);
963	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj != NIL_RTHCPHYS);
964	Assert(!(g_HmR0.aCpuInfo[i].HCPhysMemObj & PAGE_OFFSET_MASK));
965
966	g_HmR0.aCpuInfo[i].pvMemObj = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].hMemObj);
967	AssertPtr(g_HmR0.aCpuInfo[i].pvMemObj);
968	ASMMemZeroPage(g_HmR0.aCpuInfo[i].pvMemObj);
969	}
970	}
971
972	rc = VINF_SUCCESS;
973	}
974
975	if ( RT_SUCCESS(rc)
976	&& g_HmR0.fGlobalInit)
977	{
978	/* First time, so initialize each cpu/core. */
979	HMR0FIRSTRC FirstRc;
980	hmR0FirstRcInit(&FirstRc);
981	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
982	if (RT_SUCCESS(rc))
983	rc = hmR0FirstRcGetStatus(&FirstRc);
984	}
985
986	return rc;
987	}
988
989
990	/**
991	* Sets up HM on all cpus.
992	*
993	* @returns VBox status code.
994	* @param pVM The cross context VM structure.
995	*/
996	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
997	{
998	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
999	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1000	return VERR_HM_SUSPEND_PENDING;
1001
1002	return RTOnce(&g_HmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1003	}
1004
1005
1006	/**
1007	* Disable VT-x or AMD-V on the current CPU.
1008	*
1009	* @returns VBox status code.
1010	* @param idCpu The identifier for the CPU this function is called on.
1011	*
1012	* @remarks Must be called with preemption disabled.
1013	*/
1014	static int hmR0DisableCpu(RTCPUID idCpu)
1015	{
1016	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1017
1018	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1019	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1020	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
1021	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1022	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1023	AssertRelease(idCpu == RTMpCpuId());
1024
1025	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1026	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1027	AssertPtr(pCpu->pvMemObj);
1028	Assert(pCpu->HCPhysMemObj != NIL_RTHCPHYS);
1029
1030	int rc;
1031	if (pCpu->fConfigured)
1032	{
1033	rc = g_HmR0.pfnDisableCpu(pCpu, pCpu->pvMemObj, pCpu->HCPhysMemObj);
1034	AssertRCReturn(rc, rc);
1035
1036	pCpu->fConfigured = false;
1037	pCpu->idCpu = NIL_RTCPUID;
1038	}
1039	else
1040	rc = VINF_SUCCESS; /* nothing to do */
1041	return rc;
1042	}
1043
1044
1045	/**
1046	* Worker function passed to RTMpOnAll() that is to be called on the target
1047	* CPUs.
1048	*
1049	* @param idCpu The identifier for the CPU the function is called on.
1050	* @param pvUser1 The 1st user argument.
1051	* @param pvUser2 Opaque pointer to the FirstRc.
1052	*/
1053	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1054	{
1055	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1056	AssertReturnVoid(g_HmR0.fGlobalInit);
1057	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1058	}
1059
1060
1061	/**
1062	* Worker function passed to RTMpOnSpecific() that is to be called on the target
1063	* CPU.
1064	*
1065	* @param idCpu The identifier for the CPU the function is called on.
1066	* @param pvUser1 Null, not used.
1067	* @param pvUser2 Null, not used.
1068	*/
1069	static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1070	{
1071	NOREF(pvUser1);
1072	NOREF(pvUser2);
1073	hmR0DisableCpu(idCpu);
1074	}
1075
1076
1077	/**
1078	* Callback function invoked when a cpu goes online or offline.
1079	*
1080	* @param enmEvent The Mp event.
1081	* @param idCpu The identifier for the CPU the function is called on.
1082	* @param pvData Opaque data (PVM pointer).
1083	*/
1084	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1085	{
1086	NOREF(pvData);
1087	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1088
1089	/*
1090	* We only care about uninitializing a CPU that is going offline. When a
1091	* CPU comes online, the initialization is done lazily in HMR0Enter().
1092	*/
1093	switch (enmEvent)
1094	{
1095	case RTMPEVENT_OFFLINE:
1096	{
1097	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1098	RTThreadPreemptDisable(&PreemptState);
1099	if (idCpu == RTMpCpuId())
1100	{
1101	int rc = hmR0DisableCpu(idCpu);
1102	AssertRC(rc);
1103	RTThreadPreemptRestore(&PreemptState);
1104	}
1105	else
1106	{
1107	RTThreadPreemptRestore(&PreemptState);
1108	RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 /, NULL / pvUser2 */);
1109	}
1110	break;
1111	}
1112
1113	default:
1114	break;
1115	}
1116	}
1117
1118
1119	/**
1120	* Called whenever a system power state change occurs.
1121	*
1122	* @param enmEvent The Power event.
1123	* @param pvUser User argument.
1124	*/
1125	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1126	{
1127	NOREF(pvUser);
1128	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1129
1130	#ifdef LOG_ENABLED
1131	if (enmEvent == RTPOWEREVENT_SUSPEND)
1132	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1133	else
1134	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1135	#endif
1136
1137	if (enmEvent == RTPOWEREVENT_SUSPEND)
1138	ASMAtomicWriteBool(&g_HmR0.fSuspended, true);
1139
1140	if (g_HmR0.fEnabled)
1141	{
1142	int rc;
1143	HMR0FIRSTRC FirstRc;
1144	hmR0FirstRcInit(&FirstRc);
1145
1146	if (enmEvent == RTPOWEREVENT_SUSPEND)
1147	{
1148	if (g_HmR0.fGlobalInit)
1149	{
1150	/* Turn off VT-x or AMD-V on all CPUs. */
1151	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1152	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1153	}
1154	/* else nothing to do here for the local init case */
1155	}
1156	else
1157	{
1158	/* Reinit the CPUs from scratch as the suspend state might have
1159	messed with the MSRs. (lousy BIOSes as usual) */
1160	if (g_HmR0.vmx.fSupported)
1161	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1162	else
1163	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1164	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1165	if (RT_SUCCESS(rc))
1166	rc = hmR0FirstRcGetStatus(&FirstRc);
1167	#ifdef LOG_ENABLED
1168	if (RT_FAILURE(rc))
1169	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1170	#endif
1171	if (g_HmR0.fGlobalInit)
1172	{
1173	/* Turn VT-x or AMD-V back on on all CPUs. */
1174	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1175	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1176	}
1177	/* else nothing to do here for the local init case */
1178	}
1179	}
1180
1181	if (enmEvent == RTPOWEREVENT_RESUME)
1182	ASMAtomicWriteBool(&g_HmR0.fSuspended, false);
1183	}
1184
1185
1186	/**
1187	* Does ring-0 per-VM HM initialization.
1188	*
1189	* This will copy HM global into the VM structure and call the CPU specific
1190	* init routine which will allocate resources for each virtual CPU and such.
1191	*
1192	* @returns VBox status code.
1193	* @param pVM The cross context VM structure.
1194	*
1195	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1196	* vmR3InitRing3().
1197	*/
1198	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1199	{
1200	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1201
1202	#ifdef LOG_ENABLED
1203	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1204	#endif
1205
1206	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1207	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1208	return VERR_HM_SUSPEND_PENDING;
1209
1210	/*
1211	* Copy globals to the VM structure.
1212	*/
1213	pVM->hm.s.vmx.fSupported = g_HmR0.vmx.fSupported;
1214	pVM->hm.s.svm.fSupported = g_HmR0.svm.fSupported;
1215
1216	pVM->hm.s.vmx.fUsePreemptTimer &= g_HmR0.vmx.fUsePreemptTimer; /* Can be overridden by CFGM. See HMR3Init(). */
1217	pVM->hm.s.vmx.cPreemptTimerShift = g_HmR0.vmx.cPreemptTimerShift;
1218	pVM->hm.s.vmx.u64HostCr4 = g_HmR0.vmx.u64HostCr4;
1219	pVM->hm.s.vmx.u64HostEfer = g_HmR0.vmx.u64HostEfer;
1220	pVM->hm.s.vmx.u64HostSmmMonitorCtl = g_HmR0.vmx.u64HostSmmMonitorCtl;
1221	pVM->hm.s.vmx.Msrs = g_HmR0.vmx.Msrs;
1222	pVM->hm.s.svm.u64MsrHwcr = g_HmR0.svm.u64MsrHwcr;
1223	pVM->hm.s.svm.u32Rev = g_HmR0.svm.u32Rev;
1224	pVM->hm.s.svm.u32Features = g_HmR0.svm.u32Features;
1225	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HmR0.cpuid.u32AMDFeatureECX;
1226	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HmR0.cpuid.u32AMDFeatureEDX;
1227	pVM->hm.s.lLastError = g_HmR0.lLastError;
1228	pVM->hm.s.uMaxAsid = g_HmR0.uMaxAsid;
1229
1230	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1231	{
1232	pVM->hm.s.cMaxResumeLoops = 1024;
1233	if (RTThreadPreemptIsPendingTrusty())
1234	pVM->hm.s.cMaxResumeLoops = 8192;
1235	}
1236
1237	/*
1238	* Initialize some per-VCPU fields.
1239	*/
1240	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1241	{
1242	PVMCPU pVCpu = &pVM->aCpus[i];
1243	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1244	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1245	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
1246
1247	/* We'll aways increment this the first time (host uses ASID 0). */
1248	AssertReturn(!pVCpu->hm.s.uCurrentAsid, VERR_HM_IPE_3);
1249	}
1250
1251	pVM->hm.s.fHostKernelFeatures = SUPR0GetKernelFeatures();
1252
1253	/*
1254	* Call the hardware specific initialization method.
1255	*/
1256	return g_HmR0.pfnInitVM(pVM);
1257	}
1258
1259
1260	/**
1261	* Does ring-0 per VM HM termination.
1262	*
1263	* @returns VBox status code.
1264	* @param pVM The cross context VM structure.
1265	*/
1266	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1267	{
1268	Log(("HMR0TermVM: %p\n", pVM));
1269	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1270
1271	/*
1272	* Call the hardware specific method.
1273	*
1274	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1275	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1276	*/
1277	return g_HmR0.pfnTermVM(pVM);
1278	}
1279
1280
1281	/**
1282	* Sets up a VT-x or AMD-V session.
1283	*
1284	* This is mostly about setting up the hardware VM state.
1285	*
1286	* @returns VBox status code.
1287	* @param pVM The cross context VM structure.
1288	*/
1289	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1290	{
1291	Log(("HMR0SetupVM: %p\n", pVM));
1292	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1293
1294	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1295	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1296
1297	/* On first entry we'll sync everything. */
1298	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1299	HMCPU_CF_RESET_TO(&pVM->aCpus[i], HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1300
1301	/*
1302	* Call the hardware specific setup VM method. This requires the CPU to be
1303	* enabled for AMD-V/VT-x and preemption to be prevented.
1304	*/
1305	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1306	RTThreadPreemptDisable(&PreemptState);
1307	RTCPUID idCpu = RTMpCpuId();
1308
1309	/* Enable VT-x or AMD-V if local init is required. */
1310	int rc;
1311	if (!g_HmR0.fGlobalInit)
1312	{
1313	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1314	rc = hmR0EnableCpu(pVM, idCpu);
1315	if (RT_FAILURE(rc))
1316	{
1317	RTThreadPreemptRestore(&PreemptState);
1318	return rc;
1319	}
1320	}
1321
1322	/* Setup VT-x or AMD-V. */
1323	rc = g_HmR0.pfnSetupVM(pVM);
1324
1325	/* Disable VT-x or AMD-V if local init was done before. */
1326	if (!g_HmR0.fGlobalInit)
1327	{
1328	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1329	int rc2 = hmR0DisableCpu(idCpu);
1330	AssertRC(rc2);
1331	}
1332
1333	RTThreadPreemptRestore(&PreemptState);
1334	return rc;
1335	}
1336
1337
1338	/**
1339	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1340	* required for entering HM context.
1341	*
1342	* @returns VBox status code.
1343	* @param pVCpu The cross context virtual CPU structure.
1344	*
1345	* @remarks No-long-jump zone!!!
1346	*/
1347	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1348	{
1349	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1350
1351	int rc = VINF_SUCCESS;
1352	RTCPUID idCpu = RTMpCpuId();
1353	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1354	AssertPtr(pCpu);
1355
1356	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1357	if (!pCpu->fConfigured)
1358	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1359
1360	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1361	HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE);
1362
1363	Assert(pCpu->idCpu == idCpu && pCpu->idCpu != NIL_RTCPUID);
1364	pVCpu->hm.s.idEnteredCpu = idCpu;
1365	return rc;
1366	}
1367
1368
1369	/**
1370	* Enters the VT-x or AMD-V session.
1371	*
1372	* @returns VBox status code.
1373	* @param pVM The cross context VM structure.
1374	* @param pVCpu The cross context virtual CPU structure.
1375	*
1376	* @remarks This is called with preemption disabled.
1377	*/
1378	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1379	{
1380	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1381	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1382	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1383
1384	/* Load the bare minimum state required for entering HM. */
1385	int rc = HMR0EnterCpu(pVCpu);
1386	AssertRCReturn(rc, rc);
1387
1388	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1389	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_5);
1390	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1391	#endif
1392
1393	RTCPUID idCpu = RTMpCpuId();
1394	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1395	Assert(pCpu);
1396	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1397
1398	rc = g_HmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1399	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1400
1401	/* Load the host-state as we may be resuming code after a longjmp and quite
1402	possibly now be scheduled on a different CPU. */
1403	rc = g_HmR0.pfnSaveHostState(pVM, pVCpu);
1404	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1405
1406	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1407	if (fStartedSet)
1408	PGMRZDynMapReleaseAutoSet(pVCpu);
1409	#endif
1410
1411	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1412	if (RT_FAILURE(rc))
1413	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1414	return rc;
1415	}
1416
1417
1418	/**
1419	* Deinitializes the bare minimum state used for HM context and if necessary
1420	* disable HM on the CPU.
1421	*
1422	* @returns VBox status code.
1423	* @param pVCpu The cross context virtual CPU structure.
1424	*
1425	* @remarks No-long-jump zone!!!
1426	*/
1427	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1428	{
1429	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1430	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1431
1432	RTCPUID idCpu = RTMpCpuId();
1433	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1434
1435	if ( !g_HmR0.fGlobalInit
1436	&& pCpu->fConfigured)
1437	{
1438	int rc = hmR0DisableCpu(idCpu);
1439	AssertRCReturn(rc, rc);
1440	Assert(!pCpu->fConfigured);
1441	Assert(pCpu->idCpu == NIL_RTCPUID);
1442
1443	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1444	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1445	}
1446
1447	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1448	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1449
1450	return VINF_SUCCESS;
1451	}
1452
1453
1454	/**
1455	* Thread-context hook for HM.
1456	*
1457	* @param enmEvent The thread-context event.
1458	* @param pvUser Opaque pointer to the VMCPU.
1459	*/
1460	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1461	{
1462	PVMCPU pVCpu = (PVMCPU)pvUser;
1463	Assert(pVCpu);
1464	Assert(g_HmR0.pfnThreadCtxCallback);
1465
1466	g_HmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HmR0.fGlobalInit);
1467	}
1468
1469
1470	/**
1471	* Runs guest code in a hardware accelerated VM.
1472	*
1473	* @returns Strict VBox status code. (VBOXSTRICTRC isn't used because it's
1474	* called from setjmp assembly.)
1475	* @param pVM The cross context VM structure.
1476	* @param pVCpu The cross context virtual CPU structure.
1477	*
1478	* @remarks Can be called with preemption enabled if thread-context hooks are
1479	* used!!!
1480	*/
1481	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1482	{
1483	#ifdef VBOX_STRICT
1484	/* With thread-context hooks we would be running this code with preemption enabled. */
1485	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1486	{
1487	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[RTMpCpuId()];
1488	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1489	Assert(pCpu->fConfigured);
1490	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1491	}
1492	#endif
1493
1494	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1495	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_4);
1496	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1497	PGMRZDynMapStartAutoSet(pVCpu);
1498	#endif
1499
1500	VBOXSTRICTRC rcStrict = g_HmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1501
1502	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1503	PGMRZDynMapReleaseAutoSet(pVCpu);
1504	#endif
1505	return VBOXSTRICTRC_VAL(rcStrict);
1506	}
1507
1508
1509	/**
1510	* Notification from CPUM that it has unloaded the guest FPU/SSE/AVX state from
1511	* the host CPU and that guest access to it must be intercepted.
1512	*
1513	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1514	*/
1515	VMMR0_INT_DECL(void) HMR0NotifyCpumUnloadedGuestFpuState(PVMCPU pVCpu)
1516	{
1517	HMCPU_CF_SET(pVCpu, HM_CHANGED_GUEST_CR0);
1518	}
1519
1520
1521	/**
1522	* Notification from CPUM that it has modified the host CR0 (because of FPU).
1523	*
1524	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1525	*/
1526	VMMR0_INT_DECL(void) HMR0NotifyCpumModifiedHostCr0(PVMCPU pVCpu)
1527	{
1528	HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT);
1529	}
1530
1531
1532	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1533
1534	/**
1535	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1536	*
1537	* @returns VBox status code.
1538	* @param pVM The cross context VM structure.
1539	* @param pVCpu The cross context virtual CPU structure.
1540	* @param pCtx Pointer to the guest CPU context.
1541	*/
1542	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1543	{
1544	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1545	if (pVM->hm.s.vmx.fSupported)
1546	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1547	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1548	}
1549
1550
1551	/**
1552	* Save guest debug state (64 bits guest mode & 32 bits host only)
1553	*
1554	* @returns VBox status code.
1555	* @param pVM The cross context VM structure.
1556	* @param pVCpu The cross context virtual CPU structure.
1557	* @param pCtx Pointer to the guest CPU context.
1558	*/
1559	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1560	{
1561	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1562	if (pVM->hm.s.vmx.fSupported)
1563	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1564	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1565	}
1566
1567
1568	/**
1569	* Test the 32->64 bits switcher.
1570	*
1571	* @returns VBox status code.
1572	* @param pVM The cross context VM structure.
1573	*/
1574	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1575	{
1576	PVMCPU pVCpu = &pVM->aCpus[0];
1577	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1578	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1579	int rc;
1580
1581	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1582	if (pVM->hm.s.vmx.fSupported)
1583	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1584	else
1585	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1586	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1587
1588	return rc;
1589	}
1590
1591	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) */
1592
1593	/**
1594	* Returns suspend status of the host.
1595	*
1596	* @returns Suspend pending or not.
1597	*/
1598	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1599	{
1600	return ASMAtomicReadBool(&g_HmR0.fSuspended);
1601	}
1602
1603
1604	/**
1605	* Returns the cpu structure for the current cpu.
1606	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1607	*
1608	* @returns The cpu structure pointer.
1609	*/
1610	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1611	{
1612	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1613	RTCPUID idCpu = RTMpCpuId();
1614	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1615	return &g_HmR0.aCpuInfo[idCpu];
1616	}
1617
1618
1619	/**
1620	* Returns the cpu structure for the current cpu.
1621	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1622	*
1623	* @returns The cpu structure pointer.
1624	* @param idCpu id of the VCPU.
1625	*/
1626	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1627	{
1628	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1629	return &g_HmR0.aCpuInfo[idCpu];
1630	}
1631
1632
1633	/**
1634	* Save a pending IO read.
1635	*
1636	* @param pVCpu The cross context virtual CPU structure.
1637	* @param GCPtrRip Address of IO instruction.
1638	* @param GCPtrRipNext Address of the next instruction.
1639	* @param uPort Port address.
1640	* @param uAndVal AND mask for saving the result in eax.
1641	* @param cbSize Read size.
1642	*/
1643	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1644	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1645	{
1646	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1647	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1648	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1649	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1650	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1651	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1652	return;
1653	}
1654
1655	#ifdef VBOX_WITH_RAW_MODE
1656
1657	/**
1658	* Raw-mode switcher hook - disable VT-x if it's active and the current
1659	* switcher turns off paging.
1660	*
1661	* @returns VBox status code.
1662	* @param pVM The cross context VM structure.
1663	* @param enmSwitcher The switcher we're about to use.
1664	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1665	*/
1666	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1667	{
1668	NOREF(pVM);
1669
1670	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1671
1672	*pfVTxDisabled = false;
1673
1674	/* No such issues with AMD-V */
1675	if (!g_HmR0.vmx.fSupported)
1676	return VINF_SUCCESS;
1677
1678	/* Check if the switching we're up to is safe. */
1679	switch (enmSwitcher)
1680	{
1681	case VMMSWITCHER_32_TO_32:
1682	case VMMSWITCHER_PAE_TO_PAE:
1683	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1684
1685	case VMMSWITCHER_32_TO_PAE:
1686	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1687	case VMMSWITCHER_AMD64_TO_32:
1688	case VMMSWITCHER_AMD64_TO_PAE:
1689	break; /* unsafe switchers */
1690
1691	default:
1692	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1693	}
1694
1695	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1696	regardless of whether we're currently using VT-x or not. */
1697	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1698	{
1699	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1700	return VINF_SUCCESS;
1701	}
1702
1703	/** @todo Check if this code is presumptive wrt other VT-x users on the
1704	* system... */
1705
1706	/* Nothing to do if we haven't enabled VT-x. */
1707	if (!g_HmR0.fEnabled)
1708	return VINF_SUCCESS;
1709
1710	/* Local init implies the CPU is currently not in VMX root mode. */
1711	if (!g_HmR0.fGlobalInit)
1712	return VINF_SUCCESS;
1713
1714	/* Ok, disable VT-x. */
1715	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1716	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ && pCpu->pvMemObj && pCpu->HCPhysMemObj != NIL_RTHCPHYS, VERR_HM_IPE_2);
1717
1718	*pfVTxDisabled = true;
1719	return VMXR0DisableCpu(pCpu, pCpu->pvMemObj, pCpu->HCPhysMemObj);
1720	}
1721
1722
1723	/**
1724	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1725	* switcher turned off paging.
1726	*
1727	* @param pVM The cross context VM structure.
1728	* @param fVTxDisabled Whether VT-x was disabled or not.
1729	*/
1730	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1731	{
1732	Assert(!ASMIntAreEnabled());
1733
1734	if (!fVTxDisabled)
1735	return; /* nothing to do */
1736
1737	Assert(g_HmR0.vmx.fSupported);
1738	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1739	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1740	else
1741	{
1742	Assert(g_HmR0.fEnabled);
1743	Assert(g_HmR0.fGlobalInit);
1744
1745	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1746	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ && pCpu->pvMemObj && pCpu->HCPhysMemObj != NIL_RTHCPHYS);
1747
1748	VMXR0EnableCpu(pCpu, pVM, pCpu->pvMemObj, pCpu->HCPhysMemObj, false, &g_HmR0.vmx.Msrs);
1749	}
1750	}
1751
1752	#endif /* VBOX_WITH_RAW_MODE */
1753	#ifdef VBOX_STRICT
1754
1755	/**
1756	* Dumps a descriptor.
1757	*
1758	* @param pDesc Descriptor to dump.
1759	* @param Sel Selector number.
1760	* @param pszMsg Message to prepend the log entry with.
1761	*/
1762	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1763	{
1764	/*
1765	* Make variable description string.
1766	*/
1767	static struct
1768	{
1769	unsigned cch;
1770	const char *psz;
1771	} const s_aTypes[32] =
1772	{
1773	# define STRENTRY(str) { sizeof(str) - 1, str }
1774
1775	/* system */
1776	# if HC_ARCH_BITS == 64
1777	STRENTRY("Reserved0 "), /* 0x00 */
1778	STRENTRY("Reserved1 "), /* 0x01 */
1779	STRENTRY("LDT "), /* 0x02 */
1780	STRENTRY("Reserved3 "), /* 0x03 */
1781	STRENTRY("Reserved4 "), /* 0x04 */
1782	STRENTRY("Reserved5 "), /* 0x05 */
1783	STRENTRY("Reserved6 "), /* 0x06 */
1784	STRENTRY("Reserved7 "), /* 0x07 */
1785	STRENTRY("Reserved8 "), /* 0x08 */
1786	STRENTRY("TSS64Avail "), /* 0x09 */
1787	STRENTRY("ReservedA "), /* 0x0a */
1788	STRENTRY("TSS64Busy "), /* 0x0b */
1789	STRENTRY("Call64 "), /* 0x0c */
1790	STRENTRY("ReservedD "), /* 0x0d */
1791	STRENTRY("Int64 "), /* 0x0e */
1792	STRENTRY("Trap64 "), /* 0x0f */
1793	# else
1794	STRENTRY("Reserved0 "), /* 0x00 */
1795	STRENTRY("TSS16Avail "), /* 0x01 */
1796	STRENTRY("LDT "), /* 0x02 */
1797	STRENTRY("TSS16Busy "), /* 0x03 */
1798	STRENTRY("Call16 "), /* 0x04 */
1799	STRENTRY("Task "), /* 0x05 */
1800	STRENTRY("Int16 "), /* 0x06 */
1801	STRENTRY("Trap16 "), /* 0x07 */
1802	STRENTRY("Reserved8 "), /* 0x08 */
1803	STRENTRY("TSS32Avail "), /* 0x09 */
1804	STRENTRY("ReservedA "), /* 0x0a */
1805	STRENTRY("TSS32Busy "), /* 0x0b */
1806	STRENTRY("Call32 "), /* 0x0c */
1807	STRENTRY("ReservedD "), /* 0x0d */
1808	STRENTRY("Int32 "), /* 0x0e */
1809	STRENTRY("Trap32 "), /* 0x0f */
1810	# endif
1811	/* non system */
1812	STRENTRY("DataRO "), /* 0x10 */
1813	STRENTRY("DataRO Accessed "), /* 0x11 */
1814	STRENTRY("DataRW "), /* 0x12 */
1815	STRENTRY("DataRW Accessed "), /* 0x13 */
1816	STRENTRY("DataDownRO "), /* 0x14 */
1817	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1818	STRENTRY("DataDownRW "), /* 0x16 */
1819	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1820	STRENTRY("CodeEO "), /* 0x18 */
1821	STRENTRY("CodeEO Accessed "), /* 0x19 */
1822	STRENTRY("CodeER "), /* 0x1a */
1823	STRENTRY("CodeER Accessed "), /* 0x1b */
1824	STRENTRY("CodeConfEO "), /* 0x1c */
1825	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1826	STRENTRY("CodeConfER "), /* 0x1e */
1827	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1828	# undef SYSENTRY
1829	};
1830	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1831	char szMsg[128];
1832	char *psz = &szMsg[0];
1833	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1834	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1835	psz += s_aTypes[i].cch;
1836
1837	if (pDesc->Gen.u1Present)
1838	ADD_STR(psz, "Present ");
1839	else
1840	ADD_STR(psz, "Not-Present ");
1841	# if HC_ARCH_BITS == 64
1842	if (pDesc->Gen.u1Long)
1843	ADD_STR(psz, "64-bit ");
1844	else
1845	ADD_STR(psz, "Comp ");
1846	# else
1847	if (pDesc->Gen.u1Granularity)
1848	ADD_STR(psz, "Page ");
1849	if (pDesc->Gen.u1DefBig)
1850	ADD_STR(psz, "32-bit ");
1851	else
1852	ADD_STR(psz, "16-bit ");
1853	# endif
1854	# undef ADD_STR
1855	*psz = '\0';
1856
1857	/*
1858	* Limit and Base and format the output.
1859	*/
1860	#ifdef LOG_ENABLED
1861	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1862
1863	# if HC_ARCH_BITS == 64
1864	uint64_t u32Base = X86DESC64_BASE(pDesc);
1865	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1866	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1867	# else
1868	uint32_t u32Base = X86DESC_BASE(pDesc);
1869	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1870	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1871	# endif
1872	#else
1873	NOREF(Sel); NOREF(pszMsg);
1874	#endif
1875	}
1876
1877
1878	/**
1879	* Formats a full register dump.
1880	*
1881	* @param pVM The cross context VM structure.
1882	* @param pVCpu The cross context virtual CPU structure.
1883	* @param pCtx Pointer to the CPU context.
1884	*/
1885	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1886	{
1887	NOREF(pVM);
1888
1889	/*
1890	* Format the flags.
1891	*/
1892	static struct
1893	{
1894	const char pszSet; const char pszClear; uint32_t fFlag;
1895	} const s_aFlags[] =
1896	{
1897	{ "vip", NULL, X86_EFL_VIP },
1898	{ "vif", NULL, X86_EFL_VIF },
1899	{ "ac", NULL, X86_EFL_AC },
1900	{ "vm", NULL, X86_EFL_VM },
1901	{ "rf", NULL, X86_EFL_RF },
1902	{ "nt", NULL, X86_EFL_NT },
1903	{ "ov", "nv", X86_EFL_OF },
1904	{ "dn", "up", X86_EFL_DF },
1905	{ "ei", "di", X86_EFL_IF },
1906	{ "tf", NULL, X86_EFL_TF },
1907	{ "nt", "pl", X86_EFL_SF },
1908	{ "nz", "zr", X86_EFL_ZF },
1909	{ "ac", "na", X86_EFL_AF },
1910	{ "po", "pe", X86_EFL_PF },
1911	{ "cy", "nc", X86_EFL_CF },
1912	};
1913	char szEFlags[80];
1914	char *psz = szEFlags;
1915	uint32_t uEFlags = pCtx->eflags.u32;
1916	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1917	{
1918	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1919	if (pszAdd)
1920	{
1921	strcpy(psz, pszAdd);
1922	psz += strlen(pszAdd);
1923	*psz++ = ' ';
1924	}
1925	}
1926	psz[-1] = '\0';
1927
1928
1929	/*
1930	* Format the registers.
1931	*/
1932	if (CPUMIsGuestIn64BitCode(pVCpu))
1933	{
1934	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1935	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1936	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1937	"r14=%016RX64 r15=%016RX64\n"
1938	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1939	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1940	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1941	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1942	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1943	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1944	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1945	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1946	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1947	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1948	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1949	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1950	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1951	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1952	,
1953	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1954	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1955	pCtx->r14, pCtx->r15,
1956	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1957	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1958	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1959	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1960	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1961	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1962	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1963	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1964	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1965	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1966	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1967	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1968	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1969	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1970	}
1971	else
1972	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1973	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1974	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1975	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1976	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1977	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1978	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1979	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1980	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1981	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1982	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1983	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1984	,
1985	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1986	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1987	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
1988	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
1989	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
1990	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
1991	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
1992	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
1993	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1994	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1995	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1996	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1997
1998	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1999	Log(("FPU:\n"
2000	"FCW=%04x FSW=%04x FTW=%02x\n"
2001	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2002	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2003	,
2004	pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
2005	pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
2006	pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
2007	pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
2008
2009	Log(("MSR:\n"
2010	"EFER =%016RX64\n"
2011	"PAT =%016RX64\n"
2012	"STAR =%016RX64\n"
2013	"CSTAR =%016RX64\n"
2014	"LSTAR =%016RX64\n"
2015	"SFMASK =%016RX64\n"
2016	"KERNELGSBASE =%016RX64\n",
2017	pCtx->msrEFER,
2018	pCtx->msrPAT,
2019	pCtx->msrSTAR,
2020	pCtx->msrCSTAR,
2021	pCtx->msrLSTAR,
2022	pCtx->msrSFMASK,
2023	pCtx->msrKERNELGSBASE));
2024
2025	NOREF(pFpuCtx);
2026	}
2027
2028	#endif /* VBOX_STRICT */
2029

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 62338

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