HMR0.cpp@ 58912

Last change on this file since 58912 was 58912, checked in by vboxsync, 9 years ago
HMGLOBALCPUINFO: Cache the RTR0MemObjGetPagePhysAddr and RTR0MemObjAddress results as they aren't necessiarly all that fast.
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1	/* $Id: HMR0.cpp 58912 2015-11-29 20:08:14Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/hm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/vmm/gim.h>
30	#include <VBox/err.h>
31	#include <VBox/log.h>
32	#include <iprt/assert.h>
33	#include <iprt/asm.h>
34	#include <iprt/asm-amd64-x86.h>
35	#include <iprt/cpuset.h>
36	#include <iprt/mem.h>
37	#include <iprt/memobj.h>
38	#include <iprt/once.h>
39	#include <iprt/param.h>
40	#include <iprt/power.h>
41	#include <iprt/string.h>
42	#include <iprt/thread.h>
43	#include <iprt/x86.h>
44	#include "HMVMXR0.h"
45	#include "HMSVMR0.h"
46
47
48	/*********************************************************************************************************************************
49	* Internal Functions *
50	*********************************************************************************************************************************/
51	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
56	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
57
58
59	/*********************************************************************************************************************************
60	* Structures and Typedefs *
61	*********************************************************************************************************************************/
62	/**
63	* This is used to manage the status code of a RTMpOnAll in HM.
64	*/
65	typedef struct HMR0FIRSTRC
66	{
67	/** The status code. */
68	int32_t volatile rc;
69	/** The ID of the CPU reporting the first failure. */
70	RTCPUID volatile idCpu;
71	} HMR0FIRSTRC;
72	/** Pointer to a first return code structure. */
73	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
74
75
76	/*********************************************************************************************************************************
77	* Global Variables *
78	*********************************************************************************************************************************/
79	/**
80	* Global data.
81	*/
82	static struct
83	{
84	/** Per CPU globals. */
85	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
86
87	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
88	* @{ */
89	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
90	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
91	DECLR0CALLBACKMEMBER(int, pfnSaveHostState, (PVM pVM, PVMCPU pVCpu));
92	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode, (PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
93	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
94	bool fEnabledByHost, void *pvArg));
95	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
96	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
98	DECLR0CALLBACKMEMBER(int, pfnSetupVM ,(PVM pVM));
99	/** @} */
100
101	/** Maximum ASID allowed. */
102	uint32_t uMaxAsid;
103
104	/** VT-x data. */
105	struct
106	{
107	/** Set to by us to indicate VMX is supported by the CPU. */
108	bool fSupported;
109	/** Whether we're using SUPR0EnableVTx or not. */
110	bool fUsingSUPR0EnableVTx;
111	/** Whether we're using the preemption timer or not. */
112	bool fUsePreemptTimer;
113	/** The shift mask employed by the VMX-Preemption timer. */
114	uint8_t cPreemptTimerShift;
115
116	/** Host CR4 value (set by ring-0 VMX init) */
117	uint64_t u64HostCr4;
118
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t u64HostEfer;
121
122	/** VMX MSR values */
123	VMXMSRS Msrs;
124
125	/** Last instruction error. */
126	uint32_t ulLastInstrError;
127
128	/** Set if we've called SUPR0EnableVTx(true) and should disable it during
129	* module termination. */
130	bool fCalledSUPR0EnableVTx;
131	} vmx;
132
133	/** AMD-V information. */
134	struct
135	{
136	/* HWCR MSR (for diagnostics) */
137	uint64_t u64MsrHwcr;
138
139	/** SVM revision. */
140	uint32_t u32Rev;
141
142	/** SVM feature bits from cpuid 0x8000000a */
143	uint32_t u32Features;
144
145	/** Set by us to indicate SVM is supported by the CPU. */
146	bool fSupported;
147	} svm;
148	/** Saved error from detection */
149	int32_t lLastError;
150
151	/** CPUID 0x80000001 ecx:edx features */
152	struct
153	{
154	uint32_t u32AMDFeatureECX;
155	uint32_t u32AMDFeatureEDX;
156	} cpuid;
157
158	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
159	* enabled and disabled each time it's used to execute guest code. */
160	bool fGlobalInit;
161	/** Indicates whether the host is suspending or not. We'll refuse a few
162	* actions when the host is being suspended to speed up the suspending and
163	* avoid trouble. */
164	volatile bool fSuspended;
165
166	/** Whether we've already initialized all CPUs.
167	* @remarks We could check the EnableAllCpusOnce state, but this is
168	* simpler and hopefully easier to understand. */
169	bool fEnabled;
170	/** Serialize initialization in HMR0EnableAllCpus. */
171	RTONCE EnableAllCpusOnce;
172	} g_HmR0;
173
174
175
176	/**
177	* Initializes a first return code structure.
178	*
179	* @param pFirstRc The structure to init.
180	*/
181	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
182	{
183	pFirstRc->rc = VINF_SUCCESS;
184	pFirstRc->idCpu = NIL_RTCPUID;
185	}
186
187
188	/**
189	* Try set the status code (success ignored).
190	*
191	* @param pFirstRc The first return code structure.
192	* @param rc The status code.
193	*/
194	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
195	{
196	if ( RT_FAILURE(rc)
197	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
198	pFirstRc->idCpu = RTMpCpuId();
199	}
200
201
202	/**
203	* Get the status code of a first return code structure.
204	*
205	* @returns The status code; VINF_SUCCESS or error status, no informational or
206	* warning errors.
207	* @param pFirstRc The first return code structure.
208	*/
209	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
210	{
211	return pFirstRc->rc;
212	}
213
214
215	#ifdef VBOX_STRICT
216	/**
217	* Get the CPU ID on which the failure status code was reported.
218	*
219	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
220	* @param pFirstRc The first return code structure.
221	*/
222	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
223	{
224	return pFirstRc->idCpu;
225	}
226	#endif /* VBOX_STRICT */
227
228
229	/** @name Dummy callback handlers.
230	* @{ */
231
232	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
233	{
234	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
235	return VINF_SUCCESS;
236	}
237
238	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
239	{
240	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
241	}
242
243	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
244	bool fEnabledBySystem, void *pvArg)
245	{
246	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem); NOREF(pvArg);
247	return VINF_SUCCESS;
248	}
249
250	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
251	{
252	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
253	return VINF_SUCCESS;
254	}
255
256	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
257	{
258	NOREF(pVM);
259	return VINF_SUCCESS;
260	}
261
262	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
263	{
264	NOREF(pVM);
265	return VINF_SUCCESS;
266	}
267
268	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
269	{
270	NOREF(pVM);
271	return VINF_SUCCESS;
272	}
273
274	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
275	{
276	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
277	return VINF_SUCCESS;
278	}
279
280	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
281	{
282	NOREF(pVM); NOREF(pVCpu);
283	return VINF_SUCCESS;
284	}
285
286	/** @} */
287
288
289	/**
290	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
291	* Down at the Rate Specified" erratum.
292	*
293	* Errata names and related steppings:
294	* - BA86 - D0.
295	* - AAX65 - C2.
296	* - AAU65 - C2, K0.
297	* - AAO95 - B1.
298	* - AAT59 - C2.
299	* - AAK139 - D0.
300	* - AAM126 - C0, C1, D0.
301	* - AAN92 - B1.
302	* - AAJ124 - C0, D0.
303	*
304	* - AAP86 - B1.
305	*
306	* Steppings: B1, C0, C1, C2, D0, K0.
307	*
308	* @returns true if subject to it, false if not.
309	*/
310	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
311	{
312	uint32_t u = ASMCpuId_EAX(1);
313	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
314	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
315	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
316	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
317	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
318	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
319	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
320	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
321	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
322	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
323	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
324	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
325	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
326	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
327	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
328	)
329	return true;
330	return false;
331	}
332
333
334	/**
335	* Intel specific initialization code.
336	*
337	* @returns VBox status code (will only fail if out of memory).
338	*/
339	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
340	{
341	/*
342	* Check that all the required VT-x features are present.
343	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
344	*/
345	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
346	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
347	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
348	)
349	{
350	/* Read this MSR now as it may be useful for error reporting when initializing VT-x fails. */
351	g_HmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
352
353	/*
354	* First try use native kernel API for controlling VT-x.
355	* (This is only supported by some Mac OS X kernels atm.)
356	*/
357	int rc = g_HmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
358	g_HmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
359	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
360	{
361	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
362	if (RT_SUCCESS(rc))
363	{
364	g_HmR0.vmx.fSupported = true;
365	rc = SUPR0EnableVTx(false /* fEnable */);
366	AssertLogRelRC(rc);
367	}
368	}
369	else
370	{
371	HMR0FIRSTRC FirstRc;
372	hmR0FirstRcInit(&FirstRc);
373	g_HmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
374	if (RT_SUCCESS(g_HmR0.lLastError))
375	g_HmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
376	}
377	if (RT_SUCCESS(g_HmR0.lLastError))
378	{
379	/* Reread in case it was changed by SUPR0GetVmxUsability(). */
380	g_HmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
381
382	/*
383	* Read all relevant registers and MSRs.
384	*/
385	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
386	g_HmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
387	g_HmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
388	g_HmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
389	g_HmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
390	g_HmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
391	g_HmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
392	g_HmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
393	g_HmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
394	g_HmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
395	g_HmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
396	g_HmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
397	g_HmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
398	/* VPID 16 bits ASID. */
399	g_HmR0.uMaxAsid = 0x10000; /* exclusive */
400
401	if (g_HmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
402	{
403	g_HmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
404	if (g_HmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
405	g_HmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
406
407	if (g_HmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
408	g_HmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
409	}
410
411	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
412	{
413	/*
414	* Enter root mode
415	*/
416	RTR0MEMOBJ hScatchMemObj;
417	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
418	if (RT_FAILURE(rc))
419	{
420	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
421	return rc;
422	}
423
424	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
425	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
426	ASMMemZeroPage(pvScatchPage);
427
428	/* Set revision dword at the beginning of the structure. */
429	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HmR0.vmx.Msrs.u64BasicInfo);
430
431	/* Make sure we don't get rescheduled to another cpu during this probe. */
432	RTCCUINTREG fFlags = ASMIntDisableFlags();
433
434	/*
435	* Check CR4.VMXE
436	*/
437	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
438	if (!(g_HmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
439	{
440	/* In theory this bit could be cleared behind our back. Which would cause
441	#UD faults when we try to execute the VMX instructions... */
442	ASMSetCR4(g_HmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
443	}
444
445	/*
446	* The only way of checking if we're in VMX root mode or not is to try and enter it.
447	* There is no instruction or control bit that tells us if we're in VMX root mode.
448	* Therefore, try and enter VMX root mode here.
449	*/
450	rc = VMXEnable(HCPhysScratchPage);
451	if (RT_SUCCESS(rc))
452	{
453	g_HmR0.vmx.fSupported = true;
454	VMXDisable();
455	}
456	else
457	{
458	/*
459	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
460	* it will crash the host when we enter raw mode, because:
461	*
462	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
463	* this bit), and
464	* (b) turning off paging causes a #GP (unavoidable when switching
465	* from long to 32 bits mode or 32 bits to PAE).
466	*
467	* They should fix their code, but until they do we simply refuse to run.
468	*/
469	g_HmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
470	Assert(g_HmR0.vmx.fSupported == false);
471	}
472
473	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
474	if it wasn't so before (some software could incorrectly
475	think it's in VMX mode). */
476	ASMSetCR4(g_HmR0.vmx.u64HostCr4);
477	ASMSetFlags(fFlags);
478
479	RTR0MemObjFree(hScatchMemObj, false);
480	}
481
482	if (g_HmR0.vmx.fSupported)
483	{
484	rc = VMXR0GlobalInit();
485	if (RT_FAILURE(rc))
486	g_HmR0.lLastError = rc;
487
488	/*
489	* Install the VT-x methods.
490	*/
491	g_HmR0.pfnEnterSession = VMXR0Enter;
492	g_HmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
493	g_HmR0.pfnSaveHostState = VMXR0SaveHostState;
494	g_HmR0.pfnRunGuestCode = VMXR0RunGuestCode;
495	g_HmR0.pfnEnableCpu = VMXR0EnableCpu;
496	g_HmR0.pfnDisableCpu = VMXR0DisableCpu;
497	g_HmR0.pfnInitVM = VMXR0InitVM;
498	g_HmR0.pfnTermVM = VMXR0TermVM;
499	g_HmR0.pfnSetupVM = VMXR0SetupVM;
500
501	/*
502	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
503	* Timer Does Not Count Down at the Rate Specified" erratum.
504	*/
505	if (g_HmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
506	{
507	g_HmR0.vmx.fUsePreemptTimer = true;
508	g_HmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HmR0.vmx.Msrs.u64Misc);
509	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
510	g_HmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
511	}
512	}
513	}
514	#ifdef LOG_ENABLED
515	else
516	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HmR0.lLastError);
517	#endif
518	}
519	else
520	g_HmR0.lLastError = VERR_VMX_NO_VMX;
521	return VINF_SUCCESS;
522	}
523
524
525	/**
526	* AMD-specific initialization code.
527	*
528	* @returns VBox status code.
529	*/
530	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
531	{
532	/*
533	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
534	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
535	*/
536	int rc;
537	if ( (g_HmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
538	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
539	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
540	&& ASMIsValidExtRange(uMaxExtLeaf)
541	&& uMaxExtLeaf >= 0x8000000a
542	)
543	{
544	/* Call the global AMD-V initialization routine. */
545	rc = SVMR0GlobalInit();
546	if (RT_FAILURE(rc))
547	{
548	g_HmR0.lLastError = rc;
549	return rc;
550	}
551
552	/*
553	* Install the AMD-V methods.
554	*/
555	g_HmR0.pfnEnterSession = SVMR0Enter;
556	g_HmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
557	g_HmR0.pfnSaveHostState = SVMR0SaveHostState;
558	g_HmR0.pfnRunGuestCode = SVMR0RunGuestCode;
559	g_HmR0.pfnEnableCpu = SVMR0EnableCpu;
560	g_HmR0.pfnDisableCpu = SVMR0DisableCpu;
561	g_HmR0.pfnInitVM = SVMR0InitVM;
562	g_HmR0.pfnTermVM = SVMR0TermVM;
563	g_HmR0.pfnSetupVM = SVMR0SetupVM;
564
565	/* Query AMD features. */
566	uint32_t u32Dummy;
567	ASMCpuId(0x8000000a, &g_HmR0.svm.u32Rev, &g_HmR0.uMaxAsid, &u32Dummy, &g_HmR0.svm.u32Features);
568
569	/*
570	* We need to check if AMD-V has been properly initialized on all CPUs.
571	* Some BIOSes might do a poor job.
572	*/
573	HMR0FIRSTRC FirstRc;
574	hmR0FirstRcInit(&FirstRc);
575	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
576	AssertRC(rc);
577	if (RT_SUCCESS(rc))
578	rc = hmR0FirstRcGetStatus(&FirstRc);
579	#ifndef DEBUG_bird
580	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
581	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
582	#endif
583	if (RT_SUCCESS(rc))
584	{
585	/* Read the HWCR MSR for diagnostics. */
586	g_HmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
587	g_HmR0.svm.fSupported = true;
588	}
589	else
590	{
591	g_HmR0.lLastError = rc;
592	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
593	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
594	}
595	}
596	else
597	{
598	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
599	g_HmR0.lLastError = VERR_SVM_NO_SVM;
600	}
601	return rc;
602	}
603
604
605	/**
606	* Does global Ring-0 HM initialization (at module init).
607	*
608	* @returns VBox status code.
609	*/
610	VMMR0_INT_DECL(int) HMR0Init(void)
611	{
612	/*
613	* Initialize the globals.
614	*/
615	g_HmR0.fEnabled = false;
616	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
617	g_HmR0.EnableAllCpusOnce = s_OnceInit;
618	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
619	{
620	g_HmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
621	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
622	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
623	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
624	}
625
626	/* Fill in all callbacks with placeholders. */
627	g_HmR0.pfnEnterSession = hmR0DummyEnter;
628	g_HmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
629	g_HmR0.pfnSaveHostState = hmR0DummySaveHostState;
630	g_HmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
631	g_HmR0.pfnEnableCpu = hmR0DummyEnableCpu;
632	g_HmR0.pfnDisableCpu = hmR0DummyDisableCpu;
633	g_HmR0.pfnInitVM = hmR0DummyInitVM;
634	g_HmR0.pfnTermVM = hmR0DummyTermVM;
635	g_HmR0.pfnSetupVM = hmR0DummySetupVM;
636
637	/* Default is global VT-x/AMD-V init. */
638	g_HmR0.fGlobalInit = true;
639
640	/*
641	* Make sure aCpuInfo is big enough for all the CPUs on this system.
642	*/
643	if (RTMpGetArraySize() > RT_ELEMENTS(g_HmR0.aCpuInfo))
644	{
645	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HmR0.aCpuInfo)));
646	return VERR_TOO_MANY_CPUS;
647	}
648
649	/*
650	* Check for VT-x and AMD-V capabilities.
651	*/
652	int rc;
653	if (ASMHasCpuId())
654	{
655	/* Standard features. */
656	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
657	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
658	if (ASMIsValidStdRange(uMaxLeaf))
659	{
660	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
661	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
662
663	/* Query AMD features. */
664	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
665	if (ASMIsValidExtRange(uMaxExtLeaf))
666	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
667	&g_HmR0.cpuid.u32AMDFeatureECX,
668	&g_HmR0.cpuid.u32AMDFeatureEDX);
669	else
670	g_HmR0.cpuid.u32AMDFeatureECX = g_HmR0.cpuid.u32AMDFeatureEDX = 0;
671
672	/* Go to CPU specific initialization code. */
673	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
674	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
675	{
676	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
677	if (RT_FAILURE(rc))
678	return rc;
679	}
680	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
681	{
682	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
683	if (RT_FAILURE(rc))
684	return rc;
685	}
686	else
687	g_HmR0.lLastError = VERR_HM_UNKNOWN_CPU;
688	}
689	else
690	g_HmR0.lLastError = VERR_HM_UNKNOWN_CPU;
691	}
692	else
693	g_HmR0.lLastError = VERR_HM_NO_CPUID;
694
695	/*
696	* Register notification callbacks that we can use to disable/enable CPUs
697	* when brought offline/online or suspending/resuming.
698	*/
699	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
700	{
701	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
702	AssertRC(rc);
703
704	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
705	AssertRC(rc);
706	}
707
708	/* We return success here because module init shall not fail if HM
709	fails to initialize. */
710	return VINF_SUCCESS;
711	}
712
713
714	/**
715	* Does global Ring-0 HM termination (at module termination).
716	*
717	* @returns VBox status code.
718	*/
719	VMMR0_INT_DECL(int) HMR0Term(void)
720	{
721	int rc;
722	if ( g_HmR0.vmx.fSupported
723	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
724	{
725	/*
726	* Simple if the host OS manages VT-x.
727	*/
728	Assert(g_HmR0.fGlobalInit);
729
730	if (g_HmR0.vmx.fCalledSUPR0EnableVTx)
731	{
732	rc = SUPR0EnableVTx(false /* fEnable */);
733	g_HmR0.vmx.fCalledSUPR0EnableVTx = false;
734	}
735	else
736	rc = VINF_SUCCESS;
737
738	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HmR0.aCpuInfo); iCpu++)
739	{
740	g_HmR0.aCpuInfo[iCpu].fConfigured = false;
741	Assert(g_HmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
742	}
743	}
744	else
745	{
746	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
747
748	/* Doesn't really matter if this fails. */
749	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
750	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
751
752	/*
753	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
754	*/
755	if (g_HmR0.fGlobalInit)
756	{
757	HMR0FIRSTRC FirstRc;
758	hmR0FirstRcInit(&FirstRc);
759	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
760	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
761	if (RT_SUCCESS(rc))
762	rc = hmR0FirstRcGetStatus(&FirstRc);
763	}
764
765	/*
766	* Free the per-cpu pages used for VT-x and AMD-V.
767	*/
768	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
769	{
770	if (g_HmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
771	{
772	RTR0MemObjFree(g_HmR0.aCpuInfo[i].hMemObj, false);
773	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
774	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
775	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
776	}
777	}
778	}
779
780	/** @todo This needs cleaning up. There's no matching
781	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
782	* should move into their respective modules. */
783	/* Finally, call global VT-x/AMD-V termination. */
784	if (g_HmR0.vmx.fSupported)
785	VMXR0GlobalTerm();
786	else if (g_HmR0.svm.fSupported)
787	SVMR0GlobalTerm();
788
789	return rc;
790	}
791
792
793	/**
794	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
795	* on a CPU.
796	*
797	* @param idCpu The identifier for the CPU the function is called on.
798	* @param pvUser1 Pointer to the first RC structure.
799	* @param pvUser2 Ignored.
800	*/
801	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
802	{
803	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
804	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
805	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
806	NOREF(idCpu); NOREF(pvUser2);
807
808	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
809	hmR0FirstRcSetStatus(pFirstRc, rc);
810	}
811
812
813	/**
814	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
815	* on a CPU.
816	*
817	* @param idCpu The identifier for the CPU the function is called on.
818	* @param pvUser1 Pointer to the first RC structure.
819	* @param pvUser2 Ignored.
820	*/
821	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
822	{
823	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
824	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
825	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
826	NOREF(idCpu); NOREF(pvUser2);
827
828	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
829	hmR0FirstRcSetStatus(pFirstRc, rc);
830	}
831
832
833	/**
834	* Enable VT-x or AMD-V on the current CPU
835	*
836	* @returns VBox status code.
837	* @param pVM The cross context VM structure. Can be NULL.
838	* @param idCpu The identifier for the CPU the function is called on.
839	*
840	* @remarks Maybe called with interrupts disabled!
841	*/
842	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
843	{
844	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
845
846	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
847	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
848	Assert(!pCpu->fConfigured);
849	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
850
851	pCpu->idCpu = idCpu;
852	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
853
854	int rc;
855	if (g_HmR0.vmx.fSupported && g_HmR0.vmx.fUsingSUPR0EnableVTx)
856	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmR0.vmx.Msrs);
857	else
858	{
859	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
860	if (g_HmR0.vmx.fSupported)
861	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, pCpu->pvMemObj, pCpu->HCPhysMemObj, false, &g_HmR0.vmx.Msrs);
862	else
863	rc = g_HmR0.pfnEnableCpu(pCpu, pVM, pCpu->pvMemObj, pCpu->HCPhysMemObj, false, NULL /* pvArg */);
864	}
865	if (RT_SUCCESS(rc))
866	pCpu->fConfigured = true;
867
868	return rc;
869	}
870
871
872	/**
873	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
874	*
875	* @param idCpu The identifier for the CPU the function is called on.
876	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
877	* @param pvUser2 The 2nd user argument.
878	*/
879	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
880	{
881	PVM pVM = (PVM)pvUser1; /* can be NULL! */
882	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
883	AssertReturnVoid(g_HmR0.fGlobalInit);
884	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
885	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
886	}
887
888
889	/**
890	* RTOnce callback employed by HMR0EnableAllCpus.
891	*
892	* @returns VBox status code.
893	* @param pvUser Pointer to the VM.
894	*/
895	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
896	{
897	PVM pVM = (PVM)pvUser;
898
899	/*
900	* Indicate that we've initialized.
901	*
902	* Note! There is a potential race between this function and the suspend
903	* notification. Kind of unlikely though, so ignored for now.
904	*/
905	AssertReturn(!g_HmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
906	ASMAtomicWriteBool(&g_HmR0.fEnabled, true);
907
908	/*
909	* The global init variable is set by the first VM.
910	*/
911	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
912
913	#ifdef VBOX_STRICT
914	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
915	{
916	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
917	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj == NIL_RTHCPHYS);
918	Assert(g_HmR0.aCpuInfo[i].pvMemObj == NULL);
919	Assert(!g_HmR0.aCpuInfo[i].fConfigured);
920	Assert(!g_HmR0.aCpuInfo[i].cTlbFlushes);
921	Assert(!g_HmR0.aCpuInfo[i].uCurrentAsid);
922	}
923	#endif
924
925	int rc;
926	if ( g_HmR0.vmx.fSupported
927	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
928	{
929	/*
930	* Global VT-x initialization API (only darwin for now).
931	*/
932	rc = SUPR0EnableVTx(true /* fEnable */);
933	if (RT_SUCCESS(rc))
934	{
935	g_HmR0.vmx.fCalledSUPR0EnableVTx = true;
936	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
937	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
938	}
939	else
940	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
941	}
942	else
943	{
944	/*
945	* We're doing the job ourselves.
946	*/
947	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
948	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
949	{
950	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
951
952	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
953	{
954	/** @todo NUMA */
955	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
956	AssertLogRelRCReturn(rc, rc);
957
958	g_HmR0.aCpuInfo[i].HCPhysMemObj = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].hMemObj, 0);
959	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj != NIL_RTHCPHYS);
960	Assert(!(g_HmR0.aCpuInfo[i].HCPhysMemObj & PAGE_OFFSET_MASK));
961
962	g_HmR0.aCpuInfo[i].pvMemObj = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].hMemObj);
963	AssertPtr(g_HmR0.aCpuInfo[i].pvMemObj);
964	ASMMemZeroPage(g_HmR0.aCpuInfo[i].pvMemObj);
965	}
966	}
967
968	rc = VINF_SUCCESS;
969	}
970
971	if ( RT_SUCCESS(rc)
972	&& g_HmR0.fGlobalInit)
973	{
974	/* First time, so initialize each cpu/core. */
975	HMR0FIRSTRC FirstRc;
976	hmR0FirstRcInit(&FirstRc);
977	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
978	if (RT_SUCCESS(rc))
979	rc = hmR0FirstRcGetStatus(&FirstRc);
980	}
981
982	return rc;
983	}
984
985
986	/**
987	* Sets up HM on all cpus.
988	*
989	* @returns VBox status code.
990	* @param pVM The cross context VM structure.
991	*/
992	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
993	{
994	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
995	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
996	return VERR_HM_SUSPEND_PENDING;
997
998	return RTOnce(&g_HmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
999	}
1000
1001
1002	/**
1003	* Disable VT-x or AMD-V on the current CPU.
1004	*
1005	* @returns VBox status code.
1006	* @param idCpu The identifier for the CPU this function is called on.
1007	*
1008	* @remarks Must be called with preemption disabled.
1009	*/
1010	static int hmR0DisableCpu(RTCPUID idCpu)
1011	{
1012	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1013
1014	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1015	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1016	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
1017	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1018	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1019	AssertRelease(idCpu == RTMpCpuId());
1020
1021	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1022	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1023	AssertPtr(pCpu->pvMemObj);
1024	Assert(pCpu->HCPhysMemObj != NIL_RTHCPHYS);
1025
1026	int rc;
1027	if (pCpu->fConfigured)
1028	{
1029	rc = g_HmR0.pfnDisableCpu(pCpu, pCpu->pvMemObj, pCpu->HCPhysMemObj);
1030	AssertRCReturn(rc, rc);
1031
1032	pCpu->fConfigured = false;
1033	pCpu->idCpu = NIL_RTCPUID;
1034	}
1035	else
1036	rc = VINF_SUCCESS; /* nothing to do */
1037	return rc;
1038	}
1039
1040
1041	/**
1042	* Worker function passed to RTMpOnAll() that is to be called on the target
1043	* CPUs.
1044	*
1045	* @param idCpu The identifier for the CPU the function is called on.
1046	* @param pvUser1 The 1st user argument.
1047	* @param pvUser2 Opaque pointer to the FirstRc.
1048	*/
1049	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1050	{
1051	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1052	AssertReturnVoid(g_HmR0.fGlobalInit);
1053	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1054	}
1055
1056
1057	/**
1058	* Worker function passed to RTMpOnSpecific() that is to be called on the target
1059	* CPU.
1060	*
1061	* @param idCpu The identifier for the CPU the function is called on.
1062	* @param pvUser1 Null, not used.
1063	* @param pvUser2 Null, not used.
1064	*/
1065	static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1066	{
1067	NOREF(pvUser1);
1068	NOREF(pvUser2);
1069	hmR0DisableCpu(idCpu);
1070	}
1071
1072
1073	/**
1074	* Callback function invoked when a cpu goes online or offline.
1075	*
1076	* @param enmEvent The Mp event.
1077	* @param idCpu The identifier for the CPU the function is called on.
1078	* @param pvData Opaque data (PVM pointer).
1079	*/
1080	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1081	{
1082	NOREF(pvData);
1083	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1084
1085	/*
1086	* We only care about uninitializing a CPU that is going offline. When a
1087	* CPU comes online, the initialization is done lazily in HMR0Enter().
1088	*/
1089	switch (enmEvent)
1090	{
1091	case RTMPEVENT_OFFLINE:
1092	{
1093	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1094	RTThreadPreemptDisable(&PreemptState);
1095	if (idCpu == RTMpCpuId())
1096	{
1097	int rc = hmR0DisableCpu(idCpu);
1098	AssertRC(rc);
1099	RTThreadPreemptRestore(&PreemptState);
1100	}
1101	else
1102	{
1103	RTThreadPreemptRestore(&PreemptState);
1104	RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 /, NULL / pvUser2 */);
1105	}
1106	break;
1107	}
1108
1109	default:
1110	break;
1111	}
1112	}
1113
1114
1115	/**
1116	* Called whenever a system power state change occurs.
1117	*
1118	* @param enmEvent The Power event.
1119	* @param pvUser User argument.
1120	*/
1121	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1122	{
1123	NOREF(pvUser);
1124	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1125
1126	#ifdef LOG_ENABLED
1127	if (enmEvent == RTPOWEREVENT_SUSPEND)
1128	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1129	else
1130	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1131	#endif
1132
1133	if (enmEvent == RTPOWEREVENT_SUSPEND)
1134	ASMAtomicWriteBool(&g_HmR0.fSuspended, true);
1135
1136	if (g_HmR0.fEnabled)
1137	{
1138	int rc;
1139	HMR0FIRSTRC FirstRc;
1140	hmR0FirstRcInit(&FirstRc);
1141
1142	if (enmEvent == RTPOWEREVENT_SUSPEND)
1143	{
1144	if (g_HmR0.fGlobalInit)
1145	{
1146	/* Turn off VT-x or AMD-V on all CPUs. */
1147	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1148	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1149	}
1150	/* else nothing to do here for the local init case */
1151	}
1152	else
1153	{
1154	/* Reinit the CPUs from scratch as the suspend state might have
1155	messed with the MSRs. (lousy BIOSes as usual) */
1156	if (g_HmR0.vmx.fSupported)
1157	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1158	else
1159	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1160	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1161	if (RT_SUCCESS(rc))
1162	rc = hmR0FirstRcGetStatus(&FirstRc);
1163	#ifdef LOG_ENABLED
1164	if (RT_FAILURE(rc))
1165	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1166	#endif
1167	if (g_HmR0.fGlobalInit)
1168	{
1169	/* Turn VT-x or AMD-V back on on all CPUs. */
1170	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1171	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1172	}
1173	/* else nothing to do here for the local init case */
1174	}
1175	}
1176
1177	if (enmEvent == RTPOWEREVENT_RESUME)
1178	ASMAtomicWriteBool(&g_HmR0.fSuspended, false);
1179	}
1180
1181
1182	/**
1183	* Does ring-0 per-VM HM initialization.
1184	*
1185	* This will copy HM global into the VM structure and call the CPU specific
1186	* init routine which will allocate resources for each virtual CPU and such.
1187	*
1188	* @returns VBox status code.
1189	* @param pVM The cross context VM structure.
1190	*
1191	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1192	* vmR3InitRing3().
1193	*/
1194	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1195	{
1196	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1197
1198	#ifdef LOG_ENABLED
1199	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1200	#endif
1201
1202	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1203	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1204	return VERR_HM_SUSPEND_PENDING;
1205
1206	/*
1207	* Copy globals to the VM structure.
1208	*/
1209	pVM->hm.s.vmx.fSupported = g_HmR0.vmx.fSupported;
1210	pVM->hm.s.svm.fSupported = g_HmR0.svm.fSupported;
1211
1212	pVM->hm.s.vmx.fUsePreemptTimer &= g_HmR0.vmx.fUsePreemptTimer; /* Can be overridden by CFGM. See HMR3Init(). */
1213	pVM->hm.s.vmx.cPreemptTimerShift = g_HmR0.vmx.cPreemptTimerShift;
1214	pVM->hm.s.vmx.u64HostCr4 = g_HmR0.vmx.u64HostCr4;
1215	pVM->hm.s.vmx.u64HostEfer = g_HmR0.vmx.u64HostEfer;
1216	pVM->hm.s.vmx.Msrs = g_HmR0.vmx.Msrs;
1217	pVM->hm.s.svm.u64MsrHwcr = g_HmR0.svm.u64MsrHwcr;
1218	pVM->hm.s.svm.u32Rev = g_HmR0.svm.u32Rev;
1219	pVM->hm.s.svm.u32Features = g_HmR0.svm.u32Features;
1220	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HmR0.cpuid.u32AMDFeatureECX;
1221	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HmR0.cpuid.u32AMDFeatureEDX;
1222	pVM->hm.s.lLastError = g_HmR0.lLastError;
1223	pVM->hm.s.uMaxAsid = g_HmR0.uMaxAsid;
1224
1225	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1226	{
1227	pVM->hm.s.cMaxResumeLoops = 1024;
1228	if (RTThreadPreemptIsPendingTrusty())
1229	pVM->hm.s.cMaxResumeLoops = 8192;
1230	}
1231
1232	/*
1233	* Initialize some per-VCPU fields.
1234	*/
1235	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1236	{
1237	PVMCPU pVCpu = &pVM->aCpus[i];
1238	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1239	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1240	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
1241
1242	/* We'll aways increment this the first time (host uses ASID 0). */
1243	AssertReturn(!pVCpu->hm.s.uCurrentAsid, VERR_HM_IPE_3);
1244	}
1245
1246	pVM->hm.s.fHostKernelFeatures = SUPR0GetKernelFeatures();
1247
1248	/*
1249	* Call the hardware specific initialization method.
1250	*/
1251	return g_HmR0.pfnInitVM(pVM);
1252	}
1253
1254
1255	/**
1256	* Does ring-0 per VM HM termination.
1257	*
1258	* @returns VBox status code.
1259	* @param pVM The cross context VM structure.
1260	*/
1261	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1262	{
1263	Log(("HMR0TermVM: %p\n", pVM));
1264	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1265
1266	/*
1267	* Call the hardware specific method.
1268	*
1269	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1270	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1271	*/
1272	return g_HmR0.pfnTermVM(pVM);
1273	}
1274
1275
1276	/**
1277	* Sets up a VT-x or AMD-V session.
1278	*
1279	* This is mostly about setting up the hardware VM state.
1280	*
1281	* @returns VBox status code.
1282	* @param pVM The cross context VM structure.
1283	*/
1284	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1285	{
1286	Log(("HMR0SetupVM: %p\n", pVM));
1287	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1288
1289	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1290	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1291
1292	/* On first entry we'll sync everything. */
1293	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1294	HMCPU_CF_RESET_TO(&pVM->aCpus[i], HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1295
1296	/*
1297	* Call the hardware specific setup VM method. This requires the CPU to be
1298	* enabled for AMD-V/VT-x and preemption to be prevented.
1299	*/
1300	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1301	RTThreadPreemptDisable(&PreemptState);
1302	RTCPUID idCpu = RTMpCpuId();
1303
1304	/* Enable VT-x or AMD-V if local init is required. */
1305	int rc;
1306	if (!g_HmR0.fGlobalInit)
1307	{
1308	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1309	rc = hmR0EnableCpu(pVM, idCpu);
1310	if (RT_FAILURE(rc))
1311	{
1312	RTThreadPreemptRestore(&PreemptState);
1313	return rc;
1314	}
1315	}
1316
1317	/* Setup VT-x or AMD-V. */
1318	rc = g_HmR0.pfnSetupVM(pVM);
1319
1320	/* Disable VT-x or AMD-V if local init was done before. */
1321	if (!g_HmR0.fGlobalInit)
1322	{
1323	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1324	int rc2 = hmR0DisableCpu(idCpu);
1325	AssertRC(rc2);
1326	}
1327
1328	RTThreadPreemptRestore(&PreemptState);
1329	return rc;
1330	}
1331
1332
1333	/**
1334	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1335	* required for entering HM context.
1336	*
1337	* @returns VBox status code.
1338	* @param pVCpu The cross context virtual CPU structure.
1339	*
1340	* @remarks No-long-jump zone!!!
1341	*/
1342	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1343	{
1344	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1345
1346	int rc = VINF_SUCCESS;
1347	RTCPUID idCpu = RTMpCpuId();
1348	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1349	AssertPtr(pCpu);
1350
1351	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1352	if (!pCpu->fConfigured)
1353	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1354
1355	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1356	HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE);
1357
1358	Assert(pCpu->idCpu == idCpu && pCpu->idCpu != NIL_RTCPUID);
1359	pVCpu->hm.s.idEnteredCpu = idCpu;
1360	return rc;
1361	}
1362
1363
1364	/**
1365	* Enters the VT-x or AMD-V session.
1366	*
1367	* @returns VBox status code.
1368	* @param pVM The cross context VM structure.
1369	* @param pVCpu The cross context virtual CPU structure.
1370	*
1371	* @remarks This is called with preemption disabled.
1372	*/
1373	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1374	{
1375	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1376	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1377	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1378
1379	/* Load the bare minimum state required for entering HM. */
1380	int rc = HMR0EnterCpu(pVCpu);
1381	AssertRCReturn(rc, rc);
1382
1383	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1384	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_5);
1385	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1386	#endif
1387
1388	RTCPUID idCpu = RTMpCpuId();
1389	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1390	Assert(pCpu);
1391	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1392
1393	rc = g_HmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1394	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1395
1396	/* Load the host-state as we may be resuming code after a longjmp and quite
1397	possibly now be scheduled on a different CPU. */
1398	rc = g_HmR0.pfnSaveHostState(pVM, pVCpu);
1399	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1400
1401	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1402	if (fStartedSet)
1403	PGMRZDynMapReleaseAutoSet(pVCpu);
1404	#endif
1405
1406	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1407	if (RT_FAILURE(rc))
1408	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1409	return rc;
1410	}
1411
1412
1413	/**
1414	* Deinitializes the bare minimum state used for HM context and if necessary
1415	* disable HM on the CPU.
1416	*
1417	* @returns VBox status code.
1418	* @param pVCpu The cross context virtual CPU structure.
1419	*
1420	* @remarks No-long-jump zone!!!
1421	*/
1422	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1423	{
1424	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1425	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1426
1427	RTCPUID idCpu = RTMpCpuId();
1428	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[idCpu];
1429
1430	if ( !g_HmR0.fGlobalInit
1431	&& pCpu->fConfigured)
1432	{
1433	int rc = hmR0DisableCpu(idCpu);
1434	AssertRCReturn(rc, rc);
1435	Assert(!pCpu->fConfigured);
1436	Assert(pCpu->idCpu == NIL_RTCPUID);
1437
1438	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1439	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1440	}
1441
1442	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1443	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1444
1445	return VINF_SUCCESS;
1446	}
1447
1448
1449	/**
1450	* Thread-context hook for HM.
1451	*
1452	* @param enmEvent The thread-context event.
1453	* @param pvUser Opaque pointer to the VMCPU.
1454	*/
1455	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1456	{
1457	PVMCPU pVCpu = (PVMCPU)pvUser;
1458	Assert(pVCpu);
1459	Assert(g_HmR0.pfnThreadCtxCallback);
1460
1461	g_HmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HmR0.fGlobalInit);
1462	}
1463
1464
1465	/**
1466	* Runs guest code in a hardware accelerated VM.
1467	*
1468	* @returns VBox status code.
1469	* @param pVM The cross context VM structure.
1470	* @param pVCpu The cross context virtual CPU structure.
1471	*
1472	* @remarks Can be called with preemption enabled if thread-context hooks are
1473	* used!!!
1474	*/
1475	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1476	{
1477	#ifdef VBOX_STRICT
1478	/* With thread-context hooks we would be running this code with preemption enabled. */
1479	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1480	{
1481	PHMGLOBALCPUINFO pCpu = &g_HmR0.aCpuInfo[RTMpCpuId()];
1482	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1483	Assert(pCpu->fConfigured);
1484	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1485	}
1486	#endif
1487
1488	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1489	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_4);
1490	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1491	PGMRZDynMapStartAutoSet(pVCpu);
1492	#endif
1493
1494	int rc = g_HmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1495
1496	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1497	PGMRZDynMapReleaseAutoSet(pVCpu);
1498	#endif
1499	return rc;
1500	}
1501
1502	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1503
1504	/**
1505	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1506	*
1507	* @returns VBox status code.
1508	* @param pVM The cross context VM structure.
1509	* @param pVCpu The cross context virtual CPU structure.
1510	* @param pCtx Pointer to the guest CPU context.
1511	*/
1512	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1513	{
1514	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1515	if (pVM->hm.s.vmx.fSupported)
1516	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1517	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1518	}
1519
1520
1521	/**
1522	* Save guest debug state (64 bits guest mode & 32 bits host only)
1523	*
1524	* @returns VBox status code.
1525	* @param pVM The cross context VM structure.
1526	* @param pVCpu The cross context virtual CPU structure.
1527	* @param pCtx Pointer to the guest CPU context.
1528	*/
1529	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1530	{
1531	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1532	if (pVM->hm.s.vmx.fSupported)
1533	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1534	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1535	}
1536
1537
1538	/**
1539	* Test the 32->64 bits switcher.
1540	*
1541	* @returns VBox status code.
1542	* @param pVM The cross context VM structure.
1543	*/
1544	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1545	{
1546	PVMCPU pVCpu = &pVM->aCpus[0];
1547	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1548	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1549	int rc;
1550
1551	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1552	if (pVM->hm.s.vmx.fSupported)
1553	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1554	else
1555	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1556	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1557
1558	return rc;
1559	}
1560
1561	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) */
1562
1563	/**
1564	* Returns suspend status of the host.
1565	*
1566	* @returns Suspend pending or not.
1567	*/
1568	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1569	{
1570	return ASMAtomicReadBool(&g_HmR0.fSuspended);
1571	}
1572
1573
1574	/**
1575	* Returns the cpu structure for the current cpu.
1576	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1577	*
1578	* @returns The cpu structure pointer.
1579	*/
1580	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1581	{
1582	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1583	RTCPUID idCpu = RTMpCpuId();
1584	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1585	return &g_HmR0.aCpuInfo[idCpu];
1586	}
1587
1588
1589	/**
1590	* Returns the cpu structure for the current cpu.
1591	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1592	*
1593	* @returns The cpu structure pointer.
1594	* @param idCpu id of the VCPU.
1595	*/
1596	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1597	{
1598	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1599	return &g_HmR0.aCpuInfo[idCpu];
1600	}
1601
1602
1603	/**
1604	* Save a pending IO read.
1605	*
1606	* @param pVCpu The cross context virtual CPU structure.
1607	* @param GCPtrRip Address of IO instruction.
1608	* @param GCPtrRipNext Address of the next instruction.
1609	* @param uPort Port address.
1610	* @param uAndVal AND mask for saving the result in eax.
1611	* @param cbSize Read size.
1612	*/
1613	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1614	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1615	{
1616	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1617	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1618	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1619	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1620	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1621	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1622	return;
1623	}
1624
1625
1626	/**
1627	* Save a pending IO write.
1628	*
1629	* @param pVCpu The cross context virtual CPU structure.
1630	* @param GCPtrRip Address of IO instruction.
1631	* @param GCPtrRipNext Address of the next instruction.
1632	* @param uPort Port address.
1633	* @param uAndVal AND mask for fetching the result from eax.
1634	* @param cbSize Read size.
1635	*/
1636	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1637	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1638	{
1639	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1640	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1641	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1642	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1643	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1644	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1645	return;
1646	}
1647
1648	#ifdef VBOX_WITH_RAW_MODE
1649
1650	/**
1651	* Raw-mode switcher hook - disable VT-x if it's active and the current
1652	* switcher turns off paging.
1653	*
1654	* @returns VBox status code.
1655	* @param pVM The cross context VM structure.
1656	* @param enmSwitcher The switcher we're about to use.
1657	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1658	*/
1659	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1660	{
1661	NOREF(pVM);
1662
1663	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1664
1665	*pfVTxDisabled = false;
1666
1667	/* No such issues with AMD-V */
1668	if (!g_HmR0.vmx.fSupported)
1669	return VINF_SUCCESS;
1670
1671	/* Check if the switching we're up to is safe. */
1672	switch (enmSwitcher)
1673	{
1674	case VMMSWITCHER_32_TO_32:
1675	case VMMSWITCHER_PAE_TO_PAE:
1676	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1677
1678	case VMMSWITCHER_32_TO_PAE:
1679	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1680	case VMMSWITCHER_AMD64_TO_32:
1681	case VMMSWITCHER_AMD64_TO_PAE:
1682	break; /* unsafe switchers */
1683
1684	default:
1685	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1686	}
1687
1688	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1689	regardless of whether we're currently using VT-x or not. */
1690	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1691	{
1692	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1693	return VINF_SUCCESS;
1694	}
1695
1696	/** @todo Check if this code is presumptive wrt other VT-x users on the
1697	* system... */
1698
1699	/* Nothing to do if we haven't enabled VT-x. */
1700	if (!g_HmR0.fEnabled)
1701	return VINF_SUCCESS;
1702
1703	/* Local init implies the CPU is currently not in VMX root mode. */
1704	if (!g_HmR0.fGlobalInit)
1705	return VINF_SUCCESS;
1706
1707	/* Ok, disable VT-x. */
1708	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1709	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ && pCpu->pvMemObj && pCpu->HCPhysMemObj != NIL_RTHCPHYS, VERR_HM_IPE_2);
1710
1711	*pfVTxDisabled = true;
1712	return VMXR0DisableCpu(pCpu, pCpu->pvMemObj, pCpu->HCPhysMemObj);
1713	}
1714
1715
1716	/**
1717	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1718	* switcher turned off paging.
1719	*
1720	* @param pVM The cross context VM structure.
1721	* @param fVTxDisabled Whether VT-x was disabled or not.
1722	*/
1723	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1724	{
1725	Assert(!ASMIntAreEnabled());
1726
1727	if (!fVTxDisabled)
1728	return; /* nothing to do */
1729
1730	Assert(g_HmR0.vmx.fSupported);
1731	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1732	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1733	else
1734	{
1735	Assert(g_HmR0.fEnabled);
1736	Assert(g_HmR0.fGlobalInit);
1737
1738	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1739	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ && pCpu->pvMemObj && pCpu->HCPhysMemObj != NIL_RTHCPHYS);
1740
1741	VMXR0EnableCpu(pCpu, pVM, pCpu->pvMemObj, pCpu->HCPhysMemObj, false, &g_HmR0.vmx.Msrs);
1742	}
1743	}
1744
1745	#endif /* VBOX_WITH_RAW_MODE */
1746	#ifdef VBOX_STRICT
1747
1748	/**
1749	* Dumps a descriptor.
1750	*
1751	* @param pDesc Descriptor to dump.
1752	* @param Sel Selector number.
1753	* @param pszMsg Message to prepend the log entry with.
1754	*/
1755	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1756	{
1757	/*
1758	* Make variable description string.
1759	*/
1760	static struct
1761	{
1762	unsigned cch;
1763	const char *psz;
1764	} const s_aTypes[32] =
1765	{
1766	# define STRENTRY(str) { sizeof(str) - 1, str }
1767
1768	/* system */
1769	# if HC_ARCH_BITS == 64
1770	STRENTRY("Reserved0 "), /* 0x00 */
1771	STRENTRY("Reserved1 "), /* 0x01 */
1772	STRENTRY("LDT "), /* 0x02 */
1773	STRENTRY("Reserved3 "), /* 0x03 */
1774	STRENTRY("Reserved4 "), /* 0x04 */
1775	STRENTRY("Reserved5 "), /* 0x05 */
1776	STRENTRY("Reserved6 "), /* 0x06 */
1777	STRENTRY("Reserved7 "), /* 0x07 */
1778	STRENTRY("Reserved8 "), /* 0x08 */
1779	STRENTRY("TSS64Avail "), /* 0x09 */
1780	STRENTRY("ReservedA "), /* 0x0a */
1781	STRENTRY("TSS64Busy "), /* 0x0b */
1782	STRENTRY("Call64 "), /* 0x0c */
1783	STRENTRY("ReservedD "), /* 0x0d */
1784	STRENTRY("Int64 "), /* 0x0e */
1785	STRENTRY("Trap64 "), /* 0x0f */
1786	# else
1787	STRENTRY("Reserved0 "), /* 0x00 */
1788	STRENTRY("TSS16Avail "), /* 0x01 */
1789	STRENTRY("LDT "), /* 0x02 */
1790	STRENTRY("TSS16Busy "), /* 0x03 */
1791	STRENTRY("Call16 "), /* 0x04 */
1792	STRENTRY("Task "), /* 0x05 */
1793	STRENTRY("Int16 "), /* 0x06 */
1794	STRENTRY("Trap16 "), /* 0x07 */
1795	STRENTRY("Reserved8 "), /* 0x08 */
1796	STRENTRY("TSS32Avail "), /* 0x09 */
1797	STRENTRY("ReservedA "), /* 0x0a */
1798	STRENTRY("TSS32Busy "), /* 0x0b */
1799	STRENTRY("Call32 "), /* 0x0c */
1800	STRENTRY("ReservedD "), /* 0x0d */
1801	STRENTRY("Int32 "), /* 0x0e */
1802	STRENTRY("Trap32 "), /* 0x0f */
1803	# endif
1804	/* non system */
1805	STRENTRY("DataRO "), /* 0x10 */
1806	STRENTRY("DataRO Accessed "), /* 0x11 */
1807	STRENTRY("DataRW "), /* 0x12 */
1808	STRENTRY("DataRW Accessed "), /* 0x13 */
1809	STRENTRY("DataDownRO "), /* 0x14 */
1810	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1811	STRENTRY("DataDownRW "), /* 0x16 */
1812	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1813	STRENTRY("CodeEO "), /* 0x18 */
1814	STRENTRY("CodeEO Accessed "), /* 0x19 */
1815	STRENTRY("CodeER "), /* 0x1a */
1816	STRENTRY("CodeER Accessed "), /* 0x1b */
1817	STRENTRY("CodeConfEO "), /* 0x1c */
1818	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1819	STRENTRY("CodeConfER "), /* 0x1e */
1820	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1821	# undef SYSENTRY
1822	};
1823	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1824	char szMsg[128];
1825	char *psz = &szMsg[0];
1826	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1827	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1828	psz += s_aTypes[i].cch;
1829
1830	if (pDesc->Gen.u1Present)
1831	ADD_STR(psz, "Present ");
1832	else
1833	ADD_STR(psz, "Not-Present ");
1834	# if HC_ARCH_BITS == 64
1835	if (pDesc->Gen.u1Long)
1836	ADD_STR(psz, "64-bit ");
1837	else
1838	ADD_STR(psz, "Comp ");
1839	# else
1840	if (pDesc->Gen.u1Granularity)
1841	ADD_STR(psz, "Page ");
1842	if (pDesc->Gen.u1DefBig)
1843	ADD_STR(psz, "32-bit ");
1844	else
1845	ADD_STR(psz, "16-bit ");
1846	# endif
1847	# undef ADD_STR
1848	*psz = '\0';
1849
1850	/*
1851	* Limit and Base and format the output.
1852	*/
1853	#ifdef LOG_ENABLED
1854	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1855
1856	# if HC_ARCH_BITS == 64
1857	uint64_t u32Base = X86DESC64_BASE(pDesc);
1858	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1859	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1860	# else
1861	uint32_t u32Base = X86DESC_BASE(pDesc);
1862	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1863	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1864	# endif
1865	#else
1866	NOREF(Sel); NOREF(pszMsg);
1867	#endif
1868	}
1869
1870
1871	/**
1872	* Formats a full register dump.
1873	*
1874	* @param pVM The cross context VM structure.
1875	* @param pVCpu The cross context virtual CPU structure.
1876	* @param pCtx Pointer to the CPU context.
1877	*/
1878	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1879	{
1880	NOREF(pVM);
1881
1882	/*
1883	* Format the flags.
1884	*/
1885	static struct
1886	{
1887	const char pszSet; const char pszClear; uint32_t fFlag;
1888	} const s_aFlags[] =
1889	{
1890	{ "vip", NULL, X86_EFL_VIP },
1891	{ "vif", NULL, X86_EFL_VIF },
1892	{ "ac", NULL, X86_EFL_AC },
1893	{ "vm", NULL, X86_EFL_VM },
1894	{ "rf", NULL, X86_EFL_RF },
1895	{ "nt", NULL, X86_EFL_NT },
1896	{ "ov", "nv", X86_EFL_OF },
1897	{ "dn", "up", X86_EFL_DF },
1898	{ "ei", "di", X86_EFL_IF },
1899	{ "tf", NULL, X86_EFL_TF },
1900	{ "nt", "pl", X86_EFL_SF },
1901	{ "nz", "zr", X86_EFL_ZF },
1902	{ "ac", "na", X86_EFL_AF },
1903	{ "po", "pe", X86_EFL_PF },
1904	{ "cy", "nc", X86_EFL_CF },
1905	};
1906	char szEFlags[80];
1907	char *psz = szEFlags;
1908	uint32_t uEFlags = pCtx->eflags.u32;
1909	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1910	{
1911	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1912	if (pszAdd)
1913	{
1914	strcpy(psz, pszAdd);
1915	psz += strlen(pszAdd);
1916	*psz++ = ' ';
1917	}
1918	}
1919	psz[-1] = '\0';
1920
1921
1922	/*
1923	* Format the registers.
1924	*/
1925	if (CPUMIsGuestIn64BitCode(pVCpu))
1926	{
1927	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1928	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1929	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1930	"r14=%016RX64 r15=%016RX64\n"
1931	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1932	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1933	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1934	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1935	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1936	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1937	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1938	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1939	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1940	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1941	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1942	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1943	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1944	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1945	,
1946	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1947	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1948	pCtx->r14, pCtx->r15,
1949	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1950	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1951	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1952	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1953	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1954	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1955	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1956	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1957	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1958	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1959	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1960	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1961	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1962	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1963	}
1964	else
1965	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1966	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1967	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1968	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1969	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1970	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1971	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1972	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1973	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1974	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1975	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1976	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1977	,
1978	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1979	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1980	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
1981	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
1982	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
1983	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
1984	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
1985	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
1986	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1987	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1988	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1989	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1990
1991	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1992	Log(("FPU:\n"
1993	"FCW=%04x FSW=%04x FTW=%02x\n"
1994	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1995	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1996	,
1997	pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
1998	pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
1999	pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
2000	pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
2001
2002	Log(("MSR:\n"
2003	"EFER =%016RX64\n"
2004	"PAT =%016RX64\n"
2005	"STAR =%016RX64\n"
2006	"CSTAR =%016RX64\n"
2007	"LSTAR =%016RX64\n"
2008	"SFMASK =%016RX64\n"
2009	"KERNELGSBASE =%016RX64\n",
2010	pCtx->msrEFER,
2011	pCtx->msrPAT,
2012	pCtx->msrSTAR,
2013	pCtx->msrCSTAR,
2014	pCtx->msrLSTAR,
2015	pCtx->msrSFMASK,
2016	pCtx->msrKERNELGSBASE));
2017
2018	NOREF(pFpuCtx);
2019	}
2020
2021	#endif /* VBOX_STRICT */
2022

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 58912

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