HMR0.cpp@ 54201

Last change on this file since 54201 was 54201, checked in by vboxsync, 10 years ago
HostDrivers/Support, VMM: avoid code duplication.
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1	/* $Id: HMR0.cpp 54201 2015-02-13 17:13:28Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2014 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HM
22	#include <VBox/vmm/hm.h>
23	#include <VBox/vmm/pgm.h>
24	#include "HMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/hm_vmx.h>
27	#include <VBox/vmm/hm_svm.h>
28	#include <VBox/err.h>
29	#include <VBox/log.h>
30	#include <iprt/assert.h>
31	#include <iprt/asm.h>
32	#include <iprt/asm-amd64-x86.h>
33	#include <iprt/cpuset.h>
34	#include <iprt/mem.h>
35	#include <iprt/memobj.h>
36	#include <iprt/once.h>
37	#include <iprt/param.h>
38	#include <iprt/power.h>
39	#include <iprt/string.h>
40	#include <iprt/thread.h>
41	#include <iprt/x86.h>
42	#include "HMVMXR0.h"
43	#include "HMSVMR0.h"
44
45
46	/*******************************************************************************
47	* Internal Functions *
48	*******************************************************************************/
49	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
50	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
54	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
55
56
57	/*******************************************************************************
58	* Structures and Typedefs *
59	*******************************************************************************/
60	/**
61	* This is used to manage the status code of a RTMpOnAll in HM.
62	*/
63	typedef struct HMR0FIRSTRC
64	{
65	/** The status code. */
66	int32_t volatile rc;
67	/** The ID of the CPU reporting the first failure. */
68	RTCPUID volatile idCpu;
69	} HMR0FIRSTRC;
70	/** Pointer to a first return code structure. */
71	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
72
73
74	/*******************************************************************************
75	* Global Variables *
76	*******************************************************************************/
77	/**
78	* Global data.
79	*/
80	static struct
81	{
82	/** Per CPU globals. */
83	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
84
85	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
86	* @{ */
87	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu));
88	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
89	DECLR0CALLBACKMEMBER(int, pfnSaveHostState, (PVM pVM, PVMCPU pVCpu));
90	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode, (PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
91	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
92	bool fEnabledByHost, void *pvArg));
93	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
94	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
95	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
96	DECLR0CALLBACKMEMBER(int, pfnSetupVM ,(PVM pVM));
97	/** @} */
98
99	/** Maximum ASID allowed. */
100	uint32_t uMaxAsid;
101
102	/** VT-x data. */
103	struct
104	{
105	/** Set to by us to indicate VMX is supported by the CPU. */
106	bool fSupported;
107	/** Whether we're using SUPR0EnableVTx or not. */
108	bool fUsingSUPR0EnableVTx;
109	/** Whether we're using the preemption timer or not. */
110	bool fUsePreemptTimer;
111	/** The shift mask employed by the VMX-Preemption timer. */
112	uint8_t cPreemptTimerShift;
113
114	/** Host CR4 value (set by ring-0 VMX init) */
115	/** @todo This isn't used for anything relevant. Remove later? */
116	uint64_t u64HostCr4;
117
118	/** Host EFER value (set by ring-0 VMX init) */
119	uint64_t u64HostEfer;
120
121	/** VMX MSR values */
122	VMXMSRS Msrs;
123
124	/* Last instruction error */
125	uint32_t ulLastInstrError;
126	} vmx;
127
128	/** AMD-V information. */
129	struct
130	{
131	/* HWCR MSR (for diagnostics) */
132	uint64_t u64MsrHwcr;
133
134	/** SVM revision. */
135	uint32_t u32Rev;
136
137	/** SVM feature bits from cpuid 0x8000000a */
138	uint32_t u32Features;
139
140	/** Set by us to indicate SVM is supported by the CPU. */
141	bool fSupported;
142	} svm;
143	/** Saved error from detection */
144	int32_t lLastError;
145
146	struct
147	{
148	uint32_t u32AMDFeatureECX;
149	uint32_t u32AMDFeatureEDX;
150	} cpuid;
151
152	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
153	* enabled and disabled each time it's used to execute guest code. */
154	bool fGlobalInit;
155	/** Indicates whether the host is suspending or not. We'll refuse a few
156	* actions when the host is being suspended to speed up the suspending and
157	* avoid trouble. */
158	volatile bool fSuspended;
159
160	/** Whether we've already initialized all CPUs.
161	* @remarks We could check the EnableAllCpusOnce state, but this is
162	* simpler and hopefully easier to understand. */
163	bool fEnabled;
164	/** Serialize initialization in HMR0EnableAllCpus. */
165	RTONCE EnableAllCpusOnce;
166	} g_HvmR0;
167
168
169
170	/**
171	* Initializes a first return code structure.
172	*
173	* @param pFirstRc The structure to init.
174	*/
175	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
176	{
177	pFirstRc->rc = VINF_SUCCESS;
178	pFirstRc->idCpu = NIL_RTCPUID;
179	}
180
181
182	/**
183	* Try set the status code (success ignored).
184	*
185	* @param pFirstRc The first return code structure.
186	* @param rc The status code.
187	*/
188	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
189	{
190	if ( RT_FAILURE(rc)
191	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
192	pFirstRc->idCpu = RTMpCpuId();
193	}
194
195
196	/**
197	* Get the status code of a first return code structure.
198	*
199	* @returns The status code; VINF_SUCCESS or error status, no informational or
200	* warning errors.
201	* @param pFirstRc The first return code structure.
202	*/
203	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
204	{
205	return pFirstRc->rc;
206	}
207
208
209	#ifdef VBOX_STRICT
210	/**
211	* Get the CPU ID on which the failure status code was reported.
212	*
213	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
214	* @param pFirstRc The first return code structure.
215	*/
216	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
217	{
218	return pFirstRc->idCpu;
219	}
220	#endif /* VBOX_STRICT */
221
222
223	/** @name Dummy callback handlers.
224	* @{ */
225
226	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBALCPUINFO pCpu)
227	{
228	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
229	return VINF_SUCCESS;
230	}
231
232	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
233	{
234	NOREF(enmEvent); NOREF(pVCpu); NOREF(fGlobalInit);
235	}
236
237	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
238	bool fEnabledBySystem, void *pvArg)
239	{
240	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem); NOREF(pvArg);
241	return VINF_SUCCESS;
242	}
243
244	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
245	{
246	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
247	return VINF_SUCCESS;
248	}
249
250	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
251	{
252	NOREF(pVM);
253	return VINF_SUCCESS;
254	}
255
256	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
257	{
258	NOREF(pVM);
259	return VINF_SUCCESS;
260	}
261
262	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
263	{
264	NOREF(pVM);
265	return VINF_SUCCESS;
266	}
267
268	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
269	{
270	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
271	return VINF_SUCCESS;
272	}
273
274	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
275	{
276	NOREF(pVM); NOREF(pVCpu);
277	return VINF_SUCCESS;
278	}
279
280	/** @} */
281
282
283	/**
284	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
285	* Down at the Rate Specified" erratum.
286	*
287	* Errata names and related steppings:
288	* - BA86 - D0.
289	* - AAX65 - C2.
290	* - AAU65 - C2, K0.
291	* - AAO95 - B1.
292	* - AAT59 - C2.
293	* - AAK139 - D0.
294	* - AAM126 - C0, C1, D0.
295	* - AAN92 - B1.
296	* - AAJ124 - C0, D0.
297	*
298	* - AAP86 - B1.
299	*
300	* Steppings: B1, C0, C1, C2, D0, K0.
301	*
302	* @returns true if subject to it, false if not.
303	*/
304	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
305	{
306	uint32_t u = ASMCpuId_EAX(1);
307	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
308	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
309	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
310	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
311	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
312	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
313	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
314	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
315	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
316	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
317	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
318	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
319	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
320	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
321	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
322	)
323	return true;
324	return false;
325	}
326
327
328	/**
329	* Intel specific initialization code.
330	*
331	* @returns VBox status code (will only fail if out of memory).
332	*/
333	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
334	{
335	/*
336	* Check that all the required VT-x features are present.
337	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
338	*/
339	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
340	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
341	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
342	)
343	{
344	/** @todo move this into a separate function. */
345	g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
346
347	/*
348	* First try use native kernel API for controlling VT-x.
349	* (This is only supported by some Mac OS X kernels atm.)
350	*/
351	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
352	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
353	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
354	{
355	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
356	if (RT_SUCCESS(rc))
357	{
358	g_HvmR0.vmx.fSupported = true;
359	rc = SUPR0EnableVTx(false /* fEnable */);
360	AssertLogRelRC(rc);
361	}
362	}
363	else
364	{
365	/* We need to check if VT-x has been properly initialized on all
366	CPUs. Some BIOSes do a lousy job. */
367	HMR0FIRSTRC FirstRc;
368	hmR0FirstRcInit(&FirstRc);
369	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
370	if (RT_SUCCESS(g_HvmR0.lLastError))
371	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
372	}
373	if (RT_SUCCESS(g_HvmR0.lLastError))
374	{
375	/* Reread in case it was changed by hmR0InitIntelCpu(). */
376	g_HvmR0.vmx.Msrs.u64FeatureCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
377
378	/*
379	* Read all relevant registers and MSRs.
380	*/
381	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
382	g_HvmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
383	g_HvmR0.vmx.Msrs.u64BasicInfo = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
384	g_HvmR0.vmx.Msrs.VmxPinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
385	g_HvmR0.vmx.Msrs.VmxProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
386	g_HvmR0.vmx.Msrs.VmxExit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
387	g_HvmR0.vmx.Msrs.VmxEntry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
388	g_HvmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
389	g_HvmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
390	g_HvmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
391	g_HvmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
392	g_HvmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
393	g_HvmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
394	/* VPID 16 bits ASID. */
395	g_HvmR0.uMaxAsid = 0x10000; /* exclusive */
396
397	if (g_HvmR0.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
398	{
399	g_HvmR0.vmx.Msrs.VmxProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
400	if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
401	g_HvmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
402
403	if (g_HvmR0.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
404	g_HvmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
405	}
406
407	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
408	{
409	/*
410	* Enter root mode
411	*/
412	RTR0MEMOBJ hScatchMemObj;
413	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
414	if (RT_FAILURE(rc))
415	{
416	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
417	return rc;
418	}
419
420	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
421	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
422	ASMMemZeroPage(pvScatchPage);
423
424	/* Set revision dword at the beginning of the structure. */
425	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.Msrs.u64BasicInfo);
426
427	/* Make sure we don't get rescheduled to another cpu during this probe. */
428	RTCCUINTREG fFlags = ASMIntDisableFlags();
429
430	/*
431	* Check CR4.VMXE
432	*/
433	g_HvmR0.vmx.u64HostCr4 = ASMGetCR4();
434	if (!(g_HvmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
435	{
436	/* In theory this bit could be cleared behind our back. Which would cause
437	#UD faults when we try to execute the VMX instructions... */
438	ASMSetCR4(g_HvmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
439	}
440
441	/*
442	* The only way of checking if we're in VMX root mode or not is to try and enter it.
443	* There is no instruction or control bit that tells us if we're in VMX root mode.
444	* Therefore, try and enter VMX root mode here.
445	*/
446	rc = VMXEnable(HCPhysScratchPage);
447	if (RT_SUCCESS(rc))
448	{
449	g_HvmR0.vmx.fSupported = true;
450	VMXDisable();
451	}
452	else
453	{
454	/*
455	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
456	* it will crash the host when we enter raw mode, because:
457	*
458	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
459	* this bit), and
460	* (b) turning off paging causes a #GP (unavoidable when switching
461	* from long to 32 bits mode or 32 bits to PAE).
462	*
463	* They should fix their code, but until they do we simply refuse to run.
464	*/
465	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
466	Assert(g_HvmR0.vmx.fSupported == false);
467	}
468
469	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
470	if it wasn't so before (some software could incorrectly
471	think it's in VMX mode). */
472	ASMSetCR4(g_HvmR0.vmx.u64HostCr4);
473	ASMSetFlags(fFlags);
474
475	RTR0MemObjFree(hScatchMemObj, false);
476	}
477
478	if (g_HvmR0.vmx.fSupported)
479	{
480	rc = VMXR0GlobalInit();
481	if (RT_FAILURE(rc))
482	g_HvmR0.lLastError = rc;
483
484	/*
485	* Install the VT-x methods.
486	*/
487	g_HvmR0.pfnEnterSession = VMXR0Enter;
488	g_HvmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
489	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
490	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
491	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
492	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
493	g_HvmR0.pfnInitVM = VMXR0InitVM;
494	g_HvmR0.pfnTermVM = VMXR0TermVM;
495	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
496
497	/*
498	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
499	* Timer Does Not Count Down at the Rate Specified" erratum.
500	*/
501	if (g_HvmR0.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
502	{
503	g_HvmR0.vmx.fUsePreemptTimer = true;
504	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.Msrs.u64Misc);
505	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
506	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
507	}
508	}
509	}
510	#ifdef LOG_ENABLED
511	else
512	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
513	#endif
514	}
515	else
516	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
517	return VINF_SUCCESS;
518	}
519
520
521	/**
522	* AMD-specific initialization code.
523	*
524	* @returns VBox status code.
525	*/
526	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
527	{
528	/*
529	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
530	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
531	*/
532	int rc;
533	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
534	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
535	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
536	&& ASMIsValidExtRange(uMaxExtLeaf)
537	&& uMaxExtLeaf >= 0x8000000a
538	)
539	{
540	/* Call the global AMD-V initialization routine. */
541	rc = SVMR0GlobalInit();
542	if (RT_FAILURE(rc))
543	{
544	g_HvmR0.lLastError = rc;
545	return rc;
546	}
547
548	/*
549	* Install the AMD-V methods.
550	*/
551	g_HvmR0.pfnEnterSession = SVMR0Enter;
552	g_HvmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
553	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
554	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
555	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
556	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
557	g_HvmR0.pfnInitVM = SVMR0InitVM;
558	g_HvmR0.pfnTermVM = SVMR0TermVM;
559	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
560
561	/* Query AMD features. */
562	uint32_t u32Dummy;
563	ASMCpuId(0x8000000a, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxAsid, &u32Dummy, &g_HvmR0.svm.u32Features);
564
565	/*
566	* We need to check if AMD-V has been properly initialized on all CPUs.
567	* Some BIOSes might do a poor job.
568	*/
569	HMR0FIRSTRC FirstRc;
570	hmR0FirstRcInit(&FirstRc);
571	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
572	AssertRC(rc);
573	if (RT_SUCCESS(rc))
574	rc = hmR0FirstRcGetStatus(&FirstRc);
575	#ifndef DEBUG_bird
576	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
577	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
578	#endif
579	if (RT_SUCCESS(rc))
580	{
581	/* Read the HWCR MSR for diagnostics. */
582	g_HvmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
583	g_HvmR0.svm.fSupported = true;
584	}
585	else
586	{
587	g_HvmR0.lLastError = rc;
588	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
589	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
590	}
591	}
592	else
593	{
594	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
595	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
596	}
597	return rc;
598	}
599
600
601	/**
602	* Does global Ring-0 HM initialization (at module init).
603	*
604	* @returns VBox status code.
605	*/
606	VMMR0_INT_DECL(int) HMR0Init(void)
607	{
608	/*
609	* Initialize the globals.
610	*/
611	g_HvmR0.fEnabled = false;
612	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
613	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
614	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
615	{
616	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
617	g_HvmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
618	}
619
620	/* Fill in all callbacks with placeholders. */
621	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
622	g_HvmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
623	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
624	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
625	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
626	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
627	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
628	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
629	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
630
631	/* Default is global VT-x/AMD-V init. */
632	g_HvmR0.fGlobalInit = true;
633
634	/*
635	* Make sure aCpuInfo is big enough for all the CPUs on this system.
636	*/
637	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
638	{
639	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
640	return VERR_TOO_MANY_CPUS;
641	}
642
643	/*
644	* Check for VT-x and AMD-V capabilities.
645	*/
646	int rc;
647	if (ASMHasCpuId())
648	{
649	/* Standard features. */
650	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
651	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
652	if (ASMIsValidStdRange(uMaxLeaf))
653	{
654	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
655	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
656
657	/* Query AMD features. */
658	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
659	if (ASMIsValidExtRange(uMaxExtLeaf))
660	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
661	&g_HvmR0.cpuid.u32AMDFeatureECX,
662	&g_HvmR0.cpuid.u32AMDFeatureEDX);
663	else
664	g_HvmR0.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureEDX = 0;
665
666	/* Go to CPU specific initialization code. */
667	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
668	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
669	{
670	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
671	if (RT_FAILURE(rc))
672	return rc;
673	}
674	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
675	{
676	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
677	if (RT_FAILURE(rc))
678	return rc;
679	}
680	else
681	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
682	}
683	else
684	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
685	}
686	else
687	g_HvmR0.lLastError = VERR_HM_NO_CPUID;
688
689	/*
690	* Register notification callbacks that we can use to disable/enable CPUs
691	* when brought offline/online or suspending/resuming.
692	*/
693	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
694	{
695	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
696	AssertRC(rc);
697
698	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
699	AssertRC(rc);
700	}
701
702	/* We return success here because module init shall not fail if HM
703	fails to initialize. */
704	return VINF_SUCCESS;
705	}
706
707
708	/**
709	* Does global Ring-0 HM termination (at module termination).
710	*
711	* @returns VBox status code.
712	*/
713	VMMR0_INT_DECL(int) HMR0Term(void)
714	{
715	int rc;
716	if ( g_HvmR0.vmx.fSupported
717	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
718	{
719	/*
720	* Simple if the host OS manages VT-x.
721	*/
722	Assert(g_HvmR0.fGlobalInit);
723	rc = SUPR0EnableVTx(false /* fEnable */);
724
725	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
726	{
727	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
728	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
729	}
730	}
731	else
732	{
733	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
734	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
735	{
736	/* Doesn't really matter if this fails. */
737	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
738	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
739	}
740	else
741	rc = VINF_SUCCESS;
742
743	/*
744	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
745	*/
746	if (g_HvmR0.fGlobalInit)
747	{
748	HMR0FIRSTRC FirstRc;
749	hmR0FirstRcInit(&FirstRc);
750	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
751	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
752	if (RT_SUCCESS(rc))
753	{
754	rc = hmR0FirstRcGetStatus(&FirstRc);
755	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
756	}
757	}
758
759	/*
760	* Free the per-cpu pages used for VT-x and AMD-V.
761	*/
762	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
763	{
764	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
765	{
766	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
767	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
768	}
769	}
770	}
771
772	/** @todo This needs cleaning up. There's no matching
773	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
774	* should move into their respective modules. */
775	/* Finally, call global VT-x/AMD-V termination. */
776	if (g_HvmR0.vmx.fSupported)
777	VMXR0GlobalTerm();
778	else if (g_HvmR0.svm.fSupported)
779	SVMR0GlobalTerm();
780
781	return rc;
782	}
783
784
785	/**
786	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
787	* on a CPU.
788	*
789	* @param idCpu The identifier for the CPU the function is called on.
790	* @param pvUser1 Pointer to the first RC structure.
791	* @param pvUser2 Ignored.
792	*/
793	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
794	{
795	/** @todo Unify code with SUPR0QueryVTCaps(). */
796	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
797	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
798	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
799	NOREF(idCpu); NOREF(pvUser2);
800
801	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
802	hmR0FirstRcSetStatus(pFirstRc, rc);
803	}
804
805
806	/**
807	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
808	* on a CPU.
809	*
810	* @param idCpu The identifier for the CPU the function is called on.
811	* @param pvUser1 Pointer to the first RC structure.
812	* @param pvUser2 Ignored.
813	*/
814	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
815	{
816	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
817	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
818	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
819	NOREF(idCpu); NOREF(pvUser2);
820
821	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
822	hmR0FirstRcSetStatus(pFirstRc, rc);
823	}
824
825
826	/**
827	* Enable VT-x or AMD-V on the current CPU
828	*
829	* @returns VBox status code.
830	* @param pVM Pointer to the VM (can be NULL).
831	* @param idCpu The identifier for the CPU the function is called on.
832	*
833	* @remarks Maybe called with interrupts disabled!
834	*/
835	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
836	{
837	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
838
839	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
840	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
841	Assert(!pCpu->fConfigured);
842	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
843
844	pCpu->idCpu = idCpu;
845	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
846
847	int rc;
848	if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
849	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HvmR0.vmx.Msrs);
850	else
851	{
852	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
853	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
854	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0 /* iPage */);
855
856	if (g_HvmR0.vmx.fSupported)
857	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
858	else
859	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, NULL /* pvArg */);
860	}
861	AssertRC(rc);
862	if (RT_SUCCESS(rc))
863	pCpu->fConfigured = true;
864
865	return rc;
866	}
867
868
869	/**
870	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
871	*
872	* @param idCpu The identifier for the CPU the function is called on.
873	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
874	* @param pvUser2 The 2nd user argument.
875	*/
876	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
877	{
878	PVM pVM = (PVM)pvUser1; /* can be NULL! */
879	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
880	AssertReturnVoid(g_HvmR0.fGlobalInit);
881	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
882	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
883	}
884
885
886	/**
887	* RTOnce callback employed by HMR0EnableAllCpus.
888	*
889	* @returns VBox status code.
890	* @param pvUser Pointer to the VM.
891	* @param pvUserIgnore NULL, ignored.
892	*/
893	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
894	{
895	PVM pVM = (PVM)pvUser;
896
897	/*
898	* Indicate that we've initialized.
899	*
900	* Note! There is a potential race between this function and the suspend
901	* notification. Kind of unlikely though, so ignored for now.
902	*/
903	AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
904	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
905
906	/*
907	* The global init variable is set by the first VM.
908	*/
909	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
910
911	#ifdef VBOX_STRICT
912	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
913	{
914	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
915	Assert(!g_HvmR0.aCpuInfo[i].fConfigured);
916	Assert(!g_HvmR0.aCpuInfo[i].cTlbFlushes);
917	Assert(!g_HvmR0.aCpuInfo[i].uCurrentAsid);
918	}
919	#endif
920
921	int rc;
922	if ( g_HvmR0.vmx.fSupported
923	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
924	{
925	/*
926	* Global VT-x initialization API (only darwin for now).
927	*/
928	rc = SUPR0EnableVTx(true /* fEnable */);
929	if (RT_SUCCESS(rc))
930	{
931	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
932	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
933	}
934	else
935	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
936	}
937	else
938	{
939	/*
940	* We're doing the job ourselves.
941	*/
942	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
943	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
944	{
945	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
946
947	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
948	{
949	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
950	AssertLogRelRCReturn(rc, rc);
951
952	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
953	ASMMemZeroPage(pvR0);
954	}
955	}
956
957	rc = VINF_SUCCESS;
958	}
959
960	if ( RT_SUCCESS(rc)
961	&& g_HvmR0.fGlobalInit)
962	{
963	/* First time, so initialize each cpu/core. */
964	HMR0FIRSTRC FirstRc;
965	hmR0FirstRcInit(&FirstRc);
966	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
967	if (RT_SUCCESS(rc))
968	rc = hmR0FirstRcGetStatus(&FirstRc);
969	AssertMsgRC(rc, ("hmR0EnableAllCpuOnce failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
970	}
971
972	return rc;
973	}
974
975
976	/**
977	* Sets up HM on all cpus.
978	*
979	* @returns VBox status code.
980	* @param pVM Pointer to the VM.
981	*/
982	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
983	{
984	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
985	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
986	return VERR_HM_SUSPEND_PENDING;
987
988	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
989	}
990
991
992	/**
993	* Disable VT-x or AMD-V on the current CPU.
994	*
995	* @returns VBox status code.
996	* @param idCpu The identifier for the CPU the function is called on.
997	*
998	* @remarks Must be called with preemption disabled.
999	*/
1000	static int hmR0DisableCpu(RTCPUID idCpu)
1001	{
1002	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1003
1004	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1005	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1006	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
1007	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1008	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1009
1010	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1011	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1012
1013	int rc;
1014	if (pCpu->fConfigured)
1015	{
1016	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1017	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1018
1019	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1020	AssertRCReturn(rc, rc);
1021
1022	pCpu->fConfigured = false;
1023	pCpu->idCpu = NIL_RTCPUID;
1024	}
1025	else
1026	rc = VINF_SUCCESS; /* nothing to do */
1027
1028	return rc;
1029	}
1030
1031
1032	/**
1033	* Worker function passed to RTMpOnAll() that is to be called on the target
1034	* CPUs.
1035	*
1036	* @param idCpu The identifier for the CPU the function is called on.
1037	* @param pvUser1 The 1st user argument.
1038	* @param pvUser2 Opaque pointer to the FirstRc.
1039	*/
1040	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1041	{
1042	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1043	AssertReturnVoid(g_HvmR0.fGlobalInit);
1044	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1045	}
1046
1047
1048	/**
1049	* Callback function invoked when a cpu goes online or offline.
1050	*
1051	* @param enmEvent The Mp event.
1052	* @param idCpu The identifier for the CPU the function is called on.
1053	* @param pvData Opaque data (PVM pointer).
1054	*/
1055	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1056	{
1057	NOREF(pvData);
1058
1059	/*
1060	* We only care about uninitializing a CPU that is going offline. When a
1061	* CPU comes online, the initialization is done lazily in HMR0Enter().
1062	*/
1063	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1064	switch (enmEvent)
1065	{
1066	case RTMPEVENT_OFFLINE:
1067	{
1068	int rc = hmR0DisableCpu(idCpu);
1069	AssertRC(rc);
1070	break;
1071	}
1072
1073	default:
1074	break;
1075	}
1076	}
1077
1078
1079	/**
1080	* Called whenever a system power state change occurs.
1081	*
1082	* @param enmEvent The Power event.
1083	* @param pvUser User argument.
1084	*/
1085	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1086	{
1087	NOREF(pvUser);
1088	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1089
1090	#ifdef LOG_ENABLED
1091	if (enmEvent == RTPOWEREVENT_SUSPEND)
1092	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1093	else
1094	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1095	#endif
1096
1097	if (enmEvent == RTPOWEREVENT_SUSPEND)
1098	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1099
1100	if (g_HvmR0.fEnabled)
1101	{
1102	int rc;
1103	HMR0FIRSTRC FirstRc;
1104	hmR0FirstRcInit(&FirstRc);
1105
1106	if (enmEvent == RTPOWEREVENT_SUSPEND)
1107	{
1108	if (g_HvmR0.fGlobalInit)
1109	{
1110	/* Turn off VT-x or AMD-V on all CPUs. */
1111	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1112	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1113	}
1114	/* else nothing to do here for the local init case */
1115	}
1116	else
1117	{
1118	/* Reinit the CPUs from scratch as the suspend state might have
1119	messed with the MSRs. (lousy BIOSes as usual) */
1120	if (g_HvmR0.vmx.fSupported)
1121	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1122	else
1123	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1124	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1125	if (RT_SUCCESS(rc))
1126	rc = hmR0FirstRcGetStatus(&FirstRc);
1127	#ifdef LOG_ENABLED
1128	if (RT_FAILURE(rc))
1129	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1130	#endif
1131	if (g_HvmR0.fGlobalInit)
1132	{
1133	/* Turn VT-x or AMD-V back on on all CPUs. */
1134	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1135	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1136	}
1137	/* else nothing to do here for the local init case */
1138	}
1139	}
1140
1141	if (enmEvent == RTPOWEREVENT_RESUME)
1142	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1143	}
1144
1145
1146	/**
1147	* Does ring-0 per-VM HM initialization.
1148	*
1149	* This will copy HM global into the VM structure and call the CPU specific
1150	* init routine which will allocate resources for each virtual CPU and such.
1151	*
1152	* @returns VBox status code.
1153	* @param pVM Pointer to the VM.
1154	*
1155	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1156	* vmR3InitRing3().
1157	*/
1158	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1159	{
1160	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1161
1162	#ifdef LOG_ENABLED
1163	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1164	#endif
1165
1166	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1167	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1168	return VERR_HM_SUSPEND_PENDING;
1169
1170	/*
1171	* Copy globals to the VM structure.
1172	*/
1173	pVM->hm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1174	pVM->hm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1175
1176	pVM->hm.s.vmx.fUsePreemptTimer &= g_HvmR0.vmx.fUsePreemptTimer; /* Can be overridden by CFGM. See HMR3Init(). */
1177	pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1178	pVM->hm.s.vmx.u64HostCr4 = g_HvmR0.vmx.u64HostCr4;
1179	pVM->hm.s.vmx.u64HostEfer = g_HvmR0.vmx.u64HostEfer;
1180	pVM->hm.s.vmx.Msrs = g_HvmR0.vmx.Msrs;
1181	pVM->hm.s.svm.u64MsrHwcr = g_HvmR0.svm.u64MsrHwcr;
1182	pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1183	pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1184	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1185	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1186	pVM->hm.s.lLastError = g_HvmR0.lLastError;
1187
1188	pVM->hm.s.uMaxAsid = g_HvmR0.uMaxAsid;
1189
1190
1191	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1192	{
1193	pVM->hm.s.cMaxResumeLoops = 1024;
1194	if (RTThreadPreemptIsPendingTrusty())
1195	pVM->hm.s.cMaxResumeLoops = 8192;
1196	}
1197
1198	/*
1199	* Initialize some per CPU fields.
1200	*/
1201	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1202	{
1203	PVMCPU pVCpu = &pVM->aCpus[i];
1204	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1205	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1206
1207	/* We'll aways increment this the first time (host uses ASID 0). */
1208	AssertReturn(!pVCpu->hm.s.uCurrentAsid, VERR_HM_IPE_3);
1209	}
1210
1211	pVM->hm.s.uHostKernelFeatures = SUPR0GetKernelFeatures();
1212
1213	/*
1214	* Call the hardware specific initialization method.
1215	*/
1216	return g_HvmR0.pfnInitVM(pVM);
1217	}
1218
1219
1220	/**
1221	* Does ring-0 per VM HM termination.
1222	*
1223	* @returns VBox status code.
1224	* @param pVM Pointer to the VM.
1225	*/
1226	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1227	{
1228	Log(("HMR0TermVM: %p\n", pVM));
1229	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1230
1231	/*
1232	* Call the hardware specific method.
1233	*
1234	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1235	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1236	*/
1237	return g_HvmR0.pfnTermVM(pVM);
1238	}
1239
1240
1241	/**
1242	* Sets up a VT-x or AMD-V session.
1243	*
1244	* This is mostly about setting up the hardware VM state.
1245	*
1246	* @returns VBox status code.
1247	* @param pVM Pointer to the VM.
1248	*/
1249	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1250	{
1251	Log(("HMR0SetupVM: %p\n", pVM));
1252	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1253
1254	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1255	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1256
1257	/* On first entry we'll sync everything. */
1258	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1259	HMCPU_CF_RESET_TO(&pVM->aCpus[i], HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1260
1261	/*
1262	* Call the hardware specific setup VM method. This requires the CPU to be
1263	* enabled for AMD-V/VT-x and preemption to be prevented.
1264	*/
1265	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1266	RTThreadPreemptDisable(&PreemptState);
1267	RTCPUID idCpu = RTMpCpuId();
1268
1269	/* Enable VT-x or AMD-V if local init is required. */
1270	int rc;
1271	if (!g_HvmR0.fGlobalInit)
1272	{
1273	rc = hmR0EnableCpu(pVM, idCpu);
1274	AssertRCReturnStmt(rc, RTThreadPreemptRestore(&PreemptState), rc);
1275	}
1276
1277	/* Setup VT-x or AMD-V. */
1278	rc = g_HvmR0.pfnSetupVM(pVM);
1279
1280	/* Disable VT-x or AMD-V if local init was done before. */
1281	if (!g_HvmR0.fGlobalInit)
1282	{
1283	int rc2 = hmR0DisableCpu(idCpu);
1284	AssertRC(rc2);
1285	}
1286
1287	RTThreadPreemptRestore(&PreemptState);
1288	return rc;
1289	}
1290
1291
1292	/**
1293	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1294	* required for entering HM context.
1295	*
1296	* @returns VBox status code.
1297	* @param pvCpu Pointer to the VMCPU.
1298	*
1299	* @remarks No-long-jump zone!!!
1300	*/
1301	VMMR0_INT_DECL(int) HMR0EnterCpu(PVMCPU pVCpu)
1302	{
1303	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1304
1305	int rc = VINF_SUCCESS;
1306	RTCPUID idCpu = RTMpCpuId();
1307	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1308	AssertPtr(pCpu);
1309
1310	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1311	if (!pCpu->fConfigured)
1312	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1313
1314	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1315	HMCPU_CF_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE);
1316
1317	Assert(pCpu->idCpu == idCpu && pCpu->idCpu != NIL_RTCPUID);
1318	pVCpu->hm.s.idEnteredCpu = idCpu;
1319	return rc;
1320	}
1321
1322
1323	/**
1324	* Enters the VT-x or AMD-V session.
1325	*
1326	* @returns VBox status code.
1327	* @param pVM Pointer to the VM.
1328	* @param pVCpu Pointer to the VMCPU.
1329	*
1330	* @remarks This is called with preemption disabled.
1331	*/
1332	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1333	{
1334	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1335	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1336	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1337
1338	/* Load the bare minimum state required for entering HM. */
1339	int rc = HMR0EnterCpu(pVCpu);
1340	AssertRCReturn(rc, rc);
1341
1342	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1343	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_5);
1344	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1345	#endif
1346
1347	RTCPUID idCpu = RTMpCpuId();
1348	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1349	Assert(pCpu);
1350	Assert(HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_HOST_GUEST_SHARED_STATE));
1351
1352	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1353	AssertMsgRCReturn(rc, ("pfnEnterSession failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1354
1355	/* Load the host-state as we may be resuming code after a longjmp and quite
1356	possibly now be scheduled on a different CPU. */
1357	rc = g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1358	AssertMsgRCReturn(rc, ("pfnSaveHostState failed. rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1359
1360	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1361	if (fStartedSet)
1362	PGMRZDynMapReleaseAutoSet(pVCpu);
1363	#endif
1364
1365	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1366	if (RT_FAILURE(rc))
1367	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1368	return rc;
1369	}
1370
1371
1372	/**
1373	* Deinitializes the bare minimum state used for HM context and if necessary
1374	* disable HM on the CPU.
1375	*
1376	* @returns VBox status code.
1377	* @param pVCpu Pointer to the VMCPU.
1378	*
1379	* @remarks No-long-jump zone!!!
1380	*/
1381	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1382	{
1383	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1384	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1385
1386	RTCPUID idCpu = RTMpCpuId();
1387	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1388
1389	if ( !g_HvmR0.fGlobalInit
1390	&& pCpu->fConfigured)
1391	{
1392	int rc = hmR0DisableCpu(idCpu);
1393	AssertRCReturn(rc, rc);
1394	Assert(!pCpu->fConfigured);
1395	Assert(pCpu->idCpu == NIL_RTCPUID);
1396
1397	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1398	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1399	}
1400
1401	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1402	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1403
1404	/* Clear the VCPU <-> host CPU mapping as we've left HM context. */
1405	ASMAtomicWriteU32(&pVCpu->idHostCpu, NIL_RTCPUID);
1406
1407	return VINF_SUCCESS;
1408	}
1409
1410
1411	/**
1412	* Thread-context hook for HM.
1413	*
1414	* @param enmEvent The thread-context event.
1415	* @param pvUser Opaque pointer to the VMCPU.
1416	*/
1417	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1418	{
1419	PVMCPU pVCpu = (PVMCPU)pvUser;
1420	Assert(pVCpu);
1421	Assert(g_HvmR0.pfnThreadCtxCallback);
1422
1423	g_HvmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HvmR0.fGlobalInit);
1424	}
1425
1426
1427	/**
1428	* Runs guest code in a hardware accelerated VM.
1429	*
1430	* @returns VBox status code.
1431	* @param pVM Pointer to the VM.
1432	* @param pVCpu Pointer to the VMCPU.
1433	*
1434	* @remarks Can be called with preemption enabled if thread-context hooks are
1435	* used!!!
1436	*/
1437	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1438	{
1439	#ifdef VBOX_STRICT
1440	/* With thread-context hooks we would be running this code with preemption enabled. */
1441	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1442	{
1443	PHMGLOBALCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1444	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1445	Assert(pCpu->fConfigured);
1446	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1447	}
1448	#endif
1449
1450	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1451	AssertReturn(!VMMR0ThreadCtxHooksAreRegistered(pVCpu), VERR_HM_IPE_4);
1452	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1453	PGMRZDynMapStartAutoSet(pVCpu);
1454	#endif
1455
1456	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1457
1458	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1459	PGMRZDynMapReleaseAutoSet(pVCpu);
1460	#endif
1461	return rc;
1462	}
1463
1464	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1465
1466	/**
1467	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1468	*
1469	* @returns VBox status code.
1470	* @param pVM Pointer to the VM.
1471	* @param pVCpu Pointer to the VMCPU.
1472	* @param pCtx Pointer to the guest CPU context.
1473	*/
1474	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1475	{
1476	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1477	if (pVM->hm.s.vmx.fSupported)
1478	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1479	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1480	}
1481
1482
1483	/**
1484	* Save guest debug state (64 bits guest mode & 32 bits host only)
1485	*
1486	* @returns VBox status code.
1487	* @param pVM Pointer to the VM.
1488	* @param pVCpu Pointer to the VMCPU.
1489	* @param pCtx Pointer to the guest CPU context.
1490	*/
1491	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1492	{
1493	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1494	if (pVM->hm.s.vmx.fSupported)
1495	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1496	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1497	}
1498
1499
1500	/**
1501	* Test the 32->64 bits switcher.
1502	*
1503	* @returns VBox status code.
1504	* @param pVM Pointer to the VM.
1505	*/
1506	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1507	{
1508	PVMCPU pVCpu = &pVM->aCpus[0];
1509	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1510	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1511	int rc;
1512
1513	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1514	if (pVM->hm.s.vmx.fSupported)
1515	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1516	else
1517	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1518	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1519
1520	return rc;
1521	}
1522
1523	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1524
1525	/**
1526	* Returns suspend status of the host.
1527	*
1528	* @returns Suspend pending or not.
1529	*/
1530	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1531	{
1532	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1533	}
1534
1535
1536	/**
1537	* Returns the cpu structure for the current cpu.
1538	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1539	*
1540	* @returns The cpu structure pointer.
1541	*/
1542	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void)
1543	{
1544	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1545	RTCPUID idCpu = RTMpCpuId();
1546	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1547	return &g_HvmR0.aCpuInfo[idCpu];
1548	}
1549
1550
1551	/**
1552	* Returns the cpu structure for the current cpu.
1553	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1554	*
1555	* @returns The cpu structure pointer.
1556	* @param idCpu id of the VCPU.
1557	*/
1558	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1559	{
1560	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1561	return &g_HvmR0.aCpuInfo[idCpu];
1562	}
1563
1564
1565	/**
1566	* Save a pending IO read.
1567	*
1568	* @param pVCpu Pointer to the VMCPU.
1569	* @param GCPtrRip Address of IO instruction.
1570	* @param GCPtrRipNext Address of the next instruction.
1571	* @param uPort Port address.
1572	* @param uAndVal AND mask for saving the result in eax.
1573	* @param cbSize Read size.
1574	*/
1575	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1576	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1577	{
1578	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1579	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1580	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1581	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1582	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1583	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1584	return;
1585	}
1586
1587
1588	/**
1589	* Save a pending IO write.
1590	*
1591	* @param pVCpu Pointer to the VMCPU.
1592	* @param GCPtrRIP Address of IO instruction.
1593	* @param uPort Port address.
1594	* @param uAndVal AND mask for fetching the result from eax.
1595	* @param cbSize Read size.
1596	*/
1597	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1598	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1599	{
1600	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1601	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1602	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1603	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1604	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1605	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1606	return;
1607	}
1608
1609
1610	/**
1611	* Raw-mode switcher hook - disable VT-x if it's active and the current
1612	* switcher turns off paging.
1613	*
1614	* @returns VBox status code.
1615	* @param pVM Pointer to the VM.
1616	* @param enmSwitcher The switcher we're about to use.
1617	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1618	*/
1619	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1620	{
1621	NOREF(pVM);
1622
1623	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1624
1625	*pfVTxDisabled = false;
1626
1627	/* No such issues with AMD-V */
1628	if (!g_HvmR0.vmx.fSupported)
1629	return VINF_SUCCESS;
1630
1631	/* Check if the swithcing we're up to is safe. */
1632	switch (enmSwitcher)
1633	{
1634	case VMMSWITCHER_32_TO_32:
1635	case VMMSWITCHER_PAE_TO_PAE:
1636	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1637
1638	case VMMSWITCHER_32_TO_PAE:
1639	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1640	case VMMSWITCHER_AMD64_TO_32:
1641	case VMMSWITCHER_AMD64_TO_PAE:
1642	break; /* unsafe switchers */
1643
1644	default:
1645	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1646	}
1647
1648	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1649	regardless of whether we're currently using VT-x or not. */
1650	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1651	{
1652	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1653	return VINF_SUCCESS;
1654	}
1655
1656	/** @todo Check if this code is presumtive wrt other VT-x users on the
1657	* system... */
1658
1659	/* Nothing to do if we haven't enabled VT-x. */
1660	if (!g_HvmR0.fEnabled)
1661	return VINF_SUCCESS;
1662
1663	/* Local init implies the CPU is currently not in VMX root mode. */
1664	if (!g_HvmR0.fGlobalInit)
1665	return VINF_SUCCESS;
1666
1667	/* Ok, disable VT-x. */
1668	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1669	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1670
1671	*pfVTxDisabled = true;
1672	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1673	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1674	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1675	}
1676
1677
1678	/**
1679	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1680	* switcher turned off paging.
1681	*
1682	* @param pVM Pointer to the VM.
1683	* @param fVTxDisabled Whether VT-x was disabled or not.
1684	*/
1685	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1686	{
1687	Assert(!ASMIntAreEnabled());
1688
1689	if (!fVTxDisabled)
1690	return; /* nothing to do */
1691
1692	Assert(g_HvmR0.vmx.fSupported);
1693	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1694	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1695	else
1696	{
1697	Assert(g_HvmR0.fEnabled);
1698	Assert(g_HvmR0.fGlobalInit);
1699
1700	PHMGLOBALCPUINFO pCpu = HMR0GetCurrentCpu();
1701	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1702
1703	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1704	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1705	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false, &g_HvmR0.vmx.Msrs);
1706	}
1707	}
1708
1709	#ifdef VBOX_STRICT
1710
1711	/**
1712	* Dumps a descriptor.
1713	*
1714	* @param pDesc Descriptor to dump.
1715	* @param Sel Selector number.
1716	* @param pszMsg Message to prepend the log entry with.
1717	*/
1718	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1719	{
1720	/*
1721	* Make variable description string.
1722	*/
1723	static struct
1724	{
1725	unsigned cch;
1726	const char *psz;
1727	} const s_aTypes[32] =
1728	{
1729	# define STRENTRY(str) { sizeof(str) - 1, str }
1730
1731	/* system */
1732	# if HC_ARCH_BITS == 64
1733	STRENTRY("Reserved0 "), /* 0x00 */
1734	STRENTRY("Reserved1 "), /* 0x01 */
1735	STRENTRY("LDT "), /* 0x02 */
1736	STRENTRY("Reserved3 "), /* 0x03 */
1737	STRENTRY("Reserved4 "), /* 0x04 */
1738	STRENTRY("Reserved5 "), /* 0x05 */
1739	STRENTRY("Reserved6 "), /* 0x06 */
1740	STRENTRY("Reserved7 "), /* 0x07 */
1741	STRENTRY("Reserved8 "), /* 0x08 */
1742	STRENTRY("TSS64Avail "), /* 0x09 */
1743	STRENTRY("ReservedA "), /* 0x0a */
1744	STRENTRY("TSS64Busy "), /* 0x0b */
1745	STRENTRY("Call64 "), /* 0x0c */
1746	STRENTRY("ReservedD "), /* 0x0d */
1747	STRENTRY("Int64 "), /* 0x0e */
1748	STRENTRY("Trap64 "), /* 0x0f */
1749	# else
1750	STRENTRY("Reserved0 "), /* 0x00 */
1751	STRENTRY("TSS16Avail "), /* 0x01 */
1752	STRENTRY("LDT "), /* 0x02 */
1753	STRENTRY("TSS16Busy "), /* 0x03 */
1754	STRENTRY("Call16 "), /* 0x04 */
1755	STRENTRY("Task "), /* 0x05 */
1756	STRENTRY("Int16 "), /* 0x06 */
1757	STRENTRY("Trap16 "), /* 0x07 */
1758	STRENTRY("Reserved8 "), /* 0x08 */
1759	STRENTRY("TSS32Avail "), /* 0x09 */
1760	STRENTRY("ReservedA "), /* 0x0a */
1761	STRENTRY("TSS32Busy "), /* 0x0b */
1762	STRENTRY("Call32 "), /* 0x0c */
1763	STRENTRY("ReservedD "), /* 0x0d */
1764	STRENTRY("Int32 "), /* 0x0e */
1765	STRENTRY("Trap32 "), /* 0x0f */
1766	# endif
1767	/* non system */
1768	STRENTRY("DataRO "), /* 0x10 */
1769	STRENTRY("DataRO Accessed "), /* 0x11 */
1770	STRENTRY("DataRW "), /* 0x12 */
1771	STRENTRY("DataRW Accessed "), /* 0x13 */
1772	STRENTRY("DataDownRO "), /* 0x14 */
1773	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1774	STRENTRY("DataDownRW "), /* 0x16 */
1775	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1776	STRENTRY("CodeEO "), /* 0x18 */
1777	STRENTRY("CodeEO Accessed "), /* 0x19 */
1778	STRENTRY("CodeER "), /* 0x1a */
1779	STRENTRY("CodeER Accessed "), /* 0x1b */
1780	STRENTRY("CodeConfEO "), /* 0x1c */
1781	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1782	STRENTRY("CodeConfER "), /* 0x1e */
1783	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1784	# undef SYSENTRY
1785	};
1786	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1787	char szMsg[128];
1788	char *psz = &szMsg[0];
1789	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1790	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1791	psz += s_aTypes[i].cch;
1792
1793	if (pDesc->Gen.u1Present)
1794	ADD_STR(psz, "Present ");
1795	else
1796	ADD_STR(psz, "Not-Present ");
1797	# if HC_ARCH_BITS == 64
1798	if (pDesc->Gen.u1Long)
1799	ADD_STR(psz, "64-bit ");
1800	else
1801	ADD_STR(psz, "Comp ");
1802	# else
1803	if (pDesc->Gen.u1Granularity)
1804	ADD_STR(psz, "Page ");
1805	if (pDesc->Gen.u1DefBig)
1806	ADD_STR(psz, "32-bit ");
1807	else
1808	ADD_STR(psz, "16-bit ");
1809	# endif
1810	# undef ADD_STR
1811	*psz = '\0';
1812
1813	/*
1814	* Limit and Base and format the output.
1815	*/
1816	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1817
1818	# if HC_ARCH_BITS == 64
1819	uint64_t u32Base = X86DESC64_BASE(pDesc);
1820	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1821	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1822	# else
1823	uint32_t u32Base = X86DESC_BASE(pDesc);
1824	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1825	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1826	# endif
1827	}
1828
1829
1830	/**
1831	* Formats a full register dump.
1832	*
1833	* @param pVM Pointer to the VM.
1834	* @param pVCpu Pointer to the VMCPU.
1835	* @param pCtx Pointer to the CPU context.
1836	*/
1837	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1838	{
1839	NOREF(pVM);
1840
1841	/*
1842	* Format the flags.
1843	*/
1844	static struct
1845	{
1846	const char pszSet; const char pszClear; uint32_t fFlag;
1847	} const s_aFlags[] =
1848	{
1849	{ "vip", NULL, X86_EFL_VIP },
1850	{ "vif", NULL, X86_EFL_VIF },
1851	{ "ac", NULL, X86_EFL_AC },
1852	{ "vm", NULL, X86_EFL_VM },
1853	{ "rf", NULL, X86_EFL_RF },
1854	{ "nt", NULL, X86_EFL_NT },
1855	{ "ov", "nv", X86_EFL_OF },
1856	{ "dn", "up", X86_EFL_DF },
1857	{ "ei", "di", X86_EFL_IF },
1858	{ "tf", NULL, X86_EFL_TF },
1859	{ "nt", "pl", X86_EFL_SF },
1860	{ "nz", "zr", X86_EFL_ZF },
1861	{ "ac", "na", X86_EFL_AF },
1862	{ "po", "pe", X86_EFL_PF },
1863	{ "cy", "nc", X86_EFL_CF },
1864	};
1865	char szEFlags[80];
1866	char *psz = szEFlags;
1867	uint32_t uEFlags = pCtx->eflags.u32;
1868	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1869	{
1870	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1871	if (pszAdd)
1872	{
1873	strcpy(psz, pszAdd);
1874	psz += strlen(pszAdd);
1875	*psz++ = ' ';
1876	}
1877	}
1878	psz[-1] = '\0';
1879
1880
1881	/*
1882	* Format the registers.
1883	*/
1884	if (CPUMIsGuestIn64BitCode(pVCpu))
1885	{
1886	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1887	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1888	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1889	"r14=%016RX64 r15=%016RX64\n"
1890	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1891	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1892	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1893	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1894	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1895	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1896	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1897	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1898	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1899	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1900	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1901	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1902	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1903	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1904	,
1905	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1906	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1907	pCtx->r14, pCtx->r15,
1908	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1909	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1910	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1911	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1912	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1913	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1914	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1915	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1916	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1917	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1918	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1919	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1920	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1921	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1922	}
1923	else
1924	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1925	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1926	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1927	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1928	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1929	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1930	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1931	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1932	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1933	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1934	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1935	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1936	,
1937	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1938	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
1939	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
1940	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
1941	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
1942	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
1943	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
1944	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
1945	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
1946	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1947	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1948	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1949
1950	Log(("FPU:\n"
1951	"FCW=%04x FSW=%04x FTW=%02x\n"
1952	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1953	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1954	,
1955	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
1956	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
1957	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
1958	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
1959
1960	Log(("MSR:\n"
1961	"EFER =%016RX64\n"
1962	"PAT =%016RX64\n"
1963	"STAR =%016RX64\n"
1964	"CSTAR =%016RX64\n"
1965	"LSTAR =%016RX64\n"
1966	"SFMASK =%016RX64\n"
1967	"KERNELGSBASE =%016RX64\n",
1968	pCtx->msrEFER,
1969	pCtx->msrPAT,
1970	pCtx->msrSTAR,
1971	pCtx->msrCSTAR,
1972	pCtx->msrLSTAR,
1973	pCtx->msrSFMASK,
1974	pCtx->msrKERNELGSBASE));
1975	}
1976
1977	#endif /* VBOX_STRICT */
1978

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 54201

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