HMR0.cpp@ 47565

Last change on this file since 47565 was 47472, checked in by vboxsync, 11 years ago
VMM/VMMR0: HW(VMX\|SVM)R0.h -> HM(VMX\|SVM)R0.h. Now that the refactor is done.
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File size: 74.5 KB

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1	/* $Id: HMR0.cpp 47472 2013-07-30 11:57:14Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/hm.h>
24	#include <VBox/vmm/pgm.h>
25	#include "HMInternal.h"
26	#include <VBox/vmm/vm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/hm_svm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/assert.h>
32	#include <iprt/asm.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mem.h>
36	#include <iprt/memobj.h>
37	#include <iprt/once.h>
38	#include <iprt/param.h>
39	#include <iprt/power.h>
40	#include <iprt/string.h>
41	#include <iprt/thread.h>
42	#include <iprt/x86.h>
43	#include "HMVMXR0.h"
44	#include "HMSVMR0.h"
45
46
47	/*******************************************************************************
48	* Internal Functions *
49	*******************************************************************************/
50	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
51	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
52	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
55	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
56
57
58	/*******************************************************************************
59	* Structures and Typedefs *
60	*******************************************************************************/
61	/**
62	* This is used to manage the status code of a RTMpOnAll in HM.
63	*/
64	typedef struct HMR0FIRSTRC
65	{
66	/** The status code. */
67	int32_t volatile rc;
68	/** The ID of the CPU reporting the first failure. */
69	RTCPUID volatile idCpu;
70	} HMR0FIRSTRC;
71	/** Pointer to a first return code structure. */
72	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
73
74
75	/*******************************************************************************
76	* Global Variables *
77	*******************************************************************************/
78	/**
79	* Global data.
80	*/
81	static struct
82	{
83	/** Per CPU globals. */
84	HMGLOBLCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
85
86	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
87	* @{ */
88	DECLR0CALLBACKMEMBER(int, pfnEnterSession,(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu));
89	DECLR0CALLBACKMEMBER(int, pfnLeaveSession,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
90	DECLR0CALLBACKMEMBER(int, pfnSaveHostState,(PVM pVM, PVMCPU pVCpu));
91	DECLR0CALLBACKMEMBER(int, pfnLoadGuestState,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
92	DECLR0CALLBACKMEMBER(int, pfnRunGuestCode,(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx));
93	DECLR0CALLBACKMEMBER(int, pfnEnableCpu,(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
94	bool fEnabledByHost));
95	DECLR0CALLBACKMEMBER(int, pfnDisableCpu,(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
96	DECLR0CALLBACKMEMBER(int, pfnInitVM,(PVM pVM));
97	DECLR0CALLBACKMEMBER(int, pfnTermVM,(PVM pVM));
98	DECLR0CALLBACKMEMBER(int, pfnSetupVM,(PVM pVM));
99	/** @} */
100
101	/** Maximum ASID allowed. */
102	uint32_t uMaxAsid;
103
104	/** VT-x data. */
105	struct
106	{
107	/** Set to by us to indicate VMX is supported by the CPU. */
108	bool fSupported;
109	/** Whether we're using SUPR0EnableVTx or not. */
110	bool fUsingSUPR0EnableVTx;
111	/** Whether we're using the preemption timer or not. */
112	bool fUsePreemptTimer;
113	/** The shift mask employed by the VMX-Preemption timer. */
114	uint8_t cPreemptTimerShift;
115
116	/** Host CR4 value (set by ring-0 VMX init) */
117	uint64_t hostCR4;
118
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t hostEFER;
121
122	/** VMX MSR values */
123	struct
124	{
125	uint64_t feature_ctrl;
126	uint64_t vmx_basic_info;
127	VMX_CAPABILITY vmx_pin_ctls;
128	VMX_CAPABILITY vmx_proc_ctls;
129	VMX_CAPABILITY vmx_proc_ctls2;
130	VMX_CAPABILITY vmx_exit;
131	VMX_CAPABILITY vmx_entry;
132	uint64_t vmx_misc;
133	uint64_t vmx_cr0_fixed0;
134	uint64_t vmx_cr0_fixed1;
135	uint64_t vmx_cr4_fixed0;
136	uint64_t vmx_cr4_fixed1;
137	uint64_t vmx_vmcs_enum;
138	uint64_t vmx_vmfunc;
139	uint64_t vmx_ept_vpid_caps;
140	} msr;
141	/* Last instruction error */
142	uint32_t ulLastInstrError;
143	} vmx;
144
145	/** AMD-V information. */
146	struct
147	{
148	/* HWCR MSR (for diagnostics) */
149	uint64_t msrHwcr;
150
151	/** SVM revision. */
152	uint32_t u32Rev;
153
154	/** SVM feature bits from cpuid 0x8000000a */
155	uint32_t u32Features;
156
157	/** Set by us to indicate SVM is supported by the CPU. */
158	bool fSupported;
159	} svm;
160	/** Saved error from detection */
161	int32_t lLastError;
162
163	struct
164	{
165	uint32_t u32AMDFeatureECX;
166	uint32_t u32AMDFeatureEDX;
167	} cpuid;
168
169	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
170	* enabled and disabled each time it's used to execute guest code. */
171	bool fGlobalInit;
172	/** Indicates whether the host is suspending or not. We'll refuse a few
173	* actions when the host is being suspended to speed up the suspending and
174	* avoid trouble. */
175	volatile bool fSuspended;
176
177	/** Whether we've already initialized all CPUs.
178	* @remarks We could check the EnableAllCpusOnce state, but this is
179	* simpler and hopefully easier to understand. */
180	bool fEnabled;
181	/** Serialize initialization in HMR0EnableAllCpus. */
182	RTONCE EnableAllCpusOnce;
183	} g_HvmR0;
184
185
186
187	/**
188	* Initializes a first return code structure.
189	*
190	* @param pFirstRc The structure to init.
191	*/
192	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
193	{
194	pFirstRc->rc = VINF_SUCCESS;
195	pFirstRc->idCpu = NIL_RTCPUID;
196	}
197
198
199	/**
200	* Try set the status code (success ignored).
201	*
202	* @param pFirstRc The first return code structure.
203	* @param rc The status code.
204	*/
205	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
206	{
207	if ( RT_FAILURE(rc)
208	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
209	pFirstRc->idCpu = RTMpCpuId();
210	}
211
212
213	/**
214	* Get the status code of a first return code structure.
215	*
216	* @returns The status code; VINF_SUCCESS or error status, no informational or
217	* warning errors.
218	* @param pFirstRc The first return code structure.
219	*/
220	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
221	{
222	return pFirstRc->rc;
223	}
224
225
226	#ifdef VBOX_STRICT
227	/**
228	* Get the CPU ID on which the failure status code was reported.
229	*
230	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
231	* @param pFirstRc The first return code structure.
232	*/
233	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
234	{
235	return pFirstRc->idCpu;
236	}
237	#endif /* VBOX_STRICT */
238
239
240	/** @name Dummy callback handlers.
241	* @{ */
242
243	static DECLCALLBACK(int) hmR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHMGLOBLCPUINFO pCpu)
244	{
245	NOREF(pVM); NOREF(pVCpu); NOREF(pCpu);
246	return VINF_SUCCESS;
247	}
248
249	static DECLCALLBACK(int) hmR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
250	{
251	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
252	return VINF_SUCCESS;
253	}
254
255	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBLCPUINFO pCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
256	bool fEnabledBySystem)
257	{
258	NOREF(pCpu); NOREF(pVM); NOREF(pvCpuPage); NOREF(HCPhysCpuPage); NOREF(fEnabledBySystem);
259	return VINF_SUCCESS;
260	}
261
262	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBLCPUINFO pCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
263	{
264	NOREF(pCpu); NOREF(pvCpuPage); NOREF(HCPhysCpuPage);
265	return VINF_SUCCESS;
266	}
267
268	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
269	{
270	NOREF(pVM);
271	return VINF_SUCCESS;
272	}
273
274	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
275	{
276	NOREF(pVM);
277	return VINF_SUCCESS;
278	}
279
280	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
281	{
282	NOREF(pVM);
283	return VINF_SUCCESS;
284	}
285
286	static DECLCALLBACK(int) hmR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
287	{
288	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
289	return VINF_SUCCESS;
290	}
291
292	static DECLCALLBACK(int) hmR0DummySaveHostState(PVM pVM, PVMCPU pVCpu)
293	{
294	NOREF(pVM); NOREF(pVCpu);
295	return VINF_SUCCESS;
296	}
297
298	static DECLCALLBACK(int) hmR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
299	{
300	NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
301	return VINF_SUCCESS;
302	}
303
304	/** @} */
305
306
307	/**
308	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
309	* Down at the Rate Specified" erratum.
310	*
311	* Errata names and related steppings:
312	* - BA86 - D0.
313	* - AAX65 - C2.
314	* - AAU65 - C2, K0.
315	* - AAO95 - B1.
316	* - AAT59 - C2.
317	* - AAK139 - D0.
318	* - AAM126 - C0, C1, D0.
319	* - AAN92 - B1.
320	* - AAJ124 - C0, D0.
321	*
322	* - AAP86 - B1.
323	*
324	* Steppings: B1, C0, C1, C2, D0, K0.
325	*
326	* @returns true if subject to it, false if not.
327	*/
328	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
329	{
330	uint32_t u = ASMCpuId_EAX(1);
331	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
332	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
333	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
334	\|\| u == UINT32_C(0x00020652) /* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
335	\|\| u == UINT32_C(0x00020652) /* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
336	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
337	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
338	\|\| u == UINT32_C(0x000106E5) /* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
339	\|\| u == UINT32_C(0x000106E5) /* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
340	\|\| u == UINT32_C(0x000106A0) /?321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification /
341	\|\| u == UINT32_C(0x000106A1) /?321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification /
342	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
343	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
344	\|\| u == UINT32_C(0x000106A5) /* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
345	\|\| u == UINT32_C(0x000106A5) /* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
346	)
347	return true;
348	return false;
349	}
350
351
352	/**
353	* Intel specific initialization code.
354	*
355	* @returns VBox status code (will only fail if out of memory).
356	*/
357	static int hmR0InitIntel(uint32_t u32FeaturesECX, uint32_t u32FeaturesEDX)
358	{
359	/*
360	* Check that all the required VT-x features are present.
361	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
362	*/
363	if ( (u32FeaturesECX & X86_CPUID_FEATURE_ECX_VMX)
364	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
365	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
366	)
367	{
368	/** @todo move this into a separate function. */
369	g_HvmR0.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
370
371	/*
372	* First try use native kernel API for controlling VT-x.
373	* (This is only supported by some Mac OS X kernels atm.)
374	*/
375	int rc = g_HvmR0.lLastError = SUPR0EnableVTx(true /* fEnable */);
376	g_HvmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
377	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
378	{
379	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
380	if (RT_SUCCESS(rc))
381	{
382	g_HvmR0.vmx.fSupported = true;
383	rc = SUPR0EnableVTx(false /* fEnable */);
384	AssertLogRelRC(rc);
385	}
386	}
387	else
388	{
389	/* We need to check if VT-x has been properly initialized on all
390	CPUs. Some BIOSes do a lousy job. */
391	HMR0FIRSTRC FirstRc;
392	hmR0FirstRcInit(&FirstRc);
393	g_HvmR0.lLastError = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
394	if (RT_SUCCESS(g_HvmR0.lLastError))
395	g_HvmR0.lLastError = hmR0FirstRcGetStatus(&FirstRc);
396	}
397	if (RT_SUCCESS(g_HvmR0.lLastError))
398	{
399	/* Reread in case we've changed it. */
400	g_HvmR0.vmx.msr.feature_ctrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
401
402	if ( (g_HvmR0.vmx.msr.feature_ctrl & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
403	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
404	{
405	/*
406	* Read all relevant MSR.
407	*/
408	g_HvmR0.vmx.msr.vmx_basic_info = ASMRdMsr(MSR_IA32_VMX_BASIC_INFO);
409	g_HvmR0.vmx.msr.vmx_pin_ctls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
410	g_HvmR0.vmx.msr.vmx_proc_ctls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
411	g_HvmR0.vmx.msr.vmx_exit.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
412	g_HvmR0.vmx.msr.vmx_entry.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
413	g_HvmR0.vmx.msr.vmx_misc = ASMRdMsr(MSR_IA32_VMX_MISC);
414	g_HvmR0.vmx.msr.vmx_cr0_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
415	g_HvmR0.vmx.msr.vmx_cr0_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
416	g_HvmR0.vmx.msr.vmx_cr4_fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
417	g_HvmR0.vmx.msr.vmx_cr4_fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
418	g_HvmR0.vmx.msr.vmx_vmcs_enum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
419	g_HvmR0.vmx.hostCR4 = ASMGetCR4();
420	g_HvmR0.vmx.hostEFER = ASMRdMsr(MSR_K6_EFER);
421	/* VPID 16 bits ASID. */
422	g_HvmR0.uMaxAsid = 0x10000; /* exclusive */
423
424	if (g_HvmR0.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
425	{
426	g_HvmR0.vmx.msr.vmx_proc_ctls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
427	if ( g_HvmR0.vmx.msr.vmx_proc_ctls2.n.allowed1
428	& (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
429	{
430	g_HvmR0.vmx.msr.vmx_ept_vpid_caps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
431	}
432
433	if (g_HvmR0.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
434	g_HvmR0.vmx.msr.vmx_vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
435	}
436
437	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
438	{
439	/*
440	* Enter root mode
441	*/
442	RTR0MEMOBJ hScatchMemObj;
443	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
444	if (RT_FAILURE(rc))
445	{
446	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,true) -> %Rrc\n", rc));
447	return rc;
448	}
449
450	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
451	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
452	ASMMemZeroPage(pvScatchPage);
453
454	/* Set revision dword at the beginning of the structure. */
455	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(g_HvmR0.vmx.msr.vmx_basic_info);
456
457	/* Make sure we don't get rescheduled to another cpu during this probe. */
458	RTCCUINTREG fFlags = ASMIntDisableFlags();
459
460	/*
461	* Check CR4.VMXE
462	*/
463	g_HvmR0.vmx.hostCR4 = ASMGetCR4();
464	if (!(g_HvmR0.vmx.hostCR4 & X86_CR4_VMXE))
465	{
466	/* In theory this bit could be cleared behind our back. Which would cause
467	#UD faults when we try to execute the VMX instructions... */
468	ASMSetCR4(g_HvmR0.vmx.hostCR4 \| X86_CR4_VMXE);
469	}
470
471	/* Enter VMX Root Mode */
472	rc = VMXEnable(HCPhysScratchPage);
473	if (RT_SUCCESS(rc))
474	{
475	g_HvmR0.vmx.fSupported = true;
476	VMXDisable();
477	}
478	else
479	{
480	/*
481	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
482	* it will crash the host when we enter raw mode, because:
483	*
484	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
485	* this bit), and
486	* (b) turning off paging causes a #GP (unavoidable when switching
487	* from long to 32 bits mode or 32 bits to PAE).
488	*
489	* They should fix their code, but until they do we simply refuse to run.
490	*/
491	g_HvmR0.lLastError = VERR_VMX_IN_VMX_ROOT_MODE;
492	}
493
494	/* Restore CR4 again; don't leave the X86_CR4_VMXE flag set
495	if it wasn't so before (some software could incorrectly
496	think it's in VMX mode). */
497	ASMSetCR4(g_HvmR0.vmx.hostCR4);
498	ASMSetFlags(fFlags);
499
500	RTR0MemObjFree(hScatchMemObj, false);
501	}
502	}
503	else
504	{
505	AssertFailed(); /* can't hit this case anymore */
506	g_HvmR0.lLastError = VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR;
507	}
508
509	if (g_HvmR0.vmx.fSupported)
510	{
511	/* Call the global VT-x initialization routine. */
512	rc = VMXR0GlobalInit();
513	if (RT_FAILURE(rc))
514	g_HvmR0.lLastError = rc;
515
516	/*
517	* Install the VT-x methods.
518	*/
519	g_HvmR0.pfnEnterSession = VMXR0Enter;
520	g_HvmR0.pfnLeaveSession = VMXR0Leave;
521	g_HvmR0.pfnSaveHostState = VMXR0SaveHostState;
522	g_HvmR0.pfnLoadGuestState = VMXR0LoadGuestState;
523	g_HvmR0.pfnRunGuestCode = VMXR0RunGuestCode;
524	g_HvmR0.pfnEnableCpu = VMXR0EnableCpu;
525	g_HvmR0.pfnDisableCpu = VMXR0DisableCpu;
526	g_HvmR0.pfnInitVM = VMXR0InitVM;
527	g_HvmR0.pfnTermVM = VMXR0TermVM;
528	g_HvmR0.pfnSetupVM = VMXR0SetupVM;
529
530	/*
531	* Check for the VMX-Preemption Timer and adjust for the * "VMX-Preemption
532	* Timer Does Not Count Down at the Rate Specified" erratum.
533	*/
534	if (g_HvmR0.vmx.msr.vmx_pin_ctls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
535	{
536	g_HvmR0.vmx.fUsePreemptTimer = true;
537	g_HvmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HvmR0.vmx.msr.vmx_misc);
538	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
539	g_HvmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
540	}
541	}
542	}
543	#ifdef LOG_ENABLED
544	else
545	SUPR0Printf("hmR0InitIntelCpu failed with rc=%d\n", g_HvmR0.lLastError);
546	#endif
547	}
548	else
549	g_HvmR0.lLastError = VERR_VMX_NO_VMX;
550	return VINF_SUCCESS;
551	}
552
553
554	/**
555	* AMD-specific initialization code.
556	*
557	* @returns VBox status code.
558	*/
559	static int hmR0InitAmd(uint32_t u32FeaturesEDX, uint32_t uMaxExtLeaf)
560	{
561	/*
562	* Read all SVM MSRs if SVM is available. (same goes for RDMSR/WRMSR)
563	* We also assume all SVM-enabled CPUs support fxsave/fxrstor.
564	*/
565	int rc;
566	if ( (g_HvmR0.cpuid.u32AMDFeatureECX & X86_CPUID_AMD_FEATURE_ECX_SVM)
567	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_MSR)
568	&& (u32FeaturesEDX & X86_CPUID_FEATURE_EDX_FXSR)
569	&& ASMIsValidExtRange(uMaxExtLeaf)
570	&& uMaxExtLeaf >= 0x8000000a
571	)
572	{
573	/* Call the global AMD-V initialization routine. */
574	rc = SVMR0GlobalInit();
575	if (RT_FAILURE(rc))
576	{
577	g_HvmR0.lLastError = rc;
578	return rc;
579	}
580
581	/*
582	* Install the AMD-V methods.
583	*/
584	g_HvmR0.pfnEnterSession = SVMR0Enter;
585	g_HvmR0.pfnLeaveSession = SVMR0Leave;
586	g_HvmR0.pfnSaveHostState = SVMR0SaveHostState;
587	g_HvmR0.pfnLoadGuestState = SVMR0LoadGuestState;
588	g_HvmR0.pfnRunGuestCode = SVMR0RunGuestCode;
589	g_HvmR0.pfnEnableCpu = SVMR0EnableCpu;
590	g_HvmR0.pfnDisableCpu = SVMR0DisableCpu;
591	g_HvmR0.pfnInitVM = SVMR0InitVM;
592	g_HvmR0.pfnTermVM = SVMR0TermVM;
593	g_HvmR0.pfnSetupVM = SVMR0SetupVM;
594
595	/* Query AMD features. */
596	uint32_t u32Dummy;
597	ASMCpuId(0x8000000a, &g_HvmR0.svm.u32Rev, &g_HvmR0.uMaxAsid, &u32Dummy, &g_HvmR0.svm.u32Features);
598
599	/*
600	* We need to check if AMD-V has been properly initialized on all CPUs.
601	* Some BIOSes might do a poor job.
602	*/
603	HMR0FIRSTRC FirstRc;
604	hmR0FirstRcInit(&FirstRc);
605	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
606	AssertRC(rc);
607	if (RT_SUCCESS(rc))
608	rc = hmR0FirstRcGetStatus(&FirstRc);
609	#ifndef DEBUG_bird
610	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
611	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
612	#endif
613	if (RT_SUCCESS(rc))
614	{
615	/* Read the HWCR MSR for diagnostics. */
616	g_HvmR0.svm.msrHwcr = ASMRdMsr(MSR_K8_HWCR);
617	g_HvmR0.svm.fSupported = true;
618	}
619	else
620	g_HvmR0.lLastError = rc;
621	}
622	else
623	{
624	rc = VINF_SUCCESS; /* Don't fail if AMD-V is not supported. See @bugref{6785}. */
625	g_HvmR0.lLastError = VERR_SVM_NO_SVM;
626	}
627	return rc;
628	}
629
630
631	/**
632	* Does global Ring-0 HM initialization (at module init).
633	*
634	* @returns VBox status code.
635	*/
636	VMMR0_INT_DECL(int) HMR0Init(void)
637	{
638	/*
639	* Initialize the globals.
640	*/
641	g_HvmR0.fEnabled = false;
642	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
643	g_HvmR0.EnableAllCpusOnce = s_OnceInit;
644	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
645	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
646
647	/* Fill in all callbacks with placeholders. */
648	g_HvmR0.pfnEnterSession = hmR0DummyEnter;
649	g_HvmR0.pfnLeaveSession = hmR0DummyLeave;
650	g_HvmR0.pfnSaveHostState = hmR0DummySaveHostState;
651	g_HvmR0.pfnLoadGuestState = hmR0DummyLoadGuestState;
652	g_HvmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
653	g_HvmR0.pfnEnableCpu = hmR0DummyEnableCpu;
654	g_HvmR0.pfnDisableCpu = hmR0DummyDisableCpu;
655	g_HvmR0.pfnInitVM = hmR0DummyInitVM;
656	g_HvmR0.pfnTermVM = hmR0DummyTermVM;
657	g_HvmR0.pfnSetupVM = hmR0DummySetupVM;
658
659	/* Default is global VT-x/AMD-V init. */
660	g_HvmR0.fGlobalInit = true;
661
662	/*
663	* Make sure aCpuInfo is big enough for all the CPUs on this system.
664	*/
665	if (RTMpGetArraySize() > RT_ELEMENTS(g_HvmR0.aCpuInfo))
666	{
667	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HvmR0.aCpuInfo)));
668	return VERR_TOO_MANY_CPUS;
669	}
670
671	/*
672	* Check for VT-x and AMD-V capabilities.
673	*/
674	int rc;
675	if (ASMHasCpuId())
676	{
677	/* Standard features. */
678	uint32_t uMaxLeaf, u32VendorEBX, u32VendorECX, u32VendorEDX;
679	ASMCpuId(0, &uMaxLeaf, &u32VendorEBX, &u32VendorECX, &u32VendorEDX);
680	if (ASMIsValidStdRange(uMaxLeaf))
681	{
682	uint32_t u32FeaturesECX, u32FeaturesEDX, u32Dummy;
683	ASMCpuId(1, &u32Dummy, &u32Dummy, &u32FeaturesECX, &u32FeaturesEDX);
684
685	/* Query AMD features. */
686	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
687	if (ASMIsValidExtRange(uMaxExtLeaf))
688	ASMCpuId(0x80000001, &u32Dummy, &u32Dummy,
689	&g_HvmR0.cpuid.u32AMDFeatureECX,
690	&g_HvmR0.cpuid.u32AMDFeatureEDX);
691	else
692	g_HvmR0.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureEDX = 0;
693
694	/* Go to CPU specific initialization code. */
695	if ( ASMIsIntelCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX)
696	\|\| ASMIsViaCentaurCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
697	{
698	rc = hmR0InitIntel(u32FeaturesECX, u32FeaturesEDX);
699	if (RT_FAILURE(rc))
700	return rc;
701	}
702	else if (ASMIsAmdCpuEx(u32VendorEBX, u32VendorECX, u32VendorEDX))
703	{
704	rc = hmR0InitAmd(u32FeaturesEDX, uMaxExtLeaf);
705	if (RT_FAILURE(rc))
706	return rc;
707	}
708	else
709	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
710	}
711	else
712	g_HvmR0.lLastError = VERR_HM_UNKNOWN_CPU;
713	}
714	else
715	g_HvmR0.lLastError = VERR_HM_NO_CPUID;
716
717	/*
718	* Register notification callbacks that we can use to disable/enable CPUs
719	* when brought offline/online or suspending/resuming.
720	*/
721	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
722	{
723	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
724	AssertRC(rc);
725
726	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
727	AssertRC(rc);
728	}
729
730	/* We return success here because module init shall not fail if HM
731	fails to initialize. */
732	return VINF_SUCCESS;
733	}
734
735
736	/**
737	* Does global Ring-0 HM termination (at module termination).
738	*
739	* @returns VBox status code.
740	*/
741	VMMR0_INT_DECL(int) HMR0Term(void)
742	{
743	int rc;
744	if ( g_HvmR0.vmx.fSupported
745	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
746	{
747	/*
748	* Simple if the host OS manages VT-x.
749	*/
750	Assert(g_HvmR0.fGlobalInit);
751	rc = SUPR0EnableVTx(false /* fEnable */);
752
753	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo); iCpu++)
754	{
755	g_HvmR0.aCpuInfo[iCpu].fConfigured = false;
756	Assert(g_HvmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
757	}
758	}
759	else
760	{
761	Assert(!g_HvmR0.vmx.fUsingSUPR0EnableVTx);
762	if (!g_HvmR0.vmx.fUsingSUPR0EnableVTx)
763	{
764	/* Doesn't really matter if this fails. */
765	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
766	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
767	}
768	else
769	rc = VINF_SUCCESS;
770
771	/*
772	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
773	*/
774	if (g_HvmR0.fGlobalInit)
775	{
776	HMR0FIRSTRC FirstRc;
777	hmR0FirstRcInit(&FirstRc);
778	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL, &FirstRc);
779	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
780	if (RT_SUCCESS(rc))
781	{
782	rc = hmR0FirstRcGetStatus(&FirstRc);
783	AssertMsgRC(rc, ("%u: %Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
784	}
785	}
786
787	/*
788	* Free the per-cpu pages used for VT-x and AMD-V.
789	*/
790	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
791	{
792	if (g_HvmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
793	{
794	RTR0MemObjFree(g_HvmR0.aCpuInfo[i].hMemObj, false);
795	g_HvmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
796	}
797	}
798	}
799
800	/** @todo This needs cleaning up. There's no matching
801	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
802	* should move into their respective modules. */
803	/* Finally, call global VT-x/AMD-V termination. */
804	if (g_HvmR0.vmx.fSupported)
805	VMXR0GlobalTerm();
806	else if (g_HvmR0.svm.fSupported)
807	SVMR0GlobalTerm();
808
809	return rc;
810	}
811
812
813	/**
814	* Worker function used by hmR0PowerCallback and HMR0Init to initalize
815	* VT-x on a CPU.
816	*
817	* @param idCpu The identifier for the CPU the function is called on.
818	* @param pvUser1 Pointer to the first RC structure.
819	* @param pvUser2 Ignored.
820	*/
821	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
822	{
823	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
824	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
825	NOREF(pvUser2);
826
827	/*
828	* Both the LOCK and VMXON bit must be set; otherwise VMXON will generate a #GP.
829	* Once the lock bit is set, this MSR can no longer be modified.
830	*/
831	uint64_t fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
832	if ( !(fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
833	\|\| ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
834	== MSR_IA32_FEATURE_CONTROL_VMXON ) /* Some BIOSes forget to set the locked bit. */
835	)
836	{
837	/* MSR is not yet locked; we can change it ourselves here. */
838	ASMWrMsr(MSR_IA32_FEATURE_CONTROL,
839	g_HvmR0.vmx.msr.feature_ctrl \| MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK);
840	fFC = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
841	}
842
843	int rc;
844	if ( (fFC & (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
845	== (MSR_IA32_FEATURE_CONTROL_VMXON \| MSR_IA32_FEATURE_CONTROL_LOCK))
846	rc = VINF_SUCCESS;
847	else
848	rc = VERR_VMX_MSR_LOCKED_OR_DISABLED;
849
850	hmR0FirstRcSetStatus(pFirstRc, rc);
851	}
852
853
854	/**
855	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
856	* on a CPU.
857	*
858	* @param idCpu The identifier for the CPU the function is called on.
859	* @param pvUser1 Pointer to the first RC structure.
860	* @param pvUser2 Ignored.
861	*/
862	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
863	{
864	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
865	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
866	NOREF(pvUser2);
867
868	/* Check if SVM is disabled. */
869	int rc;
870	uint64_t fVmCr = ASMRdMsr(MSR_K8_VM_CR);
871	if (!(fVmCr & MSR_K8_VM_CR_SVM_DISABLE))
872	{
873	/* Turn on SVM in the EFER MSR. */
874	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
875	if (fEfer & MSR_K6_EFER_SVME)
876	rc = VERR_SVM_IN_USE;
877	else
878	{
879	ASMWrMsr(MSR_K6_EFER, fEfer \| MSR_K6_EFER_SVME);
880
881	/* Paranoia. */
882	fEfer = ASMRdMsr(MSR_K6_EFER);
883	if (fEfer & MSR_K6_EFER_SVME)
884	{
885	/* Restore previous value. */
886	ASMWrMsr(MSR_K6_EFER, fEfer & ~MSR_K6_EFER_SVME);
887	rc = VINF_SUCCESS;
888	}
889	else
890	rc = VERR_SVM_ILLEGAL_EFER_MSR;
891	}
892	}
893	else
894	rc = VERR_SVM_DISABLED;
895
896	hmR0FirstRcSetStatus(pFirstRc, rc);
897	}
898
899
900	/**
901	* Enable VT-x or AMD-V on the current CPU
902	*
903	* @returns VBox status code.
904	* @param pVM Pointer to the VM (can be 0).
905	* @param idCpu The identifier for the CPU the function is called on.
906	*/
907	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
908	{
909	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
910
911	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
912	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
913	Assert(!pCpu->fConfigured);
914	Assert(!g_HvmR0.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
915
916	pCpu->idCpu = idCpu;
917	pCpu->uCurrentAsid = 0; /* we'll aways increment this the first time (host uses ASID 0) */
918	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
919
920	int rc;
921	if (g_HvmR0.vmx.fSupported && g_HvmR0.vmx.fUsingSUPR0EnableVTx)
922	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, NULL, NIL_RTHCPHYS, true);
923	else
924	{
925	AssertLogRelMsgReturn(pCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
926	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
927	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
928	rc = g_HvmR0.pfnEnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false);
929	}
930	AssertRC(rc);
931	if (RT_SUCCESS(rc))
932	pCpu->fConfigured = true;
933
934	return rc;
935	}
936
937
938	/**
939	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
940	* is to be called on the target cpus.
941	*
942	* @param idCpu The identifier for the CPU the function is called on.
943	* @param pvUser1 The 1st user argument.
944	* @param pvUser2 The 2nd user argument.
945	*/
946	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
947	{
948	PVM pVM = (PVM)pvUser1; /* can be NULL! */
949	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
950	AssertReturnVoid(g_HvmR0.fGlobalInit);
951	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
952	}
953
954
955	/**
956	* RTOnce callback employed by HMR0EnableAllCpus.
957	*
958	* @returns VBox status code.
959	* @param pvUser Pointer to the VM.
960	* @param pvUserIgnore NULL, ignored.
961	*/
962	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
963	{
964	PVM pVM = (PVM)pvUser;
965
966	/*
967	* Indicate that we've initialized.
968	*
969	* Note! There is a potential race between this function and the suspend
970	* notification. Kind of unlikely though, so ignored for now.
971	*/
972	AssertReturn(!g_HvmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
973	ASMAtomicWriteBool(&g_HvmR0.fEnabled, true);
974
975	/*
976	* The global init variable is set by the first VM.
977	*/
978	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
979
980	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
981	{
982	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
983	g_HvmR0.aCpuInfo[i].fConfigured = false;
984	g_HvmR0.aCpuInfo[i].cTlbFlushes = 0;
985	}
986
987	int rc;
988	if ( g_HvmR0.vmx.fSupported
989	&& g_HvmR0.vmx.fUsingSUPR0EnableVTx)
990	{
991	/*
992	* Global VT-x initialization API (only darwin for now).
993	*/
994	rc = SUPR0EnableVTx(true /* fEnable */);
995	if (RT_SUCCESS(rc))
996	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
997	g_HvmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
998	else
999	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
1000	}
1001	else
1002	{
1003	/*
1004	* We're doing the job ourselves.
1005	*/
1006	/* Allocate one page per cpu for the global vt-x and amd-v pages */
1007	for (unsigned i = 0; i < RT_ELEMENTS(g_HvmR0.aCpuInfo); i++)
1008	{
1009	Assert(g_HvmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
1010
1011	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
1012	{
1013	rc = RTR0MemObjAllocCont(&g_HvmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, true /* executable R0 mapping */);
1014	AssertLogRelRCReturn(rc, rc);
1015
1016	void *pvR0 = RTR0MemObjAddress(g_HvmR0.aCpuInfo[i].hMemObj); Assert(pvR0);
1017	ASMMemZeroPage(pvR0);
1018	}
1019	}
1020
1021	rc = VINF_SUCCESS;
1022	}
1023
1024	if (RT_SUCCESS(rc) && g_HvmR0.fGlobalInit)
1025	{
1026	/* First time, so initialize each cpu/core. */
1027	HMR0FIRSTRC FirstRc;
1028	hmR0FirstRcInit(&FirstRc);
1029	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
1030	if (RT_SUCCESS(rc))
1031	rc = hmR0FirstRcGetStatus(&FirstRc);
1032	AssertMsgRC(rc, ("hmR0EnableAllCpuOnce failed for cpu %d with rc=%d\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
1033	}
1034
1035	return rc;
1036	}
1037
1038
1039	/**
1040	* Sets up HM on all cpus.
1041	*
1042	* @returns VBox status code.
1043	* @param pVM Pointer to the VM.
1044	*/
1045	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
1046	{
1047	/* Make sure we don't touch HM after we've disabled HM in
1048	preparation of a suspend. */
1049	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1050	return VERR_HM_SUSPEND_PENDING;
1051
1052	return RTOnce(&g_HvmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1053	}
1054
1055
1056	/**
1057	* Disable VT-x or AMD-V on the current CPU.
1058	*
1059	* @returns VBox status code.
1060	* @param idCpu The identifier for the CPU the function is called on.
1061	*/
1062	static int hmR0DisableCpu(RTCPUID idCpu)
1063	{
1064	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1065
1066	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1067	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /// @todo fix idCpu == index assumption (rainy day)
1068	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1069	Assert(!g_HvmR0.fGlobalInit \|\| ASMAtomicReadBool(&pCpu->fInUse) == false);
1070	Assert(!pCpu->fConfigured \|\| pCpu->hMemObj != NIL_RTR0MEMOBJ);
1071
1072	if (pCpu->hMemObj == NIL_RTR0MEMOBJ)
1073	return pCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1074
1075	int rc;
1076	if (pCpu->fConfigured)
1077	{
1078	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1079	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1080	if (idCpu == RTMpCpuId())
1081	{
1082	rc = g_HvmR0.pfnDisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1083	AssertRC(rc);
1084	}
1085	else
1086	{
1087	pCpu->fIgnoreAMDVInUseError = true;
1088	rc = VINF_SUCCESS;
1089	}
1090
1091	pCpu->fConfigured = false;
1092	}
1093	else
1094	rc = VINF_SUCCESS; /* nothing to do */
1095
1096	pCpu->uCurrentAsid = 0;
1097	return rc;
1098	}
1099
1100
1101	/**
1102	* Worker function passed to RTMpOnAll, RTMpOnOthers and RTMpOnSpecific that
1103	* is to be called on the target cpus.
1104	*
1105	* @param idCpu The identifier for the CPU the function is called on.
1106	* @param pvUser1 The 1st user argument.
1107	* @param pvUser2 The 2nd user argument.
1108	*/
1109	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1110	{
1111	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1112	AssertReturnVoid(g_HvmR0.fGlobalInit);
1113	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1114	}
1115
1116
1117	/**
1118	* Callback function invoked when a cpu goes online or offline.
1119	*
1120	* @param enmEvent The Mp event.
1121	* @param idCpu The identifier for the CPU the function is called on.
1122	* @param pvData Opaque data (PVM pointer).
1123	*/
1124	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1125	{
1126	NOREF(pvData);
1127
1128	/*
1129	* We only care about uninitializing a CPU that is going offline. When a
1130	* CPU comes online, the initialization is done lazily in HMR0Enter().
1131	*/
1132	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1133	switch (enmEvent)
1134	{
1135	case RTMPEVENT_OFFLINE:
1136	{
1137	int rc = hmR0DisableCpu(idCpu);
1138	AssertRC(rc);
1139	break;
1140	}
1141
1142	default:
1143	break;
1144	}
1145	}
1146
1147
1148	/**
1149	* Called whenever a system power state change occurs.
1150	*
1151	* @param enmEvent The Power event.
1152	* @param pvUser User argument.
1153	*/
1154	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1155	{
1156	NOREF(pvUser);
1157	Assert(!g_HvmR0.vmx.fSupported \|\| !g_HvmR0.vmx.fUsingSUPR0EnableVTx);
1158
1159	#ifdef LOG_ENABLED
1160	if (enmEvent == RTPOWEREVENT_SUSPEND)
1161	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1162	else
1163	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1164	#endif
1165
1166	if (enmEvent == RTPOWEREVENT_SUSPEND)
1167	ASMAtomicWriteBool(&g_HvmR0.fSuspended, true);
1168
1169	if (g_HvmR0.fEnabled)
1170	{
1171	int rc;
1172	HMR0FIRSTRC FirstRc;
1173	hmR0FirstRcInit(&FirstRc);
1174
1175	if (enmEvent == RTPOWEREVENT_SUSPEND)
1176	{
1177	if (g_HvmR0.fGlobalInit)
1178	{
1179	/* Turn off VT-x or AMD-V on all CPUs. */
1180	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL, &FirstRc);
1181	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1182	}
1183	/* else nothing to do here for the local init case */
1184	}
1185	else
1186	{
1187	/* Reinit the CPUs from scratch as the suspend state might have
1188	messed with the MSRs. (lousy BIOSes as usual) */
1189	if (g_HvmR0.vmx.fSupported)
1190	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1191	else
1192	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1193	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1194	if (RT_SUCCESS(rc))
1195	rc = hmR0FirstRcGetStatus(&FirstRc);
1196	#ifdef LOG_ENABLED
1197	if (RT_FAILURE(rc))
1198	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1199	#endif
1200	if (g_HvmR0.fGlobalInit)
1201	{
1202	/* Turn VT-x or AMD-V back on on all CPUs. */
1203	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL, &FirstRc /* output ignored */);
1204	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1205	}
1206	/* else nothing to do here for the local init case */
1207	}
1208	}
1209
1210	if (enmEvent == RTPOWEREVENT_RESUME)
1211	ASMAtomicWriteBool(&g_HvmR0.fSuspended, false);
1212	}
1213
1214
1215	/**
1216	* Does Ring-0 per VM HM initialization.
1217	*
1218	* This will copy HM global into the VM structure and call the CPU specific
1219	* init routine which will allocate resources for each virtual CPU and such.
1220	*
1221	* @returns VBox status code.
1222	* @param pVM Pointer to the VM.
1223	*/
1224	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1225	{
1226	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1227
1228	#ifdef LOG_ENABLED
1229	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1230	#endif
1231
1232	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1233	if (ASMAtomicReadBool(&g_HvmR0.fSuspended))
1234	return VERR_HM_SUSPEND_PENDING;
1235
1236	/*
1237	* Copy globals to the VM structure.
1238	*/
1239	pVM->hm.s.vmx.fSupported = g_HvmR0.vmx.fSupported;
1240	pVM->hm.s.svm.fSupported = g_HvmR0.svm.fSupported;
1241
1242	pVM->hm.s.vmx.fUsePreemptTimer = g_HvmR0.vmx.fUsePreemptTimer;
1243	pVM->hm.s.vmx.cPreemptTimerShift = g_HvmR0.vmx.cPreemptTimerShift;
1244	pVM->hm.s.vmx.msr.feature_ctrl = g_HvmR0.vmx.msr.feature_ctrl;
1245	pVM->hm.s.vmx.hostCR4 = g_HvmR0.vmx.hostCR4;
1246	pVM->hm.s.vmx.hostEFER = g_HvmR0.vmx.hostEFER;
1247	pVM->hm.s.vmx.msr.vmx_basic_info = g_HvmR0.vmx.msr.vmx_basic_info;
1248	pVM->hm.s.vmx.msr.vmx_pin_ctls = g_HvmR0.vmx.msr.vmx_pin_ctls;
1249	pVM->hm.s.vmx.msr.vmx_proc_ctls = g_HvmR0.vmx.msr.vmx_proc_ctls;
1250	pVM->hm.s.vmx.msr.vmx_proc_ctls2 = g_HvmR0.vmx.msr.vmx_proc_ctls2;
1251	pVM->hm.s.vmx.msr.vmx_exit = g_HvmR0.vmx.msr.vmx_exit;
1252	pVM->hm.s.vmx.msr.vmx_entry = g_HvmR0.vmx.msr.vmx_entry;
1253	pVM->hm.s.vmx.msr.vmx_misc = g_HvmR0.vmx.msr.vmx_misc;
1254	pVM->hm.s.vmx.msr.vmx_cr0_fixed0 = g_HvmR0.vmx.msr.vmx_cr0_fixed0;
1255	pVM->hm.s.vmx.msr.vmx_cr0_fixed1 = g_HvmR0.vmx.msr.vmx_cr0_fixed1;
1256	pVM->hm.s.vmx.msr.vmx_cr4_fixed0 = g_HvmR0.vmx.msr.vmx_cr4_fixed0;
1257	pVM->hm.s.vmx.msr.vmx_cr4_fixed1 = g_HvmR0.vmx.msr.vmx_cr4_fixed1;
1258	pVM->hm.s.vmx.msr.vmx_vmcs_enum = g_HvmR0.vmx.msr.vmx_vmcs_enum;
1259	pVM->hm.s.vmx.msr.vmx_vmfunc = g_HvmR0.vmx.msr.vmx_vmfunc;
1260	pVM->hm.s.vmx.msr.vmx_ept_vpid_caps = g_HvmR0.vmx.msr.vmx_ept_vpid_caps;
1261	pVM->hm.s.svm.msrHwcr = g_HvmR0.svm.msrHwcr;
1262	pVM->hm.s.svm.u32Rev = g_HvmR0.svm.u32Rev;
1263	pVM->hm.s.svm.u32Features = g_HvmR0.svm.u32Features;
1264	pVM->hm.s.cpuid.u32AMDFeatureECX = g_HvmR0.cpuid.u32AMDFeatureECX;
1265	pVM->hm.s.cpuid.u32AMDFeatureEDX = g_HvmR0.cpuid.u32AMDFeatureEDX;
1266	pVM->hm.s.lLastError = g_HvmR0.lLastError;
1267
1268	pVM->hm.s.uMaxAsid = g_HvmR0.uMaxAsid;
1269
1270
1271	if (!pVM->hm.s.cMaxResumeLoops) /* allow ring-3 overrides */
1272	{
1273	pVM->hm.s.cMaxResumeLoops = 1024;
1274	#ifdef VBOX_WITH_VMMR0_DISABLE_PREEMPTION
1275	if (RTThreadPreemptIsPendingTrusty())
1276	pVM->hm.s.cMaxResumeLoops = 8192;
1277	#endif
1278	}
1279
1280	/*
1281	* Initialize some per CPU fields.
1282	*/
1283	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1284	{
1285	PVMCPU pVCpu = &pVM->aCpus[i];
1286
1287	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1288
1289	/* Invalidate the last cpu we were running on. */
1290	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1291
1292	/* We'll aways increment this the first time (host uses ASID 0) */
1293	pVCpu->hm.s.uCurrentAsid = 0;
1294	}
1295
1296	/*
1297	* Call the hardware specific initialization method.
1298	*
1299	* Note! The fInUse handling here isn't correct as we can we can be
1300	* rescheduled to a different cpu, but the fInUse case is mostly for
1301	* debugging... Disabling preemption isn't an option when allocating
1302	* memory, so we'll let it slip for now.
1303	*/
1304	RTCCUINTREG fFlags = ASMIntDisableFlags();
1305	PHMGLOBLCPUINFO pCpu = HMR0GetCurrentCpu();
1306	ASMAtomicWriteBool(&pCpu->fInUse, true);
1307	ASMSetFlags(fFlags);
1308
1309	int rc = g_HvmR0.pfnInitVM(pVM);
1310
1311	ASMAtomicWriteBool(&pCpu->fInUse, false);
1312	return rc;
1313	}
1314
1315
1316	/**
1317	* Does Ring-0 per VM HM termination.
1318	*
1319	* @returns VBox status code.
1320	* @param pVM Pointer to the VM.
1321	*/
1322	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1323	{
1324	Log(("HMR0TermVM: %p\n", pVM));
1325	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1326
1327	/* Make sure we don't touch HM after we've disabled HM in preparation
1328	of a suspend. */
1329	/** @todo r=bird: This cannot be right, the termination functions are
1330	* just freeing memory and resetting pVM/pVCpu members...
1331	* ==> memory leak. */
1332	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1333
1334	/*
1335	* Call the hardware specific method.
1336	*
1337	* Note! Not correct as we can be rescheduled to a different cpu, but the
1338	* fInUse case is mostly for debugging.
1339	*/
1340	RTCCUINTREG fFlags = ASMIntDisableFlags();
1341	PHMGLOBLCPUINFO pCpu = HMR0GetCurrentCpu();
1342	ASMAtomicWriteBool(&pCpu->fInUse, true);
1343	ASMSetFlags(fFlags);
1344
1345	int rc = g_HvmR0.pfnTermVM(pVM);
1346
1347	ASMAtomicWriteBool(&pCpu->fInUse, false);
1348	return rc;
1349	}
1350
1351
1352	/**
1353	* Sets up a VT-x or AMD-V session.
1354	*
1355	* This is mostly about setting up the hardware VM state.
1356	*
1357	* @returns VBox status code.
1358	* @param pVM Pointer to the VM.
1359	*/
1360	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1361	{
1362	Log(("HMR0SetupVM: %p\n", pVM));
1363	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1364
1365	/* Make sure we don't touch HM after we've disabled HM in
1366	preparation of a suspend. */
1367	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1368
1369	/*
1370	* Call the hardware specific setup VM method. This requires the CPU to be
1371	* enabled for AMD-V/VT-x and preemption to be prevented.
1372	*/
1373	RTCCUINTREG fFlags = ASMIntDisableFlags();
1374	RTCPUID idCpu = RTMpCpuId();
1375	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1376	ASMAtomicWriteBool(&pCpu->fInUse, true);
1377
1378	/* On first entry we'll sync everything. */
1379	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1380	pVM->aCpus[i].hm.s.fContextUseFlags = (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1381
1382	/* Enable VT-x or AMD-V if local init is required. */
1383	int rc;
1384	if (!g_HvmR0.fGlobalInit)
1385	{
1386	rc = hmR0EnableCpu(pVM, idCpu);
1387	AssertReturnStmt(RT_SUCCESS_NP(rc), ASMSetFlags(fFlags), rc);
1388	}
1389
1390	/* Setup VT-x or AMD-V. */
1391	rc = g_HvmR0.pfnSetupVM(pVM);
1392
1393	/* Disable VT-x or AMD-V if local init was done before. */
1394	if (!g_HvmR0.fGlobalInit)
1395	{
1396	int rc2 = hmR0DisableCpu(idCpu);
1397	AssertRC(rc2);
1398	}
1399
1400	ASMAtomicWriteBool(&pCpu->fInUse, false);
1401	ASMSetFlags(fFlags);
1402
1403	return rc;
1404	}
1405
1406
1407	/**
1408	* Enters the VT-x or AMD-V session.
1409	*
1410	* @returns VBox status code.
1411	* @param pVM Pointer to the VM.
1412	* @param pVCpu Pointer to the VMCPU.
1413	*
1414	* @remarks This is called with preemption disabled.
1415	*/
1416	VMMR0_INT_DECL(int) HMR0Enter(PVM pVM, PVMCPU pVCpu)
1417	{
1418	RTCPUID idCpu = RTMpCpuId();
1419	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1420
1421	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1422	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1423	ASMAtomicWriteBool(&pCpu->fInUse, true);
1424
1425	AssertMsg(pVCpu->hm.s.idEnteredCpu == NIL_RTCPUID, ("%d", (int)pVCpu->hm.s.idEnteredCpu));
1426	pVCpu->hm.s.idEnteredCpu = idCpu;
1427
1428	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1429
1430	/* Always load the guest's FPU/XMM state on-demand. */
1431	CPUMDeactivateGuestFPUState(pVCpu);
1432
1433	/* Always load the guest's debug state on-demand. */
1434	CPUMDeactivateGuestDebugState(pVCpu);
1435
1436	/* Always reload the host context and the guest's CR0 register for the FPU
1437	bits (#NM, #MF, CR0.NE, CR0.TS, CR0.MP). */
1438	pVCpu->hm.s.fContextUseFlags \|= HM_CHANGED_GUEST_CR0 \| HM_CHANGED_HOST_CONTEXT;
1439
1440	/* Enable VT-x or AMD-V if local init is required, or enable if it's a
1441	freshly onlined CPU. */
1442	int rc;
1443	if ( !pCpu->fConfigured
1444	\|\| !g_HvmR0.fGlobalInit)
1445	{
1446	rc = hmR0EnableCpu(pVM, idCpu);
1447	AssertRCReturn(rc, rc);
1448	}
1449
1450	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1451	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1452	#endif
1453
1454	rc = g_HvmR0.pfnEnterSession(pVM, pVCpu, pCpu);
1455	AssertRC(rc);
1456	/* We must save the host context here (VT-x) as we might be rescheduled on
1457	a different cpu after a long jump back to ring 3. */
1458	rc \|= g_HvmR0.pfnSaveHostState(pVM, pVCpu);
1459	AssertRC(rc);
1460	rc \|= g_HvmR0.pfnLoadGuestState(pVM, pVCpu, pCtx);
1461	AssertRC(rc);
1462
1463	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1464	if (fStartedSet)
1465	PGMRZDynMapReleaseAutoSet(pVCpu);
1466	#endif
1467
1468	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1469	and ring-3 calls. */
1470	if (RT_FAILURE(rc))
1471	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1472	return rc;
1473	}
1474
1475
1476	/**
1477	* Leaves the VT-x or AMD-V session.
1478	*
1479	* @returns VBox status code.
1480	* @param pVM Pointer to the VM.
1481	* @param pVCpu Pointer to the VMCPU.
1482	*
1483	* @remarks Called with preemption disabled just like HMR0Enter, our
1484	* counterpart.
1485	*/
1486	VMMR0_INT_DECL(int) HMR0Leave(PVM pVM, PVMCPU pVCpu)
1487	{
1488	int rc;
1489	RTCPUID idCpu = RTMpCpuId();
1490	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[idCpu];
1491	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1492
1493	/** @todo r=bird: This can't be entirely right? */
1494	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1495
1496	/*
1497	* Save the guest FPU and XMM state if necessary.
1498	*
1499	* Note! It's rather tricky with longjmps done by e.g. Log statements or
1500	* the page fault handler. We must restore the host FPU here to make
1501	* absolutely sure we don't leave the guest FPU state active or trash
1502	* somebody else's FPU state.
1503	*/
1504	if (CPUMIsGuestFPUStateActive(pVCpu))
1505	{
1506	Log2(("CPUMR0SaveGuestFPU\n"));
1507	CPUMR0SaveGuestFPU(pVM, pVCpu, pCtx);
1508
1509	Assert(!CPUMIsGuestFPUStateActive(pVCpu));
1510	}
1511
1512	rc = g_HvmR0.pfnLeaveSession(pVM, pVCpu, pCtx);
1513
1514	/* We don't pass on invlpg information to the recompiler for nested paging
1515	guests, so we must make sure the recompiler flushes its TLB the next
1516	time it executes code. */
1517	if ( pVM->hm.s.fNestedPaging
1518	#ifdef VBOX_WITH_OLD_VTX_CODE
1519	&& CPUMIsGuestInPagedProtectedModeEx(pCtx)
1520	#else
1521	&& CPUMIsGuestPagingEnabledEx(pCtx)
1522	#endif
1523	)
1524	{
1525	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_GLOBAL_TLB_FLUSH);
1526	}
1527
1528	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness
1529	and ring-3 calls. */
1530	AssertMsgStmt( pVCpu->hm.s.idEnteredCpu == idCpu
1531	\|\| RT_FAILURE_NP(rc),
1532	("Owner is %u, I'm %u", pVCpu->hm.s.idEnteredCpu, idCpu),
1533	rc = VERR_HM_WRONG_CPU_1);
1534	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1535
1536	/*
1537	* Disable VT-x or AMD-V if local init was done before.
1538	*/
1539	if (!g_HvmR0.fGlobalInit)
1540	{
1541	rc = hmR0DisableCpu(idCpu);
1542	AssertRC(rc);
1543
1544	/* Reset these to force a TLB flush for the next entry. (-> EXPENSIVE) */
1545	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1546	pVCpu->hm.s.uCurrentAsid = 0;
1547	VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
1548	}
1549
1550	ASMAtomicWriteBool(&pCpu->fInUse, false);
1551	return rc;
1552	}
1553
1554
1555	/**
1556	* Runs guest code in a hardware accelerated VM.
1557	*
1558	* @returns VBox status code.
1559	* @param pVM Pointer to the VM.
1560	* @param pVCpu Pointer to the VMCPU.
1561	*
1562	* @remarks Called with preemption disabled and after first having called
1563	* HMR0Enter.
1564	*/
1565	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1566	{
1567	#ifdef VBOX_STRICT
1568	PHMGLOBLCPUINFO pCpu = &g_HvmR0.aCpuInfo[RTMpCpuId()];
1569	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1570	Assert(pCpu->fConfigured);
1571	AssertReturn(!ASMAtomicReadBool(&g_HvmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1572	Assert(ASMAtomicReadBool(&pCpu->fInUse) == true);
1573	#endif
1574
1575	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1576	PGMRZDynMapStartAutoSet(pVCpu);
1577	#endif
1578
1579	int rc = g_HvmR0.pfnRunGuestCode(pVM, pVCpu, CPUMQueryGuestCtxPtr(pVCpu));
1580
1581	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1582	PGMRZDynMapReleaseAutoSet(pVCpu);
1583	#endif
1584	return rc;
1585	}
1586
1587	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1588
1589	/**
1590	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1591	*
1592	* @returns VBox status code.
1593	* @param pVM Pointer to the VM.
1594	* @param pVCpu Pointer to the VMCPU.
1595	* @param pCtx Pointer to the guest CPU context.
1596	*/
1597	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1598	{
1599	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1600	if (pVM->hm.s.vmx.fSupported)
1601	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1602	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1603	}
1604
1605
1606	/**
1607	* Save guest debug state (64 bits guest mode & 32 bits host only)
1608	*
1609	* @returns VBox status code.
1610	* @param pVM Pointer to the VM.
1611	* @param pVCpu Pointer to the VMCPU.
1612	* @param pCtx Pointer to the guest CPU context.
1613	*/
1614	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1615	{
1616	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1617	if (pVM->hm.s.vmx.fSupported)
1618	return VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1619	return SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1620	}
1621
1622
1623	/**
1624	* Test the 32->64 bits switcher.
1625	*
1626	* @returns VBox status code.
1627	* @param pVM Pointer to the VM.
1628	*/
1629	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1630	{
1631	PVMCPU pVCpu = &pVM->aCpus[0];
1632	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1633	uint32_t aParam[5] = {0, 1, 2, 3, 4};
1634	int rc;
1635
1636	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1637	if (pVM->hm.s.vmx.fSupported)
1638	rc = VMXR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1639	else
1640	rc = SVMR0Execute64BitsHandler(pVM, pVCpu, pCtx, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1641	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1642
1643	return rc;
1644	}
1645
1646	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL) */
1647
1648	/**
1649	* Returns suspend status of the host.
1650	*
1651	* @returns Suspend pending or not.
1652	*/
1653	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1654	{
1655	return ASMAtomicReadBool(&g_HvmR0.fSuspended);
1656	}
1657
1658
1659	/**
1660	* Returns the cpu structure for the current cpu.
1661	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1662	*
1663	* @returns The cpu structure pointer.
1664	*/
1665	VMMR0DECL(PHMGLOBLCPUINFO) HMR0GetCurrentCpu(void)
1666	{
1667	RTCPUID idCpu = RTMpCpuId();
1668	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1669	return &g_HvmR0.aCpuInfo[idCpu];
1670	}
1671
1672
1673	/**
1674	* Returns the cpu structure for the current cpu.
1675	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1676	*
1677	* @returns The cpu structure pointer.
1678	* @param idCpu id of the VCPU.
1679	*/
1680	VMMR0DECL(PHMGLOBLCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu)
1681	{
1682	Assert(idCpu < RT_ELEMENTS(g_HvmR0.aCpuInfo));
1683	return &g_HvmR0.aCpuInfo[idCpu];
1684	}
1685
1686
1687	/**
1688	* Save a pending IO read.
1689	*
1690	* @param pVCpu Pointer to the VMCPU.
1691	* @param GCPtrRip Address of IO instruction.
1692	* @param GCPtrRipNext Address of the next instruction.
1693	* @param uPort Port address.
1694	* @param uAndVal AND mask for saving the result in eax.
1695	* @param cbSize Read size.
1696	*/
1697	VMMR0_INT_DECL(void) HMR0SavePendingIOPortRead(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1698	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1699	{
1700	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_READ;
1701	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1702	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1703	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1704	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1705	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1706	return;
1707	}
1708
1709
1710	/**
1711	* Save a pending IO write.
1712	*
1713	* @param pVCpu Pointer to the VMCPU.
1714	* @param GCPtrRIP Address of IO instruction.
1715	* @param uPort Port address.
1716	* @param uAndVal AND mask for fetching the result from eax.
1717	* @param cbSize Read size.
1718	*/
1719	VMMR0_INT_DECL(void) HMR0SavePendingIOPortWrite(PVMCPU pVCpu, RTGCPTR GCPtrRip, RTGCPTR GCPtrRipNext,
1720	unsigned uPort, unsigned uAndVal, unsigned cbSize)
1721	{
1722	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_PORT_WRITE;
1723	pVCpu->hm.s.PendingIO.GCPtrRip = GCPtrRip;
1724	pVCpu->hm.s.PendingIO.GCPtrRipNext = GCPtrRipNext;
1725	pVCpu->hm.s.PendingIO.s.Port.uPort = uPort;
1726	pVCpu->hm.s.PendingIO.s.Port.uAndVal = uAndVal;
1727	pVCpu->hm.s.PendingIO.s.Port.cbSize = cbSize;
1728	return;
1729	}
1730
1731
1732	/**
1733	* Raw-mode switcher hook - disable VT-x if it's active and the current
1734	* switcher turns off paging.
1735	*
1736	* @returns VBox status code.
1737	* @param pVM Pointer to the VM.
1738	* @param enmSwitcher The switcher we're about to use.
1739	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1740	*/
1741	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1742	{
1743	Assert(!(ASMGetFlags() & X86_EFL_IF) \|\| !RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1744
1745	*pfVTxDisabled = false;
1746
1747	/* No such issues with AMD-V */
1748	if (!g_HvmR0.vmx.fSupported)
1749	return VINF_SUCCESS;
1750
1751	/* Check if the swithcing we're up to is safe. */
1752	switch (enmSwitcher)
1753	{
1754	case VMMSWITCHER_32_TO_32:
1755	case VMMSWITCHER_PAE_TO_PAE:
1756	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1757
1758	case VMMSWITCHER_32_TO_PAE:
1759	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1760	case VMMSWITCHER_AMD64_TO_32:
1761	case VMMSWITCHER_AMD64_TO_PAE:
1762	break; /* unsafe switchers */
1763
1764	default:
1765	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1766	}
1767
1768	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1769	regardless of whether we're currently using VT-x or not. */
1770	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1771	{
1772	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1773	return VINF_SUCCESS;
1774	}
1775
1776	/** @todo Check if this code is presumtive wrt other VT-x users on the
1777	* system... */
1778
1779	/* Nothing to do if we haven't enabled VT-x. */
1780	if (!g_HvmR0.fEnabled)
1781	return VINF_SUCCESS;
1782
1783	/* Local init implies the CPU is currently not in VMX root mode. */
1784	if (!g_HvmR0.fGlobalInit)
1785	return VINF_SUCCESS;
1786
1787	/* Ok, disable VT-x. */
1788	PHMGLOBLCPUINFO pCpu = HMR0GetCurrentCpu();
1789	AssertReturn(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ, VERR_HM_IPE_2);
1790
1791	*pfVTxDisabled = true;
1792	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1793	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1794	return VMXR0DisableCpu(pCpu, pvCpuPage, HCPhysCpuPage);
1795	}
1796
1797
1798	/**
1799	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1800	* switcher turned off paging.
1801	*
1802	* @param pVM Pointer to the VM.
1803	* @param fVTxDisabled Whether VT-x was disabled or not.
1804	*/
1805	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1806	{
1807	Assert(!(ASMGetFlags() & X86_EFL_IF));
1808
1809	if (!fVTxDisabled)
1810	return; /* nothing to do */
1811
1812	Assert(g_HvmR0.vmx.fSupported);
1813	if (g_HvmR0.vmx.fUsingSUPR0EnableVTx)
1814	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1815	else
1816	{
1817	Assert(g_HvmR0.fEnabled);
1818	Assert(g_HvmR0.fGlobalInit);
1819
1820	PHMGLOBLCPUINFO pCpu = HMR0GetCurrentCpu();
1821	AssertReturnVoid(pCpu && pCpu->hMemObj != NIL_RTR0MEMOBJ);
1822
1823	void *pvCpuPage = RTR0MemObjAddress(pCpu->hMemObj);
1824	RTHCPHYS HCPhysCpuPage = RTR0MemObjGetPagePhysAddr(pCpu->hMemObj, 0);
1825	VMXR0EnableCpu(pCpu, pVM, pvCpuPage, HCPhysCpuPage, false);
1826	}
1827	}
1828
1829	#ifdef VBOX_STRICT
1830
1831	/**
1832	* Dumps a descriptor.
1833	*
1834	* @param pDesc Descriptor to dump.
1835	* @param Sel Selector number.
1836	* @param pszMsg Message to prepend the log entry with.
1837	*/
1838	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1839	{
1840	/*
1841	* Make variable description string.
1842	*/
1843	static struct
1844	{
1845	unsigned cch;
1846	const char *psz;
1847	} const s_aTypes[32] =
1848	{
1849	# define STRENTRY(str) { sizeof(str) - 1, str }
1850
1851	/* system */
1852	# if HC_ARCH_BITS == 64
1853	STRENTRY("Reserved0 "), /* 0x00 */
1854	STRENTRY("Reserved1 "), /* 0x01 */
1855	STRENTRY("LDT "), /* 0x02 */
1856	STRENTRY("Reserved3 "), /* 0x03 */
1857	STRENTRY("Reserved4 "), /* 0x04 */
1858	STRENTRY("Reserved5 "), /* 0x05 */
1859	STRENTRY("Reserved6 "), /* 0x06 */
1860	STRENTRY("Reserved7 "), /* 0x07 */
1861	STRENTRY("Reserved8 "), /* 0x08 */
1862	STRENTRY("TSS64Avail "), /* 0x09 */
1863	STRENTRY("ReservedA "), /* 0x0a */
1864	STRENTRY("TSS64Busy "), /* 0x0b */
1865	STRENTRY("Call64 "), /* 0x0c */
1866	STRENTRY("ReservedD "), /* 0x0d */
1867	STRENTRY("Int64 "), /* 0x0e */
1868	STRENTRY("Trap64 "), /* 0x0f */
1869	# else
1870	STRENTRY("Reserved0 "), /* 0x00 */
1871	STRENTRY("TSS16Avail "), /* 0x01 */
1872	STRENTRY("LDT "), /* 0x02 */
1873	STRENTRY("TSS16Busy "), /* 0x03 */
1874	STRENTRY("Call16 "), /* 0x04 */
1875	STRENTRY("Task "), /* 0x05 */
1876	STRENTRY("Int16 "), /* 0x06 */
1877	STRENTRY("Trap16 "), /* 0x07 */
1878	STRENTRY("Reserved8 "), /* 0x08 */
1879	STRENTRY("TSS32Avail "), /* 0x09 */
1880	STRENTRY("ReservedA "), /* 0x0a */
1881	STRENTRY("TSS32Busy "), /* 0x0b */
1882	STRENTRY("Call32 "), /* 0x0c */
1883	STRENTRY("ReservedD "), /* 0x0d */
1884	STRENTRY("Int32 "), /* 0x0e */
1885	STRENTRY("Trap32 "), /* 0x0f */
1886	# endif
1887	/* non system */
1888	STRENTRY("DataRO "), /* 0x10 */
1889	STRENTRY("DataRO Accessed "), /* 0x11 */
1890	STRENTRY("DataRW "), /* 0x12 */
1891	STRENTRY("DataRW Accessed "), /* 0x13 */
1892	STRENTRY("DataDownRO "), /* 0x14 */
1893	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1894	STRENTRY("DataDownRW "), /* 0x16 */
1895	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1896	STRENTRY("CodeEO "), /* 0x18 */
1897	STRENTRY("CodeEO Accessed "), /* 0x19 */
1898	STRENTRY("CodeER "), /* 0x1a */
1899	STRENTRY("CodeER Accessed "), /* 0x1b */
1900	STRENTRY("CodeConfEO "), /* 0x1c */
1901	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1902	STRENTRY("CodeConfER "), /* 0x1e */
1903	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1904	# undef SYSENTRY
1905	};
1906	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1907	char szMsg[128];
1908	char *psz = &szMsg[0];
1909	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1910	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1911	psz += s_aTypes[i].cch;
1912
1913	if (pDesc->Gen.u1Present)
1914	ADD_STR(psz, "Present ");
1915	else
1916	ADD_STR(psz, "Not-Present ");
1917	# if HC_ARCH_BITS == 64
1918	if (pDesc->Gen.u1Long)
1919	ADD_STR(psz, "64-bit ");
1920	else
1921	ADD_STR(psz, "Comp ");
1922	# else
1923	if (pDesc->Gen.u1Granularity)
1924	ADD_STR(psz, "Page ");
1925	if (pDesc->Gen.u1DefBig)
1926	ADD_STR(psz, "32-bit ");
1927	else
1928	ADD_STR(psz, "16-bit ");
1929	# endif
1930	# undef ADD_STR
1931	*psz = '\0';
1932
1933	/*
1934	* Limit and Base and format the output.
1935	*/
1936	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1937
1938	# if HC_ARCH_BITS == 64
1939	uint64_t u32Base = X86DESC64_BASE(pDesc);
1940
1941	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1942	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1943	# else
1944	uint32_t u32Base = X86DESC_BASE(pDesc);
1945
1946	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1947	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1948	# endif
1949	}
1950
1951
1952	/**
1953	* Formats a full register dump.
1954	*
1955	* @param pVM Pointer to the VM.
1956	* @param pVCpu Pointer to the VMCPU.
1957	* @param pCtx Pointer to the CPU context.
1958	*/
1959	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1960	{
1961	NOREF(pVM);
1962
1963	/*
1964	* Format the flags.
1965	*/
1966	static struct
1967	{
1968	const char pszSet; const char pszClear; uint32_t fFlag;
1969	} const s_aFlags[] =
1970	{
1971	{ "vip",NULL, X86_EFL_VIP },
1972	{ "vif",NULL, X86_EFL_VIF },
1973	{ "ac", NULL, X86_EFL_AC },
1974	{ "vm", NULL, X86_EFL_VM },
1975	{ "rf", NULL, X86_EFL_RF },
1976	{ "nt", NULL, X86_EFL_NT },
1977	{ "ov", "nv", X86_EFL_OF },
1978	{ "dn", "up", X86_EFL_DF },
1979	{ "ei", "di", X86_EFL_IF },
1980	{ "tf", NULL, X86_EFL_TF },
1981	{ "nt", "pl", X86_EFL_SF },
1982	{ "nz", "zr", X86_EFL_ZF },
1983	{ "ac", "na", X86_EFL_AF },
1984	{ "po", "pe", X86_EFL_PF },
1985	{ "cy", "nc", X86_EFL_CF },
1986	};
1987	char szEFlags[80];
1988	char *psz = szEFlags;
1989	uint32_t efl = pCtx->eflags.u32;
1990	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1991	{
1992	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1993	if (pszAdd)
1994	{
1995	strcpy(psz, pszAdd);
1996	psz += strlen(pszAdd);
1997	*psz++ = ' ';
1998	}
1999	}
2000	psz[-1] = '\0';
2001
2002
2003	/*
2004	* Format the registers.
2005	*/
2006	if (CPUMIsGuestIn64BitCode(pVCpu))
2007	{
2008	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
2009	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
2010	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2011	"r14=%016RX64 r15=%016RX64\n"
2012	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
2013	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2014	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2015	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2016	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2017	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2018	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2019	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
2020	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
2021	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
2022	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2023	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2024	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2025	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2026	,
2027	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
2028	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
2029	pCtx->r14, pCtx->r15,
2030	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2031	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2032	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2033	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2034	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2035	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2036	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2037	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
2038	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
2039	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
2040	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2041	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2042	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2043	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2044	}
2045	else
2046	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
2047	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
2048	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
2049	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
2050	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
2051	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
2052	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
2053	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
2054	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2055	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2056	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2057	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2058	,
2059	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2060	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), 31, szEFlags,
2061	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2062	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2063	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2064	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2065	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2066	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2067	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, efl,
2068	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2069	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2070	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2071
2072	Log(("FPU:\n"
2073	"FCW=%04x FSW=%04x FTW=%02x\n"
2074	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2075	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2076	,
2077	pCtx->fpu.FCW, pCtx->fpu.FSW, pCtx->fpu.FTW,
2078	pCtx->fpu.FOP, pCtx->fpu.FPUIP, pCtx->fpu.CS, pCtx->fpu.Rsrvd1,
2079	pCtx->fpu.FPUDP, pCtx->fpu.DS, pCtx->fpu.Rsrvd2,
2080	pCtx->fpu.MXCSR, pCtx->fpu.MXCSR_MASK));
2081
2082
2083	Log(("MSR:\n"
2084	"EFER =%016RX64\n"
2085	"PAT =%016RX64\n"
2086	"STAR =%016RX64\n"
2087	"CSTAR =%016RX64\n"
2088	"LSTAR =%016RX64\n"
2089	"SFMASK =%016RX64\n"
2090	"KERNELGSBASE =%016RX64\n",
2091	pCtx->msrEFER,
2092	pCtx->msrPAT,
2093	pCtx->msrSTAR,
2094	pCtx->msrCSTAR,
2095	pCtx->msrLSTAR,
2096	pCtx->msrSFMASK,
2097	pCtx->msrKERNELGSBASE));
2098
2099	}
2100
2101	#endif /* VBOX_STRICT */
2102

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source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 47565

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