HMR0.cpp@ 73299

Last change on this file since 73299 was 73293, checked in by vboxsync, 6 years ago
VMM, SUPDrv: Nested VMX: bugref:9180 Read VMX true control MSRs, dump them. Remove pVM->hm.cpuid as we for a long time now have cpum.ro.HostFeatures available. Related cleanups and simplifications.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 75.2 KB

Line
1	/* $Id: HMR0.cpp 73293 2018-07-21 15:11:53Z vboxsync $ */
2	/** @file
3	* Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <VBox/vmm/hm.h>
25	#include <VBox/vmm/pgm.h>
26	#include "HMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/vmm/hm_vmx.h>
29	#include <VBox/vmm/hm_svm.h>
30	#include <VBox/vmm/gim.h>
31	#include <VBox/err.h>
32	#include <VBox/log.h>
33	#include <iprt/assert.h>
34	#include <iprt/asm.h>
35	#include <iprt/asm-amd64-x86.h>
36	#include <iprt/cpuset.h>
37	#include <iprt/mem.h>
38	#include <iprt/memobj.h>
39	#include <iprt/once.h>
40	#include <iprt/param.h>
41	#include <iprt/power.h>
42	#include <iprt/string.h>
43	#include <iprt/thread.h>
44	#include <iprt/x86.h>
45	#include "HMVMXR0.h"
46	#include "HMSVMR0.h"
47
48
49	/*********************************************************************************************************************************
50	* Internal Functions *
51	*********************************************************************************************************************************/
52	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
53	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2);
54	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
55	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2);
56	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
57	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
58
59
60	/*********************************************************************************************************************************
61	* Structures and Typedefs *
62	*********************************************************************************************************************************/
63	/**
64	* This is used to manage the status code of a RTMpOnAll in HM.
65	*/
66	typedef struct HMR0FIRSTRC
67	{
68	/** The status code. */
69	int32_t volatile rc;
70	/** The ID of the CPU reporting the first failure. */
71	RTCPUID volatile idCpu;
72	} HMR0FIRSTRC;
73	/** Pointer to a first return code structure. */
74	typedef HMR0FIRSTRC *PHMR0FIRSTRC;
75
76
77	/*********************************************************************************************************************************
78	* Global Variables *
79	*********************************************************************************************************************************/
80	/**
81	* Global data.
82	*/
83	static struct
84	{
85	/** Per CPU globals. */
86	HMGLOBALCPUINFO aCpuInfo[RTCPUSET_MAX_CPUS];
87
88	/** @name Ring-0 method table for AMD-V and VT-x specific operations.
89	* @{ */
90	DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVMCPU pVCpu, PHMGLOBALCPUINFO pHostCpu));
91	DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit));
92	DECLR0CALLBACKMEMBER(int, pfnExportHostState, (PVMCPU pVCpu));
93	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnRunGuestCode, (PVMCPU pVCpu));
94	DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMGLOBALCPUINFO pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
95	bool fEnabledByHost, void *pvArg));
96	DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMGLOBALCPUINFO pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
97	DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVM pVM));
98	DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVM pVM));
99	DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVM pVM));
100	/** @} */
101
102	/** Maximum ASID allowed. */
103	uint32_t uMaxAsid;
104
105	/** VT-x data. */
106	struct
107	{
108	/** Set to by us to indicate VMX is supported by the CPU. */
109	bool fSupported;
110	/** Whether we're using SUPR0EnableVTx or not. */
111	bool fUsingSUPR0EnableVTx;
112	/** Whether we're using the preemption timer or not. */
113	bool fUsePreemptTimer;
114	/** The shift mask employed by the VMX-Preemption timer. */
115	uint8_t cPreemptTimerShift;
116
117	/** Host CR4 value (set by ring-0 VMX init) */
118	uint64_t u64HostCr4;
119	/** Host EFER value (set by ring-0 VMX init) */
120	uint64_t u64HostEfer;
121	/** Host SMM monitor control (used for logging/diagnostics) */
122	uint64_t u64HostSmmMonitorCtl;
123
124	/** VMX MSR values */
125	VMXMSRS Msrs;
126
127	/** Last instruction error. */
128	uint32_t ulLastInstrError;
129
130	/** Set if we've called SUPR0EnableVTx(true) and should disable it during
131	* module termination. */
132	bool fCalledSUPR0EnableVTx;
133	} vmx;
134
135	/** AMD-V information. */
136	struct
137	{
138	/* HWCR MSR (for diagnostics) */
139	uint64_t u64MsrHwcr;
140
141	/** SVM revision. */
142	uint32_t u32Rev;
143
144	/** SVM feature bits from cpuid 0x8000000a */
145	uint32_t u32Features;
146
147	/** Set by us to indicate SVM is supported by the CPU. */
148	bool fSupported;
149	} svm;
150
151	/** Last recorded error code during HM ring-0 init. */
152	int32_t rcInit;
153
154	/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
155	* enabled and disabled each time it's used to execute guest code. */
156	bool fGlobalInit;
157	/** Indicates whether the host is suspending or not. We'll refuse a few
158	* actions when the host is being suspended to speed up the suspending and
159	* avoid trouble. */
160	bool volatile fSuspended;
161
162	/** Whether we've already initialized all CPUs.
163	* @remarks We could check the EnableAllCpusOnce state, but this is
164	* simpler and hopefully easier to understand. */
165	bool fEnabled;
166	/** Serialize initialization in HMR0EnableAllCpus. */
167	RTONCE EnableAllCpusOnce;
168	} g_HmR0;
169
170
171	/**
172	* Initializes a first return code structure.
173	*
174	* @param pFirstRc The structure to init.
175	*/
176	static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
177	{
178	pFirstRc->rc = VINF_SUCCESS;
179	pFirstRc->idCpu = NIL_RTCPUID;
180	}
181
182
183	/**
184	* Try set the status code (success ignored).
185	*
186	* @param pFirstRc The first return code structure.
187	* @param rc The status code.
188	*/
189	static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
190	{
191	if ( RT_FAILURE(rc)
192	&& ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
193	pFirstRc->idCpu = RTMpCpuId();
194	}
195
196
197	/**
198	* Get the status code of a first return code structure.
199	*
200	* @returns The status code; VINF_SUCCESS or error status, no informational or
201	* warning errors.
202	* @param pFirstRc The first return code structure.
203	*/
204	static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
205	{
206	return pFirstRc->rc;
207	}
208
209
210	#ifdef VBOX_STRICT
211	# ifndef DEBUG_bird
212	/**
213	* Get the CPU ID on which the failure status code was reported.
214	*
215	* @returns The CPU ID, NIL_RTCPUID if no failure was reported.
216	* @param pFirstRc The first return code structure.
217	*/
218	static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
219	{
220	return pFirstRc->idCpu;
221	}
222	# endif
223	#endif /* VBOX_STRICT */
224
225
226	/** @name Dummy callback handlers.
227	* @{ */
228
229	static DECLCALLBACK(int) hmR0DummyEnter(PVMCPU pVCpu, PHMGLOBALCPUINFO pHostCpu)
230	{
231	RT_NOREF2(pVCpu, pHostCpu);
232	return VINF_SUCCESS;
233	}
234
235	static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPU pVCpu, bool fGlobalInit)
236	{
237	RT_NOREF3(enmEvent, pVCpu, fGlobalInit);
238	}
239
240	static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMGLOBALCPUINFO pHostCpu, PVM pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
241	bool fEnabledBySystem, void *pvArg)
242	{
243	RT_NOREF6(pHostCpu, pVM, pvCpuPage, HCPhysCpuPage, fEnabledBySystem, pvArg);
244	return VINF_SUCCESS;
245	}
246
247	static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMGLOBALCPUINFO pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
248	{
249	RT_NOREF3(pHostCpu, pvCpuPage, HCPhysCpuPage);
250	return VINF_SUCCESS;
251	}
252
253	static DECLCALLBACK(int) hmR0DummyInitVM(PVM pVM)
254	{
255	RT_NOREF1(pVM);
256	return VINF_SUCCESS;
257	}
258
259	static DECLCALLBACK(int) hmR0DummyTermVM(PVM pVM)
260	{
261	RT_NOREF1(pVM);
262	return VINF_SUCCESS;
263	}
264
265	static DECLCALLBACK(int) hmR0DummySetupVM(PVM pVM)
266	{
267	RT_NOREF1(pVM);
268	return VINF_SUCCESS;
269	}
270
271	static DECLCALLBACK(VBOXSTRICTRC) hmR0DummyRunGuestCode(PVMCPU pVCpu)
272	{
273	RT_NOREF(pVCpu);
274	return VINF_SUCCESS;
275	}
276
277	static DECLCALLBACK(int) hmR0DummyExportHostState(PVMCPU pVCpu)
278	{
279	RT_NOREF1(pVCpu);
280	return VINF_SUCCESS;
281	}
282
283	/** @} */
284
285
286	/**
287	* Checks if the CPU is subject to the "VMX-Preemption Timer Does Not Count
288	* Down at the Rate Specified" erratum.
289	*
290	* Errata names and related steppings:
291	* - BA86 - D0.
292	* - AAX65 - C2.
293	* - AAU65 - C2, K0.
294	* - AAO95 - B1.
295	* - AAT59 - C2.
296	* - AAK139 - D0.
297	* - AAM126 - C0, C1, D0.
298	* - AAN92 - B1.
299	* - AAJ124 - C0, D0.
300	*
301	* - AAP86 - B1.
302	*
303	* Steppings: B1, C0, C1, C2, D0, K0.
304	*
305	* @returns true if subject to it, false if not.
306	*/
307	static bool hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum(void)
308	{
309	uint32_t u = ASMCpuId_EAX(1);
310	u &= ~(RT_BIT_32(14) \| RT_BIT_32(15) \| RT_BIT_32(28) \| RT_BIT_32(29) \| RT_BIT_32(30) \| RT_BIT_32(31));
311	if ( u == UINT32_C(0x000206E6) /* 323344.pdf - BA86 - D0 - Intel Xeon Processor 7500 Series */
312	\|\| u == UINT32_C(0x00020652) /* 323056.pdf - AAX65 - C2 - Intel Xeon Processor L3406 */
313	/* 322814.pdf - AAT59 - C2 - Intel CoreTM i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series */
314	/* 322911.pdf - AAU65 - C2 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
315	\|\| u == UINT32_C(0x00020655) /* 322911.pdf - AAU65 - K0 - Intel CoreTM i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 */
316	\|\| u == UINT32_C(0x000106E5) /* 322373.pdf - AAO95 - B1 - Intel Xeon Processor 3400 Series */
317	/* 322166.pdf - AAN92 - B1 - Intel CoreTM i7-800 and i5-700 Desktop Processor Series */
318	/* 320767.pdf - AAP86 - B1 - Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series */
319	\|\| u == UINT32_C(0x000106A0) /* 321333.pdf - AAM126 - C0 - Intel Xeon Processor 3500 Series Specification */
320	\|\| u == UINT32_C(0x000106A1) /* 321333.pdf - AAM126 - C1 - Intel Xeon Processor 3500 Series Specification */
321	\|\| u == UINT32_C(0x000106A4) /* 320836.pdf - AAJ124 - C0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
322	\|\| u == UINT32_C(0x000106A5) /* 321333.pdf - AAM126 - D0 - Intel Xeon Processor 3500 Series Specification */
323	/* 321324.pdf - AAK139 - D0 - Intel Xeon Processor 5500 Series Specification */
324	/* 320836.pdf - AAJ124 - D0 - Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series */
325	)
326	return true;
327	return false;
328	}
329
330
331	/**
332	* Intel specific initialization code.
333	*
334	* @returns VBox status code (will only fail if out of memory).
335	* @param uFeatEcx Standard cpuid:1 feature ECX leaf.
336	* @param uFeatEdx Standard cpuid:1 feature EDX leaf.
337	*/
338	static int hmR0InitIntel(uint32_t uFeatEcx, uint32_t uFeatEdx)
339	{
340	/*
341	* Check that all the required VT-x features are present.
342	* We also assume all VT-x-enabled CPUs support fxsave/fxrstor.
343	*/
344	if ( (uFeatEcx & X86_CPUID_FEATURE_ECX_VMX)
345	&& (uFeatEdx & X86_CPUID_FEATURE_EDX_MSR)
346	&& (uFeatEdx & X86_CPUID_FEATURE_EDX_FXSR))
347	{
348	/* Read this MSR now as it may be useful for error reporting when initializing VT-x fails. */
349	g_HmR0.vmx.Msrs.u64FeatCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
350
351	/*
352	* First try use native kernel API for controlling VT-x.
353	* (This is only supported by some Mac OS X kernels atm.)
354	*/
355	int rc = g_HmR0.rcInit = SUPR0EnableVTx(true /* fEnable */);
356	g_HmR0.vmx.fUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
357	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
358	{
359	AssertLogRelMsg(rc == VINF_SUCCESS \|\| rc == VERR_VMX_IN_VMX_ROOT_MODE \|\| rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
360	if (RT_SUCCESS(rc))
361	{
362	g_HmR0.vmx.fSupported = true;
363	rc = SUPR0EnableVTx(false /* fEnable */);
364	AssertLogRelRC(rc);
365	}
366	}
367	else
368	{
369	HMR0FIRSTRC FirstRc;
370	hmR0FirstRcInit(&FirstRc);
371	g_HmR0.rcInit = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
372	if (RT_SUCCESS(g_HmR0.rcInit))
373	g_HmR0.rcInit = hmR0FirstRcGetStatus(&FirstRc);
374	}
375	if (RT_SUCCESS(g_HmR0.rcInit))
376	{
377	/* Reread in case it was changed by SUPR0GetVmxUsability(). */
378	g_HmR0.vmx.Msrs.u64FeatCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
379
380	/*
381	* Read all relevant registers and MSRs.
382	*/
383	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
384	g_HmR0.vmx.u64HostEfer = ASMRdMsr(MSR_K6_EFER);
385	g_HmR0.vmx.Msrs.u64Basic = ASMRdMsr(MSR_IA32_VMX_BASIC);
386	/* KVM workaround: Intel SDM section 34.15.5 describes that MSR_IA32_SMM_MONITOR_CTL
387	* depends on bit 49 of MSR_IA32_VMX_BASIC while table 35-2 says that this MSR is
388	* available if either VMX or SMX is supported. */
389	if (MSR_IA32_VMX_BASIC_DUAL_MON(g_HmR0.vmx.Msrs.u64Basic))
390	g_HmR0.vmx.u64HostSmmMonitorCtl = ASMRdMsr(MSR_IA32_SMM_MONITOR_CTL);
391	g_HmR0.vmx.Msrs.PinCtls.u = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
392	g_HmR0.vmx.Msrs.ProcCtls.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
393	g_HmR0.vmx.Msrs.ExitCtls.u = ASMRdMsr(MSR_IA32_VMX_EXIT_CTLS);
394	g_HmR0.vmx.Msrs.EntryCtls.u = ASMRdMsr(MSR_IA32_VMX_ENTRY_CTLS);
395	g_HmR0.vmx.Msrs.u64Misc = ASMRdMsr(MSR_IA32_VMX_MISC);
396	g_HmR0.vmx.Msrs.u64Cr0Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED0);
397	g_HmR0.vmx.Msrs.u64Cr0Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR0_FIXED1);
398	g_HmR0.vmx.Msrs.u64Cr4Fixed0 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED0);
399	g_HmR0.vmx.Msrs.u64Cr4Fixed1 = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
400	g_HmR0.vmx.Msrs.u64VmcsEnum = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
401	if (MSR_IA32_VMX_BASIC_TRUE_CONTROLS(g_HmR0.vmx.Msrs.u64Basic))
402	{
403	g_HmR0.vmx.Msrs.TruePinCtls.u = ASMRdMsr(MSR_IA32_VMX_TRUE_PINBASED_CTLS);
404	g_HmR0.vmx.Msrs.TrueProcCtls.u = ASMRdMsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS);
405	g_HmR0.vmx.Msrs.TrueEntryCtls.u = ASMRdMsr(MSR_IA32_VMX_TRUE_ENTRY_CTLS);
406	g_HmR0.vmx.Msrs.TrueExitCtls.u = ASMRdMsr(MSR_IA32_VMX_TRUE_EXIT_CTLS);
407	}
408
409	/* VPID 16 bits ASID. */
410	g_HmR0.uMaxAsid = 0x10000; /* exclusive */
411
412	if (g_HmR0.vmx.Msrs.ProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
413	{
414	g_HmR0.vmx.Msrs.ProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
415	if (g_HmR0.vmx.Msrs.ProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT \| VMX_VMCS_CTRL_PROC_EXEC2_VPID))
416	g_HmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
417
418	if (g_HmR0.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
419	g_HmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
420	}
421
422	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
423	{
424	/*
425	* Enter root mode
426	*/
427	RTR0MEMOBJ hScatchMemObj;
428	rc = RTR0MemObjAllocCont(&hScatchMemObj, PAGE_SIZE, false /* fExecutable */);
429	if (RT_FAILURE(rc))
430	{
431	LogRel(("hmR0InitIntel: RTR0MemObjAllocCont(,PAGE_SIZE,false) -> %Rrc\n", rc));
432	return rc;
433	}
434
435	void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
436	RTHCPHYS HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
437	ASMMemZeroPage(pvScatchPage);
438
439	/* Set revision dword at the beginning of the structure. */
440	(uint32_t )pvScatchPage = MSR_IA32_VMX_BASIC_VMCS_ID(g_HmR0.vmx.Msrs.u64Basic);
441
442	/* Make sure we don't get rescheduled to another cpu during this probe. */
443	RTCCUINTREG const fEFlags = ASMIntDisableFlags();
444
445	/*
446	* Check CR4.VMXE.
447	*/
448	g_HmR0.vmx.u64HostCr4 = ASMGetCR4();
449	if (!(g_HmR0.vmx.u64HostCr4 & X86_CR4_VMXE))
450	{
451	/* In theory this bit could be cleared behind our back. Which would cause #UD
452	faults when we try to execute the VMX instructions... */
453	ASMSetCR4(g_HmR0.vmx.u64HostCr4 \| X86_CR4_VMXE);
454	}
455
456	/*
457	* The only way of checking if we're in VMX root mode or not is to try and enter it.
458	* There is no instruction or control bit that tells us if we're in VMX root mode.
459	* Therefore, try and enter VMX root mode here.
460	*/
461	rc = VMXEnable(HCPhysScratchPage);
462	if (RT_SUCCESS(rc))
463	{
464	g_HmR0.vmx.fSupported = true;
465	VMXDisable();
466	}
467	else
468	{
469	/*
470	* KVM leaves the CPU in VMX root mode. Not only is this not allowed,
471	* it will crash the host when we enter raw mode, because:
472	*
473	* (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
474	* this bit), and
475	* (b) turning off paging causes a #GP (unavoidable when switching
476	* from long to 32 bits mode or 32 bits to PAE).
477	*
478	* They should fix their code, but until they do we simply refuse to run.
479	*/
480	g_HmR0.rcInit = VERR_VMX_IN_VMX_ROOT_MODE;
481	Assert(g_HmR0.vmx.fSupported == false);
482	}
483
484	/*
485	* Restore CR4 again; don't leave the X86_CR4_VMXE flag set if it was not
486	* set before (some software could incorrectly think it is in VMX mode).
487	*/
488	ASMSetCR4(g_HmR0.vmx.u64HostCr4);
489	ASMSetFlags(fEFlags);
490
491	RTR0MemObjFree(hScatchMemObj, false);
492	}
493
494	if (g_HmR0.vmx.fSupported)
495	{
496	rc = VMXR0GlobalInit();
497	if (RT_FAILURE(rc))
498	g_HmR0.rcInit = rc;
499
500	/*
501	* Install the VT-x methods.
502	*/
503	g_HmR0.pfnEnterSession = VMXR0Enter;
504	g_HmR0.pfnThreadCtxCallback = VMXR0ThreadCtxCallback;
505	g_HmR0.pfnExportHostState = VMXR0ExportHostState;
506	g_HmR0.pfnRunGuestCode = VMXR0RunGuestCode;
507	g_HmR0.pfnEnableCpu = VMXR0EnableCpu;
508	g_HmR0.pfnDisableCpu = VMXR0DisableCpu;
509	g_HmR0.pfnInitVM = VMXR0InitVM;
510	g_HmR0.pfnTermVM = VMXR0TermVM;
511	g_HmR0.pfnSetupVM = VMXR0SetupVM;
512
513	/*
514	* Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
515	* Timer Does Not Count Down at the Rate Specified" erratum.
516	*/
517	if (g_HmR0.vmx.Msrs.PinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
518	{
519	g_HmR0.vmx.fUsePreemptTimer = true;
520	g_HmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HmR0.vmx.Msrs.u64Misc);
521	if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
522	g_HmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
523	}
524	}
525	}
526	#ifdef LOG_ENABLED
527	else
528	SUPR0Printf("hmR0InitIntelCpu failed with rc=%Rrc\n", g_HmR0.rcInit);
529	#endif
530	}
531	else
532	g_HmR0.rcInit = VERR_VMX_NO_VMX;
533	return VINF_SUCCESS;
534	}
535
536
537	/**
538	* AMD-specific initialization code.
539	*
540	* @returns VBox status code.
541	* @param uFeatEdx Standard cpuid:1 feature EDX leaf.
542	* @param uExtFeatEcx Extended cpuid:0x80000001 feature ECX leaf.
543	* @param uMaxExtLeaf Extended cpuid:0x80000000 feature maximum valid leaf.
544	*/
545	static int hmR0InitAmd(uint32_t uFeatEdx, uint32_t uExtFeatEcx, uint32_t uMaxExtLeaf)
546	{
547	/*
548	* Read all SVM MSRs if SVM is available.
549	* We also require all SVM-enabled CPUs to support rdmsr/wrmsr and fxsave/fxrstor.
550	*/
551	int rc;
552	if ( (uExtFeatEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
553	&& (uFeatEdx & X86_CPUID_FEATURE_EDX_MSR)
554	&& (uFeatEdx & X86_CPUID_FEATURE_EDX_FXSR)
555	&& ASMIsValidExtRange(uMaxExtLeaf)
556	&& uMaxExtLeaf >= 0x8000000a)
557	{
558	/* Call the global AMD-V initialization routine. */
559	rc = SVMR0GlobalInit();
560	if (RT_FAILURE(rc))
561	{
562	g_HmR0.rcInit = rc;
563	return rc;
564	}
565
566	/*
567	* Install the AMD-V methods.
568	*/
569	g_HmR0.pfnEnterSession = SVMR0Enter;
570	g_HmR0.pfnThreadCtxCallback = SVMR0ThreadCtxCallback;
571	g_HmR0.pfnExportHostState = SVMR0ExportHostState;
572	g_HmR0.pfnRunGuestCode = SVMR0RunGuestCode;
573	g_HmR0.pfnEnableCpu = SVMR0EnableCpu;
574	g_HmR0.pfnDisableCpu = SVMR0DisableCpu;
575	g_HmR0.pfnInitVM = SVMR0InitVM;
576	g_HmR0.pfnTermVM = SVMR0TermVM;
577	g_HmR0.pfnSetupVM = SVMR0SetupVM;
578
579	/* Query AMD features. */
580	uint32_t u32Dummy;
581	ASMCpuId(0x8000000a, &g_HmR0.svm.u32Rev, &g_HmR0.uMaxAsid, &u32Dummy, &g_HmR0.svm.u32Features);
582
583	/*
584	* We need to check if AMD-V has been properly initialized on all CPUs.
585	* Some BIOSes might do a poor job.
586	*/
587	HMR0FIRSTRC FirstRc;
588	hmR0FirstRcInit(&FirstRc);
589	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
590	AssertRC(rc);
591	if (RT_SUCCESS(rc))
592	rc = hmR0FirstRcGetStatus(&FirstRc);
593	#ifndef DEBUG_bird
594	AssertMsg(rc == VINF_SUCCESS \|\| rc == VERR_SVM_IN_USE,
595	("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
596	#endif
597	if (RT_SUCCESS(rc))
598	{
599	/* Read the HWCR MSR for diagnostics. */
600	g_HmR0.svm.u64MsrHwcr = ASMRdMsr(MSR_K8_HWCR);
601	g_HmR0.svm.fSupported = true;
602	}
603	else
604	{
605	g_HmR0.rcInit = rc;
606	if (rc == VERR_SVM_DISABLED \|\| rc == VERR_SVM_IN_USE)
607	rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
608	}
609	}
610	else
611	{
612	/* Don't fail if AMD-V is not supported. See @bugref{6785}. */
613	rc = VINF_SUCCESS;
614	g_HmR0.rcInit = VERR_SVM_NO_SVM;
615	}
616	return rc;
617	}
618
619
620	/**
621	* Does global Ring-0 HM initialization (at module init).
622	*
623	* @returns VBox status code.
624	*/
625	VMMR0_INT_DECL(int) HMR0Init(void)
626	{
627	/*
628	* Initialize the globals.
629	*/
630	g_HmR0.fEnabled = false;
631	static RTONCE s_OnceInit = RTONCE_INITIALIZER;
632	g_HmR0.EnableAllCpusOnce = s_OnceInit;
633	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
634	{
635	g_HmR0.aCpuInfo[i].idCpu = NIL_RTCPUID;
636	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
637	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
638	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
639	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
640	g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
641	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
642	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
643	#endif
644	}
645
646	/* Fill in all callbacks with placeholders. */
647	g_HmR0.pfnEnterSession = hmR0DummyEnter;
648	g_HmR0.pfnThreadCtxCallback = hmR0DummyThreadCtxCallback;
649	g_HmR0.pfnExportHostState = hmR0DummyExportHostState;
650	g_HmR0.pfnRunGuestCode = hmR0DummyRunGuestCode;
651	g_HmR0.pfnEnableCpu = hmR0DummyEnableCpu;
652	g_HmR0.pfnDisableCpu = hmR0DummyDisableCpu;
653	g_HmR0.pfnInitVM = hmR0DummyInitVM;
654	g_HmR0.pfnTermVM = hmR0DummyTermVM;
655	g_HmR0.pfnSetupVM = hmR0DummySetupVM;
656
657	/* Default is global VT-x/AMD-V init. */
658	g_HmR0.fGlobalInit = true;
659
660	/*
661	* Make sure aCpuInfo is big enough for all the CPUs on this system.
662	*/
663	if (RTMpGetArraySize() > RT_ELEMENTS(g_HmR0.aCpuInfo))
664	{
665	LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_HmR0.aCpuInfo)));
666	return VERR_TOO_MANY_CPUS;
667	}
668
669	/*
670	* Check for VT-x and AMD-V capabilities.
671	*/
672	int rc;
673	if (ASMHasCpuId())
674	{
675	/* Standard features. */
676	uint32_t uMaxLeaf, uVendorEbx, uVendorEcx, uVendorEdx;
677	ASMCpuId(0, &uMaxLeaf, &uVendorEbx, &uVendorEcx, &uVendorEdx);
678	if (ASMIsValidStdRange(uMaxLeaf))
679	{
680	uint32_t uFeatEcx, uFeatEdx, uDummy;
681	ASMCpuId(1, &uDummy, &uDummy, &uFeatEcx, &uFeatEdx);
682
683	/* Go to CPU specific initialization code. */
684	if ( ASMIsIntelCpuEx(uVendorEbx, uVendorEcx, uVendorEdx)
685	\|\| ASMIsViaCentaurCpuEx(uVendorEbx, uVendorEcx, uVendorEdx))
686	{
687	rc = hmR0InitIntel(uFeatEcx, uFeatEdx);
688	if (RT_FAILURE(rc))
689	return rc;
690	}
691	else if (ASMIsAmdCpuEx(uVendorEbx, uVendorEcx, uVendorEdx))
692	{
693	/* Query extended features for SVM capability. */
694	uint32_t uExtFeatEcx;
695	uint32_t const uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
696	if (ASMIsValidExtRange(uMaxExtLeaf))
697	ASMCpuId(0x80000001, &uDummy, &uDummy, &uExtFeatEcx, &uDummy);
698	else
699	uExtFeatEcx = 0;
700
701	rc = hmR0InitAmd(uFeatEdx, uExtFeatEcx, uMaxExtLeaf);
702	if (RT_FAILURE(rc))
703	return rc;
704	}
705	else
706	g_HmR0.rcInit = VERR_HM_UNKNOWN_CPU;
707	}
708	else
709	g_HmR0.rcInit = VERR_HM_UNKNOWN_CPU;
710	}
711	else
712	g_HmR0.rcInit = VERR_HM_NO_CPUID;
713
714	/*
715	* Register notification callbacks that we can use to disable/enable CPUs
716	* when brought offline/online or suspending/resuming.
717	*/
718	if (!g_HmR0.vmx.fUsingSUPR0EnableVTx)
719	{
720	rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
721	AssertRC(rc);
722
723	rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
724	AssertRC(rc);
725	}
726
727	/* We return success here because module init shall not fail if HM
728	fails to initialize. */
729	return VINF_SUCCESS;
730	}
731
732
733	/**
734	* Does global Ring-0 HM termination (at module termination).
735	*
736	* @returns VBox status code.
737	*/
738	VMMR0_INT_DECL(int) HMR0Term(void)
739	{
740	int rc;
741	if ( g_HmR0.vmx.fSupported
742	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
743	{
744	/*
745	* Simple if the host OS manages VT-x.
746	*/
747	Assert(g_HmR0.fGlobalInit);
748
749	if (g_HmR0.vmx.fCalledSUPR0EnableVTx)
750	{
751	rc = SUPR0EnableVTx(false /* fEnable */);
752	g_HmR0.vmx.fCalledSUPR0EnableVTx = false;
753	}
754	else
755	rc = VINF_SUCCESS;
756
757	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_HmR0.aCpuInfo); iCpu++)
758	{
759	g_HmR0.aCpuInfo[iCpu].fConfigured = false;
760	Assert(g_HmR0.aCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
761	}
762	}
763	else
764	{
765	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
766
767	/* Doesn't really matter if this fails. */
768	rc = RTMpNotificationDeregister(hmR0MpEventCallback, NULL); AssertRC(rc);
769	rc = RTPowerNotificationDeregister(hmR0PowerCallback, NULL); AssertRC(rc);
770
771	/*
772	* Disable VT-x/AMD-V on all CPUs if we enabled it before.
773	*/
774	if (g_HmR0.fGlobalInit)
775	{
776	HMR0FIRSTRC FirstRc;
777	hmR0FirstRcInit(&FirstRc);
778	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
779	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
780	if (RT_SUCCESS(rc))
781	rc = hmR0FirstRcGetStatus(&FirstRc);
782	}
783
784	/*
785	* Free the per-cpu pages used for VT-x and AMD-V.
786	*/
787	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
788	{
789	if (g_HmR0.aCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
790	{
791	RTR0MemObjFree(g_HmR0.aCpuInfo[i].hMemObj, false);
792	g_HmR0.aCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
793	g_HmR0.aCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
794	g_HmR0.aCpuInfo[i].pvMemObj = NULL;
795	}
796	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
797	if (g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm != NIL_RTR0MEMOBJ)
798	{
799	RTR0MemObjFree(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, false);
800	g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
801	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
802	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
803	}
804	#endif
805	}
806	}
807
808	/** @todo This needs cleaning up. There's no matching
809	* hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
810	* should move into their respective modules. */
811	/* Finally, call global VT-x/AMD-V termination. */
812	if (g_HmR0.vmx.fSupported)
813	VMXR0GlobalTerm();
814	else if (g_HmR0.svm.fSupported)
815	SVMR0GlobalTerm();
816
817	return rc;
818	}
819
820
821	/**
822	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
823	* on a CPU.
824	*
825	* @param idCpu The identifier for the CPU the function is called on.
826	* @param pvUser1 Pointer to the first RC structure.
827	* @param pvUser2 Ignored.
828	*/
829	static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
830	{
831	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
832	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
833	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
834	NOREF(idCpu); NOREF(pvUser2);
835
836	int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
837	hmR0FirstRcSetStatus(pFirstRc, rc);
838	}
839
840
841	/**
842	* Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
843	* on a CPU.
844	*
845	* @param idCpu The identifier for the CPU the function is called on.
846	* @param pvUser1 Pointer to the first RC structure.
847	* @param pvUser2 Ignored.
848	*/
849	static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void pvUser1, void pvUser2)
850	{
851	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
852	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
853	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
854	NOREF(idCpu); NOREF(pvUser2);
855
856	int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
857	hmR0FirstRcSetStatus(pFirstRc, rc);
858	}
859
860
861	/**
862	* Enable VT-x or AMD-V on the current CPU
863	*
864	* @returns VBox status code.
865	* @param pVM The cross context VM structure. Can be NULL.
866	* @param idCpu The identifier for the CPU the function is called on.
867	*
868	* @remarks Maybe called with interrupts disabled!
869	*/
870	static int hmR0EnableCpu(PVM pVM, RTCPUID idCpu)
871	{
872	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[idCpu];
873
874	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
875	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
876	Assert(!pHostCpu->fConfigured);
877	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
878
879	pHostCpu->idCpu = idCpu;
880	/* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
881
882	int rc;
883	if (g_HmR0.vmx.fSupported && g_HmR0.vmx.fUsingSUPR0EnableVTx)
884	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmR0.vmx.Msrs);
885	else
886	{
887	AssertLogRelMsgReturn(pHostCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
888	if (g_HmR0.vmx.fSupported)
889	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, &g_HmR0.vmx.Msrs);
890	else
891	rc = g_HmR0.pfnEnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, NULL /* pvArg */);
892	}
893	if (RT_SUCCESS(rc))
894	pHostCpu->fConfigured = true;
895
896	return rc;
897	}
898
899
900	/**
901	* Worker function passed to RTMpOnAll() that is to be called on all CPUs.
902	*
903	* @param idCpu The identifier for the CPU the function is called on.
904	* @param pvUser1 Opaque pointer to the VM (can be NULL!).
905	* @param pvUser2 The 2nd user argument.
906	*/
907	static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
908	{
909	PVM pVM = (PVM)pvUser1; /* can be NULL! */
910	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
911	AssertReturnVoid(g_HmR0.fGlobalInit);
912	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
913	hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
914	}
915
916
917	/**
918	* RTOnce callback employed by HMR0EnableAllCpus.
919	*
920	* @returns VBox status code.
921	* @param pvUser Pointer to the VM.
922	*/
923	static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
924	{
925	PVM pVM = (PVM)pvUser;
926
927	/*
928	* Indicate that we've initialized.
929	*
930	* Note! There is a potential race between this function and the suspend
931	* notification. Kind of unlikely though, so ignored for now.
932	*/
933	AssertReturn(!g_HmR0.fEnabled, VERR_HM_ALREADY_ENABLED_IPE);
934	ASMAtomicWriteBool(&g_HmR0.fEnabled, true);
935
936	/*
937	* The global init variable is set by the first VM.
938	*/
939	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit;
940
941	#ifdef VBOX_STRICT
942	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
943	{
944	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
945	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj == NIL_RTHCPHYS);
946	Assert(g_HmR0.aCpuInfo[i].pvMemObj == NULL);
947	Assert(!g_HmR0.aCpuInfo[i].fConfigured);
948	Assert(!g_HmR0.aCpuInfo[i].cTlbFlushes);
949	Assert(!g_HmR0.aCpuInfo[i].uCurrentAsid);
950	# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
951	Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
952	Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm == NIL_RTHCPHYS);
953	Assert(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm == NULL);
954	# endif
955	}
956	#endif
957
958	int rc;
959	if ( g_HmR0.vmx.fSupported
960	&& g_HmR0.vmx.fUsingSUPR0EnableVTx)
961	{
962	/*
963	* Global VT-x initialization API (only darwin for now).
964	*/
965	rc = SUPR0EnableVTx(true /* fEnable */);
966	if (RT_SUCCESS(rc))
967	{
968	g_HmR0.vmx.fCalledSUPR0EnableVTx = true;
969	/* If the host provides a VT-x init API, then we'll rely on that for global init. */
970	g_HmR0.fGlobalInit = pVM->hm.s.fGlobalInit = true;
971	}
972	else
973	AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
974	}
975	else
976	{
977	/*
978	* We're doing the job ourselves.
979	*/
980	/* Allocate one page per cpu for the global VT-x and AMD-V pages */
981	for (unsigned i = 0; i < RT_ELEMENTS(g_HmR0.aCpuInfo); i++)
982	{
983	Assert(g_HmR0.aCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
984	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
985	Assert(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
986	#endif
987	if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
988	{
989	/** @todo NUMA */
990	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].hMemObj, PAGE_SIZE, false /* executable R0 mapping */);
991	AssertLogRelRCReturn(rc, rc);
992
993	g_HmR0.aCpuInfo[i].HCPhysMemObj = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].hMemObj, 0);
994	Assert(g_HmR0.aCpuInfo[i].HCPhysMemObj != NIL_RTHCPHYS);
995	Assert(!(g_HmR0.aCpuInfo[i].HCPhysMemObj & PAGE_OFFSET_MASK));
996
997	g_HmR0.aCpuInfo[i].pvMemObj = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].hMemObj);
998	AssertPtr(g_HmR0.aCpuInfo[i].pvMemObj);
999	ASMMemZeroPage(g_HmR0.aCpuInfo[i].pvMemObj);
1000
1001	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1002	rc = RTR0MemObjAllocCont(&g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
1003	false /* executable R0 mapping */);
1004	AssertLogRelRCReturn(rc, rc);
1005
1006	g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm = RTR0MemObjGetPagePhysAddr(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm, 0);
1007	Assert(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm != NIL_RTHCPHYS);
1008	Assert(!(g_HmR0.aCpuInfo[i].n.svm.HCPhysNstGstMsrpm & PAGE_OFFSET_MASK));
1009
1010	g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm = RTR0MemObjAddress(g_HmR0.aCpuInfo[i].n.svm.hNstGstMsrpm);
1011	AssertPtr(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm);
1012	ASMMemFill32(g_HmR0.aCpuInfo[i].n.svm.pvNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
1013	#endif
1014	}
1015	}
1016
1017	rc = VINF_SUCCESS;
1018	}
1019
1020	if ( RT_SUCCESS(rc)
1021	&& g_HmR0.fGlobalInit)
1022	{
1023	/* First time, so initialize each cpu/core. */
1024	HMR0FIRSTRC FirstRc;
1025	hmR0FirstRcInit(&FirstRc);
1026	rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
1027	if (RT_SUCCESS(rc))
1028	rc = hmR0FirstRcGetStatus(&FirstRc);
1029	}
1030
1031	return rc;
1032	}
1033
1034
1035	/**
1036	* Sets up HM on all cpus.
1037	*
1038	* @returns VBox status code.
1039	* @param pVM The cross context VM structure.
1040	*/
1041	VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVM pVM)
1042	{
1043	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1044	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1045	return VERR_HM_SUSPEND_PENDING;
1046
1047	return RTOnce(&g_HmR0.EnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1048	}
1049
1050
1051	/**
1052	* Disable VT-x or AMD-V on the current CPU.
1053	*
1054	* @returns VBox status code.
1055	* @param idCpu The identifier for the CPU this function is called on.
1056	*
1057	* @remarks Must be called with preemption disabled.
1058	*/
1059	static int hmR0DisableCpu(RTCPUID idCpu)
1060	{
1061	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1062
1063	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1064	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1065	Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
1066	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1067	Assert(!pHostCpu->fConfigured \|\| pHostCpu->hMemObj != NIL_RTR0MEMOBJ);
1068	AssertRelease(idCpu == RTMpCpuId());
1069
1070	if (pHostCpu->hMemObj == NIL_RTR0MEMOBJ)
1071	return pHostCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1072	AssertPtr(pHostCpu->pvMemObj);
1073	Assert(pHostCpu->HCPhysMemObj != NIL_RTHCPHYS);
1074
1075	int rc;
1076	if (pHostCpu->fConfigured)
1077	{
1078	rc = g_HmR0.pfnDisableCpu(pHostCpu, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj);
1079	AssertRCReturn(rc, rc);
1080
1081	pHostCpu->fConfigured = false;
1082	pHostCpu->idCpu = NIL_RTCPUID;
1083	}
1084	else
1085	rc = VINF_SUCCESS; /* nothing to do */
1086	return rc;
1087	}
1088
1089
1090	/**
1091	* Worker function passed to RTMpOnAll() that is to be called on the target
1092	* CPUs.
1093	*
1094	* @param idCpu The identifier for the CPU the function is called on.
1095	* @param pvUser1 The 1st user argument.
1096	* @param pvUser2 Opaque pointer to the FirstRc.
1097	*/
1098	static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1099	{
1100	PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1101	AssertReturnVoid(g_HmR0.fGlobalInit);
1102	hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1103	}
1104
1105
1106	/**
1107	* Worker function passed to RTMpOnSpecific() that is to be called on the target
1108	* CPU.
1109	*
1110	* @param idCpu The identifier for the CPU the function is called on.
1111	* @param pvUser1 Null, not used.
1112	* @param pvUser2 Null, not used.
1113	*/
1114	static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void pvUser1, void pvUser2)
1115	{
1116	NOREF(pvUser1);
1117	NOREF(pvUser2);
1118	hmR0DisableCpu(idCpu);
1119	}
1120
1121
1122	/**
1123	* Callback function invoked when a cpu goes online or offline.
1124	*
1125	* @param enmEvent The Mp event.
1126	* @param idCpu The identifier for the CPU the function is called on.
1127	* @param pvData Opaque data (PVM pointer).
1128	*/
1129	static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1130	{
1131	NOREF(pvData);
1132	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1133
1134	/*
1135	* We only care about uninitializing a CPU that is going offline. When a
1136	* CPU comes online, the initialization is done lazily in HMR0Enter().
1137	*/
1138	switch (enmEvent)
1139	{
1140	case RTMPEVENT_OFFLINE:
1141	{
1142	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1143	RTThreadPreemptDisable(&PreemptState);
1144	if (idCpu == RTMpCpuId())
1145	{
1146	int rc = hmR0DisableCpu(idCpu);
1147	AssertRC(rc);
1148	RTThreadPreemptRestore(&PreemptState);
1149	}
1150	else
1151	{
1152	RTThreadPreemptRestore(&PreemptState);
1153	RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 /, NULL / pvUser2 */);
1154	}
1155	break;
1156	}
1157
1158	default:
1159	break;
1160	}
1161	}
1162
1163
1164	/**
1165	* Called whenever a system power state change occurs.
1166	*
1167	* @param enmEvent The Power event.
1168	* @param pvUser User argument.
1169	*/
1170	static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1171	{
1172	NOREF(pvUser);
1173	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1174
1175	#ifdef LOG_ENABLED
1176	if (enmEvent == RTPOWEREVENT_SUSPEND)
1177	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1178	else
1179	SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1180	#endif
1181
1182	if (enmEvent == RTPOWEREVENT_SUSPEND)
1183	ASMAtomicWriteBool(&g_HmR0.fSuspended, true);
1184
1185	if (g_HmR0.fEnabled)
1186	{
1187	int rc;
1188	HMR0FIRSTRC FirstRc;
1189	hmR0FirstRcInit(&FirstRc);
1190
1191	if (enmEvent == RTPOWEREVENT_SUSPEND)
1192	{
1193	if (g_HmR0.fGlobalInit)
1194	{
1195	/* Turn off VT-x or AMD-V on all CPUs. */
1196	rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1197	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1198	}
1199	/* else nothing to do here for the local init case */
1200	}
1201	else
1202	{
1203	/* Reinit the CPUs from scratch as the suspend state might have
1204	messed with the MSRs. (lousy BIOSes as usual) */
1205	if (g_HmR0.vmx.fSupported)
1206	rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1207	else
1208	rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1209	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1210	if (RT_SUCCESS(rc))
1211	rc = hmR0FirstRcGetStatus(&FirstRc);
1212	#ifdef LOG_ENABLED
1213	if (RT_FAILURE(rc))
1214	SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1215	#endif
1216	if (g_HmR0.fGlobalInit)
1217	{
1218	/* Turn VT-x or AMD-V back on on all CPUs. */
1219	rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM /, &FirstRc / output ignored */);
1220	Assert(RT_SUCCESS(rc) \|\| rc == VERR_NOT_SUPPORTED);
1221	}
1222	/* else nothing to do here for the local init case */
1223	}
1224	}
1225
1226	if (enmEvent == RTPOWEREVENT_RESUME)
1227	ASMAtomicWriteBool(&g_HmR0.fSuspended, false);
1228	}
1229
1230
1231	/**
1232	* Does ring-0 per-VM HM initialization.
1233	*
1234	* This will copy HM global into the VM structure and call the CPU specific
1235	* init routine which will allocate resources for each virtual CPU and such.
1236	*
1237	* @returns VBox status code.
1238	* @param pVM The cross context VM structure.
1239	*
1240	* @remarks This is called after HMR3Init(), see vmR3CreateU() and
1241	* vmR3InitRing3().
1242	*/
1243	VMMR0_INT_DECL(int) HMR0InitVM(PVM pVM)
1244	{
1245	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1246
1247	#ifdef LOG_ENABLED
1248	SUPR0Printf("HMR0InitVM: %p\n", pVM);
1249	#endif
1250
1251	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1252	if (ASMAtomicReadBool(&g_HmR0.fSuspended))
1253	return VERR_HM_SUSPEND_PENDING;
1254
1255	/*
1256	* Copy globals to the VM structure.
1257	*/
1258	pVM->hm.s.vmx.fSupported = g_HmR0.vmx.fSupported;
1259	pVM->hm.s.svm.fSupported = g_HmR0.svm.fSupported;
1260	Assert(!(pVM->hm.s.vmx.fSupported && pVM->hm.s.svm.fSupported));
1261	if (pVM->hm.s.vmx.fSupported)
1262	{
1263	pVM->hm.s.vmx.fUsePreemptTimer &= g_HmR0.vmx.fUsePreemptTimer; /* Can be overridden by CFGM. See HMR3Init(). */
1264	pVM->hm.s.vmx.cPreemptTimerShift = g_HmR0.vmx.cPreemptTimerShift;
1265	pVM->hm.s.vmx.u64HostCr4 = g_HmR0.vmx.u64HostCr4;
1266	pVM->hm.s.vmx.u64HostEfer = g_HmR0.vmx.u64HostEfer;
1267	pVM->hm.s.vmx.u64HostSmmMonitorCtl = g_HmR0.vmx.u64HostSmmMonitorCtl;
1268	pVM->hm.s.vmx.Msrs = g_HmR0.vmx.Msrs;
1269	}
1270	else if (pVM->hm.s.svm.fSupported)
1271	{
1272	pVM->hm.s.svm.u64MsrHwcr = g_HmR0.svm.u64MsrHwcr;
1273	pVM->hm.s.svm.u32Rev = g_HmR0.svm.u32Rev;
1274	pVM->hm.s.svm.u32Features = g_HmR0.svm.u32Features;
1275	}
1276	pVM->hm.s.rcInit = g_HmR0.rcInit;
1277	pVM->hm.s.uMaxAsid = g_HmR0.uMaxAsid;
1278
1279	/*
1280	* Set default maximum inner loops in ring-0 before returning to ring-3.
1281	* Can be overriden using CFGM.
1282	*/
1283	if (!pVM->hm.s.cMaxResumeLoops)
1284	{
1285	pVM->hm.s.cMaxResumeLoops = 1024;
1286	if (RTThreadPreemptIsPendingTrusty())
1287	pVM->hm.s.cMaxResumeLoops = 8192;
1288	}
1289
1290	/*
1291	* Initialize some per-VCPU fields.
1292	*/
1293	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1294	{
1295	PVMCPU pVCpu = &pVM->aCpus[i];
1296	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1297	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1298	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
1299
1300	/* We'll aways increment this the first time (host uses ASID 0). */
1301	AssertReturn(!pVCpu->hm.s.uCurrentAsid, VERR_HM_IPE_3);
1302	}
1303
1304	pVM->hm.s.fHostKernelFeatures = SUPR0GetKernelFeatures();
1305
1306	/*
1307	* Call the hardware specific initialization method.
1308	*/
1309	return g_HmR0.pfnInitVM(pVM);
1310	}
1311
1312
1313	/**
1314	* Does ring-0 per VM HM termination.
1315	*
1316	* @returns VBox status code.
1317	* @param pVM The cross context VM structure.
1318	*/
1319	VMMR0_INT_DECL(int) HMR0TermVM(PVM pVM)
1320	{
1321	Log(("HMR0TermVM: %p\n", pVM));
1322	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1323
1324	/*
1325	* Call the hardware specific method.
1326	*
1327	* Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1328	* mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1329	*/
1330	return g_HmR0.pfnTermVM(pVM);
1331	}
1332
1333
1334	/**
1335	* Sets up a VT-x or AMD-V session.
1336	*
1337	* This is mostly about setting up the hardware VM state.
1338	*
1339	* @returns VBox status code.
1340	* @param pVM The cross context VM structure.
1341	*/
1342	VMMR0_INT_DECL(int) HMR0SetupVM(PVM pVM)
1343	{
1344	Log(("HMR0SetupVM: %p\n", pVM));
1345	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1346
1347	/* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1348	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1349
1350	/* On first entry we'll sync everything. */
1351	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1352	{
1353	PVMCPU pVCpu = &pVM->aCpus[i];
1354	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
1355	}
1356
1357	/*
1358	* Call the hardware specific setup VM method. This requires the CPU to be
1359	* enabled for AMD-V/VT-x and preemption to be prevented.
1360	*/
1361	RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1362	RTThreadPreemptDisable(&PreemptState);
1363	RTCPUID const idCpu = RTMpCpuId();
1364
1365	/* Enable VT-x or AMD-V if local init is required. */
1366	int rc;
1367	if (!g_HmR0.fGlobalInit)
1368	{
1369	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1370	rc = hmR0EnableCpu(pVM, idCpu);
1371	if (RT_FAILURE(rc))
1372	{
1373	RTThreadPreemptRestore(&PreemptState);
1374	return rc;
1375	}
1376	}
1377
1378	/* Setup VT-x or AMD-V. */
1379	rc = g_HmR0.pfnSetupVM(pVM);
1380
1381	/* Disable VT-x or AMD-V if local init was done before. */
1382	if (!g_HmR0.fGlobalInit)
1383	{
1384	Assert(!g_HmR0.vmx.fSupported \|\| !g_HmR0.vmx.fUsingSUPR0EnableVTx);
1385	int rc2 = hmR0DisableCpu(idCpu);
1386	AssertRC(rc2);
1387	}
1388
1389	RTThreadPreemptRestore(&PreemptState);
1390	return rc;
1391	}
1392
1393
1394	/**
1395	* Turns on HM on the CPU if necessary and initializes the bare minimum state
1396	* required for entering HM context.
1397	*
1398	* @returns VBox status code.
1399	* @param pVCpu The cross context virtual CPU structure.
1400	*
1401	* @remarks No-long-jump zone!!!
1402	*/
1403	VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPU pVCpu)
1404	{
1405	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1406
1407	int rc = VINF_SUCCESS;
1408	RTCPUID const idCpu = RTMpCpuId();
1409	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1410	AssertPtr(pHostCpu);
1411
1412	/* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1413	if (!pHostCpu->fConfigured)
1414	rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1415
1416	/* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1417	if (g_HmR0.vmx.fSupported)
1418	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE;
1419	else
1420	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE;
1421
1422	Assert(pHostCpu->idCpu == idCpu && pHostCpu->idCpu != NIL_RTCPUID);
1423	pVCpu->hm.s.idEnteredCpu = idCpu;
1424	return rc;
1425	}
1426
1427
1428	/**
1429	* Enters the VT-x or AMD-V session.
1430	*
1431	* @returns VBox status code.
1432	* @param pVCpu The cross context virtual CPU structure.
1433	*
1434	* @remarks This is called with preemption disabled.
1435	*/
1436	VMMR0_INT_DECL(int) HMR0Enter(PVMCPU pVCpu)
1437	{
1438	/* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1439	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1440	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1441
1442	/* Load the bare minimum state required for entering HM. */
1443	int rc = hmR0EnterCpu(pVCpu);
1444	AssertRCReturn(rc, rc);
1445
1446	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1447	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_5);
1448	bool fStartedSet = PGMR0DynMapStartOrMigrateAutoSet(pVCpu);
1449	#endif
1450
1451	RTCPUID const idCpu = RTMpCpuId();
1452	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1453	Assert(pHostCpu);
1454	if (g_HmR0.vmx.fSupported)
1455	{
1456	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
1457	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
1458	}
1459	else
1460	{
1461	Assert((pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
1462	== (HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
1463	}
1464
1465	rc = g_HmR0.pfnEnterSession(pVCpu, pHostCpu);
1466	AssertMsgRCReturn(rc, ("rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1467
1468	/* Exports the host-state as we may be resuming code after a longjmp and quite
1469	possibly now be scheduled on a different CPU. */
1470	rc = g_HmR0.pfnExportHostState(pVCpu);
1471	AssertMsgRCReturn(rc, ("rc=%Rrc pVCpu=%p HostCpuId=%u\n", rc, pVCpu, idCpu), rc);
1472
1473	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1474	if (fStartedSet)
1475	PGMRZDynMapReleaseAutoSet(pVCpu);
1476	#endif
1477
1478	/* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1479	if (RT_FAILURE(rc))
1480	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1481	return rc;
1482	}
1483
1484
1485	/**
1486	* Deinitializes the bare minimum state used for HM context and if necessary
1487	* disable HM on the CPU.
1488	*
1489	* @returns VBox status code.
1490	* @param pVCpu The cross context virtual CPU structure.
1491	*
1492	* @remarks No-long-jump zone!!!
1493	*/
1494	VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPU pVCpu)
1495	{
1496	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1497	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1498
1499	RTCPUID const idCpu = RTMpCpuId();
1500	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[idCpu];
1501
1502	if ( !g_HmR0.fGlobalInit
1503	&& pHostCpu->fConfigured)
1504	{
1505	int rc = hmR0DisableCpu(idCpu);
1506	AssertRCReturn(rc, rc);
1507	Assert(!pHostCpu->fConfigured);
1508	Assert(pHostCpu->idCpu == NIL_RTCPUID);
1509
1510	/* For obtaining a non-zero ASID/VPID on next re-entry. */
1511	pVCpu->hm.s.idLastCpu = NIL_RTCPUID;
1512	}
1513
1514	/* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1515	pVCpu->hm.s.idEnteredCpu = NIL_RTCPUID;
1516
1517	return VINF_SUCCESS;
1518	}
1519
1520
1521	/**
1522	* Thread-context hook for HM.
1523	*
1524	* @param enmEvent The thread-context event.
1525	* @param pvUser Opaque pointer to the VMCPU.
1526	*/
1527	VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1528	{
1529	PVMCPU pVCpu = (PVMCPU)pvUser;
1530	Assert(pVCpu);
1531	Assert(g_HmR0.pfnThreadCtxCallback);
1532
1533	g_HmR0.pfnThreadCtxCallback(enmEvent, pVCpu, g_HmR0.fGlobalInit);
1534	}
1535
1536
1537	/**
1538	* Runs guest code in a hardware accelerated VM.
1539	*
1540	* @returns Strict VBox status code. (VBOXSTRICTRC isn't used because it's
1541	* called from setjmp assembly.)
1542	* @param pVM The cross context VM structure.
1543	* @param pVCpu The cross context virtual CPU structure.
1544	*
1545	* @remarks Can be called with preemption enabled if thread-context hooks are
1546	* used!!!
1547	*/
1548	VMMR0_INT_DECL(int) HMR0RunGuestCode(PVM pVM, PVMCPU pVCpu)
1549	{
1550	RT_NOREF(pVM);
1551
1552	#ifdef VBOX_STRICT
1553	/* With thread-context hooks we would be running this code with preemption enabled. */
1554	if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1555	{
1556	PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[RTMpCpuId()];
1557	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1558	Assert(pHostCpu->fConfigured);
1559	AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING);
1560	}
1561	#endif
1562
1563	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1564	AssertReturn(!VMMR0ThreadCtxHookIsEnabled(pVCpu), VERR_HM_IPE_4);
1565	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1566	PGMRZDynMapStartAutoSet(pVCpu);
1567	#endif
1568
1569	VBOXSTRICTRC rcStrict = g_HmR0.pfnRunGuestCode(pVCpu);
1570
1571	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1572	PGMRZDynMapReleaseAutoSet(pVCpu);
1573	#endif
1574	return VBOXSTRICTRC_VAL(rcStrict);
1575	}
1576
1577
1578	/**
1579	* Notification from CPUM that it has unloaded the guest FPU/SSE/AVX state from
1580	* the host CPU and that guest access to it must be intercepted.
1581	*
1582	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1583	*/
1584	VMMR0_INT_DECL(void) HMR0NotifyCpumUnloadedGuestFpuState(PVMCPU pVCpu)
1585	{
1586	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
1587	}
1588
1589
1590	/**
1591	* Notification from CPUM that it has modified the host CR0 (because of FPU).
1592	*
1593	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1594	*/
1595	VMMR0_INT_DECL(void) HMR0NotifyCpumModifiedHostCr0(PVMCPU pVCpu)
1596	{
1597	ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_HOST_CONTEXT);
1598	}
1599
1600
1601	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1602
1603	/**
1604	* Save guest FPU/XMM state (64 bits guest mode & 32 bits host only)
1605	*
1606	* @returns VBox status code.
1607	* @param pVM The cross context VM structure.
1608	* @param pVCpu The cross context virtual CPU structure.
1609	* @param pCtx Pointer to the guest CPU context.
1610	*/
1611	VMMR0_INT_DECL(int) HMR0SaveFPUState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1612	{
1613	RT_NOREF(pCtx);
1614	STAM_COUNTER_INC(&pVCpu->hm.s.StatFpu64SwitchBack);
1615	if (pVM->hm.s.vmx.fSupported)
1616	return VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1617	return SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestFPU64, 0, NULL);
1618	}
1619
1620
1621	/**
1622	* Save guest debug state (64 bits guest mode & 32 bits host only)
1623	*
1624	* @returns VBox status code.
1625	* @param pVM The cross context VM structure.
1626	* @param pVCpu The cross context virtual CPU structure.
1627	* @param pCtx Pointer to the guest CPU context.
1628	*/
1629	VMMR0_INT_DECL(int) HMR0SaveDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1630	{
1631	RT_NOREF(pCtx);
1632	STAM_COUNTER_INC(&pVCpu->hm.s.StatDebug64SwitchBack);
1633	if (pVM->hm.s.vmx.fSupported)
1634	return VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1635	return SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCSaveGuestDebug64, 0, NULL);
1636	}
1637
1638
1639	/**
1640	* Test the 32->64 bits switcher.
1641	*
1642	* @returns VBox status code.
1643	* @param pVM The cross context VM structure.
1644	*/
1645	VMMR0_INT_DECL(int) HMR0TestSwitcher3264(PVM pVM)
1646	{
1647	PVMCPU pVCpu = &pVM->aCpus[0];
1648	uint32_t aParam[5] = { 0, 1, 2, 3, 4 };
1649	int rc;
1650
1651	STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatWorldSwitch3264, z);
1652	if (pVM->hm.s.vmx.fSupported)
1653	rc = VMXR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1654	else
1655	rc = SVMR0Execute64BitsHandler(pVCpu, HM64ON32OP_HMRCTestSwitcher64, 5, &aParam[0]);
1656	STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatWorldSwitch3264, z);
1657
1658	return rc;
1659	}
1660
1661	#endif /* HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) */
1662
1663	/**
1664	* Returns suspend status of the host.
1665	*
1666	* @returns Suspend pending or not.
1667	*/
1668	VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1669	{
1670	return ASMAtomicReadBool(&g_HmR0.fSuspended);
1671	}
1672
1673
1674	/**
1675	* Invalidates a guest page from the host TLB.
1676	*
1677	* @param pVCpu The cross context virtual CPU structure.
1678	* @param GCVirt Page to invalidate.
1679	*/
1680	VMMR0_INT_DECL(int) HMR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt)
1681	{
1682	PVM pVM = pVCpu->CTX_SUFF(pVM);
1683	if (pVM->hm.s.vmx.fSupported)
1684	return VMXR0InvalidatePage(pVCpu, GCVirt);
1685	return SVMR0InvalidatePage(pVCpu, GCVirt);
1686	}
1687
1688
1689	/**
1690	* Returns the cpu structure for the current cpu.
1691	* Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1692	*
1693	* @returns The cpu structure pointer.
1694	*/
1695	VMMR0_INT_DECL(PHMGLOBALCPUINFO) hmR0GetCurrentCpu(void)
1696	{
1697	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1698	RTCPUID const idCpu = RTMpCpuId();
1699	Assert(idCpu < RT_ELEMENTS(g_HmR0.aCpuInfo));
1700	return &g_HmR0.aCpuInfo[idCpu];
1701	}
1702
1703
1704	/**
1705	* Interface for importing state on demand (used by IEM).
1706	*
1707	* @returns VBox status code.
1708	* @param pVCpu The cross context CPU structure.
1709	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1710	*/
1711	VMMR0_INT_DECL(int) HMR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat)
1712	{
1713	if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported)
1714	return VMXR0ImportStateOnDemand(pVCpu, fWhat);
1715	return SVMR0ImportStateOnDemand(pVCpu, fWhat);
1716	}
1717
1718
1719	#ifdef VBOX_WITH_RAW_MODE
1720	/**
1721	* Raw-mode switcher hook - disable VT-x if it's active and the current
1722	* switcher turns off paging.
1723	*
1724	* @returns VBox status code.
1725	* @param pVM The cross context VM structure.
1726	* @param enmSwitcher The switcher we're about to use.
1727	* @param pfVTxDisabled Where to store whether VT-x was disabled or not.
1728	*/
1729	VMMR0_INT_DECL(int) HMR0EnterSwitcher(PVM pVM, VMMSWITCHER enmSwitcher, bool *pfVTxDisabled)
1730	{
1731	NOREF(pVM);
1732
1733	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1734
1735	*pfVTxDisabled = false;
1736
1737	/* No such issues with AMD-V */
1738	if (!g_HmR0.vmx.fSupported)
1739	return VINF_SUCCESS;
1740
1741	/* Check if the switching we're up to is safe. */
1742	switch (enmSwitcher)
1743	{
1744	case VMMSWITCHER_32_TO_32:
1745	case VMMSWITCHER_PAE_TO_PAE:
1746	return VINF_SUCCESS; /* safe switchers as they don't turn off paging */
1747
1748	case VMMSWITCHER_32_TO_PAE:
1749	case VMMSWITCHER_PAE_TO_32: /* is this one actually used?? */
1750	case VMMSWITCHER_AMD64_TO_32:
1751	case VMMSWITCHER_AMD64_TO_PAE:
1752	break; /* unsafe switchers */
1753
1754	default:
1755	AssertFailedReturn(VERR_HM_WRONG_SWITCHER);
1756	}
1757
1758	/* When using SUPR0EnableVTx we must let the host suspend and resume VT-x,
1759	regardless of whether we're currently using VT-x or not. */
1760	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1761	{
1762	*pfVTxDisabled = SUPR0SuspendVTxOnCpu();
1763	return VINF_SUCCESS;
1764	}
1765
1766	/** @todo Check if this code is presumptive wrt other VT-x users on the
1767	* system... */
1768
1769	/* Nothing to do if we haven't enabled VT-x. */
1770	if (!g_HmR0.fEnabled)
1771	return VINF_SUCCESS;
1772
1773	/* Local init implies the CPU is currently not in VMX root mode. */
1774	if (!g_HmR0.fGlobalInit)
1775	return VINF_SUCCESS;
1776
1777	/* Ok, disable VT-x. */
1778	PHMGLOBALCPUINFO pHostCpu = hmR0GetCurrentCpu();
1779	AssertReturn( pHostCpu
1780	&& pHostCpu->hMemObj != NIL_RTR0MEMOBJ
1781	&& pHostCpu->pvMemObj
1782	&& pHostCpu->HCPhysMemObj != NIL_RTHCPHYS,
1783	VERR_HM_IPE_2);
1784
1785	*pfVTxDisabled = true;
1786	return VMXR0DisableCpu(pHostCpu, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj);
1787	}
1788
1789
1790	/**
1791	* Raw-mode switcher hook - re-enable VT-x if was active and the current
1792	* switcher turned off paging.
1793	*
1794	* @param pVM The cross context VM structure.
1795	* @param fVTxDisabled Whether VT-x was disabled or not.
1796	*/
1797	VMMR0_INT_DECL(void) HMR0LeaveSwitcher(PVM pVM, bool fVTxDisabled)
1798	{
1799	Assert(!ASMIntAreEnabled());
1800
1801	if (!fVTxDisabled)
1802	return; /* nothing to do */
1803
1804	Assert(g_HmR0.vmx.fSupported);
1805	if (g_HmR0.vmx.fUsingSUPR0EnableVTx)
1806	SUPR0ResumeVTxOnCpu(fVTxDisabled);
1807	else
1808	{
1809	Assert(g_HmR0.fEnabled);
1810	Assert(g_HmR0.fGlobalInit);
1811
1812	PHMGLOBALCPUINFO pHostCpu = hmR0GetCurrentCpu();
1813	AssertReturnVoid( pHostCpu
1814	&& pHostCpu->hMemObj != NIL_RTR0MEMOBJ
1815	&& pHostCpu->pvMemObj
1816	&& pHostCpu->HCPhysMemObj != NIL_RTHCPHYS);
1817
1818	VMXR0EnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, &g_HmR0.vmx.Msrs);
1819	}
1820	}
1821	#endif /* VBOX_WITH_RAW_MODE */
1822
1823
1824	#ifdef VBOX_STRICT
1825	/**
1826	* Dumps a descriptor.
1827	*
1828	* @param pDesc Descriptor to dump.
1829	* @param Sel Selector number.
1830	* @param pszMsg Message to prepend the log entry with.
1831	*/
1832	VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
1833	{
1834	/*
1835	* Make variable description string.
1836	*/
1837	static struct
1838	{
1839	unsigned cch;
1840	const char *psz;
1841	} const s_aTypes[32] =
1842	{
1843	# define STRENTRY(str) { sizeof(str) - 1, str }
1844
1845	/* system */
1846	# if HC_ARCH_BITS == 64
1847	STRENTRY("Reserved0 "), /* 0x00 */
1848	STRENTRY("Reserved1 "), /* 0x01 */
1849	STRENTRY("LDT "), /* 0x02 */
1850	STRENTRY("Reserved3 "), /* 0x03 */
1851	STRENTRY("Reserved4 "), /* 0x04 */
1852	STRENTRY("Reserved5 "), /* 0x05 */
1853	STRENTRY("Reserved6 "), /* 0x06 */
1854	STRENTRY("Reserved7 "), /* 0x07 */
1855	STRENTRY("Reserved8 "), /* 0x08 */
1856	STRENTRY("TSS64Avail "), /* 0x09 */
1857	STRENTRY("ReservedA "), /* 0x0a */
1858	STRENTRY("TSS64Busy "), /* 0x0b */
1859	STRENTRY("Call64 "), /* 0x0c */
1860	STRENTRY("ReservedD "), /* 0x0d */
1861	STRENTRY("Int64 "), /* 0x0e */
1862	STRENTRY("Trap64 "), /* 0x0f */
1863	# else
1864	STRENTRY("Reserved0 "), /* 0x00 */
1865	STRENTRY("TSS16Avail "), /* 0x01 */
1866	STRENTRY("LDT "), /* 0x02 */
1867	STRENTRY("TSS16Busy "), /* 0x03 */
1868	STRENTRY("Call16 "), /* 0x04 */
1869	STRENTRY("Task "), /* 0x05 */
1870	STRENTRY("Int16 "), /* 0x06 */
1871	STRENTRY("Trap16 "), /* 0x07 */
1872	STRENTRY("Reserved8 "), /* 0x08 */
1873	STRENTRY("TSS32Avail "), /* 0x09 */
1874	STRENTRY("ReservedA "), /* 0x0a */
1875	STRENTRY("TSS32Busy "), /* 0x0b */
1876	STRENTRY("Call32 "), /* 0x0c */
1877	STRENTRY("ReservedD "), /* 0x0d */
1878	STRENTRY("Int32 "), /* 0x0e */
1879	STRENTRY("Trap32 "), /* 0x0f */
1880	# endif
1881	/* non system */
1882	STRENTRY("DataRO "), /* 0x10 */
1883	STRENTRY("DataRO Accessed "), /* 0x11 */
1884	STRENTRY("DataRW "), /* 0x12 */
1885	STRENTRY("DataRW Accessed "), /* 0x13 */
1886	STRENTRY("DataDownRO "), /* 0x14 */
1887	STRENTRY("DataDownRO Accessed "), /* 0x15 */
1888	STRENTRY("DataDownRW "), /* 0x16 */
1889	STRENTRY("DataDownRW Accessed "), /* 0x17 */
1890	STRENTRY("CodeEO "), /* 0x18 */
1891	STRENTRY("CodeEO Accessed "), /* 0x19 */
1892	STRENTRY("CodeER "), /* 0x1a */
1893	STRENTRY("CodeER Accessed "), /* 0x1b */
1894	STRENTRY("CodeConfEO "), /* 0x1c */
1895	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1896	STRENTRY("CodeConfER "), /* 0x1e */
1897	STRENTRY("CodeConfER Accessed ") /* 0x1f */
1898	# undef SYSENTRY
1899	};
1900	# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1901	char szMsg[128];
1902	char *psz = &szMsg[0];
1903	unsigned i = pDesc->Gen.u1DescType << 4 \| pDesc->Gen.u4Type;
1904	memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1905	psz += s_aTypes[i].cch;
1906
1907	if (pDesc->Gen.u1Present)
1908	ADD_STR(psz, "Present ");
1909	else
1910	ADD_STR(psz, "Not-Present ");
1911	# if HC_ARCH_BITS == 64
1912	if (pDesc->Gen.u1Long)
1913	ADD_STR(psz, "64-bit ");
1914	else
1915	ADD_STR(psz, "Comp ");
1916	# else
1917	if (pDesc->Gen.u1Granularity)
1918	ADD_STR(psz, "Page ");
1919	if (pDesc->Gen.u1DefBig)
1920	ADD_STR(psz, "32-bit ");
1921	else
1922	ADD_STR(psz, "16-bit ");
1923	# endif
1924	# undef ADD_STR
1925	*psz = '\0';
1926
1927	/*
1928	* Limit and Base and format the output.
1929	*/
1930	#ifdef LOG_ENABLED
1931	uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1932
1933	# if HC_ARCH_BITS == 64
1934	uint64_t u32Base = X86DESC64_BASE(pDesc);
1935	Log(("%s %04x - %RX64 %RX64 - base=%RX64 limit=%08x dpl=%d %s\n", pszMsg,
1936	Sel, pDesc->au64[0], pDesc->au64[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1937	# else
1938	uint32_t u32Base = X86DESC_BASE(pDesc);
1939	Log(("%s %04x - %08x %08x - base=%08x limit=%08x dpl=%d %s\n", pszMsg,
1940	Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1941	# endif
1942	#else
1943	NOREF(Sel); NOREF(pszMsg);
1944	#endif
1945	}
1946
1947
1948	/**
1949	* Formats a full register dump.
1950	*
1951	* @param pVCpu The cross context virtual CPU structure.
1952	*/
1953	VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPU pVCpu)
1954	{
1955	/*
1956	* Format the flags.
1957	*/
1958	static struct
1959	{
1960	const char pszSet; const char pszClear; uint32_t fFlag;
1961	} const s_aFlags[] =
1962	{
1963	{ "vip", NULL, X86_EFL_VIP },
1964	{ "vif", NULL, X86_EFL_VIF },
1965	{ "ac", NULL, X86_EFL_AC },
1966	{ "vm", NULL, X86_EFL_VM },
1967	{ "rf", NULL, X86_EFL_RF },
1968	{ "nt", NULL, X86_EFL_NT },
1969	{ "ov", "nv", X86_EFL_OF },
1970	{ "dn", "up", X86_EFL_DF },
1971	{ "ei", "di", X86_EFL_IF },
1972	{ "tf", NULL, X86_EFL_TF },
1973	{ "nt", "pl", X86_EFL_SF },
1974	{ "nz", "zr", X86_EFL_ZF },
1975	{ "ac", "na", X86_EFL_AF },
1976	{ "po", "pe", X86_EFL_PF },
1977	{ "cy", "nc", X86_EFL_CF },
1978	};
1979	char szEFlags[80];
1980	char *psz = szEFlags;
1981	PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1982	uint32_t uEFlags = pCtx->eflags.u32;
1983	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1984	{
1985	const char *pszAdd = s_aFlags[i].fFlag & uEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1986	if (pszAdd)
1987	{
1988	strcpy(psz, pszAdd);
1989	psz += strlen(pszAdd);
1990	*psz++ = ' ';
1991	}
1992	}
1993	psz[-1] = '\0';
1994
1995	/*
1996	* Format the registers.
1997	*/
1998	if (CPUMIsGuestIn64BitCode(pVCpu))
1999	{
2000	Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
2001	"rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
2002	"r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2003	"r14=%016RX64 r15=%016RX64\n"
2004	"rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
2005	"cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2006	"ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2007	"es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2008	"fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2009	"gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2010	"ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2011	"cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
2012	"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
2013	"dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
2014	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2015	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2016	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2017	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2018	,
2019	pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
2020	pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
2021	pCtx->r14, pCtx->r15,
2022	pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
2023	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2024	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2025	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2026	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2027	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2028	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2029	pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
2030	pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
2031	pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
2032	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
2033	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2034	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2035	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2036	}
2037	else
2038	Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
2039	"eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
2040	"cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
2041	"ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
2042	"es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
2043	"fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
2044	"gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
2045	"ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
2046	"gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
2047	"ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2048	"tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2049	"SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2050	,
2051	pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
2052	pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(uEFlags), 31, szEFlags,
2053	pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
2054	pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
2055	pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
2056	pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
2057	pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
2058	pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
2059	pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, uEFlags,
2060	pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2061	pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2062	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
2063
2064	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
2065	Log(("FPU:\n"
2066	"FCW=%04x FSW=%04x FTW=%02x\n"
2067	"FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
2068	"FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
2069	,
2070	pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
2071	pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
2072	pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
2073	pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
2074
2075	Log(("MSR:\n"
2076	"EFER =%016RX64\n"
2077	"PAT =%016RX64\n"
2078	"STAR =%016RX64\n"
2079	"CSTAR =%016RX64\n"
2080	"LSTAR =%016RX64\n"
2081	"SFMASK =%016RX64\n"
2082	"KERNELGSBASE =%016RX64\n",
2083	pCtx->msrEFER,
2084	pCtx->msrPAT,
2085	pCtx->msrSTAR,
2086	pCtx->msrCSTAR,
2087	pCtx->msrLSTAR,
2088	pCtx->msrSFMASK,
2089	pCtx->msrKERNELGSBASE));
2090
2091	NOREF(pFpuCtx);
2092	}
2093	#endif /* VBOX_STRICT */
2094

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 73299

Download in other formats: