CPUMR0.cpp@ 76553

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1	/* $Id: CPUMR0.cpp 76553 2019-01-01 01:45:53Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/err.h>
27	#include <VBox/log.h>
28	#include <VBox/vmm/hm.h>
29	#include <iprt/assert.h>
30	#include <iprt/asm-amd64-x86.h>
31	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
32	# include <iprt/mem.h>
33	# include <iprt/memobj.h>
34	# include <VBox/apic.h>
35	#endif
36	#include <iprt/x86.h>
37
38
39	/*********************************************************************************************************************************
40	* Structures and Typedefs *
41	*********************************************************************************************************************************/
42	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
43	/**
44	* Local APIC mappings.
45	*/
46	typedef struct CPUMHOSTLAPIC
47	{
48	/** Indicates that the entry is in use and have valid data. */
49	bool fEnabled;
50	/** Whether it's operating in X2APIC mode (EXTD). */
51	bool fX2Apic;
52	/** The APIC version number. */
53	uint32_t uVersion;
54	/** The physical address of the APIC registers. */
55	RTHCPHYS PhysBase;
56	/** The memory object entering the physical address. */
57	RTR0MEMOBJ hMemObj;
58	/** The mapping object for hMemObj. */
59	RTR0MEMOBJ hMapObj;
60	/** The mapping address APIC registers.
61	* @remarks Different CPUs may use the same physical address to map their
62	* APICs, so this pointer is only valid when on the CPU owning the
63	* APIC. */
64	void *pv;
65	} CPUMHOSTLAPIC;
66	#endif
67
68
69	/*********************************************************************************************************************************
70	* Global Variables *
71	*********************************************************************************************************************************/
72	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
73	static CPUMHOSTLAPIC g_aLApics[RTCPUSET_MAX_CPUS];
74	#endif
75
76	/**
77	* CPUID bits to unify among all cores.
78	*/
79	static struct
80	{
81	uint32_t uLeaf; /*< Leaf to check. /
82	uint32_t uEcx; /*< which bits in ecx to unify between CPUs. /
83	uint32_t uEdx; /*< which bits in edx to unify between CPUs. /
84	}
85	const g_aCpuidUnifyBits[] =
86	{
87	{
88	0x00000001,
89	X86_CPUID_FEATURE_ECX_CX16 \| X86_CPUID_FEATURE_ECX_MONITOR,
90	X86_CPUID_FEATURE_EDX_CX8
91	}
92	};
93
94
95
96	/*********************************************************************************************************************************
97	* Internal Functions *
98	*********************************************************************************************************************************/
99	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
100	static int cpumR0MapLocalApics(void);
101	static void cpumR0UnmapLocalApics(void);
102	#endif
103	static int cpumR0SaveHostDebugState(PVMCPU pVCpu);
104
105
106	/**
107	* Does the Ring-0 CPU initialization once during module load.
108	* XXX Host-CPU hot-plugging?
109	*/
110	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void)
111	{
112	int rc = VINF_SUCCESS;
113	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
114	rc = cpumR0MapLocalApics();
115	#endif
116	return rc;
117	}
118
119
120	/**
121	* Terminate the module.
122	*/
123	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void)
124	{
125	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
126	cpumR0UnmapLocalApics();
127	#endif
128	return VINF_SUCCESS;
129	}
130
131
132	/**
133	* Check the CPUID features of this particular CPU and disable relevant features
134	* for the guest which do not exist on this CPU. We have seen systems where the
135	* X86_CPUID_FEATURE_ECX_MONITOR feature flag is only set on some host CPUs, see
136	* @bugref{5436}.
137	*
138	* @note This function might be called simultaneously on more than one CPU!
139	*
140	* @param idCpu The identifier for the CPU the function is called on.
141	* @param pvUser1 Pointer to the VM structure.
142	* @param pvUser2 Ignored.
143	*/
144	static DECLCALLBACK(void) cpumR0CheckCpuid(RTCPUID idCpu, void pvUser1, void pvUser2)
145	{
146	PVM pVM = (PVM)pvUser1;
147
148	NOREF(idCpu); NOREF(pvUser2);
149	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
150	{
151	/* Note! Cannot use cpumCpuIdGetLeaf from here because we're not
152	necessarily in the VM process context. So, we using the
153	legacy arrays as temporary storage. */
154
155	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
156	PCPUMCPUID pLegacyLeaf;
157	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
158	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
159	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
160	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
161	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
162	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
163	else
164	continue;
165
166	uint32_t eax, ebx, ecx, edx;
167	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &eax, &ebx, &ecx, &edx);
168
169	ASMAtomicAndU32(&pLegacyLeaf->uEcx, ecx \| ~g_aCpuidUnifyBits[i].uEcx);
170	ASMAtomicAndU32(&pLegacyLeaf->uEdx, edx \| ~g_aCpuidUnifyBits[i].uEdx);
171	}
172	}
173
174
175	/**
176	* Does Ring-0 CPUM initialization.
177	*
178	* This is mainly to check that the Host CPU mode is compatible
179	* with VBox.
180	*
181	* @returns VBox status code.
182	* @param pVM The cross context VM structure.
183	*/
184	VMMR0_INT_DECL(int) CPUMR0InitVM(PVM pVM)
185	{
186	LogFlow(("CPUMR0Init: %p\n", pVM));
187
188	/*
189	* Check CR0 & CR4 flags.
190	*/
191	uint32_t u32CR0 = ASMGetCR0();
192	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
193	{
194	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
195	return VERR_UNSUPPORTED_CPU_MODE;
196	}
197
198	/*
199	* Check for sysenter and syscall usage.
200	*/
201	if (ASMHasCpuId())
202	{
203	/*
204	* SYSENTER/SYSEXIT
205	*
206	* Intel docs claim you should test both the flag and family, model &
207	* stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
208	* but don't support it. AMD CPUs may support this feature in legacy
209	* mode, they've banned it from long mode. Since we switch to 32-bit
210	* mode when entering raw-mode context the feature would become
211	* accessible again on AMD CPUs, so we have to check regardless of
212	* host bitness.
213	*/
214	uint32_t u32CpuVersion;
215	uint32_t u32Dummy;
216	uint32_t fFeatures;
217	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
218	uint32_t const u32Family = u32CpuVersion >> 8;
219	uint32_t const u32Model = (u32CpuVersion >> 4) & 0xF;
220	uint32_t const u32Stepping = u32CpuVersion & 0xF;
221	if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
222	&& ( u32Family != 6 /* (> pentium pro) */
223	\|\| u32Model >= 3
224	\|\| u32Stepping >= 3
225	\|\| !ASMIsIntelCpu())
226	)
227	{
228	/*
229	* Read the MSR and see if it's in use or not.
230	*/
231	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
232	if (u32)
233	{
234	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSENTER;
235	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
236	}
237	}
238
239	/*
240	* SYSCALL/SYSRET
241	*
242	* This feature is indicated by the SEP bit returned in EDX by CPUID
243	* function 0x80000001. Intel CPUs only supports this feature in
244	* long mode. Since we're not running 64-bit guests in raw-mode there
245	* are no issues with 32-bit intel hosts.
246	*/
247	uint32_t cExt = 0;
248	ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
249	if (ASMIsValidExtRange(cExt))
250	{
251	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
252	if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
253	{
254	#ifdef RT_ARCH_X86
255	if (!ASMIsIntelCpu())
256	#endif
257	{
258	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
259	if (fEfer & MSR_K6_EFER_SCE)
260	{
261	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSCALL;
262	Log(("CPUMR0Init: host uses syscall\n"));
263	}
264	}
265	}
266	}
267
268	/*
269	* Unify/cross check some CPUID feature bits on all available CPU cores
270	* and threads. We've seen CPUs where the monitor support differed.
271	*
272	* Because the hyper heap isn't always mapped into ring-0, we cannot
273	* access it from a RTMpOnAll callback. We use the legacy CPUID arrays
274	* as temp ring-0 accessible memory instead, ASSUMING that they're all
275	* up to date when we get here.
276	*/
277	RTMpOnAll(cpumR0CheckCpuid, pVM, NULL);
278
279	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
280	{
281	bool fIgnored;
282	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
283	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, 0, &fIgnored);
284	if (pLeaf)
285	{
286	PCPUMCPUID pLegacyLeaf;
287	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
288	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
289	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
290	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
291	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
292	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
293	else
294	continue;
295
296	pLeaf->uEcx = pLegacyLeaf->uEcx;
297	pLeaf->uEdx = pLegacyLeaf->uEdx;
298	}
299	}
300
301	}
302
303
304	/*
305	* Check if debug registers are armed.
306	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
307	*/
308	uint32_t u32DR7 = ASMGetDR7();
309	if (u32DR7 & X86_DR7_ENABLED_MASK)
310	{
311	for (VMCPUID i = 0; i < pVM->cCpus; i++)
312	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
313	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
314	}
315
316	return VINF_SUCCESS;
317	}
318
319
320	/**
321	* Trap handler for device-not-available fault (\#NM).
322	* Device not available, FP or (F)WAIT instruction.
323	*
324	* @returns VBox status code.
325	* @retval VINF_SUCCESS if the guest FPU state is loaded.
326	* @retval VINF_EM_RAW_GUEST_TRAP if it is a guest trap.
327	* @retval VINF_CPUM_HOST_CR0_MODIFIED if we modified the host CR0.
328	*
329	* @param pVM The cross context VM structure.
330	* @param pVCpu The cross context virtual CPU structure.
331	*/
332	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVM pVM, PVMCPU pVCpu)
333	{
334	Assert(pVM->cpum.s.HostFeatures.fFxSaveRstor);
335	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
336
337	/* If the FPU state has already been loaded, then it's a guest trap. */
338	if (CPUMIsGuestFPUStateActive(pVCpu))
339	{
340	Assert( ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS))
341	\|\| ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM)));
342	return VINF_EM_RAW_GUEST_TRAP;
343	}
344
345	/*
346	* There are two basic actions:
347	* 1. Save host fpu and restore guest fpu.
348	* 2. Generate guest trap.
349	*
350	* When entering the hypervisor we'll always enable MP (for proper wait
351	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
352	* is taken from the guest OS in order to get proper SSE handling.
353	*
354	*
355	* Actions taken depending on the guest CR0 flags:
356	*
357	* 3 2 1
358	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
359	* ------------------------------------------------------------------------
360	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
361	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
362	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
363	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
364	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
365	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
366	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
367	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
368	*/
369
370	switch (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
371	{
372	case X86_CR0_MP \| X86_CR0_TS:
373	case X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM:
374	return VINF_EM_RAW_GUEST_TRAP;
375	default:
376	break;
377	}
378
379	return CPUMR0LoadGuestFPU(pVM, pVCpu);
380	}
381
382
383	/**
384	* Saves the host-FPU/XMM state (if necessary) and (always) loads the guest-FPU
385	* state into the CPU.
386	*
387	* @returns VINF_SUCCESS on success, host CR0 unmodified.
388	* @returns VINF_CPUM_HOST_CR0_MODIFIED on success when the host CR0 was
389	* modified and VT-x needs to update the value in the VMCS.
390	*
391	* @param pVM The cross context VM structure.
392	* @param pVCpu The cross context virtual CPU structure.
393	*/
394	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu)
395	{
396	int rc = VINF_SUCCESS;
397	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
398	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST));
399	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
400
401	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
402	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
403	{
404	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
405
406	/* Save the host state if necessary. */
407	if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST))
408	rc = cpumRZSaveHostFPUState(&pVCpu->cpum.s);
409
410	/* Restore the state on entry as we need to be in 64-bit mode to access the full state. */
411	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_FPU_STATE;
412
413	Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM))
414	== (CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM));
415	}
416	else
417	#endif
418	{
419	if (!pVM->cpum.s.HostFeatures.fLeakyFxSR)
420	{
421	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
422	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
423	}
424	else
425	{
426	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE) \|\| (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST));
427	/** @todo r=ramshankar: Can't we used a cached value here
428	* instead of reading the MSR? host EFER doesn't usually
429	* change. */
430	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
431	if (!(uHostEfer & MSR_K6_EFER_FFXSR))
432	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
433	else
434	{
435	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
436	pVCpu->cpum.s.fUseFlags \|= CPUM_USED_MANUAL_XMM_RESTORE;
437	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
438	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
439	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
440	ASMSetFlags(uSavedFlags);
441	}
442	}
443	Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM))
444	== (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM));
445	}
446	return rc;
447	}
448
449
450	/**
451	* Saves the guest FPU/XMM state if needed, restores the host FPU/XMM state as
452	* needed.
453	*
454	* @returns true if we saved the guest state.
455	* @param pVCpu The cross context virtual CPU structure.
456	*/
457	VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu)
458	{
459	bool fSavedGuest;
460	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.HostFeatures.fFxSaveRstor);
461	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
462	if (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST))
463	{
464	fSavedGuest = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
465	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
466	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
467	{
468	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST)
469	{
470	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
471	HMR0SaveFPUState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
472	}
473	else
474	pVCpu->cpum.s.fUseFlags &= ~CPUM_SYNC_FPU_STATE;
475	cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
476	}
477	else
478	#endif
479	{
480	if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE))
481	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
482	else
483	{
484	/* Temporarily clear MSR_K6_EFER_FFXSR or else we'll be unable to
485	save/restore the XMM state with fxsave/fxrstor. */
486	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
487	if (uHostEfer & MSR_K6_EFER_FFXSR)
488	{
489	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
490	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
491	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
492	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
493	ASMSetFlags(uSavedFlags);
494	}
495	else
496	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
497	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_MANUAL_XMM_RESTORE;
498	}
499	}
500	}
501	else
502	fSavedGuest = false;
503	Assert(!( pVCpu->cpum.s.fUseFlags
504	& (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_SYNC_FPU_STATE \| CPUM_USED_MANUAL_XMM_RESTORE)));
505	return fSavedGuest;
506	}
507
508
509	/**
510	* Saves the host debug state, setting CPUM_USED_HOST_DEBUG_STATE and loading
511	* DR7 with safe values.
512	*
513	* @returns VBox status code.
514	* @param pVCpu The cross context virtual CPU structure.
515	*/
516	static int cpumR0SaveHostDebugState(PVMCPU pVCpu)
517	{
518	/*
519	* Save the host state.
520	*/
521	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
522	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
523	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
524	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
525	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
526	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
527	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
528
529	/* Preemption paranoia. */
530	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HOST);
531
532	/*
533	* Make sure DR7 is harmless or else we could trigger breakpoints when
534	* load guest or hypervisor DRx values later.
535	*/
536	if (pVCpu->cpum.s.Host.dr7 != X86_DR7_INIT_VAL)
537	ASMSetDR7(X86_DR7_INIT_VAL);
538
539	return VINF_SUCCESS;
540	}
541
542
543	/**
544	* Saves the guest DRx state residing in host registers and restore the host
545	* register values.
546	*
547	* The guest DRx state is only saved if CPUMR0LoadGuestDebugState was called,
548	* since it's assumed that we're shadowing the guest DRx register values
549	* accurately when using the combined hypervisor debug register values
550	* (CPUMR0LoadHyperDebugState).
551	*
552	* @returns true if either guest or hypervisor debug registers were loaded.
553	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
554	* @param fDr6 Whether to include DR6 or not.
555	* @thread EMT(pVCpu)
556	*/
557	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu, bool fDr6)
558	{
559	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
560	bool const fDrXLoaded = RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
561
562	/*
563	* Do we need to save the guest DRx registered loaded into host registers?
564	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
565	*/
566	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
567	{
568	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
569	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
570	{
571	uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
572	HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
573	if (!fDr6)
574	pVCpu->cpum.s.Guest.dr[6] = uDr6;
575	}
576	else
577	#endif
578	{
579	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
580	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
581	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
582	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
583	if (fDr6)
584	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
585	}
586	}
587	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~( CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER
588	\| CPUM_SYNC_DEBUG_REGS_GUEST \| CPUM_SYNC_DEBUG_REGS_HYPER));
589
590	/*
591	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
592	*/
593	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST)
594	{
595	/* A bit of paranoia first... */
596	uint64_t uCurDR7 = ASMGetDR7();
597	if (uCurDR7 != X86_DR7_INIT_VAL)
598	ASMSetDR7(X86_DR7_INIT_VAL);
599
600	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
601	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
602	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
603	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
604	/** @todo consider only updating if they differ, esp. DR6. Need to figure how
605	* expensive DRx reads are over DRx writes. */
606	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
607	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
608
609	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HOST);
610	}
611
612	return fDrXLoaded;
613	}
614
615
616	/**
617	* Saves the guest DRx state if it resides host registers.
618	*
619	* This does NOT clear any use flags, so the host registers remains loaded with
620	* the guest DRx state upon return. The purpose is only to make sure the values
621	* in the CPU context structure is up to date.
622	*
623	* @returns true if the host registers contains guest values, false if not.
624	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
625	* @param fDr6 Whether to include DR6 or not.
626	* @thread EMT(pVCpu)
627	*/
628	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPU pVCpu, bool fDr6)
629	{
630	/*
631	* Do we need to save the guest DRx registered loaded into host registers?
632	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
633	*/
634	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
635	{
636	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
637	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
638	{
639	uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
640	HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
641	if (!fDr6)
642	pVCpu->cpum.s.Guest.dr[6] = uDr6;
643	}
644	else
645	#endif
646	{
647	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
648	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
649	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
650	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
651	if (fDr6)
652	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
653	}
654	return true;
655	}
656	return false;
657	}
658
659
660	/**
661	* Lazily sync in the debug state.
662	*
663	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
664	* @param fDr6 Whether to include DR6 or not.
665	* @thread EMT(pVCpu)
666	*/
667	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPU pVCpu, bool fDr6)
668	{
669	/*
670	* Save the host state and disarm all host BPs.
671	*/
672	cpumR0SaveHostDebugState(pVCpu);
673	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
674
675	/*
676	* Activate the guest state DR0-3.
677	* DR7 and DR6 (if fDr6 is true) are left to the caller.
678	*/
679	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
680	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
681	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_SYNC_DEBUG_REGS_GUEST); /* Postpone it to the world switch. */
682	else
683	#endif
684	{
685	ASMSetDR0(pVCpu->cpum.s.Guest.dr[0]);
686	ASMSetDR1(pVCpu->cpum.s.Guest.dr[1]);
687	ASMSetDR2(pVCpu->cpum.s.Guest.dr[2]);
688	ASMSetDR3(pVCpu->cpum.s.Guest.dr[3]);
689	if (fDr6)
690	ASMSetDR6(pVCpu->cpum.s.Guest.dr[6]);
691
692	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
693	}
694	}
695
696
697	/**
698	* Lazily sync in the hypervisor debug state
699	*
700	* @returns VBox status code.
701	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
702	* @param fDr6 Whether to include DR6 or not.
703	* @thread EMT(pVCpu)
704	*/
705	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPU pVCpu, bool fDr6)
706	{
707	/*
708	* Save the host state and disarm all host BPs.
709	*/
710	cpumR0SaveHostDebugState(pVCpu);
711	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
712
713	/*
714	* Make sure the hypervisor values are up to date.
715	*/
716	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */, true);
717
718	/*
719	* Activate the guest state DR0-3.
720	* DR7 and DR6 (if fDr6 is true) are left to the caller.
721	*/
722	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
723	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
724	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_SYNC_DEBUG_REGS_HYPER); /* Postpone it. */
725	else
726	#endif
727	{
728	ASMSetDR0(pVCpu->cpum.s.Hyper.dr[0]);
729	ASMSetDR1(pVCpu->cpum.s.Hyper.dr[1]);
730	ASMSetDR2(pVCpu->cpum.s.Hyper.dr[2]);
731	ASMSetDR3(pVCpu->cpum.s.Hyper.dr[3]);
732	if (fDr6)
733	ASMSetDR6(X86_DR6_INIT_VAL);
734
735	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
736	}
737	}
738
739	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
740
741	/**
742	* Per-CPU callback that probes the CPU for APIC support.
743	*
744	* @param idCpu The identifier for the CPU the function is called on.
745	* @param pvUser1 Ignored.
746	* @param pvUser2 Ignored.
747	*/
748	static DECLCALLBACK(void) cpumR0MapLocalApicCpuProber(RTCPUID idCpu, void pvUser1, void pvUser2)
749	{
750	NOREF(pvUser1); NOREF(pvUser2);
751	int iCpu = RTMpCpuIdToSetIndex(idCpu);
752	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
753
754	/*
755	* Check for APIC support.
756	*/
757	uint32_t uMaxLeaf, u32EBX, u32ECX, u32EDX;
758	ASMCpuId(0, &uMaxLeaf, &u32EBX, &u32ECX, &u32EDX);
759	if ( ( ASMIsIntelCpuEx(u32EBX, u32ECX, u32EDX)
760	\|\| ASMIsAmdCpuEx(u32EBX, u32ECX, u32EDX)
761	\|\| ASMIsViaCentaurCpuEx(u32EBX, u32ECX, u32EDX))
762	&& ASMIsValidStdRange(uMaxLeaf))
763	{
764	uint32_t uDummy;
765	ASMCpuId(1, &uDummy, &u32EBX, &u32ECX, &u32EDX);
766	if ( (u32EDX & X86_CPUID_FEATURE_EDX_APIC)
767	&& (u32EDX & X86_CPUID_FEATURE_EDX_MSR))
768	{
769	/*
770	* Safe to access the MSR. Read it and calc the BASE (a little complicated).
771	*/
772	uint64_t u64ApicBase = ASMRdMsr(MSR_IA32_APICBASE);
773	uint64_t u64Mask = MSR_IA32_APICBASE_BASE_MIN;
774
775	/* see Intel Manual: Local APIC Status and Location: MAXPHYADDR default is bit 36 */
776	uint32_t uMaxExtLeaf;
777	ASMCpuId(0x80000000, &uMaxExtLeaf, &u32EBX, &u32ECX, &u32EDX);
778	if ( uMaxExtLeaf >= UINT32_C(0x80000008)
779	&& ASMIsValidExtRange(uMaxExtLeaf))
780	{
781	uint32_t u32PhysBits;
782	ASMCpuId(0x80000008, &u32PhysBits, &u32EBX, &u32ECX, &u32EDX);
783	u32PhysBits &= 0xff;
784	u64Mask = ((UINT64_C(1) << u32PhysBits) - 1) & UINT64_C(0xfffffffffffff000);
785	}
786
787	AssertCompile(sizeof(g_aLApics[iCpu].PhysBase) == sizeof(u64ApicBase));
788	g_aLApics[iCpu].PhysBase = u64ApicBase & u64Mask;
789	g_aLApics[iCpu].fEnabled = RT_BOOL(u64ApicBase & MSR_IA32_APICBASE_EN);
790	g_aLApics[iCpu].fX2Apic = (u64ApicBase & (MSR_IA32_APICBASE_EXTD \| MSR_IA32_APICBASE_EN))
791	== (MSR_IA32_APICBASE_EXTD \| MSR_IA32_APICBASE_EN);
792	}
793	}
794	}
795
796
797
798	/**
799	* Per-CPU callback that verifies our APIC expectations.
800	*
801	* @param idCpu The identifier for the CPU the function is called on.
802	* @param pvUser1 Ignored.
803	* @param pvUser2 Ignored.
804	*/
805	static DECLCALLBACK(void) cpumR0MapLocalApicCpuChecker(RTCPUID idCpu, void pvUser1, void pvUser2)
806	{
807	NOREF(pvUser1); NOREF(pvUser2);
808
809	int iCpu = RTMpCpuIdToSetIndex(idCpu);
810	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
811	if (!g_aLApics[iCpu].fEnabled)
812	return;
813
814	/*
815	* 0x0X 82489 external APIC
816	* 0x1X Local APIC
817	* 0x2X..0xFF reserved
818	*/
819	uint32_t uApicVersion;
820	if (g_aLApics[iCpu].fX2Apic)
821	uApicVersion = ApicX2RegRead32(APIC_REG_VERSION);
822	else
823	uApicVersion = ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_VERSION);
824	if ((APIC_REG_VERSION_GET_VER(uApicVersion) & 0xF0) == 0x10)
825	{
826	g_aLApics[iCpu].uVersion = uApicVersion;
827
828	#if 0 /* enable if you need it. */
829	if (g_aLApics[iCpu].fX2Apic)
830	SUPR0Printf("CPUM: X2APIC %02u - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
831	iCpu, uApicVersion,
832	ApicX2RegRead32(APIC_REG_LVT_LINT0), ApicX2RegRead32(APIC_REG_LVT_LINT1),
833	ApicX2RegRead32(APIC_REG_LVT_PC), ApicX2RegRead32(APIC_REG_LVT_THMR),
834	ApicX2RegRead32(APIC_REG_LVT_CMCI));
835	else
836	{
837	SUPR0Printf("CPUM: APIC %02u at %RGp (mapped at %p) - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
838	iCpu, g_aLApics[iCpu].PhysBase, g_aLApics[iCpu].pv, uApicVersion,
839	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT0), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT1),
840	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_PC), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_THMR),
841	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_CMCI));
842	if (uApicVersion & 0x80000000)
843	{
844	uint32_t uExtFeatures = ApicRegRead(g_aLApics[iCpu].pv, 0x400);
845	uint32_t cEiLvt = (uExtFeatures >> 16) & 0xff;
846	SUPR0Printf("CPUM: APIC %02u: ExtSpace available. extfeat=%08x eilvt[0..3]=%08x %08x %08x %08x\n",
847	iCpu,
848	ApicRegRead(g_aLApics[iCpu].pv, 0x400),
849	cEiLvt >= 1 ? ApicRegRead(g_aLApics[iCpu].pv, 0x500) : 0,
850	cEiLvt >= 2 ? ApicRegRead(g_aLApics[iCpu].pv, 0x510) : 0,
851	cEiLvt >= 3 ? ApicRegRead(g_aLApics[iCpu].pv, 0x520) : 0,
852	cEiLvt >= 4 ? ApicRegRead(g_aLApics[iCpu].pv, 0x530) : 0);
853	}
854	}
855	#endif
856	}
857	else
858	{
859	g_aLApics[iCpu].fEnabled = false;
860	g_aLApics[iCpu].fX2Apic = false;
861	SUPR0Printf("VBox/CPUM: Unsupported APIC version %#x (iCpu=%d)\n", uApicVersion, iCpu);
862	}
863	}
864
865
866	/**
867	* Map the MMIO page of each local APIC in the system.
868	*/
869	static int cpumR0MapLocalApics(void)
870	{
871	/*
872	* Check that we'll always stay within the array bounds.
873	*/
874	if (RTMpGetArraySize() > RT_ELEMENTS(g_aLApics))
875	{
876	LogRel(("CPUM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_aLApics)));
877	return VERR_TOO_MANY_CPUS;
878	}
879
880	/*
881	* Create mappings for all online CPUs we think have legacy APICs.
882	*/
883	int rc = RTMpOnAll(cpumR0MapLocalApicCpuProber, NULL, NULL);
884
885	for (unsigned iCpu = 0; RT_SUCCESS(rc) && iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
886	{
887	if (g_aLApics[iCpu].fEnabled && !g_aLApics[iCpu].fX2Apic)
888	{
889	rc = RTR0MemObjEnterPhys(&g_aLApics[iCpu].hMemObj, g_aLApics[iCpu].PhysBase,
890	PAGE_SIZE, RTMEM_CACHE_POLICY_MMIO);
891	if (RT_SUCCESS(rc))
892	{
893	rc = RTR0MemObjMapKernel(&g_aLApics[iCpu].hMapObj, g_aLApics[iCpu].hMemObj, (void *)-1,
894	PAGE_SIZE, RTMEM_PROT_READ \| RTMEM_PROT_WRITE);
895	if (RT_SUCCESS(rc))
896	{
897	g_aLApics[iCpu].pv = RTR0MemObjAddress(g_aLApics[iCpu].hMapObj);
898	continue;
899	}
900	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
901	}
902	g_aLApics[iCpu].fEnabled = false;
903	}
904	g_aLApics[iCpu].pv = NULL;
905	}
906
907	/*
908	* Check the APICs.
909	*/
910	if (RT_SUCCESS(rc))
911	rc = RTMpOnAll(cpumR0MapLocalApicCpuChecker, NULL, NULL);
912
913	if (RT_FAILURE(rc))
914	{
915	cpumR0UnmapLocalApics();
916	return rc;
917	}
918
919	#ifdef LOG_ENABLED
920	/*
921	* Log the result (pretty useless, requires enabling CPUM in VBoxDrv
922	* and !VBOX_WITH_R0_LOGGING).
923	*/
924	if (LogIsEnabled())
925	{
926	uint32_t cEnabled = 0;
927	uint32_t cX2Apics = 0;
928	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
929	if (g_aLApics[iCpu].fEnabled)
930	{
931	cEnabled++;
932	cX2Apics += g_aLApics[iCpu].fX2Apic;
933	}
934	Log(("CPUM: %u APICs, %u X2APICs\n", cEnabled, cX2Apics));
935	}
936	#endif
937
938	return VINF_SUCCESS;
939	}
940
941
942	/**
943	* Unmap the Local APIC of all host CPUs.
944	*/
945	static void cpumR0UnmapLocalApics(void)
946	{
947	for (unsigned iCpu = RT_ELEMENTS(g_aLApics); iCpu-- > 0;)
948	{
949	if (g_aLApics[iCpu].pv)
950	{
951	RTR0MemObjFree(g_aLApics[iCpu].hMapObj, true /* fFreeMappings */);
952	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
953	g_aLApics[iCpu].hMapObj = NIL_RTR0MEMOBJ;
954	g_aLApics[iCpu].hMemObj = NIL_RTR0MEMOBJ;
955	g_aLApics[iCpu].fEnabled = false;
956	g_aLApics[iCpu].fX2Apic = false;
957	g_aLApics[iCpu].pv = NULL;
958	}
959	}
960	}
961
962
963	/**
964	* Updates CPUMCPU::pvApicBase and CPUMCPU::fX2Apic prior to world switch.
965	*
966	* Writes the Local APIC mapping address of the current host CPU to CPUMCPU so
967	* the world switchers can access the APIC registers for the purpose of
968	* disabling and re-enabling the NMIs. Must be called with disabled preemption
969	* or disabled interrupts!
970	*
971	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
972	* @param iHostCpuSet The CPU set index of the current host CPU.
973	*/
974	VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPU pVCpu, uint32_t iHostCpuSet)
975	{
976	Assert(iHostCpuSet <= RT_ELEMENTS(g_aLApics));
977	pVCpu->cpum.s.pvApicBase = g_aLApics[iHostCpuSet].pv;
978	pVCpu->cpum.s.fX2Apic = g_aLApics[iHostCpuSet].fX2Apic;
979	// Log6(("CPUMR0SetLApic: pvApicBase=%p fX2Apic=%d\n", g_aLApics[idxCpu].pv, g_aLApics[idxCpu].fX2Apic));
980	}
981
982	#endif /* VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI */
983

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source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 76553

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