CPUMR0.cpp@ 61068

Last change on this file since 61068 was 61068, checked in by vboxsync, 8 years ago
CPUM,IEM: FPU/SSE/AVX state and host resources APIs, first installment. This should fix the win 8.1 issue.
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1	/* $Id: CPUMR0.cpp 61068 2016-05-20 01:24:53Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/err.h>
27	#include <VBox/log.h>
28	#include <VBox/vmm/hm.h>
29	#include <iprt/assert.h>
30	#include <iprt/asm-amd64-x86.h>
31	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
32	# include <iprt/mem.h>
33	# include <iprt/memobj.h>
34	# include <VBox/apic.h>
35	#endif
36	#include <iprt/x86.h>
37
38
39	/*********************************************************************************************************************************
40	* Structures and Typedefs *
41	*********************************************************************************************************************************/
42	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
43	/**
44	* Local APIC mappings.
45	*/
46	typedef struct CPUMHOSTLAPIC
47	{
48	/** Indicates that the entry is in use and have valid data. */
49	bool fEnabled;
50	/** Whether it's operating in X2APIC mode (EXTD). */
51	bool fX2Apic;
52	/** The APIC version number. */
53	uint32_t uVersion;
54	/** The physical address of the APIC registers. */
55	RTHCPHYS PhysBase;
56	/** The memory object entering the physical address. */
57	RTR0MEMOBJ hMemObj;
58	/** The mapping object for hMemObj. */
59	RTR0MEMOBJ hMapObj;
60	/** The mapping address APIC registers.
61	* @remarks Different CPUs may use the same physical address to map their
62	* APICs, so this pointer is only valid when on the CPU owning the
63	* APIC. */
64	void *pv;
65	} CPUMHOSTLAPIC;
66	#endif
67
68
69	/*********************************************************************************************************************************
70	* Global Variables *
71	*********************************************************************************************************************************/
72	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
73	static CPUMHOSTLAPIC g_aLApics[RTCPUSET_MAX_CPUS];
74	#endif
75
76	/**
77	* CPUID bits to unify among all cores.
78	*/
79	static struct
80	{
81	uint32_t uLeaf; /*< Leaf to check. /
82	uint32_t uEcx; /*< which bits in ecx to unify between CPUs. /
83	uint32_t uEdx; /*< which bits in edx to unify between CPUs. /
84	}
85	const g_aCpuidUnifyBits[] =
86	{
87	{
88	0x00000001,
89	X86_CPUID_FEATURE_ECX_CX16 \| X86_CPUID_FEATURE_ECX_MONITOR,
90	X86_CPUID_FEATURE_EDX_CX8
91	}
92	};
93
94
95
96	/*********************************************************************************************************************************
97	* Internal Functions *
98	*********************************************************************************************************************************/
99	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
100	static int cpumR0MapLocalApics(void);
101	static void cpumR0UnmapLocalApics(void);
102	#endif
103	static int cpumR0SaveHostDebugState(PVMCPU pVCpu);
104
105
106	/**
107	* Does the Ring-0 CPU initialization once during module load.
108	* XXX Host-CPU hot-plugging?
109	*/
110	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void)
111	{
112	int rc = VINF_SUCCESS;
113	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
114	rc = cpumR0MapLocalApics();
115	#endif
116	return rc;
117	}
118
119
120	/**
121	* Terminate the module.
122	*/
123	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void)
124	{
125	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
126	cpumR0UnmapLocalApics();
127	#endif
128	return VINF_SUCCESS;
129	}
130
131
132	/**
133	*
134	*
135	* Check the CPUID features of this particular CPU and disable relevant features
136	* for the guest which do not exist on this CPU. We have seen systems where the
137	* X86_CPUID_FEATURE_ECX_MONITOR feature flag is only set on some host CPUs, see
138	* @bugref{5436}.
139	*
140	* @note This function might be called simultaneously on more than one CPU!
141	*
142	* @param idCpu The identifier for the CPU the function is called on.
143	* @param pvUser1 Pointer to the VM structure.
144	* @param pvUser2 Ignored.
145	*/
146	static DECLCALLBACK(void) cpumR0CheckCpuid(RTCPUID idCpu, void pvUser1, void pvUser2)
147	{
148	PVM pVM = (PVM)pvUser1;
149
150	NOREF(idCpu); NOREF(pvUser2);
151	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
152	{
153	/* Note! Cannot use cpumCpuIdGetLeaf from here because we're not
154	necessarily in the VM process context. So, we using the
155	legacy arrays as temporary storage. */
156
157	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
158	PCPUMCPUID pLegacyLeaf;
159	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
160	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
161	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
162	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
163	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
164	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
165	else
166	continue;
167
168	uint32_t eax, ebx, ecx, edx;
169	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &eax, &ebx, &ecx, &edx);
170
171	ASMAtomicAndU32(&pLegacyLeaf->uEcx, ecx \| ~g_aCpuidUnifyBits[i].uEcx);
172	ASMAtomicAndU32(&pLegacyLeaf->uEdx, edx \| ~g_aCpuidUnifyBits[i].uEdx);
173	}
174	}
175
176
177	/**
178	* Does Ring-0 CPUM initialization.
179	*
180	* This is mainly to check that the Host CPU mode is compatible
181	* with VBox.
182	*
183	* @returns VBox status code.
184	* @param pVM The cross context VM structure.
185	*/
186	VMMR0_INT_DECL(int) CPUMR0InitVM(PVM pVM)
187	{
188	LogFlow(("CPUMR0Init: %p\n", pVM));
189
190	/*
191	* Check CR0 & CR4 flags.
192	*/
193	uint32_t u32CR0 = ASMGetCR0();
194	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
195	{
196	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
197	return VERR_UNSUPPORTED_CPU_MODE;
198	}
199
200	/*
201	* Check for sysenter and syscall usage.
202	*/
203	if (ASMHasCpuId())
204	{
205	/*
206	* SYSENTER/SYSEXIT
207	*
208	* Intel docs claim you should test both the flag and family, model &
209	* stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
210	* but don't support it. AMD CPUs may support this feature in legacy
211	* mode, they've banned it from long mode. Since we switch to 32-bit
212	* mode when entering raw-mode context the feature would become
213	* accessible again on AMD CPUs, so we have to check regardless of
214	* host bitness.
215	*/
216	uint32_t u32CpuVersion;
217	uint32_t u32Dummy;
218	uint32_t fFeatures;
219	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
220	uint32_t const u32Family = u32CpuVersion >> 8;
221	uint32_t const u32Model = (u32CpuVersion >> 4) & 0xF;
222	uint32_t const u32Stepping = u32CpuVersion & 0xF;
223	if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
224	&& ( u32Family != 6 /* (> pentium pro) */
225	\|\| u32Model >= 3
226	\|\| u32Stepping >= 3
227	\|\| !ASMIsIntelCpu())
228	)
229	{
230	/*
231	* Read the MSR and see if it's in use or not.
232	*/
233	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
234	if (u32)
235	{
236	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSENTER;
237	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
238	}
239	}
240
241	/*
242	* SYSCALL/SYSRET
243	*
244	* This feature is indicated by the SEP bit returned in EDX by CPUID
245	* function 0x80000001. Intel CPUs only supports this feature in
246	* long mode. Since we're not running 64-bit guests in raw-mode there
247	* are no issues with 32-bit intel hosts.
248	*/
249	uint32_t cExt = 0;
250	ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
251	if (ASMIsValidExtRange(cExt))
252	{
253	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
254	if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
255	{
256	#ifdef RT_ARCH_X86
257	if (!ASMIsIntelCpu())
258	#endif
259	{
260	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
261	if (fEfer & MSR_K6_EFER_SCE)
262	{
263	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSCALL;
264	Log(("CPUMR0Init: host uses syscall\n"));
265	}
266	}
267	}
268	}
269
270	/*
271	* Unify/cross check some CPUID feature bits on all available CPU cores
272	* and threads. We've seen CPUs where the monitor support differed.
273	*
274	* Because the hyper heap isn't always mapped into ring-0, we cannot
275	* access it from a RTMpOnAll callback. We use the legacy CPUID arrays
276	* as temp ring-0 accessible memory instead, ASSUMING that they're all
277	* up to date when we get here.
278	*/
279	RTMpOnAll(cpumR0CheckCpuid, pVM, NULL);
280
281	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
282	{
283	bool fIgnored;
284	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
285	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, 0, &fIgnored);
286	if (pLeaf)
287	{
288	PCPUMCPUID pLegacyLeaf;
289	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
290	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
291	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
292	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
293	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
294	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
295	else
296	continue;
297
298	pLeaf->uEcx = pLegacyLeaf->uEcx;
299	pLeaf->uEdx = pLegacyLeaf->uEdx;
300	}
301	}
302
303	}
304
305
306	/*
307	* Check if debug registers are armed.
308	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
309	*/
310	uint32_t u32DR7 = ASMGetDR7();
311	if (u32DR7 & X86_DR7_ENABLED_MASK)
312	{
313	for (VMCPUID i = 0; i < pVM->cCpus; i++)
314	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
315	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
316	}
317
318	return VINF_SUCCESS;
319	}
320
321
322	/**
323	* Trap handler for device-not-available fault (\#NM).
324	* Device not available, FP or (F)WAIT instruction.
325	*
326	* @returns VBox status code.
327	* @retval VINF_SUCCESS if the guest FPU state is loaded.
328	* @retval VINF_EM_RAW_GUEST_TRAP if it is a guest trap.
329	*
330	* @param pVM The cross context VM structure.
331	* @param pVCpu The cross context virtual CPU structure.
332	*/
333	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVM pVM, PVMCPU pVCpu)
334	{
335	Assert(pVM->cpum.s.HostFeatures.fFxSaveRstor);
336	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
337
338	/* If the FPU state has already been loaded, then it's a guest trap. */
339	if (CPUMIsGuestFPUStateActive(pVCpu))
340	{
341	Assert( ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS))
342	\|\| ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM)));
343	return VINF_EM_RAW_GUEST_TRAP;
344	}
345
346	/*
347	* There are two basic actions:
348	* 1. Save host fpu and restore guest fpu.
349	* 2. Generate guest trap.
350	*
351	* When entering the hypervisor we'll always enable MP (for proper wait
352	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
353	* is taken from the guest OS in order to get proper SSE handling.
354	*
355	*
356	* Actions taken depending on the guest CR0 flags:
357	*
358	* 3 2 1
359	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
360	* ------------------------------------------------------------------------
361	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
362	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
363	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
364	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
365	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
366	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
367	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
368	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
369	*/
370
371	switch (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
372	{
373	case X86_CR0_MP \| X86_CR0_TS:
374	case X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM:
375	return VINF_EM_RAW_GUEST_TRAP;
376	default:
377	break;
378	}
379
380	return CPUMR0LoadGuestFPU(pVM, pVCpu);
381	}
382
383
384	/**
385	* Saves the host-FPU/XMM state (if necessary) and (always) loads the guest-FPU
386	* state into the CPU.
387	*
388	* @returns VINF_SUCCESS (for CPUMR0Trap07Handler).
389	*
390	* @param pVM The cross context VM structure.
391	* @param pVCpu The cross context virtual CPU structure.
392	*/
393	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu)
394	{
395	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
396	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST));
397	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
398
399	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
400	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
401	{
402	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
403
404	/* Save the host state if necessary. */
405	if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST))
406	cpumRZSaveHostFPUState(&pVCpu->cpum.s);
407
408	/* Restore the state on entry as we need to be in 64-bit mode to access the full state. */
409	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_FPU_STATE;
410
411	Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM))
412	== (CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM));
413	}
414	else
415	#endif
416	{
417	if (!pVM->cpum.s.HostFeatures.fLeakyFxSR)
418	{
419	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
420	cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
421	}
422	else
423	{
424	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE) \|\| (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST));
425	/** @todo r=ramshankar: Can't we used a cached value here
426	* instead of reading the MSR? host EFER doesn't usually
427	* change. */
428	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
429	if (!(uHostEfer & MSR_K6_EFER_FFXSR))
430	cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
431	else
432	{
433	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
434	pVCpu->cpum.s.fUseFlags \|= CPUM_USED_MANUAL_XMM_RESTORE;
435	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
436	cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
437	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
438	ASMSetFlags(uSavedFlags);
439	}
440	}
441	Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM))
442	== (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM));
443	}
444	return VINF_SUCCESS;
445	}
446
447
448	/**
449	* Saves the guest FPU/XMM state if needed, restores the host FPU/XMM state as
450	* needed.
451	*
452	* @returns true if we saved the guest state.
453	* @param pVCpu The cross context virtual CPU structure.
454	*/
455	VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu)
456	{
457	bool fSavedGuest;
458	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.HostFeatures.fFxSaveRstor);
459	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
460	if (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST))
461	{
462	fSavedGuest = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
463	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
464	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
465	{
466	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST)
467	{
468	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
469	HMR0SaveFPUState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
470	}
471	else
472	pVCpu->cpum.s.fUseFlags &= ~CPUM_SYNC_FPU_STATE;
473	cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
474	}
475	else
476	#endif
477	{
478	if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE))
479	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
480	else
481	{
482	/* Temporarily clear MSR_K6_EFER_FFXSR or else we'll be unable to
483	save/restore the XMM state with fxsave/fxrstor. */
484	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
485	if (uHostEfer & MSR_K6_EFER_FFXSR)
486	{
487	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
488	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
489	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
490	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
491	ASMSetFlags(uSavedFlags);
492	}
493	else
494	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
495	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_MANUAL_XMM_RESTORE;
496	}
497	}
498	}
499	else
500	fSavedGuest = false;
501	Assert(!( pVCpu->cpum.s.fUseFlags
502	& (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_SYNC_FPU_STATE \| CPUM_USED_MANUAL_XMM_RESTORE)));
503	return fSavedGuest;
504	}
505
506
507	/**
508	* Saves the host debug state, setting CPUM_USED_HOST_DEBUG_STATE and loading
509	* DR7 with safe values.
510	*
511	* @returns VBox status code.
512	* @param pVCpu The cross context virtual CPU structure.
513	*/
514	static int cpumR0SaveHostDebugState(PVMCPU pVCpu)
515	{
516	/*
517	* Save the host state.
518	*/
519	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
520	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
521	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
522	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
523	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
524	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
525	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
526
527	/* Preemption paranoia. */
528	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HOST);
529
530	/*
531	* Make sure DR7 is harmless or else we could trigger breakpoints when
532	* load guest or hypervisor DRx values later.
533	*/
534	if (pVCpu->cpum.s.Host.dr7 != X86_DR7_INIT_VAL)
535	ASMSetDR7(X86_DR7_INIT_VAL);
536
537	return VINF_SUCCESS;
538	}
539
540
541	/**
542	* Saves the guest DRx state residing in host registers and restore the host
543	* register values.
544	*
545	* The guest DRx state is only saved if CPUMR0LoadGuestDebugState was called,
546	* since it's assumed that we're shadowing the guest DRx register values
547	* accurately when using the combined hypervisor debug register values
548	* (CPUMR0LoadHyperDebugState).
549	*
550	* @returns true if either guest or hypervisor debug registers were loaded.
551	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
552	* @param fDr6 Whether to include DR6 or not.
553	* @thread EMT(pVCpu)
554	*/
555	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPU pVCpu, bool fDr6)
556	{
557	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
558	bool const fDrXLoaded = RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
559
560	/*
561	* Do we need to save the guest DRx registered loaded into host registers?
562	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
563	*/
564	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
565	{
566	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
567	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
568	{
569	uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
570	HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
571	if (!fDr6)
572	pVCpu->cpum.s.Guest.dr[6] = uDr6;
573	}
574	else
575	#endif
576	{
577	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
578	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
579	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
580	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
581	if (fDr6)
582	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
583	}
584	}
585	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~( CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER
586	\| CPUM_SYNC_DEBUG_REGS_GUEST \| CPUM_SYNC_DEBUG_REGS_HYPER));
587
588	/*
589	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
590	*/
591	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST)
592	{
593	/* A bit of paranoia first... */
594	uint64_t uCurDR7 = ASMGetDR7();
595	if (uCurDR7 != X86_DR7_INIT_VAL)
596	ASMSetDR7(X86_DR7_INIT_VAL);
597
598	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
599	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
600	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
601	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
602	/** @todo consider only updating if they differ, esp. DR6. Need to figure how
603	* expensive DRx reads are over DRx writes. */
604	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
605	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
606
607	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HOST);
608	}
609
610	return fDrXLoaded;
611	}
612
613
614	/**
615	* Saves the guest DRx state if it resides host registers.
616	*
617	* This does NOT clear any use flags, so the host registers remains loaded with
618	* the guest DRx state upon return. The purpose is only to make sure the values
619	* in the CPU context structure is up to date.
620	*
621	* @returns true if the host registers contains guest values, false if not.
622	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
623	* @param fDr6 Whether to include DR6 or not.
624	* @thread EMT(pVCpu)
625	*/
626	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPU pVCpu, bool fDr6)
627	{
628	/*
629	* Do we need to save the guest DRx registered loaded into host registers?
630	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
631	*/
632	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
633	{
634	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
635	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
636	{
637	uint64_t uDr6 = pVCpu->cpum.s.Guest.dr[6];
638	HMR0SaveDebugState(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.s.Guest);
639	if (!fDr6)
640	pVCpu->cpum.s.Guest.dr[6] = uDr6;
641	}
642	else
643	#endif
644	{
645	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
646	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
647	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
648	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
649	if (fDr6)
650	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
651	}
652	return true;
653	}
654	return false;
655	}
656
657
658	/**
659	* Lazily sync in the debug state.
660	*
661	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
662	* @param fDr6 Whether to include DR6 or not.
663	* @thread EMT(pVCpu)
664	*/
665	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPU pVCpu, bool fDr6)
666	{
667	/*
668	* Save the host state and disarm all host BPs.
669	*/
670	cpumR0SaveHostDebugState(pVCpu);
671	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
672
673	/*
674	* Activate the guest state DR0-3.
675	* DR7 and DR6 (if fDr6 is true) are left to the caller.
676	*/
677	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
678	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
679	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_SYNC_DEBUG_REGS_GUEST); /* Postpone it to the world switch. */
680	else
681	#endif
682	{
683	ASMSetDR0(pVCpu->cpum.s.Guest.dr[0]);
684	ASMSetDR1(pVCpu->cpum.s.Guest.dr[1]);
685	ASMSetDR2(pVCpu->cpum.s.Guest.dr[2]);
686	ASMSetDR3(pVCpu->cpum.s.Guest.dr[3]);
687	if (fDr6)
688	ASMSetDR6(pVCpu->cpum.s.Guest.dr[6]);
689
690	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
691	}
692	}
693
694
695	/**
696	* Lazily sync in the hypervisor debug state
697	*
698	* @returns VBox status code.
699	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
700	* @param fDr6 Whether to include DR6 or not.
701	* @thread EMT(pVCpu)
702	*/
703	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPU pVCpu, bool fDr6)
704	{
705	/*
706	* Save the host state and disarm all host BPs.
707	*/
708	cpumR0SaveHostDebugState(pVCpu);
709	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
710
711	/*
712	* Make sure the hypervisor values are up to date.
713	*/
714	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */, true);
715
716	/*
717	* Activate the guest state DR0-3.
718	* DR7 and DR6 (if fDr6 is true) are left to the caller.
719	*/
720	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
721	if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.s.Guest))
722	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_SYNC_DEBUG_REGS_HYPER); /* Postpone it. */
723	else
724	#endif
725	{
726	ASMSetDR0(pVCpu->cpum.s.Hyper.dr[0]);
727	ASMSetDR1(pVCpu->cpum.s.Hyper.dr[1]);
728	ASMSetDR2(pVCpu->cpum.s.Hyper.dr[2]);
729	ASMSetDR3(pVCpu->cpum.s.Hyper.dr[3]);
730	if (fDr6)
731	ASMSetDR6(X86_DR6_INIT_VAL);
732
733	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
734	}
735	}
736
737	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
738
739	/**
740	* Per-CPU callback that probes the CPU for APIC support.
741	*
742	* @param idCpu The identifier for the CPU the function is called on.
743	* @param pvUser1 Ignored.
744	* @param pvUser2 Ignored.
745	*/
746	static DECLCALLBACK(void) cpumR0MapLocalApicCpuProber(RTCPUID idCpu, void pvUser1, void pvUser2)
747	{
748	NOREF(pvUser1); NOREF(pvUser2);
749	int iCpu = RTMpCpuIdToSetIndex(idCpu);
750	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
751
752	/*
753	* Check for APIC support.
754	*/
755	uint32_t uMaxLeaf, u32EBX, u32ECX, u32EDX;
756	ASMCpuId(0, &uMaxLeaf, &u32EBX, &u32ECX, &u32EDX);
757	if ( ( ASMIsIntelCpuEx(u32EBX, u32ECX, u32EDX)
758	\|\| ASMIsAmdCpuEx(u32EBX, u32ECX, u32EDX)
759	\|\| ASMIsViaCentaurCpuEx(u32EBX, u32ECX, u32EDX))
760	&& ASMIsValidStdRange(uMaxLeaf))
761	{
762	uint32_t uDummy;
763	ASMCpuId(1, &uDummy, &u32EBX, &u32ECX, &u32EDX);
764	if ( (u32EDX & X86_CPUID_FEATURE_EDX_APIC)
765	&& (u32EDX & X86_CPUID_FEATURE_EDX_MSR))
766	{
767	/*
768	* Safe to access the MSR. Read it and calc the BASE (a little complicated).
769	*/
770	uint64_t u64ApicBase = ASMRdMsr(MSR_IA32_APICBASE);
771	uint64_t u64Mask = MSR_IA32_APICBASE_BASE_MIN;
772
773	/* see Intel Manual: Local APIC Status and Location: MAXPHYADDR default is bit 36 */
774	uint32_t uMaxExtLeaf;
775	ASMCpuId(0x80000000, &uMaxExtLeaf, &u32EBX, &u32ECX, &u32EDX);
776	if ( uMaxExtLeaf >= UINT32_C(0x80000008)
777	&& ASMIsValidExtRange(uMaxExtLeaf))
778	{
779	uint32_t u32PhysBits;
780	ASMCpuId(0x80000008, &u32PhysBits, &u32EBX, &u32ECX, &u32EDX);
781	u32PhysBits &= 0xff;
782	u64Mask = ((UINT64_C(1) << u32PhysBits) - 1) & UINT64_C(0xfffffffffffff000);
783	}
784
785	AssertCompile(sizeof(g_aLApics[iCpu].PhysBase) == sizeof(u64ApicBase));
786	g_aLApics[iCpu].PhysBase = u64ApicBase & u64Mask;
787	g_aLApics[iCpu].fEnabled = RT_BOOL(u64ApicBase & MSR_IA32_APICBASE_EN);
788	g_aLApics[iCpu].fX2Apic = (u64ApicBase & (MSR_IA32_APICBASE_EXTD \| MSR_IA32_APICBASE_EN))
789	== (MSR_IA32_APICBASE_EXTD \| MSR_IA32_APICBASE_EN);
790	}
791	}
792	}
793
794
795
796	/**
797	* Per-CPU callback that verifies our APIC expectations.
798	*
799	* @param idCpu The identifier for the CPU the function is called on.
800	* @param pvUser1 Ignored.
801	* @param pvUser2 Ignored.
802	*/
803	static DECLCALLBACK(void) cpumR0MapLocalApicCpuChecker(RTCPUID idCpu, void pvUser1, void pvUser2)
804	{
805	NOREF(pvUser1); NOREF(pvUser2);
806
807	int iCpu = RTMpCpuIdToSetIndex(idCpu);
808	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
809	if (!g_aLApics[iCpu].fEnabled)
810	return;
811
812	/*
813	* 0x0X 82489 external APIC
814	* 0x1X Local APIC
815	* 0x2X..0xFF reserved
816	*/
817	uint32_t uApicVersion;
818	if (g_aLApics[iCpu].fX2Apic)
819	uApicVersion = ApicX2RegRead32(APIC_REG_VERSION);
820	else
821	uApicVersion = ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_VERSION);
822	if ((APIC_REG_VERSION_GET_VER(uApicVersion) & 0xF0) == 0x10)
823	{
824	g_aLApics[iCpu].uVersion = uApicVersion;
825
826	#if 0 /* enable if you need it. */
827	if (g_aLApics[iCpu].fX2Apic)
828	SUPR0Printf("CPUM: X2APIC %02u - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
829	iCpu, uApicVersion,
830	ApicX2RegRead32(APIC_REG_LVT_LINT0), ApicX2RegRead32(APIC_REG_LVT_LINT1),
831	ApicX2RegRead32(APIC_REG_LVT_PC), ApicX2RegRead32(APIC_REG_LVT_THMR),
832	ApicX2RegRead32(APIC_REG_LVT_CMCI));
833	else
834	{
835	SUPR0Printf("CPUM: APIC %02u at %RGp (mapped at %p) - ver %#010x, lint0=%#07x lint1=%#07x pc=%#07x thmr=%#07x cmci=%#07x\n",
836	iCpu, g_aLApics[iCpu].PhysBase, g_aLApics[iCpu].pv, uApicVersion,
837	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT0), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_LINT1),
838	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_PC), ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_THMR),
839	ApicRegRead(g_aLApics[iCpu].pv, APIC_REG_LVT_CMCI));
840	if (uApicVersion & 0x80000000)
841	{
842	uint32_t uExtFeatures = ApicRegRead(g_aLApics[iCpu].pv, 0x400);
843	uint32_t cEiLvt = (uExtFeatures >> 16) & 0xff;
844	SUPR0Printf("CPUM: APIC %02u: ExtSpace available. extfeat=%08x eilvt[0..3]=%08x %08x %08x %08x\n",
845	iCpu,
846	ApicRegRead(g_aLApics[iCpu].pv, 0x400),
847	cEiLvt >= 1 ? ApicRegRead(g_aLApics[iCpu].pv, 0x500) : 0,
848	cEiLvt >= 2 ? ApicRegRead(g_aLApics[iCpu].pv, 0x510) : 0,
849	cEiLvt >= 3 ? ApicRegRead(g_aLApics[iCpu].pv, 0x520) : 0,
850	cEiLvt >= 4 ? ApicRegRead(g_aLApics[iCpu].pv, 0x530) : 0);
851	}
852	}
853	#endif
854	}
855	else
856	{
857	g_aLApics[iCpu].fEnabled = false;
858	g_aLApics[iCpu].fX2Apic = false;
859	SUPR0Printf("VBox/CPUM: Unsupported APIC version %#x (iCpu=%d)\n", uApicVersion, iCpu);
860	}
861	}
862
863
864	/**
865	* Map the MMIO page of each local APIC in the system.
866	*/
867	static int cpumR0MapLocalApics(void)
868	{
869	/*
870	* Check that we'll always stay within the array bounds.
871	*/
872	if (RTMpGetArraySize() > RT_ELEMENTS(g_aLApics))
873	{
874	LogRel(("CPUM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_aLApics)));
875	return VERR_TOO_MANY_CPUS;
876	}
877
878	/*
879	* Create mappings for all online CPUs we think have legacy APICs.
880	*/
881	int rc = RTMpOnAll(cpumR0MapLocalApicCpuProber, NULL, NULL);
882
883	for (unsigned iCpu = 0; RT_SUCCESS(rc) && iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
884	{
885	if (g_aLApics[iCpu].fEnabled && !g_aLApics[iCpu].fX2Apic)
886	{
887	rc = RTR0MemObjEnterPhys(&g_aLApics[iCpu].hMemObj, g_aLApics[iCpu].PhysBase,
888	PAGE_SIZE, RTMEM_CACHE_POLICY_MMIO);
889	if (RT_SUCCESS(rc))
890	{
891	rc = RTR0MemObjMapKernel(&g_aLApics[iCpu].hMapObj, g_aLApics[iCpu].hMemObj, (void *)-1,
892	PAGE_SIZE, RTMEM_PROT_READ \| RTMEM_PROT_WRITE);
893	if (RT_SUCCESS(rc))
894	{
895	g_aLApics[iCpu].pv = RTR0MemObjAddress(g_aLApics[iCpu].hMapObj);
896	continue;
897	}
898	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
899	}
900	g_aLApics[iCpu].fEnabled = false;
901	}
902	g_aLApics[iCpu].pv = NULL;
903	}
904
905	/*
906	* Check the APICs.
907	*/
908	if (RT_SUCCESS(rc))
909	rc = RTMpOnAll(cpumR0MapLocalApicCpuChecker, NULL, NULL);
910
911	if (RT_FAILURE(rc))
912	{
913	cpumR0UnmapLocalApics();
914	return rc;
915	}
916
917	#ifdef LOG_ENABLED
918	/*
919	* Log the result (pretty useless, requires enabling CPUM in VBoxDrv
920	* and !VBOX_WITH_R0_LOGGING).
921	*/
922	if (LogIsEnabled())
923	{
924	uint32_t cEnabled = 0;
925	uint32_t cX2Apics = 0;
926	for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
927	if (g_aLApics[iCpu].fEnabled)
928	{
929	cEnabled++;
930	cX2Apics += g_aLApics[iCpu].fX2Apic;
931	}
932	Log(("CPUM: %u APICs, %u X2APICs\n", cEnabled, cX2Apics));
933	}
934	#endif
935
936	return VINF_SUCCESS;
937	}
938
939
940	/**
941	* Unmap the Local APIC of all host CPUs.
942	*/
943	static void cpumR0UnmapLocalApics(void)
944	{
945	for (unsigned iCpu = RT_ELEMENTS(g_aLApics); iCpu-- > 0;)
946	{
947	if (g_aLApics[iCpu].pv)
948	{
949	RTR0MemObjFree(g_aLApics[iCpu].hMapObj, true /* fFreeMappings */);
950	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
951	g_aLApics[iCpu].hMapObj = NIL_RTR0MEMOBJ;
952	g_aLApics[iCpu].hMemObj = NIL_RTR0MEMOBJ;
953	g_aLApics[iCpu].fEnabled = false;
954	g_aLApics[iCpu].fX2Apic = false;
955	g_aLApics[iCpu].pv = NULL;
956	}
957	}
958	}
959
960
961	/**
962	* Updates CPUMCPU::pvApicBase and CPUMCPU::fX2Apic prior to world switch.
963	*
964	* Writes the Local APIC mapping address of the current host CPU to CPUMCPU so
965	* the world switchers can access the APIC registers for the purpose of
966	* disabling and re-enabling the NMIs. Must be called with disabled preemption
967	* or disabled interrupts!
968	*
969	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
970	* @param iHostCpuSet The CPU set index of the current host CPU.
971	*/
972	VMMR0_INT_DECL(void) CPUMR0SetLApic(PVMCPU pVCpu, uint32_t iHostCpuSet)
973	{
974	Assert(iHostCpuSet <= RT_ELEMENTS(g_aLApics));
975	pVCpu->cpum.s.pvApicBase = g_aLApics[iHostCpuSet].pv;
976	pVCpu->cpum.s.fX2Apic = g_aLApics[iHostCpuSet].fX2Apic;
977	// Log6(("CPUMR0SetLApic: pvApicBase=%p fX2Apic=%d\n", g_aLApics[idxCpu].pv, g_aLApics[idxCpu].fX2Apic));
978	}
979
980	#endif /* VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI */
981

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source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 61068

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