CPUMR0.cpp@ 37529

Last change on this file since 37529 was 36236, checked in by vboxsync, 14 years ago
HWACCMR0: CPU bounds check. CPUMR0: updated message.
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1	/* $Id: CPUMR0.cpp 36236 2011-03-09 17:27:22Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/x86.h>
27	#include <VBox/err.h>
28	#include <VBox/log.h>
29	#include <VBox/vmm/hwaccm.h>
30	#include <iprt/assert.h>
31	#include <iprt/asm-amd64-x86.h>
32	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
33	# include <iprt/mem.h>
34	# include <iprt/memobj.h>
35	# include <VBox/apic.h>
36	#endif
37
38
39	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
40	/** Local APIC mappings */
41	typedef struct
42	{
43	bool fEnabled;
44	uint64_t PhysBase;
45	RTR0MEMOBJ hMemObj;
46	RTR0MEMOBJ hMapObj;
47	void *pv;
48	uint32_t fHasThermal;
49	} CPUMHOSTLAPIC;
50
51	static CPUMHOSTLAPIC g_aLApics[RTCPUSET_MAX_CPUS];
52	static int cpumR0MapLocalApics(void);
53	static void cpumR0UnmapLocalApics(void);
54	#endif
55
56
57	/**
58	* Does the Ring-0 CPU initialization once during module load.
59	* XXX Host-CPU hot-plugging?
60	*/
61	VMMR0DECL(int) CPUMR0ModuleInit(void)
62	{
63	int rc = VINF_SUCCESS;
64	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
65	rc = cpumR0MapLocalApics();
66	#endif
67	return rc;
68	}
69
70
71	/**
72	* Terminate the module.
73	*/
74	VMMR0DECL(int) CPUMR0ModuleTerm(void)
75	{
76	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
77	cpumR0UnmapLocalApics();
78	#endif
79	return VINF_SUCCESS;
80	}
81
82
83	/**
84	* Does Ring-0 CPUM initialization.
85	*
86	* This is mainly to check that the Host CPU mode is compatible
87	* with VBox.
88	*
89	* @returns VBox status code.
90	* @param pVM The VM to operate on.
91	*/
92	VMMR0DECL(int) CPUMR0Init(PVM pVM)
93	{
94	LogFlow(("CPUMR0Init: %p\n", pVM));
95
96	/*
97	* Check CR0 & CR4 flags.
98	*/
99	uint32_t u32CR0 = ASMGetCR0();
100	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
101	{
102	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
103	return VERR_UNSUPPORTED_CPU_MODE;
104	}
105
106	/*
107	* Check for sysenter and syscall usage.
108	*/
109	if (ASMHasCpuId())
110	{
111	/*
112	* SYSENTER/SYSEXIT
113	*
114	* Intel docs claim you should test both the flag and family, model &
115	* stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
116	* but don't support it. AMD CPUs may support this feature in legacy
117	* mode, they've banned it from long mode. Since we switch to 32-bit
118	* mode when entering raw-mode context the feature would become
119	* accessible again on AMD CPUs, so we have to check regardless of
120	* host bitness.
121	*/
122	uint32_t u32CpuVersion;
123	uint32_t u32Dummy;
124	uint32_t fFeatures;
125	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
126	uint32_t u32Family = u32CpuVersion >> 8;
127	uint32_t u32Model = (u32CpuVersion >> 4) & 0xF;
128	uint32_t u32Stepping = u32CpuVersion & 0xF;
129	if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
130	&& ( u32Family != 6 /* (> pentium pro) */
131	\|\| u32Model >= 3
132	\|\| u32Stepping >= 3
133	\|\| !ASMIsIntelCpu())
134	)
135	{
136	/*
137	* Read the MSR and see if it's in use or not.
138	*/
139	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
140	if (u32)
141	{
142	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSENTER;
143	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
144	}
145	}
146
147	/*
148	* SYSCALL/SYSRET
149	*
150	* This feature is indicated by the SEP bit returned in EDX by CPUID
151	* function 0x80000001. Intel CPUs only supports this feature in
152	* long mode. Since we're not running 64-bit guests in raw-mode there
153	* are no issues with 32-bit intel hosts.
154	*/
155	uint32_t cExt = 0;
156	ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
157	if ( cExt >= 0x80000001
158	&& cExt <= 0x8000ffff)
159	{
160	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
161	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_SEP)
162	{
163	#ifdef RT_ARCH_X86
164	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
165	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE)
166	# else
167	if (!ASMIsIntelCpu())
168	# endif
169	#endif
170	{
171	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
172	if (fEfer & MSR_K6_EFER_SCE)
173	{
174	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSCALL;
175	Log(("CPUMR0Init: host uses syscall\n"));
176	}
177	}
178	}
179	}
180	}
181
182
183	/*
184	* Check if debug registers are armed.
185	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
186	*/
187	uint32_t u32DR7 = ASMGetDR7();
188	if (u32DR7 & X86_DR7_ENABLED_MASK)
189	{
190	for (VMCPUID i = 0; i < pVM->cCpus; i++)
191	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
192	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
193	}
194
195	return VINF_SUCCESS;
196	}
197
198
199	/**
200	* Lazily sync in the FPU/XMM state
201	*
202	* @returns VBox status code.
203	* @param pVM VM handle.
204	* @param pVCpu VMCPU handle.
205	* @param pCtx CPU context
206	*/
207	VMMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
208	{
209	Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
210	Assert(ASMGetCR4() & X86_CR4_OSFSXR);
211
212	/* If the FPU state has already been loaded, then it's a guest trap. */
213	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU)
214	{
215	Assert( ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
216	\|\| ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS)));
217	return VINF_EM_RAW_GUEST_TRAP;
218	}
219
220	/*
221	* There are two basic actions:
222	* 1. Save host fpu and restore guest fpu.
223	* 2. Generate guest trap.
224	*
225	* When entering the hypervisor we'll always enable MP (for proper wait
226	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
227	* is taken from the guest OS in order to get proper SSE handling.
228	*
229	*
230	* Actions taken depending on the guest CR0 flags:
231	*
232	* 3 2 1
233	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
234	* ------------------------------------------------------------------------
235	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
236	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
237	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
238	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
239	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
240	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
241	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
242	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
243	*/
244
245	switch (pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
246	{
247	case X86_CR0_MP \| X86_CR0_TS:
248	case X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS:
249	return VINF_EM_RAW_GUEST_TRAP;
250	default:
251	break;
252	}
253
254	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
255	if (CPUMIsGuestInLongModeEx(pCtx))
256	{
257	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
258
259	/* Save the host state and record the fact (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM). */
260	cpumR0SaveHostFPUState(&pVCpu->cpum.s);
261
262	/* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
263	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_FPU_STATE;
264	}
265	else
266	#endif
267	{
268	#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
269	# if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined(VBOX_WITH_KERNEL_USING_XMM) /** @todo remove the #else here and move cpumHandleLazyFPUAsm back to VMMGC after branching out 3.0!!. */
270	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE));
271	/** @todo Move the FFXR handling down into
272	* cpumR0SaveHostRestoreguestFPUState to optimize the
273	* VBOX_WITH_KERNEL_USING_XMM handling. */
274	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
275	uint64_t SavedEFER = 0;
276	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
277	{
278	SavedEFER = ASMRdMsr(MSR_K6_EFER);
279	if (SavedEFER & MSR_K6_EFER_FFXSR)
280	{
281	ASMWrMsr(MSR_K6_EFER, SavedEFER & ~MSR_K6_EFER_FFXSR);
282	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
283	}
284	}
285
286	/* Do the job and record that we've switched FPU state. */
287	cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
288
289	/* Restore EFER. */
290	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
291	ASMWrMsr(MSR_K6_EFER, SavedEFER);
292
293	# else
294	uint64_t oldMsrEFERHost = 0;
295	uint32_t oldCR0 = ASMGetCR0();
296
297	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
298	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
299	{
300	/** @todo Do we really need to read this every time?? The host could change this on the fly though.
301	* bird: what about starting by skipping the ASMWrMsr below if we didn't
302	* change anything? Ditto for the stuff in CPUMR0SaveGuestFPU. */
303	oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
304	if (oldMsrEFERHost & MSR_K6_EFER_FFXSR)
305	{
306	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
307	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
308	}
309	}
310
311	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
312	int rc = CPUMHandleLazyFPU(pVCpu);
313	AssertRC(rc);
314	Assert(CPUMIsGuestFPUStateActive(pVCpu));
315
316	/* Restore EFER MSR */
317	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
318	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost);
319
320	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
321	ASMSetCR0(oldCR0);
322	# endif
323
324	#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
325
326	/*
327	* Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
328	* We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
329	*/
330	pVCpu->cpum.s.Host.fpu.FCW = CPUMGetFCW();
331	if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
332	pVCpu->cpum.s.Host.fpu.MXCSR = CPUMGetMXCSR();
333
334	cpumR0LoadFPU(pCtx);
335
336	/*
337	* The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
338	*
339	* MSR_K6_EFER_FFXSR changes the behaviour of fxsave and fxrstore: the XMM state isn't saved/restored
340	*/
341	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
342	{
343	/** @todo Do we really need to read this every time?? The host could change this on the fly though. */
344	uint64_t msrEFERHost = ASMRdMsr(MSR_K6_EFER);
345
346	if (msrEFERHost & MSR_K6_EFER_FFXSR)
347	{
348	/* fxrstor doesn't restore the XMM state! */
349	cpumR0LoadXMM(pCtx);
350	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
351	}
352	}
353
354	#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
355	}
356
357	Assert((pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM)) == (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM));
358	return VINF_SUCCESS;
359	}
360
361
362	/**
363	* Save guest FPU/XMM state
364	*
365	* @returns VBox status code.
366	* @param pVM VM handle.
367	* @param pVCpu VMCPU handle.
368	* @param pCtx CPU context
369	*/
370	VMMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
371	{
372	Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
373	Assert(ASMGetCR4() & X86_CR4_OSFSXR);
374	AssertReturn((pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU), VINF_SUCCESS);
375
376	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
377	if (CPUMIsGuestInLongModeEx(pCtx))
378	{
379	if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE))
380	{
381	HWACCMR0SaveFPUState(pVM, pVCpu, pCtx);
382	cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
383	}
384	/* else nothing to do; we didn't perform a world switch */
385	}
386	else
387	#endif
388	{
389	#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
390	# ifdef VBOX_WITH_KERNEL_USING_XMM
391	/*
392	* We've already saved the XMM registers in the assembly wrapper, so
393	* we have to save them before saving the entire FPU state and put them
394	* back afterwards.
395	*/
396	/** @todo This could be skipped if MSR_K6_EFER_FFXSR is set, but
397	* I'm not able to test such an optimization tonight.
398	* We could just all this in assembly. */
399	uint128_t aGuestXmmRegs[16];
400	memcpy(&aGuestXmmRegs[0], &pVCpu->cpum.s.Guest.fpu.aXMM[0], sizeof(aGuestXmmRegs));
401	# endif
402
403	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
404	uint64_t oldMsrEFERHost = 0;
405	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
406	{
407	oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
408	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
409	}
410	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
411
412	/* Restore EFER MSR */
413	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
414	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost \| MSR_K6_EFER_FFXSR);
415
416	# ifdef VBOX_WITH_KERNEL_USING_XMM
417	memcpy(&pVCpu->cpum.s.Guest.fpu.aXMM[0], &aGuestXmmRegs[0], sizeof(aGuestXmmRegs));
418	# endif
419
420	#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
421	# ifdef VBOX_WITH_KERNEL_USING_XMM
422	# error "Fix all the NM_TRAPS_IN_KERNEL_MODE code path. I'm not going to fix unused code now."
423	# endif
424	cpumR0SaveFPU(pCtx);
425	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
426	{
427	/* fxsave doesn't save the XMM state! */
428	cpumR0SaveXMM(pCtx);
429	}
430
431	/*
432	* Restore the original FPU control word and MXCSR.
433	* We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
434	*/
435	cpumR0SetFCW(pVCpu->cpum.s.Host.fpu.FCW);
436	if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
437	cpumR0SetMXCSR(pVCpu->cpum.s.Host.fpu.MXCSR);
438	#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
439	}
440
441	pVCpu->cpum.s.fUseFlags &= ~(CPUM_USED_FPU \| CPUM_SYNC_FPU_STATE \| CPUM_MANUAL_XMM_RESTORE);
442	return VINF_SUCCESS;
443	}
444
445
446	/**
447	* Save guest debug state
448	*
449	* @returns VBox status code.
450	* @param pVM VM handle.
451	* @param pVCpu VMCPU handle.
452	* @param pCtx CPU context
453	* @param fDR6 Include DR6 or not
454	*/
455	VMMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
456	{
457	Assert(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS);
458
459	/* Save the guest's debug state. The caller is responsible for DR7. */
460	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
461	if (CPUMIsGuestInLongModeEx(pCtx))
462	{
463	if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_DEBUG_STATE))
464	{
465	uint64_t dr6 = pCtx->dr[6];
466
467	HWACCMR0SaveDebugState(pVM, pVCpu, pCtx);
468	if (!fDR6) /* dr6 was already up-to-date */
469	pCtx->dr[6] = dr6;
470	}
471	}
472	else
473	#endif
474	{
475	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
476	cpumR0SaveDRx(&pCtx->dr[0]);
477	#else
478	pCtx->dr[0] = ASMGetDR0();
479	pCtx->dr[1] = ASMGetDR1();
480	pCtx->dr[2] = ASMGetDR2();
481	pCtx->dr[3] = ASMGetDR3();
482	#endif
483	if (fDR6)
484	pCtx->dr[6] = ASMGetDR6();
485	}
486
487	/*
488	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
489	* DR7 contains 0x400 right now.
490	*/
491	CPUMR0LoadHostDebugState(pVM, pVCpu);
492	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS));
493	return VINF_SUCCESS;
494	}
495
496
497	/**
498	* Lazily sync in the debug state
499	*
500	* @returns VBox status code.
501	* @param pVM VM handle.
502	* @param pVCpu VMCPU handle.
503	* @param pCtx CPU context
504	* @param fDR6 Include DR6 or not
505	*/
506	VMMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
507	{
508	/* Save the host state. */
509	CPUMR0SaveHostDebugState(pVM, pVCpu);
510	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
511
512	/* Activate the guest state DR0-3; DR7 is left to the caller. */
513	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
514	if (CPUMIsGuestInLongModeEx(pCtx))
515	{
516	/* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
517	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_DEBUG_STATE;
518	}
519	else
520	#endif
521	{
522	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
523	cpumR0LoadDRx(&pCtx->dr[0]);
524	#else
525	ASMSetDR0(pCtx->dr[0]);
526	ASMSetDR1(pCtx->dr[1]);
527	ASMSetDR2(pCtx->dr[2]);
528	ASMSetDR3(pCtx->dr[3]);
529	#endif
530	if (fDR6)
531	ASMSetDR6(pCtx->dr[6]);
532	}
533
534	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS;
535	return VINF_SUCCESS;
536	}
537
538	/**
539	* Save the host debug state
540	*
541	* @returns VBox status code.
542	* @param pVM VM handle.
543	* @param pVCpu VMCPU handle.
544	*/
545	VMMR0DECL(int) CPUMR0SaveHostDebugState(PVM pVM, PVMCPU pVCpu)
546	{
547	/* Save the host state. */
548	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
549	AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
550	cpumR0SaveDRx(&pVCpu->cpum.s.Host.dr0);
551	#else
552	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
553	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
554	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
555	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
556	#endif
557	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
558	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
559	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
560	/* Make sure DR7 is harmless or else we could trigger breakpoints when restoring dr0-3 (!) */
561	ASMSetDR7(X86_DR7_INIT_VAL);
562
563	return VINF_SUCCESS;
564	}
565
566	/**
567	* Load the host debug state
568	*
569	* @returns VBox status code.
570	* @param pVM VM handle.
571	* @param pVCpu VMCPU handle.
572	*/
573	VMMR0DECL(int) CPUMR0LoadHostDebugState(PVM pVM, PVMCPU pVCpu)
574	{
575	Assert(pVCpu->cpum.s.fUseFlags & (CPUM_USE_DEBUG_REGS \| CPUM_USE_DEBUG_REGS_HYPER));
576
577	/*
578	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
579	* DR7 contains 0x400 right now.
580	*/
581	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
582	AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
583	cpumR0LoadDRx(&pVCpu->cpum.s.Host.dr0);
584	#else
585	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
586	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
587	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
588	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
589	#endif
590	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
591	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
592
593	pVCpu->cpum.s.fUseFlags &= ~(CPUM_USE_DEBUG_REGS \| CPUM_USE_DEBUG_REGS_HYPER);
594	return VINF_SUCCESS;
595	}
596
597
598	/**
599	* Lazily sync in the hypervisor debug state
600	*
601	* @returns VBox status code.
602	* @param pVM VM handle.
603	* @param pVCpu VMCPU handle.
604	* @param pCtx CPU context
605	* @param fDR6 Include DR6 or not
606	*/
607	VMMR0DECL(int) CPUMR0LoadHyperDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
608	{
609	/* Save the host state. */
610	CPUMR0SaveHostDebugState(pVM, pVCpu);
611	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
612
613	/* Activate the guest state DR0-3; DR7 is left to the caller. */
614	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
615	if (CPUMIsGuestInLongModeEx(pCtx))
616	{
617	AssertFailed();
618	return VERR_NOT_IMPLEMENTED;
619	}
620	else
621	#endif
622	{
623	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
624	AssertFailed();
625	return VERR_NOT_IMPLEMENTED;
626	#else
627	ASMSetDR0(CPUMGetHyperDR0(pVCpu));
628	ASMSetDR1(CPUMGetHyperDR1(pVCpu));
629	ASMSetDR2(CPUMGetHyperDR2(pVCpu));
630	ASMSetDR3(CPUMGetHyperDR3(pVCpu));
631	#endif
632	if (fDR6)
633	ASMSetDR6(CPUMGetHyperDR6(pVCpu));
634	}
635
636	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HYPER;
637	return VINF_SUCCESS;
638	}
639
640
641	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
642	/**
643	* Worker for cpumR0MapLocalApics. Check each CPU for a present Local APIC.
644	* Play safe and treat each CPU separate.
645	*/
646	static void cpumR0MapLocalApicWorker(RTCPUID idCpu, void pvUser1, void pvUser2)
647	{
648	int iCpu = RTMpCpuIdToSetIndex(idCpu);
649	AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
650
651	uint32_t u32MaxIdx, u32EBX, u32ECX, u32EDX;
652	ASMCpuId(0, &u32MaxIdx, &u32EBX, &u32ECX, &u32EDX);
653	if ( ( ( u32EBX == X86_CPUID_VENDOR_INTEL_EBX
654	&& u32ECX == X86_CPUID_VENDOR_INTEL_ECX
655	&& u32EDX == X86_CPUID_VENDOR_INTEL_EDX)
656	\|\| ( u32EBX == X86_CPUID_VENDOR_AMD_EBX
657	&& u32ECX == X86_CPUID_VENDOR_AMD_ECX
658	&& u32EDX == X86_CPUID_VENDOR_AMD_EDX))
659	&& u32MaxIdx >= 1)
660	{
661	ASMCpuId(1, &u32MaxIdx, &u32EBX, &u32ECX, &u32EDX);
662	if ( (u32EDX & X86_CPUID_FEATURE_EDX_APIC)
663	&& (u32EDX & X86_CPUID_FEATURE_EDX_MSR))
664	{
665	uint64_t u64ApicBase = ASMRdMsr(MSR_IA32_APICBASE);
666	uint64_t u64Mask = UINT64_C(0x0000000ffffff000);
667
668	/* see Intel Manual: Local APIC Status and Location: MAXPHYADDR default is bit 36 */
669	uint32_t u32MaxExtIdx;
670	ASMCpuId(0x80000000, &u32MaxExtIdx, &u32EBX, &u32ECX, &u32EDX);
671	if ( u32MaxExtIdx >= 0x80000008
672	&& u32MaxExtIdx < 0x8000ffff)
673	{
674	uint32_t u32PhysBits;
675	ASMCpuId(0x80000008, &u32PhysBits, &u32EBX, &u32ECX, &u32EDX);
676	u32PhysBits &= 0xff;
677	u64Mask = ((UINT64_C(1) << u32PhysBits) - 1) & UINT64_C(0xfffffffffffff000);
678	}
679
680	g_aLApics[iCpu].fEnabled = true;
681	g_aLApics[iCpu].PhysBase = u64ApicBase & u64Mask;
682	}
683	}
684	}
685
686
687	/**
688	* Map the MMIO page of each local APIC in the system.
689	*/
690	static int cpumR0MapLocalApics(void)
691	{
692	/*
693	* Check that we'll always stay within the array bounds.
694	*/
695	if (RTMpGetArraySize() > RT_ELEMENTS(g_aLApics))
696	{
697	LogRel(("CPUM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_aLApics)));
698	return VERR_TOO_MANY_CPUS;
699	}
700
701	/*
702	* Create mappings for all online CPUs we think have APICs.
703	*/
704	/** @todo r=bird: This code is not adequately handling CPUs that are
705	* offline or unplugged at init time and later bought into action. */
706	int rc = RTMpOnAll(cpumR0MapLocalApicWorker, NULL, NULL);
707
708	for (unsigned iCpu = 0; RT_SUCCESS(rc) && iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
709	{
710	if (g_aLApics[iCpu].fEnabled)
711	{
712	rc = RTR0MemObjEnterPhys(&g_aLApics[iCpu].hMemObj, g_aLApics[iCpu].PhysBase,
713	PAGE_SIZE, RTMEM_CACHE_POLICY_MMIO);
714	if (RT_SUCCESS(rc))
715	{
716	rc = RTR0MemObjMapKernel(&g_aLApics[iCpu].hMapObj, g_aLApics[iCpu].hMemObj, (void *)-1,
717	PAGE_SIZE, RTMEM_PROT_READ \| RTMEM_PROT_WRITE);
718	if (RT_SUCCESS(rc))
719	{
720	void *pvApicBase = RTR0MemObjAddress(g_aLApics[iCpu].hMapObj);
721
722	/*
723	* 0x0X 82489 external APIC
724	* 0x1X Local APIC
725	* 0x2X..0xFF reserved
726	*/
727	uint32_t ApicVersion = ApicRegRead(pvApicBase, APIC_REG_VERSION);
728	if ((APIC_REG_VERSION_GET_VER(ApicVersion) & 0xF0) == 0x10)
729	{
730	g_aLApics[iCpu].fHasThermal = APIC_REG_VERSION_GET_MAX_LVT(ApicVersion) >= 5;
731	g_aLApics[iCpu].pv = pvApicBase;
732	continue;
733	}
734
735	RTR0MemObjFree(g_aLApics[iCpu].hMapObj, true /* fFreeMappings */);
736	}
737	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
738	}
739	g_aLApics[iCpu].fEnabled = false;
740	}
741	}
742	if (RT_FAILURE(rc))
743	{
744	cpumR0UnmapLocalApics();
745	return rc;
746	}
747
748	return VINF_SUCCESS;
749	}
750
751
752	/**
753	* Unmap the Local APIC of all host CPUs.
754	*/
755	static void cpumR0UnmapLocalApics(void)
756	{
757	for (unsigned iCpu = RT_ELEMENTS(g_aLApics); iCpu-- > 0;)
758	{
759	if (g_aLApics[iCpu].pv)
760	{
761	RTR0MemObjFree(g_aLApics[iCpu].hMapObj, true /* fFreeMappings */);
762	RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
763	g_aLApics[iCpu].hMapObj = NIL_RTR0MEMOBJ;
764	g_aLApics[iCpu].hMemObj = NIL_RTR0MEMOBJ;
765	g_aLApics[iCpu].fEnabled = false;
766	g_aLApics[iCpu].pv = NULL;
767	}
768	}
769	}
770
771
772	/**
773	* Write the Local APIC mapping address of the current host CPU to CPUM to be
774	* able to access the APIC registers in the raw mode switcher for disabling/
775	* re-enabling the NMI. Must be called with disabled preemption or disabled
776	* interrupts!
777	*
778	* @param pVM VM handle.
779	* @param idHostCpu The ID of the current host CPU.
780	*/
781	VMMR0DECL(void) CPUMR0SetLApic(PVM pVM, RTCPUID idHostCpu)
782	{
783	pVM->cpum.s.pvApicBase = g_aLApics[RTMpCpuIdToSetIndex(idHostCpu)].pv;
784	}
785
786	#endif /* VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI */

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source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 37529

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