CPUMR0.cpp@ 21937

Last change on this file since 21937 was 21937, checked in by vboxsync, 15 years ago
Fixed wrong check for sysenter.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 18.7 KB

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1	/* $Id: CPUMR0.cpp 21937 2009-08-03 08:50:47Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_CPUM
27	#include <VBox/cpum.h>
28	#include "CPUMInternal.h"
29	#include <VBox/vm.h>
30	#include <VBox/x86.h>
31	#include <VBox/err.h>
32	#include <VBox/log.h>
33	#include <VBox/hwaccm.h>
34	#include <iprt/assert.h>
35	#include <iprt/asm.h>
36
37
38
39	/**
40	* Does Ring-0 CPUM initialization.
41	*
42	* This is mainly to check that the Host CPU mode is compatible
43	* with VBox.
44	*
45	* @returns VBox status code.
46	* @param pVM The VM to operate on.
47	*/
48	VMMR0DECL(int) CPUMR0Init(PVM pVM)
49	{
50	LogFlow(("CPUMR0Init: %p\n", pVM));
51
52	/*
53	* Check CR0 & CR4 flags.
54	*/
55	uint32_t u32CR0 = ASMGetCR0();
56	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
57	{
58	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
59	return VERR_UNSUPPORTED_CPU_MODE;
60	}
61
62	/*
63	* Check for sysenter if it's used.
64	*/
65	if (ASMHasCpuId())
66	{
67	uint32_t u32CpuVersion;
68	uint32_t u32Dummy;
69	uint32_t u32Features;
70	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &u32Features);
71	uint32_t u32Family = u32CpuVersion >> 8;
72	uint32_t u32Model = (u32CpuVersion >> 4) & 0xF;
73	uint32_t u32Stepping = u32CpuVersion & 0xF;
74
75	/*
76	* Intel docs claim you should test both the flag and family, model & stepping.
77	* Some Pentium Pro cpus have the SEP cpuid flag set, but don't support it.
78	*/
79	if ( (u32Features & X86_CPUID_FEATURE_EDX_SEP)
80	&& !(u32Family == 6 && u32Model < 3 && u32Stepping < 3))
81	{
82	/*
83	* Read the MSR and see if it's in use or not.
84	*/
85	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
86	if (u32)
87	{
88	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSENTER;
89	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
90	}
91	}
92
93	/** @todo check for AMD and syscall!!!!!! */
94	}
95
96
97	/*
98	* Check if debug registers are armed.
99	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
100	*/
101	uint32_t u32DR7 = ASMGetDR7();
102	if (u32DR7 & X86_DR7_ENABLED_MASK)
103	{
104	for (unsigned i=0;i<pVM->cCPUs;i++)
105	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST;
106	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
107	}
108
109	return VINF_SUCCESS;
110	}
111
112
113	/**
114	* Lazily sync in the FPU/XMM state
115	*
116	* @returns VBox status code.
117	* @param pVM VM handle.
118	* @param pVCpu VMCPU handle.
119	* @param pCtx CPU context
120	*/
121	VMMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
122	{
123	Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
124	Assert(ASMGetCR4() & X86_CR4_OSFSXR);
125
126	/* If the FPU state has already been loaded, then it's a guest trap. */
127	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU)
128	{
129	Assert( ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
130	\|\| ((pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS)));
131	return VINF_EM_RAW_GUEST_TRAP;
132	}
133
134	/*
135	* There are two basic actions:
136	* 1. Save host fpu and restore guest fpu.
137	* 2. Generate guest trap.
138	*
139	* When entering the hypervisor we'll always enable MP (for proper wait
140	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
141	* is taken from the guest OS in order to get proper SSE handling.
142	*
143	*
144	* Actions taken depending on the guest CR0 flags:
145	*
146	* 3 2 1
147	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
148	* ------------------------------------------------------------------------
149	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
150	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
151	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
152	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
153	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
154	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
155	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
156	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
157	*/
158
159	switch (pCtx->cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
160	{
161	case X86_CR0_MP \| X86_CR0_TS:
162	case X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS:
163	return VINF_EM_RAW_GUEST_TRAP;
164	default:
165	break;
166	}
167
168	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
169	if (CPUMIsGuestInLongModeEx(pCtx))
170	{
171	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
172
173	/* Save the host state and record the fact (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM). */
174	cpumR0SaveHostFPUState(&pVCpu->cpum.s);
175
176	/* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
177	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_FPU_STATE;
178	}
179	else
180	#endif
181	{
182	#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
183	# if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined(VBOX_WITH_KERNEL_USING_XMM) /** @todo remove the #else here and move cpumHandleLazyFPUAsm back to VMMGC after branching out 3.0!!. */
184	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE));
185	/** @todo Move the FFXR handling down into
186	* cpumR0SaveHostRestoreguestFPUState to optimize the
187	* VBOX_WITH_KERNEL_USING_XMM handling. */
188	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
189	uint64_t SavedEFER = 0;
190	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
191	{
192	SavedEFER = ASMRdMsr(MSR_K6_EFER);
193	if (SavedEFER & MSR_K6_EFER_FFXSR)
194	{
195	ASMWrMsr(MSR_K6_EFER, SavedEFER & ~MSR_K6_EFER_FFXSR);
196	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
197	}
198	}
199
200	/* Do the job and record that we've switched FPU state. */
201	cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
202
203	/* Restore EFER. */
204	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
205	ASMWrMsr(MSR_K6_EFER, SavedEFER);
206
207	# else
208	uint64_t oldMsrEFERHost = 0;
209	uint32_t oldCR0 = ASMGetCR0();
210
211	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
212	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
213	{
214	/** @todo Do we really need to read this every time?? The host could change this on the fly though.
215	* bird: what about starting by skipping the ASMWrMsr below if we didn't
216	* change anything? Ditto for the stuff in CPUMR0SaveGuestFPU. */
217	oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
218	if (oldMsrEFERHost & MSR_K6_EFER_FFXSR)
219	{
220	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
221	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
222	}
223	}
224
225	/* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
226	int rc = CPUMHandleLazyFPU(pVCpu);
227	AssertRC(rc);
228	Assert(CPUMIsGuestFPUStateActive(pVCpu));
229
230	/* Restore EFER MSR */
231	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
232	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost);
233
234	/* CPUMHandleLazyFPU could have changed CR0; restore it. */
235	ASMSetCR0(oldCR0);
236	# endif
237
238	#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
239
240	/*
241	* Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
242	* We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
243	*/
244	pVCpu->cpum.s.Host.fpu.FCW = CPUMGetFCW();
245	if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
246	pVCpu->cpum.s.Host.fpu.MXCSR = CPUMGetMXCSR();
247
248	cpumR0LoadFPU(pCtx);
249
250	/*
251	* The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
252	*
253	* MSR_K6_EFER_FFXSR changes the behaviour of fxsave and fxrstore: the XMM state isn't saved/restored
254	*/
255	if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
256	{
257	/** @todo Do we really need to read this every time?? The host could change this on the fly though. */
258	uint64_t msrEFERHost = ASMRdMsr(MSR_K6_EFER);
259
260	if (msrEFERHost & MSR_K6_EFER_FFXSR)
261	{
262	/* fxrstor doesn't restore the XMM state! */
263	cpumR0LoadXMM(pCtx);
264	pVCpu->cpum.s.fUseFlags \|= CPUM_MANUAL_XMM_RESTORE;
265	}
266	}
267
268	#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
269	}
270
271	Assert((pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM)) == (CPUM_USED_FPU \| CPUM_USED_FPU_SINCE_REM));
272	return VINF_SUCCESS;
273	}
274
275
276	/**
277	* Save guest FPU/XMM state
278	*
279	* @returns VBox status code.
280	* @param pVM VM handle.
281	* @param pVCpu VMCPU handle.
282	* @param pCtx CPU context
283	*/
284	VMMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
285	{
286	Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
287	Assert(ASMGetCR4() & X86_CR4_OSFSXR);
288	AssertReturn((pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU), VINF_SUCCESS);
289
290	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
291	if (CPUMIsGuestInLongModeEx(pCtx))
292	{
293	if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE))
294	{
295	HWACCMR0SaveFPUState(pVM, pVCpu, pCtx);
296	cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
297	}
298	/* else nothing to do; we didn't perform a world switch */
299	}
300	else
301	#endif
302	{
303	#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
304	# ifdef VBOX_WITH_KERNEL_USING_XMM
305	/*
306	* We've already saved the XMM registers in the assembly wrapper, so
307	* we have to save them before saving the entire FPU state and put them
308	* back afterwards.
309	*/
310	/** @todo This could be skipped if MSR_K6_EFER_FFXSR is set, but
311	* I'm not able to test such an optimization tonight.
312	* We could just all this in assembly. */
313	uint128_t aGuestXmmRegs[16];
314	memcpy(&aGuestXmmRegs[0], &pVCpu->cpum.s.Guest.fpu.aXMM[0], sizeof(aGuestXmmRegs));
315	# endif
316
317	/* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
318	uint64_t oldMsrEFERHost = 0;
319	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
320	{
321	oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
322	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
323	}
324	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
325
326	/* Restore EFER MSR */
327	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
328	ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost \| MSR_K6_EFER_FFXSR);
329
330	# ifdef VBOX_WITH_KERNEL_USING_XMM
331	memcpy(&pVCpu->cpum.s.Guest.fpu.aXMM[0], &aGuestXmmRegs[0], sizeof(aGuestXmmRegs));
332	# endif
333
334	#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
335	# ifdef VBOX_WITH_KERNEL_USING_XMM
336	# error "Fix all the NM_TRAPS_IN_KERNEL_MODE code path. I'm not going to fix unused code now."
337	# endif
338	cpumR0SaveFPU(pCtx);
339	if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
340	{
341	/* fxsave doesn't save the XMM state! */
342	cpumR0SaveXMM(pCtx);
343	}
344
345	/*
346	* Restore the original FPU control word and MXCSR.
347	* We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
348	*/
349	cpumR0SetFCW(pVCpu->cpum.s.Host.fpu.FCW);
350	if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
351	cpumR0SetMXCSR(pVCpu->cpum.s.Host.fpu.MXCSR);
352	#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
353	}
354
355	pVCpu->cpum.s.fUseFlags &= ~(CPUM_USED_FPU \| CPUM_SYNC_FPU_STATE \| CPUM_MANUAL_XMM_RESTORE);
356	return VINF_SUCCESS;
357	}
358
359
360	/**
361	* Save guest debug state
362	*
363	* @returns VBox status code.
364	* @param pVM VM handle.
365	* @param pVCpu VMCPU handle.
366	* @param pCtx CPU context
367	* @param fDR6 Include DR6 or not
368	*/
369	VMMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
370	{
371	Assert(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS);
372
373	/* Save the guest's debug state. The caller is responsible for DR7. */
374	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
375	if (CPUMIsGuestInLongModeEx(pCtx))
376	{
377	if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_DEBUG_STATE))
378	{
379	uint64_t dr6 = pCtx->dr[6];
380
381	HWACCMR0SaveDebugState(pVM, pVCpu, pCtx);
382	if (!fDR6) /* dr6 was already up-to-date */
383	pCtx->dr[6] = dr6;
384	}
385	}
386	else
387	#endif
388	{
389	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
390	cpumR0SaveDRx(&pCtx->dr[0]);
391	#else
392	pCtx->dr[0] = ASMGetDR0();
393	pCtx->dr[1] = ASMGetDR1();
394	pCtx->dr[2] = ASMGetDR2();
395	pCtx->dr[3] = ASMGetDR3();
396	#endif
397	if (fDR6)
398	pCtx->dr[6] = ASMGetDR6();
399	}
400
401	/*
402	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
403	* DR7 contains 0x400 right now.
404	*/
405	CPUMR0LoadHostDebugState(pVM, pVCpu);
406	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS));
407	return VINF_SUCCESS;
408	}
409
410
411	/**
412	* Lazily sync in the debug state
413	*
414	* @returns VBox status code.
415	* @param pVM VM handle.
416	* @param pVCpu VMCPU handle.
417	* @param pCtx CPU context
418	* @param fDR6 Include DR6 or not
419	*/
420	VMMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
421	{
422	/* Save the host state. */
423	CPUMR0SaveHostDebugState(pVM, pVCpu);
424	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
425
426	/* Activate the guest state DR0-3; DR7 is left to the caller. */
427	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
428	if (CPUMIsGuestInLongModeEx(pCtx))
429	{
430	/* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
431	pVCpu->cpum.s.fUseFlags \|= CPUM_SYNC_DEBUG_STATE;
432	}
433	else
434	#endif
435	{
436	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
437	cpumR0LoadDRx(&pCtx->dr[0]);
438	#else
439	ASMSetDR0(pCtx->dr[0]);
440	ASMSetDR1(pCtx->dr[1]);
441	ASMSetDR2(pCtx->dr[2]);
442	ASMSetDR3(pCtx->dr[3]);
443	#endif
444	if (fDR6)
445	ASMSetDR6(pCtx->dr[6]);
446	}
447
448	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS;
449	return VINF_SUCCESS;
450	}
451
452	/**
453	* Save the host debug state
454	*
455	* @returns VBox status code.
456	* @param pVM VM handle.
457	* @param pVCpu VMCPU handle.
458	*/
459	VMMR0DECL(int) CPUMR0SaveHostDebugState(PVM pVM, PVMCPU pVCpu)
460	{
461	/* Save the host state. */
462	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
463	AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
464	cpumR0SaveDRx(&pVCpu->cpum.s.Host.dr0);
465	#else
466	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
467	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
468	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
469	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
470	#endif
471	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
472	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
473	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
474	/* Make sure DR7 is harmless or else we could trigger breakpoints when restoring dr0-3 (!) */
475	ASMSetDR7(X86_DR7_INIT_VAL);
476
477	return VINF_SUCCESS;
478	}
479
480	/**
481	* Load the host debug state
482	*
483	* @returns VBox status code.
484	* @param pVM VM handle.
485	* @param pVCpu VMCPU handle.
486	*/
487	VMMR0DECL(int) CPUMR0LoadHostDebugState(PVM pVM, PVMCPU pVCpu)
488	{
489	Assert(pVCpu->cpum.s.fUseFlags & (CPUM_USE_DEBUG_REGS \| CPUM_USE_DEBUG_REGS_HYPER));
490
491	/*
492	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
493	* DR7 contains 0x400 right now.
494	*/
495	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
496	AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
497	cpumR0LoadDRx(&pVCpu->cpum.s.Host.dr0);
498	#else
499	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
500	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
501	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
502	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
503	#endif
504	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
505	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
506
507	pVCpu->cpum.s.fUseFlags &= ~(CPUM_USE_DEBUG_REGS \| CPUM_USE_DEBUG_REGS_HYPER);
508	return VINF_SUCCESS;
509	}
510
511
512	/**
513	* Lazily sync in the hypervisor debug state
514	*
515	* @returns VBox status code.
516	* @param pVM VM handle.
517	* @param pVCpu VMCPU handle.
518	* @param pCtx CPU context
519	* @param fDR6 Include DR6 or not
520	*/
521	VMMR0DECL(int) CPUMR0LoadHyperDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
522	{
523	/* Save the host state. */
524	CPUMR0SaveHostDebugState(pVM, pVCpu);
525	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
526
527	/* Activate the guest state DR0-3; DR7 is left to the caller. */
528	#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
529	if (CPUMIsGuestInLongModeEx(pCtx))
530	{
531	AssertFailed();
532	return VERR_NOT_IMPLEMENTED;
533	}
534	else
535	#endif
536	{
537	#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
538	AssertFailed();
539	return VERR_NOT_IMPLEMENTED;
540	#else
541	ASMSetDR0(CPUMGetHyperDR0(pVCpu));
542	ASMSetDR1(CPUMGetHyperDR1(pVCpu));
543	ASMSetDR2(CPUMGetHyperDR2(pVCpu));
544	ASMSetDR3(CPUMGetHyperDR3(pVCpu));
545	#endif
546	if (fDR6)
547	ASMSetDR6(CPUMGetHyperDR6(pVCpu));
548	}
549
550	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HYPER;
551	return VINF_SUCCESS;
552	}
553
554

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source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 21937

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