1 | /* $Id: CPUMR0.cpp 12227 2008-09-08 13:24:05Z vboxsync $ */
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2 | /** @file
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3 | * CPUM - Host Context Ring 0.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2007 Sun Microsystems, Inc.
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | *
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17 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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18 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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19 | * additional information or have any questions.
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20 | */
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21 |
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22 |
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23 | /*******************************************************************************
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24 | * Header Files *
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25 | *******************************************************************************/
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26 | #define LOG_GROUP LOG_GROUP_CPUM
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27 | #include <VBox/cpum.h>
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28 | #include "CPUMInternal.h"
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29 | #include <VBox/vm.h>
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30 | #include <VBox/x86.h>
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31 | #include <VBox/err.h>
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32 | #include <VBox/log.h>
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33 | #include <iprt/assert.h>
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34 | #include <iprt/asm.h>
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35 |
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36 |
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37 |
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38 |
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39 | /**
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40 | * Does Ring-0 CPUM initialization.
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41 | *
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42 | * This is mainly to check that the Host CPU mode is compatible
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43 | * with VBox.
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44 | *
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45 | * @returns VBox status code.
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46 | * @param pVM The VM to operate on.
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47 | */
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48 | CPUMR0DECL(int) CPUMR0Init(PVM pVM)
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49 | {
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50 | LogFlow(("CPUMR0Init: %p\n", pVM));
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51 |
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52 | /*
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53 | * Check CR0 & CR4 flags.
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54 | */
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55 | uint32_t u32CR0 = ASMGetCR0();
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56 | if ((u32CR0 & (X86_CR0_PE | X86_CR0_PG)) != (X86_CR0_PE | X86_CR0_PG)) /* a bit paranoid perhaps.. */
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57 | {
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58 | Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
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59 | return VERR_UNSUPPORTED_CPU_MODE;
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60 | }
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61 |
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62 | /*
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63 | * Check for sysenter if it's used.
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64 | */
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65 | if (ASMHasCpuId())
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66 | {
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67 | uint32_t u32CpuVersion;
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68 | uint32_t u32Dummy;
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69 | uint32_t u32Features;
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70 | ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &u32Features);
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71 | uint32_t u32Family = u32CpuVersion >> 8;
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72 | uint32_t u32Model = (u32CpuVersion >> 4) & 0xF;
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73 | uint32_t u32Stepping = u32CpuVersion & 0xF;
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74 |
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75 | /*
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76 | * Intel docs claim you should test both the flag and family, model & stepping.
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77 | * Some Pentium Pro cpus have the SEP cpuid flag set, but don't support it.
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78 | */
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79 | if ( (u32Features & X86_CPUID_FEATURE_EDX_SEP)
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80 | && !(u32Family == 6 && u32Model < 3 && u32Stepping < 3))
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81 | {
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82 | /*
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83 | * Read the MSR and see if it's in use or not.
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84 | */
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85 | uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
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86 | if (u32)
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87 | {
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88 | pVM->cpum.s.fUseFlags |= CPUM_USE_SYSENTER;
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89 | Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
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90 | }
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91 | }
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92 |
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93 | /** @todo check for AMD and syscall!!!!!! */
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94 | }
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95 |
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96 |
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97 | /*
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98 | * Check if debug registers are armed.
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99 | * This ASSUMES that DR7.GD is not set, or that it's handled transparently!
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100 | */
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101 | uint32_t u32DR7 = ASMGetDR7();
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102 | if (u32DR7 & X86_DR7_ENABLED_MASK)
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103 | {
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104 | pVM->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HOST;
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105 | Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
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106 | }
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107 |
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108 | return VINF_SUCCESS;
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109 | }
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110 |
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111 |
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112 | /**
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113 | * Lazily sync in the FPU/XMM state
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114 | *
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115 | * @returns VBox status code.
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116 | * @param pVM VM handle.
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117 | * @param pCtx CPU context
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118 | */
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119 | CPUMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PCPUMCTX pCtx)
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120 | {
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121 | Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
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122 | Assert(ASMGetCR4() & X86_CR4_OSFSXR);
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123 |
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124 | /* If the FPU state has already been loaded, then it's a guest trap. */
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125 | if (pVM->cpum.s.fUseFlags & CPUM_USED_FPU)
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126 | {
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127 | Assert( ((pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
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128 | || ((pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)));
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129 | return VINF_EM_RAW_GUEST_TRAP;
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130 | }
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131 |
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132 | /*
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133 | * There are two basic actions:
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134 | * 1. Save host fpu and restore guest fpu.
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135 | * 2. Generate guest trap.
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136 | *
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137 | * When entering the hypervisor we'll always enable MP (for proper wait
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138 | * trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
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139 | * is taken from the guest OS in order to get proper SSE handling.
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140 | *
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141 | *
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142 | * Actions taken depending on the guest CR0 flags:
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143 | *
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144 | * 3 2 1
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145 | * TS | EM | MP | FPUInstr | WAIT :: VMM Action
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146 | * ------------------------------------------------------------------------
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147 | * 0 | 0 | 0 | Exec | Exec :: Clear TS & MP, Save HC, Load GC.
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148 | * 0 | 0 | 1 | Exec | Exec :: Clear TS, Save HC, Load GC.
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149 | * 0 | 1 | 0 | #NM | Exec :: Clear TS & MP, Save HC, Load GC.
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150 | * 0 | 1 | 1 | #NM | Exec :: Clear TS, Save HC, Load GC.
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151 | * 1 | 0 | 0 | #NM | Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
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152 | * 1 | 0 | 1 | #NM | #NM :: Go to guest taking trap there.
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153 | * 1 | 1 | 0 | #NM | Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
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154 | * 1 | 1 | 1 | #NM | #NM :: Go to guest taking trap there.
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155 | */
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156 |
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157 | switch(pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
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158 | {
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159 | case X86_CR0_MP | X86_CR0_TS:
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160 | case X86_CR0_MP | X86_CR0_EM | X86_CR0_TS:
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161 | return VINF_EM_RAW_GUEST_TRAP;
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162 |
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163 | default:
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164 | break;
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165 | }
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166 |
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167 | #ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
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168 | uint64_t oldMsrEFERHost;
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169 | uint32_t oldCR0 = ASMGetCR0();
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170 |
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171 | /* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
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172 | if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
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173 | {
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174 | /* @todo Do we really need to read this every time?? The host could change this on the fly though. */
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175 | oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
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176 |
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177 | if (oldMsrEFERHost & MSR_K6_EFER_FFXSR)
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178 | {
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179 | ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
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180 | pVM->cpum.s.fUseFlags |= CPUM_MANUAL_XMM_RESTORE;
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181 | }
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182 | }
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183 |
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184 | /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
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185 | int rc = CPUMHandleLazyFPU(pVM);
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186 | AssertRC(rc);
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187 | Assert(CPUMIsGuestFPUStateActive(pVM));
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188 |
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189 | /* Restore EFER MSR */
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190 | if (pVM->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
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191 | ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost);
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192 |
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193 | /* CPUMHandleLazyFPU could have changed CR0; restore it. */
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194 | ASMSetCR0(oldCR0);
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195 | #else
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196 | /* Save the FPU control word and MXCSR, so we can restore the properly afterwards.
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197 | * We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
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198 | */
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199 | pVM->cpum.s.Host.fpu.FCW = CPUMGetFCW();
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200 | if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
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201 | pVM->cpum.s.Host.fpu.MXCSR = CPUMGetMXCSR();
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202 |
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203 | CPUMLoadFPUAsm(pCtx);
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204 |
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205 | /* The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
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206 | *
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207 | * MSR_K6_EFER_FFXSR changes the behaviour of fxsave and fxrstore: the XMM state isn't saved/restored
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208 | */
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209 | if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
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210 | {
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211 | /* @todo Do we really need to read this every time?? The host could change this on the fly though. */
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212 | uint64_t msrEFERHost = ASMRdMsr(MSR_K6_EFER);
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213 |
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214 | if (msrEFERHost & MSR_K6_EFER_FFXSR)
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215 | {
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216 | /* fxrstor doesn't restore the XMM state! */
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217 | CPUMLoadXMMAsm(pCtx);
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218 | pVM->cpum.s.fUseFlags |= CPUM_MANUAL_XMM_RESTORE;
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219 | }
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220 | }
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221 | #endif
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222 |
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223 | pVM->cpum.s.fUseFlags |= CPUM_USED_FPU;
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224 | return VINF_SUCCESS;
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225 | }
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226 |
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227 |
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228 | /**
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229 | * Save guest FPU/XMM state
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230 | *
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231 | * @returns VBox status code.
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232 | * @param pVM VM handle.
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233 | * @param pCtx CPU context
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234 | */
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235 | CPUMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PCPUMCTX pCtx)
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236 | {
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237 | Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
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238 | Assert(ASMGetCR4() & X86_CR4_OSFSXR);
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239 | AssertReturn((pVM->cpum.s.fUseFlags & CPUM_USED_FPU), VINF_SUCCESS);
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240 |
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241 | #ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
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242 | uint64_t oldMsrEFERHost;
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243 |
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244 | /* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
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245 | if (pVM->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
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246 | {
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247 | oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
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248 | ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
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249 | }
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250 | CPUMRestoreHostFPUState(pVM);
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251 |
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252 | /* Restore EFER MSR */
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253 | if (pVM->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
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254 | ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost | MSR_K6_EFER_FFXSR);
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255 |
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256 | #else
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257 | CPUMSaveFPUAsm(pCtx);
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258 | if (pVM->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
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259 | {
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260 | /* fxsave doesn't save the XMM state! */
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261 | CPUMSaveXMMAsm(pCtx);
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262 | }
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263 | /* Restore the original FPU control word and MXCSR.
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264 | * We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
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265 | */
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266 | CPUMSetFCW(pVM->cpum.s.Host.fpu.FCW);
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267 | if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
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268 | CPUMSetMXCSR(pVM->cpum.s.Host.fpu.MXCSR);
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269 | #endif
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270 |
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271 | pVM->cpum.s.fUseFlags &= ~(CPUM_USED_FPU|CPUM_MANUAL_XMM_RESTORE);
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272 | return VINF_SUCCESS;
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273 | }
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