CPUMR0.cpp@ 95140

Last change on this file since 95140 was 95134, checked in by vboxsync, 3 years ago
VMM,SUPDrv: Pass proper fCtxHook value to SUPR0FpuBegin/End so it can be used for assertions on linux. Wrote a more detailed explanation for the preemption hack in the linux SUPR0FpuBegin code and propped it up with an Assert(). bugref:10209
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1	/* $Id: CPUMR0.cpp 95134 2022-05-27 14:50:17Z vboxsync $ */
2	/** @file
3	* CPUM - Host Context Ring 0.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#define CPUM_WITH_NONCONST_HOST_FEATURES
24	#include <VBox/vmm/cpum.h>
25	#include <VBox/vmm/hm.h>
26	#include "CPUMInternal.h"
27	#include <VBox/vmm/vmcc.h>
28	#include <VBox/vmm/gvm.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <VBox/vmm/hm.h>
32	#include <iprt/assert.h>
33	#include <iprt/asm-amd64-x86.h>
34	#include <iprt/mem.h>
35	#include <iprt/x86.h>
36
37
38	/*********************************************************************************************************************************
39	* Global Variables *
40	*********************************************************************************************************************************/
41	/** Host CPU features. */
42	DECL_HIDDEN_DATA(CPUHOSTFEATURES) g_CpumHostFeatures;
43	/** Static storage for host MSRs. */
44	static CPUMMSRS g_CpumHostMsrs;
45
46	/**
47	* CPUID bits to unify among all cores.
48	*/
49	static struct
50	{
51	uint32_t uLeaf; /*< Leaf to check. /
52	uint32_t uEcx; /*< which bits in ecx to unify between CPUs. /
53	uint32_t uEdx; /*< which bits in edx to unify between CPUs. /
54	}
55	const g_aCpuidUnifyBits[] =
56	{
57	{
58	0x00000001,
59	X86_CPUID_FEATURE_ECX_CX16 \| X86_CPUID_FEATURE_ECX_MONITOR,
60	X86_CPUID_FEATURE_EDX_CX8
61	}
62	};
63
64
65
66	/*********************************************************************************************************************************
67	* Internal Functions *
68	*********************************************************************************************************************************/
69	static int cpumR0SaveHostDebugState(PVMCPUCC pVCpu);
70
71
72	/**
73	* Check the CPUID features of this particular CPU and disable relevant features
74	* for the guest which do not exist on this CPU.
75	*
76	* We have seen systems where the X86_CPUID_FEATURE_ECX_MONITOR feature flag is
77	* only set on some host CPUs, see @bugref{5436}.
78	*
79	* @note This function might be called simultaneously on more than one CPU!
80	*
81	* @param idCpu The identifier for the CPU the function is called on.
82	* @param pvUser1 Leaf array.
83	* @param pvUser2 Number of leaves.
84	*/
85	static DECLCALLBACK(void) cpumR0CheckCpuid(RTCPUID idCpu, void pvUser1, void pvUser2)
86	{
87	PCPUMCPUIDLEAF const paLeaves = (PCPUMCPUIDLEAF)pvUser1;
88	uint32_t const cLeaves = (uint32_t)(uintptr_t)pvUser2;
89	RT_NOREF(idCpu);
90
91	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
92	{
93	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, g_aCpuidUnifyBits[i].uLeaf, 0);
94	if (pLeaf)
95	{
96	uint32_t uEax, uEbx, uEcx, uEdx;
97	ASMCpuIdExSlow(g_aCpuidUnifyBits[i].uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
98
99	ASMAtomicAndU32(&pLeaf->uEcx, uEcx \| ~g_aCpuidUnifyBits[i].uEcx);
100	ASMAtomicAndU32(&pLeaf->uEdx, uEdx \| ~g_aCpuidUnifyBits[i].uEdx);
101	}
102	}
103	}
104
105
106	/**
107	* Does the Ring-0 CPU initialization once during module load.
108	* XXX Host-CPU hot-plugging?
109	*/
110	VMMR0_INT_DECL(int) CPUMR0ModuleInit(void)
111	{
112	/*
113	* Query the hardware virtualization capabilities of the host CPU first.
114	*/
115	uint32_t fHwCaps = 0;
116	int rc = SUPR0GetVTSupport(&fHwCaps);
117	AssertLogRelMsg(RT_SUCCESS(rc) \|\| rc == VERR_UNSUPPORTED_CPU \|\| rc == VERR_SVM_NO_SVM \|\| rc == VERR_VMX_NO_VMX,
118	("SUPR0GetHwvirtMsrs -> %Rrc\n", rc));
119	if (RT_SUCCESS(rc))
120	{
121	SUPHWVIRTMSRS HwvirtMsrs;
122	rc = SUPR0GetHwvirtMsrs(&HwvirtMsrs, fHwCaps, false /fIgnored/);
123	AssertLogRelRC(rc);
124	if (RT_SUCCESS(rc))
125	{
126	if (fHwCaps & SUPVTCAPS_VT_X)
127	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &g_CpumHostMsrs.hwvirt.vmx);
128	else
129	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &g_CpumHostMsrs.hwvirt.svm);
130	}
131	}
132
133	/*
134	* Collect CPUID leaves.
135	*/
136	PCPUMCPUIDLEAF paLeaves;
137	uint32_t cLeaves;
138	rc = CPUMCpuIdCollectLeavesX86(&paLeaves, &cLeaves);
139	AssertLogRelRCReturn(rc, rc);
140
141	/*
142	* Unify/cross check some CPUID feature bits on all available CPU cores
143	* and threads. We've seen CPUs where the monitor support differed.
144	*/
145	RTMpOnAll(cpumR0CheckCpuid, paLeaves, (void *)(uintptr_t)cLeaves);
146
147	/*
148	* Populate the host CPU feature global variable.
149	*/
150	rc = cpumCpuIdExplodeFeaturesX86(paLeaves, cLeaves, &g_CpumHostMsrs, &g_CpumHostFeatures.s);
151	RTMemFree(paLeaves);
152	AssertLogRelRCReturn(rc, rc);
153
154	/*
155	* Get MSR_IA32_ARCH_CAPABILITIES and expand it into the host feature structure.
156	*/
157	if (ASMHasCpuId())
158	{
159	/** @todo Should add this MSR to CPUMMSRS and expose it via SUPDrv... */
160	g_CpumHostFeatures.s.fArchRdclNo = 0;
161	g_CpumHostFeatures.s.fArchIbrsAll = 0;
162	g_CpumHostFeatures.s.fArchRsbOverride = 0;
163	g_CpumHostFeatures.s.fArchVmmNeedNotFlushL1d = 0;
164	g_CpumHostFeatures.s.fArchMdsNo = 0;
165	uint32_t const cStdRange = ASMCpuId_EAX(0);
166	if ( RTX86IsValidStdRange(cStdRange)
167	&& cStdRange >= 7)
168	{
169	uint32_t const fStdFeaturesEdx = ASMCpuId_EDX(1);
170	uint32_t fStdExtFeaturesEdx;
171	ASMCpuIdExSlow(7, 0, 0, 0, NULL, NULL, NULL, &fStdExtFeaturesEdx);
172	if ( (fStdExtFeaturesEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
173	&& (fStdFeaturesEdx & X86_CPUID_FEATURE_EDX_MSR))
174	{
175	uint64_t fArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
176	g_CpumHostFeatures.s.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
177	g_CpumHostFeatures.s.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
178	g_CpumHostFeatures.s.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
179	g_CpumHostFeatures.s.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
180	g_CpumHostFeatures.s.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
181	}
182	else
183	g_CpumHostFeatures.s.fArchCap = 0;
184	}
185	}
186
187	return VINF_SUCCESS;
188	}
189
190
191	/**
192	* Terminate the module.
193	*/
194	VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void)
195	{
196	return VINF_SUCCESS;
197	}
198
199
200	/**
201	* Initializes the CPUM data in the VM structure.
202	*
203	* @param pGVM The global VM structure.
204	*/
205	VMMR0_INT_DECL(void) CPUMR0InitPerVMData(PGVM pGVM)
206	{
207	/* Copy the ring-0 host feature set to the shared part so ring-3 can pick it up. */
208	pGVM->cpum.s.HostFeatures = g_CpumHostFeatures.s;
209	}
210
211
212	/**
213	* Check the CPUID features of this particular CPU and disable relevant features
214	* for the guest which do not exist on this CPU. We have seen systems where the
215	* X86_CPUID_FEATURE_ECX_MONITOR feature flag is only set on some host CPUs, see
216	* @bugref{5436}.
217	*
218	* @note This function might be called simultaneously on more than one CPU!
219	*
220	* @param idCpu The identifier for the CPU the function is called on.
221	* @param pvUser1 Pointer to the VM structure.
222	* @param pvUser2 Ignored.
223	*/
224	static DECLCALLBACK(void) cpumR0CheckCpuidLegacy(RTCPUID idCpu, void pvUser1, void pvUser2)
225	{
226	PVMCC pVM = (PVMCC)pvUser1;
227
228	NOREF(idCpu); NOREF(pvUser2);
229	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
230	{
231	/* Note! Cannot use cpumCpuIdGetLeaf from here because we're not
232	necessarily in the VM process context. So, we using the
233	legacy arrays as temporary storage. */
234
235	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
236	PCPUMCPUID pLegacyLeaf;
237	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
238	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
239	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
240	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
241	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
242	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
243	else
244	continue;
245
246	uint32_t eax, ebx, ecx, edx;
247	ASMCpuIdExSlow(uLeaf, 0, 0, 0, &eax, &ebx, &ecx, &edx);
248
249	ASMAtomicAndU32(&pLegacyLeaf->uEcx, ecx \| ~g_aCpuidUnifyBits[i].uEcx);
250	ASMAtomicAndU32(&pLegacyLeaf->uEdx, edx \| ~g_aCpuidUnifyBits[i].uEdx);
251	}
252	}
253
254
255	/**
256	* Does Ring-0 CPUM initialization.
257	*
258	* This is mainly to check that the Host CPU mode is compatible
259	* with VBox.
260	*
261	* @returns VBox status code.
262	* @param pVM The cross context VM structure.
263	*/
264	VMMR0_INT_DECL(int) CPUMR0InitVM(PVMCC pVM)
265	{
266	LogFlow(("CPUMR0Init: %p\n", pVM));
267	AssertCompile(sizeof(pVM->aCpus[0].cpum.s.Host.abXState) >= sizeof(pVM->aCpus[0].cpum.s.Guest.abXState));
268
269	/*
270	* Check CR0 & CR4 flags.
271	*/
272	uint32_t u32CR0 = ASMGetCR0();
273	if ((u32CR0 & (X86_CR0_PE \| X86_CR0_PG)) != (X86_CR0_PE \| X86_CR0_PG)) /* a bit paranoid perhaps.. */
274	{
275	Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
276	return VERR_UNSUPPORTED_CPU_MODE;
277	}
278
279	/*
280	* Check for sysenter and syscall usage.
281	*/
282	if (ASMHasCpuId())
283	{
284	/*
285	* SYSENTER/SYSEXIT
286	*
287	* Intel docs claim you should test both the flag and family, model &
288	* stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
289	* but don't support it. AMD CPUs may support this feature in legacy
290	* mode, they've banned it from long mode. Since we switch to 32-bit
291	* mode when entering raw-mode context the feature would become
292	* accessible again on AMD CPUs, so we have to check regardless of
293	* host bitness.
294	*/
295	uint32_t u32CpuVersion;
296	uint32_t u32Dummy;
297	uint32_t fFeatures; /* (Used further down to check for MSRs, so don't clobber.) */
298	ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
299	uint32_t const u32Family = u32CpuVersion >> 8;
300	uint32_t const u32Model = (u32CpuVersion >> 4) & 0xF;
301	uint32_t const u32Stepping = u32CpuVersion & 0xF;
302	if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
303	&& ( u32Family != 6 /* (> pentium pro) */
304	\|\| u32Model >= 3
305	\|\| u32Stepping >= 3
306	\|\| !ASMIsIntelCpu())
307	)
308	{
309	/*
310	* Read the MSR and see if it's in use or not.
311	*/
312	uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
313	if (u32)
314	{
315	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSENTER;
316	Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
317	}
318	}
319
320	/*
321	* SYSCALL/SYSRET
322	*
323	* This feature is indicated by the SEP bit returned in EDX by CPUID
324	* function 0x80000001. Intel CPUs only supports this feature in
325	* long mode. Since we're not running 64-bit guests in raw-mode there
326	* are no issues with 32-bit intel hosts.
327	*/
328	uint32_t cExt = 0;
329	ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
330	if (RTX86IsValidExtRange(cExt))
331	{
332	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
333	if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
334	{
335	#ifdef RT_ARCH_X86
336	if (!ASMIsIntelCpu())
337	#endif
338	{
339	uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
340	if (fEfer & MSR_K6_EFER_SCE)
341	{
342	pVM->cpum.s.fHostUseFlags \|= CPUM_USE_SYSCALL;
343	Log(("CPUMR0Init: host uses syscall\n"));
344	}
345	}
346	}
347	}
348
349	/*
350	* Copy MSR_IA32_ARCH_CAPABILITIES bits over into the host and guest feature
351	* structure and as well as the guest MSR.
352	* Note! we assume this happens after the CPUMR3Init is done, so CPUID bits are settled.
353	*/
354	pVM->cpum.s.HostFeatures.fArchRdclNo = 0;
355	pVM->cpum.s.HostFeatures.fArchIbrsAll = 0;
356	pVM->cpum.s.HostFeatures.fArchRsbOverride = 0;
357	pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = 0;
358	pVM->cpum.s.HostFeatures.fArchMdsNo = 0;
359	uint32_t const cStdRange = ASMCpuId_EAX(0);
360	if ( RTX86IsValidStdRange(cStdRange)
361	&& cStdRange >= 7)
362	{
363	uint32_t fEdxFeatures = ASMCpuId_EDX(7);
364	if ( (fEdxFeatures & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
365	&& (fFeatures & X86_CPUID_FEATURE_EDX_MSR))
366	{
367	/* Host: */
368	uint64_t fArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
369	pVM->cpum.s.HostFeatures.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
370	pVM->cpum.s.HostFeatures.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
371	pVM->cpum.s.HostFeatures.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
372	pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
373	pVM->cpum.s.HostFeatures.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
374
375	/* guest: */
376	if (!pVM->cpum.s.GuestFeatures.fArchCap)
377	fArchVal = 0;
378	else if (!pVM->cpum.s.GuestFeatures.fIbrs)
379	fArchVal &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL;
380	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps = fArchVal);
381	pVM->cpum.s.GuestFeatures.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
382	pVM->cpum.s.GuestFeatures.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
383	pVM->cpum.s.GuestFeatures.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
384	pVM->cpum.s.GuestFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
385	pVM->cpum.s.GuestFeatures.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
386	}
387	else
388	pVM->cpum.s.HostFeatures.fArchCap = 0;
389	}
390
391	/*
392	* Unify/cross check some CPUID feature bits on all available CPU cores
393	* and threads. We've seen CPUs where the monitor support differed.
394	*
395	* Because the hyper heap isn't always mapped into ring-0, we cannot
396	* access it from a RTMpOnAll callback. We use the legacy CPUID arrays
397	* as temp ring-0 accessible memory instead, ASSUMING that they're all
398	* up to date when we get here.
399	*/
400	RTMpOnAll(cpumR0CheckCpuidLegacy, pVM, NULL);
401
402	for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
403	{
404	bool fIgnored;
405	uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
406	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, 0, &fIgnored);
407	if (pLeaf)
408	{
409	PCPUMCPUID pLegacyLeaf;
410	if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
411	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
412	else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
413	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
414	else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
415	pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
416	else
417	continue;
418
419	pLeaf->uEcx = pLegacyLeaf->uEcx;
420	pLeaf->uEdx = pLegacyLeaf->uEdx;
421	}
422	}
423
424	}
425
426
427	/*
428	* Check if debug registers are armed.
429	* This ASSUMES that DR7.GD is not set, or that it's handled transparently!
430	*/
431	uint32_t u32DR7 = ASMGetDR7();
432	if (u32DR7 & X86_DR7_ENABLED_MASK)
433	{
434	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.fUseFlags \|= CPUM_USE_DEBUG_REGS_HOST);
435	Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
436	}
437
438	return VINF_SUCCESS;
439	}
440
441
442	/**
443	* Trap handler for device-not-available fault (\#NM).
444	* Device not available, FP or (F)WAIT instruction.
445	*
446	* @returns VBox status code.
447	* @retval VINF_SUCCESS if the guest FPU state is loaded.
448	* @retval VINF_EM_RAW_GUEST_TRAP if it is a guest trap.
449	* @retval VINF_CPUM_HOST_CR0_MODIFIED if we modified the host CR0.
450	*
451	* @param pVM The cross context VM structure.
452	* @param pVCpu The cross context virtual CPU structure.
453	*/
454	VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVMCC pVM, PVMCPUCC pVCpu)
455	{
456	Assert(pVM->cpum.s.HostFeatures.fFxSaveRstor);
457	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
458
459	/* If the FPU state has already been loaded, then it's a guest trap. */
460	if (CPUMIsGuestFPUStateActive(pVCpu))
461	{
462	Assert( ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS))
463	\|\| ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS)) == (X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM)));
464	return VINF_EM_RAW_GUEST_TRAP;
465	}
466
467	/*
468	* There are two basic actions:
469	* 1. Save host fpu and restore guest fpu.
470	* 2. Generate guest trap.
471	*
472	* When entering the hypervisor we'll always enable MP (for proper wait
473	* trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
474	* is taken from the guest OS in order to get proper SSE handling.
475	*
476	*
477	* Actions taken depending on the guest CR0 flags:
478	*
479	* 3 2 1
480	* TS \| EM \| MP \| FPUInstr \| WAIT :: VMM Action
481	* ------------------------------------------------------------------------
482	* 0 \| 0 \| 0 \| Exec \| Exec :: Clear TS & MP, Save HC, Load GC.
483	* 0 \| 0 \| 1 \| Exec \| Exec :: Clear TS, Save HC, Load GC.
484	* 0 \| 1 \| 0 \| #NM \| Exec :: Clear TS & MP, Save HC, Load GC.
485	* 0 \| 1 \| 1 \| #NM \| Exec :: Clear TS, Save HC, Load GC.
486	* 1 \| 0 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
487	* 1 \| 0 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
488	* 1 \| 1 \| 0 \| #NM \| Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
489	* 1 \| 1 \| 1 \| #NM \| #NM :: Go to guest taking trap there.
490	*/
491
492	switch (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP \| X86_CR0_EM \| X86_CR0_TS))
493	{
494	case X86_CR0_MP \| X86_CR0_TS:
495	case X86_CR0_MP \| X86_CR0_TS \| X86_CR0_EM:
496	return VINF_EM_RAW_GUEST_TRAP;
497	default:
498	break;
499	}
500
501	return CPUMR0LoadGuestFPU(pVM, pVCpu);
502	}
503
504
505	/**
506	* Saves the host-FPU/XMM state (if necessary) and (always) loads the guest-FPU
507	* state into the CPU.
508	*
509	* @returns VINF_SUCCESS on success, host CR0 unmodified.
510	* @returns VINF_CPUM_HOST_CR0_MODIFIED on success when the host CR0 was
511	* modified and VT-x needs to update the value in the VMCS.
512	*
513	* @param pVM The cross context VM structure.
514	* @param pVCpu The cross context virtual CPU structure.
515	*/
516	VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVMCC pVM, PVMCPUCC pVCpu)
517	{
518	int rc;
519	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
520	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST));
521
522	/* Notify the support driver prior to loading the guest-FPU register state. */
523	SUPR0FpuBegin(VMMR0ThreadCtxHookIsEnabled(pVCpu));
524	/** @todo use return value? Currently skipping that to be on the safe side
525	* wrt. extended state (linux). */
526
527	if (!pVM->cpum.s.HostFeatures.fLeakyFxSR)
528	{
529	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
530	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
531	}
532	else
533	{
534	Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE) \|\| (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST));
535	/** @todo r=ramshankar: Can't we used a cached value here
536	* instead of reading the MSR? host EFER doesn't usually
537	* change. */
538	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
539	if (!(uHostEfer & MSR_K6_EFER_FFXSR))
540	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
541	else
542	{
543	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
544	pVCpu->cpum.s.fUseFlags \|= CPUM_USED_MANUAL_XMM_RESTORE;
545	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
546	rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
547	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
548	ASMSetFlags(uSavedFlags);
549	}
550	}
551	Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM))
552	== (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_FPU_SINCE_REM));
553	Assert(pVCpu->cpum.s.Guest.fUsedFpuGuest);
554	return rc;
555	}
556
557
558	/**
559	* Saves the guest FPU/XMM state if needed, restores the host FPU/XMM state as
560	* needed.
561	*
562	* @returns true if we saved the guest state.
563	* @param pVCpu The cross context virtual CPU structure.
564	*/
565	VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu)
566	{
567	bool fSavedGuest;
568	Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.HostFeatures.fFxSaveRstor);
569	Assert(ASMGetCR4() & X86_CR4_OSFXSR);
570	if (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST))
571	{
572	fSavedGuest = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
573	Assert(fSavedGuest == pVCpu->cpum.s.Guest.fUsedFpuGuest);
574	if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE))
575	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
576	else
577	{
578	/* Temporarily clear MSR_K6_EFER_FFXSR or else we'll be unable to
579	save/restore the XMM state with fxsave/fxrstor. */
580	uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
581	if (uHostEfer & MSR_K6_EFER_FFXSR)
582	{
583	RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
584	ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
585	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
586	ASMWrMsr(MSR_K6_EFER, uHostEfer \| MSR_K6_EFER_FFXSR);
587	ASMSetFlags(uSavedFlags);
588	}
589	else
590	cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
591	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_MANUAL_XMM_RESTORE;
592	}
593
594	/* Notify the support driver after loading the host-FPU register state. */
595	SUPR0FpuEnd(VMMR0ThreadCtxHookIsEnabled(pVCpu));
596	}
597	else
598	fSavedGuest = false;
599	Assert(!( pVCpu->cpum.s.fUseFlags
600	& (CPUM_USED_FPU_GUEST \| CPUM_USED_FPU_HOST \| CPUM_USED_MANUAL_XMM_RESTORE)));
601	Assert(!pVCpu->cpum.s.Guest.fUsedFpuGuest);
602	return fSavedGuest;
603	}
604
605
606	/**
607	* Saves the host debug state, setting CPUM_USED_HOST_DEBUG_STATE and loading
608	* DR7 with safe values.
609	*
610	* @returns VBox status code.
611	* @param pVCpu The cross context virtual CPU structure.
612	*/
613	static int cpumR0SaveHostDebugState(PVMCPUCC pVCpu)
614	{
615	/*
616	* Save the host state.
617	*/
618	pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
619	pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
620	pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
621	pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
622	pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
623	/** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
624	pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
625
626	/* Preemption paranoia. */
627	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HOST);
628
629	/*
630	* Make sure DR7 is harmless or else we could trigger breakpoints when
631	* load guest or hypervisor DRx values later.
632	*/
633	if (pVCpu->cpum.s.Host.dr7 != X86_DR7_INIT_VAL)
634	ASMSetDR7(X86_DR7_INIT_VAL);
635
636	return VINF_SUCCESS;
637	}
638
639
640	/**
641	* Saves the guest DRx state residing in host registers and restore the host
642	* register values.
643	*
644	* The guest DRx state is only saved if CPUMR0LoadGuestDebugState was called,
645	* since it's assumed that we're shadowing the guest DRx register values
646	* accurately when using the combined hypervisor debug register values
647	* (CPUMR0LoadHyperDebugState).
648	*
649	* @returns true if either guest or hypervisor debug registers were loaded.
650	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
651	* @param fDr6 Whether to include DR6 or not.
652	* @thread EMT(pVCpu)
653	*/
654	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu, bool fDr6)
655	{
656	Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
657	bool const fDrXLoaded = RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
658
659	/*
660	* Do we need to save the guest DRx registered loaded into host registers?
661	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
662	*/
663	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
664	{
665	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
666	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
667	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
668	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
669	if (fDr6)
670	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
671	}
672	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~(CPUM_USED_DEBUG_REGS_GUEST \| CPUM_USED_DEBUG_REGS_HYPER));
673
674	/*
675	* Restore the host's debug state. DR0-3, DR6 and only then DR7!
676	*/
677	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST)
678	{
679	/* A bit of paranoia first... */
680	uint64_t uCurDR7 = ASMGetDR7();
681	if (uCurDR7 != X86_DR7_INIT_VAL)
682	ASMSetDR7(X86_DR7_INIT_VAL);
683
684	ASMSetDR0(pVCpu->cpum.s.Host.dr0);
685	ASMSetDR1(pVCpu->cpum.s.Host.dr1);
686	ASMSetDR2(pVCpu->cpum.s.Host.dr2);
687	ASMSetDR3(pVCpu->cpum.s.Host.dr3);
688	/** @todo consider only updating if they differ, esp. DR6. Need to figure how
689	* expensive DRx reads are over DRx writes. */
690	ASMSetDR6(pVCpu->cpum.s.Host.dr6);
691	ASMSetDR7(pVCpu->cpum.s.Host.dr7);
692
693	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HOST);
694	}
695
696	return fDrXLoaded;
697	}
698
699
700	/**
701	* Saves the guest DRx state if it resides host registers.
702	*
703	* This does NOT clear any use flags, so the host registers remains loaded with
704	* the guest DRx state upon return. The purpose is only to make sure the values
705	* in the CPU context structure is up to date.
706	*
707	* @returns true if the host registers contains guest values, false if not.
708	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
709	* @param fDr6 Whether to include DR6 or not.
710	* @thread EMT(pVCpu)
711	*/
712	VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPUCC pVCpu, bool fDr6)
713	{
714	/*
715	* Do we need to save the guest DRx registered loaded into host registers?
716	* (DR7 and DR6 (if fDr6 is true) are left to the caller.)
717	*/
718	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
719	{
720	pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
721	pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
722	pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
723	pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
724	if (fDr6)
725	pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
726	return true;
727	}
728	return false;
729	}
730
731
732	/**
733	* Lazily sync in the debug state.
734	*
735	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
736	* @param fDr6 Whether to include DR6 or not.
737	* @thread EMT(pVCpu)
738	*/
739	VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPUCC pVCpu, bool fDr6)
740	{
741	/*
742	* Save the host state and disarm all host BPs.
743	*/
744	cpumR0SaveHostDebugState(pVCpu);
745	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
746
747	/*
748	* Activate the guest state DR0-3.
749	* DR7 and DR6 (if fDr6 is true) are left to the caller.
750	*/
751	ASMSetDR0(pVCpu->cpum.s.Guest.dr[0]);
752	ASMSetDR1(pVCpu->cpum.s.Guest.dr[1]);
753	ASMSetDR2(pVCpu->cpum.s.Guest.dr[2]);
754	ASMSetDR3(pVCpu->cpum.s.Guest.dr[3]);
755	if (fDr6)
756	ASMSetDR6(pVCpu->cpum.s.Guest.dr[6]);
757
758	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
759	}
760
761
762	/**
763	* Lazily sync in the hypervisor debug state
764	*
765	* @returns VBox status code.
766	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
767	* @param fDr6 Whether to include DR6 or not.
768	* @thread EMT(pVCpu)
769	*/
770	VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPUCC pVCpu, bool fDr6)
771	{
772	/*
773	* Save the host state and disarm all host BPs.
774	*/
775	cpumR0SaveHostDebugState(pVCpu);
776	Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
777
778	/*
779	* Make sure the hypervisor values are up to date.
780	*/
781	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */);
782
783	/*
784	* Activate the guest state DR0-3.
785	* DR7 and DR6 (if fDr6 is true) are left to the caller.
786	*/
787	ASMSetDR0(pVCpu->cpum.s.Hyper.dr[0]);
788	ASMSetDR1(pVCpu->cpum.s.Hyper.dr[1]);
789	ASMSetDR2(pVCpu->cpum.s.Hyper.dr[2]);
790	ASMSetDR3(pVCpu->cpum.s.Hyper.dr[3]);
791	if (fDr6)
792	ASMSetDR6(X86_DR6_INIT_VAL);
793
794	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
795	}
796

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source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 95140

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